WO2024143386A1 - ＳｉＣ半導体装置 - Google Patents

ＳｉＣ半導体装置 Download PDF

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Publication number
WO2024143386A1
WO2024143386A1 PCT/JP2023/046707 JP2023046707W WO2024143386A1 WO 2024143386 A1 WO2024143386 A1 WO 2024143386A1 JP 2023046707 W JP2023046707 W JP 2023046707W WO 2024143386 A1 WO2024143386 A1 WO 2024143386A1
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Prior art keywords
region
layer
regions
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thickness
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024567877A priority Critical patent/JPWO2024143386A1/ja
Priority to DE112023004913.0T priority patent/DE112023004913T5/de
Priority to CN202380088761.4A priority patent/CN120457785A/zh
Publication of WO2024143386A1 publication Critical patent/WO2024143386A1/ja
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Definitions

  • the present disclosure provides a semiconductor device that includes a chip having a side surface and a decorative pattern formed on the side surface.
  • the present disclosure provides a SiC semiconductor device including a first SiC layer of a first conductivity type having a first axial channel along a stacking direction, a second SiC layer of a first conductivity type having a second axial channel along the stacking direction and stacked on the first SiC layer, a first region of a second conductivity type extending along the first axial channel in the first SiC layer in a cross-sectional view and extending in a first extension direction in a planar view, and a second region of a second conductivity type extending along the second axial channel in the second SiC layer in a cross-sectional view and extending in a second extension direction intersecting the first extension direction so as to intersect the first region in a planar view.
  • FIG. 1 is a plan view showing a SiC semiconductor device according to the first embodiment.
  • FIG. 2A is a cross-sectional view taken along line IIA-IIA shown in FIG.
  • FIG. 2B is a cross-sectional view taken along line IIB-IIB shown in FIG.
  • FIG. 3A is a plan view showing an example of the layout of a chip (first layer).
  • FIG. 3B is a plan view showing an example of the layout of the chip (second layer).
  • FIG. 4A is a perspective view showing a chip together with a decorative pattern according to the first embodiment.
  • FIG. 4B is a perspective view showing a chip together with a decorative pattern according to the first embodiment.
  • FIG. 5 is a perspective view of a main part showing a decorative pattern.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.
  • the SiC semiconductor device 1A includes an active region 10 set in the chip 2.
  • the active region 10 is set in the inner part of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side faces 5A to 5D) in a plan view.
  • the active region 10 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 10 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the SiC semiconductor device 1A includes a peripheral region 11 that is set outside the active region 10 in the chip 2.
  • the peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a planar view.
  • the peripheral region 11 extends in a band shape along the active region 10 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 10.
  • the lower end of the first difference mark Md1 may be formed at a distance from the upper ends of the first marks Mk1 toward the upper end of the second layer 9, and may face the first marks Mk1 across a portion (lower end) of the second layer 9.
  • the lower ends of the first difference marks Md1 may be connected to the upper ends of the first marks Mk1 (first spaces Sp1).
  • the lower end of the first difference mark Md1 may have an extension that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.
  • the lower end (extension) of the first difference mark Md1 may be connected to multiple first marks Mk1 within the first layer 8.
  • the lower end (extension) of the first difference mark Md1 may be formed at a distance from the multiple first marks Mk1 toward the upper end of the second layer 9.
  • the upper end of the first difference mark Md1 may be formed at a distance from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the second layer 9 across a portion (upper end) of the second layer 9.
  • the upper end of the first difference mark Md1 may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).
  • the second difference mark Md2 is formed in a lower range relative to the upper range, and overlaps at least one second mark Mk2 in the thickness direction.
  • the second difference mark Md2 extends in a band shape in the lower range in the second direction Y, and overlaps multiple second marks Mk2 in the thickness direction.
  • the second difference mark Md2 extends from a corner on one side of the second side 5B to a corner on the other side of the second side 5B in the second direction Y, and is exposed from the corner on one side and the corner on the other side of the second side 5B. In other words, the second difference mark Md2 overlaps all of the second marks Mk2 in the thickness direction.
  • the second difference mark Md2 has a portion exposed from a corner of the first side surface 5A and a corner of the third side surface 5C.
  • the second difference mark Md2 is formed at a corner of the first side surface 5A (third side surface 5C) at a distance in the first direction X from the outermost first mark Mk1, and faces the outermost first mark Mk1 in the first direction X.
  • the second difference mark Md2 is formed in a portion of the second side surface 5B made of the first layer 8, and defines a plurality of second spaces Sp2 together with the plurality of second marks Mk2.
  • the upper end of the second difference mark Md2 may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face multiple second marks Mk2 across a portion (upper end) of the first layer 8.
  • the upper end of the second difference mark Md2 may be exposed from the upper end of the first layer 8 (i.e., the first main surface 3).
  • the upper end of the second difference mark Md2 may be connected to the lower ends of the second marks Mk2.
  • the upper end of the second difference mark Md2 may be formed at a distance from the lower ends of the second marks Mk2 toward the lower end of the first layer 8, and may face the second marks Mk2 across a part (lower end) of the first layer 8.
  • the SiC semiconductor device 1A may include a decorative pattern PT according to a fourth embodiment formed on at least one of the first to fourth side surfaces 5A to 5D.
  • the decorative pattern PT according to the fourth embodiment includes the first difference mark Md1 according to the second embodiment and the second difference mark Md2 according to the third embodiment in addition to the configuration according to the first embodiment.
  • the second difference mark Md2 extends in a thickness range different from the thickness range of the first difference mark Md1 and in an extension direction different from the extension direction of the first difference mark Md1.
  • the SiC semiconductor device 1A may include a decorative pattern PT according to a fifth embodiment formed on at least one of the first to fourth side surfaces 5A to 5D.
  • the decorative pattern PT according to the fifth embodiment has a configuration in which the positional relationship between the multiple first marks Mk1 and the multiple second marks Mk2 is swapped.
  • the multiple first marks Mk1 are arranged at intervals in the second direction Y in the lower range of the second side surface 5B, and define multiple n-type first spaces Sp1 each consisting of a part of the laminated portion 7.
  • the multiple first marks Mk1 are each formed in a portion of the second side surface 5B consisting of the first layer 8, and the multiple first spaces Sp1 each consist of a part of the first layer 8.
  • the configuration of the first mark Mk1 (first space Sp1) in the fifth embodiment is similar to the configuration of the first mark Mk1 (first space Sp1) in the first embodiment, except that it is formed on the second side surface 5B.
  • the multiple second marks Mk2 are arranged at intervals in the first direction X in the upper range of the first side surface 5A, and define multiple n-type second spaces Sp2 each consisting of a part of the laminated portion 7.
  • the multiple second marks Mk2 are each formed in a portion of the first side surface 5A consisting of the second layer 9, and the multiple second spaces Sp2 each consist of a part of the second layer 9.
  • the configuration of the second mark Mk2 (second spaces Sp2) in the fifth embodiment is similar to the configuration of the second mark Mk2 (second spaces Sp2) in the first embodiment, except that it is formed on the first side surface 5A.
  • the configuration of the decorative pattern PT according to the second to fourth embodiments can also be applied to the decorative pattern PT according to the fifth embodiment.
  • the first difference mark Md1 is formed in the upper area of the second side surface 5B.
  • the second difference mark Md2 is formed in the lower area of the first side surface 5.
  • the SiC semiconductor device 1A includes a p-type column region 12 formed in the stacked portion 7 at least in the active region 10.
  • the column region 12 may also be referred to as a "column layer,” a “pillar layer (region),” a “p-type layer (region),” a “p-type zone,” or the like.
  • the column region 12 is formed in a three-dimensional lattice shape within the stacked portion 7, and defines a three-dimensional lattice-shaped n-type drift region 13 made up of a part of the stacked portion 7.
  • the column region 12 is formed in at least one of the multiple semiconductor layers that make up the stacked portion 7, and forms a superjunction structure SJ with the drift region 13 within the stacked portion 7.
  • the column region 12 has a stacked structure that includes multiple p-type first regions 14 and multiple p-type second regions 15.
  • the first regions 14 are formed in the first layer 8 at intervals in the horizontal direction, and define a plurality of n-type first drift regions 16, each of which is made up of a part of the first layer 8.
  • the first regions 14, together with the first drift regions 16, form a plurality of first pn junctions having charge balance.
  • a state of charge balance means a state in which, for multiple adjacent first regions 14, the depletion layer extending from one first pn junction and the depletion layer extending from the other first pn junction are connected within the multiple first drift regions 16.
  • the multiple first regions 14 are arranged at intervals in the first array direction Da1 in the first layer 8, and are each formed in a strip shape extending in the first extension direction De1.
  • the first extension direction De1 is a direction that intersects or is perpendicular to the first array direction Da1.
  • the multiple first regions 14 are formed in a stripe shape extending in the first extension direction De1
  • the multiple first drift regions 16 are formed in a stripe shape extending in the first extension direction De1.
  • the multiple first regions 14 are extended from the active region 10 to the peripheral region 11 (see FIG. 3A). That is, the multiple first regions 14 are extended from a portion of the first layer 8 located within the active region 10 to a portion of the first layer 8 located within the peripheral region 11.
  • the multiple first regions 14 are also arranged at intervals in the first array direction Da1 in the peripheral region 11, and are each formed in a band shape extending in the first extension direction De1.
  • the multiple first regions 14 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each has a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).
  • the multiple first marks Mk1 are each formed using a portion (exposed portion) of the multiple first regions 14.
  • the layout (exposed locations and arrangement direction) of the multiple first marks Mk1 on the first side 5A (third side 5C) is appropriately adjusted depending on the layout (first arrangement direction Da1 and first extension direction De1) of the multiple first regions 14.
  • the multiple first marks Mk1 do not necessarily need to be formed continuously from the main body portions of the multiple first regions 14, but may be formed as separate portions separated from the main body portions of the multiple first regions 14. In this case, it is preferable that the multiple first marks Mk1 are separated from the main body portions of the multiple first regions 14 in the outer circumferential region 11.
  • the explanation for the first region 14 also applies to the first mark Mk1 (the portion of the first region 14 exposed from the first side surface 5A/third side surface 5C).
  • the first regions 14 are made up of channeling regions (first channeling regions) that extend along the first axis channel CH1 in the first layer 8 in a cross-sectional view.
  • the first regions 14 are impurity regions that are introduced parallel or nearly parallel to the region (first axis channel CH1) surrounded by atomic rows along the low-index crystal axis in the first layer 8, and extend at an angle with respect to the first main surface 3.
  • the multiple first regions 14 have an off direction Doff and an off angle ⁇ off that are approximately the same as the off direction Doff and the off angle ⁇ off of the first axis channel CH1. In other words, the multiple first regions 14 are inclined by the off angle ⁇ off from the vertical axis toward the off direction Doff.
  • the first regions 14 each have a first lower end 14a at the lower end of the first layer 8 and a first upper end 14b at the upper end of the first layer 8.
  • the first lower end 14a is located in a region on the lower end side of the first layer 8 relative to the intermediate part of the thickness range of the first layer 8
  • the first upper end 14b is located in a region on the upper end side of the first layer 8 relative to the intermediate part of the thickness range of the first layer 8.
  • the first regions 14 each consist of a single impurity region having a thickness (depth) that crosses the intermediate part of the first layer 8 along the first axial channel CH1.
  • the first lower end 14a may be formed with a gap from the lower end to the upper end of the first layer 8, and may face the base layer 6 across a part (lower end) of the first layer 8.
  • the first lower end 14a may be approximately coincident with the lower end of the first layer 8 and connected to the base layer 6.
  • the first lower end 14a may have an extension that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.
  • the thickness of the extension of the first lower end 14a based on the upper end of the base layer 6 may be greater than 0 ⁇ m and less than 2 ⁇ m.
  • the thickness of the extension of the first lower end 14a may have a value that belongs to any one of the following ranges: greater than 0 ⁇ m and less than 0.5 ⁇ m, 0.5 ⁇ m or more and less than 1 ⁇ m, 1 ⁇ m or more and less than 1.5 ⁇ m, and 1.5 ⁇ m or more and less than 2 ⁇ m.
  • the first upper end 14b may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a portion (upper end) of the first layer 8.
  • the first upper end 14b may be substantially coincident with the upper end of the first layer 8 and connected to the second layer 9.
  • the distance between the upper end of the first layer 8 and the first upper end 14b may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper end of the first layer 8 and the first upper end 14b may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the plurality of first regions 14 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the first region 14 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the first region 14 is adjusted by a trivalent element belonging to the heavy elements heavier than carbon. In other words, the first region 14 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the first region 14 is adjusted by aluminum.
  • the first regions 14 each have a first width W1.
  • the first width W1 is the width along the first arrangement direction Da1 of the first regions 14. It is preferable that the first width W1 is less than the first thickness T1 of the first layer 8. Of course, the first width W1 may be equal to or greater than the first thickness T1. It is preferable that the first width W1 is less than the second thickness T2 of the second layer 9. Of course, the first width W1 may be equal to or greater than the second thickness T2.
  • the first width W1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 may have a value belonging to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the multiple first regions 14 each have a first region thickness TR1 (first region depth).
  • the first region thickness TR1 may be less than the first thickness T1 of the first layer 8.
  • the first region thickness TR1 may be greater than the first thickness T1.
  • the first region thickness TR1 may be approximately equal to the first thickness T1.
  • the first region thickness TR1 may be less than the second thickness T2 of the second layer 9.
  • the first region thickness TR1 may be greater than the second thickness T2.
  • the first region thickness TR1 may be approximately equal to the second thickness T2.
  • the first region thickness TR1 is preferably 1 ⁇ m or more.
  • the first region thickness TR1 is preferably 5 ⁇ m or less.
  • the first region thickness TR1 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 is less than the first thickness T1 of the first layer 8, and that the first region thickness TR1 is greater than the first width W1.
  • each of the multiple first regions 14 has a first aspect ratio TR1/W1 that extends in a vertically elongated columnar shape along the first axial channel CH1.
  • the first aspect ratio TR1/W1 is the ratio of the first region thickness TR1 to the first width W1.
  • the first region thickness TR1 is greater than the first thickness T1.
  • the first aspect ratio TR1/W1 may be greater than 1 and less than or equal to 100.
  • the first regions 14 are formed at intervals of a first pitch P1 in the first arrangement direction Da1. It is preferable that the first pitch P1 is less than the first thickness T1 of the first layer 8. Of course, the first pitch P1 may be equal to or greater than the first thickness T1. It is preferable that the first pitch P1 is less than the second thickness T2 of the second layer 9. Of course, the first pitch P1 may be equal to or greater than the second thickness T2.
  • the first pitch P1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch P1 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch P1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second regions 15 are formed in the second layer 9 at intervals in the horizontal direction, and define a plurality of n-type second drift regions 17, each of which is made up of a part of the second layer 9.
  • the second array direction Da2 is a direction that intersects with the first array direction Da1
  • the second extension direction De2 is a direction that intersects with the first extension direction De1.
  • the second extension direction De2 is a direction that intersects or is perpendicular to the second array direction Da2.
  • the multiple second regions 15 are formed in stripes extending in the second extension direction De2
  • the multiple second drift regions 17 are formed in stripes extending in the second extension direction De2.
  • the multiple second regions 15 are extended from the active region 10 to the peripheral region 11 (see FIG. 3B). That is, the multiple second regions 15 are extended from a portion of the second layer 9 located within the active region 10 to a portion of the second layer 9 located within the peripheral region 11.
  • the multiple second regions 15 are also arranged at intervals in the second array direction Da2 in the peripheral region 11, and are each formed in a strip shape extending in the second extension direction De2. That is, the multiple second regions 15 intersect with the multiple first regions 14 in the peripheral region 11 as well.
  • the multiple second regions 15 extend from the outer peripheral region 11 toward either or both of the second side surface 5B and the fourth side surface 5D (both in this embodiment), and each has a portion exposed from either or both of the second side surface 5B and the fourth side surface 5D (both in this embodiment).
  • the portions of the multiple second regions 15 exposed from the second side surface 5B form multiple second marks Mk2 on the second side surface 5B
  • the portions of the multiple second regions 15 exposed from the fourth side surface 5D form multiple second marks Mk2 on the fourth side surface 5D.
  • the multiple second regions 15 include either or both of the multiple second marks Mk2 as exposed portions exposed from the second side surface 5B and the multiple second marks Mk2 as exposed portions exposed from the fourth side surface 5D.
  • the multiple second marks Mk2 are each formed using a portion (exposed portion) of the multiple second regions 15.
  • the layout (exposed locations and arrangement direction) of the multiple second marks Mk2 on the second side 5B (fourth side 5D) is appropriately adjusted depending on the layout (second arrangement direction Da2 and second extension direction De2) of the multiple second regions 15.
  • the second marks Mk2 do not necessarily need to be formed continuously from the main body portions of the second regions 15, but may be formed as separate portions separated from the main body portions of the second regions 15. In this case, it is preferable that the second marks Mk2 are separated from the main body portions of the second regions 15 in the outer circumferential region 11.
  • the explanation for the second region 15 also applies to the second marks Mk2 (portions of the second region 15 exposed from the second side surface 5B/fourth side surface 5D).
  • the second width W2 is preferably less than the first thickness T1 of the first layer 8. Of course, the second width W2 may be greater than or equal to the first thickness T1. The second width W2 is preferably approximately equal to the first width W1 of the first region 14. Of course, the second width W2 may be greater than or equal to the first width W1, or may be less than the first width W1.
  • the second regions 15 each have a second region thickness TR2 (region depth).
  • the second region thickness TR2 may be less than the second thickness T2 of the second layer 9.
  • the second region thickness TR2 may be greater than the second thickness T2.
  • the second region thickness TR2 may be approximately equal to the second thickness T2.
  • the second region thickness TR2 is preferably 1 ⁇ m or more.
  • the second region thickness TR2 is preferably 5 ⁇ m or less.
  • the second region thickness TR2 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the second pitch P2 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the second pitch P2 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the second pitch P2 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • a superjunction structure SJ having a two-layer structure is shown.
  • a superjunction structure SJ having a stacked structure of three or more layers may also be adopted.
  • a stack section 7 having a stacked structure of three or more layers may be formed, and a column region 12 having a stacked structure of three or more layers may be formed.
  • the second region 15 (190 KeV) has a second region thickness TR2 of 1.5 ⁇ m or more and 1.8 ⁇ m or less, and has a second lower end 15a spaced from the lower end of the second layer 9 toward the upper end, and a second upper end 15b exposed from the upper end (first main surface 3) of the second layer 9.
  • the distance between the lower end of the second layer 9 and the second lower end 15a is 1.2 ⁇ m or more and 1.5 ⁇ m or less.
  • the second region 15 (380 KeV) has a second region thickness TR2 of 2.2 ⁇ m or more and 2.4 ⁇ m or less, and has a second lower end 15a spaced from the lower end to the upper end of the second layer 9, and a second upper end 15b spaced from the upper end (first main surface 3) of the second layer 9 to the lower end side (first layer 8 side).
  • the distance between the lower end of the second layer 9 and the second lower end 15a is 0.5 ⁇ m or more and 0.8 ⁇ m or less.
  • the distance between the upper end of the second layer 9 and the second upper end 15b of the second region 15 is 0.01 ⁇ m or more and 0.2 ⁇ m or less.
  • the gradual portion 22 has a thickness of 1.5 ⁇ m or more and 1.8 ⁇ m or less, and has a concentration decrease rate of 50% or less in this thickness range.
  • the gradual portion 22 crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. That is, the extension of the second region 15 includes a part of the gradual portion 22.
  • the p-type impurity concentration of the gradual portion 22 is within a concentration range of 2 ⁇ 10 16 cm ⁇ 3 or more and 4 ⁇ 10 16 cm ⁇ 3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual portion 22 to 1 ⁇ 10 15 cm ⁇ 3 .
  • the first upper end 14b of the first region 14 is formed at a distance from the upper end (second layer 9) of the first layer 8 toward the lower end, and faces the second layer 9 across a part (upper end) of the first layer 8.
  • the first gradually increasing portion 20A, the first peak portion 21A, the first gradual portion 22A, and the first gradually decreasing portion 23A of the first region 14 are located within the first layer 8.
  • the second region 15 has a second region thickness TR2 that is less than the second thickness T2 of the second layer 9, and is formed within the second layer 9 at a distance from both the lower end and the upper end of the second layer 9. Specifically, the second lower end 15a of the second region 15 is formed at a distance from the lower end (first layer 8) of the second layer 9 toward the upper end, and faces the first layer 8 with a part of the second layer 9 (lower end) in between.
  • the second gradually increasing portion 20B, the second peak portion 21B, the second gradually decreasing portion 22B and the second gradually decreasing portion 23B of the second region 15 are located in the second layer 9. At least a portion of the second gradually decreasing portion 23B is located in the first layer 8. That is, the extension of the second lower end portion 15a includes the second gradually decreasing portion 23B. Of course, a portion of the second gradually decreasing portion 22B may be located in the first layer 8 (see FIG. 13E). That is, the extension of the second lower end portion 15a may include a portion of the second gradually decreasing portion 22B and the second gradually decreasing portion 23B.
  • the second layer 9 has a first thickness T1 of 3 ⁇ m
  • the second region 15 is formed in the second layer 9 by an implantation energy of 960 KeV.
  • the second region 15 may be formed by an implantation energy of 960 KeV or more.
  • the second thickness T2 may be greater than 3 ⁇ m and less than or equal to 5 ⁇ m.
  • the second region 15 connected to the first region 14 is formed in the first layer 8 by an implantation energy of 960 KeV or more (see also FIGS. 13F to 13E).
  • the second region 15 in the second embodiment is formed in the second layer 9 having a second thickness T2 that is approximately equal to the first thickness T1 of the first layer 8.
  • the second region 15 in the third embodiment is formed in the second layer 9 having a second thickness T2 that is less than the first thickness T1 of the first layer 8.
  • the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 of the second layer 9.
  • the second thickness T2 may be 1 ⁇ m or more and 2 ⁇ m or less.
  • a second region 15 that is connected to the first region 14 is formed in the first layer 8 by an implantation energy of 190 KeV or more (see also Figures 13A to 13E).
  • the second thickness T2 may be 2 ⁇ m or more and less than 3 ⁇ m.
  • a second region 15 that is connected to the first region 14 is formed in the first layer 8 by an implantation energy of 380 KeV or more (see also Figures 13B to 13E).
  • the first region thickness TR1 (implantation energy) of the first region 14 and the second region thickness TR2 (implantation energy) of the second region 15 can be set to be the same, while a second region 15 connected to the first region 14 can be formed within the first layer 8.
  • the second thickness T2 of the second layer 9 can be set to be less than the first thickness T1 of the first layer 8, and a second region 15 having a second region thickness TR2 greater than the second thickness T2 can be formed.
  • the first region 14 is formed in the first layer 8 with a gap between the upper end and the lower end of the first layer 8, and has a portion that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.
  • the first lower end 14a of the first region 14 has an extension that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.
  • the extension of the first lower end 14a is formed along the base axial channel CHB within the base layer 6. It is preferable that the extension of the first lower end 14a is located on the upper end side of the base layer 6 relative to the intermediate part of the thickness range of the base layer 6. The extension of the first lower end 14a is connected to the base layer 6 within the base layer 6.
  • the first region 14 has a first region thickness TR1 that is greater than the first thickness T1 of the first layer 8.
  • the first region thickness TR1 is also greater than the second thickness T2 of the second layer 9.
  • the first region thickness TR1 is also greater than the second region thickness TR2 of the second region 15.
  • the first region thickness TR1 may be less than the first thickness T1.
  • the first region thickness TR1 may be less than the second thickness T2.
  • the first region thickness TR1 may be less than the second region thickness TR2.
  • the first increasing portion 20A, the first peak portion 21A, the first gradual portion 22A and the first decreasing portion 23A of the first region 14 are located in the first layer 8. At least a portion of the first decreasing portion 23A is located in the base layer 6. That is, the extension of the first lower end 14a includes the first decreasing portion 23A. Of course, a portion of the first gradual portion 22A may be located in the base layer 6 (see FIG. 13E). That is, the extension of the first lower end 14a may include a portion of the first gradual portion 22A and the first decreasing portion 23A.
  • FIG. 23 is a cross-sectional perspective view showing the column region 12 according to the fifth embodiment.
  • FIG. 24 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 23.
  • the column region 12 according to the fifth embodiment has a shape obtained by modifying the first region 14 according to the fourth embodiment.
  • the second region 15 according to the fifth embodiment has a shape similar to that of the second region 15 according to the second embodiment.
  • the second region 15 according to the fifth embodiment may have a shape similar to that of the second region 15 according to the third embodiment.
  • the first layer 8 has a first thickness T1 of 3 ⁇ m, and the first region 14 is formed in the first layer 8 by an implantation energy of 960 KeV or more.
  • the first layer 8 has a first thickness T1 of less than 3 ⁇ m, and the first region 14 is formed in the first layer 8 by an implantation energy of 650 KeV or more.
  • the first region 14 has a first region thickness TR1 that is greater than the first thickness T1 in this example.
  • the first thickness T1 is less than the second thickness T2 of the second layer 9 in this example.
  • the first thickness T1 may be 1 ⁇ m or more and 2 ⁇ m or less.
  • the first region 14 is formed partially located within the base layer 6 by implantation energy of 190 KeV or more (see also Figures 13A to 13E).
  • the first thickness T1 may be 2 ⁇ m or more and less than 3 ⁇ m.
  • the first region 14 is formed partially located within the base layer 6 by implantation energy of 380 KeV or more (see also Figures 13B to 13E).
  • FIG. 25 is a cross-sectional perspective view showing a column region 12 according to a sixth embodiment.
  • FIG. 26 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 25.
  • the column region 12 includes a p-type intermediate region 25 interposed between the first region 14 and the second region 15, in addition to the first region 14 and the second region 15.
  • the first region 14 may have a shape similar to any one of the shapes of the first region 14 according to the first to fifth embodiment examples.
  • the first region 14 has a shape similar to the shape of the first region 14 according to the fourth embodiment example.
  • the second region 15 may have a shape similar to any one of the shapes of the second region 15 according to the first to fifth embodiment examples.
  • the second region 15 has a shape similar to the shape of the second region 15 according to the fourth embodiment example (second embodiment example).
  • the intermediate regions 25 are formed in the surface layer portion on the upper end side of the first layer 8 so as to be positioned at least at multiple intersections between the multiple first regions 14 and the multiple second regions 15, and overlap the corresponding first regions 14 and second regions 15 in the stacking direction.
  • the intermediate regions 25 are arranged at intervals in the first arrangement direction Da1 so as to overlap the multiple first regions 14 in a one-to-one correspondence in the stacking direction, and are each formed in a band shape extending in the first extension direction De1.
  • the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y).
  • the arrangement direction and extension direction of the multiple intermediate regions 25 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction.
  • the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction
  • the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the intermediate regions 25, together with the first regions 14, are drawn out from the active region 10 to the peripheral region 11.
  • the intermediate regions 25 are drawn out from a portion of the first layer 8 located within the active region 10 to a portion of the first layer 8 located within the peripheral region 11.
  • the intermediate regions 25 are also arranged at intervals in the first array direction Da1 in the peripheral region 11, and are each formed in a band shape extending in the first extension direction De1.
  • the multiple intermediate regions 25 extend from the peripheral region 11 toward either or both of the first side 5A and the third side 5C (both in this embodiment), and each has a portion exposed from either or both of the first side 5A and the third side 5C (both in this embodiment).
  • the portions of the multiple intermediate regions 25 exposed from the first side surface 5A form a portion (upper end portion) of the multiple first marks Mk1 on the first side surface 5A
  • the portions of the multiple intermediate regions 25 exposed from the third side surface 5C form a portion (upper end portion) of the multiple first marks Mk1 on the third side surface 5C.
  • the multiple intermediate regions 25 include either or both of the portions (upper end portions) of the multiple first marks Mk1 as exposed portions exposed from the first side surface 5A and the portions (upper end portions) of the multiple first marks Mk1 as exposed portions exposed from the third side surface 5C.
  • the multiple first marks Mk1 are each formed using the multiple first regions 14 and the multiple intermediate regions 25.
  • the layout (exposed locations and arrangement direction) of the multiple first marks Mk1 on the first side 5A (third side 5C) is also appropriately adjusted depending on the layout (first arrangement direction Da1 and first extension direction De1) of the multiple first regions 14 and the multiple intermediate regions 25.
  • the multiple first marks Mk1 do not necessarily need to be formed continuously from the main body portions of the multiple intermediate regions 25, but may be formed as separate portions separated from the main body portions of the multiple intermediate regions 25. In this case, it is preferable that the multiple first marks Mk1 are separated from the main body portions of the multiple intermediate regions 25 in the outer circumferential region 11.
  • the multiple intermediate regions 25 do not necessarily have to form part (upper end) of the multiple first marks Mk1.
  • the multiple intermediate regions 25 may be formed in the inner part of the first layer 8 at a distance from the first to fourth side faces 5A to 5D in a plan view.
  • the explanation for the intermediate regions 25 also applies to the first mark Mk1 (the portions of the intermediate regions 25 exposed from the first side face 5A/third side face 5C).
  • the intermediate regions 25 are formed in the first layer 8 in a region between the upper end of the first layer 8 and the first upper end 14b of the first region 14.
  • the intermediate regions 25 are preferably located on the upper end side of the first layer 8 relative to the middle part of the thickness range of the first layer 8.
  • the intermediate regions 25 may be exposed from the upper end of the first layer 8, or may be formed at intervals from the upper end to the lower end side of the first layer 8.
  • Each intermediate region 25 may be formed in a horizontally elongated columnar shape extending in the horizontal direction in a cross-sectional view. Of course, each intermediate region 25 may be formed in a vertically elongated columnar shape extending in the vertical direction Z.
  • the intermediate regions 25 form intermediate pn junctions having charge balance together with the first layer 8.
  • the intermediate regions 25 form part of the first superjunction structure SJ1 together with the first drift regions 16.
  • the state of having charge balance means that, for adjacent intermediate regions 25, the depletion layer extending from one intermediate pn junction and the depletion layer extending from the other intermediate pn junction are connected within the first drift regions 16.
  • each intermediate region 25 may include a single or multiple area elements 25a.
  • FIG. 26 shows an example in which each intermediate region 25 includes multiple (two) area elements 25a.
  • the single area element 25a is formed in the area between the upper end of the first layer 8 and the first upper end 14b of the first region 14, and is connected to the first upper end 14b of the first region 14.
  • the region element 25a is composed of a random impurity region introduced into the surface layer of the first layer 8 by a random injection method into the first layer 8 (see also FIG. 14). In other words, the region element 25a is not formed in the second layer 9. Furthermore, the region element 25a has a thickness in the direction along the first axial channel CH1 that is less than the first region thickness TR1 of the first region 14. Furthermore, the thickness of the region element 25a is less than the second region thickness TR2 of the second region 15.
  • the region element 25a does not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 in a range of 0.5 ⁇ m.
  • each intermediate region 25 has multiple peak portions 21 (peak value P) according to the number of multiple region elements 25a in the thickness direction of the first layer 8.
  • the p-type impurity concentration of the intermediate region 25 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the intermediate region 25 may be the same as the trivalent element of the first region 14, etc., or may be a different species from the trivalent element of the first region 14, etc.
  • the trivalent element of the intermediate region 25 may be at least one of boron, aluminum, gallium, and indium.
  • the intermediate regions 25 each have an intermediate width WM.
  • the intermediate width WM is a width along the first arrangement direction Da1. It is preferable that the intermediate width WM is less than the first thickness T1 of the first layer 8. Of course, the intermediate width WM may be equal to or greater than the first thickness T1. It is preferable that the intermediate width WM is less than the second thickness T2 of the second layer 9. Of course, the intermediate width WM may be equal to or greater than the second thickness T2.
  • the n-type impurity concentration of the buffer layer 26 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the buffer layer 26 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the buffer layer 26 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the buffer layer 26 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the first layer 8 is stacked on the buffer layer 26, and the second layer 9 is stacked on the first layer 8.
  • the first layer 8 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the buffer layer 26, and has n-type conductivity. Therefore, the first layer 8 has an off-direction Doff and an off-angle ⁇ off that are approximately equal to the off-direction Doff and off-angle ⁇ off of the buffer layer 26.
  • the first axis channel CH1 approximately coincides with the buffer axis channel CHBu.
  • Figure 33 is a cross-sectional perspective view showing a column region 12 according to an eleventh embodiment.
  • a superjunction structure SJ having a stacked structure of three or more layers may be adopted.
  • Figure 33 shows a stacked portion 7 having a three-layer structure and a column region 12 having a three-layer structure.
  • the third axis channel CH3 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the third axis channel CH3 extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the third axis channel CH3 is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the n-type impurity concentration of the third layer 27 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the third layer 27 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the third layer 27 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the third layer 27 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the multiple third regions 28 and the third layer 27 form a third superjunction structure SJ3.
  • the state of charge balance means that, for multiple adjacent third regions 28, the depletion layer extending from one third pn junction and the depletion layer extending from the other third pn junction are connected within the multiple third drift regions 29.
  • the multiple third regions 28 are drawn from the active region 10 to the peripheral region 11. That is, the multiple third regions 28 are drawn from a portion of the third layer 27 located within the active region 10 to a portion of the third layer 27 located within the peripheral region 11.
  • the multiple third regions 28 are also arranged at intervals in the third array direction Da3 in the peripheral region 11, and are each formed in a band shape extending in the third extension direction De3.
  • the multiple third regions 28 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each has a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).
  • the portions of the multiple third regions 28 exposed from the first side surface 5A form multiple third marks (not shown) on the first side surface 5A, and the portions of the multiple third regions 28 exposed from the third side surface 5C form multiple third marks on the third side surface 5C.
  • the multiple third regions 28 include either or both of multiple third marks as exposed portions exposed from the first side surface 5A and multiple third marks as exposed portions exposed from the third side surface 5C.
  • the third width W3 is less than the third thickness T3 of the third layer 27, and that the third region thickness TR3 is greater than the third width W3.
  • each of the multiple third regions 28 has a third aspect ratio TR3/W3 that extends in a vertically elongated columnar shape along the third axial channel CH3.
  • the third aspect ratio TR3/W3 is the ratio of the third region thickness TR3 to the third width W3.
  • the third region thickness TR3 is greater than the third thickness T3.
  • the third aspect ratio TR3/W3 may be greater than 1 and less than or equal to 100.
  • the top layer 30 is grown continuously from the second layer 9, so that the bottom end of the top layer 30 coincides with the top end of the second layer 9.
  • the boundary between the top layer 30 and the second layer 9 is not necessarily visible, and can be indirectly evaluated and/or determined from other configurations or elements.
  • the top layer 30 has an off-direction Doff and an off-angle ⁇ off that are approximately the same as the off-direction Doff and the off-angle ⁇ off of the second layer 9.
  • the second array direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X).
  • the array direction and extension direction of the multiple body regions 32 are changed according to the second array direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second array direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction.
  • the second array direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple gate structures 35 are arranged at intervals in the second array direction Da2 and are each formed in a strip shape extending in the second extension direction De2.
  • the second array direction Da2 is the m-axis direction (second direction Y)
  • the second extension direction De2 is the a-axis direction (first direction X).
  • the gate pad 45 is arranged in a region along the center of the first side surface 5A on the periphery of the active region 10.
  • the gate pad 45 may be arranged in a region along any of the centers of the first to fourth side surfaces 5A to 5D.
  • the gate pad 45 may be arranged at any corner of the active region 10 in a planar view.
  • the gate pad 45 may be arranged in the center of the active region 10 in a planar view.
  • the gate pad 45 is formed in a rectangular shape in a planar view.
  • the first gate wiring 46A is pulled out from the gate pad 45 toward the second side surface 5B and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) a portion (specifically, one end) of the multiple gate structures 35.
  • the first gate wiring 46A penetrates the interlayer insulating film 40 via multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35.
  • the SiC semiconductor device 1A includes a source pad 47 disposed on the interlayer insulating film 40 at a distance from the gate pad 45 and the gate wiring 46.
  • the source pad 47 is an electrode to which a source potential is applied from the outside.
  • the source pad 47 may be referred to as a "source pad electrode", a "second pad electrode”, etc.
  • the source pad 47 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.
  • the multiple gate structures 35 may face the multiple first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may face the multiple first regions 14 in the stacking direction. The multiple gate structures 35 may face the multiple first drift regions 16 in a one-to-one correspondence in the stacking direction.
  • the arrangement direction and extension direction of the multiple gate structures 35 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14 (body regions 32). Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple gate structures 35 are each arranged to straddle two adjacent body regions 32, and each cover the multiple source regions 33 located in one and the other body region 32. In addition, the multiple gate structures 35 each face the multiple second regions 15 (second regions 15) and the multiple second drift regions 17 in the stacking direction.
  • Figure 40 is a schematic diagram showing a wafer 50 used in the manufacture of the SiC semiconductor device 1A.
  • the wafer 50 is a substrate for the base layer 6 and contains a SiC single crystal.
  • the wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.
  • the wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal.
  • the mark 54 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 51 in a plan view.
  • the mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • Figure 40 shows an orientation flat extending in the a-axis direction in a plan view.
  • a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like.
  • Each device region 55 corresponds to the SiC semiconductor device 1A.
  • Each of the plurality of device regions 55 is set to have a rectangular shape in a plan view.
  • the multiple device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 55 are each set at intervals inward from the periphery of the first wafer main surface 51 in a plan view.
  • the multiple cutting lines 56 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 55.
  • FIG. 41 is a flow chart showing an example of a method for manufacturing a SiC semiconductor device 1A.
  • FIG. 42A to FIG. 42H are cross-sectional perspective views showing an example of a method for manufacturing a SiC semiconductor device 1A.
  • FIG. 43A to FIG. 43B are schematic diagrams for explaining the crystal orientation measurement process.
  • FIG. 44A to FIG. 44B are schematic diagrams for explaining the ion implantation process.
  • FIG. 42A to FIG. 42H show cross-sectional perspective views of a portion of an active region 10 of one device region 55.
  • step S1 in FIG. 41 the aforementioned wafer 50 preparation process is performed (step S1 in FIG. 41).
  • a determination process is performed as to whether or not an n-type buffer layer 26 (see FIG. 31 and FIG. 32) formation process is performed (step S2 in FIG. 41). If a buffer layer 26 is to be formed (step S2 in FIG. 41: YES), the buffer layer 26 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth (step S3 in FIG. 41). If a buffer layer 26 formation process is not performed (step S2 in FIG. 41: NO), this process is omitted.
  • a step of forming an n-type first layer 8 is performed (step S4 in FIG. 41). If the step of forming the buffer layer 26 is omitted, the first layer 8 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth. If the buffer layer 26 is formed, the first layer 8 is formed starting from the buffer layer 26 by epitaxial growth. In this case, the first layer 8 may be formed by continuous crystal growth from the buffer layer 26 using the step of forming the buffer layer 26 after the step of forming the buffer layer 26.
  • the crystal orientation of the first layer 8 includes a process for measuring the off angle ⁇ off of the first layer 8. In other words, this process includes a process for measuring the crystal orientation of the first axis channel CH1 of the first layer 8.
  • the wafer 50 is cut from an ingot (SiC ingot), which is a crystalline mass, but there is a risk that an error will occur in the off-angle ⁇ off due to process error. If an error occurs in the off-angle ⁇ off of the wafer 50, a process error will also occur in the off-angle ⁇ off of the first layer 8, which will become an obstacle during the channeling implantation process. Therefore, it is preferable that data (information) on the off-angle ⁇ off is obtained prior to the channeling implantation process, and the channeling implantation process is carried out based on the data (information) on the off-angle ⁇ off.
  • the crystal orientation of the first layer 8 is measured by an X-ray diffraction method (the so-called ⁇ -2 ⁇ measurement method) using an X-ray diffraction device 57.
  • the X-ray diffraction device 57 may also be referred to as an "XRD (X-ray Diffraction) device.”
  • the X-ray diffraction device 57 includes an irradiation unit 58 and a detection unit 59, and performs the rocking curve measurement method.
  • the irradiation unit 58 irradiates the incident X-ray L1 having a predetermined incident angle ⁇ with respect to the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).
  • the incident angle ⁇ is defined as the angle between the incident X-ray L1 and the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).
  • the rocking curve measurement method is performed only at one location (e.g., the center) of the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50). If in-plane variation in the off angle ⁇ off is expected, the rocking curve measurement method may be performed at multiple locations (e.g., the center and peripheral areas) of the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50).
  • FIG. 43B shows the measurement points when the rocking curve measurement method is performed on multiple points (here, five points) on the upper end of the first layer 8.
  • the off angle ⁇ off of the first layer 8 is set to about 4° here.
  • the first to fifth measurement points Po1 to Po5 are shown.
  • the first measurement point Po1 is set in the center of the first layer 8.
  • the second measurement point Po2 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to one side in the second direction Y (the opposite side from the mark 54).
  • the third measurement point Po3 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to one side in the first direction X (to the right of the mark 54).
  • the fourth measurement point Po4 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the second direction Y (the side toward the mark 54).
  • the fifth measurement point Po5 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the first direction X (to the left of the mark 54).
  • the measurement results of the incident angle ⁇ , diffraction angle 2 ⁇ , and off angle ⁇ off at the first to fifth measurement points Po1 to Po5 are shown in the following Table 1.
  • the off angle ⁇ off is calculated using the incident angle ⁇ and diffraction angle 2 ⁇ by the formula " ⁇ -(2 ⁇ 1/2)".
  • the average value of the off angle ⁇ off of the first to fifth measurement points Po1 to Po5 was 4.036°, and the standard deviation of these off angles ⁇ off was 0.009° ( ⁇ 0.01°). From this, it can be understood that the in-plane variation of the off angle ⁇ off occurring at the upper end of the first layer 8 (first wafer main surface 51 of wafer 50) is extremely small, and is not enough to interfere with the channeling implantation process.
  • the measurement point may be any one or more (all) of the first to fifth measurement points Po1 to Po5.
  • the measurement point may be only the first measurement point Po1.
  • the off angle ⁇ off may be measured at multiple points on the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50) and an implantation angle may be set in the channeling implantation process according to the in-plane variation of the off angle ⁇ off.
  • the manufacturing man-hours manufactured costs
  • the in-plane error of the first region 14 formed in the first layer 8 is appropriately suppressed.
  • the off-angle ⁇ off of the first layer 8 is approximately equal to the off-angle ⁇ off of the wafer 50 and the off-angle ⁇ off of the buffer layer 26. Therefore, the crystal orientation measurement process may be performed on the wafer 50 or the buffer layer 26 prior to the formation process of the first layer 8. However, from the standpoint of ensuring accuracy, it is preferable that the crystal orientation measurement process be performed on the first layer 8.
  • the multiple first openings 61 are formed at intervals in the first array direction Da1 over the entire surface of the upper end of the first layer 8, and are each partitioned into stripes extending in the first extension direction De1.
  • the multiple first openings 61 cross the multiple device regions 55 and the multiple lines to be cut 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple lines to be cut 56 in a stripe pattern.
  • the multiple first openings 61 expose both the portion of the upper end of the first layer 8 that is located within the active region 10 and the portion that is located within the peripheral region 11 in each device region 55.
  • the process for forming a plurality of first regions 14 includes a channeling injection process of a trivalent element (p-type impurity) into the first layer 8.
  • the first layer 8 (wafer 50) has an off angle ⁇ off inclined at a predetermined angle in a predetermined off direction Doff with respect to the first wafer main surface 51.
  • the channeling injection process is carried out based on data (information) of the off angle ⁇ off.
  • a trivalent element is introduced into the first layer 8 with a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle ⁇ off) (see also Figure 14).
  • a trivalent element is implanted along the vertical direction Z perpendicular to the upper end of the first layer 8 (first wafer main surface 51).
  • the trivalent element is introduced along a direction in which the atomic rows are relatively dense in plan view, so the trivalent element collides with the atomic rows at a relatively shallow depth position. Therefore, the atomic rows prevent the introduction of the trivalent element into the first layer 8 at a relatively deep depth position. As a result, a first region 14 that does not have a slow portion 22 is formed (see also FIG. 14).
  • the wafer 50 may be supported horizontally and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • the wafer 50 may be supported tilted by the off angle ⁇ off from the horizontal and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • a plurality of first regions 14 having a predetermined thickness are formed at a predetermined depth (see also Figures 13A to 13E).
  • the implantation energy of the trivalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection temperature of the trivalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • a trivalent element belonging to the heavy elements heavier than carbon is introduced into the first layer 8.
  • the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium).
  • the trivalent element is aluminum.
  • the first extension direction De1 may be the a-axis direction or the m-axis direction.
  • the first extension direction De1 may be a direction other than the a-axis direction or the m-axis direction.
  • the trivalent element is introduced into the first layer 8 through the multiple first openings 61 at an angle of approximately the off angle ⁇ off with respect to the upper end of the first layer 8 in a cross-sectional view along the first array direction Da1.
  • the trivalent element is introduced into the first layer 8 through the multiple first openings 61 almost perpendicular to the upper end of the first layer 8 in a cross-sectional view along the first array direction Da1. This prevents the multiple first regions 14 from being formed in the first layer 8 in an inclined position. In addition, the wall surfaces of the multiple first openings 61 are prevented from becoming a shield against the entrance path of the trivalent element.
  • the trivalent element may be electrically activated by an annealing method, and at the same time, lattice defects and the like that have occurred in the first layer 8 may be repaired.
  • the annealing temperature for the first layer 8 may be 500°C or higher and 2000°C or lower. This forms a first superjunction structure SJ1 at the same time as forming a plurality of first regions 14.
  • the process of forming the multiple intermediate regions 25 includes placing a mask (not shown) having a predetermined pattern on the upper end of the first layer 8.
  • the mask (not shown) is preferably an organic mask (resist mask).
  • the mask (not shown) has multiple openings that each expose an area in the first layer 8 where the multiple first regions 14 are formed.
  • the process of forming the multiple intermediate regions 25 includes a process of introducing a trivalent element into the first layer 8 at a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle ⁇ off) by a random implantation method through a mask (not shown) (see also FIG. 14).
  • the trivalent element may be introduced into the first layer 8 once or multiple times. When the trivalent element is introduced multiple times, the trivalent element may be introduced in multiple stages at different depth positions in the first layer 8 with multiple implantation energies.
  • the process of forming the multiple intermediate regions 25 may be performed consecutively from the process of forming the multiple first regions 14. In this case, the multiple intermediate regions 25 may be formed using the above-mentioned first mask 60.
  • the second openings 63 are formed at intervals in a second arrangement direction Da2 different from the first arrangement direction Da1 over the entire surface of the upper end of the second layer 9, and are each partitioned into strips extending in a second extension direction De2 different from the first extension direction De1.
  • the second openings 63 cross the device regions 55 and the lines to be cut 56 in the second extension direction De2, exposing the device regions 55 and the lines to be cut 56 in a stripe pattern.
  • the second openings 63 expose both a portion of the upper end of the second layer 9 that is located within the active region 10 and a portion that is located within the peripheral region 11 in each device region 55.
  • the injection angle of the trivalent element into the second layer 9 is controlled, and the trivalent element is introduced into the second layer 9 along the second axial channel CH2 (the c-axis of the SiC single crystal in this embodiment) with a predetermined injection energy (see also Figures 13A to 13E).
  • a predetermined injection energy see also Figures 13A to 13E.
  • the implantation energy of the trivalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection temperature of the trivalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection temperature for the second region 15 may be approximately equal to the injection temperature for the first region 14, or may be different from the injection temperature for the first region 14.
  • the injection temperature for the second region 15 may be equal to or higher than the injection temperature for the first region 14. Also, the injection temperature for the second region 15 may be lower than the injection temperature for the first region 14.
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • the trivalent element is introduced along the second axial channel CH2, in which the atomic rows are relatively sparse in plan view.
  • the trivalent element travels through the second axial channel CH2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the second layer 9.
  • the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.
  • the trivalent element may be electrically activated by an annealing method, and at the same time, lattice defects and the like that have occurred in the second layer 9 may be repaired.
  • the annealing temperature for the second layer 9 may be 500°C or higher and 2000°C or lower. This forms a plurality of second regions 15 and at the same time forms the second superjunction structure SJ2.
  • a determination step is performed as to whether or not a thickness adjustment step for the second layer 9 is to be performed (step S15 in FIG. 41). If the thickness of the second layer 9 is to be adjusted (step S15 in FIG. 41: YES), the second layer 9 is thinned from the upper end side (step S16 in FIG. 41).
  • multiple modified layers are formed (remain) on the portions of the first to fourth side surfaces 5A to 5D that are made of the base layer 6 after cleavage. This makes it possible to prevent the multiple modified layers from overlapping the decorative pattern PT (the multiple first marks Mk1 and the multiple second marks Mk2). This improves the visibility of the decorative pattern PT. In addition, the electrical influence that the multiple modified layers have on the multiple first regions 14 and the multiple second regions 15 via the decorative pattern PT is reduced.
  • Figure 45 is a plan view showing a SiC semiconductor device 1B relating to the second embodiment.
  • Figure 46A is a cross-sectional view taken along line XLVIA-XLVIA shown in Figure 45.
  • Figure 46B is a cross-sectional view taken along line XLVIB-XLVIB shown in Figure 45.
  • Figure 47A is a plan view showing an example layout of chip 2 (first layer 8).
  • Figure 47B is a plan view showing an example layout of chip 2 (second layer 9).
  • Figure 48 is a perspective view showing an example layout of chip 2.
  • the decorative pattern PT includes the second difference mark Md2 (see Figures 6B and 6C, etc.), it is preferable that the second difference mark Md2 is formed at a distance from the outer peripheral surface 72 toward the lower end of the first layer 8, and faces the outer peripheral surface 72 with multiple second marks Mk2 in between.
  • the SiC semiconductor device 1B includes a p-type column region 12 formed in the stack portion 7 in the active region 10.
  • the column region 12 is formed in the same layout as in the SiC semiconductor device 1A. That is, the multiple first regions 14 are formed in the first layer 8 in the same layout as the multiple first regions 14 in the SiC semiconductor device 1A, and define multiple first drift regions 16.
  • the multiple second regions 15 are formed in the second layer 9 in the same layout as the multiple second regions 15 in the SiC semiconductor device 1A, and define multiple second drift regions 17.
  • the multiple first regions 14 are drawn out from a portion of the first layer 8 facing the active surface 71 to a portion of the first layer 8 facing the outer peripheral surface 72.
  • the multiple first regions 14 are also arranged at intervals in the first arrangement direction Da1 in the outer peripheral region 11, and are each formed in a strip shape extending in the first extension direction De1.
  • the multiple first regions 14 are formed at intervals from the outer peripheral surface 72 to the lower end side of the first layer 8 in the outer peripheral region 11, and face the outer peripheral surface 72 with the second layer 9 in between.
  • the portions of the second regions 15 located in the outer peripheral region 11 may have a thickness less than that of the first regions 14. Of course, the portions of the second regions 15 located in the outer peripheral region 11 may have a thickness greater than or equal to that of the first regions 14.
  • the second lower ends 15a of the second regions 15 are located in a region closer to the lower end of the second layer 9 than the depth position of the outer peripheral surface 72 in the thickness direction of the second layer 9.
  • the second upper ends 15b of the second regions 15 are located in a region closer to the active surface 71 than the outer peripheral surface 72 in the thickness direction of the second layer 9.
  • the second region 15 may be exposed from the entire area of the first connection surface 73A.
  • the third connection surface 73C is formed along the second extension direction De2 from the middle of the second region 15, the second region 15 may be exposed from the entire area of the third connection surface 73C.
  • the second regions 15 are also arranged at intervals in the second arrangement direction Da2 in the outer peripheral region 11, and are each formed in a band shape extending in the second extension direction De2.
  • the second regions 15 are exposed from the outer peripheral surface 72 in the outer peripheral region 11.
  • the multiple second regions 15 extend from the outer peripheral region 11 toward either or both (both in this embodiment) the second side surface 5B and the fourth side surface 5D, and each has a portion exposed from either or both (both in this embodiment) the second side surface 5B and the fourth side surface 5D.
  • the portions of the multiple second regions 15 exposed from the second side surface 5B form multiple second marks Mk2 on the second side surface 5B
  • the portions of the multiple second regions 15 exposed from the fourth side surface 5D form multiple second marks Mk2 on the fourth side surface 5D.
  • body region 32 does not have gradual portion 22 having a thickness of 0.5 ⁇ m or more, and has a concentration gradient including gradually increasing portion 20, peak portion 21, and gradually decreasing portion 23 within a range of 0.5 ⁇ m.
  • Body region 32 may have a peak value of a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the body region 32 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the body region 32 may be the same as the trivalent element of the second region 15, etc., or may be a different species from the trivalent element of the second region 15, etc.
  • the trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium.
  • the body region 32 may be formed by utilizing a part of the p-type top layer 30.
  • the SiC semiconductor device 1B includes a plurality of trench electrode type gate structures 35 formed on the first main surface 3 (active surface 71) in the active region 10.
  • the gate structures 35 may be referred to as "trench gate structures.”
  • a gate potential is applied to the plurality of gate structures 35 as a control potential.
  • the plurality of gate structures 35 control the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.
  • the multiple gate structures 35 are arranged at intervals inward from the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 in the active region 10.
  • the multiple gate structures 35 are arranged at intervals in the second array direction Da2 and are each formed in a strip shape extending in the second extension direction De2. That is, in this embodiment, the multiple gate structures 35 are arranged in stripes extending along the multiple second regions 15 and intersect with the multiple first regions 14 and the multiple first drift regions 16 in the stacking direction.
  • the second array direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X).
  • the array direction and extension direction of the multiple gate structures 35 are changed according to the second array direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second array direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction.
  • the second array direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple gate structures 35 are arranged offset from the multiple second regions 15 toward the multiple second drift regions 17. Specifically, the multiple gate structures 35 penetrate the body region 32 at intervals from the multiple second regions 15, and are arranged in a one-to-one correspondence within the multiple second drift regions 17. In other words, the multiple gate structures 35 are arranged alternately with the multiple second regions 15 along the second array direction Da2, and face the multiple second regions 15 in the horizontal direction.
  • the multiple gate structures 35 are formed at intervals from the lower ends of the multiple second drift regions 17 toward the active surface 71, and face the multiple first regions 14 and the multiple first drift regions 16 across parts of the multiple second drift regions 17. It is preferable that the multiple gate structures 35 are formed at intervals from the intermediate portions of the thickness ranges of the multiple second regions 15 toward the active surface 71. Of course, the multiple gate structures 35 may be formed at a depth position that crosses the intermediate portions of the thickness ranges of the multiple second regions 15.
  • Each gate structure 35 has a trench width WT in the arrangement direction (second direction Y in this embodiment) and a trench depth DT in the vertical direction Z.
  • the trench width WT is less than the second pitch P2 (first pitch P1).
  • the trench depth DT is less than the second thickness T2 of the second layer 9. It is preferable that the trench depth DT is approximately equal to the aforementioned peripheral depth DO.
  • the trench depth DT may be greater than or equal to the peripheral depth DO, or may be less than the peripheral depth DO.
  • the trench width WT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench width WT may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, and 4 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • Each gate structure 35 includes a trench 75, an insulating film 76, and a buried electrode 77.
  • the trench 75 is formed in the active surface 71 and defines the wall surface of the gate structure 35.
  • the insulating film 76 covers the wall surface of the trench 75.
  • the insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of an oxide of the chip 2.
  • the buried electrode 77 is embedded in the trench 75 with the insulating film 76 in between, and faces the channel with the insulating film 76 in between.
  • the buried electrode 77 may include p-type or n-type conductive polysilicon.
  • the SiC semiconductor device 1B includes a plurality of source regions 33 formed on both sides of a plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71).
  • the plurality of source regions 33 are formed in a surface layer portion of the body region 32.
  • the plurality of source regions 33 have a higher n-type impurity concentration (peak value) than the second layer 9 (second drift region 17).
  • the plurality of source regions 33 may have an n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the multiple source regions 33 extend in a band shape along the corresponding gate structures 35 in a plan view.
  • the multiple source regions 33 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the second drift region 17 across a portion of the body region 32 in the stacking direction.
  • the multiple source regions 33, together with the multiple second drift regions 17 located directly below, define a channel (current path) that extends along the wall surface of the corresponding gate structure 35.
  • the multiple source regions 33 may face the second region 15 across a portion of the body region 32 in the stacking direction.
  • the multiple source regions 33 may be formed at intervals from the second region 15 to the second drift region 17 side (gate structure 35 side) so as not to face the second region 15 in the stacking direction.
  • the plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32.
  • the p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second regions 15.
  • the plurality of contact regions 34 may have a p-type impurity concentration (peak value) of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the multiple contact regions 34 are interposed between the multiple source regions 33 adjacent to each other, and extend in a strip shape along the multiple gate structures 35.
  • the multiple contact regions 34 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the multiple second regions 15 across a portion of the body region 32 in the stacking direction.
  • Figure 51 is a perspective view showing the configuration of the outer peripheral region 11.
  • Figure 52A is a cross-sectional view in the first direction X showing a main part of the outer peripheral region 11.
  • Figure 52B is a cross-sectional view in the second direction Y showing a main part of the outer peripheral region 11.
  • the column region 12 is omitted from Figure 51.
  • the bottom of the well region 78 is located closer to the lower end of the second layer 9 than the bottom wall of the gate structure 35. It is preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the second lower ends 15a of the second regions 15. It is particularly preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the intermediate portions of the thickness ranges of the second regions 15.
  • the well region 78 is composed of a random impurity region introduced into the surface layer of the second layer 9 by a random injection method into the second layer 9 (see also FIG. 14). Therefore, the well region 78 has a thickness in the direction along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the well region 78 is less than the first region thickness TR1 of the first region 14.
  • the SiC semiconductor device 1B includes at least one (preferably 2 to 20) p-type field region 38 formed in the surface layer of the outer peripheral surface 72 in the outer peripheral region 11.
  • the multiple field regions 38 are formed in the surface layer of the outer peripheral surface 72 in a manner similar to that of the SiC semiconductor device 1A.
  • the multiple field regions 38 are arranged at intervals from the periphery of the active surface 71 (first to fourth connection surfaces 73A to 73D) and the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). Specifically, the multiple field regions 38 are arranged at intervals from the well region 78 to the periphery side of the outer circumferential surface 72.
  • the multiple field regions 38 extend in a band shape along the active surface 71 in a plan view, and are formed in a ring shape (specifically a square ring) surrounding the active surface 71.
  • the bottoms of the multiple field regions 38 are preferably located on the outer peripheral surface 72 side relative to the middle part of the thickness range of the second region 15.
  • the multiple field regions 38 may be connected to the multiple second regions 15 in the portion extending along the second extension direction De2.
  • the multiple field regions 38 may be formed horizontally spaced apart from the multiple second regions 15 in the portion extending along the second extension direction De2, and may not be connected to the multiple second regions 15.
  • the SiC semiconductor device 1B includes the aforementioned interlayer insulating film 40 that covers the first main surface 3.
  • the interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D.
  • the first insulating film 41 is connected to the insulating film 76 on the active surface 71, exposing the buried electrode 77.
  • the first insulating film 41 covers the well region 78 and the multiple field regions 38 on the outer peripheral surface 72.
  • the first insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Therefore, the first insulating film 41 covers the multiple second marks Mk2 (multiple second regions 15) on the periphery of the outer peripheral surface 72.
  • the gate pad 45 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view.
  • the gate pad 45 is disposed in a region close to the center of one side of the active surface 71 (the second connection surface 73B in this embodiment) in a plan view.
  • the gate pad 45 may also be disposed at a corner of the active surface 71 or in the center of the active surface 71 in a plan view.
  • the buried electrodes 77 face the corresponding second regions 15 across the insulating film 76 in the stacking direction, and face the corresponding second drift regions 17 across the insulating film 76 in the horizontal direction.
  • the aforementioned multiple source regions 33 and multiple contact regions 34 each face the corresponding second drift regions 17 across a portion of the body region 32 in the stacking direction.
  • FIG. 55 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment.
  • the multiple gate structures 35 according to the fourth embodiment each have a configuration that contributes to narrowing the pitch.
  • the multiple gate structures 35 according to the fourth embodiment are particularly effective in realizing a narrower pitch in the column region 12 (multiple second regions 15).
  • FIG. 55 shows an example in which the gate structure 35 according to the first embodiment described above is replaced with the gate structure 35 according to the fourth embodiment, but the configuration of the gate structure 35 according to the fourth embodiment is also applicable to the configurations of the gate structures 35 according to the second and third embodiments.
  • the multiple source regions 33 on one side may face the regions between the multiple source regions 33 on the other side in a one-to-one correspondence.
  • the multiple source regions 33 may be arranged in a staggered pattern in a planar view.
  • the multiple source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 between them.
  • the aforementioned contact regions 34 are formed in the regions between adjacent gate structures 35 on the surface layer of the first main surface 3 (active surface 71).
  • the contact regions 34 are arranged at intervals along the gate structures 35 so as to be connected to the gate structures 35 located on both sides.
  • the multiple contact regions 34 on one side may face the regions between the multiple source regions 33 on the other side (i.e., the multiple source regions 33) in a one-to-one correspondence.
  • the multiple contact regions 34 may be arranged in a staggered pattern in a planar view.
  • the multiple contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 between them.
  • the aforementioned interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D.
  • the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D across the first insulating film 41.
  • the second insulating film 42 covers the peripheral portion of the active surface 71, exposing the multiple gate structures 35 collectively at the inner portion of the active surface 71.
  • the second insulating film 42 penetrates into the trench 75 from above the first main surface 3 (active surface 71) at both ends of the multiple gate structures 35, and is connected to the buried insulator 80 within the trench 75.
  • the interlayer insulating film 40 includes a plurality of contact openings 43 (not shown) that expose both ends (buried electrodes 77) of the plurality of gate structures 35, and a single contact opening 43 that collectively exposes the inner portions (buried insulator 80) of the plurality of gate structures 35, the plurality of source regions 33, and the plurality of contact regions 34.
  • Figure 57 is a plan view showing a SiC semiconductor device 1C relating to the third embodiment.
  • Figure 58A is a cross-sectional view taken along line LVIIIA-LVIIIA shown in Figure 57.
  • Figure 58B is a cross-sectional view taken along line LVIIIB-LVIIIB shown in Figure 57.
  • Figure 59A is a plan view showing an example layout of chip 2 (first layer 8).
  • Figure 59B is a plan view showing an example layout of chip 2 (second layer 9).
  • Figure 60 is a perspective view showing an example layout of chip 2.
  • Figure 61 is a perspective view showing the configuration of the outer periphery region 11. In Figure 61, the column region 12 is omitted from illustration.
  • the decorative pattern PT may have at least one of the multiple features shown in the first to fifth embodiment examples.
  • the column region 12 may have at least one of the multiple features shown in the first to twelfth embodiment examples described above.
  • the column region 12 may have a feature that combines multiple (two or more) features shown in the first to twelfth embodiment examples described above.
  • the interlayer insulating film 90 covers the multiple field regions 38 in the peripheral region 11.
  • the interlayer insulating film 90 is continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).
  • the interlayer insulating film 90 may be formed at a distance inward from the periphery of the first main surface 3, exposing the second layer 9 from the periphery of the first main surface 3.
  • Figure 63 is a cross-sectional perspective view showing an SBD structure 93 according to a second embodiment.
  • the first pad electrode 92 is mechanically and electrically connected to the second regions 15 and the second drift regions 17 at the first main surface 3.
  • the first pad electrode 92 forms a JBS structure (Junction Barrier Controlled Schottky structure) with the second regions 15, and forms a Schottky junction with the second drift regions 17.
  • JBS structure Joint Barrier Controlled Schottky structure
  • the width of the surface region 95 may be greater than the width of the second regions 15, and the pitch of the surface region 95 may be less than the pitch of the second regions 15.
  • the width of the surface region 95 may be greater than the width of the second regions 15, and the pitch of the surface region 95 may be greater than the pitch of the second regions 15.
  • the width of the surface regions 95 may be approximately equal to the width of the second regions 15.
  • the pitch of the surface regions 95 may be approximately equal to the pitch of the second regions 15.
  • the p-type impurity concentration of the multiple surface regions 95 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the surface region 95 may be the same as the trivalent element of the second region 15, etc., or may be a different species from the trivalent element of the second region 15, etc.
  • the trivalent element of the surface region 95 may be at least one of boron, aluminum, gallium, and indium.
  • the first pad electrode 92 is mechanically and electrically connected to the top layer 30 on the first main surface 3.
  • the first pad electrode 92 forms a JBS structure with the multiple surface layer regions 95 on the first main surface 3, and forms a Schottky junction with the region between the multiple surface layer regions 95 on the first main surface 3.
  • the layout restrictions and electrical characteristic restrictions of the JBS structure resulting from the layout of the superjunction structure SJ are alleviated.
  • the multiple surface regions 95 are arranged at intervals in the first arrangement direction Da1 of the first region 14 and extend in the first extension direction De1 of the first region 14.
  • the first arrangement direction Da1 is the m-axis direction
  • the first extension direction De1 is the a-axis direction.
  • modified examples of the decorative pattern PT are shown. Below, an example is shown in which the modified decorative pattern PT is adopted in the SiC semiconductor device 1 according to the first embodiment, but the modified decorative pattern PT can also be applied to the SiC semiconductor device 1B according to the second embodiment and the SiC semiconductor device 1C according to the third embodiment.
  • the decorative pattern PT of the first modified example is realized by forming a plurality of first regions 14 extending in a direction intersecting both the first side 5A and the second side 5B.
  • the first extension direction De1 of the plurality of first regions 14 is a direction intersecting both the a-axis direction and the m-axis direction.
  • the second difference mark Md2 is not formed on the second side 5B.
  • the second marks Mk2 may have a width (second width W2) different from the width (first width W1) of the first marks Mk1 on the first side 5A.
  • the second marks Mk2 may have a pitch (second pitch P2) different from the pitch (first pitch P1) of the first marks Mk1 on the first side 5A.
  • the second marks Mk2 may overlap either one or both of the first marks Mk1 and the first spaces Sp1 in the thickness direction on the first side 5A.
  • the decorative pattern PT of the second modified example is realized by forming a plurality of second regions 15 extending in a direction intersecting both the first side 5A and the second side 5B.
  • the second extension direction De2 of the plurality of second regions 15 is a direction intersecting both the a-axis direction and the m-axis direction.
  • Figure 69 is an oblique view showing a chip 2 together with a decorative pattern PT according to a third modified example.
  • the decorative pattern PT according to the third modified example has a form that combines the decorative pattern PT according to the first modified example and the decorative pattern PT according to the second modified example.
  • the multiple first marks Mk1 are exposed from both the first side 5A and the second side 5B
  • the multiple second marks Mk2 are exposed from both the first side 5A and the second side 5B.
  • a plurality of first regions 14 are formed extending in a direction intersecting the first side surface 5A and the second side surface 5B, and a plurality of second regions 15 are formed extending in a direction intersecting the first side surface 5A and the second side surface 5B.
  • the plurality of second regions 15 intersect or are perpendicular to the plurality of first regions 14.
  • Figure 70 is a perspective view showing a chip 2 together with a decorative pattern PT relating to the fourth modified example.
  • Figure 71 is a cross-sectional perspective view showing a column region 12 relating to the modified example.
  • Figure 72 is a cross-sectional view showing a main part of the outer periphery region 11 together with a column region 12 relating to the modified example.
  • Figure 71 shows a modified example of the column region 12 relating to the first basic form.
  • the column region 12 according to the modified example may have at least one of the multiple features shown in the first to twelfth embodiment examples.
  • the column region 12 according to the modified example may have a feature that combines multiple (two or more) features shown in the first to twelfth embodiment examples.
  • the lower end of the second mark Mk2 may be formed at a distance from the lower end to the upper end of the second layer 9, facing the first mark Mk1 across a part (lower end) of the second layer 9.
  • the lower end of the second mark Mk2 may have an extension that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.
  • the extensions of the multiple second marks Mk2 are connected to the multiple first marks Mk1 in a one-to-one correspondence.
  • the multiple second marks Mk2 form a stripe pattern integrated with the multiple first marks Mk1.
  • the decorative pattern PT according to the fourth modified example is realized by matching both the second arrangement direction Da2 and the second extension direction De2 of the multiple second regions 15 with both the first arrangement direction Da1 and the first extension direction De1 of the multiple first regions 14.
  • the multiple second regions 15 are formed in the second layer 9 so as to overlap the multiple first regions 14 in a one-to-one correspondence in the stacking direction in both the active region 10 and the peripheral region 11.
  • the multiple first regions 14 extend in stripes in the first extension direction De1 (second extension direction De2) within the first layer 8.
  • the multiple first regions 14 define multiple first drift regions 16 that extend in stripes in the first extension direction De1 (second extension direction De2) within the first layer 8.
  • the multiple second regions 15 extend in stripes in the first extension direction De1 (second extension direction De2) within the second layer 9.
  • the multiple second regions 15 define multiple second drift regions 17 that extend in stripes in the first extension direction De1 (second extension direction De2) within the second layer 9.
  • the second regions 15, together with the first regions 14, form column regions 12 that extend in stripes in the first extension direction De1 (second extension direction De2) within the stack 7.
  • the column regions 12 define drift regions 13 that extend in stripes in the first extension direction De1 (second extension direction De2) within the stack 7.
  • first arrangement direction Da1 and the second arrangement direction Da2 are the a-axis direction
  • first extension direction De1 and the second extension direction De2 are the m-axis direction
  • first arrangement direction Da1 and the second arrangement direction Da2 may be the m-axis direction
  • first extension direction De1 and the second extension direction De2 may be the a-axis direction.
  • first extension direction De1 and the second extension direction De2 may be directions other than the a-axis direction and the m-axis direction.
  • a decorative pattern PT similar to the decorative pattern PT of the third modified example is formed by a plurality of column regions 12 extending in a stripe shape.
  • the field regions 38 are formed in a region on the first main surface 3 side of the striped column regions 12.
  • the field regions 38 extend along the first regions 14 and the second regions 15 in the portion extending in the first extension direction De1 (second extension direction De2).
  • the multiple field regions 38 intersect with the multiple first regions 14 and the multiple second regions 15 at the same locations in the portion extending in a direction intersecting the first extension direction De1 (second extension direction De2).
  • the multiple field regions 38 may be connected to the multiple second regions 15, or may be formed at a distance from the multiple second regions 15.
  • the decorative pattern PT is formed on the first to fourth side faces 5A to 5D.
  • a structure without the decorative pattern PT may be adopted.
  • the multiple first regions 14 and the multiple second regions 15 are formed in the laminated portion 7 at intervals inward from the first to fourth side faces 5A to 5D.
  • the multiple first regions 14 and the multiple second regions 15 may be formed in the active region 10 at intervals inward from the peripheral region 11.
  • one of the multiple first regions 14 and the multiple second regions 15 may be exposed from the first to fourth side surfaces 5A to 5D, and the other of the multiple first regions 14 and the multiple second regions 15 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D.
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 each contain a SiC single crystal.
  • at least one or all of the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • a wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon.
  • Examples of single crystals of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga 2 O 3 ).
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 may be made of the same type of single crystal or different types of single crystals.
  • the aforementioned channeling injection process (the process of injecting impurities into regions with sparse atomic rows) can also be applied to single crystals that form a cubic crystal.
  • the single crystal of the wide band gap semiconductor may be a cubic crystal or a hexagonal crystal.
  • these axial channels are formed by regions surrounded by atomic rows that are aligned along the low-index crystal axes of the cubic crystal axes.
  • the low-index crystal axis of a cubic crystal is a crystal axis in which the absolute values of "h", "k” and “l” in the Miller indices (h, k, l) are all 2 or less (preferably 1 or less).
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26 and the top layer 30 may contain single crystal silicon.
  • [C12] A semiconductor device (1A, 1B, 1C) according to C10 or C11, in which the first mark (Mk1) is formed at an interval from the upper end to the lower end of the first layer (8).
  • the semiconductor device (1A, 1B, 1C) according to any one of C10 to C14, wherein the first mark (Mk1) includes a first peak value (PA, 21A) on the upper end side of the first layer (8) and a first gradual portion (22A) in which the impurity concentration gradually decreases at a gradual rate in a region on the lower end side of the first layer (8) from the first peak value (PA, 21A), and the second mark (Mk2) includes a second peak value (PB, 21B) on the upper end side of the second layer (9) and a second gradual portion (22B) in which the impurity concentration gradually decreases at a gradual rate in a region on the lower end side of the second layer (9) from the second peak value (PB, 21B).
  • the first mark (Mk1) includes a first peak value (PA, 21A) on the upper end side of the first layer (8) and a first gradual portion (22A) in which the impurity concentration gradually decreases at a gradual rate in a region on the lower end side
  • Md1 a first different mark
  • p-type second conductivity type
  • Md2 a second different mark
  • p-type a second conductivity type

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
PCT/JP2023/046707 2022-12-28 2023-12-26 ＳｉＣ半導体装置 Ceased WO2024143386A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012142537A (ja) * 2010-12-16 2012-07-26 Mitsubishi Electric Corp 絶縁ゲート型バイポーラトランジスタとその製造方法
JP2019054273A (ja) * 2018-11-22 2019-04-04 株式会社東芝 半導体装置
JP2019186252A (ja) * 2018-04-02 2019-10-24 株式会社豊田中央研究所 半導体装置
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置
JP2022182509A (ja) * 2021-05-28 2022-12-08 株式会社デンソー 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012142537A (ja) * 2010-12-16 2012-07-26 Mitsubishi Electric Corp 絶縁ゲート型バイポーラトランジスタとその製造方法
JP2019186252A (ja) * 2018-04-02 2019-10-24 株式会社豊田中央研究所 半導体装置
JP2019054273A (ja) * 2018-11-22 2019-04-04 株式会社東芝 半導体装置
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置
JP2022182509A (ja) * 2021-05-28 2022-12-08 株式会社デンソー 半導体装置およびその製造方法

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