WO2024128057A1 - 半導体デバイスの製造方法 - Google Patents

半導体デバイスの製造方法 Download PDF

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Publication number
WO2024128057A1
WO2024128057A1 PCT/JP2023/043371 JP2023043371W WO2024128057A1 WO 2024128057 A1 WO2024128057 A1 WO 2024128057A1 JP 2023043371 W JP2023043371 W JP 2023043371W WO 2024128057 A1 WO2024128057 A1 WO 2024128057A1
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Prior art keywords
substrate
semiconductor
fixing portion
semiconductor substrate
forming step
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PCT/JP2023/043371
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English (en)
French (fr)
Japanese (ja)
Inventor
良則 五十川
浩 山邊
スニル ウィクラマナヤカ
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Tazmo Co Ltd
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Tazmo Co Ltd
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Priority to EP23903346.7A priority Critical patent/EP4636810A1/en
Priority to KR1020257021077A priority patent/KR20250114080A/ko
Priority to CN202380085253.0A priority patent/CN120359595A/zh
Publication of WO2024128057A1 publication Critical patent/WO2024128057A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/20—Bonding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/20—Bonding
    • B23K26/32—Bonding taking account of the properties of the material involved
    • B23K26/323—Bonding taking account of the properties of the material involved involving parts made of dissimilar metallic material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/20—Bonding
    • B23K26/32—Bonding taking account of the properties of the material involved
    • B23K26/324—Bonding taking account of the properties of the material involved involving non-metallic parts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/57—Working by transmitting the laser beam through or within the workpiece the laser beam entering a face of the workpiece from which it is transmitted through the workpiece material to work on a different workpiece face, e.g. for effecting removal, fusion splicing, modifying or reforming
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H10P72/0421—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0436—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/11—Separation of active layers from substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/18—Dissimilar materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic materials other than metals or composite materials
    • B23K2103/56—Inorganic materials other than metals or composite materials being semiconducting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates

Definitions

  • the present invention relates to semiconductor device manufacturing technology.
  • a manufacturing technology for semiconductor devices that involves a process of polishing a semiconductor wafer (e.g., a wafer with a thickness of about 300 ⁇ m) to form a semiconductor substrate of a desired thickness (e.g., a thickness of 150 ⁇ m or less).
  • a semiconductor wafer e.g., a wafer with a thickness of about 300 ⁇ m
  • a desired thickness e.g., a thickness of 150 ⁇ m or less.
  • WBG wide band gap
  • GaAs, SiC, GaN, AlN, BN, and diamond have been attracting attention as semiconductor materials that enable semiconductor devices to operate normally even at high temperatures reaching 300°C.
  • WBG materials are also semiconductor materials that enable faster switching speeds, and in that respect, they are expected to be used as materials for semiconductor devices for high-speed communications.
  • WBG materials are also semiconductor materials that are resistant to high electric fields, and in that respect, they are expected to be used as materials for high-voltage semiconductor devices. In this way, WBG materials have various advantages as materials for semiconductor devices.
  • WBG materials are expensive materials. Despite this, when a semiconductor substrate made of WBG materials is formed by polishing a semiconductor wafer, the portion of the semiconductor wafer that is removed by polishing becomes waste, resulting in a significant increase in manufacturing costs.
  • the method of bonding a semiconductor wafer and a support was to perform CMP (Chemical Mechanical Polishing) on both bonding surfaces, then directly bond the bonding surfaces together, so that the entire bonding area is bonded to each other by atomic or molecular forces (direct bonding method).
  • CMP Chemical Mechanical Polishing
  • bonding using CMP has the following problems: (1) the cost of the CMP process is high; and (2) because the semiconductor wafer and the support are firmly bonded, if it is desired to remove the support from the semiconductor substrate after separation from the semiconductor wafer, a process of grinding off the support is required.
  • the object of the present invention is to facilitate the handling of a semiconductor substrate after its formation in a semiconductor device manufacturing technique that includes a process for forming the semiconductor substrate using a split layer.
  • the method for manufacturing a semiconductor device includes a split layer forming step, a fixing portion forming step, and a splitting step.
  • a split layer is formed at a position at a predetermined depth from the surface of a first substrate whose main component is a semiconductor, to enable a semiconductor substrate having a thickness of the predetermined depth to be separated from the first substrate.
  • a fixing portion for fixing a portion of the first substrate that will become the semiconductor substrate to the second substrate is formed in an annular shape in an atmosphere at a lower pressure than the predetermined pressure, thereby sealing the inside of the annular shape.
  • the first substrate is split at the split layer in an atmosphere at the above-mentioned predetermined pressure.
  • a ring-shaped fixing portion is formed in an atmosphere at a lower pressure than a predetermined pressure (e.g., atmospheric pressure).
  • a predetermined pressure e.g., atmospheric pressure
  • a pressure difference can be generated between the pressure inside the ring of the fixing portion (internal pressure) and the pressure outside the ring (external pressure).
  • an adhesive force due to the pressure difference can be generated between the first substrate and the second substrate. Therefore, in an atmosphere at the predetermined pressure, the first substrate and the second substrate can be firmly bonded by the bonding force of the fixing portion and the adhesive force due to the pressure difference between the internal pressure and the external pressure.
  • the present invention makes it easier to handle a semiconductor substrate after it is formed in a semiconductor device manufacturing technique that includes a process for forming the semiconductor substrate using a split layer.
  • FIG. 1 is a conceptual diagram showing the manufacturing method according to the embodiment in the order of steps.
  • FIG. 2 is a conceptual diagram showing the process continued from FIG. 1 in processing order.
  • FIG. 3 is a plan view showing the shape of the fixing portion formed in the embodiment.
  • FIG. 4 is a conceptual diagram showing a part of the manufacturing method according to the first modification in the order of processing.
  • FIG. 5A is a conceptual diagram showing a division layer forming step executed in a manufacturing method according to a second modified example
  • FIG. 5B is a conceptual diagram showing a comparative example.
  • FIG. 6 is a conceptual diagram showing a part of a manufacturing method according to the fourth modification in the order of processing.
  • FIG. 7 is a plan view showing the shape of the fixing portion formed in the fourth modified example.
  • FIGS. 8A and 8B are a conceptual diagram and a plan view showing a further modification of the manufacturing method shown in FIGS.
  • FIG. 9 is a plan view showing a first example of the shape of the fixing portion Q formed in the fifth modified example.
  • 10A and 10B are plan views showing second and third examples, respectively, of the shape of the fixing portion Q formed in the fifth modified example.
  • FIG. 11(A) is a conceptual diagram showing the adhesion portion forming step and the cutting step performed in a manufacturing method according to the sixth modified example
  • FIG. 11(B) is a plan view showing the shape of the adhesion portion formed in the sixth modified example.
  • FIG. 12 is a conceptual diagram showing a cutting step and a peeling step performed in a manufacturing method according to the eighth modified example.
  • FIGS. 1 and 2 are conceptual diagrams showing a manufacturing method according to an embodiment in the order of processing.
  • a division layer forming step S1 a fixing part forming step S2, a division step S3, a device forming step S4, a cutting step S5, a peeling step S6, and a singulation step S7 are performed in this order.
  • a division layer forming step S1 a fixing part forming step S2
  • a division step S3 a device forming step S4
  • a cutting step S5 a peeling step S6, and a singulation step S7 are performed in this order.
  • a split layer 111 is formed at a position at a predetermined depth Dt from the surface 11a of the first substrate 11, which is mainly composed of a semiconductor.
  • the first substrate 11 is not particularly limited, but may be, for example, a single crystal semiconductor wafer, and its main component (semiconductor) may be a wide band gap (WBG) material such as GaAs, SiC, GaN, AlN, BN, or diamond.
  • WBG wide band gap
  • the split layer 111 is a layer that enables the semiconductor substrate K having a thickness Td of the predetermined depth Dt to be separated from the first substrate 11, and can be formed by implanting hydrogen ions from the surface 11a of the first substrate 11. According to the method of implanting hydrogen ions, the split layer 111 can be formed at a depth of about 10 ⁇ m or shallower from the surface 11a, and as a result, a semiconductor substrate K having a thin thickness Td can be obtained.
  • the division layer 111 can be formed by irradiating laser light with a focal point at a position at a predetermined depth Dt from the surface 11a. With this method, the focal position can be changed in the depth direction, so that the division layer 111 can be formed at a desired depth.
  • the division layer 111 can be formed at a deeper position (for example, a position at a depth of about 50 to 150 ⁇ m from the surface 11a) than with the method of injecting hydrogen ions, and as a result, a semiconductor substrate K with a large thickness Td can be obtained.
  • the first substrate 11 is divided at the division layer 111 in a division step S3 described below, and as a result, a semiconductor substrate K having a thickness Td corresponding to a predetermined depth Dt is separated from the first substrate 11.
  • a semiconductor substrate K having a thickness Td corresponding to a predetermined depth Dt is separated from the first substrate 11.
  • the second substrate 12 which will become the support, is bonded to the surface 11a of the first substrate 11.
  • the second substrate 12 is not particularly limited, but may be, for example, a polycrystalline semiconductor wafer, and its main component (semiconductor) may be a wide band gap (WBG) material such as GaAs, SiC, GaN, AlN, BN, diamond, etc. Note that, instead of a semiconductor wafer, the second substrate 12 may be a substrate formed of another material (Si, sapphire, quartz, etc.) that is not limited to semiconductors.
  • WBG wide band gap
  • a fixing portion Q for fixing the portion of the first substrate 11 that will become the semiconductor substrate K to the second substrate 12 is formed in an annular shape in an atmosphere at a lower pressure than the predetermined pressure Pt, thereby sealing the inside of the annular shape.
  • the predetermined pressure Pt is the atmospheric pressure used in the division step S3 described below, and is not limited to atmospheric pressure, for example.
  • the metal layer formation step S21 and the laser light irradiation step S22 are carried out in this order.
  • a metal layer 13 is formed on the entire surface 11a of the first substrate 11.
  • the metal layer 13 is formed to a thickness of 1 ⁇ m or less using a film formation method such as a vapor deposition method.
  • the main component of the metal layer 13 can be metals such as Cu, Al, Cr, Ti, Ta, and Au.
  • the first substrate 11 and the second substrate 12 are opposed to each other with the metal layer 13 interposed therebetween.
  • the portion of the metal layer 13 where the fixing portion Q is to be formed (in this embodiment, the portion on the peripheral portion 112 of the first substrate 11; details will be described later (see FIG. 3)) is heated by irradiating the portion with laser light.
  • the first substrate 11 and the second substrate 12 may be sandwiched between quartz plates or the like to increase the degree of adhesion with the portion of the metal layer 13 where the fixing portion Q is to be formed.
  • the metal layer 13 By irradiating the metal layer 13 with laser light in this way, the metal layer 13 can be melted together with the first substrate 11 and the second substrate 12 at the irradiated location of the laser light (the area where the fixing portion Q is to be formed), or the metal that is the main component of the metal layer 13 can be diffused into the first substrate 11 and the second substrate 12.
  • such a fixed portion Q is formed continuously and annularly in an atmosphere with a lower pressure than the predetermined pressure Pt, so that the inside of the annular portion is sealed while maintaining a state of lower pressure than the predetermined pressure Pt.
  • FIG. 3 is a plan view showing the shape of the fixing portion Q formed in this embodiment.
  • the fixing portion Q is formed around the entire periphery of the peripheral portion 112 of the first substrate 11 (specifically, the peripheral portion of the portion of the first substrate 11 that will become the semiconductor substrate K; see also FIG. 1).
  • the first substrate 11 is disk-shaped, and the fixing portion Q is formed in an annular shape along the peripheral portion 112.
  • the shape of the fixing portion Q is not limited to a circular ring shape, and can be appropriately changed to another ring shape (such as a polygonal shape) according to the peripheral shape of the first substrate 11.
  • the metal layer forming step S21 is not limited to forming the metal layer 13 on the entire surface 11a of the first substrate 11, but may form the metal layer 13 only on the region on the peripheral portion 112 of the surface 11a, or may form the metal layer 13 only on the portion of the surface 11a where the fixing portion Q is to be formed.
  • the metal layer 13 may be formed on the surface 12a of the second substrate 12.
  • the metal layer 13 is not limited to being formed on the entire surface 12a of the second substrate 12, but may be formed only on the area of the surface 12a that faces the peripheral portion 112, or may be formed only on the portion of the surface 12a where the fixing portion Q is to be formed.
  • the fixing portion forming step S2 by forming the annular fixing portion Q in an atmosphere lower than the predetermined pressure Pt (e.g., atmospheric pressure), a pressure difference can be generated between the pressure inside the annular region of the fixing portion Q (internal pressure) and the pressure outside the annular region (external pressure) in the atmosphere of the predetermined pressure Pt (the atmosphere used in the division step S3 described later).
  • the predetermined pressure Pt e.g., atmospheric pressure
  • the peripheral portion 112 of the semiconductor substrate K is held by the second substrate 12 by the bonding force of the fixing portion Q, while the portion of the semiconductor substrate K inside the fixing portion Q (the portion where the multiple device regions Rd are provided) can be held by the second substrate 12 by the suction force caused by the pressure difference, and as a result, the semiconductor substrate K can be held by the second substrate 12 with sufficient bonding force.
  • ⁇ Division step S3> In the dividing step S3 (see FIG. 1), the atmospheric pressure is adjusted to a predetermined pressure Pt (e.g., atmospheric pressure). This allows the portion of the first substrate 11 that will become the semiconductor substrate K to be held to the second substrate 12 with sufficient bonding strength (bonding strength by the fixing portion Q and an adhesive force resulting from the pressure difference between the internal and external air pressures). Then, in the dividing step S3, the first substrate 11 is divided at the dividing layer 111 in an atmosphere of the predetermined pressure Pt.
  • a predetermined pressure Pt e.g., atmospheric pressure
  • the semiconductor substrate K which has a thickness Td equal to the depth (predetermined depth Dt) at which the division layer 111 was formed, is separated from the first substrate 11 while still being held by the second substrate 12.
  • the device formation step S4 described below is then performed on this semiconductor substrate K. Meanwhile, the remaining portion 11R of the first substrate 11 other than the semiconductor substrate K (the portion remaining after division) is reused for manufacturing a new semiconductor substrate K and semiconductor device.
  • ⁇ Device formation step S4> In the device formation step S4 (see FIG. 2), at least some of the elements (hereinafter referred to as "elements Gd") that will be included in the semiconductor device are fabricated in each of the device regions Rd (see also FIG. 3) provided in the semiconductor substrate K. Although not particularly limited, in the device formation step S4, elements Gd such as MOSFETs and Schottky diodes can be formed in each device region Rd. Note that, before the elements Gd are formed in the semiconductor substrate K, the surface Ka of the semiconductor substrate K (the surface that appears after division at the division layer 111) may be polished to adjust the smoothness (surface roughness) of the surface Ka to the smoothness required for fabricating the elements Gd in the semiconductor substrate K.
  • Such device formation step S4 is often performed at a high temperature exceeding 1000°C.
  • the expansion coefficient of the semiconductor substrate K is different from that of the second substrate 12.
  • bonding is performed using CMP
  • the device formation step S4 is performed at a high temperature, one of the semiconductor substrate K and the second substrate 12, which has a larger expansion coefficient, will pull the other substrate and expand it more than its expansion coefficient, and conversely, the other substrate will try to hinder the expansion of the other substrate.
  • stress is generated in the semiconductor substrate K and the second substrate 12, and the stress may appear in the semiconductor substrate K or the second substrate 12 as defects such as distortion.
  • the stress generated in the semiconductor substrate K may also cause defects in elements Gd such as MOSFETs and Schottky diodes formed on the semiconductor substrate K.
  • the semiconductor substrate K and the second substrate 12 are not bonded to each other inside the fixing portion Q. Therefore, when the device formation step S4 is performed at high temperature, inside the fixing portion Q, the one of the semiconductor substrate K and the second substrate 12, which has a larger expansion coefficient, can bend independently of the other substrate, and as a result, each of the two substrates can expand by an amount according to its own expansion coefficient. Therefore, stress is unlikely to occur in either the semiconductor substrate K or the second substrate 12, and therefore defects are unlikely to occur in elements Gd such as MOSFETs and Schottky diodes formed on the semiconductor substrate K.
  • elements Gd such as MOSFETs and Schottky diodes formed on the semiconductor substrate K.
  • ⁇ Cutting step S5> In the cutting step S5 (see FIG. 2), the semiconductor substrate K and the second substrate 12 are held on the holding sheet 14 in a position in which the semiconductor substrate K faces the holding sheet 14. In this state, the second substrate 12 and the semiconductor substrate K are cut in an annular shape along the annular fixing portion Q at a position inside the fixing portion Q. Specifically, the second substrate 12 and the semiconductor substrate K are cut so that the cutting line surrounds all of the device regions Rd provided on the semiconductor substrate K.
  • the cutting method used at this time may be a blade dicing method, a plasma etching method, a laser ablation method, or the like.
  • the semiconductor substrate K and the second substrate 12 are not bonded to each other inside the fixing portion Q. Therefore, by cutting inside the annular fixing portion Q, the parts of the semiconductor substrate K and the second substrate 12 inside the cut point are separated from the fixing portion Q. That is, these inner parts are released from the bond by the fixing portion Q. In addition, by cutting, the sealing inside the annular shape by the fixing portion Q is released, and as a result, the suction force generated by the pressure difference between the internal air pressure and the external air pressure disappears. Therefore, the part of the second substrate 12 inside the cut point (hereinafter referred to as the "inner portion 121") is separated from both the fixing portion Q and the semiconductor substrate K. In other words, the inner portion 121 of the second substrate 12 is in a state where it can be easily peeled off from the semiconductor substrate K.
  • ⁇ Removal step S6> In the peeling step S6 (see FIG. 2 ), the inner portion 121 of the second substrate 12 is peeled off from the semiconductor substrate K at the interface between the second substrate 12 and the metal layer 13. This makes it possible to expose the metal layer 13 inside the annular portion 122 remaining after the peeling (after the peeling of the inner portion 121) of the second substrate 12. Thereafter, the exposed metal layer 13 is removed by a method such as polishing or etching, thereby making it possible to expose the semiconductor substrate K inside the annular portion 122.
  • the inner portion 121 of the second substrate 12 can be peeled off from the semiconductor substrate K at the interface between the metal layer 13 and the semiconductor substrate K in the peeling step S6.
  • the semiconductor substrate K can be exposed by peeling off the inner portion 121 of the second substrate 12.
  • the metal layer 13 is formed only on the region on the peripheral portion 112 of the surface 11a of the first substrate 11, or the region facing the peripheral portion 112 of the surface 12a of the second substrate 12 in the metal layer forming step S21, the metal layer 13 is not interposed between the semiconductor substrate K and the second substrate 12 inside the peripheral portion 112, so in this case too, the semiconductor substrate K can be exposed by peeling off the inner portion 121 of the second substrate 12.
  • ⁇ Singulation step S7> the semiconductor substrate K is cut while it is held on the holding sheet 14, thereby singulating the multiple device regions Rd provided on the semiconductor substrate K. Specifically, the semiconductor substrate K is cut along boundary lines Lb (see FIG. 3) that separate the multiple device regions Rd, thereby singulating the multiple device regions Rd.
  • the cutting method used in this process may be a blade dicing method, a plasma etching method, a laser ablation method, or the like. This produces multiple semiconductor devices each having an element Gd such as a MOSFET or a Schottky diode.
  • the first substrate 11 and the second substrate 12 can be firmly bonded to each other by the bonding force of the annular fixing portion Q and the suction force caused by the pressure difference between the air pressure inside the annular region (internal air pressure) and the air pressure outside the annular region (external air pressure). Therefore, even if the first substrate 11 and the second substrate 12 are not bonded to each other over the entire bonding surface as in the conventional method (i.e., even if bonding is not performed using CMP), a bonding force sufficient to hold the semiconductor substrate K separated from the first substrate 11 in the division step S3 on the second substrate 12 can be obtained.
  • the inner portion 121 of the second substrate 12 can be easily peeled off from the semiconductor substrate K by cutting inside the annular fixing portion Q in the cutting step S5, and the peeling of the inner portion 121 can expose the semiconductor substrate K.
  • the manufacturing method of this embodiment in a semiconductor device manufacturing technique that includes a process of forming a semiconductor substrate K using a division layer 111, the semiconductor substrate K can be easily handled after it is formed (after division step S3 is performed in this embodiment).
  • FIG. 4 is a conceptual diagram showing a part of the manufacturing method according to the first modification in the order of processing.
  • the reinforcing layer forming step S8 may be performed after the peeling step S6 and before the singulation step S7.
  • a reinforcing layer 21 of a predetermined thickness Te is formed on the back surface Kb (the surface that was the front surface 11a of the first substrate 11) of the semiconductor substrate K located on the opposite side to the front surface Ka of the semiconductor substrate K facing the holding sheet 14.
  • a reinforcing material for example, a thermoplastic material, etc.
  • a coating method such as a spin coating method or a spray coating method, thereby forming the reinforcing layer 21 of a predetermined thickness Te.
  • the reinforcing material may be an electrically insulating material or a conductive material.
  • the reinforcing layer 21 is also cut at the same positions as the cutting positions of the semiconductor substrate K when viewed in a plan view, thereby singulating each of the multiple device regions Rd provided on the semiconductor substrate K. This makes it possible to manufacture semiconductor devices supported by the reinforcing substrate 21S.
  • FIG. 5(A) is a conceptual diagram showing the division layer forming step S1 executed in the manufacturing method according to the second modification.
  • a substrate having a rounded outer peripheral surface 11d (in other words, a convex outer peripheral surface 11d) may be used as the first substrate 11 as shown in FIG. 5(A).
  • the division step S3 is executed as it is after the division layer 111 is formed, a sharp edge 11e is formed on the outer peripheral edge of the semiconductor substrate K formed in the division step S3 as shown in FIG. 5(B). And, such a sharp edge 11e may damage other members or chip and cause defects in the semiconductor substrate K during the manufacturing process of the semiconductor device.
  • the peripheral portion 112 (the portion with the rounded outer circumferential surface 11d) of the first substrate 11 may be cut off. Then, the first substrate 11 from which the peripheral portion 112 has been cut off may be used as a new first substrate 11, and the process from the fixing portion formation step S2 described above may be carried out.
  • the peripheral portion 112 (the portion with the rounded outer circumferential surface 11d) of the first substrate 11 in this manner, it is possible to prevent the above-mentioned sharp edge 11e from being formed on the outer periphery of the semiconductor substrate K.
  • the dividing layer 111 may be formed after cutting off the peripheral portion 112 (the portion with the rounded outer surface 11d) of the first substrate 11.
  • the inside of the annular portion is sealed while the pressure inside the annular portion remains lower than the predetermined pressure Pt, so that in an atmosphere of the predetermined pressure Pt or an atmosphere of a higher pressure than the predetermined pressure Pt, a pressure difference can be generated between the pressure inside the annular portion of the fixing portion Q (internal pressure) and the pressure outside the annular portion (external pressure), and as a result, an adhesive force due to the pressure difference can be generated between the first substrate 11 and the second substrate 12. Therefore, this adhesive force can adhere the first substrate 11 and the second substrate 12 to each other, or, if a metal layer 13 is interposed between the substrates, the substrate can be adhered to the metal layer 13.
  • the semiconductor substrate K and the second substrate 12 may be subjected to a heat treatment while maintaining the above-mentioned state of adhesion (i.e., in an atmosphere of a predetermined pressure Pt or in an atmosphere of a higher pressure than the predetermined pressure Pt), thereby generating a compound (such as a metal silicide) or an alloy (such as a metal-Si alloy) between the main component (such as a semiconductor) of the first substrate 11 and the second substrate 12 and the metal that is the main component of the metal layer 13 at their interface, and as a result, the semiconductor substrate K and the second substrate 12 may be bonded even in the region inside the bonding portion Q.
  • a compound such as a metal silicide
  • an alloy such as a metal-Si alloy
  • This method of bonding the inner region of the bonding portion Q by utilizing the adhesive force caused by the pressure difference can also be realized when performing heat treatment at a low temperature of 1000°C or less (e.g., 400°C) (e.g., eutectic bonding).
  • a low temperature of 1000°C or less e.g. 400°C
  • the inner region of the bonding portion Q can be bonded without causing a large difference in the amount of expansion.
  • the inner region of the bonding portion Q can be bonded without generating a large stress caused by the difference in expansion coefficient.
  • the method of bonding the inner region of the bonding portion Q by heat treatment at such a low temperature can be used.
  • FIG. 6 is a conceptual diagram showing a part of the manufacturing method according to the fourth modification in the order of processing.
  • FIG. 7 is a plan view showing the shape of the fixing portion Q formed in this modification.
  • the fixing portion Q in the fixing portion forming step S2, for each of the device regions Rd provided in the portion that becomes the semiconductor substrate K of the first substrate 11, the fixing portion Q may be formed in an annular shape around the entire periphery of the peripheral portion of the device region Rd. At this time, the fixing portion Q is formed continuously and annularly in an atmosphere with a lower pressure than the predetermined pressure Pt, so that the inside of the annular portion is sealed while being in a state of a lower pressure than the predetermined pressure Pt.
  • each device region Rd is a rectangle
  • the fixing portion Q is formed in a rectangular ring shape along the peripheral portion.
  • the shape of the fixing portion Q is not limited to a rectangular ring shape, but can be appropriately changed to another ring shape (such as a circle or a polygon) according to the peripheral shape of each device region Rd.
  • the fixing portion Q By forming the fixing portion Q in this way, in an atmosphere of a predetermined atmospheric pressure Pt, a pressure difference can be generated between the atmospheric pressure inside the ring of the fixing portion Q (internal pressure) and the atmospheric pressure outside the ring (external pressure) for each device region Rd. As a result, an adhesion force due to the pressure difference can be generated at multiple locations between the first substrate 11 and the second substrate 12. Therefore, in an atmosphere of a predetermined atmospheric pressure Pt, the first substrate 11 and the second substrate 12 can be firmly bonded by the bonding force of the fixing portion Q and the adhesion force due to the pressure difference between the internal pressure and the external pressure.
  • the semiconductor substrate K and the second substrate 12 are cut at positions between the fixing parts Q formed in each of the two adjacent device regions Rd while held by the holding sheet 14, thereby separating the multiple device regions Rd provided on the semiconductor substrate K.
  • semiconductor devices supported by the support substrate 12S substrate formed by cutting the second substrate 12
  • each semiconductor device is supported by the support substrate 12S in a state where it is firmly bonded by the bonding force of the annular fixing parts Q and the suction force caused by the pressure difference between the air pressure inside the annular region (internal air pressure) and the air pressure outside the annular region (external air pressure).
  • FIGS. 8(A) and 8(B) are a conceptual diagram and a plan view showing a further modification of the manufacturing method of FIGS. 6 and 7 described above.
  • an annular fixing portion Q may also be formed along the periphery 112 of the first substrate 11 (specifically, the periphery of the portion of the first substrate 11 that will become the semiconductor substrate K).
  • the annular fixing portion Q is not limited to the shape shown in FIG. 3 (embodiment) or FIG. 7 (fourth modification), and may have the following shape.
  • FIG 9, 10(A), and 10(B) are plan views showing three examples of the shape of the fixing portion Q formed in the fifth modified example.
  • the device regions Rd may be divided into several groups, and for each group, the fixing portion Q may be formed in a ring shape so as to surround all the device regions Rd in that group.
  • the fixing portion Q is formed to have an independent ring shape for each group.
  • the fixing portion Q is formed by combining a circular portion and a straight portion so that a part of the fixing portion Q can be shared between groups.
  • FIG. 10(A) shows a case where the fixing portion Q is formed by a circular portion formed in a ring shape along the peripheral portion 112 and one straight portion that crosses the inside of the circular portion.
  • the straight portion of the fixing portion Q is shared between the groups, and as a result, two ring-shaped portions that can surround all the device regions Rd in each group are formed in the fixing portion Q.
  • FIG. 10(A) shows a case where the fixing portion Q is formed by a circular portion formed in a ring shape along the peripheral portion 112 and one straight portion that crosses the inside of the circular portion.
  • the straight portion of the fixing portion Q is shared between the groups, and as a result, two ring-shaped portions that can surround all the device regions Rd in each group are formed in the fixing portion Q.
  • FIG. 10(B) shows a case where the fixing portion Q is formed by a circular portion formed in a ring shape along the peripheral portion 112 and two straight portions that cross the inside of the circular portion and intersect with each other (orthogonal in the example of FIG. 10(B)).
  • the straight line portions of the fixing portion Q are shared between the groups, and as a result, the fixing portion Q forms four annular portions for each group that can surround all of the device regions Rd in that group.
  • FIG. 11(A) is a conceptual diagram showing the fixing portion forming step S2 and the cutting step S5 performed in the manufacturing method according to the sixth modification.
  • Fig. 11(B) is a plan view showing the shape of the fixing portion Q formed in the sixth modification.
  • the fixing portion Q may be formed on the boundary line Lb that divides the multiple device regions Rd provided on the first substrate 11.
  • FIG. 10(B) shows a case in which the fixing portion Q is formed by a circular portion formed in an annular shape along the peripheral portion 112 and a plurality of straight line portions that cross the inside of the circular portion through the boundary line Lb to form a lattice.
  • the fixing portion Q is formed on the boundary line Lb of the device region Rd in this manner, in the cutting step S5 (see FIG. 11(A)), the second substrate 12 and the semiconductor substrate K are cut along the boundary line Lb, so that the fixing portion Q can be removed together with the portions of the second substrate 12 and the semiconductor substrate K that are removed during cutting.
  • the method of forming the adhesion portion Q in the adhesion portion formation step S2 is not limited to the method of forming the adhesion portion Q by irradiating the metal layer 13 with laser light, and may be appropriately changed to a method of forming the adhesion portion Q by irradiating the interface between the first substrate 11 and the second substrate 12 while they are in direct contact with each other.
  • FIG. 12 is a conceptual diagram showing a cutting step S5 and a peeling step S6 executed in a manufacturing method according to an eighth modification.
  • the cutting step S5 only the second substrate 12 out of the second substrate 12 and the semiconductor substrate K may be cut annularly along the annular fixing portion Q at a position inside the fixing portion Q. Specifically, only the cutting of the second substrate 12 is executed so that the cutting line surrounds all the device regions Rd provided in the semiconductor substrate K.
  • the inner portion 121 of the second substrate 12 is separated from the fixing portion Q, while the entire semiconductor substrate K remains connected to the fixing portion Q.
  • the entire semiconductor substrate K is joined by the fixing portion Q to the annular portion 122 that remains after peeling of the second substrate 12 (after peeling of the inner portion 121).
  • the annular portion 122 of the second substrate 12 can be used as an annular support to obtain the semiconductor substrate K supported by the support.
  • the shape of the fixed portion Q may be appropriately changed to various shapes other than the annular shape.
  • the fixed portion Q may be formed in the form of a dot or an open line (a line with an end).
  • steps constituting the method for manufacturing a semiconductor device may be partially extracted as the subject of the invention, or each step may be extracted individually.

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PCT/JP2023/043371 2022-12-14 2023-12-05 半導体デバイスの製造方法 Ceased WO2024128057A1 (ja)

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JP2004146461A (ja) * 2002-10-22 2004-05-20 Sumitomo Mitsubishi Silicon Corp 貼り合わせｓｏｉ基板およびその製造方法ならびに半導体装置
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JP2022078625A (ja) * 2020-11-13 2022-05-25 タツモ株式会社 接合装置

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JP2003243334A (ja) * 2002-02-20 2003-08-29 Matsushita Electric Ind Co Ltd 電子デバイスの製造方法および電子デバイス
JP2004146461A (ja) * 2002-10-22 2004-05-20 Sumitomo Mitsubishi Silicon Corp 貼り合わせｓｏｉ基板およびその製造方法ならびに半導体装置
JP2007250576A (ja) 2006-03-13 2007-09-27 Shin Etsu Chem Co Ltd マイクロチップ及びマイクロチップ製造用ｓｏｉ基板
JP2009141249A (ja) * 2007-12-10 2009-06-25 Semiconductor Energy Lab Co Ltd 半導体基板及びその作製方法
JP2012253367A (ja) * 2008-01-24 2012-12-20 Brewer Science Inc デバイスウェーハーをキャリヤー基板に逆に装着する方法
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JP2022078625A (ja) * 2020-11-13 2022-05-25 タツモ株式会社 接合装置

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