WO2024114579A1 - 环珊tfet器件的制备方法 - Google Patents

环珊tfet器件的制备方法 Download PDF

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WO2024114579A1
WO2024114579A1 PCT/CN2023/134341 CN2023134341W WO2024114579A1 WO 2024114579 A1 WO2024114579 A1 WO 2024114579A1 CN 2023134341 W CN2023134341 W CN 2023134341W WO 2024114579 A1 WO2024114579 A1 WO 2024114579A1
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gate
film layer
forming
dummy gate
layer
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PCT/CN2023/134341
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English (en)
French (fr)
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周娜
李俊杰
高建峰
杨涛
李俊峰
罗军
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中国科学院微电子研究所
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Publication of WO2024114579A1 publication Critical patent/WO2024114579A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Definitions

  • the present application relates to the technical field of semiconductor device preparation, and in particular to a method for preparing a ring-shaped TFET device.
  • the existing FinFET device structure in the integrated circuit technology below 5 nanometers faces many challenges.
  • the gate-all-around nanowire device is considered to be one of the key architectures to continue Moore's Law due to its advantages such as better channel electrostatic integrity, leakage current control and one-dimensional carrier ballistic transport.
  • combining the ideal gate-all-around nanowire structure with the mainstream FinFET process to develop the next generation of integrated technology has become one of the key research and development hotspots for the in-depth development of integrated circuits.
  • the gate-all-around devices still face the problem of high power consumption due to the increasing difficulty of continuously reducing the power supply voltage, the increase of device leakage current and the subthreshold swing being limited to 60mV/Dec. If the leakage current of the device in the off state is to be reduced, it can be achieved by reducing the subthreshold swing.
  • the tunneling field effect transistor (TFET) that works by the conduction principle of band-to-band tunneling (BTBT) is used to break the limitation of the subthreshold swing caused by the conduction mechanism of MOSFET using thermal electron emission from the working principle, so that it has extremely small leakage current in the off state.
  • TFET tunneling field effect transistor
  • BTBT band-to-band tunneling
  • the preparation method of the ring-gate TFET device provided in the present application can make the preparation of the TFET device compatible with the preparation process of the ring-gate device, thereby realizing the mass production of the ring-gate TFET devices.
  • the present application provides a method for preparing a Huanshan TFET device, the method comprising:
  • the source and drain regions are prepared in sequence; when preparing the source region, the drain region is protected by a dielectric material, and when preparing the drain region, the source region is protected by a dielectric material;
  • a ring-shaped metal gate is prepared in the ring-shaped gate preparation space to form a ring-shaped gate TFET device.
  • alternately forming one or more channel layers and one or more sacrificial layers on the substrate to form a channel stack includes:
  • a silicon-germanium film layer and a boron-doped silicon film layer are alternately formed by epitaxy, wherein the silicon-germanium film layer is a sacrificial layer and the boron-doped silicon film layer is a channel layer;
  • the channel stack is etched by a dry etching process to form a fin-shaped channel stack extending along a first direction.
  • forming a dummy gate across the channel stack on the substrate comprises:
  • the first film layer is etched to form a dummy gate which has a step with the channel stack along a first direction and crosses the channel stack along a second direction.
  • forming a first spacer on the surface of the dummy gate includes:
  • the second film layer is etched to form a first spacer which is aligned with the side surface of the channel stack along a first direction, surrounds the side surface of the dummy gate and covers the upper surface of the dummy gate.
  • etching the sacrificial layer to form a concave structure on a side surface of the channel stack includes:
  • the exposed sidewalls of the sacrificial layer are etched inwardly to form a concave structure; wherein the etching depth is equal to the thickness of the first sidewall.
  • forming a second sidewall in the concave structure includes:
  • the thickness of the third film layer is not less than the depth of the concave structure
  • the third film layer is etched to form a second sidewall spacer aligned with the channel layer in a first direction.
  • a dielectric material is used to protect the drain region:
  • the second film layer corresponding to the drain region is removed.
  • using a dielectric material to protect the source region includes:
  • the second film layer in the source region is removed.
  • etching the dummy gate and the sacrificial layer to form a ring gate preparation space includes:
  • the sacrificial layer is chemically etched or atomically etched to remove the sacrificial layer and form a space required for the ring gate.
  • preparing a ring-shaped dielectric metal gate in the ring-gate preparation space to form a ring-gate TFET device includes:
  • a ring-shaped dielectric metal gate is formed in the ring-shaped gate preparation space.
  • the dummy gate and the sacrificial layer are matched to provide the preliminary structure of the TFET device.
  • the source and drain are prepared in sequence, and the drain is covered and protected when preparing the source, and the source is covered and protected when preparing the drain, so as to realize the source and drain preparation of the TFET device.
  • a ring gate is provided for the channel layer between the source and the drain.
  • FIG1 is a flow chart of a method for preparing a Huanshan TFET device according to an embodiment of the present application
  • FIG2 is a flow chart of a method for preparing a channel stack according to another embodiment of the present application.
  • FIG. 3 is a flow chart of a method for preparing a dummy gate of a Huanshan TFET device according to another embodiment of the present application;
  • FIG. 4 is a flow chart of preparing a first sidewall in a method for preparing a Huanshan TFET device according to another embodiment of the present application;
  • FIG. 5 is a flow chart of a method for preparing a second sidewall spacer according to another embodiment of the present application.
  • FIG6 is a flow chart of a method for preparing a source electrode of a Huanshan TFET device according to another embodiment of the present application.
  • FIG. 7 is a flow chart of a method for preparing a drain electrode of a Huanshan TFET device according to another embodiment of the present application.
  • FIG. 8 is a flow chart of etching a dummy gate and a sacrificial layer in a method for preparing a Huanshan TFET device according to another embodiment of the present application;
  • FIG. 9 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing a sacrificial layer and a channel layer;
  • FIG10 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing a channel stack;
  • FIG. 11 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing a dummy gate and a first spacer;
  • FIG12 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing an inner concave structure
  • FIG. 13 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing a second sidewall;
  • FIG14 is a structural diagram of a method for preparing a Huanshan TFET device protecting a drain electrode according to another embodiment of the present application.
  • FIG15 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing a source electrode;
  • FIG16 is a structural diagram of a method for preparing a Huanshan TFET device for protecting a source electrode according to another embodiment of the present application.
  • FIG17 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing a drain electrode;
  • FIG18 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after etching a dummy gate;
  • FIG19 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after etching a sacrificial layer;
  • FIG20 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing a dielectric metal gate;
  • FIG. 21 is a structural diagram of a method for preparing a Huanshan TFET device according to another embodiment of the present application after preparing a metal plug.
  • the present application provides a method for preparing a ring-shaped TFET device, as shown in FIG1 , the method comprising:
  • Step 100 alternately forming one or more channel layers and one or more sacrificial layers on a substrate to form a channel stack;
  • the substrate refers to a structure formed by supporting semiconductor devices.
  • the substrate can be, for example, a silicon-on-insulator substrate, or other substrates.
  • the channel layer refers to a material film layer used as a channel after the device is formed, and the sacrificial layer refers to a material film layer that will be removed during the preparation of the device.
  • the channel layer can be formed first in the first layer, or the sacrificial layer can be formed first in the first layer.
  • the channel layer uses a lightly doped n-type silicon film layer to meet the channel layer requirements of the TFET device.
  • Step 200 forming a dummy gate across the channel stack on a substrate, and forming a first spacer on a surface of the dummy gate;
  • a dummy gate refers to a material film layer formed in the area corresponding to the gate, and the material film layer serves as a placeholder to reserve space for the gate.
  • the dummy gate will be removed before preparing the gate, and the space formed after the removal is used to form the gate.
  • a dummy gate across the channel stack means that the extension direction of the dummy gate is perpendicular to the extension direction of the channel stack, and the dummy gate will cover the two opposite sides of the channel stack in its own extension direction, and at the same time, cover the upper surface of the channel stack.
  • Forming a first sidewall on the surface of the dummy gate means forming a first sidewall around the dummy gate, and the first sidewall covers the side surface and upper surface of the dummy gate.
  • Step 300 etching the sacrificial layer to form a concave structure on the side surface of the channel stack, and forming a second spacer in the concave structure;
  • the sidewalls exposed by the sacrificial layer are etched inwardly. After the sacrificial layer is etched, part of the sacrificial layer is removed, and an inward depression will be formed on the side surface of the channel stack corresponding to the position of the sacrificial layer.
  • Forming the second sidewall means filling the concave structure so that the side surface of the channel stack is restored to flatness.
  • the filling material can be one of SiC, Si3N4 and SiON, or a mixture of two or more. Since the position of the sacrificial layer is used for the subsequent preparation of the ring gate, the second sidewall has two functions, one is to limit the size of the ring gate, and the other is to insulate the ring gate from the source and drain.
  • Step 400 sequentially preparing source and drain regions; when preparing the source region, using a dielectric material to protect the drain region, and when preparing the drain region, using a dielectric material to protect the source region;
  • the source and drain of the TFET device since the source and drain of the TFET device have different doping characteristics, the source and drain need to be prepared separately during the preparation of the source and drain.
  • the drain When preparing the source, the drain is covered and protected to prevent the source material from contaminating the drain.
  • the source also needs to be covered and protected to prevent the drain material from contaminating the source.
  • the source and drain will contact the channel layer.
  • Step 500 etching the dummy gate and the sacrificial layer to form a ring gate preparation space
  • the dummy gate and the sacrificial layer occupy the space of the ring gate, the dummy gate and the sacrificial layer need to be removed before preparing the ring gate.
  • the dummy gate and the sacrificial layer have different etching characteristics, they can be removed by etching in batches.
  • Step 600 preparing a ring-shaped dielectric metal gate in the ring-shaped gate preparation space to form a ring-shaped gate TFET device.
  • the space occupied by the sacrificial layer and the dummy gate forms a cavity, which provides space for the preparation of the ring gate. Since the dummy gate and the sacrificial layer form a wrapping structure for the channel layer, the cavity is also formed around the channel layer. After the dielectric metal is formed in the cavity, the dielectric metal will surround the channel layer to form a ring gate.
  • the dielectric layer can be made of high-K materials such as HfO2 , ZrO2 , Al2O3 , etc.
  • the dummy gate and the sacrificial layer are matched to provide the preliminary structure of the TFET device.
  • the source and drain are prepared in sequence, and the drain is covered and protected when preparing the source.
  • the drain is covered and protected.
  • the covering protection realizes the source and drain preparation of the TFET device, and finally, by removing the dummy gate and sacrificial layer and preparing the dielectric metal gate, a ring gate is provided for the channel layer between the source and drain.
  • alternately forming one or more channel layers and one or more sacrificial layers on a substrate to form a channel stack includes:
  • Step 110 alternately forming silicon germanium film layers and boron-doped silicon film layers on a silicon-on-insulator substrate by epitaxy, wherein the silicon germanium film layer is a sacrificial layer and the boron-doped silicon film layer is a channel layer;
  • the silicon film layer has the characteristics of a channel layer and can be used as a channel layer, while the silicon germanium film layer can show a selectivity ratio with the silicon film layer during the etching process, which is more conducive to etching the silicon germanium film layer while retaining the silicon film layer.
  • Step 120 etching the channel stack using a dry etching process to form a fin-shaped channel stack extending along a first direction.
  • the channel stack since a channel stack is formed on the entire surface of the substrate during epitaxial growth, the channel stack needs to be etched to form a fin shape in order to achieve device fabrication.
  • the fin-shaped channel stack is conducive to forming a dummy gate across the channel stack.
  • forming a dummy gate across the channel stack on the substrate includes:
  • Step 210 forming a first film layer on the substrate surface and the channel stack
  • a cover is formed on the substrate and the channel stack, and a conformal structure is formed from the substrate surface to the channel stack surface, thereby covering the sidewalls of the channel stack.
  • Step 220 etching the first film layer according to the pattern shape of the channel stack to form a dummy gate having a step with the channel stack along a first direction and crossing the channel stack along a second direction.
  • the size of the retained portion in the first direction when etching the first film layer, is smaller than the size of the channel stack in the first direction, thereby forming a step from the channel stack to the first film layer; the size of the retained portion in the second direction is larger than the size of the channel stack in the second direction, thereby forming a dummy gate across the channel stack.
  • the axis of the dummy gate in the first direction is aligned with the axis of the channel stack in the first direction
  • the axis of the dummy gate in the second direction is aligned with the axis of the channel stack in the second direction.
  • forming a first spacer on the surface of the dummy gate includes:
  • Step 230 forming a second film layer on the dummy gate, the channel stack and the surface of the substrate, wherein the second film layer has an etching selectivity ratio with the first film layer;
  • the second film layer will cover the dummy gate, the channel stack and the substrate surface and form a conformal structure, thereby also covering the side of the dummy gate and the channel stack.
  • the second film layer has an etching selectivity with the first film layer, and can not damage the second film layer during the etching process of the dummy gate, that is, not damaging the first sidewall, which is conducive to the subsequent formation of the ring gate.
  • Step 240 etching the second film layer to form a first spacer aligned with the side surface of the channel stack along a first direction, surrounding the side surface of the dummy gate and covering the upper surface of the dummy gate.
  • the retained portion when etching the second film layer, is aligned with the side surface of the channel stack in the first direction, so that the side of the channel stack can be exposed, so that the sacrificial layer can be subsequently etched to form a concave structure.
  • the size of the dummy gate in the first direction is smaller than the size of the channel stack in the first direction, after etching is completed, the two sides of the dummy gate perpendicular to the first direction have sufficient thickness to form a sidewall.
  • etching the sacrificial layer to form a concave structure on the side surface of the channel stack includes:
  • the exposed sidewalls of the sacrificial layer are etched inwardly to form a concave structure; wherein the etching depth is equal to the thickness of the first sidewall.
  • the ring gate occupies the space of the dummy gate and the sacrificial layer during its formation, in this embodiment, setting the etching depth equal to the thickness of the first sidewall helps to form a ring gate with consistent size in the first direction.
  • forming a second sidewall in the concave structure includes:
  • Step 310 forming a third film layer, wherein the thickness of the third film layer is not less than the depth of the concave structure
  • the entire device surface is covered as the upper surfaces of the various parts are covered and the conformal structure is formed.
  • the thickness of the third film layer is set to be not less than the depth of the concave structure.
  • Step 320 etching the third film layer to form a Align the second side wall.
  • all portions outside the concave structure are etched away, and only the portion inside the concave structure is retained as the second sidewall.
  • a dielectric material is used to protect the drain region:
  • Step 410 forming a second film layer
  • the source, the drain and the dummy gate are all covered.
  • Step 420 etching the second film layer to expose the upper surface of the substrate corresponding to the source region
  • the second film layer in order to prepare the source electrode, the second film layer needs to be etched to expose the upper surface of the substrate so that the source electrode can contact the channel layer. During the etching process, only the area required for the source electrode preparation can be etched, or the second film layer in the area outside the drain electrode can be completely etched and removed.
  • Step 430 epitaxially forming a source electrode on the exposed upper surface of the substrate by in-situ doping
  • the sidewalls of the channel layer are also exposed.
  • a source electrode is prepared on the substrate so that the source electrode can be in contact with the channel layer.
  • Step 440 removing the second film layer corresponding to the drain region.
  • the drain electrode needs to be prepared later, so the second film layer of the drain electrode needs to be removed.
  • the second film layer since the second film layer will be deposited again in the subsequent drain electrode preparation process, the second film layer corresponding to the drain region may not be removed after the source electrode is prepared.
  • the second film layer of the drain region may be removed after the protective film layer for the source electrode is formed.
  • using a dielectric material to protect the source region includes:
  • Step 450 forming a second film layer
  • the source, the drain and the dummy gate are all covered.
  • Step 460 etching the second film layer to expose the upper surface of the substrate corresponding to the drain region
  • the second film layer in order to prepare the drain electrode, the second film layer needs to be etched to expose the upper surface of the substrate so that the drain electrode can contact the channel layer. During the etching process, only the area required for drain electrode preparation can be etched, or the second film layer outside the drain electrode can be completely etched and removed.
  • Step 470 epitaxially forming a drain electrode on the exposed upper surface of the substrate by in-situ doping
  • the sidewalls of the channel layer are also exposed.
  • a drain is prepared on the substrate so that the drain can be in contact with the channel.
  • Step 480 removing the second film layer in the source region.
  • the second film layer is usually contaminated, and therefore, it is removed to avoid device performance degradation due to contamination.
  • the degree of contamination of the second film layer is within an acceptable range, it can also be retained to reduce the amount used in subsequent film filling.
  • etching the dummy gate and the sacrificial layer to form a ring gate preparation space includes:
  • Step 510 planarizing the device to remove the second film layer on the top of the dummy gate to expose the upper surface of the dummy gate;
  • the top of the dummy gate is covered when the second film layer is formed, at least part of the top of the dummy gate is retained during the etching process.
  • the second film layer covering the top needs to be planarized first, and etching can only be performed after the dummy gate is exposed.
  • Step 520 wet-etching the dummy gate to remove the dummy gate and expose the sacrificial layer
  • wet etching can be used to etch away only the dummy gate without affecting the first spacer and the sacrificial layer.
  • Step 530 chemically etching or atomic layer etching the sacrificial layer to remove the sacrificial layer and form a space required for the ring gate.
  • the sacrificial layer since the sacrificial layer is in the space surrounding the channel layer, there are shielded parts in its structure. In order to smoothly etch the sacrificial layer, chemical etching or atomic layer etching needs to be used.
  • preparing a ring-shaped dielectric metal gate in the ring-gate preparation space to form a ring-gate TFET device includes:
  • a ring-shaped dielectric metal gate is formed in the ring-shaped gate preparation space.
  • the ring gate preparation space is a special-shaped space formed around the channel layer, in order to prepare the dielectric metal gate in the space, it is necessary to adopt atomic layer deposition or vapor deposition.
  • SiGe and boron-doped Si layers are grown in sequence on a SOI (Silicon On Insulator) wafer by epitaxy; wherein the boron-doped Si layer determines the number of subsequent nanowires; and the boron-doped Si layer is at least one layer.
  • the SiGe layer is a sacrificial layer
  • the boron-doped Si layer is a channel layer.
  • a channel stack is formed, and its structure is shown in FIG10 .
  • a false gate is formed by depositing a film layer, such as a polysilicon film layer, and etching the polysilicon film layer.
  • a film layer, such as a silicon dioxide film layer is deposited again, and the silicon dioxide film layer is etched to form a first sidewall, and the structure after the first sidewall is formed is shown in FIG11 .
  • the sacrificial layer is etched to form an inwardly recessed structure, as shown in FIG12 .
  • a second sidewall is formed by depositing a film layer, such as a silicon nitride film layer, and etching the silicon nitride film layer.
  • a film layer such as a silicon nitride film layer
  • etching the silicon nitride film layer is shown in FIG13.
  • an anisotropic etching method with a high selectivity ratio can be used for etching.
  • the film layer on the horizontal plane will be etched away quickly, while the film layer on the vertical plane will be etched away at a slower rate.
  • the device is filled with a dielectric, for example, silicon dioxide can be used for filling.
  • the dielectric is photoetched to expose the source region, and its structure is shown in FIG14.
  • SiGe with B ions is epitaxially doped in the source region by in-situ doping to form a source, and its structure is shown in FIG15.
  • the drain region is photoetched to expose the drain region, and its structure is shown in FIG16.
  • SiGe-P is epitaxially grown in the drain region by in-situ doping to form a drain, as shown in FIG17 .
  • the dielectric in the source region is removed, as shown in FIG18 .
  • the device is filled with dielectric and planarized, for example, by chemical mechanical polishing, to open the silicon dioxide film layer on the top of the dummy gate. Then, the dummy gate is removed by etching, for example, The dummy gate is removed by wet etching. The structure after removing the dummy gate is shown in Figure 18. After completing the above steps, the sacrificial layer is exposed, and the sacrificial layer can be etched at this time.
  • the etching method can be, for example, dry etching, wet atomic layer etching or etching by hydrogen chloride gas reaction.
  • a cavity is formed in the space occupied by the dummy gate and the sacrificial layer, and its structure is shown in Figure 19.
  • a high-K dielectric metal gate is grown in the space where the dummy gate and the sacrificial layer are located, that is, a ring-shaped dielectric metal gate is formed, and its structure is shown in Figure 20.
  • a film layer is formed, such as a silicon dioxide dielectric film layer, and a hole is opened in the dielectric film layer and a metal plug is formed to form the final device.
  • the device structure is shown in Figure 21.

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Abstract

本申请提供一种环珊TFET器件的制备方法，方法包括：在衬底上依次交替形成一个以上的沟道层和一个以上的牺牲层，以形成沟道叠层；在衬底上形成跨沟道叠层的假栅，并在假栅的表面形成第一侧墙；对牺牲层进行刻蚀，以在沟道叠层的侧表面上形成内凹结构，并在内凹结构内形成第二侧墙；依次制备源漏区域；在制备源极区域时，采用介质材料对漏极区域进行保护，在制备漏极区域时，采用介质材料对源极区域进行保护；对假栅和牺牲层进行刻蚀，以形成环栅制备空间；在环栅制备空间内制备环形的金属栅，以形成环栅TFET器件。本申请提供的环珊TFET器件的制备方法，能够使TFET器件的制备能够兼容环栅器件的制备工艺，实现对环栅TFET器件的批量生产。

Description

环珊TFET器件的制备方法
本申请要求于2022年11月30日提交中国专利局、申请号为202211533675.3、发明名称为“环珊TFET器件的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件制备技术领域，尤其涉及一种环珊TFET器件的制备方法。
背景技术
5纳米以下集成电路技术中现有的FinFET器件结构面临诸多挑战。环栅纳米线器件由于具有更好的沟道静电完整性、漏电流控制和载流子一维弹道输运等优势，被认为是延续摩尔定律的关键架构之一。近年来，将理想环栅纳米线结构和主流FinFET工艺结合发展下一代集成技术已成为集成电路深入发展的研发关键热点之一。
尽管这些先进工艺节点下的器件较过去已有显著的性能提升，但由于持续减小电源电压的难度增加、器件泄漏电流的增大及亚阈值摆幅受限于60mV/Dec等因素，环栅器件仍面临着高功耗的问题。若要减小器件在关态下的泄漏电流，可以通过降低亚阈值摆幅来实现，其中采用通过带带隧穿(BTBT)的导通原理工作的隧穿场效应晶体管(TFET)，从工作原理上打破MOSFET采用热电子发射的导通机理带来的亚阈值摆幅上的限制，从而在关态下具有极小的漏电流。然而，如何将TFET器件与主流的环栅纳米线器件工艺兼容进行制作仍然存在极大的挑战。
发明内容
本申请提供的环珊TFET器件的制备方法，能够使TFET器件的制备能够兼容环栅器件的制备工艺，实现对环栅TFET器件的批量生产。
本申请提供一种环珊TFET器件的制备方法，所述方法包括：
在衬底上依次交替形成一个以上的沟道层和一个以上的牺牲层，以形成沟道叠层；
在衬底上形成跨所述沟道叠层的假栅，并在所述假栅的表面形成第一侧墙；
对所述牺牲层进行刻蚀，以在所述沟道叠层的侧表面上形成内凹结构，并在所述内凹结构内形成第二侧墙；
依次制备源漏区域；在制备源极区域时，采用介质材料对漏极区域进行保护，在制备漏极区域时，采用介质材料对源极区域进行保护；
对所述假栅和牺牲层进行刻蚀，以形成环栅制备空间；
在所述环栅制备空间内制备环形的金属栅，以形成环栅TFET器件。
可选地，在衬底上依次交替形成一个以上的沟道层和一个以上的牺牲层，以形成沟道叠层包括：
在绝缘体上硅衬底上采用外延的方式交替形成硅锗膜层和硼掺杂的硅膜层，其中，硅锗膜层为牺牲层，硼掺杂的硅膜层为沟道层；
采用干法刻蚀工艺对所述沟道叠层进行刻蚀，以形成沿第一方向延伸的鳍片形状的沟道叠层。
可选地，在衬底上形成跨所述沟道叠层的假栅包括：
在所述衬底表面和所述沟道叠层上形成第一膜层；
依据所述沟道叠层的图案形状，对所述第一膜层进行刻蚀，以形成沿第一方向与所述沟道叠层具有台阶，沿第二方向跨过所述沟道叠层的假栅。
可选地，在所述假栅的表面形成第一侧墙包括：
在所述假栅、沟道叠层以及衬底表面形成第二膜层，其中，所述第二膜层与所述第一膜层具有刻蚀选择比；
对所述第二膜层进行刻蚀，以形成沿第一方向与所述沟道叠层侧表面对齐，围绕所述假栅侧表面并覆盖所述假栅上表面的第一侧墙。
可选地，对所述牺牲层进行刻蚀，以在所述沟道叠层的侧表面上形成内凹结构包括：
对所述牺牲层暴露的侧壁向内进行刻蚀，以形成内凹结构；其中，刻蚀深度与所述第一侧墙的厚度相等。
可选地，在所述内凹结构内形成第二侧墙包括：
形成第三膜层，所述第三膜层的厚度不小于所述内凹结构的深度；
对所述第三膜层进行刻蚀，以形成在第一方向上与所述沟道层对齐的第二侧墙。
可选地，在制备源极区域时，采用介质材料对漏极区域进行保护：
形成第二膜层；
对所述第二膜层进行刻蚀，以使所述源极区域对应的衬底上表面暴露；
在所述衬底暴露的上表面采用原位掺杂的方式外延形成源极；
对所述漏极区域对应的第二膜层进行去除。
可选地，在制备漏极区域时，采用介质材料对源极区域进行保护包括：
形成第二膜层；
对所述第二膜层进行刻蚀，以使所述漏极区域对应的衬底上表面暴露；
在所述衬底暴露的上表面采用原位掺杂的方式外延形成漏极；
对所述源极区域的第二膜层进行去除。
可选地，对所述假栅和牺牲层进行刻蚀，以形成环栅制备空间包括：
对器件进行平坦化，以去除假栅顶部的第二膜层，暴露所述假栅的上表面；
对所述假栅进行湿法刻蚀，以去除所述假栅，暴露所述牺牲层；
对所述牺牲层进行化学刻蚀或者原子层刻蚀，以去除所述牺牲层，形成环栅所需的空间。
可选地，在所述环栅制备空间内制备环形的介质金属栅，以形成环栅TFET器件包括：
采用原子层沉积或者气相沉积的方式，所述环形栅制备空间内形成环形的介质金属栅。
在本申请提供的技术方案中，通过沟道叠层的设置，将假栅与牺牲层进行配合，提供了TFET器件的前期结构，在制备源漏区域时，通过对源漏的依次制备，并在制备源极时对漏极进行覆盖保护，在制备漏极时对源极进行覆盖保护，实现了TFET器件的源漏制备，最后通过对假栅以及牺牲层的去除和介质金属栅的制备，为源漏之间的沟道层提供了环栅。通过本申请提供的技术方案，能够将TFET器件与环栅器件的生产工艺相兼容，实现环栅TFET器件的批量生产，有效的提高了生产效率。
附图说明
图1为本申请一实施例环珊TFET器件的制备方法的流程图；
图2为本申请另一实施例环珊TFET器件的制备方法制备沟道叠层的流程图；
图3为本申请另一实施例环珊TFET器件的制备方法制备假栅的流程图；
图4为本申请另一实施例环珊TFET器件的制备方法制备第一侧墙的流程图；
图5为本申请另一实施例环珊TFET器件的制备方法制备第二侧墙的流程图；
图6为本申请另一实施例环珊TFET器件的制备方法制备源极的流程图；
图7为本申请另一实施例环珊TFET器件的制备方法制备漏极的流程图；
图8为本申请另一实施例环珊TFET器件的制备方法刻蚀假栅和牺牲层的流程图；
图9为本申请另一实施例环珊TFET器件的制备方法制备牺牲层和沟道层后的结构图；
图10为本申请另一实施例环珊TFET器件的制备方法制备沟道叠层后的结构图；
图11为本申请另一实施例环珊TFET器件的制备方法制备假栅和第一侧墙后的结构图；
图12为本申请另一实施例环珊TFET器件的制备方法制备内凹结构后的结构图；
图13为本申请另一实施例环珊TFET器件的制备方法制备第二侧墙后的结构图；
图14为本申请另一实施例环珊TFET器件的制备方法保护漏极的结构图；
图15为本申请另一实施例环珊TFET器件的制备方法制备源极后的结构图；
图16为本申请另一实施例环珊TFET器件的制备方法保护源极的结构图；
图17为本申请另一实施例环珊TFET器件的制备方法制备漏极后的结构图；
图18为本申请另一实施例环珊TFET器件的制备方法刻蚀假栅后的结构图；
图19为本申请另一实施例环珊TFET器件的制备方法刻蚀牺牲层后的结构图；
图20为本申请另一实施例环珊TFET器件的制备方法制备介质金属栅后的结构图；
图21为本申请另一实施例环珊TFET器件的制备方法制备金属塞后的结构图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种环珊TFET器件的制备方法，如图1所示，所述方法包括：
步骤100，在衬底上依次交替形成一个以上的沟道层和一个以上的牺牲层，以形成沟道叠层；
在一些实施例中，衬底是指承载半导体器件形成的结构。在本实施方式中，衬底例如可以采用绝缘体上硅衬底，也可以采用其他衬底。沟道层是指在形成器件后，作为沟道使用的材料膜层，牺牲层是指在制备器件的过程中会被去除的材料膜层。在本步骤中，可以采用第一层首先形成沟道层的方式，也可以采用第一层首先形成牺牲层的方式。在本实施方式中，沟道层采用轻掺杂的n型硅膜层，以满足TFET器件的沟道层要求。
步骤200，在衬底上形成跨所述沟道叠层的假栅，并在所述假栅的表面形成第一侧墙；
在一些实施例中，假栅是指在栅极对应的区域形成的材料膜层，该材料膜层起到占位的作用，用来为栅极预留空间位置。在后续的制备工艺中，制备栅极前，将会对假栅进行去除，去除后的形成的空间用来形成栅极。跨所述沟道叠层的假栅是指假栅的延伸方向与沟道叠层的延伸方向垂直，并且，假栅将在其自身的延伸方向上对沟道叠层的两个相对侧面进行覆盖，同时，对沟道叠层的上表面进行覆盖。对所述假栅的表面形成第一侧墙是指围绕所述假栅形成第一侧墙，第一侧墙覆盖假栅的侧表面及上表面。
步骤300，对所述牺牲层进行刻蚀，以在所述沟道叠层的侧表面上形成内凹结构，并在所述内凹结构内形成第二侧墙；
在一些实施例中，对牺牲层进行刻蚀的过程中，由牺牲层暴露的侧壁向内刻蚀。在对所述牺牲层进行刻蚀之后，去除了部分牺牲层，在沟道叠层的侧表面对应牺牲层的位置将形成向内的凹陷。形成第二侧墙是指对内凹结构进行填充，以使沟道叠层的侧表面重新恢复平整。填充的材料可以采用SiC、Si3N4以及SiON中的其中一种或者两种以上的混合。由于牺牲层的位置是用于在后续制备环栅的，因此，第二侧墙具有两个作用，其一为限制环栅的尺寸，其二是将环栅与源漏进行绝缘。
步骤400，依次制备源漏区域；在制备源极区域时，采用介质材料对漏极区域进行保护，在制备漏极区域时，采用介质材料对源极区域进行保护；
在一些实施例中，由于TFET器件的源极和漏极掺杂特性不同，因此，在制备源漏的过程中，需要对源漏分别进行制备，在制备源极时，对漏极进行覆盖保护，以免源极材料对漏极产生污染，同理，在制备漏极时，也需要对源极进行覆盖保护，以免漏极材料对源极产生污染。在制备源漏的过程中，由于沟道层的侧面是裸露的，因此，源漏将与沟道层进行接触。
步骤500，对所述假栅和牺牲层进行刻蚀，以形成环栅制备空间；
在一些实施例中，由于假栅和牺牲层占据了环栅的空间，因此，在制备环栅之前，需要对假栅和牺牲层进行去除，在去除的过程中，由于假栅和牺牲层具有不同的刻蚀特性，因此可以采用分次刻蚀的方式进行去除。
步骤600，在所述环栅制备空间内制备环形的介质金属栅，以形成环栅TFET器件。
在一些实施例中，由于牺牲层和假栅去除后，牺牲层和假栅所占的空间形成了空腔，为环栅的制备提供了空间。由于假栅和牺牲层对沟道层形成了包裹的结构，因此，空腔也是环绕沟道层形成的，在空腔中形成介质金属后，介质金属会环绕沟道层形成环栅。在一些实施例中，介质层可以选用高K材料如HfO2，ZrO2，Al2O3等。
在本申请实施例提供的技术方案中，通过沟道叠层的设置，将假栅与牺牲层进行配合，提供了TFET器件的前期结构，在制备源漏区域时，通过对源漏的依次制备，并在制备源极时对漏极进行覆盖保护，在制备漏极时对源极进行 覆盖保护，实现了TFET器件的源漏制备，最后通过对假栅以及牺牲层的去除和介质金属栅的制备，为源漏之间的沟道层提供了环栅。通过本申请提供的技术方案，能够将TFET器件与环栅器件的生产工艺相兼容，实现环栅TFET器件的批量生产，有效的提高了生产效率。
作为一种可选的实施方式，如图2所示，在衬底上依次交替形成一个以上的沟道层和一个以上的牺牲层，以形成沟道叠层包括：
步骤110，在绝缘体上硅衬底上采用外延的方式交替形成硅锗膜层和硼掺杂的硅膜层，其中，硅锗膜层为牺牲层，硼掺杂的硅膜层为沟道层；
在一些实施例中，硅膜层具备沟道层的特性，可以用来作为沟道层使用，而硅锗膜层则在刻蚀过程中能够与硅膜层表现出选择比，更有利于在刻蚀过程中将硅锗膜层刻蚀，而将硅膜层保留。
步骤120，采用干法刻蚀工艺对所述沟道叠层进行刻蚀，以形成沿第一方向延伸的鳍片形状的沟道叠层。
在一些实施例中，由于在外延生长的过程中，会在衬底的整个表面上形成沟道叠层，为了实现器件的制备，需要对沟道叠层进行刻蚀形成鳍片形状。鳍片形状的沟道叠层有利于在形成跨沟道叠层的假栅形成。
作为一种可选的实施方式，如图3所示，在衬底上形成跨所述沟道叠层的假栅包括：
步骤210，在所述衬底表面和所述沟道叠层上形成第一膜层；
在一些实施例中，在形成第一膜层时，会对衬底和沟道叠层上形成覆盖，并且，会形成由衬底表面到沟道叠层表面的随形结构，从而，将沟道叠层的侧壁进行覆盖。
步骤220，依据所述沟道叠层的图案形状，对所述第一膜层进行刻蚀，以形成沿第一方向与所述沟道叠层具有台阶，沿第二方向跨过所述沟道叠层的假栅。
在一些实施例中，在对第一膜层进行刻蚀时，保留的部分在第一方向上的尺寸小于所述沟道叠层在第一方向上的尺寸，从而，形成由沟道叠层到第一膜层的台阶；保留的部分在第二方向上的尺寸大于所述沟道叠层在第二方向上的尺寸，从而，形成跨沟道叠层的假栅。假栅在第一方向的轴线与沟道叠层在第一方向的轴线对齐，假栅在第二方向的轴线与沟道叠层在第二方向轴线对齐。
作为一种可选的实施方式，如图4所示，在所述假栅的表面形成第一侧墙包括：
步骤230，在所述假栅、沟道叠层以及衬底表面形成第二膜层，其中，所述第二膜层与所述第一膜层具有刻蚀选择比；
在一些实施例中，第二膜层在形成的过程中，会对假栅、沟道叠层以及衬底表面覆盖并形成随形结构，从而，会对假栅以及沟道叠层的侧面也形成覆盖。第二膜层与第一膜层具有刻蚀选择比，能够在刻蚀假栅的过程中不损伤第二膜层，即，不损坏第一侧墙，有利于后续的环栅形成。
步骤240，对所述第二膜层进行刻蚀，以形成沿第一方向与所述沟道叠层侧表面对齐，围绕所述假栅侧表面并覆盖所述假栅上表面的第一侧墙。
在一些实施例中，在对第二膜层进行刻蚀时，保留的部分在第一方向上与沟道叠层的侧表面对齐，从而，能够将沟道叠层的侧面进行暴露，这样才能够在后续对牺牲层进行刻蚀形成内凹结构。并且，由于假栅在第一方向上的尺寸小于沟道叠层在第一方向上的尺寸，在刻蚀完成后，在假栅垂直于第一方向的两个侧面具有足够的厚度形成侧墙。
作为一种可选的实施方式，对所述牺牲层进行刻蚀，以在所述沟道叠层的侧表面上形成内凹结构包括：
对所述牺牲层暴露的侧壁向内进行刻蚀，以形成内凹结构；其中，刻蚀深度与所述第一侧墙的厚度相等。
在一些实施例中，由于环栅在形成的过程中，是占用了假栅以及牺牲层的空间形成的，因此，在本实施方式中，将刻蚀深度设置为与第一侧墙的厚度相等，有助于形成在第一方向上尺寸一致的环栅。
作为一种可选的实施方式，如图5所示，在所述内凹结构内形成第二侧墙包括：
步骤310，形成第三膜层，所述第三膜层的厚度不小于所述内凹结构的深度；
在一些实施例中，在形成第三膜层的过程中，随着对各个部分的上表面的覆盖以及随形结构的形成，将对整个器件的表面进行覆盖。为了将内凹结构填满，将第三膜层的厚度设置为不小于内凹结构的深度。
步骤320，对所述第三膜层进行刻蚀，以形成在第一方向上与所述沟道层 对齐的第二侧墙。
在一些实施例中，对第三膜层进行刻蚀的过程中，会将内凹结构之外的部分全部刻蚀去掉，仅保留内凹结构内的部分作为第二侧墙。
作为一种可选的实施方式，如图6所示，在制备源极区域时，采用介质材料对漏极区域进行保护：
步骤410，形成第二膜层；
在一些实施例中，由于在形成第二膜层时，会将源极、漏极以及假栅全部覆盖。
步骤420，对所述第二膜层进行刻蚀，以使所述源极区域对应的衬底上表面暴露；
在一些实施例中，为了制备源极，需要将第二膜层进行刻蚀，使衬底上表面暴露出来，这样才能够使源极与沟道层进行接触。在刻蚀的过程中，可以仅刻蚀源极制备所需要的区域，也可以将漏极之外的区域的第二膜层全部刻蚀去除。
步骤430，在所述衬底暴露的上表面采用原位掺杂的方式外延形成源极；
在一些实施例中，在衬底暴露以后，沟道层的侧壁也会暴露出来，此时，在衬底上进行源极的制备，能够使源极与沟道层进行接触。
步骤440，对所述漏极区域对应的第二膜层进行去除。
在一些实施例中，在源极制备完成以后，由于后续还需要制备漏极，因此，需要将漏极的第二膜层进行去除。当然，由于后续的漏极制备过程中还会再次沉积第二膜层，也可以在源极制备完成后不去除漏极区域对应的第二膜层，而在漏极制备过程中，形成对源极的保护膜层之后一并进行漏极区域的第二膜层的去除。
作为一种可选的实施方式，如图7所示，在制备漏极区域时，采用介质材料对源极区域进行保护包括：
步骤450，形成第二膜层；
在一些实施例中，由于在形成第二膜层时，会将源极、漏极以及假栅全部覆盖。
步骤460，对所述第二膜层进行刻蚀，以使所述漏极区域对应的衬底上表面暴露；
在一些实施例中，为了制备漏极，需要将第二膜层进行刻蚀，使衬底上表面暴露出来，这样才能够使漏极与沟道层进行接触。在刻蚀的过程中，可以仅刻蚀漏极制备所需要的区域，也可以将漏极之外的区域的第二膜层全部刻蚀去除。
步骤470，在所述衬底暴露的上表面采用原位掺杂的方式外延形成漏极；
在一些实施例中，在衬底暴露以后，沟道层的侧壁也会暴露出来，此时，在衬底上进行漏极的制备，能够使漏极与沟道进行接触。
步骤480，对所述源极区域的第二膜层进行去除。
在一些实施例中，在漏极制备完成后，由于第二膜层是对源极进行保护的，因此，第二膜层通常会被污染，因此，会对其进行去除，以避免由于污染导致的器件性能下降。当然，当漏极制备的过程中，如果对第二膜层的污染程度在可接受范围之内，也可以对其进行保留，以减少后续膜层填充时的用量。
作为一种可选的实施方式，如图8所示，对所述假栅和牺牲层进行刻蚀，以形成环栅制备空间包括：
步骤510，对器件进行平坦化，以去除假栅顶部的第二膜层，暴露所述假栅的上表面；
在一些实施例中，由于在对第二膜层在形成时，覆盖了假栅的顶部，在刻蚀的过程中，假栅顶部的部分也至少有部分被保留下来，在对假栅进行刻蚀之前，需要首先对顶部覆盖的第二膜层进行平坦化，将假栅暴露出来之后，才能够进行刻蚀。
步骤520，对所述假栅进行湿法刻蚀，以去除所述假栅，暴露所述牺牲层；
在一些实施例中，由于假栅与第一侧墙和牺牲层均具有不同的刻蚀特性，因此，采用湿法刻蚀能够在刻蚀过程中仅将假栅刻蚀去除，而不会影响第一侧墙和牺牲层。
步骤530，对所述牺牲层进行化学刻蚀或者原子层刻蚀，以去除所述牺牲层，形成环栅所需的空间。
在一些实施例中，由于牺牲层处于环绕沟道层的空间内，其结构存在被遮挡的部分，为了顺利的刻蚀牺牲层，需要采用化学刻蚀或者原子层刻蚀。
作为一种可选的实施方式，在所述环栅制备空间内制备环形的介质金属栅，以形成环栅TFET器件包括：
采用原子层沉积或者气相沉积的方式，所述环形栅制备空间内形成环形的介质金属栅。
在一些实施例中，由于环栅制备空间是一个环绕沟道层形成的异形空间，为了实现在该空间内制备介质金属栅，需要采用原子层沉积或者气相沉积的方式来实现。
如图9-18所示，提供了一种示例性的实施方式，对本申请提供的技术方案予以说明：
首先，在SOI(Silicon On Insulator，绝缘层上的硅)片上通过外延方式依次生长SiGe，掺杂硼的Si层；其中，掺杂硼的Si层决定了后续纳米线根数；掺杂硼的Si层至少为一层。在本实施方式中，SiGe层为牺牲层，掺杂硼的Si层为沟道层。形成叠层之后，其结构如图9所示。为了将叠层的形状制备为符合器件要求的形状，需要对叠层进行光刻和刻蚀，刻蚀的方式例如可以采用干法刻蚀。刻蚀完成后，形成沟道叠层，其结构如图10所示。通过沉积膜层，例如多晶硅膜层，以及对多晶硅膜层的刻蚀，形成假栅。再次沉积膜层，例如二氧化硅膜层，以及对二氧化硅膜层的刻蚀，形成第一侧墙，形成第一侧墙后的结构如图11所示。在形成第一侧墙之后，对牺牲层进行刻蚀，形成向内的凹陷结构，如图12所示。在形成凹陷结构之后，通过沉积膜层，例如氮化硅膜层，以及对氮化硅膜层的刻蚀，形成第二侧墙，形成第二侧墙之后的结构如图13所示。在侧墙的形成过程中，可以采用高选择比的各向异性刻蚀方式进行刻蚀，在刻蚀的过程中，水平平面上的膜层会被快速刻蚀掉，而竖直平面上的膜层将以较慢的速率被刻蚀掉。在形成第二侧墙之后，对器件进行介质填充，例如可以采用二氧化硅进行填充，填充完成后，对介质进行光刻刻蚀，暴露出源极区域，其结构如图14所示。在暴露出源极区域之后，在源极区域通过原位掺杂方式外延掺杂B离子的SiGe，形成源极，其结构如图15所示。采用与源极的形成方式类似的方式，对器件进行介质填充后，对漏极区域进行光刻刻蚀，暴露出漏极区域，其结构如图16所示。在暴露出漏极区域之后，在漏极区域通过原位掺杂方式外延SiGe-P形成漏极，其结构如图17所示。在形成漏极后，对源极区域的介质进行去除，其结构如图18所示。在形成源漏之后，对器件进行介质填充并平坦化，例如采用化学机械研磨的方式进行平坦化，打开假栅顶部的二氧化硅膜层。再采用刻蚀的方式对假栅进行去除，例如可以采 用湿法刻蚀的方式对假栅进行去除。去除假栅后的结构如图18所示。在完成上述的步骤之后，牺牲层被暴露出来，此时可以对牺牲层进行刻蚀，刻蚀方式例如可以为干法刻蚀、湿法原子层刻蚀或者氯化氢气体反应的方式进行刻蚀。刻蚀完成后，假栅和牺牲层所占用的空间形成空腔，其结构如图19所示。再在假栅和牺牲层所在空间内生长高K介质金属栅，即形成环形介质金属栅，其结构如图20所示。完成上述的步骤之后，再形成膜层，例如二氧化硅介质膜层，对介质膜层开孔再形成金属塞，即可形成最终的器件。器件结构如图21所示。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 一种环珊TFET器件的制备方法，其特征在于，所述方法包括：
    在衬底上依次交替形成一个以上的沟道层和一个以上的牺牲层，以形成沟道叠层；
    在所述衬底上形成跨所述沟道叠层的假栅，并在所述假栅的表面形成第一侧墙；
    对所述牺牲层进行刻蚀，以在所述沟道叠层的侧表面上形成内凹结构，并在所述内凹结构内形成第二侧墙；
    依次制备源漏区域；在制备源极区域时，采用介质材料对漏极区域进行保护，在制备漏极区域时，采用介质材料对源极区域进行保护；
    对所述假栅和所述牺牲层进行刻蚀，以形成环栅制备空间；
    在所述环栅制备空间内制备环形的介质金属栅，以形成环栅TFET器件。
  2. 根据权利要求1所述的方法，其特征在于，在所述衬底上依次交替形成一个以上的所述沟道层和一个以上的所述牺牲层，以形成所述沟道叠层包括：
    在绝缘体上硅衬底上采用外延的方式交替形成硅锗膜层和硼掺杂的硅膜层，其中，所述硅锗膜层为所述牺牲层，所述硼掺杂的硅膜层为所述沟道层；
    采用干法刻蚀工艺对所述沟道叠层进行刻蚀，以形成沿第一方向延伸的鳍片形状的沟道叠层。
  3. 根据权利要求1所述的方法，其特征在于，在所述衬底上形成跨所述沟道叠层的假栅包括：
    在所述衬底表面和所述沟道叠层上形成第一膜层；
    依据所述沟道叠层的图案形状，对所述第一膜层进行刻蚀，以形成沿第一方向与所述沟道叠层具有台阶，沿第二方向跨过所述沟道叠层的假栅。
  4. 根据权利要求3所述的方法，其特征在于，在所述假栅的表面形成所述第一侧墙包括：
    在所述假栅、沟道叠层以及衬底表面形成第二膜层，其中，所述第二膜层与所述第一膜层具有刻蚀选择比；
    对所述第二膜层进行刻蚀，以形成沿所述第一方向与所述沟道叠层侧表面对齐，围绕所述假栅侧表面并覆盖所述假栅上表面的第一侧墙。
  5. 根据权利要求1所述的方法，其特征在于，对所述牺牲层进行刻蚀，以在所述沟道叠层的侧表面上形成所述内凹结构包括：
    对所述牺牲层暴露的侧壁向内进行刻蚀，以形成所述内凹结构；其中，刻蚀深度与所述第一侧墙的厚度相等。
  6. 根据权利要求1所述的方法，其特征在于，在所述内凹结构内形成所述第二侧墙包括：
    形成第三膜层，所述第三膜层的厚度不小于所述内凹结构的深度；
    对所述第三膜层进行刻蚀，以形成在第一方向上与所述沟道层对齐的第二侧墙。
  7. 根据权利要求1所述的方法，其特征在于，在制备源极区域时，采用介质材料对漏极区域进行保护：
    形成第二膜层；
    对所述第二膜层进行刻蚀，以使所述源极区域对应的衬底上表面暴露；
    在所述衬底暴露的上表面采用原位掺杂的方式外延形成源极；
    对所述漏极区域对应的第二膜层进行去除。
  8. 根据权利要求7所述的方法，其特征在于，在制备漏极区域时，采用介质材料对源极区域进行保护包括：
    形成第二膜层；
    对所述第二膜层进行刻蚀，以使所述漏极区域对应的衬底上表面暴露；
    在所述衬底暴露的上表面采用原位掺杂的方式外延形成漏极；
    对所述源极区域的第二膜层进行去除。
  9. 根据权利要求1所述的方法，其特征在于，对所述假栅和牺牲层进行刻蚀，以形成环栅制备空间包括：
    对器件进行平坦化，以去除所述假栅顶部的第二膜层，暴露所述假栅的上表面；
    对所述假栅进行湿法刻蚀，以去除所述假栅，暴露所述牺牲层；
    对所述牺牲层进行化学刻蚀或者原子层刻蚀，以去除所述牺牲层，形成环栅所需的空间。
  10. 根据权利要求1所述的方法，其特征在于，在所述环栅制备空间内制备环形的介质金属栅，以形成环栅TFET器件包括：
    采用原子层沉积或者气相沉积的方式，所述环形栅制备空间内形成环形的介质金属栅。
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CN106784001A (zh) * 2016-11-21 2017-05-31 华为技术有限公司 一种场效应晶体管及其制作方法
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KR102459732B1 (ko) * 2021-05-13 2022-10-27 (재)한국나노기술원 게이트 올 어라운드 채널을 갖는 반도체 소자의 제조 방법
CN116072542A (zh) * 2022-11-30 2023-05-05 中国科学院微电子研究所 环珊tfet器件的制备方法

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