WO2024113775A1 - 集成电路及电子设备 - Google Patents

集成电路及电子设备 Download PDF

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Publication number
WO2024113775A1
WO2024113775A1 PCT/CN2023/101325 CN2023101325W WO2024113775A1 WO 2024113775 A1 WO2024113775 A1 WO 2024113775A1 CN 2023101325 W CN2023101325 W CN 2023101325W WO 2024113775 A1 WO2024113775 A1 WO 2024113775A1
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Prior art keywords
cells
standard cell
standard
cell
row
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PCT/CN2023/101325
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English (en)
French (fr)
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WO2024113775A9 (zh
Inventor
陈志锋
陈赞锋
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华为技术有限公司
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Publication of WO2024113775A1 publication Critical patent/WO2024113775A1/zh
Publication of WO2024113775A9 publication Critical patent/WO2024113775A9/zh

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  • the present application relates to the field of semiconductor technology, and in particular to an integrated circuit and an electronic device.
  • the standard cell library includes layout library, symbol library, circuit logic library, etc., and is the basic part of the back-end design process of integrated circuit chips.
  • the standard cells can be divided into three categories according to the isolation type between standard cells (stand-cell, STC): double diffusion break (DDB) standard cell, single diffusion break (SDB) standard cell and mixed diffusion break (MDB) standard cell.
  • DDB double diffusion break
  • SDB single diffusion break
  • MDB mixed diffusion break
  • the DDB standard cell has a lower preparation cost, the SDB standard cell has a smaller design area, and the MDB standard cell has better performance.
  • the three types of standard cells have their own advantages. How to make different types of standard cells compatible in the same integrated circuit has become a technical problem that technicians in this field need to solve.
  • Embodiments of the present application provide an integrated circuit and an electronic device, which are used to achieve compatibility of different types of standard cells in the same integrated circuit.
  • an integrated circuit which may specifically include: a plurality of first standard cells, a plurality of second standard cells, a plurality of first pins, and a plurality of second pins.
  • the first standard cell may be a single diffusion break standard cell (SDB)
  • the second standard cell may be a mixed diffusion break standard cell (MDB) or a double diffusion break standard cell (DDB).
  • the second standard cell may be an SDB
  • the first standard cell may be an MDB or a DDB.
  • MDB and DDB may exist at the same time, or only MDB or DDB may exist, which is not limited here.
  • a plurality of first standard cells and a plurality of second standard cells are arranged in a plurality of standard cell rows extending along a first direction (also referred to as a row direction or a horizontal direction) and arranged along a second direction (also referred to as a column direction or a vertical direction).
  • Each first standard cell occupies a positive integer number of first lattices among a plurality of first lattices closely arranged along the first direction, and the number of first lattices occupied by each first standard cell can be adjusted according to actual design requirements, for example, one first standard cell can occupy three first lattices, and another first standard cell can occupy five first lattices, which are not exhaustively listed here;
  • the second standard cell occupies a positive integer number of second lattices among a plurality of second lattices closely arranged along the first direction, and the number of second lattices occupied by each second standard cell can be adjusted according to actual design requirements, for example, one second standard cell can occupy two second lattices, and another second standard cell can occupy four second lattices, which are not exhaustively listed here.
  • the width of the first cell and the second cell in the first direction needs to be an integer multiple of the contact polysilicon pitch (CPP).
  • the width of the first cell and the second cell in the first direction can be the same, and further can be equal to one CPP, in which case the first cell and the second cell are both the smallest distinguishable cell of the process.
  • the width of the first cell in the first direction can be equal to one CPP
  • the width of the second cell in the first direction can be equal to two or more CPPs, in which case the first cell is the smallest distinguishable cell of the process.
  • the width of the first cell in the first direction can be equal to two or more CPPs
  • the width of the second cell in the first direction can be equal to two or more CPPs
  • the width of the first cell and the second cell in the first direction can be the same number of CPPs, or different numbers of CPPs.
  • the following is an example in which the width of the first cell and the second cell in the first direction is equal to one CPP.
  • the closely arranged multiple first lattices and the closely arranged multiple second lattices need to be staggered in the first direction by a non-integer number of first lattices, so that the first standard cell placed on the first lattice and the second standard cell placed on the second lattice can maintain a non-integer number of CPPs staggered in the first direction, that is, the first standard cell and the second standard cell will not be aligned in the first direction (in this case, the first standard cell and the second standard cell need to be located in different standard cell rows), nor will they be staggered by an integer number of CPPs (in this case, the first standard cell and the second standard cell can be located in different standard cell rows or in the same standard cell row).
  • the closely arranged multiple first lattices and the closely arranged multiple second lattices can be staggered in the first direction by 0.5 of the first lattice, so that the first standard cell and the second standard cell can be staggered by 0.5 of the first lattice.
  • the two standard cells can maintain a relationship of staggering an odd number of 0.5 CPPs in the first direction, that is, the first standard cell and the second standard cell can be staggered by 0.5 CPPs in the first direction, or can be staggered by 1.5 CPPs, or can be staggered by 2.5 CPPs, which are not exhaustively listed here.
  • the following is an example of a distance of 0.5 first cells staggered in the first direction between a plurality of closely arranged first cells and a plurality of closely arranged second cells. It is worth noting that when determining the distance staggered between the first cell and the second cell in the first direction, the boundary of the first cell and the second cell on the same side can be used as a reference for comparison, for example, the left boundary of the first cell and the second cell can be used as a reference for comparison.
  • the boundary of the same side of the first standard cell and the second standard cell can be used as a reference for comparison, for example, the left boundary of the first standard cell and the second standard cell can be used as a reference for comparison.
  • a plurality of first pins and a plurality of second pins extend along the second direction, the first pin is located above the first standard cell and coupled to the first standard cell, and the second pin is located above the second standard cell and coupled to the second standard cell.
  • the routing track spacing: CPP can be 1:1, or 3:2 or 4:3, which are not exhaustive here.
  • the routing track can have different offsets relative to the boundaries of the first grid and the second grid, for example, the boundary of the second grid is aligned with the routing track, and the boundary of the first grid is offset by 0.5 CPP from the routing track, so that the first pin coupled to the first standard cell and the second pin coupled to the second standard cell can be arranged on the routing track.
  • the integrated circuit provided in the embodiment of the present application can create multiple types of sites in the same design during layout planning and design, that is, a plurality of closely arranged first sites and a plurality of closely arranged second sites can be simultaneously created in the same design, the first sites can only be used to place first standard cells, and the second sites can only be used to place second standard cells, and the closely arranged first sites and the closely arranged second sites are staggered in the first direction by a non-integer number of first sites, so that the first standard cells and the second standard cells can be mixed in the same design.
  • the position of the standard cell row in which the first standard cell and the second standard cell can be arranged can be determined according to the placement position relationship between the multiple closely arranged first cells and the multiple closely arranged second cells.
  • the standard cell row in which only the first standard cell can be placed in the multiple standard cell rows can be called the first standard cell row
  • the standard cell row in which only the second standard cell can be placed in the multiple standard cell rows can be called the second standard cell row
  • the standard cell row in which the first standard cell row and the second standard cell can be placed at the same time in the multiple standard cell rows can be called the third standard cell row
  • only the first standard cell or the second standard cell can be placed in one or more third standard cell rows.
  • the difference between the first standard cell row, the second standard cell row and the third standard cell row is that: the first standard cell row is divided into a plurality of closely arranged first cells along the first direction; the second standard cell row is divided into a plurality of closely arranged second cells along the first direction; the third standard cell row is divided into a plurality of closely arranged first cells along the first direction and a plurality of closely arranged second cells along the first direction, and the first cells and the second cells in the third standard cell row are overlapped. Furthermore, in the first direction, the multiple closely arranged first grids are staggered with the multiple closely arranged second grids by a distance less than one first grid.
  • multiple standard cell rows can be composed of a first standard cell row and a second standard cell row, or, multiple standard cell rows can be composed of a first standard cell row, a second standard cell row and a third standard cell row, or, multiple standard cell rows can be composed of a first standard cell row and a third standard cell row, or, multiple standard cell rows can be composed of a second standard cell row and a third standard cell row, or, multiple standard cell rows can be composed of only a third standard cell row.
  • the above-mentioned several configuration methods of multiple standard cell rows can all support the mixing of the first standard cell and the second standard cell in the same design.
  • the height of the first grid position and the second grid position in the second direction can be the same or different. The following is a detailed description through specific embodiments.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the plurality of standard cell rows specifically include a plurality of first standard cell rows and a plurality of second standard cell rows, wherein only the first standard cell is placed in the first standard cell row, and only the second standard cell is placed in the second standard cell row.
  • the first standard cell row is divided into a plurality of first cells closely arranged along the first direction
  • the second standard cell row is divided into a plurality of second cells closely arranged along the first direction.
  • the width of the first cell and the second cell in the first direction is the same and equal to one CPP, and the height of the first cell and the second cell in the second direction is the same.
  • the first cells in different first standard cell rows are aligned, and the second cells in different second standard cell rows are aligned. In the first direction, the first cells in the first standard cell row and the second cells in the second standard cell row are staggered by a distance of 0.5 of the first cells.
  • every two first standard cell rows and every two second standard cell rows are used as the minimum cycle unit for repeated arrangement. This is not a limitation of the actual layout planning design.
  • a first standard cell may occupy a plurality of first cells in a row of first standard cells, or, according to the actual situation, According to actual design requirements, a first standard cell may also occupy multiple first cells in multiple rows of first standard cells.
  • a second standard cell may occupy multiple second cells in one row of second standard cells, or, according to actual design requirements, a second standard cell may also occupy multiple second cells in multiple rows of second standard cells.
  • one or more first standard cells may be placed in the same first standard cell row, and two adjacent first standard cells may be closely arranged, that is, no first cell may be spaced between two adjacent first standard cells, or one or more first cells may be spaced between two adjacent first standard cells.
  • one or more second standard cells may be placed in the same second standard cell row, and two adjacent second standard cells may be closely arranged, that is, no second cell may be spaced between two adjacent second standard cells, or one or more second cells may be spaced between two adjacent second standard cells.
  • first standard cells placed in different first standard cell rows can be aligned or staggered by an integer number of first cells.
  • second standard cells placed in different second standard cell rows can be aligned or staggered by an integer number of second cells.
  • the first standard cell placed in the first standard cell row and the second standard cell placed in the second standard cell row may be staggered by 0.5, 1.5, 2.5, ... first grid positions.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the plurality of standard cell rows specifically include a plurality of first standard cell rows and a plurality of second standard cell rows, wherein only the first standard cell is placed in the first standard cell row, and only the second standard cell is placed in the second standard cell row.
  • the first standard cell row is divided into a plurality of first cells closely arranged along the first direction
  • the second standard cell row is divided into a plurality of second cells closely arranged along the first direction.
  • the width of the first cell and the second cell in the first direction is the same and equal to one CPP.
  • the difference from the first embodiment is that the height of the first cell and the second cell in the second direction is different, for example, the height of the first cell may be greater than the height of the second cell.
  • the first cells in different first standard cell rows are aligned, and the second cells in different second standard cell rows are aligned.
  • the first cell in the first standard cell row and the second cell in the second standard cell row are staggered by 0.5 of the first cell.
  • every two first standard cell rows and every two second standard cell rows are used as the minimum cycle unit for repeated arrangement. This is not a limitation of the actual layout planning design.
  • a first standard cell may occupy a plurality of first cells in a row of first standard cells, or, according to actual design requirements, a first standard cell may occupy a plurality of first cells in multiple rows of first standard cells.
  • a second standard cell may occupy a plurality of second cells in a row of second standard cells, or, according to actual design requirements, a second standard cell may occupy a plurality of second cells in multiple rows of second standard cells.
  • one or more first standard cells may be placed in the same first standard cell row, and two adjacent first standard cells may be closely arranged, that is, no first cell may be spaced between two adjacent first standard cells, or one or more first cells may be spaced between two adjacent first standard cells.
  • one or more second standard cells may be placed in the same second standard cell row, and two adjacent second standard cells may be closely arranged, that is, no second cell may be spaced between two adjacent second standard cells, or one or more second cells may be spaced between two adjacent second standard cells.
  • first standard cells placed in different first standard cell rows can be aligned or staggered by an integer number of first cells.
  • second standard cells placed in different second standard cell rows can be aligned or staggered by an integer number of second cells.
  • the first standard cell placed in the first standard cell row and the second standard cell placed in the second standard cell row may be staggered by 0.5, 1.5, 2.5, ... first grid positions.
  • the plurality of standard cell rows specifically include a plurality of first standard cell rows, a plurality of second standard cell rows, and a plurality of third standard cell rows. Only the first standard cell is placed in the first standard cell row, only the second standard cell is placed in the second standard cell row, and the first standard cell and the second standard cell can be placed in the third standard cell row.
  • the first standard cell row is divided into a plurality of first lattices closely arranged along the first direction
  • the second standard cell row is divided into a plurality of second lattices closely arranged along the first direction
  • the third standard cell row is divided into a plurality of first lattices closely arranged along the first direction and a plurality of second lattices closely arranged along the first direction
  • the first lattices and the second lattices in the third standard cell row are overlapped.
  • the width of the first lattice and the second lattice in the first direction is the same and equal to one CPP
  • the height of the first lattice and the second lattice in the second direction is the same.
  • the first lattices in different first standard cell rows are aligned, and the second lattices in different second standard cell rows are aligned.
  • the first lattice in the first standard cell row and the second lattice in the second standard cell row are staggered by 0.5 of the first lattice.
  • the first cells in the third standard cell row are aligned with the first cells in the first standard cell row, and the second cells in each third standard cell row are aligned with the second cells in the second standard cell row.
  • every two first standard cell rows, every two second standard cell rows, and every two third standard cell rows are used as the minimum cycle unit for repeated arrangement, which is not a limitation of the actual layout planning design.
  • a first standard cell may occupy a plurality of first cells in a row of the first standard cell row or the third standard cell row, or, according to actual design requirements, a first standard cell may occupy a plurality of first cells in multiple rows of the first standard cell row or the third standard cell row.
  • a second standard cell may occupy a plurality of second cells in a row of the second standard cell row or the third standard cell row, or, according to actual design requirements, a second standard cell may occupy a plurality of second cells in multiple rows of the second standard cell row or the third standard cell row.
  • one or more first standard cells may be placed, and two adjacent first standard cells may be closely arranged, that is, the first grid position may not be spaced between two adjacent first standard cells, and one or more first grid positions may be spaced between two adjacent first standard cells.
  • one or more second standard cells may be placed, and two adjacent second standard cells may be closely arranged, that is, the second grid position may not be spaced between two adjacent second standard cells, and one or more second grid positions may be spaced between two adjacent second standard cells.
  • first standard cells In the same third standard cell row, only one or more first standard cells may be placed, and two adjacent first standard cells may be closely arranged, that is, the first grid position may not be spaced between two adjacent first standard cells, and one or more first grid positions may be spaced between two adjacent first standard cells.
  • only one or more second standard cells may be placed, and two adjacent second standard cells may be closely arranged, that is, the second grid position may not be spaced between two adjacent second standard cells, and one or more second grid positions may be spaced between two adjacent second standard cells.
  • one or more first standard cells and one or more second standard cells may be placed simultaneously, and adjacent first standard cells and second standard cells are spaced 0.5, 1.5, 2.5, ..., by first grid positions.
  • first standard cells placed in different first standard cell rows or third standard cell rows may be aligned or staggered by an integer number of first grid positions.
  • second standard cells placed in different second standard cell rows or third standard cell rows may be aligned or staggered by an integer number of second grid positions.
  • the first standard cell placed in the first standard cell row or the third standard cell row and the second standard cell placed in the second standard cell row or a different third standard cell row may be staggered by 0.5, 1.5, 2.5, ... first grid positions.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the plurality of standard cell rows are composed of a plurality of third standard cell rows, and the first standard cell and the second standard cell can be placed in the third standard cell row.
  • the third standard cell row is divided into a plurality of first lattices closely arranged along the first direction and a plurality of second lattices closely arranged along the first direction, and the first lattices and the second lattices in the third standard cell row are overlapped.
  • the width of the first lattice and the second lattice in the first direction is the same and equal to one CPP, and the height of the first lattice and the second lattice in the second direction is the same.
  • the first lattice and the second lattice in a third standard cell row can be staggered by a distance of 0.5 of the first lattice.
  • the first lattices in different third standard cell rows are aligned, and the second lattices in different third standard cell rows are aligned.
  • a first standard cell may occupy a plurality of first cells in a row of third standard cells, or, according to actual design requirements, a first standard cell may occupy a plurality of first cells in multiple rows of third standard cells.
  • a second standard cell may occupy a plurality of second cells in a row of third standard cells, or, according to actual design requirements, a second standard cell may occupy a plurality of second cells in multiple rows of third standard cells.
  • first standard cells in the same third standard cell row, only one or more first standard cells may be placed, and two adjacent first standard cells may be closely arranged, that is, there may be no first grid position between two adjacent first standard cells, or one or more first grid positions may be separated between two adjacent first standard cells.
  • second standard cells in the same third standard cell row, only one or more second standard cells may be placed, and two adjacent second standard cells may be closely arranged, that is, there may be no second grid position between two adjacent second standard cells, or one or more second grid positions may be separated between two adjacent second standard cells.
  • one or more first standard cells and one or more second standard cells may be placed at the same time, and the adjacent first standard cells and second standard cells are separated by 0.5, 1.5, 2.5... first grid positions.
  • the first standard cells placed in different third standard cell rows can be aligned or staggered by an integer number of first grid positions.
  • the second standard cells placed in different third standard cell rows can be aligned or staggered by an integer number of second grid positions.
  • the first standard cells and the second standard cells placed in different third standard cell rows can be staggered by 0.5, 1.5, 2.5, ..., first grid positions.
  • a second aspect of an embodiment of the present application provides an electronic device, including a circuit board and an integrated circuit, wherein the integrated circuit is an integrated circuit of any possible design provided in the first aspect.
  • FIG1A is a schematic diagram of a framework of an electronic device provided in an embodiment of the present application.
  • FIG1B is a schematic diagram of a framework of a SOC provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of creating a grid for placing standard cells during physical design of a digital chip
  • FIG3A is a schematic structural diagram of a DDB standard unit provided by the related art.
  • FIG3B is a schematic structural diagram of an MDB standard unit provided by the related art.
  • FIG3C is a schematic structural diagram of a SDB standard unit provided by the related art.
  • FIG4A is a schematic structural diagram of a DDB standard unit spliced with a DDB standard unit provided by the related art
  • FIG4B is a schematic structural diagram of a splicing of an MDB standard cell and an MDB standard cell provided by the related art
  • FIG4C is a schematic structural diagram of a SDB standard cell and a SDB standard cell spliced together provided by the related art
  • FIG5A is a schematic diagram of the relative position relationship between a grid position and an M2 layer routing track during SDB design provided by the related art
  • FIG5B is a schematic diagram of the relative position relationship between the grid position and the M2 layer routing track during MDB/DDB design provided by the related art
  • FIG6 is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of a standard cell row in Embodiment 1;
  • FIG8 is a schematic diagram of an arrangement of the first standard unit and the second standard unit in the first embodiment
  • FIG9 is an enlarged detail view of the dotted line frame in FIG8 ;
  • FIG10 is a schematic diagram of another arrangement of the first standard unit and the second standard unit in the first embodiment
  • FIG11 is a schematic diagram of the structure of a standard cell row in Embodiment 2;
  • FIG12 is a schematic diagram of an arrangement of the first standard unit and the second standard unit in the second embodiment
  • FIG13 is an enlarged detail view of the dotted line frame in FIG12;
  • FIG14 is a schematic diagram of the structure of a standard cell row in Embodiment 3.
  • FIG15 is a schematic diagram of an arrangement of the first standard unit and the second standard unit in Embodiment 3;
  • FIG16 is an enlarged detail view of the dotted line frame in FIG15 ;
  • FIG17 is a schematic diagram of the structure of a standard cell row in Embodiment 4.
  • FIG. 18 is a schematic diagram showing an arrangement of the first standard cell and the second standard cell in the fourth embodiment.
  • directional terms such as “up”, “down”, “left” and “right” may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • coupled can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • contact can be a direct contact or an indirect contact through an intermediate medium.
  • a and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • the embodiment of the present application provides an electronic device.
  • the electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, and a communication electronic product.
  • consumer electronic products are such as mobile phones, tablet computers (pad), laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products are such as smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (such as soybean milk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products are such as vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVD), etc.
  • Financial terminal products are such as automated teller machines (ATMs), self-service terminals, etc.
  • Communication electronic products are such as communication equipment such as servers, storage devices, radars, base stations, etc.
  • the electronic device mainly includes a cover plate 1, a display screen 2, a middle frame 3, and a rear shell 4.
  • the rear shell 4 and the display screen 2 are respectively located on both sides of the middle frame 3, and the middle frame 3 and the display screen 2 are arranged in the rear shell 4, the cover plate 1 is arranged on the side of the display screen 2 away from the middle frame 3, and the display surface of the display screen 2 faces the cover plate 1.
  • the display screen 2 may be a liquid crystal display (LCD).
  • the liquid crystal display includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is arranged between the cover plate 1 and the backlight module.
  • the backlight module is used to provide a light source for the liquid crystal display panel.
  • the display screen 2 may also be an organic light emitting diode (OLED) display screen. Since the OLED display screen is a self-luminous display screen, there is no need to set a backlight module.
  • OLED organic light emitting diode
  • the middle frame 3 includes a carrier plate 31 and a frame 32 surrounding the carrier plate 31.
  • the electronic device may also include electronic components such as printed circuit boards (PCB), batteries, and cameras, and the printed circuit boards, batteries, and cameras may be arranged on the carrier plate 31.
  • PCB printed circuit boards
  • the above-mentioned electronic device may also include a system on chip (SOC), a radio frequency chip, etc. arranged on the PCB.
  • SOC system on chip
  • the PCB is used to carry the system on chip, the radio frequency chip, etc., and is electrically connected to the system on chip, the radio frequency chip, etc.
  • an embodiment of the present application also provides a SOC.
  • the SOC includes a processor 11, a memory 12, a digital-to-analog conversion module (ADC/DAC) 13, a power management module 14, an interface module 15 and a user-defined logic 16.
  • ADC/DAC digital-to-analog conversion module
  • the above structure can be coupled to a bus 17 to perform communication.
  • the processor 11 can perform specific calculations or tasks, and the processor 11 can include, for example, a microprocessor, a central processing unit (CPU), a digital signal processor DSP, etc.
  • the memory 12 can store data necessary for operating the SOC.
  • the memory 12 can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a ferroelectric random access memory (ferroelectric random access memory), a magnetic random access memory (magnetic random access memory, MRAM), etc.
  • the digital-to-analog conversion module 13 is used to realize the conversion between data signals and analog signals.
  • the power management module 14 is used to provide power to each module in the SOC.
  • the interface module 15 is used to realize the communication between the SOC and the outside.
  • the user-defined logic 16 or other digital modules can be, for example, an application specific integrated circuit (ASIC) formed by a field programmable gate array (FPGA) or a complex programmable logic device (CPLD).
  • the bus 17 may include, for example, an address bus, a control bus, a data bus, or an expansion bus.
  • EDA electronic design automation
  • a placement area needs to be created to place standard cells.
  • the placement area is divided into multiple rows, and each row is divided into multiple sites.
  • Sites are the smallest unit for placing standard cells.
  • a site is generally the smallest distinguishable site of the process, and all standard cells must be placed on a site.
  • the standard cells can be divided into three categories according to the isolation type between the standard cells (stand-cell, STC): double diffusion break (DDB) standard cell, single diffusion break (SDB) standard cell and mixed diffusion break (SDB) standard cell.
  • DDB double diffusion break
  • SDB single diffusion break
  • SDB mixed diffusion break
  • MDB Mix diffusion break
  • the DDB standard cell includes a plurality of first gate strips G, two edge gates, a P-type active area (P active, PA) and an N-type active area (N active, NA).
  • the edge gate is arranged in the same layer as the first gate strips G and is located above the P-type active area PA and the N-type active area NA.
  • the two edge gates are located on both sides of the plurality of first gate strips G. From a top view, the P-type active area PA and the N-type active area NA are located between the two edge gates.
  • Contact holes are correspondingly arranged above the first gate strips G, the P-type active area PA and the N-type active area NA, and no contact hole is arranged above the edge gate.
  • the P-type active area PA, the N-type active area NA, the edge gate and the first gate strip are located between two isolation strips (poly cut).
  • a shallow trench isolation is provided outside the edge gate of the DDB standard cell away from the first gate bar G.
  • the distance from the edge of the STI to the edge gate is approximately half (0.5CPP) of the spacing between adjacent first gate bars G (or understood as the contact poly pitch (CPP)).
  • the boundary of the DDB standard cell is 0.5CPP outside the edge gate, and the STI is provided to leave a gap for blocking the P-type active area PA and the N-type active area NA.
  • the MDB standard cell refers to an NMOS/PMOS that mixes two types of diffusion fractures, SDB/DDB.
  • FIG3B only illustrates one of the structures.
  • the MDB standard cell includes a plurality of first gate strips G, two edge gates, a P-type active area PA, and an N-type active area NA.
  • the two edge gates are located on both sides of the plurality of first gate strips G, and the first gate strip G is located above the P-type active area PA and the N-type active area NA.
  • the edge gate includes a diffusion fracture, a barrier gate, and a barrier portion that separates the two.
  • the diffusion fracture runs through the P-type active area PA and plays a barrier role.
  • the barrier gate is located above the N-type active area NA.
  • Connection holes are correspondingly arranged above the first gate strips G, the P-type active area PA, and the N-type active area NA, and no connection hole is arranged above the edge gate.
  • the P-type active area PA, the N-type active area NA, the edge gate, and the first gate strip are located between the two isolation strips.
  • the P-type active area PA extends outside the edge gate, and an STI is arranged outside the N-type active area NA.
  • the distance from the edge of the P-type active area PA to the edge gate is about 0.5CPP, and the distance from the edge of the STI to the edge gate is about 0.5CPP.
  • the boundary of the MDB standard cell is 0.5CPP outside the edge gate, and the STI is arranged to leave a gap for blocking the N-type active area NA.
  • the P-type active area PA has been blocked by the diffusion fracture, so a P-type active area PA can be formed outside the diffusion fracture to improve the performance of the standard cell.
  • the SDB standard cell includes a plurality of first gate strips G, two edge gates, a P-type active area PA, and an N-type active area NA.
  • the two edge gates are located on both sides of the plurality of first gate strips G, and the first gate strip G is located above the P-type active area PA and the N-type active area NA.
  • the edge gate is a diffusion fracture, penetrating the P-type active area PA and the N-type active area NA, and the P-type active area PA and the N-type active area NA are located between the two edge gates.
  • Connection holes are correspondingly arranged above the first gate strip G, the P-type active area PA, and the N-type active area NA, and no connection hole is arranged above the edge gate.
  • the P-type active area PA, the N-type active area NA, the edge gate, and the first gate strip are located between the two isolation strips.
  • the center line of the edge gate in the SDB standard cell serves as the boundary of the SDB standard cell.
  • the P-type active area PA and the N-type active area NA are blocked by diffusion fractures, and the boundary of the SDB standard cell does not need to extend outside the edge gate.
  • the left and right ends of the DDB standard cell and the MDB standard cell are extended by about 0.5 CPP respectively compared with the left and right ends of the SDB standard cell, and the width of 1 CPP is generally equal to the width of 1 site.
  • the DDB standard cell can use two fewer masks for preparing diffusion fractures, and has a lower preparation cost.
  • the active area and insulating layer of the SDB standard cell do not need to extend outside the edge gate, and have a smaller design area.
  • the MDB standard cell uses the layout dependent effect (LDE) to combine the DDB standard cell and the SDB standard cell, and realizes the speed improvement of the MDB standard cell relative to the SDB standard cell or the DDB standard cell, so that the MDB standard cell has a better performance.
  • LDE layout dependent effect
  • HP standard cell libraries are generally implemented using DDB standard cells
  • HD standard cell libraries are generally implemented based on SDB standard cells.
  • the performance power area (PPA) of the module implemented by the MDB standard cell and the module implemented by the SDB standard cell is compared.
  • the physical synthesis implementation is compared under the conditions of power supply voltage VDD of 0.6V, temperature of 85°C, and typical corner (TT) of TT0 (that is, tt0p6v85c in Table 1), and power supply voltage VDD of 1.0V, temperature of 85°C, and typical corner (TT) of TT1 (that is, tt1p0v85c in Table 1).
  • the speed of the MDB standard cell is improved by 2% to 8% compared with the SDB standard cell
  • the area of the MDB standard cell is increased by 5% to 12% compared with the SDB standard cell.
  • Using the MDB standard cell will increase the area of the chip, thereby increasing the chip cost.
  • the leakage power consumption of the MDB standard cell increases by more than 25% compared with the SDB standard cell. For consumer products, leakage power consumption is a relatively important indicator, and excessive increase in leakage power consumption is unacceptable.
  • the MDB standard cell, the SDB standard cell and the DDB standard cell each have their own advantages and disadvantages, and the three can be mixed and used in the same integrated circuit to effectively improve the performance of the integrated circuit.
  • the left and right ends of the MDB standard cell and the DDB standard cell are distributed and expanded by about 0.5 CPP compared with the left and right ends of the SDB standard cell, as shown in FIG4A, when two DDB standard cells are spliced, the splicing line is located between the edge gates of the two DDB standard cells, and the splicing line is about 0.5 CPP away from the edge gate.
  • the splicing line is located between the edge gates of the two MDB standard cells, and the splicing line is about 0.5 CPP away from the edge gate.
  • the splicing line is located on the center line of the edge gate in the SDB standard cell, and the edge gates of the two SDB standard cells overlap. Due to the different positions of the splicing lines, the DDB/MDB standard cell cannot be placed in the same row as the SDB standard cell.
  • the routing track where the vertical pins connected to the SDB are placed needs to be aligned with the edge of the sites where the SDB is placed, that is, the routing track has no offset (offset spacing) relative to the boundaries of the sites of the SDB; as shown in Figure 5B, the routing track where the vertical pins connected to the MDB/DDB are placed needs to be aligned with the center line of the sites where the MDB/DDB is placed, that is, the routing track is offset by 0.5 site relative to the boundaries of the sites of the MDB/DDB.
  • FIG. 5A and FIG. 5B only illustrate the case where the site pitch (approximately equal to CPP) and the routing track pitch (pitch) are 1:1.
  • the pitch ratio of the two can also be 3:2 (for example, 63nm:42nm), or 4:3 (for example, 84nm:63nm).
  • the floor plan stage creates sites of the same type (all sites are arranged with the same horizontal starting point, which can also be called aligned arrangement), and creates corresponding routing tracks at the same time. Since the offset of the routing tracks relative to the site boundaries of SDB and MDB/DDB is different, they are classified into different types of standard cell libraries, which means that only the same type of standard cell library can be used in the same integrated circuit. That is, due to the different alignment methods of the three types of standard cells, different types of standard cells of the same height (or height that is an integer multiple) cannot be compatible with each other in an integrated circuit, and EDA tools cannot support the direct mixing of MDB standard cells and DDB standard cells with SDB standard cells in the same integrated circuit. For example, whether based on the HP standard cell library or the HD standard cell library, the integrated circuit is designed using one type of standard cell. However, hybrid diffusion break (HDB) that mixes different types of standard cells can obtain a more optimized design.
  • HDB hybrid diffusion break
  • an embodiment of the present application provides an integrated circuit designed with a new layout plan to achieve compatibility of different types of standard cells in the same integrated circuit.
  • an integrated circuit may specifically include: a plurality of first standard cells 100, a plurality of second standard cells 200, a plurality of first pins 310, and a plurality of second pins 320.
  • the first standard cell 100 may be a single diffusion break standard cell (SDB)
  • the second standard cell 200 may be a mixed diffusion break standard cell (MDB) or a double diffusion break standard cell (DDB).
  • the second standard cell 200 may be an SDB
  • the first standard cell 100 may be an MDB or a DDB.
  • MDB and DDB may exist at the same time, or only MDB or DDB may exist, which is not limited here.
  • a plurality of first standard cells 100 and a plurality of second standard cells 200 are arranged in a plurality of standard cell rows R extending along a first direction x (also referred to as a row direction or a horizontal direction) and arranged along a second direction y (also referred to as a column direction or a vertical direction).
  • Each first standard cell 100 occupies a positive integer number of first cells S1 among a plurality of first cells S1 closely arranged along the first direction x, and the number of first cells S1 occupied by each first standard cell 100 can be adjusted according to actual design requirements, for example, one first standard cell 100 can occupy three first cells S1, and another first standard cell 100 can occupy five first cells S1, which are not exhaustively listed here;
  • the second standard cell 200 occupies a positive integer number of second cells S2 among a plurality of second cells S2 closely arranged along the first direction x, and the number of second cells S2 occupied by each second standard cell 200 can be adjusted according to actual design requirements, for example, one second standard cell 200 can occupy two second cells S2, and another second standard cell 200 can occupy four second cells S2, which are not exhaustively listed here.
  • the width of the first cell S1 and the second cell S2 in the first direction x needs to be an integer multiple of the contact polysilicon pitch (CPP).
  • the width of the first cell S1 and the second cell S2 in the first direction x can be the same, and can further be equal to one CPP, in this case, the first cell S1 and the second cell S2 are both the smallest distinguishable cells of the process.
  • the width of the first cell S1 in the first direction x can be equal to one CPP
  • the width of the second cell S2 in the first direction x can be equal to two or more CPPs, in this case, the first cell S1 is the smallest distinguishable cell of the process.
  • the width of the first cell S1 in the first direction x can be equal to two or more CPPs
  • the width of the second cell S2 in the first direction x can be equal to two or more CPPs
  • the widths of the first cell S1 and the second cell S2 in the first direction x can be the same number of CPPs or different numbers of CPPs.
  • the following is an example in which the widths of the first cell S1 and the second cell S2 in the first direction x are equal to one CPP.
  • the closely arranged multiple first cells S1 and the closely arranged multiple second cells S2 need to be staggered by a non-integer number of first cells S1 in the first direction x, so that the first standard cell 100 placed on the first cell S1 and the second standard cell 200 placed on the second cell S2 can maintain a non-integer number of CPPs staggered in the first direction x, that is, the first standard cell 100 and the second standard cell 200 will not be aligned in the first direction x (in this case, the first standard cell 100 and the second standard cell 200 need to be located in different standard cell rows R), nor will they be staggered by an integer number of CPPs (in this case, the first standard cell 100 and the second standard cell 200 can be located in different standard cell rows R, or in the same standard cell row R).
  • a plurality of closely arranged first lattices S1 and a plurality of closely arranged second lattices S2 may be staggered by a distance of 0.5 of the first lattices S1 in the first direction x, so that the first standard cell 100 and the second standard cell 200 may maintain a staggered relationship of an odd number of 0.5 CPPs in the first direction x, that is, the first standard cell 100 and the second standard cell 200 may be staggered by 0.5 CPPs, or may be staggered by 1.5 CPPs, or may be staggered by 2.5 CPPs in the first direction x, which are not exhaustive here.
  • the following description is based on an example that a plurality of closely arranged first lattices S1 and a plurality of closely arranged second lattices S2 are staggered by a distance of 0.5 of the first lattice S1 in the first direction x. It is worth noting that when determining the offset distance between the first cell S1 and the second cell S2 in the first direction x, the boundary of the first cell S1 and the second cell S2 on the same side can be used as a reference for comparison, for example, the left boundary of the first cell S1 and the second cell S2 can be used as a reference for comparison.
  • the boundary of the first standard cell 100 and the second standard cell 200 on the same side can be used as a reference for comparison, for example, the left boundary of the first standard cell 100 and the second standard cell 200 can be used as a reference for comparison.
  • a plurality of first pins 310 and a plurality of second pins 320 extend along the second direction y, the first pin 310 is located above the first standard cell 100 and coupled to the first standard cell 100, and the second pin 320 is located above the second standard cell 200 and coupled to the second standard cell 200.
  • the routing track t spacing: CPP can be 1:1, or 3:2 or 4:3, which are not exhaustive here. The following description is based on the routing track t spacing: CPP of 1:1 as an example.
  • the routing track t can have different offsets relative to the boundaries of the first cells S1 and the second cells S2.
  • the boundary of the second cell S2 is aligned with the routing track t, and the boundary of the first cell S1 is offset from the routing track t by 0.5 CPP. In this way, it can be ensured that the first pin 310 coupled to the first standard cell 100 and the second pin 320 coupled to the second standard cell 200 are both arranged on the routing track t.
  • the integrated circuit provided in the embodiment of the present application can create multiple types of sites in the same design during layout planning and design, that is, a plurality of closely arranged first sites S1 and a plurality of closely arranged second sites S2 can be simultaneously created in the same design, the first sites S1 can only accommodate the first standard cells 100, and the second sites S2 can only accommodate the second standard cells 200.
  • the closely arranged first sites S1 and the closely arranged second sites S2 are staggered in the first direction x by a non-integer number of the first sites S1, so that the first standard cells 100 and the second standard cells 200 can be mixed in the same design.
  • the positions of the standard cell rows in which the first standard cell 100 and the second standard cell 200 can be arranged can be determined according to the placement position relationship between the closely arranged plurality of first cells and the closely arranged plurality of second cells.
  • the standard cell row in which only the first standard cell 100 can be placed among the plurality of standard cell rows R can be referred to as the first standard cell row R1
  • the standard cell row in which only the second standard cell 200 can be placed among the plurality of standard cell rows R can be referred to as the second standard cell row R2
  • the standard cell row in which both the first standard cell row 100 and the second standard cell 200 can be placed among the plurality of standard cell rows R can be referred to as the third standard cell row R3, and according to design requirements, only the first standard cell 100 or the second standard cell 200 can be placed in one or more third standard cell rows R3.
  • the difference between the first standard cell row R1, the second standard cell row R2 and the third standard cell row R3 is that: the first standard cell row R1 is divided into a plurality of first cells S1 closely arranged along the first direction x; the second standard cell row R2 is divided into a plurality of second cells S2 closely arranged along the first direction x; the third standard cell row R3 is divided into a plurality of first cells S1 closely arranged along the first direction x and a plurality of second cells S2 closely arranged along the first direction x, and the first cells S1 and the second cells S2 in the third standard cell row R3 are overlapped.
  • the plurality of closely arranged first cells S1 and the plurality of closely arranged second cells S2 are staggered by a distance less than one first cell S1.
  • multiple standard cell rows can be composed of a first standard cell row R1 and a second standard cell row R2.
  • the plurality of standard cell rows may be composed of a first standard cell row R1, a second standard cell row R2 and a third standard cell row R3, or a plurality of standard cell rows may be composed of a first standard cell row R1 and a third standard cell row R3, or a plurality of standard cell rows may be composed of a second standard cell row R2 and a third standard cell row R3, or a plurality of standard cell rows may be composed of only a third standard cell row R3.
  • the above-mentioned configuration methods of the plurality of standard cell rows can all support the mixing of the first standard cell 100 and the second standard cell 200 in the same design. Moreover, in the same layout planning design, the heights of the first cell position S1 and the second cell position S2 in the second direction y may be the same or different. The following is a detailed description through specific embodiments.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the plurality of standard cell rows R specifically include a plurality of first standard cell rows R1 and a plurality of second standard cell rows R2. Only the first standard cell 100 is placed in the first standard cell row R1, and only the second standard cell 200 is placed in the second standard cell row R2.
  • the first standard cell row R1 is divided into a plurality of first cells S1 closely arranged along the first direction x
  • the second standard cell row R2 is divided into a plurality of second cells S2 closely arranged along the first direction x.
  • the width of the first cell S1 and the second cell S2 in the first direction x is the same and equal to one CPP, and the height of the first cell S1 and the second cell S2 in the second direction y is the same.
  • the first cells S1 in different first standard cell rows R1 are aligned, and the second cells S2 in different second standard cell rows R2 are aligned.
  • the first cells S1 in the first standard cell row R1 and the second cells S2 in the second standard cell row R2 are staggered by a distance of 0.5 of the first cells S1.
  • every two first standard cell rows R1 and every two second standard cell rows R2 are used as the minimum cycle unit for repeated arrangement for illustration, which is not a limitation of the actual layout planning design.
  • a first standard cell 100 may occupy a plurality of first cells S1 in a row of first standard cell rows R1, or, according to actual design requirements, as shown in Fig. 10, a first standard cell 100 may also occupy a plurality of first cells S1 in multiple rows of first standard cell rows R1.
  • a second standard cell 200 may occupy a plurality of second cells S2 in a row of second standard cell rows R2, or, according to actual design requirements, as shown in Fig. 10, a second standard cell 200 may also occupy a plurality of second cells S2 in multiple rows of second standard cell rows R2.
  • one or more first standard cells 100 may be placed in the same first standard cell row R1, and two adjacent first standard cells 100 may be closely arranged, that is, the first cell position S1 may not be spaced between two adjacent first standard cells 100, or one or more first cell positions S1 may be spaced between two adjacent first standard cells 100.
  • one or more second standard cells 200 may be placed in the same second standard cell row R2, and two adjacent second standard cells 200 may be closely arranged, that is, the second cell position S2 may not be spaced between two adjacent second standard cells 200, or one or more second cell positions S2 may be spaced between two adjacent second standard cells 200.
  • first standard cells 100 placed in different first standard cell rows R1 can be aligned or staggered by an integer number of first cells S1.
  • second standard cells 200 placed in different second standard cell rows R2 can be aligned or staggered by an integer number of second cells S2.
  • first standard cells 100 placed in the first standard cell row R1 and the second standard cells 200 placed in the second standard cell row R2 may be staggered by 0.5, 1.5, 2.5, ... first cells S1.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the plurality of standard cell rows R specifically include a plurality of first standard cell rows R1 and a plurality of second standard cell rows R2, wherein only the first standard cell 100 is placed in the first standard cell row R1, and only the second standard cell 200 is placed in the second standard cell row R2.
  • the first standard cell row R1 is divided into a plurality of first cells S1 closely arranged along the first direction x
  • the second standard cell row R2 is divided into a plurality of second cells S2 closely arranged along the first direction x.
  • the widths of the first cells S1 and the second cells S2 in the first direction x are the same and equal to one CPP.
  • the difference from the first embodiment is that the heights of the first cells S1 and the second cells S2 in the second direction y are different, for example, the height of the first cells S1 may be greater than the height of the second cells S2.
  • the first cells S1 in different first standard cell rows R1 are aligned, and the second cells S2 in different second standard cell rows R2 are aligned.
  • the first cell S1 in the first standard cell row R1 and the second cell S2 in the second standard cell row R2 are offset by a distance of 0.5 of the first cell S1 .
  • every two first standard cell rows R1 and every two second standard cell rows R2 are used as the minimum cycle unit for repeated arrangement for illustration, which is not a limitation of the actual layout planning design.
  • a first standard cell 100 may occupy a plurality of first cells S1 in a row of first standard cell rows R1, or, according to actual design requirements, a first standard cell 100 may also occupy a plurality of first cells S1 in multiple rows of first standard cell rows R1.
  • a second standard cell 200 may occupy a plurality of second cells S2 in a row of second standard cell rows R2, or, according to actual design requirements, a second standard cell 200 may also occupy a plurality of second cells S2 in multiple rows of second standard cell rows R2.
  • one or more first standard cells 100 may be placed in the same first standard cell row R1, and two adjacent first standard cells 100 may be closely arranged, that is, the first cell position S1 may not be spaced between two adjacent first standard cells 100, or one or more first cell positions S1 may be spaced between two adjacent first standard cells 100.
  • one or more second standard cells 200 may be placed in the same second standard cell row R2, and two adjacent second standard cells 200 may be closely arranged, that is, the second cell position S2 may not be spaced between two adjacent second standard cells 200, or one or more second cell positions S2 may be spaced between two adjacent second standard cells 200.
  • first standard cells 100 placed in different first standard cell rows R1 can be aligned or staggered by an integer number of first cells S1.
  • second standard cells 200 placed in different second standard cell rows R2 can be aligned or staggered by an integer number of second cells S2.
  • first standard cells 100 placed in the first standard cell row R1 and the second standard cells 200 placed in the second standard cell row R2 may be staggered by 0.5, 1.5, 2.5, ... first cells S1.
  • the plurality of standard cell rows R specifically include a plurality of first standard cell rows R1, a plurality of second standard cell rows R2, and a plurality of third standard cell rows R3. Only the first standard cell 100 is placed in the first standard cell row R1, only the second standard cell 200 is placed in the second standard cell row R2, and the first standard cell 100 and the second standard cell 200 can be placed in the third standard cell row R3.
  • the first standard cell row R1 is divided into a plurality of first cells S1 closely arranged along the first direction x
  • the second standard cell row R2 is divided into a plurality of second cells S2 closely arranged along the first direction x
  • the third standard cell row R3 is divided into a plurality of first cells S1 closely arranged along the first direction x and a plurality of second cells S2 closely arranged along the first direction x, and the first cells S1 and the second cells S2 in the third standard cell row R3 are overlapped.
  • the width of the first cell S1 and the second cell S2 in the first direction x is the same and equal to one CPP
  • the height of the first cell S1 and the second cell S2 in the second direction y is the same.
  • the first cells S1 in different first standard cell rows R1 are aligned, and the second cells S2 in different second standard cell rows R2 are aligned.
  • the first cells S1 in the first standard cell row R1 and the second cells S2 in the second standard cell row R2 are staggered by a distance of 0.5 of the first cells S1.
  • the first cells S1 in the third standard cell row R3 are aligned with the first cells S1 in the first standard cell row R1, and the second cells S2 in each third standard cell row R3 are aligned with the second cells S2 in the second standard cell row R2.
  • every two first standard cell rows R1, every two second standard cell rows R2 and every two third standard cell rows R3 are used as the minimum cycle unit for repeated arrangement, which is not a limitation of the actual layout planning design.
  • a first standard cell 100 may occupy a plurality of first cells S1 in a row of the first standard cell row R1 or the third standard cell row R3, or, according to actual design requirements, a first standard cell 100 may also occupy a plurality of first cells S1 in multiple rows of the first standard cell row R1 or the third standard cell row R3.
  • a second standard cell 200 may occupy a plurality of second cells S2 in a row of the second standard cell row R2 or the third standard cell row R3, or, according to actual design requirements, a second standard cell 200 may also occupy a plurality of second cells S2 in multiple rows of the second standard cell row R2 or the third standard cell row R3.
  • one or more first standard cells 100 may be placed in the same first standard cell row R1, and two adjacent first standard cells 100 may be closely arranged, that is, the first cell S1 may not be spaced between two adjacent first standard cells 100, or one or more first cell S1 may be spaced between two adjacent first standard cells 100.
  • one or more second standard cells 200 may be placed in the same second standard cell row R2, and two adjacent second standard cells 200 may be closely arranged, that is, the second cell S2 may not be spaced between two adjacent second standard cells 200, or one or more second cell S2 may be spaced between two adjacent second standard cells 200.
  • first standard cells 100 In the same third standard cell row R3, only one or more first standard cells 100 may be placed, and two adjacent first standard cells 100 may be closely arranged, that is, the first cell S1 may not be spaced between two adjacent first standard cells 100, or one or more first cell S1 may be spaced between two adjacent first standard cells 100.
  • only one or more second standard cells 200 may be placed, and two adjacent second standard cells 200 may be closely arranged, that is, no second cell S2 may be spaced between two adjacent second standard cells 200, or one or more second cell S2 may be spaced between two adjacent second standard cells 200.
  • one or more first standard cells 100 and one or more second standard cells 200 may be placed at the same time, and the adjacent first standard cells 100 and second standard cells 200 may be spaced 0.5, 1.5, 2.5, ..., by first cell S1.
  • first standard cells 100 placed in different first standard cell rows R1 or third standard cell rows R3 can be aligned or staggered by an integer number of first cells S1.
  • second standard cells 200 placed in different second standard cell rows R2 or third standard cell rows R3 can be aligned or staggered by an integer number of second cells S2.
  • the first standard cell 100 placed in the first standard cell row R1 or the third standard cell row R3 is
  • the second standard cells 200 in the second standard cell row R2 or in a different third standard cell row R3 may be staggered by 0.5, 1.5, 2.5, ... first cells S1.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the plurality of standard cell rows R are composed of a plurality of third standard cell rows R3, and the first standard cell 100 and the second standard cell 200 can be placed in the third standard cell row R3.
  • the third standard cell row R3 is divided into a plurality of first cells S1 closely arranged along the first direction x and a plurality of second cells S2 closely arranged along the first direction x, and the first cells S1 and the second cells S2 in the third standard cell row R3 are arranged overlappingly.
  • the width of the first cell S1 and the second cell S2 in the first direction x is the same and equal to one CPP, and the height of the first cell S1 and the second cell S2 in the second direction y is the same.
  • the first cell S1 and the second cell S2 in a third standard cell row R3 can be staggered by a distance of 0.5 of the first cell S1.
  • the first cells S1 in different third standard cell rows R3 are aligned, and the second cells S2 in different third standard cell rows R3 are aligned.
  • a first standard cell 100 may occupy a plurality of first cells S1 in a row of third standard cell rows R3, or, according to actual design requirements, a first standard cell 100 may also occupy a plurality of first cells S1 in multiple rows of third standard cell rows R3.
  • a second standard cell 200 may occupy a plurality of second cells S2 in a row of third standard cell rows R3, or, according to actual design requirements, a second standard cell 200 may also occupy a plurality of second cells S2 in multiple rows of third standard cell rows R3.
  • first standard cells 100 in the same third standard cell row R3, only one or more first standard cells 100 may be placed, and two adjacent first standard cells 100 may be closely arranged, that is, the first cell S1 may not be spaced between two adjacent first standard cells 100, and one or more first cell S1 may be spaced between two adjacent first standard cells 100.
  • only one or more second standard cells 200 may be placed, and two adjacent second standard cells 200 may be closely arranged, that is, the second cell S2 may not be spaced between two adjacent second standard cells 200, and one or more second cell S2 may be spaced between two adjacent second standard cells 200.
  • one or more first standard cells 100 and one or more second standard cells 200 may be placed at the same time, and the adjacent first standard cells 100 and second standard cells 200 may be spaced by 0.5, 1.5, 2.5, ... first cell S1.
  • the first standard cells 100 placed in different third standard cell rows R3 can be aligned or staggered by an integer number of first cells S1.
  • the second standard cells 200 placed in different third standard cell rows R3 can be aligned or staggered by an integer number of second cells S2.
  • the first standard cells 100 and the second standard cells 200 placed in different third standard cell rows R3 can be staggered by 0.5, 1.5, 2.5, ..., first cells S1.
  • the embodiment of the present application also provides an electronic device, including the above-mentioned integrated circuit and circuit board provided in the embodiment of the present application. Since the principle of solving the problem by the electronic device is similar to that of the above-mentioned integrated circuit, the implementation of the electronic device can refer to the implementation of the above-mentioned integrated circuit, and the repeated parts will not be repeated.

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Abstract

本申请公开了一种集成电路及电子设备，涉及半导体技术领域，用以实现在同一集成电路中兼容不同类型的标准单元。集成电路包括第一标准单元、第二标准单元、第一管脚和第二管脚。第一标准单元和第二标准单元排布在沿着第一方向延伸且沿着第二方向排列的多个标准单元行中，第一标准单元占用沿着第一方向紧密排列的正整数个第一格位，第二标准单元占用沿着第一方向紧密排列的正整数个第二格位，第一格位与第二格位在第一方向上错开非整数个第一格位的距离。第一管脚和第二管脚沿着第二方向延伸，第一管脚与第一标准单元耦接，第二管脚与第二标准单元耦接，第一管脚和第二管脚均排布在多条等间距设置的走线轨道上。

Description

集成电路及电子设备
相关申请的交叉引用
本申请要求在2022年11月30日提交中国专利局、申请号为202211522517.8、申请名称为“集成电路及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种集成电路及电子设备。
背景技术
标准单元库(standard cell library)包括版图库、符号库、电路逻辑库等，是集成电路芯片后端设计过程中的基础部分。当前鳍式场效应晶体管(fin field-effect transistor，FinFET)技术节点的标准单元库中，按照标准单元(stand-cell，STC)之间隔离类型进行划分，可将标准单元分为三类：双扩散断裂(double diffusion break，DDB)标准单元、单扩散断裂(single diffusion break，SDB)标准单元以及混合扩散断裂(mix diffusion break，MDB)标准单元。
DDB标准单元具有较低的制备成本，SDB标准单元具有较小的设计面积，MDB标准单元具有更优异的性能。三种类型的标准单元有着各自的优点，如何在同一集成电路中兼容不同类型的标准单元，成为本领域技术人员需要解决的技术问题。
发明内容
本申请实施例提供一种集成电路及电子设备，用以实现在同一集成电路中兼容不同类型的标准单元。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种集成电路，具体可以包括：多个第一标准单元、多个第二标准单元、多个第一管脚和多个第二管脚。具体地，第一标准单元可以为单扩散断裂标准单元(SDB)，第二标准单元可以为混合扩散断裂标准单元(MDB)或双扩散断裂标准单元(DDB)。或者，第二标准单元可以为SDB，第一标准单元可以为MDB或DDB。并且，在一个集成电路中，可以同时存在MDB和DDB，也可以仅存在MDB或DDB，在此不做限定。
在本申请实施例中，多个第一标准单元和多个第二标准单元排布在沿着第一方向(也可以称为行方向或水平方向)延伸且沿着第二方向(也可以称为列方向或竖直方向)排列的多个标准单元行中。各第一标准单元占用沿着第一方向紧密排列的多个第一格位中的正整数个第一格位，且各第一标准单元占用的第一格位的数量可以根据实际设计需要进行调节，例如一个第一标准单元可以占用三个第一格位，另一个第一标准单元可以占用五个第一格位，在此不做穷举；第二标准单元占用沿着第一方向紧密排列的多个第二格位中的正整数个第二格位，且各第二标准单元占用的第二格位的数量可以根据实际设计需要进行调节，例如一个第二标准单元可以占用两个第二格位，另一个第二标准单元可以占用四个第二格位，在此不做穷举。
在本申请实施例中，第一格位和第二格位在第一方向上的宽度需要为接触多晶硅间距(CPP)的整数倍。例如，第一格位与第二格位在第一方向上的宽度可以相同，进一步可以等于一个CPP，此时第一格位和第二格位均为工艺的最小可分辨格位。又如，第一格位在第一方向上的宽度可以等于一个CPP，第二格位在第一方向上的宽度可以等于两个或以上CPP，此时第一格位为工艺的最小可分辨格位。再如，第一格位在第一方向上的宽度可以等于两个或以上CPP，第二格位在第一方向上的宽度可以等于两个或以上CPP，且第一格位和第二格位在第一方向上的宽度可以为相同数量的CPP，也可以为不同数量的CPP。以下均是以第一格位与第二格位在第一方向上的宽度等于一个CPP为例进行说明。紧密排列的多个第一格位与紧密排列的多个第二格位需要在第一方向上错开非整数个第一格位的距离，使得放置在第一格位上的第一标准单元和放置在第二格位上的第二标准单元在第一方向上可以保持错开非整数个CPP的关系，即第一标准单元和第二标准单元在第一方向上不会出现对齐排列的关系(此时第一标准单元和第二标准单元需要位于不同标准单元行)，也不会出现错开整数个CPP的关系(此时第一标准单元和第二标准单元可以位于不同标准单元行，也可以位于同一标准单元行)。例如，紧密排列的多个第一格位与紧密排列的多个第二格位可以在第一方向上错开0.5个第一格位的距离，使得第一标准单元和第 二标准单元在第一方向上可以保持错开奇数个0.5的CPP的关系，即第一标准单元和第二标准单元在第一方向上可以错开0.5个CPP，或者可以错开1.5个CPP，或者可以错开2.5个CPP，在此不做穷举。以下均是以紧密排列的多个第一格位与紧密排列的多个第二格位在第一方向上错开0.5个第一格位的距离为例进行说明。值得注意的是，在确定第一格位和第二格位在第一方向上错开的距离时，可以以第一格位和第二格位在同一侧的边界作为基准进行比较，例如可以以第一格位和第二格位的左侧边界作为基准进行比较，同理，在确定第一标准单元和第二标准单元在第一方向上错开的距离时，可以以第一标准单元和第二标准单元的同一侧边界作为基准进行比较，例如可以以第一标准单元和第二标准单元的左侧边界作为基准进行比较。
在本申请实施例中，多个第一管脚和多个第二管脚沿着第二方向延伸，第一管脚位于第一标准单元上方且与第一标准单元耦接，第二管脚位于第二标准单元上方且与第二标准单元耦接。在设计时会创建多条等间距设置的走线轨道，走线轨道间距与CPP之间具有固定的比例关系，例如走线轨道间距：CPP可以为1:1，也可以为3:2或4:3，在此不做穷举。以下均是以走线轨道间距：CPP为1:1为例进行说明。由于紧密排列的多个第一格位与紧密排列的多个第二格位在第一方向上错开非整数个第一格位的距离，可以使得走线轨道相对于第一格位和第二格位的边界分别具有不同的偏移量，例如第二格位的边界与走线轨道对齐设置，第一格位的边界与走线轨道之间偏移0.5个CPP，这样可以保证将与第一标准单元耦接的第一管脚，以及与第二标准单元耦接的第二管脚均排布在走线轨道上。
本申请实施例提供的集成电路，在进行布图规划设计时，可以在同一个设计里创建多种类型的格位(sites)，即在同一个设计里同时创建紧密排列的多个第一格位和紧密排列的多个第二格位，第一格位仅能放置第一标准单元，第二格位仅能放置第二标准单元，紧密排列的多个第一格位与紧密排列的多个第二格位在第一方向上错开非整数个第一格位的距离，可以支持第一标准单元和第二标准单元在同一设计里进行混用。
在本申请实施例中，根据紧密排列的多个第一格位和紧密排列的多个第二格位的摆放位置关系，可以决定第一标准单元和第二标准单元所能排布的标准单元行的位置。具体地，可以将多个标准单元行中仅能放置第一标准单元的标准单元行称为第一标准单元行，将多个标准单元行中仅能放置第二标准单元的标准单元行称为第二标准单元行，将多个标准单元行中可以同时放置第一标准单元行和第二标准单元的标准单元行称为第三标准单元行，并且，可以根据设计需要，在一个或多个第三标准单元行中仅放置第一标准单元或第二标准单元。第一标准单元行、第二标准单元行和第三标准单元行的区别在于：第一标准单元行被划分为沿着第一方向紧密排列的多个第一格位；第二标准单元行被划分为沿着第一方向紧密排列的多个第二格位；第三标准单元行被分为沿着第一方向紧密排列的多个第一格位和沿着第一方向紧密排列的多个第二格位，且在第三标准单元行中的第一格位和第二格位交叠设置。且在第一方向上，紧密排列的多个第一格位与紧密排列的多个第二格位错开小于1个第一格位的距离。
在本申请实施例中，在同一个布图规划设计中，多个标准单元行可以由第一标准单元行和第二标准单元行构成，或者，多个标准单元行也可以由第一标准单元行、第二标准单元行和第三标准单元行构成，或者，多个标准单元行也可以由第一标准单元行和第三标准单元行构成，或者，多个标准单元行也可以由第二标准单元行和第三标准单元行构成，或者，多个标准单元行也可以仅由第三标准单元行构成。上述几种多个标准单元行的构成方式均可支持第一标准单元和第二标准单元在同一设计里进行混用。并且，在同一个布图规划设计中，第一格位与第二格位在第二方向上的高度可以相同也可以不同。下面通过具体实施例进行详细说明。
实施例一：
在本实施例中，多个标准单元行具体包括多个第一标准单元行和多个第二标准单元行，第一标准单元行中仅放置第一标准单元，第二标准单元行中仅放置第二标准单元。第一标准单元行划分为沿着第一方向紧密排列的多个第一格位，第二标准单元行划分为沿着第一方向紧密排列的多个第二格位。第一格位与第二格位在第一方向上的宽度相同且等于一个CPP，且第一格位与第二格位在第二方向上的高度相同。不同第一标准单元行中的第一格位对齐排列，不同第二标准单元行中的第二格位对齐排列。在第一方向上，第一标准单元行中的第一格位与第二标准单元行中的第二格位错开0.5个第一格位的距离。
在本实施例中，是以每两个第一标准单元行和每两个第二标准单元行为最小循环单位进行重复排列的方式进行举例说明，不作为实际布图规划设计的限制。
在本实施例中，一个第一标准单元可以占用一行第一标准单元行中的多个第一格位，或者，根据实 际设计需要，一个第一标准单元也可以占用多行第一标准单元行中的多个第一格位。同样，一个第二标准单元可以占用一行第二标准单元行中的多个第二格位，或者，根据实际设计需要，一个第二标准单元也可以占用多行第二标准单元行中的多个第二格位。
在本实施例中，在同一个第一标准单元行中，可以放置一个或多个第一标准单元，且相邻的两个第一标准单元之间可以紧密排列，即相邻的两个第一标准单元之间可以不间隔第一格位，相邻的两个第一标准单元之间也可以间隔一个或多个第一格位。同样，在同一个第二标准单元行中，可以放置一个或多个第二标准单元，且相邻的两个第二标准单元之间可以紧密排列，即相邻的两个第二标准单元之间可以不间隔第二格位，相邻的两个第二标准单元之间也可以间隔一个或多个第二格位。
在本实施例中，放置在不同第一标准单元行中的第一标准单元之间可以对齐排列，也可以错开整数个第一格位排列。同样，放置在不同第二标准单元行中的第二标准单元之间可以对齐排列，也可以错开整数个第二格位排列。
在本实施例中，放置在第一标准单元行中的第一标准单元与放置在第二标准单元行中的第二标准单元可以错开0.5、1.5、2.5……个第一格位。
实施例二：
在本实施例中，多个标准单元行具体包括多个第一标准单元行和多个第二标准单元行，第一标准单元行中仅放置第一标准单元，第二标准单元行中仅放置第二标准单元。第一标准单元行划分为沿着第一方向紧密排列的多个第一格位，第二标准单元行划分为沿着第一方向紧密排列的多个第二格位。第一格位与第二格位在第一方向上的宽度相同且等于一个CPP。与实施例一不同之处在于：第一格位与第二格位在第二方向上的高度不同，例如第一格位的高度可以大于第二格位的高度。不同第一标准单元行中的第一格位对齐排列，不同第二标准单元行中的第二格位对齐排列。在第一方向上，第一标准单元行中的第一格位与第二标准单元行中的第二格位错开0.5个第一格位的距离。
在本实施例中，是以每两个第一标准单元行和每两个第二标准单元行为最小循环单位进行重复排列的方式进行举例说明，不作为实际布图规划设计的限制。
在本实施例中，一个第一标准单元可以占用一行第一标准单元行中的多个第一格位，或者，根据实际设计需要，一个第一标准单元也可以占用多行第一标准单元行中的多个第一格位。同样，一个第二标准单元可以占用一行第二标准单元行中的多个第二格位，或者，根据实际设计需要，一个第二标准单元也可以占用多行第二标准单元行中的多个第二格位。
在本实施例中，在同一个第一标准单元行中，可以放置一个或多个第一标准单元，且相邻的两个第一标准单元之间可以紧密排列，即相邻的两个第一标准单元之间可以不间隔第一格位，相邻的两个第一标准单元之间也可以间隔一个或多个第一格位。同样，在同一个第二标准单元行中，可以放置一个或多个第二标准单元，且相邻的两个第二标准单元之间可以紧密排列，即相邻的两个第二标准单元之间可以不间隔第二格位，相邻的两个第二标准单元之间也可以间隔一个或多个第二格位。
在本实施例中，放置在不同第一标准单元行中的第一标准单元之间可以对齐排列，也可以错开整数个第一格位排列。同样，放置在不同第二标准单元行中的第二标准单元之间可以对齐排列，也可以错开整数个第二格位排列。
在本实施例中，放置在第一标准单元行中的第一标准单元与放置在第二标准单元行中的第二标准单元可以错开0.5、1.5、2.5……个第一格位。
实施例三：
在本实施例中，多个标准单元行具体包括多个第一标准单元行、多个第二标准单元行和多个第三标准单元行，第一标准单元行中仅放置第一标准单元，第二标准单元行中仅放置第二标准单元，第三标准单元行中可以放置第一标准单元和第二标准单元。第一标准单元行划分为沿着第一方向紧密排列的多个第一格位，第二标准单元行划分为沿着第一方向紧密排列的多个第二格位，第三标准单元行分为沿着第一方向紧密排列的多个第一格位和沿着第一方向紧密排列的多个第二格位，第三标准单元行中的第一格位和第二格位交叠设置。第一格位与第二格位在第一方向上的宽度相同且等于一个CPP，且第一格位与第二格位在第二方向上的高度相同。不同第一标准单元行中的第一格位对齐排列，不同第二标准单元行中的第二格位对齐排列。在第一方向上，第一标准单元行中的第一格位与第二标准单元行中的第二格位错开0.5个第一格位的距离。第三标准单元行中的第一格位与第一标准单元行中的第一格位对齐排列，每个第三标准单元行中的第二格位与第二标准单元行中的第二格位对齐排列。
在本实施例中，是以每两个第一标准单元行、每两个第二标准单元行和每两个第三标准单元行为最小循环单位进行重复排列的方式进行举例说明，不作为实际布图规划设计的限制。
在本实施例中，一个第一标准单元可以占用一行第一标准单元行或第三标准单元行中的多个第一格位，或者，根据实际设计需要，一个第一标准单元也可以占用多行第一标准单元行或第三标准单元行中的多个第一格位。同样，一个第二标准单元可以占用一行第二标准单元行或第三标准单元行中的多个第二格位，或者，根据实际设计需要，一个第二标准单元也可以占用多行第二标准单元行或第三标准单元行中的多个第二格位。
在本实施例中，在同一个第一标准单元行中，可以放置一个或多个第一标准单元，且相邻的两个第一标准单元之间可以紧密排列，即相邻的两个第一标准单元之间可以不间隔第一格位，相邻的两个第一标准单元之间也可以间隔一个或多个第一格位。同样，在同一个第二标准单元行中，可以放置一个或多个第二标准单元，且相邻的两个第二标准单元之间可以紧密排列，即相邻的两个第二标准单元之间可以不间隔第二格位，相邻的两个第二标准单元之间也可以间隔一个或多个第二格位。在同一个第三标准单元行中，可以仅放置一个或多个第一标准单元，且相邻的两个第一标准单元之间可以紧密排列，即相邻的两个第一标准单元之间可以不间隔第一格位，相邻的两个第一标准单元之间也可以间隔一个或多个第一格位。在同一个第三标准单元行中，也可以仅放置一个或多个第二标准单元，且相邻的两个第二标准单元之间可以紧密排列，即相邻的两个第二标准单元之间可以不间隔第二格位，相邻的两个第二标准单元之间也可以间隔一个或多个第二格位。在同一个第三标准单元行中，还可以同时放置一个或多个第一标准单元和一个或多个第二标准单元，且相邻的第一标准单元和第二标准单元间隔0.5、1.5、2.5……个第一格位。
在本实施例中，放置在不同第一标准单元行或第三标准单元行中的第一标准单元之间可以对齐排列，也可以错开整数个第一格位排列。同样，放置在不同第二标准单元行或第三标准单元行中的第二标准单元之间可以对齐排列，也可以错开整数个第二格位排列。
在本实施例中，放置在第一标准单元行或第三标准单元行中的第一标准单元与放置在第二标准单元行或不同的第三标准单元行中的第二标准单元可以错开0.5、1.5、2.5……个第一格位。
实施例四：
在本实施例中，多个标准单元行由多个第三标准单元行构成，第三标准单元行中可以放置第一标准单元和第二标准单元。第三标准单元行分为沿着第一方向紧密排列的多个第一格位和沿着第一方向紧密排列的多个第二格位，第三标准单元行中的第一格位和第二格位交叠设置。第一格位与第二格位在第一方向上的宽度相同且等于一个CPP，且第一格位与第二格位在第二方向上的高度相同。在第一方向上，一个第三标准单元行中的第一格位与第二格位可以错开0.5个第一格位的距离。不同第三标准单元行中的第一格位对齐排列，不同第三标准单元行中的第二格位对齐排列。
在本实施例中，一个第一标准单元可以占用一行第三标准单元行中的多个第一格位，或者，根据实际设计需要，一个第一标准单元也可以占用多行第三标准单元行中的多个第一格位。同样，一个第二标准单元可以占用一行第三标准单元行中的多个第二格位，或者，根据实际设计需要，一个第二标准单元也可以占用多行第三标准单元行中的多个第二格位。
在本实施例中，根据实际设计需要，在同一个第三标准单元行中，可以仅放置一个或多个第一标准单元，且相邻的两个第一标准单元之间可以紧密排列，即相邻的两个第一标准单元之间可以不间隔第一格位，相邻的两个第一标准单元之间也可以间隔一个或多个第一格位。在同一个第三标准单元行中，也可以仅放置一个或多个第二标准单元，且相邻的两个第二标准单元之间可以紧密排列，即相邻的两个第二标准单元之间可以不间隔第二格位，相邻的两个第二标准单元之间也可以间隔一个或多个第二格位。在同一个第三标准单元行中，还可以同时放置一个或多个第一标准单元和一个或多个第二标准单元，且相邻的第一标准单元和第二标准单元间隔0.5、1.5、2.5……个第一格位。
在本实施例中，放置在不同第三标准单元行中的第一标准单元之间可以对齐排列，也可以错开整数个第一格位排列。同样，放置在不同第三标准单元行中的第二标准单元之间可以对齐排列，也可以错开整数个第二格位排列。放置在不同第三标准单元行中的第一标准单元与第二标准单元可以错开0.5、1.5、2.5……个第一格位。
本申请实施例的第二方面，提供一种电子设备，包括电路板和集成电路，集成电路为第一方面提供任一可能设计的集成电路。
上述第二方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到的技术效果说明，这里不再重复赘述。
附图说明
图1A为本申请实施例提供的一种电子设备的框架示意图；
图1B为本申请实施例提供的一种SOC的框架示意图；
图2为数字芯片物理设计时创建摆放标准单元的格位的示意图；
图3A为相关技术提供的一种DDB标准单元的结构示意图；
图3B为相关技术提供的一种MDB标准单元的结构示意图；
图3C为相关技术提供的一种SDB标准单元的结构示意图；
图4A为相关技术提供的一种DDB标准单元与DDB标准单元拼接的结构示意图；
图4B为相关技术提供的一种MDB标准单元与MDB标准单元拼接的结构示意图；
图4C为相关技术提供的一种SDB标准单元与SDB标准单元拼接的结构示意图；
图5A为相关技术提供的一种SDB设计时格位与M2层走线轨道相对位置关系的示意图；
图5B为相关技术提供的一种MDB/DDB设计时格位与M2层走线轨道相对位置关系的示意图；
图6为本申请实施例提供的一种集成电路的结构示意图；
图7为实施例一中标准单元行的结构示意图；
图8为实施例一中第一标准单元和第二标准单元的一种排布示意图；
图9为图8中虚线框处的放大细节图；
图10为实施例一中第一标准单元和第二标准单元的另一种排布示意图；
图11为实施例二中标准单元行的结构示意图；
图12为实施例二中第一标准单元和第二标准单元的一种排布示意图；
图13为图12中虚线框处的放大细节图；
图14为实施例三中标准单元行的结构示意图；
图15为实施例三中第一标准单元和第二标准单元的一种排布示意图；
图16为图15中虚线框处的放大细节图；
图17为实施例四中标准单元行的结构示意图；
图18为实施例四中第一标准单元和第二标准单元的一种排布示意图。
附图标记：
1-盖板，2-显示屏，3-中框，4-后壳，31-承载板，32-边框，11-处理器，12-存储器，13-数模转换模
块，14-电源管理模块，15-接口模块，16-用户定义逻辑，17-总线，G-第一栅条，PA-P型有源区，NA-N型有源区，100-第一标准单元，200-第二标准单元，310-第一管脚，320-第二管脚，t-走线轨道，x-第一方向，y-第二方向，R-标准单元行，R1-第一标准单元行，R2-第二标准单元行，R3-第三标准单元行，S1-第一格位，S2-第二格位。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第二”、“第一”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第二”、“第一”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“相耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。术语“接触”可以是直接接触，也可以是通过中间媒介间接的接触。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请实施例提供一种的电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘(digital video disc，DVD)等。金融终端产品如为自动取款机(automated teller machine，ATM)机、自助办理业务的终端等。通信电子产品如为服务器、存储器、雷达、基站等通信设备。
以下为了方便说明，以电子设备为手机为例进行举例说明。如图1A所示，电子设备主要包括盖板1、显示屏2、中框3以及后壳4。后壳4和显示屏2分别位于中框3的两侧，且中框3和显示屏2设置于后壳4内，盖板1设置在显示屏2远离中框3的一侧，显示屏2的显示面朝向盖板1。
上述显示屏2可以是液晶显示屏(liquid crystal display，LCD)，在此情况下，液晶显示屏包括液晶显示面板和背光模组，液晶显示面板设置在盖板1和背光模组之间，背光模组用于为液晶显示面板提供光源。上述显示屏2也可以为有机发光二极管(organic light emitting diode，OLED)显示屏。由于OLED显示屏为自发光显示屏，因而无需设置背光模组。
上述中框3包括承载板31以及绕承载板31一周的边框32。上述电子设备还可以包括印刷电路板(printed circuit boards，PCB)、电池、摄像头等电子元器件，印刷电路板、电池、摄像头等电子元器件可以设置在承载板31上。
上述电子设备还可以包括设置于PCB上的系统级芯片(system on chip，SOC)、射频芯片等，PCB用于承载系统级芯片、射频芯片等，且与系统级芯片、射频芯片等电连接。
本申请实施例还提供一种SOC，示例的，如图1B所示，SOC包括处理器11、存储器12、数模转换模块(ADC/DAC)13、电源管理模块14、接口模块15以及用户定义逻辑16，上述结构可以与总线17耦接执行通信。
其中，处理器11可以执行具体的计算或任务，处理器11例如可以包括微处理器、中央处理器(CPU)、数字信号处理器DSP等。存储器12可以存储用于操作SOC所必需的数据。例如，存储器12可以为动态随机存取存储器(dynamic random access memory，DRAM)、静态随机存取存储器(static random-access memory，SRAM)、铁电随机存储器(ferroelectric random access memory)、磁性随机存取存储器(magnetic random access memory，MRAM)等。数模转换模块13用于实现数据信号与模拟信号之间的转换。电源管理模块14用于为SOC中各模块提供电源。接口模块15用于实现SOC与外部的通讯。用户定义逻辑16或者其他数字模块例如可以为通过现场可编程门阵列(field programmable gate array，FPGA)或者复杂可编程逻辑器件(complex programmable logic device，CPLD)形成的专用集成电路(application specific integrated circuit，ASIC)。总线17例如可以包括地址总线、控制总线、数据总线或扩展总线等。
CPU中的核里乱序/整数执行模块(out of order integer executive，OEX)、FPGA和CPLD等模块，例如可以借助电子设计自动化(electronic design automation，EDA)来实现版图设计(design)，EDA是指利用计算机辅助设计(computer aided design，CAD)软件，来完成超大规模集成电路(very large scale integration，VLSI)芯片的功能设计、综合、验证、物理设计(包括布局、布线、版图、设计规则检查等)等流程的设计方式。
使用EDA调取标准单元库中的标准单元，并进行标准单元间的拼接，以完成集成电路的设计。
如图2所示，在数字芯片物理设计时，需要创建摆放区域(placement area)用来摆放标准单元，摆放区域会被划分为多个行(rows)，每个行又会被划分为多个格位(sites)。sites是标准单元摆放时的最小单位，一个格位一般为工艺的最小可分辨格位，所有的标准单元都必须摆放在site上。
当前技术中，鳍式场效应晶体管(fin field-effect transistor，FinFET)技术节点的标准单元库中，按照标准单元(stand-cell，STC)之间隔离类型进行划分，可将标准单元分为三类：双扩散断裂(double diffusion break，DDB)标准单元、单扩散断裂(single diffusion break，SDB)标准单元以及混合扩散断 裂(mix diffusion break，MDB)标准单元。
如图3A所示，DDB标准单元包括多个第一栅条G、两个边缘栅、P型有源区(P active，PA)以及N型有源区(N active，NA)。边缘栅与第一栅条G同层设置、位于P型有源区PA和N型有源区NA上方，两个边缘栅位于多个第一栅条G的两侧。从俯视图上看，P型有源区PA和N型有源区NA位于两个边缘栅之间。第一栅条G、P型有源区PA以及N型有源区NA上方对应设置有连接孔(contact)，边缘栅上方没有设置连接孔。P型有源区PA、N型有源区NA、边缘栅和第一栅条位于两个隔离条(poly cut)之间。
从俯视图上看，DDB标准单元中边缘栅远离第一栅条G的外侧还设置有沟槽隔离区(shallow trench isolation，STI)，STI的边缘到边缘栅的距离大约为相邻第一栅条G之间间距(或者理解为是接触多晶硅间距(contact poly pitch，CPP))的一半(0.5CPP)。也就是说，为了实现相邻标准单元间P型有源区PA及N型有源区NA的隔离，DDB标准单元的边界为边缘栅再向外0.5CPP处，设置STI，为P型有源区PA及N型有源区NA的阻断留有间隙。
MDB标准单元指NMOS/PMOS混用了SDB/DDB两种扩散断裂，图3B仅示意了其中一种结构。如图3B所示，MDB标准单元包括多个第一栅条G、两个边缘栅、P型有源区PA以及N型有源区NA。两个边缘栅位于多个第一栅条G的两侧，第一栅条G位于P型有源区PA和N型有源区NA上方。边缘栅包括扩散断裂、阻隔栅以及将二者隔离开的阻隔部，扩散断裂贯穿P型有源区PA，起到阻隔作用，阻隔栅位于N型有源区NA上方。第一栅条G、P型有源区PA以及N型有源区NA上方对应设置有连接孔，边缘栅上方没有设置连接孔。P型有源区PA、N型有源区NA、边缘栅和第一栅条位于两个隔离条之间。
从俯视图上看，P型有源区PA延伸至边缘栅外，N型有源区NA外侧设置有STI，P型有源区PA的边缘到边缘栅的距离大约为0.5CPP，STI的边缘到边缘栅的距离大约为0.5CPP。也就是说，为了实现相邻标准单元间N型有源区NA的隔离，MDB标准单元的边界为边缘栅再向外0.5CPP处，设置STI，为N型有源区NA的阻断留有间隙。在MDB标准单元的边界为边缘栅再向外0.5CPP处的情况下，P型有源区PA已经被扩散断裂阻断，那么可在扩散断裂外侧形成有P型有源区PA；以提升标准单元的性能。
如图3C所示，SDB标准单元包括多个第一栅条G、两个边缘栅、P型有源区PA以及N型有源区NA。两个边缘栅位于多个第一栅条G的两侧，第一栅条G位于P型有源区PA和N型有源区NA上方。边缘栅为扩散断裂，贯穿P型有源区PA和N型有源区NA，P型有源区PA和N型有源区NA位于两个边缘栅之间。第一栅条G、P型有源区PA以及N型有源区NA上方对应设置有连接孔，边缘栅上方没有设置连接孔。P型有源区PA、N型有源区NA、边缘栅和第一栅条位于两个隔离条之间。
从俯视图上看，SDB标准单元中边缘栅的中心线作为SDB标准单元的边界。也就是说，P型有源区PA和N型有源区NA被扩散断裂阻断，SDB标准单元的边界无需向边缘栅外延伸。那么，DDB标准单元和MDB标准单元的左右两端比SDB标准单元的左右两端各分布扩展了约0.5CPP，1个CPP宽度一般等于1个site宽度。
DDB标准单元可以少用两张用于制备扩散断裂的掩膜板(mask)，具有较低的制备成本。SDB标准单元的有源区和绝缘层均无需延伸至边缘栅外，具有较小的设计面积。MDB标准单元利用版图依赖效应(layout dependent effect，LDE)，对DDB标准单元和SDB标准单元进行结合，实现MDB标准单元相对SDB标准单元或DDB标准单元的速度提升，使MDB标准单元具有更优异的性能。
三种类型的标准单元具有各自的优点，当前技术中，制造厂(foundry)会提供多套标准单元库，以满足不同产品的性能和功耗需求。通常情况下，有高性能(high performance，HP)标准单元库和高密度(high density，HD)标准单元库，HP标准单元库一般采用DDB标准单元实现，HD标准单元库一般基于SDB标准单元实现。
如表1所示，以CPU核中的乱序执行模块为例，对采用MDB标准单元实现该模块与采用SDB标准单元实现该模块进行性能功耗面积指标(performance power area，PPA)对比。分别以电源电压VDD为0.6V、温度为85℃、常规工艺角(typical corner，TT)为TT0为条件(也就是表1中的tt0p6v85c)，和以电源电压VDD为1.0V、温度为85℃、常规工艺角(typical corner，TT)为TT1为条件(也就是表1中的tt1p0v85c)，进行物理综合实现对比，发现MDB标准单元相对SDB标准单元虽然速度(speed)上有2％～8％的提升，但是MDB标准单元相对SDB标准单元面积增加5％～12％，使用MDB标准单元，会增加芯片的面积，从而造成芯片成本的增加。同时，MDB标准单元相对SDB标准单元的漏电(leakage)功耗增加25％以上，消费类产品来说漏电功耗是一个比较重要的指标，漏电功耗过大的增加是难以接受的。
表1：MDB相对SDB模块级PPA对比
因此，MDB标准单元、SDB标准单元以及DDB标准单元各有优略，三者能够在同一集成电路中混合使用，才能有效提升集成电路的性能。
但是，由于MDB标准单元和DDB标准单元的左右两端比SDB标准单元的左右两端各分布扩展了约0.5CPP，如图4A所示，两个DDB标准单元拼接时，拼接线位于两个DDB标准单元的边缘栅之间，拼接线距离边缘栅约0.5CPP。如图4B所示，两个MDB标准单元拼接时，拼接线位于两个MDB标准单元的边缘栅之间，拼接线距离边缘栅约0.5CPP。如图4C所示，两个SDB标准单元拼接时，拼接线位于SDB标准单元中边缘栅的中线上，两个SDB标准单元的边缘栅重合。由于拼接线的位置不同，因此，DDB/MDB标准单元无法与SDB标准单元放置在同一种row里。
在数字芯片设计时，还需要考虑与标准单元连接的纵向管脚(pin)在所属金属层中的摆放位置。为了保证标准单元连接的纵向管脚都摆放在走线轨道(track)上，同时考虑SDB/MDB/DDB布局(layout)，在标准单元设计时，需要对摆放标准单元的sites和放置纵向管脚的走线轨道的相对位置关系做约定：如图5A所示，放置与SDB连接的纵向管脚的走线轨道需要与摆放SDB的sites的边缘对齐设置，即走线轨道相对SDB的sites边界无偏移量(offset spacing)；如图5B所示，放置与MDB/DDB连接的纵向管脚的走线轨道需要与摆放MDB/DDB的sites的中线对齐设置，即走线轨道相对MDB/DDB的sites边界偏移0.5site。值得注意的是，图5A和图5B中仅是示意了site间距(pitch)(约等于CPP)：走线轨道间距(pitch)为1:1的情况，在实际设计时，两者的间距比例也可以为3:2(例如63nm：42nm)，或4:3(例如84nm：63nm)。
通常情况下，在数字芯片物理设计时，布图规划(floor plan)阶段会创建同一类型的sites(所有sites以相同的横向起点进行排列，也可称为对齐排列)，同时创建对应的走线轨道。由于走线轨道相对SDB和MDB/DDB的sites边界的偏移量不一样，归类为不同种类型的标准单元库，这就导致在同一集成电路内只能使用相同类型的标准单元库。即由于三种类型的标准单元的对齐方式不同，导致同等高度(或者高度为整数倍)不同类型的标准单元之间不能在一个集成电路中相互兼容，EDA工具不能支持MDB标准单元及DDB标准单元与SDB标准单元在同一个集成电路里进行直接混用。例如，无论是基于HP标准单元库，还是基于HD标准单元库，集成电路均是采用一种类型的标准单元设计而成。但是不同类型标准单元混用的混用扩散(hybrid diffusion break，HDB)可以得到更优化的设计。
为了解决在同一集成电路中不能兼容不同类型的标准单元的问题，本申请实施例提供一种采用新的布图规划设计的集成电路，以实现在同一集成电路中可以兼容不同类型的标准单元。
如图6所示，本申请实施例提供的一种集成电路，具体可以包括：多个第一标准单元100、多个第二标准单元200、多个第一管脚310和多个第二管脚320。具体地，第一标准单元100可以为单扩散断裂标准单元(SDB)，第二标准单元200可以为混合扩散断裂标准单元(MDB)或双扩散断裂标准单元(DDB)。或者，第二标准单元200可以为SDB，第一标准单元100可以为MDB或DDB。并且，在一个集成电路中，可以同时存在MDB和DDB，也可以仅存在MDB或DDB，在此不做限定。
在本申请实施例中，多个第一标准单元100和多个第二标准单元200排布在沿着第一方向x(也可以称为行方向或水平方向)延伸且沿着第二方向y(也可以称为列方向或竖直方向)排列的多个标准单元行R中。各第一标准单元100占用沿着第一方向x紧密排列的多个第一格位S1中的正整数个第一格位S1，且各第一标准单元100占用的第一格位S1的数量可以根据实际设计需要进行调节，例如一个第一标准单元100可以占用三个第一格位S1，另一个第一标准单元100可以占用五个第一格位S1，在此不做穷举；第二标准单元200占用沿着第一方向x紧密排列的多个第二格位S2中的正整数个第二格位S2，且各第二标准单元200占用的第二格位S2的数量可以根据实际设计需要进行调节，例如一个第二标准单元200可以占用两个第二格位S2，另一个第二标准单元200可以占用四个第二格位S2，在此不做穷举。
在本申请实施例中，第一格位S1和第二格位S2在第一方向x上的宽度需要为接触多晶硅间距(CPP)的整数倍。例如，第一格位S1与第二格位S2在第一方向x上的宽度可以相同，进一步可以等于一个 CPP，此时第一格位S1和第二格位S2均为工艺的最小可分辨格位。又如，第一格位S1在第一方向x上的宽度可以等于一个CPP，第二格位S2在第一方向x上的宽度可以等于两个或以上CPP，此时第一格位S1为工艺的最小可分辨格位。再如，第一格位S1在第一方向x上的宽度可以等于两个或以上CPP，第二格位S2在第一方向x上的宽度可以等于两个或以上CPP，且第一格位S1和第二格位S2在第一方向x上的宽度可以为相同数量的CPP，也可以为不同数量的CPP。以下均是以第一格位S1与第二格位S2在第一方向x上的宽度等于一个CPP为例进行说明。紧密排列的多个第一格位S1与紧密排列的多个第二格位S2需要在第一方向x上错开非整数个第一格位S1的距离，使得放置在第一格位S1上的第一标准单元100和放置在第二格位S2上的第二标准单元200在第一方向x上可以保持错开非整数个CPP的关系，即第一标准单元100和第二标准单元200在第一方向x上不会出现对齐排列的关系(此时第一标准单元100和第二标准单元200需要位于不同标准单元行R)，也不会出现错开整数个CPP的关系(此时第一标准单元100和第二标准单元200可以位于不同标准单元行R，也可以位于同一标准单元行R)。例如，紧密排列的多个第一格位S1与紧密排列的多个第二格位S2可以在第一方向x上错开0.5个第一格位S1的距离，使得第一标准单元100和第二标准单元200在第一方向x上可以保持错开奇数个0.5的CPP的关系，即第一标准单元100和第二标准单元200在第一方向x上可以错开0.5个CPP，或者可以错开1.5个CPP，或者可以错开2.5个CPP，在此不做穷举。以下均是以紧密排列的多个第一格位S1与紧密排列的多个第二格位S2在第一方向x上错开0.5个第一格位S1的距离为例进行说明。值得注意的是，在确定第一格位S1和第二格位S2在第一方向x上错开的距离时，可以以第一格位S1和第二格位S2在同一侧的边界作为基准进行比较，例如可以以第一格位S1和第二格位S2的左侧边界作为基准进行比较，同理，在确定第一标准单元100和第二标准单元200在第一方向x上错开的距离时，可以以第一标准单元100和第二标准单元200的同一侧边界作为基准进行比较，例如可以以第一标准单元100和第二标准单元200的左侧边界作为基准进行比较。
在本申请实施例中，多个第一管脚310和多个第二管脚320沿着第二方向y延伸，第一管脚310位于第一标准单元100上方且与第一标准单元100耦接，第二管脚320位于第二标准单元200上方且与第二标准单元200耦接。在设计时会创建多条等间距设置的走线轨道t，走线轨道t间距与CPP之间具有固定的比例关系，例如走线轨道t间距：CPP可以为1:1，也可以为3:2或4:3，在此不做穷举。以下均是以走线轨道t间距：CPP为1:1为例进行说明。由于紧密排列的多个第一格位S1与紧密排列的多个第二格位S2在第一方向x上错开非整数个第一格位S1的距离，可以使得走线轨道t相对于第一格位S1和第二格位S2的边界分别具有不同的偏移量，例如第二格位S2的边界与走线轨道t对齐设置，第一格位S1的边界与走线轨道t之间偏移0.5个CPP，这样可以保证将与第一标准单元100耦接的第一管脚310，以及与第二标准单元200耦接的第二管脚320均排布在走线轨道t上。
本申请实施例提供的集成电路，在进行布图规划设计时，可以在同一个设计里创建多种类型的格位(sites)，即在同一个设计里同时创建紧密排列的多个第一格位S1和紧密排列的多个第二格位S2，第一格位S1仅能放置第一标准单元100，第二格位S2仅能放置第二标准单元200，紧密排列的多个第一格位S1与紧密排列的多个第二格位S2在第一方向x上错开非整数个第一格位S1的距离，可以支持第一标准单元100和第二标准单元200在同一设计里进行混用。
在本申请实施例中，根据紧密排列的多个第一格位和紧密排列的多个第二格位的摆放位置关系，可以决定第一标准单元100和第二标准单元200所能排布的标准单元行的位置。具体地，可以将多个标准单元行R中仅能放置第一标准单元100的标准单元行称为第一标准单元行R1，将多个标准单元行R中仅能放置第二标准单元200的标准单元行称为第二标准单元行R2，将多个标准单元行R中可以同时放置第一标准单元行100和第二标准单元200的标准单元行称为第三标准单元行R3，并且，可以根据设计需要，在一个或多个第三标准单元行R3中仅放置第一标准单元100或第二标准单元200。第一标准单元行R1、第二标准单元行R2和第三标准单元行R3的区别在于：第一标准单元行R1被划分为沿着第一方向x紧密排列的多个第一格位S1；第二标准单元行R2被划分为沿着第一方向x紧密排列的多个第二格位S2；第三标准单元行R3被分为沿着第一方向x紧密排列的多个第一格位S1和沿着第一方向x紧密排列的多个第二格位S2，且在第三标准单元行R3中的第一格位S1和第二格位S2交叠设置。且在第一方向x上，紧密排列的多个第一格位S1与紧密排列的多个第二格位S2错开小于1个第一格位S1的距离。
在本申请实施例中，在同一个布图规划设计中，多个标准单元行可以由第一标准单元行R1和第二 标准单元行R2构成，或者，多个标准单元行也可以由第一标准单元行R1、第二标准单元行R2和第三标准单元行R3构成，或者，多个标准单元行也可以由第一标准单元行R1和第三标准单元行R3构成，或者，多个标准单元行也可以由第二标准单元行R2和第三标准单元行R3构成，或者，多个标准单元行也可以仅由第三标准单元行R3构成。上述几种多个标准单元行的构成方式均可支持第一标准单元100和第二标准单元200在同一设计里进行混用。并且，在同一个布图规划设计中，第一格位S1与第二格位S2在第二方向y上的高度可以相同也可以不同。下面通过具体实施例进行详细说明。
实施例一：
如图7至图10所示，在本实施例中，多个标准单元行R具体包括多个第一标准单元行R1和多个第二标准单元行R2，第一标准单元行R1中仅放置第一标准单元100，第二标准单元行R2中仅放置第二标准单元200。第一标准单元行R1划分为沿着第一方向x紧密排列的多个第一格位S1，第二标准单元行R2划分为沿着第一方向x紧密排列的多个第二格位S2。第一格位S1与第二格位S2在第一方向x上的宽度相同且等于一个CPP，且第一格位S1与第二格位S2在第二方向y上的高度相同。不同第一标准单元行R1中的第一格位S1对齐排列，不同第二标准单元行R2中的第二格位S2对齐排列。在第一方向x上，第一标准单元行R1中的第一格位S1与第二标准单元行R2中的第二格位S2错开0.5个第一格位S1的距离。
在本实施例中，是以每两个第一标准单元行R1和每两个第二标准单元行R2为最小循环单位进行重复排列的方式进行举例说明，不作为实际布图规划设计的限制。
在本实施例中，如图8所示，一个第一标准单元100可以占用一行第一标准单元行R1中的多个第一格位S1，或者，根据实际设计需要，如图10所示，一个第一标准单元100也可以占用多行第一标准单元行R1中的多个第一格位S1。同样，如图8所示，一个第二标准单元200可以占用一行第二标准单元行R2中的多个第二格位S2，或者，根据实际设计需要，如图10所示，一个第二标准单元200也可以占用多行第二标准单元行R2中的多个第二格位S2。
在本实施例中，在同一个第一标准单元行R1中，可以放置一个或多个第一标准单元100，且相邻的两个第一标准单元100之间可以紧密排列，即相邻的两个第一标准单元100之间可以不间隔第一格位S1，相邻的两个第一标准单元100之间也可以间隔一个或多个第一格位S1。同样，在同一个第二标准单元行R2中，可以放置一个或多个第二标准单元200，且相邻的两个第二标准单元200之间可以紧密排列，即相邻的两个第二标准单元200之间可以不间隔第二格位S2，相邻的两个第二标准单元200之间也可以间隔一个或多个第二格位S2。
在本实施例中，放置在不同第一标准单元行R1中的第一标准单元100之间可以对齐排列，也可以错开整数个第一格位S1排列。同样，放置在不同第二标准单元行R2中的第二标准单元200之间可以对齐排列，也可以错开整数个第二格位S2排列。
在本实施例中，放置在第一标准单元行R1中的第一标准单元100与放置在第二标准单元行R2中的第二标准单元200可以错开0.5、1.5、2.5……个第一格位S1。
实施例二：
如图11至图13所示，在本实施例中，多个标准单元行R具体包括多个第一标准单元行R1和多个第二标准单元行R2，第一标准单元行R1中仅放置第一标准单元100，第二标准单元行R2中仅放置第二标准单元200。第一标准单元行R1划分为沿着第一方向x紧密排列的多个第一格位S1，第二标准单元行R2划分为沿着第一方向x紧密排列的多个第二格位S2。第一格位S1与第二格位S2在第一方向x上的宽度相同且等于一个CPP。与实施例一不同之处在于：第一格位S1与第二格位S2在第二方向y上的高度不同，例如第一格位S1的高度可以大于第二格位S2的高度。不同第一标准单元行R1中的第一格位S1对齐排列，不同第二标准单元行R2中的第二格位S2对齐排列。在第一方向x上，第一标准单元行R1中的第一格位S1与第二标准单元行R2中的第二格位S2错开0.5个第一格位S1的距离。
在本实施例中，是以每两个第一标准单元行R1和每两个第二标准单元行R2为最小循环单位进行重复排列的方式进行举例说明，不作为实际布图规划设计的限制。
在本实施例中，一个第一标准单元100可以占用一行第一标准单元行R1中的多个第一格位S1，或者，根据实际设计需要，一个第一标准单元100也可以占用多行第一标准单元行R1中的多个第一格位S1。同样，一个第二标准单元200可以占用一行第二标准单元行R2中的多个第二格位S2，或者，根据实际设计需要，一个第二标准单元200也可以占用多行第二标准单元行R2中的多个第二格位S2。
在本实施例中，在同一个第一标准单元行R1中，可以放置一个或多个第一标准单元100，且相邻的两个第一标准单元100之间可以紧密排列，即相邻的两个第一标准单元100之间可以不间隔第一格位S1，相邻的两个第一标准单元100之间也可以间隔一个或多个第一格位S1。同样，在同一个第二标准单元行R2中，可以放置一个或多个第二标准单元200，且相邻的两个第二标准单元200之间可以紧密排列，即相邻的两个第二标准单元200之间可以不间隔第二格位S2，相邻的两个第二标准单元200之间也可以间隔一个或多个第二格位S2。
在本实施例中，放置在不同第一标准单元行R1中的第一标准单元100之间可以对齐排列，也可以错开整数个第一格位S1排列。同样，放置在不同第二标准单元行R2中的第二标准单元200之间可以对齐排列，也可以错开整数个第二格位S2排列。
在本实施例中，放置在第一标准单元行R1中的第一标准单元100与放置在第二标准单元行R2中的第二标准单元200可以错开0.5、1.5、2.5……个第一格位S1。
实施例三：
如图14至图16所示，在本实施例中，多个标准单元行R具体包括多个第一标准单元行R1、多个第二标准单元行R2和多个第三标准单元行R3，第一标准单元行R1中仅放置第一标准单元100，第二标准单元行R2中仅放置第二标准单元200，第三标准单元行R3中可以放置第一标准单元100和第二标准单元200。第一标准单元行R1划分为沿着第一方向x紧密排列的多个第一格位S1，第二标准单元行R2划分为沿着第一方向x紧密排列的多个第二格位S2，第三标准单元行R3分为沿着第一方向x紧密排列的多个第一格位S1和沿着第一方向x紧密排列的多个第二格位S2，第三标准单元行R3中的第一格位S1和第二格位S2交叠设置。第一格位S1与第二格位S2在第一方向x上的宽度相同且等于一个CPP，且第一格位S1与第二格位S2在第二方向y上的高度相同。不同第一标准单元行R1中的第一格位S1对齐排列，不同第二标准单元行R2中的第二格位S2对齐排列。在第一方向x上，第一标准单元行R1中的第一格位S1与第二标准单元行R2中的第二格位S2错开0.5个第一格位S1的距离。第三标准单元行R3中的第一格位S1与第一标准单元行R1中的第一格位S1对齐排列，每个第三标准单元行R3中的第二格位S2与第二标准单元行R2中的第二格位S2对齐排列。
在本实施例中，是以每两个第一标准单元行R1、每两个第二标准单元行R2和每两个第三标准单元行R3为最小循环单位进行重复排列的方式进行举例说明，不作为实际布图规划设计的限制。
在本实施例中，一个第一标准单元100可以占用一行第一标准单元行R1或第三标准单元行R3中的多个第一格位S1，或者，根据实际设计需要，一个第一标准单元100也可以占用多行第一标准单元行R1或第三标准单元行R3中的多个第一格位S1。同样，一个第二标准单元200可以占用一行第二标准单元行R2或第三标准单元行R3中的多个第二格位S2，或者，根据实际设计需要，一个第二标准单元200也可以占用多行第二标准单元行R2或第三标准单元行R3中的多个第二格位S2。
在本实施例中，在同一个第一标准单元行R1中，可以放置一个或多个第一标准单元100，且相邻的两个第一标准单元100之间可以紧密排列，即相邻的两个第一标准单元100之间可以不间隔第一格位S1，相邻的两个第一标准单元100之间也可以间隔一个或多个第一格位S1。同样，在同一个第二标准单元行R2中，可以放置一个或多个第二标准单元200，且相邻的两个第二标准单元200之间可以紧密排列，即相邻的两个第二标准单元200之间可以不间隔第二格位S2，相邻的两个第二标准单元200之间也可以间隔一个或多个第二格位S2。在同一个第三标准单元行R3中，可以仅放置一个或多个第一标准单元100，且相邻的两个第一标准单元100之间可以紧密排列，即相邻的两个第一标准单元100之间可以不间隔第一格位S1，相邻的两个第一标准单元100之间也可以间隔一个或多个第一格位S1。在同一个第三标准单元行R3中，也可以仅放置一个或多个第二标准单元200，且相邻的两个第二标准单元200之间可以紧密排列，即相邻的两个第二标准单元200之间可以不间隔第二格位S2，相邻的两个第二标准单元200之间也可以间隔一个或多个第二格位S2。在同一个第三标准单元行R3中，还可以同时放置一个或多个第一标准单元100和一个或多个第二标准单元200，且相邻的第一标准单元100和第二标准单元200间隔0.5、1.5、2.5……个第一格位S1。
在本实施例中，放置在不同第一标准单元行R1或第三标准单元行R3中的第一标准单元100之间可以对齐排列，也可以错开整数个第一格位S1排列。同样，放置在不同第二标准单元行R2或第三标准单元行R3中的第二标准单元200之间可以对齐排列，也可以错开整数个第二格位S2排列。
在本实施例中，放置在第一标准单元行R1或第三标准单元行R3中的第一标准单元100与放置在 第二标准单元行R2或不同的第三标准单元行R3中的第二标准单元200可以错开0.5、1.5、2.5……个第一格位S1。
实施例四：
如图17和图18所示，在本实施例中，多个标准单元行R由多个第三标准单元行R3构成，第三标准单元行R3中可以放置第一标准单元100和第二标准单元200。第三标准单元行R3分为沿着第一方向x紧密排列的多个第一格位S1和沿着第一方向x紧密排列的多个第二格位S2，第三标准单元行R3中的第一格位S1和第二格位S2交叠设置。第一格位S1与第二格位S2在第一方向x上的宽度相同且等于一个CPP，且第一格位S1与第二格位S2在第二方向y上的高度相同。在第一方向x上，一个第三标准单元行R3中的第一格位S1与第二格位S2可以错开0.5个第一格位S1的距离。不同第三标准单元行R3中的第一格位S1对齐排列，不同第三标准单元行R3中的第二格位S2对齐排列。
在本实施例中，一个第一标准单元100可以占用一行第三标准单元行R3中的多个第一格位S1，或者，根据实际设计需要，一个第一标准单元100也可以占用多行第三标准单元行R3中的多个第一格位S1。同样，一个第二标准单元200可以占用一行第三标准单元行R3中的多个第二格位S2，或者，根据实际设计需要，一个第二标准单元200也可以占用多行第三标准单元行R3中的多个第二格位S2。
在本实施例中，根据实际设计需要，在同一个第三标准单元行R3中，可以仅放置一个或多个第一标准单元100，且相邻的两个第一标准单元100之间可以紧密排列，即相邻的两个第一标准单元100之间可以不间隔第一格位S1，相邻的两个第一标准单元100之间也可以间隔一个或多个第一格位S1。在同一个第三标准单元行R3中，也可以仅放置一个或多个第二标准单元200，且相邻的两个第二标准单元200之间可以紧密排列，即相邻的两个第二标准单元200之间可以不间隔第二格位S2，相邻的两个第二标准单元200之间也可以间隔一个或多个第二格位S2。在同一个第三标准单元行R3中，还可以同时放置一个或多个第一标准单元100和一个或多个第二标准单元200，且相邻的第一标准单元100和第二标准单元200间隔0.5、1.5、2.5……个第一格位S1。
在本实施例中，放置在不同第三标准单元行R3中的第一标准单元100之间可以对齐排列，也可以错开整数个第一格位S1排列。同样，放置在不同第三标准单元行R3中的第二标准单元200之间可以对齐排列，也可以错开整数个第二格位S2排列。放置在不同第三标准单元行R3中的第一标准单元100与第二标准单元200可以错开0.5、1.5、2.5……个第一格位S1。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
基于同一发明构思，本申请实施例还提供了一种电子设备，包括本申请实施例提供的上述集成电路和电路板。由于该电子设备解决问题的原理与前述一种集成电路相似，因此该电子设备的实施可以参见前述集成电路的实施，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

  1. 一种集成电路，其特征在于，包括：
    多个第一标准单元和多个第二标准单元，所述多个第一标准单元和多个第二标准单元排布在沿着第一方向延伸且沿着第二方向排列的多个标准单元行中，所述第一标准单元和所述第二标准单元在所述第一方向上错开非整数个接触多晶硅间距CPP；所述第一标准单元占用沿着所述第一方向紧密排列的多个第一格位中的正整数个所述第一格位，所述第二标准单元占用沿着所述第一方向紧密排列的多个第二格位中的正整数个所述第二格位，所述紧密排列的多个第一格位与所述紧密排列的多个第二格位在所述第一方向上错开非整数个所述第一格位的距离，所述第一格位和所述第二格位在所述第一方向上的宽度为所述CPP的整数倍；
    沿着所述第二方向延伸的多个第一管脚和多个第二管脚，所述第一管脚位于所述第一标准单元上方且与所述第一标准单元耦接，所述第二管脚位于所述第二标准单元上方且与所述第二标准单元耦接，所述第一管脚和所述第二管脚均排布在多条等间距设置的走线轨道上。
  2. 如权利要求1所述的集成电路，其特征在于，所述第一格位与所述第二格位在所述第一方向上的宽度相同。
  3. 如权利要求2所述的集成电路，其特征在于，所述紧密排列的多个第一格位与所述紧密排列的多个第二格位在所述第一方向上错开0.5个第一格位的距离。
  4. 如权利要求1-3任一项所述的集成电路，其特征在于，所述多个标准单元行包括多个第一标准单元行和多个第二标准单元行，所述第一标准单元行中仅放置所述第一标准单元，所述第二标准单元行中仅放置所述第二标准单元；
    所述第一标准单元行划分为沿着所述第一方向紧密排列的多个所述第一格位，所述第二标准单元行划分为沿着所述第一方向紧密排列的多个所述第二格位；
    在所述第一方向上，所述第一标准单元行中的第一格位与所述第二标准单元行中的第二格位错开小于1个第一格位的距离，不同所述第一标准单元行中的第一格位对齐排列，不同所述第二标准单元行中的第二格位对齐排列。
  5. 如权利要求4所述的集成电路，其特征在于，多个所述第一格位与多个所述第二格位在所述第二方向上的高度相同。
  6. 如权利要求4所述的集成电路，其特征在于，多个所述第一格位与多个所述第二格位在所述第二方向上的高度不同。
  7. 如权利要求5所述的集成电路，其特征在于，所述多个标准单元行还包括多个第三标准单元行，所述第三标准单元行中放置所述第一标准单元和所述第二标准单元；
    所述第三标准单元行分为沿着所述第一方向紧密排列的多个所述第一格位和沿着所述第一方向紧密排列的多个所述第二格位，所述第三标准单元行中的所述第一格位和所述第二格位交叠设置，所述第三标准单元行中的所述第一格位与所述第一标准单元行中的所述第一格位对齐排列，每个所述第三标准单元行中的所述第二格位与所述第二标准单元行中的所述第二格位对齐排列。
  8. 如权利要求1-3任一项所述的集成电路，其特征在于，所述标准单元行划分为多个沿着所述第一方向紧密排列的多个所述第一格位和多个沿着所述第一方向紧密排列的多个所述第二格位，所述标准单元行中的所述第一格位和所述第二格位交叠设置且在所述第一方向上错开小于1个第一格位的距离，多个所述第一格位与多个所述第二格位在所述第二方向上的高度相同。
  9. 如权利要求1-8任一项所述的集成电路，其特征在于，所述第一标准单元为单扩散断裂标准单元，所述第二标准单元为混合扩散断裂标准单元或双扩散断裂标准单元。
  10. 一种电子设备，其特征在于，包括电路板和集成电路，所述集成电路为权利要求1-9任一项所述的集成电路。
PCT/CN2023/101325 2022-11-30 2023-06-20 集成电路及电子设备 WO2024113775A1 (zh)

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