WO2024113296A1 - 发光基板、显示面板和显示装置 - Google Patents

发光基板、显示面板和显示装置 Download PDF

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Publication number
WO2024113296A1
WO2024113296A1 PCT/CN2022/135777 CN2022135777W WO2024113296A1 WO 2024113296 A1 WO2024113296 A1 WO 2024113296A1 CN 2022135777 W CN2022135777 W CN 2022135777W WO 2024113296 A1 WO2024113296 A1 WO 2024113296A1
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WIPO (PCT)
Prior art keywords
layer
light
emitting
base substrate
substrate
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Ceased
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PCT/CN2022/135777
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English (en)
French (fr)
Inventor
李浪涛
郑克宁
徐健
胡椹
吴翰
白静璐
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2022/135777 priority Critical patent/WO2024113296A1/zh
Priority to CN202280004797.5A priority patent/CN121359621A/zh
Priority to US18/553,771 priority patent/US12696654B2/en
Publication of WO2024113296A1 publication Critical patent/WO2024113296A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a light-emitting substrate, a display panel and a display device.
  • light emitting diode displays have been widely used as self-luminous display devices. Unlike liquid crystal displays, light emitting diode display devices have self-emitting characteristics, and therefore may not include a separate light source, so that their thickness and weight can be reduced. In addition, light emitting diode display devices have various desired characteristics, such as low power consumption, high brightness, and fast response speed.
  • light emitting diode display devices generally include a plurality of transistors and a plurality of light emitting elements. In such light emitting diode display devices, transistors are connected to signal lines and can transmit drive current to the light emitting elements.
  • the transistor may include an active pattern including a channel region and a conductive region.
  • display devices are able to display images with high resolution, such as ultra-high definition (UHD) resolution.
  • UHD ultra-high definition
  • the driving voltage applied to the pixels may be uneven, resulting in differences in the displayed image and reducing the viewing quality.
  • a light-emitting substrate comprising:
  • a first power line arranged on the base substrate
  • an auxiliary electrode pattern arranged on a side of the first power line away from the base substrate and electrically connected to the first power line;
  • an organic material layer which is disposed on a surface of the auxiliary electrode pattern on a side away from the base substrate and has a first via hole penetrating the organic material layer, wherein the bottom of the first via hole exposes a portion of the surface of the auxiliary electrode pattern, wherein the portion of the surface of the auxiliary electrode pattern exposed at the bottom of the first via hole is a non-planar surface;
  • the first electrode layer is disposed on a side of the organic material layer away from the base substrate and is electrically connected to the auxiliary electrode pattern through the first via hole.
  • the auxiliary electrode pattern includes a first convex surface protruding along a first direction, and a portion of the surface of the first convex surface is exposed at the bottom of the first via hole, wherein the first direction is perpendicular to the plane of the base substrate and toward the light emitting side of the light emitting substrate.
  • the first convex surface has a curved surface remaining after a spherical surface is cut by a plane.
  • the light emitting substrate further comprises:
  • a first conductive pattern disposed between the auxiliary electrode pattern and the first power line, and electrically connected to the first power line through a via hole;
  • a flat layer disposed between the first conductive pattern and the first electrode layer, and having a groove on a surface away from the base substrate,
  • the auxiliary electrode pattern is at least partially disposed in the groove and is electrically connected to the first conductive pattern through a second via hole penetrating the planar layer.
  • the bottom of the groove includes a second convex surface protruding along the first direction, and an orthographic projection of the second convex surface on the base substrate at least partially overlaps with an orthographic projection of the first convex surface on the base substrate.
  • the second convex surface is conformal to the first convex surface.
  • the distance from the top of the second convex surface to the plane where the lowest position of the bottom of the groove is located is H1
  • the height from the notch plane of the groove to the plane where the lowest position of the bottom of the groove is located is H2
  • the thickness of the auxiliary electrode pattern corresponding to the position of the top of the second convex surface is T, and H1, H2 and T satisfy: H2 ⁇ H1+T ⁇ 2*H2.
  • H1, H2 and T satisfy: H2 ⁇ H1+T ⁇ 1.5*H2.
  • the maximum length of the second convex surface is L1
  • the minimum distance between the second convex surface and the second via hole is L2
  • L1 and L2 satisfy: 0.5*L1 ⁇ L2 ⁇ L1, wherein the second direction is a direction parallel to the plane of the substrate and pointing from the center of the second convex surface to the center of the second via hole.
  • the maximum length of the second convex surface is L1
  • the maximum length of the first via hole is L3, L1 and L3 satisfy: 0.25*L1 ⁇ L3 ⁇ L1
  • the second direction is a direction parallel to the plane of the substrate and pointing from the center of the second convex surface to the center of the second via hole.
  • the slope angle of the bottom edge of the second convex surface is ⁇ , and ⁇ satisfies: 20° ⁇ 45°.
  • the light emitting substrate further comprises:
  • a pixel definition layer located on a side of the planar layer away from the base substrate, and having a first opening
  • the first electrode layer is arranged on the surface of the pixel definition layer away from the base substrate, and at least covers the side walls of the organic material layer and the first opening, and the slope angle of the pixel definition layer at the bottom edge of the first opening is ⁇ , and ⁇ satisfies: 20° ⁇ 30°.
  • the light emitting substrate further comprises:
  • a pixel unit including a thin film transistor and a light emitting device
  • the light-emitting device comprises a first electrode, a light-emitting layer and a second electrode layer, the thin film transistor is located between the base substrate and the planar layer, the first electrode is located on the side of the planar layer away from the base substrate, and is electrically connected to the thin film transistor through a third via hole penetrating the planar layer, at least part of the light-emitting layer is located on the surface of the first electrode away from the base substrate, the second electrode layer is located on the side of the light-emitting layer away from the base substrate, the pixel definition layer also has a second opening, at least part of the light-emitting layer is located in the second opening, and the second electrode layer is arranged on the surface of the pixel definition layer away from the base substrate, and at least covers the light-emitting layer and the side walls of the second opening.
  • the slope angle of the pixel definition layer at the bottom edge of the second opening is ⁇ , and ⁇ and ⁇ satisfy: ⁇ .
  • the first electrode and the auxiliary electrode pattern are located in the same layer and are made of the same material
  • the light-emitting layer and the organic material layer are located in the same layer and are made of the same material
  • the second electrode layer and the first electrode layer are located in the same layer and are made of the same material.
  • the light emitting substrate further comprises:
  • a second power line is provided on the base substrate.
  • a second conductive pattern is disposed on a side of the third insulating layer away from the base substrate and is electrically connected to the second power line through a via hole penetrating the third insulating layer, the second insulating layer and a portion of the first insulating layer;
  • the first insulating layer covers the first power line and the second power line
  • the fourth insulating layer covers the first conductive pattern and the second conductive pattern
  • the second conductive pattern is electrically connected to the thin film transistor.
  • the thin film transistor includes a gate, an active layer, a source and a drain.
  • the active layer is arranged on the surface of the first insulating layer away from the substrate, the source and the drain are arranged on the surface of the third insulating layer away from the substrate, and are electrically connected to the active layer through vias penetrating the third insulating layer and part of the second insulating layer, respectively.
  • the gate insulating layer covers the active layer, and the gate is arranged on the surface of the second insulating layer away from the substrate.
  • a display panel comprising:
  • the aforementioned light-emitting substrate, driver IC and power supply circuit The aforementioned light-emitting substrate, driver IC and power supply circuit.
  • the display panel further comprises:
  • the color conversion substrate is located on the light emitting side of the light emitting substrate.
  • a display device including: the aforementioned display panel.
  • FIG1 is a schematic diagram of a three-dimensional structure of an embodiment of a display panel disclosed in the present invention.
  • FIG2 is a schematic diagram of the AA section in FIG1;
  • FIG3 is a cross-sectional schematic diagram of a display area in an embodiment of a display panel disclosed herein;
  • FIG4 is a cross-sectional schematic diagram of a display area in another embodiment of a display panel disclosed herein;
  • FIG5 is a schematic diagram of partitions of an embodiment of a light-emitting substrate disclosed in the present invention at a viewing angle perpendicular to the plane where the light-emitting substrate is located;
  • FIG6 is a schematic diagram of the formation of particulate foreign matter in the auxiliary electrode region of the light-emitting substrate due to laser ablation of the electroluminescent material in the related art
  • FIG7 is a schematic diagram of the BB section in FIG3;
  • FIG8 is a schematic diagram of another example of the BB section in FIG3;
  • FIG9 is an exploded schematic diagram of a local structure of an auxiliary electrode region of an embodiment of a light-emitting substrate disclosed herein;
  • FIG10 is a schematic diagram showing the size relationship of the grooves of the flat layer of an embodiment of the light-emitting substrate disclosed in the present invention at a viewing angle perpendicular to the plane where the light-emitting substrate is located;
  • FIG11 is a schematic diagram showing the size relationship of the grooves of the flat layer of another embodiment of the light-emitting substrate disclosed in the present invention at a viewing angle perpendicular to the plane where the light-emitting substrate is located;
  • FIG12 is a schematic diagram of a manufacturing process of an embodiment of a light-emitting substrate disclosed herein;
  • FIGS. 13A-13G are partial process diagrams of a manufacturing process example of a light-emitting substrate embodiment of the present disclosure.
  • 14A-14H are partial process schematic diagrams of an example of a manufacturing process of an embodiment of the light-emitting substrate disclosed in the present invention.
  • a specific device when a specific device is described as being located between a first device and a second device, there may or may not be an intermediate device between the specific device and the first device or the second device.
  • the specific device When a specific device is described as being connected to other devices, the specific device may be directly connected to the other device without an intermediate device, or may not be directly connected to the other device but have an intermediate device.
  • FIG. 1 is a schematic diagram of a three-dimensional structure of an embodiment of a display panel of the present disclosure.
  • FIG. 2 is a schematic diagram of the AA section in FIG. 1 .
  • the display panel DP includes a light-emitting substrate LS and a color conversion substrate CS.
  • the display panel may further include a driver IC (Integrated Circuit) and a power supply circuit.
  • the display panel DP includes a display area DA for displaying an image and a non-display area NDA for not displaying an image, and the non-display area NDA surrounds the outside of the display area DA.
  • the non-display area NDA may enclose the display area DA and may be located outside the display area DA in at least one direction.
  • the display panel DP may further include a filling layer FL filling the space between the light-emitting substrate LS and the color conversion substrate CS, and a sealing layer SL for sealing the space between the light-emitting substrate LS and the color conversion substrate CS.
  • the first direction may be defined as a direction perpendicular to the plane where the base substrate of the light-emitting substrate is located and toward the light-emitting side of the light-emitting substrate, such as the direction z in FIGS. 1 and 2 .
  • the second direction and the third direction (such as the x direction and the y direction in FIG. 1 ) are perpendicular to each other and are both perpendicular to the plane where the base substrate of the light-emitting substrate is located.
  • the color conversion substrate CS may be arranged opposite to the light-emitting substrate LS.
  • the color conversion substrate CS may include a color conversion pattern for converting the color of incident light.
  • the color conversion pattern may include at least one of a color filter and a wavelength conversion pattern.
  • the sealing layer SL may be located between the light emitting substrate LS and the color conversion substrate CS and in the non-display area NDA.
  • the color conversion substrate CS may be disposed along the edges of the light emitting substrate LS and the color conversion substrate CS in the non-display area NDA to surround the periphery of the display area DA in a plan view or around the periphery of the display area DA.
  • the sealing layer SL may be made of an organic material, such as an epoxy-based resin, but the present disclosure is not limited thereto.
  • the filling layer FL may be located and fill the space between the light emitting substrate LS and the color conversion substrate CS and surrounded by the sealing layer SL.
  • the filler FL may be made of a material capable of transmitting light.
  • the filling layer FL may be made of an organic material, for example, a silicon-based organic material or an epoxy-based organic material, etc., but is not limited thereto. In some embodiments, the filling layer FL may be omitted.
  • Fig. 3 is a schematic cross-sectional view of a display area in one embodiment of a display panel of the present disclosure.
  • Fig. 4 is a schematic cross-sectional view of a display area in another embodiment of a display panel of the present disclosure.
  • the display panel can be obtained by a box-matching method, that is, a light-emitting substrate LS and a color conversion substrate CS are separately manufactured, and then the light-emitting substrate LS and the color conversion substrate CS are bonded together by a filling layer FL.
  • the light-emitting substrate LS may be an OLED backplane.
  • the light-emitting substrate LS may include a first substrate SUB1, an insulating structure INL, a pixel definition layer PDL, a thin film encapsulation structure TFE (e.g., stacked encapsulation layers ENL1, ENL2, ENL3), a plurality of light-emitting devices (e.g., LD1, LD2, LD3) and corresponding transistors (e.g., T1, T2, T3).
  • the light-emitting device may include a plurality of light-emitting diodes, such as a blue light-emitting diode; or a two-color light-emitting diode, such as a light-emitting diode having a blue and a green light-emitting layer; or a white light-emitting diode, such as a light-emitting diode having a plurality of light-emitting layers of different colors that emit white light after being combined.
  • a plurality of light-emitting diodes such as a blue light-emitting diode
  • a two-color light-emitting diode such as a light-emitting diode having a blue and a green light-emitting layer
  • a white light-emitting diode such as a light-emitting diode having a plurality of light-emitting layers of different colors that emit white light after being combined.
  • the light emitting devices LD1, LD2, and LD3 may correspond to three sub-pixels in the pixel unit, wherein the light emitting device LD1 may include an anode AE1, a light emitting layer OL, and a cathode CE, the light emitting device LD2 may include an anode AE2, a light emitting layer OL, and a cathode CE, and the light emitting device LD3 may include an anode AE3, a light emitting layer OL, and a cathode CE.
  • the anodes AE1, AE2, and AE3 are electrically connected to the transistors T1, T2, and T3, respectively.
  • the color conversion substrate CS is disposed on the light-exiting side of the light-emitting substrate LS.
  • the color conversion substrate CS may include a color conversion layer and a light-transmitting pattern TP located in a plurality of openings defined by the partition wall PW.
  • the color conversion layer includes a first color conversion pattern CCP1 and a second color conversion pattern CCP2.
  • the color conversion substrate CS may include color filters CF1, CF2, and CF3 in a plurality of openings defined by the light-shielding pattern BM.
  • the color conversion substrate CS also includes a second base substrate SUB2, a first cover plate CAP1, and a second cover plate CAP2.
  • the partition wall PW, the color conversion layer, and the light-transmitting pattern TP are located between the first cover plate CAP1 and the second cover plate CAP2, and the light-shielding pattern BM, the color filters CF1, CF2, and CF3 are located between the second base substrate SUB2 and the first cover plate CAP1.
  • the first color conversion pattern CCP1 may emit light by converting or shifting the peak wavelength of incident light to another specific peak wavelength.
  • the first color conversion pattern CCP1 may convert the emission light provided from the first light emitting device LD1 into red light having a peak wavelength in the range of about 610 nm to about 650 nm.
  • the first color conversion pattern CCP1 may include a first base resin and a first color conversion material dispersed in the first base resin, and may include first scattering particles dispersed in the first base resin.
  • the second color conversion pattern CCP2 may emit light by converting or shifting the peak wavelength of incident light to another specific peak wavelength.
  • the second wavelength conversion pattern CCP2 may convert the emission light provided from the second light emitting element LD2 into green light having a peak wavelength in the range of about 510 nm to about 550 nm.
  • the second color conversion pattern CCP2 may include a second base resin and a second color conversion material dispersed in the second base resin, and may include first scattering particles dispersed in the second base resin.
  • the first color conversion material and the second color conversion material may include semiconductor nanocrystal materials, which may emit light of a specific color when electrons transition from a conduction band to a valence band.
  • the quantum dots may have any shape as long as the shape is commonly used in the art, and may specifically be spherical, conical, multi-armed or cubic nanoparticles, or may be nanotubes, nanowires, nanofibers or nanoparticles, etc.
  • the light-emitting substrate may also be a white light OLED backplane including three-color sub-pixels, and a color filter layer CF is provided on the light-emitting side thereof.
  • the display panel can be formed by an ON-EL method, wherein the light-emitting substrate LS is substantially the same as FIG3 , a partition wall PW is made on the thin film encapsulation structure TFE of the light-emitting substrate LS, and then a color conversion layer and a light-transmitting pattern TP are printed in a plurality of openings defined by the partition wall PW.
  • the color conversion substrate CS further includes color filters CF1, CF2, and CF3, a first cover plate CAP1, and a second cover plate CAP2 in a plurality of openings defined by a light-shielding pattern BM.
  • the partition wall PW, the color conversion layer, and the light-transmitting pattern TP are located between the first cover plate CAP1 and the second cover plate CAP2, and the light-shielding pattern BM, the color filters CF1, CF2, and CF3 are located on the side of the first cover plate CAP1 away from the light-emitting substrate LS.
  • FIG5 is a schematic diagram of the partitioning of an embodiment of the light-emitting substrate of the present disclosure at a viewing angle perpendicular to the plane where the light-emitting substrate is located.
  • the light-emitting substrate LS may include a display area A, and a non-display area NA surrounding the outside of the display area A.
  • the display area A of the light-emitting substrate LS may correspond to the display area DA of the display panel DP, and the non-display area NA of the light-emitting substrate LS may correspond to the non-display area NDA of the display panel DP.
  • the light-emitting substrate LS includes a plurality of pixel areas A1 and a plurality of auxiliary electrode areas A2 in the display area A. The plurality of pixel areas A1 and the auxiliary electrode areas A2 may be arranged alternately along the direction y.
  • the light-emitting substrate may include a plurality of pixel units 90 in each pixel region A1.
  • Each pixel unit 90 may include at least one sub-pixel, such as a plurality of sub-pixels of one color, two colors, or three colors.
  • the plurality of pixel units 90 may be arranged in sequence along direction x.
  • each pixel unit 90 includes a first sub-pixel 901, a second sub-pixel 902, and a third sub-pixel 903 of three different colors.
  • the first sub-pixel 901 is a blue sub-pixel
  • the second sub-pixel 902 is a green sub-pixel
  • the third sub-pixel 903 is a red sub-pixel.
  • each pixel unit 90 may further include a fourth sub-pixel, for example, the fourth sub-pixel is a white sub-pixel.
  • the light-emitting substrate includes at least one auxiliary electrode pattern 3 in each auxiliary electrode region A2.
  • Each pixel unit 90 may correspond to one auxiliary electrode pattern 3, or may correspond to multiple auxiliary electrode patterns 3, or each auxiliary electrode pattern 3 may correspond to multiple pixel units 90.
  • at least part of the auxiliary electrode patterns 3 in some auxiliary electrode regions A2 are laser ablated to be electrically connected to the cathode power line.
  • multiple auxiliary electrode patterns 3 in multiple auxiliary electrode patterns 3 in one auxiliary electrode region, multiple auxiliary electrode patterns 3 may be arranged at intervals along the direction x, wherein at least part of the auxiliary electrode patterns 3 are laser ablated and electrically connected to the cathode power line.
  • FIG6 is a schematic diagram of the formation of particulate foreign matter in the auxiliary electrode area of the light-emitting substrate due to laser ablation of the electroluminescent material in the related art.
  • the cathode power line 1a is set in the display area of the light-emitting substrate, and the cathode power line 1a and the cathode material layer 1d are electrically connected through the electrode pattern 1b (i.e., the auxiliary electrode pattern) located in the display area, so as to connect the cathode signal (VSS) to the cathode material layer 1d.
  • the electrode pattern 1b i.e., the auxiliary electrode pattern
  • the related art deposits an organic electroluminescent (EL) material 1c on the surface of the electrode pattern 1b after electrically connecting the electrode pattern 1b with the cathode power line 1a, and then ablates the EL material 1c by laser to expose the electrode pattern 1b, so as to subsequently partially deposit the cathode material layer 1d on the exposed electrode pattern 1b, thereby realizing that the cathode signal is directly connected to the cathode material layer 1d through in-plane overlap.
  • EL organic electroluminescent
  • the inventors have found that when the laser ablates the EL material 1c, foreign particles 1e are generated. These foreign particles 1e are deposited on the pixel definition layer 1f, the EL material and the exposed electrode pattern 1b, affecting the reliability of the package. At the same time, since the ablation area of the EL material is relatively limited, the deposition of foreign particles will also cause the cathode material layer 1d to have insufficient contact area with the anode material layer 1b and fail to form an effective overlap with the anode material layer 1b, resulting in a higher voltage drop of the cathode signal, thereby affecting the uniformity of the display.
  • the packaging performance may be weakened in the area where it gathers.
  • an embodiment of the present disclosure provides a light-emitting substrate capable of achieving effective overlapping of auxiliary electrode regions.
  • FIG7 is a schematic diagram of the BB section in FIG3 .
  • FIG7 includes a cross-sectional structure in the pixel area A1 and the auxiliary electrode area A2.
  • the light-emitting substrate LS provided in the embodiment of the present disclosure includes: a base substrate 1, a first power line 21, an auxiliary electrode pattern 3, an organic material layer 4 and a first electrode layer 5.
  • the base substrate 1 can be made of a light-transmitting material (for example, inorganic glass, organic glass, a plastic substrate or other organic material substrate).
  • the base substrate 1 can be rigid or flexible.
  • a buffer layer or an insulating layer may also be included on the base substrate 1 to provide a substrate surface with better performance.
  • the light emitting substrate LS may also include a second power line 22 located on the base substrate 1 and spaced apart from the first power line 21.
  • the first power line 21 and the second power line 22 may be signal lines formed by stacking a single layer or multiple layers of metal wires, and have the same or different widths.
  • the first power line 21 and the second power line 22 have different potentials, for example, the first power line 21 provides a cathode signal VSS, and the second power line 22 provides an anode signal VDD.
  • the light emitting substrate LS may further include a first insulating layer 95 (e.g., a buffer layer), a second insulating layer 96 (e.g., a gate insulating layer), a third insulating layer 97 (e.g., an interlayer dielectric layer), and a fourth insulating layer 98 (e.g., a passivation layer) sequentially stacked on the base substrate 1.
  • the first insulating layer 95 covers the first power line 21 and the second power line 22.
  • the light-emitting substrate LS may also include a plurality of thin film transistors (TFTs) 91 located on the substrate 1.
  • the thin film transistor 91 may be a thin film transistor including polysilicon or a thin film transistor including an oxide semiconductor, and may have a top gate or bottom gate structure. As shown in FIG7 , in some embodiments, the thin film transistor 91 includes a gate 911, an active layer 912, a source 913, and a drain 914.
  • the active layer 912 is disposed on the surface of the first insulating layer 95 away from the substrate 1.
  • the source 913 and the drain 914 are disposed on the surface of the third insulating layer 97 away from the substrate 1, and are electrically connected to the active layer 912 through vias penetrating the third insulating layer 97 and a portion of the second insulating layer 96.
  • the second insulating layer 96 is disposed on the surface of the first insulating layer 95 away from the substrate 1, and covers the active layer 912.
  • the gate 911 is disposed on the surface of the second insulating layer 96 away from the substrate 1.
  • the light-emitting substrate LS may further include a first conductive pattern 61 and a second conductive pattern 62 located on a side of the third insulating layer 97 away from the base substrate 1.
  • the first conductive pattern 61 is located between the auxiliary electrode pattern 3 and the first power line 21, and is electrically connected to the first power line 21 through a via hole penetrating the third insulating layer 97, the second insulating layer 96, and a portion of the first insulating layer 95.
  • the second conductive pattern 62 is electrically connected to the second power line 22 through a via hole penetrating the third insulating layer 97, the second insulating layer 96, and a portion of the first insulating layer 95.
  • the fourth insulating layer 98 covers the first conductive pattern 61 and the second conductive pattern 62, and the second conductive pattern 62 is electrically connected to the thin film transistor 91.
  • the first conductive pattern 61 and the second conductive pattern 62 may be made in the same layer as the source 913 and the drain 914 in the thin film transistor 91.
  • the light-emitting substrate LS may include a flat layer 7 located on a side of the fourth insulating layer 98 away from the base substrate 1.
  • the flat layer 7 may provide a flat surface in the pixel area A1 and may be formed of an organic layer.
  • the flat layer 7 may include acrylic resin, epoxy resin, imide resin, or ester resin, etc.
  • the flat layer 7 and a portion of the fourth insulating layer 98 may have a third via hole V3 extending therethrough so as to expose the drain electrode 914 of the thin film transistor 91 for electrical connection.
  • the flat layer 7 and a portion of the fourth insulating layer 98 may be provided with a second via hole V2 extending therethrough so as to expose the first conductive pattern 61 for electrical connection.
  • the light-emitting substrate LS may include a plurality of light-emitting devices LD.
  • the light-emitting device LD includes a first electrode 92, a light-emitting layer 93, and a second electrode layer 94.
  • the first electrode 92 is located on a side of the planar layer 7 away from the base substrate 1, and is electrically connected to the drain 914 of the thin film transistor 91 through a third via hole V3.
  • the light-emitting layer 93 is located on a surface of the first electrode 92 away from the base substrate 1, and the second electrode layer 94 is located on a side of the light-emitting layer 93 away from the base substrate 1.
  • the multiple light-emitting devices LD can share a light-emitting layer 93.
  • the light-emitting layer 93 can also have the shape of a continuous film layer located in the pixel area A1 and the auxiliary electrode area A2.
  • the light-emitting layer 93 includes an organic light-emitting layer, and can also include multiple other stacked auxiliary layers, such as a hole transport layer, an electron transport layer, a charge generation layer, and the like.
  • the organic light-emitting layer may include multiple stacked layers, such as a first light-emitting layer and a second light-emitting layer.
  • the first light-emitting layer and the second light-emitting layer can emit light of the same color, for example, both emit blue light.
  • the first light-emitting layer and the second light-emitting layer can also emit light of different colors, for example, the first light-emitting layer emits blue light and the second light-emitting layer emits green light.
  • the auxiliary electrode pattern 3 and the first electrode 92 can be made in the same layer.
  • the auxiliary electrode pattern 3 is in contact with the first conductive pattern 61 through the second via hole V2 to achieve electrical connection, thereby achieving electrical connection with the first power line 21 through the first conductive pattern 61 .
  • FIG8 is a schematic diagram of another example of the BB section in FIG3.
  • the organic material layer 4 is disposed on the surface of the auxiliary electrode pattern 3 on the side away from the base substrate 1, and has a first via hole V1 penetrating the organic material layer 4.
  • the bottom of the first via hole V1 exposes a portion of the surface of the auxiliary electrode pattern 3, wherein the portion of the surface of the auxiliary electrode pattern 3 exposed at the bottom of the first via hole V1 is a non-planar surface, such as a concave surface, a convex surface or a curved surface.
  • a non-planar surface Compared with a flat surface, a non-planar surface has a larger surface area, which can increase the overlap area between the first electrode layer 5 and the auxiliary electrode pattern 3, thereby effectively reducing the voltage drop of the cathode signal provided by the first power line 21.
  • the auxiliary electrode pattern 3 includes a first convex surface 31 protruding along a first direction, and a portion of the surface of the first convex surface 31 is exposed at the bottom of the first via hole V1, wherein the first direction is a direction perpendicular to the plane where the base substrate is located and toward the light-emitting side of the light-emitting substrate, such as the z direction in FIG7 .
  • the first convex surface 31 can effectively reduce the aggregation of particles on the auxiliary electrode pattern 3 after the EL material is ablated, thereby improving the overlap quality between the first electrode layer 5 and the auxiliary electrode pattern 3.
  • the auxiliary electrode pattern 3 includes a first concave surface 33 concave in the opposite direction of the first direction.
  • the first convex surface 31 with a larger surface area can still achieve sufficient overlapping area between the first electrode layer 5 and the auxiliary electrode pattern 3 to ensure effective overlapping, thereby reducing the resistance from the first power line 21 to the first electrode layer 5, and further reducing the voltage drop of the power signal provided by the first power line 21.
  • the power signal provided by the first power line 21 is a cathode signal (VSS).
  • the first electrode layer 5 overlaps the auxiliary electrode pattern 3 through the first convex surface 31 exposed at the bottom of the first via V1, which can effectively reduce the voltage drop of the cathode signal provided by the first power line 21.
  • the power signal provided by the first power line 21 is an anode signal (VDD).
  • the first electrode layer 5 overlaps the auxiliary electrode pattern 3 through the first convex surface 31 exposed at the bottom of the first via V1, which can effectively reduce the voltage drop of the anode signal provided by the first power line 21.
  • the first convex surface 31 can be a curved surface remaining after a sphere is cut by a plane. This surface is relatively smooth, not easy to form obvious step differences, and easier to process and form.
  • the first convex surface can also be a truncated cone or a truncated cone convex surface.
  • the auxiliary electrode pattern 3 and the organic material layer 4 can be formed by mask evaporation, and the first electrode layer 5 can be formed by full-surface evaporation and be continuous in the surface.
  • FIG9 is an exploded schematic diagram of a local structure of an auxiliary electrode region of an embodiment of the light-emitting substrate of the present disclosure.
  • the planar layer 7 has a groove 71 on a surface of a side away from the base substrate 1.
  • the auxiliary electrode pattern 3 is at least partially disposed in the groove 71 and is electrically connected to the first conductive pattern 61 through a second via V2 penetrating the planar layer 7.
  • the groove 71 of the planar layer 7 can reliably define the position and shape of the auxiliary electrode pattern 3.
  • the first conductive pattern 61 can be electrically connected to the auxiliary electrode pattern 3 and the first power line 21, respectively, so as to realize the transmission of the power signal between the auxiliary electrode pattern 3 and the first power line 21.
  • the bottom of the groove 71 may include a second convex surface 713 protruding along the first direction (e.g., z direction).
  • the orthographic projection of the second convex surface 713 on the base substrate 1 at least partially overlaps with the orthographic projection of the first convex surface 31 on the base substrate 1.
  • the auxiliary electrode pattern 3 may be formed by covering the surface of the second convex surface 713 to form the first convex surface 31 on the auxiliary electrode pattern 3.
  • the auxiliary electrode pattern 3 may have a second concave surface 32 that is concave along the first direction on the surface that contacts the bottom of the groove 71.
  • the second concave surface 32 may be completely in contact with the second convex surface 713.
  • the second convex surface 713 may be conformal to the first convex surface 31, that is, the surface morphology of the second convex surface 713 may be substantially consistent with the surface morphology of the first convex surface 31, for example, both are truncated cone shaped convex surfaces, truncated cone shaped convex surfaces or spherical crown shaped convex surfaces.
  • the light-emitting substrate may include a pixel definition layer (Pixel Define Layer, PDL) 8 that defines a pixel area A1 and an auxiliary electrode area A2.
  • the pixel definition layer 8 is located on a side of the planar layer 7 away from the base substrate 1, and may include a plurality of second openings 82 corresponding to the light-emitting device LD and a first opening 81 corresponding to the auxiliary electrode pattern 3.
  • the first electrode layer 5 is disposed on a surface of the pixel definition layer 8 away from the base substrate 1 and at least covers the organic material layer 4 and the sidewalls of the first opening 81 .
  • the organic material layer 4 may include the same film structure as the light-emitting layer 93.
  • the organic material layer 4 includes an organic light-emitting layer, and may also include multiple other stacked auxiliary layers, such as a hole transport layer, an electron transport layer, a charge generation layer, etc.
  • the organic light-emitting layer may include multiple stacked layers, such as a first light-emitting layer and a second light-emitting layer.
  • the first light-emitting layer and the second light-emitting layer may emit light of the same color, such as both emitting blue light.
  • the first light-emitting layer and the second light-emitting layer may also emit light of different colors, such as the first light-emitting layer emitting blue light and the second light-emitting layer emitting green light.
  • the slope angle of the pixel definition layer 8 at the bottom edge of the first opening 81 is ⁇ .
  • the slope angle of a point on the curved surface refers to the angle between the tangent plane at the point on the curved surface and the plane parallel to the substrate 1.
  • the slope angle ⁇ can be made to satisfy: 20° ⁇ 30°, so as to reduce the step difference by setting the slope angle ⁇ in a suitable range to compensate for the possibility of particulate foreign matter aggregation and the adverse effect on packaging performance.
  • Part of the light-emitting layer 93 is located in the second opening 82, and the second electrode layer 94 is arranged on the surface of the pixel definition layer 8 away from the base substrate 1, and at least covers the sidewalls of the light-emitting layer 93 and the second opening 82.
  • the slope angle of the bottom edge of the second opening 82 is ⁇ .
  • the light-emitting layer 93 and the organic material layer 4 are formed by the same patterning process.
  • ⁇ and ⁇ can satisfy: ⁇ , thereby reducing the step difference by adopting a smaller slope angle ⁇ to compensate for the possible aggregation of particulate foreign matter on the packaging performance.
  • the first electrode 92 and the auxiliary electrode pattern 3 are located in the same layer and are made of the same material, which allows the first electrode 92 and the auxiliary electrode pattern 3 to be formed by the same patterning process, simplifying the processing steps.
  • the light-emitting layer 93 and the organic material layer 4 are located in the same layer and are made of the same material, which allows the light-emitting layer 93 and the organic material layer 4 to be formed by the same patterning process, simplifying the processing steps.
  • the second electrode layer 94 and the first electrode layer 5 are located in the same layer and are made of the same material, which allows the second electrode layer 94 and the first electrode layer 5 to be formed by the same patterning process, simplifying the processing steps.
  • FIG10 is a schematic diagram showing the dimensional relationship of the grooves of the flat layer of an embodiment of the light-emitting substrate of the present disclosure at a viewing angle perpendicular to the plane where the light-emitting substrate is located.
  • FIG11 is a schematic diagram showing the dimensional relationship of the grooves of the flat layer of another embodiment of the light-emitting substrate of the present disclosure at a viewing angle perpendicular to the plane where the light-emitting substrate is located.
  • the second direction may be defined as a direction (e.g., an x direction) parallel to the plane where the substrate 1 is located and pointing from the center of the second convex surface 713 to the center of the second via hole V2.
  • the groove 71 further includes a first portion 711 surrounding the second convex surface 713 and a second portion 712 connected to the first portion 711 and provided with the second via hole V2.
  • the plane where the lowest position of the groove bottom of the groove 71 is located is the first plane S1.
  • the notch plane of the groove 71 is the second plane S2.
  • the first plane S1 and the second plane S2 are both parallel to the plane where the substrate 1 is located.
  • the distance from the second convex surface 713 to the second plane S2 is H1
  • the height from the first plane S1 to the second plane S2 is H2
  • the thickness of the auxiliary electrode pattern 3 corresponding to the top of the second convex surface 713 is T, wherein the relationship among H1, H2 and T satisfies: H2 ⁇ H1+T ⁇ 2*H2.
  • the sum of H1 and T is the maximum distance between the auxiliary electrode pattern 3 and the first plane S1 along the first direction (for example, the z direction in FIG. 9 ). If the sum of H1 and T is too large, that is, the step difference between the highest point and the lowest point at the bottom of the groove 71 is too large, the slope angle of the first convex surface 31 will increase and/or the space occupied by the auxiliary electrode pattern 3 in the plane position will increase. In the subsequent process, the thickness of the first electrode layer 5 is relatively thin, and the step difference between the highest point and the lowest point at the bottom of the groove 71 is too large, which will cause the first electrode layer 5 to break, affecting the electrical connection performance here.
  • the increase in the space occupied by the auxiliary electrode pattern 3 on the plane will occupy the area of the pixel unit, which will have an adverse effect on the pixel arrangement density.
  • the first inorganic encapsulation layer in the thin film encapsulation layer will also be made on the first electrode layer 5. If the step difference here is too large, it may cause the first inorganic encapsulation layer to fail to climb or have thin film defects, affecting the encapsulation performance.
  • the highest point of the first convex surface 31 protrudes from the second plane S2, so that when the auxiliary electrode pattern 3 is formed, the auxiliary electrode pattern 3 forms the first convex surface 31, ensuring effective overlap between the auxiliary electrode pattern 3 and the first electrode layer 5.
  • the slope angle of the bottom edge of the second convex surface 713 is ⁇ , where the slope angle is the slope angle of a point on the curved surface, which refers to the angle between the tangent plane at the point on the curved surface and a plane parallel to the substrate 1.
  • the slope angle ⁇ can reflect the step difference formed by the second convex surface 713.
  • ⁇ can satisfy: 20° ⁇ 45°, so as to ensure the packaging performance of the area corresponding to the second convex surface while ensuring the effective overlap between the first electrode layer and the second electrode layer.
  • FIG10 shows the groove 71 of the flat layer 7 at a viewing angle perpendicular to the plane where the light-emitting substrate is located.
  • the circular area surrounded by the dotted line on the right corresponds to the second via hole V2
  • the larger dotted line box in the circular area surrounded by the two dotted lines on the right corresponds to the bottom edge of the second convex surface 713
  • the smaller dotted line box corresponds to the projection of the first via hole V1 on the auxiliary electrode pattern 3 on the flat layer 7.
  • the cross-sectional shapes of the first via hole V1, the second via hole V2, and the second convex surface 713 may all be circular.
  • the cross-sectional shape of the second convex surface 713 may also be other shapes, such as a polygon or ellipse as shown in FIG11.
  • the center of the first via hole V1 may coincide with the center of the second convex surface 713, or may not coincide.
  • the maximum length of the second convex surface 713 is L1
  • the minimum distance between the second convex surface 713 and the second via hole V2 is L2.
  • the maximum length L1 is the diameter of the maximum cross section of the second convex surface 713.
  • the orthographic projection of the groove 71 and the auxiliary electrode pattern 3 can basically overlap. Accordingly, the ratio of L2 to L1 can reflect the area size relationship of the orthographic projection of the second convex surface 713 corresponding to the first convex surface 31 on the base substrate 1 and the orthographic projection of the auxiliary electrode pattern 3 on the base substrate 1.
  • L1 and L2 can satisfy: 0.5*L1 ⁇ L2 ⁇ L1, so that the auxiliary electrode pattern occupies less space while reducing the difficulty of the processing technology.
  • the maximum length of the second convex surface 713 is L1
  • the maximum length of the first via hole V1 is L3.
  • the maximum length L1 is the diameter of the maximum cross section of the second convex surface 713.
  • the maximum length L3 is the diameter of the maximum cross section of the first via hole V1.
  • the maximum length L3 is the spot diameter of laser ablation.
  • the ratio of L3 to L1 can reflect the size of the projection of the first via hole V1 on the flat layer 7 on the second convex surface 713. If L3 exceeds L1, when the laser ablation process of the first via hole V1 is adopted, in addition to causing the process time to be too long, the film layers outside the auxiliary electrode area will also be ablated, causing damage to other film layers. If the ratio of L3 to L1 is too small, the portion of the auxiliary electrode pattern 71 exposed by the first via hole V1 will be too small, making the surface area for overlap too small, making it difficult to form an effective overlap. Therefore, in some embodiments, L1 and L3 can satisfy: 0.25*L1 ⁇ L3 ⁇ L1, so as to reduce the process time and avoid damage to other film layers while ensuring sufficient and effective overlap area between the auxiliary electrode pattern 71 and the first electrode layer 5.
  • the light-emitting substrates of the above-mentioned embodiments of the present disclosure can be applied to display panels. Therefore, the embodiments of the present disclosure also provide a display panel DP, comprising the light-emitting substrate LS of any of the above-mentioned embodiments.
  • the display panel DP may also include a driver IC and a power supply circuit, wherein the driver IC is used to drive the pixel unit of the light-emitting substrate LS, and the power supply circuit is used to supply power to the driver IC and the light-emitting substrate LS.
  • the display panel DP may also include a color conversion substrate CS located on the light-emitting side of the light-emitting substrate LS.
  • the display panels of the above-mentioned embodiments of the present disclosure can be applied to various display devices, and can also be applied to other fields, such as lighting devices. Therefore, the embodiments of the present disclosure also provide a display device, including the light-emitting substrate of any of the above-mentioned embodiments.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Fig. 12 is a schematic diagram of a manufacturing process of an embodiment of the light-emitting substrate of the present disclosure. Referring to the light-emitting substrate of the above embodiment of the present disclosure and Fig. 12, the manufacturing process of the light-emitting substrate includes: steps S1 to S7.
  • step S1 a base substrate 1 is provided, and a first power line 21, an insulating structure, a first conductive pattern 61 and a planar layer 7 are sequentially formed on the base substrate 1, wherein the first conductive pattern 61 is electrically connected to the first power line 21 through a via penetrating the insulating structure.
  • the insulating structure may include a first insulating layer 95 (e.g., a buffer layer), a second insulating layer 96 (e.g., a gate insulating layer), a third insulating layer 97 (e.g., an interlayer dielectric layer), and a fourth insulating layer 98 (e.g., a passivation layer) sequentially stacked on the base substrate 1.
  • a first insulating layer 95 e.g., a buffer layer
  • a second insulating layer 96 e.g., a gate insulating layer
  • a third insulating layer 97 e.g., an interlayer dielectric layer
  • a fourth insulating layer 98 e.g., a passivation layer
  • step S2 a groove 71 and a second via hole V2 are formed on the surface of the flat layer 7 away from the base substrate 1, wherein the second via hole V2 is opened on the bottom surface of the groove 71, penetrates the flat layer 7 and part of the insulating structure and exposes the first conductive pattern 61.
  • an auxiliary electrode pattern 3 is formed on the flat layer 7 in an area including at least the groove 71, so that the auxiliary electrode pattern 3 covers the bottom of the groove 71 and is electrically connected to the first conductive pattern 61 through the second via hole V2, wherein the auxiliary electrode pattern 3 includes a first convex surface 31 protruding along the light emitting direction of the light emitting substrate.
  • step S4 an organic material layer 4 is formed on the surface of the auxiliary electrode pattern 3 away from the base substrate 1 .
  • step S5 laser ablation is performed on the organic material layer 4 , so as to form a first via hole V1 penetrating through the organic material layer 4 and exposing the first convex surface 31 .
  • a first electrode layer 5 is formed on the surface of the organic material layer 4 away from the base substrate 1 , so that the first electrode layer 5 covers the organic material layer 4 and is electrically connected to the first convex surface 31 through the first via hole V1 .
  • the first convex surface 31 formed in step S3 increases the surface area of the auxiliary electrode pattern 3 exposed by the first via hole V1 obtained by laser ablation of the organic material layer 4, so that the overlapping area of the first electrode layer 5 is increased when overlapping with the auxiliary electrode pattern 3 through the first via hole V1, ensuring effective overlapping, thereby reducing the resistance from the first power line 21 to the first electrode layer 5, and further reducing the voltage drop of the power signal provided by the first power line 21.
  • the step of forming a groove 71 and a second via hole V2 on the surface of the flat layer 7 away from the base substrate 1 in step S2 may specifically include: etching the groove 71 on the surface of the flat layer 7 away from the base substrate 1 through a half-tone mask, wherein the bottom of the groove 71 includes a second convex surface 713 protruding along the first direction and the second via hole V2.
  • the half-tone mask is a semi-transparent mask with a small exposure amount. It can achieve residual etching (i.e., incomplete etching) of the film layer by reducing the amount of light entering during exposure, thereby forming a gentler slope angle on the substrate without completely etching the substrate.
  • the use of the half-tone mask can reduce the difficulty of forming the groove 71 with the second convex surface 713 on the surface of the flat layer 7.
  • the step of forming the groove 71 and the second via hole V2 on the surface of the flat layer 7 away from the base substrate 1 in step S2 may include: removing the material of the flat layer 7 of the same thickness at the position corresponding to the groove 71 on the surface of the flat layer 7 away from the base substrate 1, so that the bottom of the groove 71 includes a second convex surface 713 protruding along the first direction; etching the second via hole V2 at the bottom of the groove 71.
  • the step of forming the auxiliary electrode pattern 3 on the flat layer 7 in the region including at least the groove 71 in step S3 may include: evaporating the material of the auxiliary electrode pattern 3 on the region including at least the groove 71 on the flat layer 7, and forming the first convex surface 31 by covering the material of the auxiliary electrode pattern 3 on the second convex surface 713.
  • this embodiment can make the surface have a convex structure when forming the flat layer, and then etch away the flat layer material of the same thickness, so as to form a second convex structure in the groove. Then, a second via hole is etched so that the auxiliary electrode pattern is electrically connected to the first conductive pattern through the second via hole.
  • the manufacturing method may further include: forming a pixel definition layer 8 on the side of the flat layer 7 away from the base substrate 1 by mask photolithography, wherein the pixel definition layer 8 has a first opening 81 for setting the organic material layer 4 and a second opening 82 for setting the light-emitting layer 93 of the pixel unit 90, the slope angle of the pixel definition layer 8 at the bottom edge position of the first opening 81 is ⁇ , and the slope angle of the pixel definition layer 8 at the bottom edge position of the second opening 82 is ⁇ , and ⁇ and ⁇ satisfy: ⁇ .
  • the step difference is reduced by adopting a smaller slope angle ⁇ to compensate for the adverse effect of the possible aggregation of particulate foreign matter on the packaging performance.
  • partial processes of the manufacturing process example of the light-emitting substrate include:
  • a base substrate 1 is provided, and a first power line 21, an insulating structure, a first conductive pattern 61 and a planar layer 7 are sequentially formed on the base substrate 1, wherein the first conductive pattern 61 is electrically connected to the first power line 21 through a via penetrating the insulating structure, and the insulating structure may include a first insulating layer 95 (e.g., a buffer layer), a second insulating layer 96 (e.g., a gate insulating layer), a third insulating layer 97 (e.g., an interlayer dielectric layer) and a fourth insulating layer 98 (e.g., a passivation layer) sequentially stacked on the base substrate 1, i.e., the structure shown in FIG. 13A;
  • a first insulating layer 95 e.g., a buffer layer
  • a second insulating layer 96 e.g., a gate insulating layer
  • a third insulating layer 97 e.
  • the groove 71 and the second via hole V2 are etched on the surface of the flat layer 7 away from the base substrate 1 by using a half-tone mask, wherein the bottom of the groove 71 includes a second convex surface 713 protruding along the first direction, thereby forming the structure shown in FIG. 13B ;
  • the auxiliary electrode pattern 3 is evaporated on the flat layer 7 in a region including at least the groove 71, so that the auxiliary electrode pattern 3 covers the bottom of the groove 71 and is electrically connected to the first conductive pattern 61 through the second via hole V2, wherein the auxiliary electrode pattern 3 includes a first convex surface 31 protruding along the first direction, thereby forming a structure shown in FIG. 13C ;
  • a pixel definition layer 8 is formed on the side of the planar layer 7 away from the base substrate 1 through a half-tone mask, and the pixel definition layer 8 has a first opening for setting the organic material layer 4.
  • the pixel definition layer 8 covers a portion of the auxiliary electrode pattern and exposes at least a portion of the first convex surface 31, thereby forming a structure shown in FIG. 13D ;
  • An organic material layer 4 is evaporated on the surface of the auxiliary electrode pattern in the first opening, thereby forming a structure shown in FIG. 13E ;
  • the organic material layer 4 is laser ablated to form a first via hole V1 penetrating the organic material layer 4 and exposing the first convex surface 31 , thereby forming a structure shown in FIG. 13F ;
  • a first electrode layer 5 is evaporated on the surface of the organic material layer 4 away from the base substrate 1, so that the first electrode layer 5 covers the organic material layer 4, the surface of the pixel definition layer 8 and the side wall of the first opening, and the first via hole V1 is overlapped with the first convex surface 31 to achieve electrical connection, thereby forming the structure shown in FIG. 13G ;
  • a packaging layer may be formed on the basis of Figure 13G to realize the packaging of the light-emitting substrate.
  • a quantum dot layer or a color filter may also be provided in the first direction.
  • partial processes of the manufacturing process example of the light-emitting substrate include:
  • a base substrate 1 is provided, and a first power line 21, an insulating structure, a first conductive pattern 61 and a flat layer 7 are sequentially formed on the base substrate 1, wherein a surface of the flat layer 7 away from the base substrate 1 has a protruding structure 73, and the first conductive pattern 61 is electrically connected to the first power line 21 through a via penetrating the insulating structure, and the insulating structure may include a first insulating layer 95 (e.g., a buffer layer), a second insulating layer 96 (e.g., a gate insulating layer), a third insulating layer 97 (e.g., an interlayer dielectric layer) and a fourth insulating layer 98 (e.g., a passivation layer) sequentially stacked on the base substrate 1, i.e., the structure shown in FIG. 14A;
  • a first insulating layer 95 e.g., a buffer layer
  • a second insulating layer 96 e
  • the material of the flat layer 7 having the same thickness is removed from the position corresponding to the groove 71 on the surface of the flat layer 7 away from the base substrate 1, so that the bottom of the groove 71 includes a second convex surface 713 protruding along the first direction, thereby forming the structure shown in FIG. 14B ;
  • the second via hole V2 is etched at the bottom of the groove 71, thereby forming the structure shown in FIG. 14C;
  • the auxiliary electrode pattern 3 is evaporated on the flat layer 7 in a region including at least the groove 71, so that the auxiliary electrode pattern 3 covers the bottom of the groove 71 and is electrically connected to the first conductive pattern 61 through the second via hole V2, wherein the auxiliary electrode pattern 3 includes a first convex surface 31 protruding along the first direction, thereby forming a structure shown in FIG. 14D ;
  • a pixel definition layer 8 is formed on the side of the planar layer 7 away from the base substrate 1 through a half-tone mask, and the pixel definition layer 8 has a first opening for setting the organic material layer 4.
  • the pixel definition layer 8 covers a portion of the auxiliary electrode pattern and exposes at least a portion of the first convex surface 31, thereby forming a structure shown in FIG. 14E ;
  • An organic material layer 4 is evaporated on the surface of the auxiliary electrode pattern in the first opening, thereby forming a structure shown in FIG. 14F ;
  • Laser ablation is performed on the organic material layer 4 to form a first via hole V1 penetrating the organic material layer 4 and exposing the first convex surface 31 , thereby forming a structure shown in FIG. 14G ;
  • a first electrode layer 5 is evaporated on the surface of the organic material layer 4 away from the base substrate 1, so that the first electrode layer 5 covers the organic material layer 4, the surface of the pixel definition layer 8 and the side wall of the first opening, and the first via hole V1 is overlapped with the first convex surface 31 to achieve electrical connection, thereby forming the structure shown in Figure 14H.
  • a packaging layer may be formed on the basis of the structure shown in Fig. 14H to realize the packaging of the light-emitting substrate.
  • a quantum dot layer or a color filter may also be arranged in the light-emitting direction of the light-emitting substrate.

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Abstract

一种发光基板（LS）、显示面板（DP）和显示装置。发光基板（LS）包括：衬底基板（1）；第一电源线（21），设置在衬底基板（1）上；辅助电极图案（3），设置在第一电源线（21）远离衬底基板（1）的一侧，并与第一电源线（21）电连接；有机材料层（4），设置在辅助电极图案（3）远离衬底基板（1）的一侧的表面上，且具有贯穿有机材料层（4）的第一过孔（V1），第一过孔（V1）的底部露出辅助电极图案（3）的部分表面，其中，辅助电极图案（3）在第一过孔（V1）的底部露出的部分表面为非平面的表面；和第一电极层（5），设置在有机材料层（4）远离衬底基板（1）的一侧，并通过第一过孔（V1）与辅助电极图案（3）电连接。

Description

发光基板、显示面板和显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种发光基板、显示面板和显示装置。
背景技术
近来，发光二极管显示器已经被广泛地用作自发光显示装置。与液晶显示器不同，发光二极管显示装置具有自发射特性，因此可以不包括单独的光源，使得可以减小其厚度和重量。此外，发光二极管显示装置具有各种期望的特性，诸如低功耗、高亮度和快响应速度。通常，发光二极管显示装置通常包括多个晶体管和多个发光元件。在这种发光二极管显示装置中，晶体管被连接到信号线，并且可以将驱动电流传输到发光元件。晶体管可以包括包含沟道区和导电区的有源图案。
随着显示技术的发展，显示装置能够以诸如超高清(UHD)分辨率的高分辨率显示图像。在高分辨率显示装置的情况下，随着像素数量的增加，施加到像素的驱动电压可能不均匀，导致显示画面出现差异性，降低观看质量。
发明内容
在本公开的一个方面，提供一种发光基板，包括：
衬底基板；
第一电源线，设置在所述衬底基板上；
辅助电极图案，设置在所述第一电源线远离所述衬底基板的一侧，并与所述第一电源线电连接；
有机材料层，设置在所述辅助电极图案远离所述衬底基板的一侧的表面上，且具有贯穿所述有机材料层的第一过孔，所述第一过孔的底部露出所述辅助电极图案的部分表面，其中，所述辅助电极图案在所述第一过孔的底部露出的部分表面为非平面的表面；和
第一电极层，设置在所述有机材料层远离所述衬底基板的一侧，并通过所述第一过孔与所述辅助电极图案电连接。
在一些实施例中，所述辅助电极图案包括沿第一方向凸起的第一凸面，所述第一凸面的部分表面在所述第一过孔的底部露出，其中，所述第一方向为与所述衬底基板 所在平面垂直且朝向所述发光基板的出光侧的方向。
在一些实施例中，所述第一凸面具有球面被平面所截后剩下的曲面。
在一些实施例中，所述发光基板还包括：
第一导电图案，设置在所述辅助电极图案和所述第一电源线之间，并与所述第一电源线通过过孔电连接；和
平坦层，设置在所述第一导电图案和所述第一电极层之间，且在远离所述衬底基板的一侧的表面具有凹槽，
其中，所述辅助电极图案至少部分地设置在所述凹槽内，并通过贯穿所述平坦层的第二过孔与所述第一导电图案电连接。
在一些实施例中，所述凹槽的底部包括沿所述第一方向凸起的第二凸面，所述第二凸面在所述衬底基板上的正投影与所述第一凸面在所述衬底基板上的正投影至少部分重合。
在一些实施例中，所述第二凸面与所述第一凸面共形。
在一些实施例中，在所述第一方向上，所述第二凸面的顶部到所述凹槽的槽底最低位置所在平面的距离为H1，所述凹槽的槽口平面到所述凹槽的槽底最低位置所在平面的高度为H2，所述辅助电极图案对应于第二凸面的顶部的位置的厚度为T，H1、H2和T满足：H2<H1+T≤2*H2。
在一些实施例中，H1、H2和T满足：H2<H1+T≤1.5*H2。
在一些实施例中，在第二方向上，所述第二凸面的最大长度为L1，所述第二凸面与所述第二过孔的最小距离为L2，L1和L2满足：0.5*L1≤L2≤L1，其中，所述第二方向为与所述衬底基板所在平面平行且从所述第二凸面的中心指向所述第二过孔的中心的方向。
在一些实施例中，在第二方向上，所述第二凸面的最大长度为L1，所述第一过孔的最大长度为L3，L1和L3满足：0.25*L1≤L3≤L1，其中，所述第二方向为与所述衬底基板所在平面平行且从所述第二凸面的中心指向所述第二过孔的中心的方向。
在一些实施例中，所述第二凸面的底边位置的坡度角为θ，θ满足：20°≤θ≤45°。
在一些实施例中，所述发光基板还包括：
像素定义层，位于所述平坦层远离所述衬底基板的一侧，且具有第一开口；
其中，所述有机材料层的至少部分位于所述第一开口内，所述第一电极层设置在 所述像素定义层远离所述衬底基板一侧的表面，并至少覆盖所述有机材料层和所述第一开口的侧壁，所述像素定义层在所述第一开口的底边位置的坡度角为α，α满足：20°≤α≤30°。
在一些实施例中，所述发光基板还包括：
像素单元，包括薄膜晶体管和发光器件；；
其中，所述发光器件包括第一电极、发光层和第二电极层，所述薄膜晶体管位于所述衬底基板和所述平坦层之间，所述第一电极位于所述平坦层远离所述衬底基板的一侧，并通过贯穿所述平坦层的第三过孔与所述薄膜晶体管电连接，所述发光层的至少部分位于所述第一电极远离所述衬底基板一侧的表面上，所述第二电极层位于所述发光层远离所述衬底基板的一侧，所述像素定义层还具有第二开口，所述发光层的至少部分位于所述第二开口内，所述第二电极层设置在所述像素定义层远离所述衬底基板一侧的表面，并至少覆盖所述发光层和所述第二开口的侧壁。
在一些实施例中，所述像素定义层在所述第二开口的底边位置的坡度角为β，且α和β满足：α<β。
在一些实施例中，所述第一电极与所述辅助电极图案位于同层内且材料相同，所述发光层与所述有机材料层位于同层内且材料相同，所述第二电极层与所述第一电极层位于同层且材料相同。
在一些实施例中，所述发光基板还包括：
在所述衬底基板上依次层叠的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
第二电源线，设置在所述衬底基板上；和
第二导电图案，设置在所述第三绝缘层远离所述衬底基板的一侧，并通过贯穿所述第三绝缘层、所述第二绝缘层和部分所述第一绝缘层的过孔与所述第二电源线电连接；
其中，所述第一绝缘层覆盖所述第一电源线和所述第二电源线，所述第四绝缘层覆盖所述第一导电图案和所述第二导电图案，所述第二导电图案与所述薄膜晶体管电连接。
在一些实施例中，所述薄膜晶体管包括栅极、有源层、源极和漏极，所述有源层设置在所述第一绝缘层远离所述衬底基板一侧的表面上，所述源极和所述漏极设置在所述第三绝缘层远离所述衬底基板一侧的表面上，并分别通过贯穿所述第三绝缘层和 部分所述第二绝缘层的过孔与所述有源层电连接，所述栅极绝缘层覆盖所述有源层，所述栅极设置在所述第二绝缘层远离所述衬底基板一侧的表面上。
在本公开的一个方面，提供一种显示面板，包括：
前述的发光基板、驱动IC和供电电路。
在一些实施例中，所述显示面板还包括：
颜色转换基板，位于所述发光基板的出光侧。
在本公开的一个方面，提供一种显示装置，包括：前述的显示面板。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是本公开显示面板的一实施例的立体结构示意图；
图2是图1中AA截面的示意图；
图3是本公开显示面板的一实施例中显示区的截面示意图；
图4是本公开显示面板的另一实施例中显示区的截面示意图；
图5是本公开发光基板的一实施例在垂直于发光基板所在平面的视角下的分区示意图；
图6是相关技术中发光基板的辅助电极区域因激光烧蚀电致发光材料形成微粒异物的示意图；
图7是图3中BB截面的示意图；
图8是图3中BB截面的另一实例的示意图；
图9是本公开发光基板的一实施例的辅助电极区域的局部结构的爆炸示意图；
图10是本公开发光基板的一实施例的平坦层的凹槽在垂直于发光基板所在平面的的视角下的尺寸关系示意图；
图11是本公开发光基板的另一实施例的平坦层的凹槽在垂直于发光基板所在平面的的视角下的尺寸关系示意图；
图12是本公开发光基板的一实施例的制造流程的示意图；
图13A-图13G分别是本公开发光基板实施例的一种制造流程实例的部分工序示意图；
图14A-图14H分别是本公开发光基板实施例的一种制造流程实例的部分工序示意图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特定器件连接其它器件时，该特定器件可以与所述其它器件直接连接而不具有居间器件，也可以不与所述其它器件直接连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
图1是本公开显示面板的一实施例的立体结构示意图。图2是图1中AA截面的示意图。如图1和图2所示，显示面板DP包括发光基板LS和颜色转换基板CS。显示面板还可以包括驱动IC(集成电路，Integrated Circuit)和供电电路。显示面板 DP包括用于显示图像的显示区DA和不显示图像的非显示区NDA，非显示区NDA围绕在显示区DA的外侧。在一些实施例中，非显示区NDA可以封闭包围显示区DA，可以在至少一个方向上位于显示区DA的外侧。显示面板DP还可以包括填充在发光基板LS和颜色转换基板CS之间空间的填充层FL，以及用于密封发光基板LS和颜色转换基板CS之间空间的密封层SL。
在图1和图2中，第一方向可被定义为与发光基板的衬底基板所在平面垂直且朝向所述发光基板的出光侧的方向，例如图1和图2中的方向z。第二方向和第三方向(例如图1中的x方向和y方向)相互垂直，并均与发光基板的衬底基板所在平面垂直。沿第一方向z，颜色转换基板CS可以和发光基板LS相对设置。颜色转换基板CS可以包括用于转换入射光的颜色的颜色转换图案。颜色转换图案可以包括滤色器和波长转换图案中的至少一种。
密封层SL可以位于发光基板LS和颜色转换基板CS之间并且在非显示区NDA中。颜色转换基板CS可以在非显示区NDA中沿着发光基板LS和颜色转换基板CS的边缘设置，以在平面图中围绕显示区DA的外围或在显示区DA的外围周围。密封层SL可以由有机材料制成，例如由环氧基树脂制成，本公开不限于此。
填充层FL可以位于并填充发光基板LS和颜色转换基板CS之间、并且由密封层SL围绕的空间。填充物FL可以由能够透射光的材料制成。填充层FL可以由有机材料制成，例如，由硅基有机材料或环氧基有机材料等形成，但不限于此。在一些实施例中，填充层FL可以省略。
图3是本公开显示面板的一实施例中显示区的截面示意图。图4是本公开显示面板的另一实施例中显示区的截面示意图。参考图3，显示面板可采用对盒方式获得，即分别制作发光基板LS和颜色转换基板CS，然后通过填充层FL对发光基板LS和颜色转换基板CS进行粘合。
在图3中，发光基板LS可以为OLED背板。发光基板LS可包括第一衬底基板SUB1、绝缘结构INL、像素定义层PDL、薄膜封装结构TFE(例如层叠设置的封装层ENL1、ENL2、ENL3)、多个发光器件(例如LD1、LD2、LD3)及对应的晶体管(例如T1、T2、T3)。发光器件可包括多个发光二极管，例如蓝色发光二极管；或者双色发光二极管，例如具有蓝色和绿色发光层的发光二极管；或者白色发光二极管，例如具有多个不同颜色的发光层复合后发射白光的发光二极管。
发光器件LD1、LD2、LD3可对应于像素单元中的三个子像素，其中发光器件 LD1可包括阳极AE1、发光层OL和阴极CE，发光器件LD2可包括阳极AE2、发光层OL和阴极CE，发光器件LD3可包括阳极AE3、发光层OL和阴极CE。阳极AE1、AE2和AE3分别与晶体管T1、T2和T3电连接。
颜色转换基板CS设置在发光基板LS的出光侧。在图3中，颜色转换基板CS可以包括位于分隔壁PW限定的多个开口内的颜色转换层和透光图案TP。颜色转换层包括第一颜色转换图案CCP1和第二颜色转换图案CCP2。颜色转换基板CS可以包括遮光图案BM限定的多个开口内的滤色器CF1、CF2和CF3。颜色转换基板CS还包括第二衬底基板SUB2、第一盖板CAP1和第二盖板CAP2。分隔壁PW、颜色转换层和透光图案TP位于第一盖板CAP1和第二盖板CAP2之间，遮光图案BM、滤色器CF1、CF2和CF3位于第二衬底基板SUB2和第一盖板CAP1之间。
第一颜色转换图案CCP1可以通过将入射光的峰值波长转换或移动到另一特定峰值波长来发光。第一颜色转换图案CCP1可以将从第一发光器件LD1提供的发射光转换为具有在大约610nm至大约650nm的范围内的峰值波长的红光。第一颜色转换图案CCP1可以包括第一基础树脂和分散在第一基础树脂的第一颜色转换材料，并且可以包括分散在第一基础树脂中的第一散射粒子。第二颜色转换图案CCP2可以通过将入射光的峰值波长转换或移动到另一特定峰值波长来发光。第二波长转换图案CCP2可以将从第二发光元件LD2提供的发射光转换为具有在大约510nm至大约550nm的范围内的峰值波长的绿光。第二颜色转换图案CCP2可以包括第二基础树脂和分散在第二基础树脂中的第二颜色转换材料，并且可以包括分散在第二基础树脂中的第一散射粒子。
第一颜色转换材料和第二颜色转换材料可以包括半导体纳米晶体材料，可以在电子从导带跃迁到价带的情况下发射特定颜色的光。量子点可以具有任何形状，只要该形状在本领域中是通常使用的，并且具体地可以是球形、锥形、多臂或立方体的纳米颗粒，或者可以是纳米管、纳米线、纳米纤维或纳米颗粒等。
在另一些实施例中，发光基板还可以为包括三色子像素的白光OLED背板，并在其出光侧设置滤色层CF。
参考图4，显示面板可采用ON-EL方式形成，其中，发光基板LS与图3基本相同，在发光基板LS的薄膜封装结构TFE上制作分隔壁PW，然后在分隔壁PW限定的多个开口内打印颜色转换层和透光图案TP。颜色转换基板CS还包括遮光图案BM限定的多个开口内的滤色器CF1、CF2和CF3、第一盖板CAP1和第二盖板CAP2。 分隔壁PW、颜色转换层和透光图案TP位于第一盖板CAP1和第二盖板CAP2之间，遮光图案BM、滤色器CF1、CF2和CF3位于第一盖板CAP1远离发光基板LS的一侧。
图5是本公开发光基板的一实施例在垂直于发光基板所在平面的视角下的分区示意图。参考图5，在垂直于发光基板所在平面的视角(也就是发光基板LS的厚度方向的视角)下，发光基板LS可包括显示区A，以及环绕在在显示区A外侧的非显示区NA。对于包括发光基板LS的显示面板DP来说，发光基板LS的显示区A可对应于显示面板DP的显示区DA，发光基板LS的非显示区NA可对应于显示面板DP的非显示区NDA。在图5中，发光基板LS在显示区A中包括多个像素区域A1和多个辅助电极区域A2。多个像素区域A1和辅助电极区域A2可沿方向y交替地排布。
在一些实施方式中，发光基板在每个像素区域A1中可包括多个像素单元90。每个像素单元90可包括至少一个子像素，例如一种颜色、两种颜色或三种颜色的多个子像素。在一个像素区域A1中，多个像素单元90可沿方向x依次排布。
在一些实施方式中，每个像素单元90包括三种不同颜色的第一子像素901、第二子像素902和第三子像素903。例如，第一子像素901为蓝色子像素，第二子像素902为绿色子像素，第三子像素903为红色子像素。在另一些实施方式中，每个像素单元90还可以包括第四子像素，例如，第四子像素为白色子像素。
在一些实施方式中，发光基板在每个辅助电极区域A2内包括至少一个辅助电极图案3。每个像素单元90可对应一个辅助电极图案3，也可以对应多个辅助电极图案3，或者每个辅助电极图案3可对应多个像素单元90。在一些实施方式中，在多个辅助电极区域A2中，部分辅助电极区域A2内的至少部分辅助电极图案3经过激光烧蚀以与阴极电源线电连接。在一些实施方式中，在一个辅助电极区域内的多个辅助电极图案3中，多个辅助电极图案3可沿方向x间隔排布，其中至少部分辅助电极图案3经过激光烧蚀并和阴极电源线电连接。
图6是相关技术中发光基板的辅助电极区域因激光烧蚀电致发光材料形成微粒异物的示意图。参考图6，在一些相关技术的发光基板中，将阴极电源线1a设置在发光基板的显示区域，通过位于显示区域的电极图案1b(即辅助电极图案)实现阴极电源线1a和阴极材料层1d之间的电连接，以便将阴极信号(VSS)接入阴极材料层1d。为了使阴极材料层1d与阴极电源线实现电连接，相关技术在使电极图案1b与阴极电源线1a电连接后，在电极图案1b表面沉积有机电致发光(electroluminescent，简称 EL)材料1c，然后通过激光对EL材料1c进行烧蚀，以便露出电极图案1b，以便后续将阴极材料层1d部分沉积在露出的电极图案1b上，从而实现阴极信号直接通过面内搭接接入到阴极材料层1d。
经发明人研究发现，激光在对EL材料1c进行烧蚀时会产生微粒异物1e，这些微粒异物1e会沉积在像素定义层1f、EL材料和露出的电极图案1b的部分区域，影响封装的信赖性。同时，由于EL材料的烧蚀区域较为有限，也会因微粒异物沉积而导致阴极材料层1d与阳极材料层1b接触面积不足而无法与阳极材料层1b形成有效搭接，导致阴极信号较高的电压降，从而影响显示的均匀性。
由于激光烧蚀工艺不可避免地产生微粒异物，其分布范围难以控制，因此在其聚集的区域可能会导致封装性能被削弱。这使得辅助电极区的无机封装层由于无法包覆微粒异物所在的部位或包覆不牢靠，导致抗水氧入侵能力下降，导致封装信赖性下降。另外，辅助电极区的像素定义层的开口存在段差，加之微粒异物影响封装性能，从而使得段差位置的无机封装层较薄。
有鉴于此，本公开实施例提供一种发光基板，能够实现辅助电极区的有效搭接。
图7是图3中BB截面的示意图。图7包含了像素区域A1和辅助电极区域A2中的截面结构。参考图5和图7，5，本公开实施例提供的发光基板LS包括：衬底基板1、第一电源线21、辅助电极图案3、有机材料层4和第一电极层5。衬底基板1可以由透光材料(例如，无机玻璃、有机玻璃、塑料基板或其他有机材料基板)制成。衬底基板1可以具有刚性或具有柔性。衬底基板1上还可以包括缓冲层或绝缘层，以提供性能更好的基板表面。
发光基板LS除了包括第一电源线21，还可以包括位于衬底基板1上且与第一电源线21间隔排列的第二电源线22。第一电源线21和第二电源线22可为由单层或多层金属线堆叠形成的信号线，具有相同或不同的宽度。第一电源线21和第二电源线22的电位不同，例如由第一电源线21提供阴极信号VSS，第二电源线22提供阳极信号VDD。
发光基板LS还可以包括在衬底基板1上依次层叠的第一绝缘层95(例如缓冲层)、第二绝缘层96(例如栅极绝缘层)和第三绝缘层97(例如层间介质层)和第四绝缘层98(例如钝化层)。第一绝缘层95覆盖所述第一电源线21和所述第二电源线22。
发光基板LS还可以包括多个位于衬底基板1上的薄膜晶体管(Thin Film Transistor，TFT)91。薄膜晶体管91可以是包括多晶硅的薄膜晶体管或包括氧化物 半导体的薄膜晶体管，可以具有顶栅或底栅的结构。如图7所示，在一些实施例中，所述薄膜晶体管91包括栅极911、有源层912、源极913和漏极914。所述有源层912设置在所述第一绝缘层95远离所述衬底基板1一侧的表面上。所述源极913和所述漏极914设置在所述第三绝缘层97远离所述衬底基板1一侧的表面上，并分别通过贯穿所述第三绝缘层97和部分所述第二绝缘层96的过孔与所述有源层912电连接。所述第二绝缘层96设置在第一绝缘层95远离衬底基板1一侧的表面上，并覆盖所述有源层912。所述栅极911设置在所述第二绝缘层96远离衬底基板1一侧的表面上。
发光基板LS还可以包括位于第三绝缘层97远离衬底基板1的一侧的第一导电图案61和第二导电图案62。第一导电图案61位于辅助电极图案3和第一电源线21之间，并通过贯穿第三绝缘层97、第二绝缘层96和部分第一绝缘层95的过孔与所述第一电源线21电连接。第二导电图案62通过贯穿第三绝缘层97、第二绝缘层96和部分第一绝缘层95的过孔与所述第二电源线22电连接。所述第四绝缘层98覆盖所述第一导电图案61和所述第二导电图案62，所述第二导电图案62与所述薄膜晶体管91电连接。在一些实施方式中，第一导电图案61和第二导电图案62可以和薄膜晶体管91中的源极913和漏极914同层制作。
发光基板LS可以包括位于第四绝缘层98远离衬底基板1一侧的平坦层7。平坦层7可以在像素区域A1提供平坦的表面，并以由有机层形成。例如，平坦层7可以包括丙烯酸树脂、环氧树脂、酰亚胺树脂或酯树脂等。平坦层7和第四绝缘层98的部分可以具有贯穿的第三过孔V3，以便暴露薄膜晶体管91的漏极914，实现电连接。平坦层7和第四绝缘层98的部分设置有贯穿的第二过孔V2，以便暴露第一导电图案61，实现电连接。
发光基板LS可以包括多个发光器件LD。发光器件LD包括第一电极92、发光层93和第二电极层94。所述第一电极92位于所述平坦层7远离所述衬底基板1的一侧，并通过第三过孔V3与所述薄膜晶体管91的漏极914电连接。所述发光层93位于所述第一电极92远离所述衬底基板1一侧的表面上，所述第二电极层94位于所述发光层93远离所述衬底基板1的一侧。
参考图7，在一些实施例中，所述多个发光器件LD可以共用发光层93。发光层93还可以具有位于像素区域A1和辅助电极区域A2中连续膜层的形状。发光层93包括有机发光层，还可以包括堆叠的其他多个辅助层，例如，空穴传输层、电子传输层、电荷产生层等。有机发光层可以包括多个堆叠的层，例如第一发光层和第二发光层。 第一发光层和第二发光层可以发射相同颜色的光，例如均发射蓝光。第一发光层和第二发光层还可以发射不同颜色的光，例如，第一发光层发射蓝光，第二发光层发射绿光。
辅助电极图案3和第一电极92可以同层制作。辅助电极图案3通过第二过孔V2和第一导电图案61接触而实现电连接，从而通过第一导电图案61实现与第一电源线21之间的电连接。
图8是图3中BB截面的另一实例的示意图。参考图7和图8，在一些实施例中，有机材料层4设置在所述辅助电极图案3远离所述衬底基板1的一侧的表面上，且具有贯穿所述有机材料层4的第一过孔V1。所述第一过孔V1的底部露出所述辅助电极图案3的部分表面，其中，所述辅助电极图案3在所述第一过孔V1的底部露出的部分表面为非平面的表面，例如凹面、凸面或曲面。相比于平的表面，非平面的表面具有更大的表面积，可以增加第一电极层5与辅助电极图案3之间的搭接面积，从而有效降低第一电源线21提供的阴极信号的电压降。
参考图7，在一些实施例中，所述辅助电极图案3包括沿第一方向凸起的第一凸面31，第一凸面31的部分表面在所述第一过孔V1的底部露出，其中，所述第一方向为与所述衬底基板所在平面垂直且朝向所述发光基板的出光侧的方向，例如图7中的z方向。第一凸面31可有效地降低EL材料烧蚀后微粒在辅助电极图案3上的聚集，从而改善第一电极层5与辅助电极图案3之间的搭接质量。参考图8，在另一些实施例中，所述辅助电极图案3包括沿第一方向的相反方向凹入的第一凹面33。
在采用激光烧蚀有机材料层的方式形成第一过孔V1的加工工艺中，虽然烧蚀产生的微粒异物会沉积到第一凸面31的部分表面区域，但较大表面积的第一凸面31仍然可以实现第一电极层5与辅助电极图案3之间充足的搭接面积，以确保有效搭接，从而降低第一电源线21到第一电极层5的电阻，进而减少第一电源线21提供的电源信号的电压降。
在一些实施例中，第一电源线21提供的电源信号为阴极信号(VSS)。第一电极层5通过第一过孔V1的底部露出的第一凸面31搭接辅助电极图案3，可有效降低第一电源线21提供的阴极信号的电压降。在另一些实施例中，第一电源线21提供的电源信号为阳极信号(VDD)。第一电极层5通过第一过孔V1的底部露出的第一凸面31搭接辅助电极图案3，可有效减少第一电源线21提供的阳极信号的电压降。
在一些实施例中，所述第一凸面31可采用球面被平面所截后剩下的曲面，这种 表面比较平滑，不容易形成明显的段差，更易加工成形。第一凸面也可以采用也可以采用圆台形或锥台形的凸面等。在一些实施例中，辅助电极图案3以及有机材料层4可采用掩膜蒸镀形成，第一电极层5可以采用整面蒸镀形成，并在面内连续。
图9是本公开发光基板的一实施例的辅助电极区域的局部结构的爆炸示意图。参考图7和图9，在一些实施例中，平坦层7在远离所述衬底基板1的一侧表面具有凹槽71。所述辅助电极图案3至少部分地设置在所述凹槽71内，并通过贯穿所述平坦层7的第二过孔V2与所述第一导电图案61电连接。平坦层7的凹槽71能够可靠地限定辅助电极图案3的位置和形状。第一导电图案61能够分别与辅助电极图案3和第一电源线21电连接，从而实现辅助电极图案3和第一电源线21之间的电源信号的传输。
在图7和图9中，凹槽71的底部可包括沿所述第一方向(例如z方向)凸起的第二凸面713。所述第二凸面713在所述衬底基板1上的正投影与所述第一凸面31在所述衬底基板1上的正投影至少部分重合。辅助电极图案3可通过覆盖在第二凸面713的表面来形成辅助电极图案3上的第一凸面31。
在图9中，辅助电极图案3在与凹槽71的底部接触的表面可具有沿第一方向凹入的第二凹面32。第二凹面32可与第二凸面713完全贴合。对于具有厚度均匀的薄膜结构的辅助电极图案3来说，所述第二凸面713可以与与所述第一凸面31共形，即第二凸面713的表面形态可与第一凸面31的表面形态基本一致，例如均呈圆台形凸起表面、锥台形凸起表面或球冠形凸起表面。
发光基板可以包括限定像素区域A1和辅助电极区域A2的像素定义层(Pixel Define Layer，PDL)8。像素定义层8位于所述平坦层7远离所述衬底基板1的一侧，可以包括对应于发光器件LD的多个第二开口82和对应辅助电极图案3的第一开口81。
所述有机材料层4的至少部分位于所述第一开口81内，所述第一电极层5设置在所述像素定义层8远离所述衬底基板1一侧的表面，并至少覆盖所述有机材料层4和所述第一开口81的侧壁。
在一些实施例中，所述有机材料层4可以包括和发光层93相同的膜层结构。有机材料层4包括有机发光层，还可以包括堆叠的其他多个辅助层，例如，空穴传输层、电子传输层、电荷产生层等。有机发光层可以包括多个堆叠的层，例如第一发光层和第二发光层。第一发光层和第二发光层可以发射相同颜色的光，例如均发射蓝光。第 一发光层和第二发光层还可以发射不同颜色的光，例如，第一发光层发射蓝光，第二发光层发射绿光。
像素定义层8在所述第一开口81的底边位置的坡度角为α。曲面上某点的坡度角是指曲面上该点处的切平面与平行于衬底基板1的平面之间的夹角。第一开口81内的有机材料层4在采用激光烧蚀工艺时会产生微粒异物，这些微粒异物会附着在第一开口的侧壁、底边或顶边等处。这些位置属于封装薄弱区，而如果坡度角α过大，则会由于较大的段差和微粒异物的可能性聚集而造成封装层难以整面沉积，导致封装性能恶化。
如果坡度角α过小，则会使第一开口81的尺寸增大，且坡度角α过小可能会导致第一开口81的斜坡壁面不平整性增大，可能致使整面的发光基板上像素定义层上的各个开口的均一性变差。而且更小的坡度角要求更大的孔尺寸，从而占用更多空间而影响辅助电极区域的尺寸。因此，在一些实施例中，可使该坡度角α满足：20°≤α≤30°，从而通过将坡度角α设置在合适的范围来降低段差以弥补微粒异物的可能性聚集对封装性能的不利影响。
所述发光层93的部分位于所述第二开口82内，所述第二电极层94设置在所述像素定义层8远离所述衬底基板1一侧的表面，并至少覆盖所述发光层93和所述第二开口82的侧壁。所述第二开口82的底边位置的坡度角为β。在一些实施例中，发光层93和有机材料层4采用同一构图工艺形成，相比于发光层93，由于有机材料层4通过激光烧蚀出第一过孔V1，产生的微粒异物会导致第一开口81所在区域在同等封装条件下封装性能弱于第二开口82所在区域，因此可使α和β满足：α<β，从而通过采用较小的坡度角α来降低段差以弥补微粒异物的可能性聚集对封装性能的不利影响。
参考图7和图8，在一些实施例中，所述第一电极92与所述辅助电极图案3位于同层内且材料相同，这使得第一电极92与辅助电极图案3可通过同一构图工艺形成，简化加工工序。在一些实施例中，所述发光层93与所述有机材料层4位于同层内且材料相同，这使得发光层93与有机材料层4可通过同一构图工艺形成，简化加工工序。在一些实施例中，所述第二电极层94与所述第一电极层5位于同层且材料相同，这使得第二电极层94与所述第一电极层5可通过同一构图工艺形成，简化加工工序。
图10是本公开发光基板的一实施例的平坦层的凹槽在垂直于发光基板所在平面的的视角下的尺寸关系示意图。图11是本公开发光基板的另一实施例的平坦层的凹 槽在垂直于发光基板所在平面的的视角下的尺寸关系示意图
参考图7、图9-图11，可定义第二方向为与所述衬底基板1所在平面平行且从所述第二凸面713的中心指向所述第二过孔V2的中心的方向(例如x方向)。参考图9-图11，在一些实施例中，所述凹槽71还包括围绕第二凸面713的第一部分711和与第一部分711连接且设置第二过孔V2的第二部分712。
参考图9，在一些实施例中，所述凹槽71的槽底最低位置所在平面为第一平面S1。所述凹槽71的槽口平面为第二平面S2。第一平面S1和第二平面S2均与衬底基板1所在平面平行。
在所述第一方向上，所述第二凸面713到第二平面S2的距离为H1，所述第一平面S1到所述第二平面S2的高度为H2，所述辅助电极图案3对应于第二凸面713的顶部的位置的厚度为T，其中，H1、H2和T的关系满足：H2<H1+T≤2*H2。
H1和T之和是辅助电极图案3和所述第一平面S1之间沿着第一方向(例如图9中z方向)的最大距离，如H1与T之和过大，即凹槽71底部的最高处和最低处段差过大，会导致第一凸面31的坡度角增大和/或辅助电极图案3在平面位置上的占用空间增大。而在后续工艺中，第一电极层5的厚度较薄，凹槽71底部的最高处和最低处段差过大会导致第一电极层5的断裂，影响此处的电连接性能。而辅助电极图案3在平面上的占用空间增大，会挤占像素单元的面积，对于像素排布密度造成不利影响。同时，在后续工艺中，还会在第一电极层5上制作薄膜封装层中的第一无机封装层，如此处段差过大，那么可能会导致第一无机封装层的爬坡失败或存在薄膜缺陷，影响封装性能。
因此，当H1与T之和大于H2，第一凸面31的最高点(最远离衬底基板1的位置)突出于第二平面S2，从而便于在形成辅助电极图案3时，使辅助电极图案3形成第一凸面31，确保辅助电极图案3和第一电极层5之间的有效搭接。而通过使H1和T之和小于2倍的H2，可选地，小于1.5倍的H2，则可以提升辅助电极图案所在区域的封装性能，减少辅助电极图案3在发光基板的占用空间。
参考图9，在一些实施例中，所述第二凸面713的底边位置的坡度角为θ，其中，坡度角为曲面上某点的坡度角是指曲面上该点处的切平面与平行于衬底基板1的平面之间的夹角。坡度角θ可以体现第二凸面713所形成的段差。
如果θ过大，则会造成段差增大，而通常有机材料层的厚度较薄，过大的坡度角或较大的段差容易造给有机材料层的断裂，影响此处的封装性能。如果θ过小， 则在其上形成的辅助电极图案3的坡度较缓，在工艺波动的情况下叠加辅助电极图案3的厚度不均，则可能导致辅助电极图案3上难以形成实质上的第一凸面31，从而导致搭接面积不足，影响有效搭接。因此，在一些实施例中，可使θ满足：20°≤θ≤45°，从而在确保第二凸面对应区域的封装性能的同时，保证第一电极层和第二电极层之间的有效搭接。图10示出了平坦层7在垂直于发光基板所在平面的视角下的凹槽71。在图10中，右侧虚线围成的圆形区域对应为第二过孔V2，右侧两个虚线围成的圆形区域中较大的虚线框对应为第二凸面713的底边，较小的虚线框对应为辅助电极图案3上第一过孔V1在平坦层7上的投影。参考图10，在在垂直于发光基板所在平面的视角下，第一过孔V1、第二过孔V2和第二凸面713的横截面形状可以均为圆形。第二凸面713的横截面形状也可以为其他形状，例如图11所示的多边形或椭圆形。第一过孔V1的中心可以与第二凸面713的中心重合，也可以不重合。
参考图9和图10，在一些实施例中，在第二方向上，所述第二凸面713的最大长度为L1，所述第二凸面713与所述第二过孔V2的最小距离为L2。对于横截面为圆形的第二凸面713来说，最大长度L1为第二凸面713的最大面积横截面的直径。
在垂直于发光基板所在平面的视角下，凹槽71与辅助电极图案3的正投影可基本重合。相应地，L2与L1的比值可以体现出对应于第一凸面31的第二凸面713在衬底基板1上的正投影在辅助电极图案3在衬底基板1上的正投影的面积大小关系。如果L2与L1的比值过大，则在确保第二凸面713与有足够的表面积与辅助电极图案3进行搭接的基础上，导致辅助电极图案3的占用空间增大，挤占像素单元的空间，不利于增加发光基板的像素密度。如果L2与L1的比值过小，则使得第二凸面713距离第二过孔V2过近，增加加工工艺难度，导致良率下降。因此，在一些实施例中，可使得L1和L2满足：0.5*L1≤L2≤L1，从而在辅助电极图案占用较少空间的同时降低加工工艺难度。
参考图9和图10，在一些实施例中，在第二方向上，所述第二凸面713的最大长度为L1，所述第一过孔V1的最大长度为L3。对于横截面为圆形的第二凸面713来说，最大长度L1为第二凸面713的最大面积横截面的直径。对于横截面为圆形的第一过孔V1来说，最大长度L3为第一过孔V1的最大面积横截面的直径。对于采用激光烧蚀工艺形成第一过孔V1来说，最大长度L3为激光烧蚀的光斑直径。
L3与L1的比值可以体现出第一过孔V1在平坦层7上的投影在第二凸面713上占据的尺寸。如果L3超过L1，则当采用激光烧蚀第一过孔V1的工艺时，除了会导 致工艺时间过长，还会烧蚀辅助电极区域以外的膜层，造成其他膜层的损伤。如果L3与L1的比值过小，则导致第一过孔V1所露出辅助电极图案71的部分过小，使得用于搭接的表面积过小，从而难以形成有效搭接。因此，在一些实施例中，可使得L1和L3满足：0.25*L1≤L3≤L1，从而在确保辅助电极图案71和第一电极层5之间足够且有效的搭接面积的同时，降低工艺时间，避免对其他膜层的损伤。
上述本公开各实施例的发光基板可应用于显示面板。因此，本公开实施例还提供一种显示面板DP，包括前述任一实施例的发光基板LS。显示面板DP还可以包括驱动IC和供电电路，其中，驱动IC用于驱动发光基板LS的像素单元，供电电路用于给驱动IC和发光基板LS供电。在一些实施例中，显示面板DP还可包括位于所述发光基板LS的出光侧的颜色转换基板CS。
上述本公开各实施例的显示面板可应用于各类显示装置，也可应用其他领域，例如照明装置。因此，本公开实施例还提供了一种显示装置，包括前述任一实施例的发光基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图12是本公开发光基板的一实施例的制造流程的示意图。参考前述本公开实施例的发光基板和图12，发光基板的制造流程包括：步骤S1到步骤S7。
在步骤S1中，提供衬底基板1，并在所述衬底基板1上依次形成第一电源线21、绝缘结构、第一导电图案61和平坦层7，其中，所述第一导电图案61与所述第一电源线21通过贯穿所述绝缘结构的过孔电连接。参考图7，绝缘结构可以包括在衬底基板1上依次层叠的第一绝缘层95(例如缓冲层)、第二绝缘层96(例如栅极绝缘层)和第三绝缘层97(例如层间介质层)和第四绝缘层98(例如钝化层)。
在步骤S2中，在所述平坦层7远离所述衬底基板1一侧的表面形成凹槽71和第二过孔V2，其中所述第二过孔V2开设在凹槽71的槽底表面，并贯穿所述平坦层7和部分绝缘结构并露出所述第一导电图案61。
在步骤S3中，在所述平坦层7上至少包括所述凹槽71的区域形成辅助电极图案3，以使得所述辅助电极图案3覆盖所述凹槽71的底部，并通过所述第二过孔V2与所述第一导电图案61电连接，其中，所述辅助电极图案3包括沿所述发光基板的出光方向凸起的第一凸面31。
在步骤S4中，在所述辅助电极图案3远离所述衬底基板1一侧的表面形成有机材料层4。
在步骤S5中，对所述有机材料层4进行激光烧蚀，以便在所述有机材料层4形成贯穿所述有机材料层4并露出所述第一凸面31的第一过孔V1。
在步骤S6中，在所述有机材料层4远离所述衬底基板1一侧的表面形成第一电极层5，以使所述第一电极层5覆盖所述有机材料层4，并通过所述第一过孔V1与所述第一凸面31电连接。
在本实施例中，通过在步骤S3形成的第一凸面31增加了激光烧蚀有机材料层4所得到的第一过孔V1露出辅助电极图案3的表面积，使得第一电极层5在通过第一过孔V1与辅助电极图案3进行搭接时增加搭接面积，确保有效搭接，从而降低第一电源线21到第一电极层5的电阻，进而降低第一电源线21提供的电源信号的电压降。
在一些实施例中，步骤S2中在所述平坦层7远离所述衬底基板1一侧的表面形成凹槽71和第二过孔V2的步骤可具体包括：通过半色调掩膜(Half-Tone Mask)在所述平坦层7远离所述衬底基板1一侧的表面刻蚀出所述凹槽71，其中，所述凹槽71的底部包括沿第一方向凸起的第二凸面713和所述第二过孔V2。
半色调掩膜为半透视Mask，其曝光量较少，可以通过减少曝光时的进光量实现对膜层的带余量的刻蚀(即不完全刻蚀)，从而在基底上形成更缓的坡度角，且不会完成刻蚀基底。采用半色调掩膜可以降低在平坦层7的表面上形成具有第二凸面713的凹槽71的难度。
在另一些实施例中，在形成所述平坦层7时，使所述平坦层7远离所述衬底基板1一侧的表面具有凸起结构73。相应地，步骤S2中在所述平坦层7远离所述衬底基板1一侧的表面形成凹槽71和第二过孔V2的步骤可包括：在所述平坦层7远离所述衬底基板1一侧的表面对应于所述凹槽71的位置去除相同厚度的平坦层7的材料，以使所述凹槽71的底部包括沿第一方向凸起的第二凸面713；在所述凹槽71的底部刻蚀所述第二过孔V2。步骤S3中在所述平坦层7上至少包括所述凹槽71的区域形成辅助电极图案3的步骤可包括：在所述平坦层7上至少包括所述凹槽71的区域蒸镀辅助电极图案3的材料，通过覆盖所述第二凸面713的辅助电极图案3的材料形成所述第一凸面31。
相比于之前的制造方法实施例，本实施例可在形成平坦层时就使表面具有凸起结构，再刻蚀掉相同厚度的平坦层材料，这样就在凹槽内形成第二凸起结构。然后再刻蚀出第二过孔，以便辅助电极图案通过第二过孔与第一导电图案电连接。
在上述制造方法的各实施例中，在形成辅助电极图案3的步骤之后，所述制造方 法还可包括：在所述平坦层7远离所述衬底基板1的一侧通过掩膜光刻工艺形成像素定义层8，其中，所述像素定义层8具有用于设置所述有机材料层4的第一开口81和用于设置像素单元90的发光层93的第二开口82，像素定义层8在所述第一开口81的的底边位置的坡度角为α，像素定义层8在所述第二开口82的底边位置的坡度角为β，α和β满足：α<β。这样，通过采用较小的坡度角α来降低段差以弥补微粒异物的可能性聚集对封装性能的不利影响。
图13A-图13G分别是本公开发光基板实施例的一种制造流程实例的部分工序示意图。参考图13A-图13G，在一些实施例中，发光基板的制造流程实例的部分工序包括：
提供衬底基板1，并在所述衬底基板1上依次形成第一电源线21、绝缘结构、第一导电图案61和平坦层7，所述第一导电图案61与所述第一电源线21通过贯穿所述绝缘结构的过孔电连接，绝缘结构可包括在衬底基板1上依次层叠的第一绝缘层95(例如缓冲层)、第二绝缘层96(例如栅极绝缘层)和第三绝缘层97(例如层间介质层)和第四绝缘层98(例如钝化层)，即图13A所示结构；
通过半色调掩膜在所述平坦层7远离所述衬底基板1一侧的表面刻蚀出所述凹槽71和所述第二过孔V2，其中，所述凹槽71的底部包括沿所述第一方向凸起的第二凸面713，从而形成图13B所示结构；
在所述平坦层7上至少包括所述凹槽71的区域蒸镀辅助电极图案3，以使得所述辅助电极图案3覆盖所述凹槽71的底部，并通过所述第二过孔V2与所述第一导电图案61电连接，其中，所述辅助电极图案3包括沿所述第一方向凸起的第一凸面31，从而形成图13C所示结构；
在所述平坦层7远离所述衬底基板1的一侧通过半色调掩膜形成像素定义层8，并使所述像素定义层8具有用于设置所述有机材料层4的第一开口，像素定义层8覆盖部分辅助电极图案，并露出至少部分第一凸面31，从而形成图13D所示结构；
对第一开口内的所述辅助电极图案的表面蒸镀有机材料层4，从而形成图13E所示结构；
对所述有机材料层4进行激光烧蚀，以便在所述有机材料层4形成贯穿所述有机材料层4并露出所述第一凸面31的第一过孔V1，从而形成图13F所示结构；
在所述有机材料层4远离所述衬底基板1一侧的表面蒸镀第一电极层5，以使所述第一电极层5覆盖所述有机材料层4，以及像素定义层8表面和第一开口的侧壁等， 并通过所述第一过孔V1与所述第一凸面31进行搭接来实现电连接，从而形成图13G所示结构；
后续可在图13G的基础上形成封装层来实现发光基板的封装。在第一方向还可以设置量子点层或彩色滤光片。
图14A-图14H分别是本公开发光基板实施例的一种制造流程实例的部分工序示意图。参考图14A-图14H，在一些实施例中，发光基板的制造流程实例的部分工序包括：
提供衬底基板1，并在所述衬底基板1上依次形成第一电源线21、绝缘结构、第一导电图案61和平坦层7，平坦层7远离所述衬底基板1一侧的表面具有凸起结构73，所述第一导电图案61与所述第一电源线21通过贯穿所述绝缘结构的过孔电连接，绝缘结构可包括在衬底基板1上依次层叠的第一绝缘层95(例如缓冲层)、第二绝缘层96(例如栅极绝缘层)和第三绝缘层97(例如层间介质层)和第四绝缘层98(例如钝化层)，即图14A所示结构；
在所述平坦层7远离所述衬底基板1一侧的表面对应于所述凹槽71的位置去除相同厚度的平坦层7的材料，以使所述凹槽71的底部包括沿所述第一方向凸起的第二凸面713，从而形成图14B所示结构；
在所述凹槽71的底部刻蚀所述第二过孔V2，从而形成图14C所示结构；
在所述平坦层7上至少包括所述凹槽71的区域蒸镀辅助电极图案3，以使得所述辅助电极图案3覆盖所述凹槽71的底部，并通过所述第二过孔V2与所述第一导电图案61电连接，其中，所述辅助电极图案3包括沿所述第一方向凸起的第一凸面31，从而形成图14D所示结构；
在所述平坦层7远离所述衬底基板1的一侧通过半色调掩膜形成像素定义层8，并使所述像素定义层8具有用于设置所述有机材料层4的第一开口，像素定义层8覆盖部分辅助电极图案，并露出至少部分第一凸面31，从而形成图14E所示结构；
对第一开口内的所述辅助电极图案的表面蒸镀有机材料层4，从而形成图14F所示结构；
对所述有机材料层4进行激光烧蚀，以便在所述有机材料层4形成贯穿所述有机材料层4并露出所述第一凸面31的第一过孔V1，从而形成图14G所示结构；
在所述有机材料层4远离所述衬底基板1一侧的表面蒸镀第一电极层5，以使所述第一电极层5覆盖所述有机材料层4，以及像素定义层8表面和第一开口的侧壁等， 并通过所述第一过孔V1与所述第一凸面31进行搭接来实现电连接，从而形成图14H所示结构。
后续可在图14H所示结构的基础上形成封装层来实现发光基板的封装。在发光基板的出光方向还可以设置量子点层或彩色滤光片。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种发光基板，包括：
    衬底基板；
    第一电源线，设置在所述衬底基板上；
    辅助电极图案，设置在所述第一电源线远离所述衬底基板的一侧，并与所述第一电源线电连接；
    有机材料层，设置在所述辅助电极图案远离所述衬底基板的一侧的表面上，且具有贯穿所述有机材料层的第一过孔，所述第一过孔的底部露出所述辅助电极图案的部分表面，其中，所述辅助电极图案在所述第一过孔的底部露出的部分表面为非平面的表面；和
    第一电极层，设置在所述有机材料层远离所述衬底基板的一侧，并通过所述第一过孔与所述辅助电极图案电连接。
  2. 根据权利要求1所述的发光基板，其中，所述辅助电极图案包括沿第一方向凸起的第一凸面，所述第一凸面的部分表面在所述第一过孔的底部露出，其中，所述第一方向为与所述衬底基板所在平面垂直且朝向所述发光基板的出光侧的方向。
  3. 根据权利要求2所述的发光基板，其中，所述第一凸面具有球面被平面所截后剩下的曲面。
  4. 根据权利要求2或3所述的发光基板，还包括：
    第一导电图案，设置在所述辅助电极图案和所述第一电源线之间，并与所述第一电源线通过过孔电连接；和
    平坦层，设置在所述第一导电图案和所述第一电极层之间，且在远离所述衬底基板的一侧的表面具有凹槽，
    其中，所述辅助电极图案至少部分地设置在所述凹槽内，并通过贯穿所述平坦层的第二过孔与所述第一导电图案电连接。
  5. 根据权利要求4所述的发光基板，其中，所述凹槽的底部包括沿所述第一方向凸起的第二凸面，所述第二凸面在所述衬底基板上的正投影与所述第一凸面在所述衬底基板上的正投影至少部分重合。
  6. 根据权利要求5所述的发光基板，其中，所述第二凸面与所述第一凸面共形。
  7. 根据权利要求5或6所述的发光基板，其中，在所述第一方向上，所述第二 凸面的顶部到所述凹槽的槽底最低位置所在平面的距离为H1，所述凹槽的槽口平面到所述凹槽的槽底最低位置所在平面的高度为H2，所述辅助电极图案对应于第二凸面的顶部的位置的厚度为T，H1、H2和T满足：H2<H1+T≤2*H2。
  8. 根据权利要求7所述的发光基板，其中，H1、H2和T满足：H2<H1+T≤1.5*H2。
  9. 根据权利要求5～8任一所述的发光基板，其中，在第二方向上，所述第二凸面的最大长度为L1，所述第二凸面与所述第二过孔的最小距离为L2，L1和L2满足：0.5*L1≤L2≤L1，其中，所述第二方向为与所述衬底基板所在平面平行且从所述第二凸面的中心指向所述第二过孔的中心的方向。
  10. 根据权利要求5～8任一所述的发光基板，其中，在第二方向上，所述第二凸面的最大长度为L1，所述第一过孔的最大长度为L3，L1和L3满足：0.25*L1≤L3≤L1，其中，所述第二方向为与所述衬底基板所在平面平行且从所述第二凸面的中心指向所述第二过孔的中心的方向。
  11. 根据权利要求5～10任一所述的发光基板，其中，所述第二凸面的底边位置的坡度角为θ，θ满足：20°≤θ≤45°。
  12. 根据权利要求4～11任一所述的发光基板，还包括：
    像素定义层，位于所述平坦层远离所述衬底基板的一侧，且具有第一开口；
    其中，所述有机材料层的至少部分位于所述第一开口内，所述第一电极层设置在所述像素定义层远离所述衬底基板一侧的表面，并至少覆盖所述有机材料层和所述第一开口的侧壁，所述像素定义层在所述第一开口的底边位置的坡度角为α，α满足：20°≤α≤30°。
  13. 根据权利要求12所述的发光基板，还包括：
    像素单元，包括薄膜晶体管和发光器件；；
    其中，所述发光器件包括第一电极、发光层和第二电极层，所述薄膜晶体管位于所述衬底基板和所述平坦层之间，所述第一电极位于所述平坦层远离所述衬底基板的一侧，并通过贯穿所述平坦层的第三过孔与所述薄膜晶体管电连接，所述发光层的至少部分位于所述第一电极远离所述衬底基板一侧的表面上，所述第二电极层位于所述发光层远离所述衬底基板的一侧，所述像素定义层还具有第二开口，所述发光层的至少部分位于所述第二开口内，所述第二电极层设置在所述像素定义层远离所述衬底基板一侧的表面，并至少覆盖所述发光层和所述第二开口的侧壁。
  14. 根据权利要求13所述的发光基板，其中，所述像素定义层在所述第二开口 的底边位置的坡度角为β，且α和β满足：α<β。
  15. 根据权利要求13或14所述的发光基板，其中，所述第一电极与所述辅助电极图案位于同层内且材料相同，所述发光层与所述有机材料层位于同层内且材料相同，所述第二电极层与所述电极层位于同层且材料相同。
  16. 根据权利要求13～15任一所述的发光基板，还包括：
    在所述衬底基板上依次层叠的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
    第二电源线，设置在所述衬底基板上；和
    第二导电图案，设置在所述第三绝缘层远离所述衬底基板的一侧，并通过贯穿所述第三绝缘层、所述第二绝缘层和部分所述第一绝缘层的过孔与所述第二电源线电连接；
    其中，所述第一绝缘层覆盖所述第一电源线和所述第二电源线，所述第四绝缘层覆盖所述第一导电图案和所述第二导电图案，所述第二导电图案与所述薄膜晶体管电连接。
  17. 根据权利要求16所述的发光基板，其中，所述薄膜晶体管包括栅极、有源层、源极和漏极，所述有源层设置在所述第一绝缘层远离所述衬底基板一侧的表面上，所述源极和所述漏极设置在所述第三绝缘层远离所述衬底基板一侧的表面上，并分别通过贯穿所述第三绝缘层和部分所述第二绝缘层的过孔与所述有源层电连接，所述栅极绝缘层覆盖所述有源层，所述栅极设置在所述第二绝缘层远离所述衬底基板一侧的表面上。
  18. 一种显示面板，包括：
    权利要求1～17任一所述的发光基板、驱动IC和供电电路。
  19. 根据权利要求18所述的显示面板，还包括：
    颜色转换基板，位于所述发光基板的出光侧。
  20. 一种显示装置，包括：
    权利要求18或19所述的显示面板。
PCT/CN2022/135777 2022-12-01 2022-12-01 发光基板、显示面板和显示装置 Ceased WO2024113296A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140080231A (ko) * 2012-12-20 2014-06-30 엘지디스플레이 주식회사 플렉서블 유기발광 표시장치 및 이의 제조방법
KR20170080756A (ko) * 2015-12-30 2017-07-11 엘지디스플레이 주식회사 보조전극 구조 및 이를 갖는 유기전계발광 표시 장치
CN108172597A (zh) * 2016-12-07 2018-06-15 三星显示有限公司 有机发光二极管显示器及其制造方法
CN110085648A (zh) * 2019-05-17 2019-08-02 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
CN113241367A (zh) * 2021-07-09 2021-08-10 北京京东方技术开发有限公司 显示基板及其制备方法
CN115241399A (zh) * 2022-07-29 2022-10-25 京东方科技集团股份有限公司 一种电致发光二极管显示基板、显示面板和制作方法
CN115280537A (zh) * 2021-02-26 2022-11-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4216008B2 (ja) * 2002-06-27 2009-01-28 株式会社半導体エネルギー研究所 発光装置およびその作製方法、ならびに前記発光装置を有するビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ、カーナビゲーション、パーソナルコンピュータ、ｄｖｄプレーヤー、電子遊技機器、または携帯情報端末
KR101084193B1 (ko) 2010-02-16 2011-11-17 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 그 제조방법
JP2015050051A (ja) 2013-09-02 2015-03-16 大日本印刷株式会社 トップエミッション型有機エレクトロルミネッセンス表示装置
KR102112844B1 (ko) * 2013-10-15 2020-05-19 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조방법
US10032844B2 (en) 2014-12-29 2018-07-24 Lg Display Co., Ltd. Organic light emitting display device and method of manufacturing the same
KR102390441B1 (ko) * 2015-10-15 2022-04-26 삼성디스플레이 주식회사 유기발광 표시장치
KR102397686B1 (ko) 2015-10-30 2022-05-12 엘지디스플레이 주식회사 유기 발광 표시 장치
KR102370355B1 (ko) 2017-03-09 2022-03-07 삼성디스플레이 주식회사 유기발광 표시장치
CN107068727A (zh) 2017-05-05 2017-08-18 京东方科技集团股份有限公司 显示基板和显示装置
KR102461391B1 (ko) 2017-10-16 2022-10-31 엘지디스플레이 주식회사 대면적 유기발광 다이오드 표시장치
CN109136834B (zh) 2018-09-07 2021-03-05 京东方科技集团股份有限公司 一种掩膜版、oled显示基板及其制备方法
CN112952023B (zh) 2021-02-20 2022-11-04 合肥鑫晟光电科技有限公司 显示基板及其制备方法、显示装置
CN216054713U (zh) 2021-09-17 2022-03-15 昆山国显光电有限公司 显示面板和显示装置
CN114050174B (zh) 2021-10-26 2023-05-05 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法、电子设备

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140080231A (ko) * 2012-12-20 2014-06-30 엘지디스플레이 주식회사 플렉서블 유기발광 표시장치 및 이의 제조방법
KR20170080756A (ko) * 2015-12-30 2017-07-11 엘지디스플레이 주식회사 보조전극 구조 및 이를 갖는 유기전계발광 표시 장치
CN108172597A (zh) * 2016-12-07 2018-06-15 三星显示有限公司 有机发光二极管显示器及其制造方法
CN110085648A (zh) * 2019-05-17 2019-08-02 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
CN115280537A (zh) * 2021-02-26 2022-11-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113241367A (zh) * 2021-07-09 2021-08-10 北京京东方技术开发有限公司 显示基板及其制备方法
CN115241399A (zh) * 2022-07-29 2022-10-25 京东方科技集团股份有限公司 一种电致发光二极管显示基板、显示面板和制作方法

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