WO2024113147A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2024113147A1
WO2024113147A1 PCT/CN2022/134938 CN2022134938W WO2024113147A1 WO 2024113147 A1 WO2024113147 A1 WO 2024113147A1 CN 2022134938 W CN2022134938 W CN 2022134938W WO 2024113147 A1 WO2024113147 A1 WO 2024113147A1
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WO
WIPO (PCT)
Prior art keywords
common electrode
base substrate
array substrate
strip
electrode bus
Prior art date
Application number
PCT/CN2022/134938
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English (en)
French (fr)
Inventor
王婷婷
王旭
王祺
闫岩
马禹
尹晓峰
麻志强
龚涛
任浩岩
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/134938 priority Critical patent/WO2024113147A1/zh
Priority to US18/547,390 priority patent/US20240210766A1/en
Publication of WO2024113147A1 publication Critical patent/WO2024113147A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a display device.
  • the array substrate needs to be placed on the light-emitting side of the display panel, and the counter substrate needs to be placed on the light-incoming side of the display panel.
  • the non-display area of the array substrate a large piece of metal needs to be placed, which will reflect ambient light and cause a bright metal edge, affecting the display effect.
  • an array substrate comprising: a substrate substrate, the substrate substrate comprising a first surface and a second surface arranged oppositely, the substrate substrate comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a first peripheral area and a second peripheral area, the first peripheral area surrounding the display area, and the second peripheral area surrounding the first peripheral area; a plurality of pixel units, the plurality of pixel units are located on the second surface of the substrate substrate, the orthographic projections of the plurality of pixel units on the substrate substrate are located in the display area, and are distributed in an array, at least a portion of the pixel units comprising a common electrode; a light shielding layer, the light shielding layer is located on the first surface of the substrate substrate, the orthographic projection of the light shielding layer on the substrate substrate is located in the peripheral area, and at least a portion of the orthographic projection of the light shielding layer on the substrate substrate is located in the second peripheral area; and a first common electrode bus, the
  • the first common electrode bus includes a first portion located in the first peripheral area and a second portion located in the second peripheral area, the second portion includes a bulk metal portion; and the first portion includes a strip metal portion.
  • a first portion of the first common electrode bus located in the first peripheral area includes a plurality of strip-shaped metal portions and at least one strip-shaped slit, and the plurality of strip-shaped metal portions and the at least one strip-shaped slit are alternately arranged along an edge of the base substrate in a direction pointing toward the display area.
  • the strip-shaped slit includes a first width along a first direction
  • the strip-shaped metal part includes a second width along the first direction
  • the first direction is substantially perpendicular to an extension direction of the strip-shaped slit or the strip-shaped metal part; and a value of the first width divided by the sum of the first width and the second width is greater than 0.5.
  • an orthographic projection of the first common electrode bus close to a boundary of the display area on the base substrate is located at a junction of the first peripheral area and the second peripheral area.
  • an orthographic projection of the first common electrode bus line on the base substrate close to a boundary of the display area is located within an orthographic projection of the light shielding layer on the base substrate.
  • the base substrate includes a first side, a second side, a third side and a fourth side, the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other;
  • the array substrate also includes a data signal line and a scan signal line arranged on the second surface of the base substrate, the scan signal line extends from the first side toward the second side, and the data signal line extends from the third side toward the fourth side; at least two columns of virtual pixel units are arranged in a first peripheral area of at least one of the first side and the second side.
  • the base substrate includes a first side, a second side, a third side and a fourth side, the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other;
  • the array substrate also includes a data signal line and a scan signal line arranged on the second surface of the base substrate, the scan signal line extends from the first side toward the second side, and the data signal line extends from the third side toward the fourth side; in a first peripheral area of at least one of the first side and the second side, at least one column of virtual pixel units is arranged between the first part and the display area.
  • At least one row of dummy pixel units is disposed in a first peripheral region of at least one of the third side and the fourth side.
  • the array substrate also includes a second common electrode bus, which is located on the second surface of the base substrate, and the orthographic projection of the second common electrode bus on the base substrate is located within the first peripheral area and the second peripheral area, and the second common electrode bus is electrically connected to the first common electrode bus.
  • the array substrate includes a first metal conductive layer and a first transparent conductive layer disposed on the second surface of the base substrate, the first common electrode bus is located in the first metal conductive layer, and the second common electrode bus is located in the first transparent conductive layer.
  • the first portion of the first common electrode bus located in the first peripheral area includes a plurality of first strip-shaped metal portions and a plurality of second strip-shaped metal portions, the plurality of first strip-shaped metal portions extending along a second direction, the plurality of second strip-shaped metal portions extending along a third direction, and the second direction intersects the third direction.
  • the first direction and the third direction intersect.
  • the first portion of the first common electrode bus located in the first peripheral area includes a plurality of first strip-shaped metal portions and a plurality of second strip-shaped metal portions, the plurality of first strip-shaped metal portions extending along a second direction, the plurality of second strip-shaped metal portions extending along a third direction, and the second direction intersects the third direction.
  • the second common electrode bus includes at least one second opening, the at least one second opening is located in the first peripheral area, and the orthographic projection of at least one intersection between the plurality of first strip-shaped metal portions and the plurality of second strip-shaped metal portions on the base substrate at least partially overlaps with the orthographic projection of the at least one second opening on the base substrate.
  • the base substrate includes a first side, a second side, a third side and a fourth side, the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other;
  • the array substrate also includes a data signal line and a scan signal line arranged on the second surface of the base substrate, the scan signal line extends from the first side toward the second side, and the data signal line extends from the third side toward the fourth side; in a first peripheral area of at least one of the first side and the second side, at least one column of virtual pixel units is arranged between the first part and the display area.
  • the array substrate also includes a second common electrode bus, which is located on the second surface of the base substrate, and the orthographic projection of the second common electrode bus on the base substrate is located within the first peripheral area and the second peripheral area, and the second common electrode bus is electrically connected to the first common electrode bus.
  • the first portion of the first common electrode bus located in the first peripheral area includes a plurality of first strip-shaped metal portions and a plurality of second strip-shaped metal portions, the plurality of first strip-shaped metal portions extending along a second direction, the plurality of second strip-shaped metal portions extending along a third direction, and the second direction intersects the third direction.
  • the second common electrode bus includes at least one second opening, the at least one second opening is located in the first peripheral area, and the orthographic projection of at least one intersection between the plurality of first strip-shaped metal portions and the plurality of second strip-shaped metal portions on the base substrate at least partially overlaps with the orthographic projection of the at least one second opening on the base substrate.
  • the portion of the scan signal line located in the peripheral area includes a first scan signal sub-portion and a second scan signal sub-portion, the first scan signal sub-portion extends along a first direction, the second scan signal sub-portion extends along a second direction, and the first direction and the second direction intersect; and the extension direction of the second scan signal sub-portion and the data signal line are basically parallel.
  • an orthographic projection of the first scan signal sub-portion on the substrate substrate at least partially overlaps with an orthographic projection of the at least one second opening on the substrate substrate; and/or an orthographic projection of at least one intersection between the first strip metal portion, the second strip metal portion and the first scan signal sub-portion on the substrate substrate at least partially overlaps with an orthographic projection of the at least one second opening on the substrate substrate.
  • the second portion includes at least one first opening, and an orthographic projection of the at least one first opening on the substrate at least partially overlaps with an orthographic projection of the first scan signal sub-portion on the substrate.
  • a ratio of a length of the at least one strip-shaped slit in its extending direction to a width of the strip-shaped slit in a direction perpendicular to its extending direction is greater than 10.
  • the array substrate also includes data signal lines and scan signal lines arranged on the second surface of the base substrate, and the array substrate also includes: a second metal conductive layer arranged on the base substrate; and a second transparent conductive layer arranged on the base substrate; the data signal line is located in the first metal conductive layer, and the scan signal line is located in the second metal conductive layer; and at least a portion of the pixel units also include a pixel electrode, the pixel electrode is located in the first transparent conductive layer, and the common electrode is located in the second transparent conductive layer.
  • a display device comprising: an array substrate as described above; an opposing substrate arranged opposite to the array substrate; and a liquid crystal layer located between the array substrate and the opposing substrate, wherein the light emitting surface of the display device is the first surface of the base substrate in the array substrate.
  • FIG. 1 is a schematic structural diagram of a display panel according to some exemplary embodiments of the present disclosure.
  • FIGS. 2A and 2B are schematic structural diagrams of array substrates according to some exemplary embodiments of the present disclosure, which schematically illustrate electrode arrangements of pixel units.
  • FIG. 3A is a schematic plan view of an array substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 3B is a partial enlarged view of portion I in FIG. 3A .
  • FIG. 4 is a schematic plan view of an array substrate according to some exemplary embodiments of the present disclosure, which schematically shows the arrangement of pixel units.
  • FIG. 5 is a schematic plan view of an array substrate according to some exemplary embodiments of the present disclosure, which schematically shows a more detailed arrangement of pixel units.
  • FIG. 6 is a partial enlarged view of a portion II of an array substrate in FIG. 3A according to some exemplary embodiments of the present disclosure.
  • FIG. 7 is a partial enlarged view of a portion III of FIG. 3A of an array substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 8 is a partial enlarged view of a portion IV of an array substrate in FIG. 6 according to some exemplary embodiments of the present disclosure.
  • FIG. 9 is a partial enlarged view of a portion V of an array substrate in FIG. 7 according to some exemplary embodiments of the present disclosure.
  • FIG. 10A is a schematic plan view of a portion of FIG. 9 in a metal conductive layer.
  • FIG. 10B is a schematic plan view of the portion in FIG. 9 in two metal conductive layers.
  • FIG. 10C is a plan view schematically showing the portion of FIG. 9 in two metal conductive layers and one transparent conductive layer.
  • FIG. 10D is a plan view schematically showing a portion of FIG. 9 in two metal conductive layers and two transparent conductive layers.
  • FIG. 11 is a partial enlarged view of a portion IV of an array substrate in FIG. 7 according to some other exemplary embodiments of the present disclosure.
  • FIG. 12 is a schematic cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure, taken along line AA′ in FIG. 3B .
  • FIG. 13 is a partial enlarged view of a portion IV of an array substrate in FIG. 7 according to some other exemplary embodiments of the present disclosure.
  • FIG. 14 is a partial enlarged view of a portion II of an array substrate in FIG. 3A according to some exemplary embodiments of the present disclosure, which schematically shows a more detailed arrangement.
  • FIG. 15 is a schematic plan view of an array substrate according to some exemplary embodiments of the present disclosure, which schematically illustrates a pixel unit and a dummy pixel unit.
  • first the terms “first”, “second”, etc. may be used herein to describe various parts, components, elements, regions, layers and/or parts, these parts, components, elements, regions, layers and/or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and/or part from another.
  • first part, first member, first element, first region, first layer and/or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and/or second part without departing from the teachings of the present disclosure.
  • the expressions “same layer”, “same layer arrangement” or similar expressions refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process.
  • a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.
  • the expression “electrically connected” may mean that two parts or elements are directly electrically connected, for example, part or element A is in direct contact with part or element B, and electrical signals can be transmitted between the two parts; it may also mean that two parts or elements are electrically connected through a conductive medium such as a conductive wire, for example, part or element A is electrically connected to part or element B through a conductive wire to transmit electrical signals between the two parts or elements; it may also mean that two parts or elements are electrically connected through at least one electronic component, for example, part or element A is electrically connected to part or element B through at least one thin film transistor to transmit electrical signals between the two parts or elements.
  • FIG1 is a schematic diagram of the structure of a display panel according to some exemplary embodiments of the present disclosure.
  • the display panel may be a liquid crystal display panel.
  • the liquid crystal display panel may use In-cell technology to achieve the integration of display and touch.
  • FIC abbreviation of Full In Cell
  • FIC technology a single-layer touch wiring design is adopted, and multi-point touch is realized by using the principle of self-capacitance.
  • FIC technology adopts the "time-sharing scanning" method, dividing the unit time into two parts, one for touch scanning and the other for display scanning, without interfering with each other.
  • the display panel may include an array substrate 1 , an opposing substrate 7 , and a liquid crystal layer 9 located between the array substrate 1 and the opposing substrate 7 .
  • the opposing substrate 7 and the array substrate 1 are disposed opposite to each other.
  • the counter substrate 7 is located at the light-emitting side of the display panel.
  • a transparent conductive layer eg, an ITO layer
  • ITO layer is usually coated on the back of the counter substrate 7 .
  • the opposing substrate 7 is located at the light-emitting side of the display panel, when a finger touches the display panel, the transparent conductive layer for preventing static electricity will affect the touch effect.
  • the array substrate 1 is located at the light emitting side of the display panel, and the counter substrate 7 is located at the light incident side of the display panel.
  • the display panel further includes a backlight module 8, and the counter substrate 7 is closer to the backlight module 8 than the array substrate 1.
  • Borderless display products are increasingly and beautiful in appearance, especially 4-sided borderless display products, which make people feel high-end and are deeply loved by customers.
  • 4-sided borderless display products include a display area and a peripheral area (i.e., a non-display area) surrounding the display area.
  • Large pieces of metal such as fan-out lines, gate drive circuits, and common electrode buses are provided in the peripheral area. These large pieces of metal will reflect ambient light and cause bright metal edges, affecting the display effect.
  • By coating the peripheral area with ink large pieces of metal can be avoided from reflecting light.
  • the coated ink usually has a ⁇ 0.15mm offset.
  • the ink design center value needs to be 0.15mm away from the display area. Therefore, the ink may not be covered in the area 0 to 0.3mm away from the boundary of the display area. The large piece of metal of the common electrode bus leaked in this area will still cause a bright metal edge.
  • the array substrate faces the user, and a large piece of metal is usually arranged on the array substrate. If the distribution density of the metal is too high, reflection is very likely to occur. In particular, in the area where the gate drive circuit and/or the common electrode bus of the array substrate are located, it is easy to have a large piece of metal, resulting in a high distribution density of the metal, thereby causing reflection. For the display area, the distribution density and width of the large piece of metal will not be very large, so the reflection phenomenon is not particularly obvious.
  • a layer of ink can be applied to block the metal reflection. For example, the ink coating can be carried out after the display panel is matched.
  • the ink can be applied to the four peripheral areas of the array substrate facing the user, and the ink is applied along the outer edge of the array substrate to the center of the array substrate.
  • the end point of the coating is at a certain distance from the display area, and the peripheral area within this certain distance range is covered by the diffusion of the ink.
  • the ink is irradiated with the device (with UV curing) that has applied the ink to solidify the ink, and then the polarizer is attached.
  • the ink may not completely cover the peripheral area within a certain distance range. As a result, the larger metal pieces in the non-display area of the array substrate will still reflect ambient light to form bright metal edges, thus affecting the display effect.
  • the array substrate 1 may include: a base substrate 10, the base substrate 10 includes a first surface 101 and a second surface 102 arranged opposite to each other, the base substrate 10 includes a display area AA and a peripheral area NA surrounding the display area, the peripheral area NA includes a first peripheral area NA1 and a second peripheral area NA2, the first peripheral area NA1 surrounds the display area AA, and the second peripheral area NA2 surrounds the first peripheral area NA1. That is, the first peripheral area NA1 is a part of the peripheral area NA close to the display area AA, and the second peripheral area NA2 is a part of the peripheral area NA away from the display area AA.
  • display area refers to the area of effective display pixels.
  • ink can be applied to the four peripheral areas of the array substrate facing the user, and the ink is applied along the outer edge of the array substrate toward the center of the array substrate, and the end point of the coating is at a certain distance from the display area.
  • the peripheral area within this certain distance range is covered by ink diffusion.
  • the certain distance may be about 300 microns.
  • the first peripheral area NA1 may correspond to a peripheral area within a certain distance, that is, the width of the first peripheral area NA1 may be about 300 microns.
  • the first peripheral area NA1 may be an annular area that extends outward from the outer boundary of the display area AA by a certain distance (e.g., about 300 microns).
  • the array substrate may further include a shading layer 2, which is located on the first surface 101 of the base substrate, the orthographic projection of the shading layer 2 on the base substrate 10 is located in the peripheral area NA, and the orthographic projection of at least a portion of the shading layer 2 on the base substrate 10 is located in the second peripheral area NA2.
  • a shading layer 2 which is located on the first surface 101 of the base substrate, the orthographic projection of the shading layer 2 on the base substrate 10 is located in the peripheral area NA, and the orthographic projection of at least a portion of the shading layer 2 on the base substrate 10 is located in the second peripheral area NA2.
  • the material of the light shielding layer 2 may be ink.
  • b is the design center value of the ink
  • a and c are respectively the maximum ranges of the ink that may deviate from the design center value, for example, about ⁇ 150 micrometers.
  • the orthographic projection of the light shielding layer 2 on the base substrate 10 is arranged around the display area AA, and there is a gap d between the orthographic projection of the light shielding layer 2 on the base substrate 10 and the display area AA.
  • the value range of the gap d may be greater than 0 and less than or equal to 300 micrometers.
  • the display panel may adopt a vertical ADS structure to improve the aperture ratio of the pixel unit.
  • the array substrate may include a common electrode CE and a pixel electrode PE disposed on a base substrate 10.
  • the common electrode CE may be located on a side closer to the user.
  • the pixel electrode PE may be located on a side closer to the user.
  • the common electrode CE and the pixel electrode PE can generate a corresponding liquid crystal electric field under the drive of a driving signal, and the liquid crystal in the liquid crystal layer can be deflected under the action of the liquid crystal electric field, thereby realizing a corresponding display function.
  • the pixel unit P may include a plurality of sub-pixels 23.
  • the plurality of sub-pixels 23 are divided into a plurality of groups, at least one group includes two adjacent rows of sub-pixels 23, and the sub-pixels 23 of different groups belong to different rows.
  • the plurality of rows of sub-pixels 23 are repeatedly arranged in the array substrate with two rows as a period, and for any group of sub-pixels 23, the pixel electrodes PE of one row of sub-pixels 23 extend toward the first direction, and the pixel electrodes PE of another row of sub-pixels 23 extend toward the second direction.
  • the array substrate may adopt a sub-pixel structure design with two images and two domains.
  • the touch electrode 22 can be reused as a common electrode of a sub-pixel, which will be described in detail below and will not be described here.
  • the touch electrode 22 includes a plurality of touch units 221, at least one touch unit 221 is connected to at least one touch line 24, and different touch units 221 are connected to different touch lines 24, for example, each touch unit 221 is connected to one touch line 24, or each touch unit 221 is connected to multiple touch lines 24, which can be determined according to actual needs and is not limited here.
  • Each touch unit 221 can be connected to a touch recognition module via a touch line 24, for example, each touch unit 221 is connected to a pin of the touch recognition module via a touch line 24.
  • the non-display area NA of the display substrate includes a signal input side (the lower side of the display area AA in FIG. 4 ).
  • a driver chip IC may be provided, and the touch recognition module may be integrated in the driver chip IC.
  • the driver chip IC may be a TDDI chip.
  • a plurality of touch lines 24 may extend along the second direction D2 to the lower side of the display area AA, thereby connecting to the touch recognition module.
  • the TDDI chip may provide a driving signal for display to the touch unit 221 through the touch line 24.
  • the touch unit 221 is multiplexed as a common electrode, and a corresponding electric field may be formed between the pixel electrode and the common electrode to realize the display function.
  • the TDDI chip may provide a touch signal for touch recognition to realize the touch function.
  • the array substrate may include: a second metal conductive layer 12 disposed on a base substrate 10, a first metal conductive layer 11 disposed on a side of the second metal conductive layer 12 away from the base substrate 10, a second transparent conductive layer 14 disposed on a side of the first metal conductive layer 11 away from the base substrate 10, and a first transparent conductive layer 13 disposed on a side of the second transparent conductive layer 14 away from the base substrate 10.
  • the array substrate may also include multiple insulating layers, for example, a buffer layer BFL arranged between the base substrate 10 and the second metal conductive layer 12, a first insulating layer IL1 arranged between the second metal conductive layer 12 and the first metal conductive layer 11, a second insulating layer IL2 arranged between the first metal conductive layer 11 and the second transparent conductive layer 14, and a third insulating layer IL3 arranged between the second transparent conductive layer 14 and the first transparent conductive layer 13.
  • a buffer layer BFL arranged between the base substrate 10 and the second metal conductive layer 12
  • a first insulating layer IL1 arranged between the second metal conductive layer 12 and the first metal conductive layer 11
  • a second insulating layer IL2 arranged between the first metal conductive layer 11 and the second transparent conductive layer
  • a third insulating layer IL3 arranged between the second transparent conductive layer 14 and the first transparent conductive layer 13.
  • the pixel unit includes a pixel driving circuit, the pixel driving circuit includes at least one thin film transistor, and the thin film transistor includes an active layer, a gate, a source electrode, and a drain electrode.
  • the gate electrode of the thin film transistor is located in the second metal conductive layer 12, and the source electrode and the drain electrode of the thin film transistor are located in the first metal conductive layer 11.
  • One of the pixel electrode PE and the common electrode CE can be located in the first transparent conductive layer 13, and the other of the pixel electrode PE and the common electrode CE can be located in the second transparent conductive layer 14.
  • the array substrate includes data signal lines DL and scan signal lines GL.
  • the data signal lines DL are used to transmit data signals to each pixel unit P.
  • the scan signal lines GL are used to transmit gate scan signals to each pixel unit P.
  • the data signal lines DL may extend from the peripheral area NA to the display area AA
  • the scan signal lines GL may extend from the peripheral area NA to the display area AA.
  • the scan signal lines GL may extend mainly along the first direction D1
  • the data signal lines DL may extend mainly along the second direction D2.
  • the scan signal lines GL may be located in the second metal conductive layer 12, and the data signal lines DL may be located in the first metal conductive layer 11.
  • the array substrate may further include common electrode lines CL.
  • the common electrode lines CL are used to transmit common voltage signals to the common electrodes.
  • the common electrode lines CL may extend from the peripheral area NA to the display area AA.
  • the common electrode lines CL may extend mainly along the first direction D1.
  • the common electrode lines CL may be located in the second metal conductive layer 12.
  • a plurality of second via holes VH2 may be provided, and the common electrode line CL may be electrically connected to the common electrode bus through the plurality of second via holes VH2.
  • the common electrode line CL may be electrically connected to the first common electrode bus 3 through the plurality of second via holes VH2.
  • the array substrate may further include a first common electrode bus 3, the first common electrode bus 3 is located on the second surface 102 of the base substrate 10, the orthographic projection of the first common electrode bus 3 on the base substrate 10 is at least partially located in the second peripheral area NA2, and the first common electrode bus 3 is electrically connected to the common electrode CE.
  • the first common electrode bus 3 is used to provide a first voltage signal to the common electrode CE.
  • the first common electrode bus 3 may be located in the first metal conductive layer 11.
  • the distribution density of the first common electrode bus 3 in the first peripheral area NA1 is less than the distribution density of the first common electrode bus 3 in the second peripheral area NA2.
  • the first common electrode bus 3 may include a first portion 31 located in the first peripheral area NA1 and a second portion 32 located in the second peripheral area NA2, and the distribution density of the first portion 31 of the first common electrode bus 3 located in the first peripheral area NA1 is less than the distribution density of the second portion 32 of the first common electrode bus 3 located in the second peripheral area NA2.
  • the first common electrode bus 3 does not include the portion located in the first peripheral area NA1, and the first common electrode bus 3 may only include the portion located in the second peripheral area NA2.
  • the distribution density of the first common electrode bus 3 in the first peripheral area NA1 is substantially 0, and the distribution density of the first common electrode bus 3 in the second peripheral area NA2 is greater than 0. It can also be considered that the distribution density of the first common electrode bus 3 in the first peripheral area NA1 is less than the distribution density of the first common electrode bus 3 in the second peripheral area NA2.
  • the common electrode line CL may be electrically connected to the second portion 32 of the first common electrode bus 3 through a plurality of second via holes VH2 .
  • the expression “distribution density” herein refers to the area occupied by the portion of the first common electrode bus within a unit area in the area surrounded by the outer edge of the first common electrode bus.
  • the reflection area of the common electrode bus 3 in the area is greatly reduced, thereby effectively improving the metal bright edge problem.
  • the second portion 32 of the first common electrode bus 3 located in the second peripheral area NA2 includes a block metal portion.
  • the first portion 31 of the first common electrode bus 3 located in the first peripheral area NA1 includes a strip metal portion 312.
  • the first portion 31 of the first common electrode bus 3 located in the first peripheral area NA1 includes a plurality of strip metal portions 312 and a plurality of strip slits 311, and the plurality of strip metal portions 312 and the plurality of strip slits 311 are alternately arranged in a direction pointing from the edge of the base substrate 10 to the display area AA.
  • the second portion 32 is a bulk metal portion.
  • the expression “bulk metal portion” may refer to a continuous whole piece of metal without a hollow structure in the middle.
  • the ratio of the length of the plurality of strip-shaped slits in the extension direction to the width of the strip-shaped slits in the direction perpendicular to the extension direction is greater than 10.
  • the ratio of the length of the plurality of strip-shaped metal portions in the extension direction to the width of the strip-shaped metal portions in the direction perpendicular to the extension direction is greater than 10. That is, in the first peripheral area NA1, the slits or metal portions of the first common electrode bus 3 have a large aspect ratio, thereby presenting a strip-shaped structure.
  • a plurality of strip-shaped slits are formed in the portion of the first common electrode bus 3 located in the first peripheral area NA1.
  • the base substrate 10 may include a first side, a second side, a third side and a fourth side, the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other.
  • the scan signal line GL extends from the first side toward the second side
  • the data signal line DL extends from the third side toward the fourth side.
  • the first side and the second side may be the left side and the right side of the base substrate 10, respectively
  • the third side and the fourth side may be the upper side and the lower side of the base substrate 10, respectively.
  • multiple strip metal parts 312 and multiple strip slits 311 are alternately arranged in the left-right direction.
  • multiple strip metal parts 312 and multiple strip slits 311 are alternately arranged in the up-down direction.
  • the strip slit 311 includes a first width W1 along a first direction
  • the strip metal portion 312 includes a second width W2 along the first direction
  • the first direction is substantially perpendicular to the extension direction of the strip slit or the strip metal portion.
  • the first direction is the left-right direction
  • the first direction is the up-down direction.
  • the value of the first width W1 divided by the sum of the first width W1 and the second width W2 is greater than 0.5.
  • the value of the first width W1 divided by the sum of the first width W1 and the second width W2 is greater than 0.52 and is between 0.52 and 0.9.
  • the inventors have found through research that in the embodiments of the present disclosure, as long as the hollowing ratio of the strip slit (ie, the value of the first width W1 divided by the sum of the first width W1 and the second width W2) is greater than 0.5, the metal reflection phenomenon is visually imperceptible.
  • the orthographic projection of the boundary 33 of the first common electrode bus 3 close to the display area AA on the base substrate 10 is located at the junction of the first peripheral area NA1 and the second peripheral area NA2 .
  • the orthographic projection of the boundary 33 of the first common electrode bus 3 close to the display area AA on the base substrate 10 is located within the orthographic projection of the light shielding layer 2 on the base substrate 10 .
  • the first common electrode bus is basically not arranged in the first peripheral area NA1, that is, by not arranging the common electrode bus 3 in the peripheral area that may not be blocked by the shading layer 2, the reflection area of the common electrode bus 3 in the area is reduced to basically 0, thereby effectively improving the metal bright edge problem.
  • At least two columns of virtual pixel units DPX are provided in a first peripheral area NA1 of at least one of the first side and the second side.
  • the virtual pixel unit DPX may be a virtual sub-pixel unit, for example, one of the three RGB sub-pixels.
  • At least one row of dummy pixel units DPX is disposed in the first peripheral area NA1 of at least one of the third side and the fourth side.
  • a pixel driving circuit may be provided on the array substrate, and the pixel driving circuit may include a transistor.
  • FIG. 14 schematically illustrates a source TS and a drain TD of a transistor, and the drain TD of the transistor may be electrically connected to the pixel unit through a first via hole VH1, for example, electrically connected to a pixel electrode of a sub-pixel.
  • a via hole for electrically connecting the drain TD of the transistor to the pixel unit is not formed, that is, for the virtual pixel unit DPX, its pixel driving circuit is not electrically connected to the pixel electrode.
  • the array substrate may further include a second common electrode bus 4, the second common electrode bus 4 is located on the second surface 102 of the base substrate, the orthographic projection of the second common electrode bus 4 on the base substrate is located in the first peripheral area NA1 and the second peripheral area NA2, and the second common electrode bus 4 is electrically connected to the first common electrode bus 3.
  • the second common electrode bus 4 is located in the first transparent conductive layer 13.
  • the second common electrode bus 4 includes a block-shaped conductive portion.
  • the second common electrode bus 4 can be made of a transparent conductive material such as indium tin oxide. Therefore, the second common electrode bus 4 with a block structure can directly transmit light without reflecting light, and will not cause a bright edge problem.
  • the second common electrode bus 4 is electrically connected to the first common electrode bus 3 for transmitting the first voltage signal in parallel, which can effectively reduce the total resistance on the common electrode bus, thereby reducing the impact of IR drop.
  • the first portion 31 of the first common electrode bus 3 located in the first peripheral area NA1 includes a plurality of first strip metal parts 3121 and a plurality of second strip metal parts 3122, the plurality of first strip metal parts 3121 extend along the second direction D2, the plurality of second strip metal parts 3122 extend along the third direction D3, and the second direction D2 and the third direction D3 intersect.
  • the first direction D1 and the third direction D3 intersect.
  • the plurality of first strip metal parts 3121 and the plurality of second strip metal parts 3122 form a grid, and the grid has a plurality of hollow slits inside.
  • the third direction D3 intersects with the first direction D1, so that the slits are arranged irregularly along the first direction, avoiding problems such as moiré caused by the transmission and/or reflection of light.
  • the second common electrode bus 4 includes at least one second opening 41, at least one second opening 41 is located in the first peripheral area NA1, and the orthographic projection of at least one intersection between the plurality of first strip-shaped metal portions 3121 and the plurality of second strip-shaped metal portions 3122 on the substrate at least partially overlaps with the orthographic projection of the at least one second opening 41 on the substrate.
  • a portion of the scan signal line GL located in the peripheral area includes a first scan signal sub-portion GL1 and a second scan signal sub-portion GL2, the first scan signal sub-portion GL1 extends along a first direction D1, the second scan signal sub-portion GL2 extends along a second direction D2, and the first direction D1 and the second direction D2 intersect.
  • the extension direction of the second scan signal sub-portion GL2 and the data signal line DL is substantially parallel.
  • the second scan signal sub-portion GL2 and the adjacent common electrode bus located in the first metal conductive layer 11 can be made not to overlap, so that the overlapping area of the scan signal line GL located in the second metal conductive layer 12 and the common electrode bus located in the first metal conductive layer 11 can be minimized, so that the generated parasitic capacitance can be reduced, and the load on the scan signal line and the common electrode bus can be reduced.
  • the orthographic projection of the first scan signal sub-unit GL1 on the base substrate at least partially overlaps with the orthographic projection of at least one second opening 41 on the base substrate.
  • at least one second opening 41 is provided in the first transparent conductive layer 13, so that the overlapping area between the second common electrode bus 4 located in the first transparent conductive layer 13 and the first scan signal sub-unit GL1 thereunder can be reduced, thereby reducing the generated parasitic capacitance and reducing the load on the scan signal line and the common electrode bus.
  • the orthographic projection of at least one intersection of the first strip metal portion 3121, the second strip metal portion 3122 and the first scan signal sub-portion GL1 on the base substrate at least partially overlaps with the orthographic projection of at least one second opening 41 on the base substrate.
  • at least one second opening 41 located in the first transparent conductive layer 13 exposes the first common electrode bus and the scan signal line below, which can reduce the overlapping area between the three, so that the generated parasitic capacitance can be reduced, and the load on the scan signal line and the common electrode bus can be reduced.
  • the second portion 32 of the first common electrode bus 3 located in the second peripheral area NA2 includes at least one first opening 321, and the orthographic projection of the at least one first opening 321 of the first common electrode bus on the base substrate overlaps at least partially with the orthographic projection of the first scan signal sub-unit GL1 on the base substrate.
  • at least one first opening 321 is provided in the first metal conductive layer 11, so that the overlapping area between the first common electrode bus 3 located in the first metal conductive layer 11 and the first scan signal sub-unit GL1 thereunder can be reduced, so that the generated parasitic capacitance can be reduced, and the load on the scan signal line and the common electrode bus can be reduced.
  • the first transparent conductive layer 13 may further include at least one third opening 42, and the orthographic projection of the second scan signal sub-portion GL2 on the base substrate at least partially overlaps with the orthographic projection of the at least one third opening 42 on the base substrate.
  • at least one third opening 42 is provided in the first transparent conductive layer 13, so that the overlapping area between the second common electrode bus 4 located in the first transparent conductive layer 13 and the second scan signal sub-portion GL2 thereunder can be reduced, so that the generated parasitic capacitance can be reduced, and the load on the scan signal line and the common electrode bus can be reduced.
  • the first transparent conductive layer 13 may further include at least one fourth opening 43, and the position of the fourth opening 43 may correspond to the position of the first opening 321, that is, the orthographic projection of the fourth opening 43 on the base substrate may at least partially overlap with the orthographic projection of the first opening 321 on the base substrate, for example, the orthographic projection of the fourth opening 43 on the base substrate may substantially coincide with the orthographic projection of the first opening 321 on the base substrate.
  • At least one fourth opening 43 is provided in the first transparent conductive layer 13, which can reduce the overlapping area of the second common electrode bus 4 located in the first transparent conductive layer 13 and the first scan signal sub-portion GL1 thereunder, so that the generated parasitic capacitance can be reduced, and the load on the scan signal line and the common electrode bus can be reduced.
  • Embodiments of the present disclosure also provide a display device, which includes the above-mentioned array substrate or display panel.
  • display devices include tablet personal computers (PCs), smart phones, personal digital assistants (PDAs), portable multimedia players, game consoles, or wristwatch-type electronic devices.
  • PCs personal computers
  • PDAs personal digital assistants
  • portable multimedia players Portable multimedia players
  • game consoles or wristwatch-type electronic devices.
  • the embodiments of the present disclosure are not intended to limit the type of display device.
  • the display device can be used not only in large electronic devices such as televisions (TVs) or external billboards, but also in medium or small electronic devices such as PCs, notebook computers, car navigation devices, or cameras.

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Abstract

一种阵列基板（1）和显示装置。阵列基板（1）包括：衬底基板（10），包括相反设置的第一表面（101）和第二表面（102），衬底基板（10）包括显示区（AA）、第一周边区（NA1）和第二周边区（NA2）；多个像素单元（P），位于衬底基板（10）的第二表面（102）上，多个像素单元（P）在衬底基板（10）上的正投影位于显示区（AA）内，且呈阵列分布，至少一部分像素单元（P）包括公共电极（CE）；遮光层（2），位于衬底基板（10）的第一表面（101）上，遮光层（2）在衬底基板（10）上的正投影位于周边区（NA）内，遮光层（2）的至少一部分在衬底基板（10）上的正投影位于第二周边区（NA2）内；第一公共电极总线（3），位于衬底基板（10）的第二表面（102）上，第一公共电极总线（3）在衬底基板（10）上的正投影至少部分位于第二周边区（NA2）内，第一公共电极总线（3）与公共电极（CE）电连接。第一公共电极总线（3）的材料包括金属材料，第一公共电极总线（3）在第一周边区（NA1）内的分布密度小于第一公共电极总线（3）在第二周边区（NA2）内的分布密度。

Description

阵列基板和显示装置 技术领域
本公开涉及显示技术领域，具体地涉及一种阵列基板和显示装置。
背景技术
目前，为实现窄边框甚至无边框设计，需要将阵列基板设置在显示面板的出光侧，将对置基板设置在显示面板的入光侧。然而，在阵列基板的非显示区，需要设置较大块金属，这些大块金属会反射环境光造成金属亮边，影响显示效果。
在本部分中公开的以上信息仅用于对本公开的技术构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
根据本公开的一个方面，提供了一种阵列基板，包括：衬底基板，所述衬底基板包括相反设置的第一表面和第二表面，所述衬底基板包括显示区和环绕所述显示区的周边区，所述周边区包括第一周边区和第二周边区，所述第一周边区环绕所述显示区，所述第二周边区环绕所述第一周边区；多个像素单元，所述多个像素单元位于所述衬底基板的第二表面上，所述多个像素单元在所述衬底基板上的正投影位于所述显示区内，且呈阵列分布，至少一部分所述像素单元包括公共电极；遮光层，所述遮光层位于所述衬底基板的第一表面上，所述遮光层在所述衬底基板上的正投影位于所述周边区内，所述遮光层的至少一部分在所述衬底基板上的正投影位于所述第二周边区内；以及第一公共电极总线，所述第一公共电极总线位于所述衬底基板的第二表面上，所述第一公共电极总线在所述衬底基板上的正投影至少部分位于所述第二周边区内，所述第一公共电极总线与所述公共电极电连接，其中，所述第一公共电极总线的材料包括金属材料，所述第一公共电极总线在所述第一周边区内的分布密度小于所述第一公共电极总线在所述第二周边区内的分布密度。
根据一些示例性的实施例，所述第一公共电极总线包括位于所述第一周边区内的第一部分和位于所述第二周边区内的第二部分，所述第二部分包括块状金属部；以及 所述第一部分包括条状金属部。
根据一些示例性的实施例，所述第一公共电极总线位于所述第一周边区内的第一部分包括多个条状金属部和至少一个条状狭缝，所述多个条状金属部和所述至少一个条状狭缝沿所述衬底基板的边缘指向所述显示区的方向交替排列。
根据一些示例性的实施例，所述条状狭缝包括沿第一方向的第一宽度，所述条状金属部包括沿第一方向的第二宽度，所述第一方向基本垂直于所述条状狭缝或所述条状金属部的延伸方向；以及所述第一宽度除以所述第一宽度和所述第二宽度之和的值在0.5以上。
根据一些示例性的实施例，所述第一公共电极总线靠近所述显示区的边界在所述衬底基板上的正投影位于所述第一周边区和所述第二周边区的交界处。
根据一些示例性的实施例，所述第一公共电极总线靠近所述显示区的边界在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影内。
根据一些示例性的实施例，所述衬底基板包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧相对设置，所述第三侧和所述第四侧相对设置；所述阵列基板还包括设置在所述衬底基板的第二表面上的数据信号线和扫描信号线，所述扫描信号线从所述第一侧朝向所述第二侧延伸，所述数据信号线从所述第三侧朝向所述第四侧延伸；在所述第一侧和所述第二侧中至少一个的第一周边区内，设置有至少两列虚拟像素单元。
根据一些示例性的实施例，所述衬底基板包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧相对设置，所述第三侧和所述第四侧相对设置；所述阵列基板还包括设置在所述衬底基板的第二表面上的数据信号线和扫描信号线，所述扫描信号线从所述第一侧朝向所述第二侧延伸，所述数据信号线从所述第三侧朝向所述第四侧延伸；在所述第一侧和所述第二侧中至少一个的第一周边区内，在所述第一部分和所述显示区之间至少设置有一列虚拟像素单元。
根据一些示例性的实施例，在所述第三侧和所述第四侧中至少一个的第一周边区内，设置有至少一行虚拟像素单元。
根据一些示例性的实施例，所述阵列基板还包括第二公共电极总线，所述第二公共电极总线位于所述衬底基板的第二表面上，所述第二公共电极总线在所述衬底基板上的正投影位于所述第一周边区和所述第二周边区内，所述第二公共电极总线与所述第一公共电极总线电连接。
根据一些示例性的实施例，所述阵列基板包括设置在所述衬底基板的第二表面上的第一金属导电层和第一透明导电层，所述第一公共电极总线位于所述第一金属导电层中，所述第二公共电极总线位于所述第一透明导电层中。
根据一些示例性的实施例，在所述第一侧和所述第二侧的至少一个中，所述第一公共电极总线位于所述第一周边区内的第一部分包括多个第一条状金属部和多个第二条状金属部，所述多个第一条状金属部沿第二方向延伸，所述多个第二条状金属部沿第三方向延伸，所述第二方向和所述第三方向交叉。
根据一些示例性的实施例，所述第一方向和所述第三方向交叉。
根据一些示例性的实施例，在所述第一侧和所述第二侧的至少一个中，所述第一公共电极总线位于所述第一周边区内的第一部分包括多个第一条状金属部和多个第二条状金属部，所述多个第一条状金属部沿第二方向延伸，所述多个第二条状金属部沿第三方向延伸，所述第二方向和所述第三方向交叉。
根据一些示例性的实施例，所述第二公共电极总线包括至少一个第二开孔，所述至少一个第二开孔位于所述第一周边区中，所述多个第一条状金属部和所述多个第二条状金属部之间的至少一个相交部分在所述衬底基板上的正投影与所述至少一个第二开孔在所述衬底基板上的正投影至少部分交叠。
根据一些示例性的实施例，所述衬底基板包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧相对设置，所述第三侧和所述第四侧相对设置；所述阵列基板还包括设置在所述衬底基板的第二表面上的数据信号线和扫描信号线，所述扫描信号线从所述第一侧朝向所述第二侧延伸，所述数据信号线从所述第三侧朝向所述第四侧延伸；在所述第一侧和所述第二侧中至少一个的第一周边区内，在所述第一部分和所述显示区之间至少设置有一列虚拟像素单元。
根据一些示例性的实施例，所述阵列基板还包括第二公共电极总线，所述第二公共电极总线位于所述衬底基板的第二表面上，所述第二公共电极总线在所述衬底基板上的正投影位于所述第一周边区和所述第二周边区内，所述第二公共电极总线与所述第一公共电极总线电连接。
根据一些示例性的实施例，在所述第一侧和所述第二侧的至少一个中，所述第一公共电极总线位于所述第一周边区内的第一部分包括多个第一条状金属部和多个第二条状金属部，所述多个第一条状金属部沿第二方向延伸，所述多个第二条状金属部沿第三方向延伸，所述第二方向和所述第三方向交叉。
根据一些示例性的实施例，所述第二公共电极总线包括至少一个第二开孔，所述至少一个第二开孔位于所述第一周边区中，所述多个第一条状金属部和所述多个第二条状金属部之间的至少一个相交部分在所述衬底基板上的正投影与所述至少一个第二开孔在所述衬底基板上的正投影至少部分交叠。
根据一些示例性的实施例，在所述第一侧和所述第二侧的至少一个中，所述扫描信号线位于所述周边区中的部分包括第一扫描信号子部和第二扫描信号子部，所述第一扫描信号子部沿第一方向延伸，所述第二扫描信号子部沿第二方向延伸，所述第一方向和所述第二方向交叉；以及所述第二扫描信号子部和所述数据信号线的延伸方向基本平行。
根据一些示例性的实施例，所述第一扫描信号子部在所述衬底基板上的正投影与所述至少一个第二开孔在所述衬底基板上的正投影至少部分交叠；和/或，所述第一条状金属部、所述第二条状金属部和所述第一扫描信号子部三者之间的至少一个相交部分在所述衬底基板上的正投影与所述至少一个第二开孔在所述衬底基板上的正投影至少部分交叠。
根据一些示例性的实施例，所述第二部分包括至少一个第一开孔，所述至少一个第一开孔在所述衬底基板上的正投影与所述第一扫描信号子部在所述衬底基板上的正投影至少部分交叠。
根据一些示例性的实施例，所述至少一个条状狭缝在其延伸方向上的长度与该条状狭缝在垂直于其延伸方向的方向上的宽度之比在10以上。
根据一些示例性的实施例，所述阵列基板还包括设置在所述衬底基板的第二表面上的数据信号线和扫描信号线，所述阵列基板还包括：设置在所述衬底基板上的第二金属导电层；和设置在所述衬底基板上的第二透明导电层；所述数据信号线位于所述第一金属导电层，所述扫描信号线位于所述第二金属导电层；以及至少一部分所述像素单元还包括像素电极，所述像素电极位于所述第一透明导电层，所述公共电极位于所述第二透明导电层。
在另一方面，提供一种显示装置，包括：如上所述的阵列基板；与所述阵列基板相对设置的对置基板；以及位于所述阵列基板与所述对置基板之间的液晶层，其中，所述显示装置的出光面为所述阵列基板中所述衬底基板的第一表面。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述内容以及其他目的、特征和优点将更为清楚，在附图中：
图1是根据本公开的一些示例性实施例的显示面板的结构示意图。
图2A和图2B分别是根据本公开的一些示例性实施例的阵列基板的结构示意图，其示意性示出了像素单元的电极布置。
图3A是根据本公开的一些示例性实施例的阵列基板的平面示意图。
图3B是图3A中的部分I的局部放大图。
图4是根据本公开的一些示例性实施例的阵列基板的平面示意图，其示意性示出了像素单元的布置。
图5是根据本公开的一些示例性实施例的阵列基板的平面示意图，其示意性示出了像素单元的更详细布置。
图6是根据本公开的一些示例性实施例的阵列基板在图3A中的部分II处的局部放大图。
图7是根据本公开的一些示例性实施例的阵列基板在图3A中的部分III处的局部放大图。
图8是根据本公开的一些示例性实施例的阵列基板在图6中的部分IV处的局部放大图。
图9是根据本公开的一些示例性实施例的阵列基板在图7中的部分V处的局部放大图。
图10A是图9中的部分在一个金属导电层中的平面示意图。
图10B是图9中的部分在两个金属导电层中的平面示意图。
图10C是图9中的部分在两个金属导电层和一个透明导电层中的平面示意图。
图10D是图9中的部分在两个金属导电层和两个透明导电层中的平面示意图。
图11是根据本公开的另一些示例性实施例的阵列基板在图7中的部分IV处的局部放大图。
图12是根据本公开的一些示例性实施例的阵列基板沿图3B中的线AA’截取的示意截面图。
图13是根据本公开的另一些示例性实施例的阵列基板在图7中的部分IV处的局部放大图。
图14是根据本公开的一些示例性实施例的阵列基板在图3A中的部分II处的局部 放大图，其示意性示出了更详细布置。
图15是根据本公开的一些示例性实施例的阵列基板的平面示意图，其示意性示出了像素单元和虚拟像素单元。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，元件可以直接在另一元件上、直接连接到另一元件或直接结合到另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
需要说明的是，表述“同一层”，“同层设置”或类似表述，指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本文中，除非另有说明，表述“电连接”可以表示两个部件或元件直接电连接， 例如，部件或元件A与部件或元件B直接接触，并且二者之间可以传递电信号；也可以表示两个部件或元件通过例如导电线的导电媒介电连接，例如，部件或元件A通过导电线与部件或元件B电连接，以在两个部件或元件之间传递电信号；还可以表示两个部件或元件通过至少一个电子元器件电连接，例如，部件或元件A通过至少一个薄膜晶体管与部件或元件B电连接，以在两个部件或元件之间传递电信号。
图1是根据本公开的一些示例性实施例的显示面板的结构示意图。如图1所示，在一些实施例中，显示面板可以为液晶显示面板，例如，液晶显示面板可以采用In-cell技术实现显示和触控的集成。示例性地，在根据本公开实施例的液晶显示面板中，可以采用FIC(Full In Cell的缩写)技术。
在FIC技术中，采用单层触控走线设计，利用自电容原理，实现多点触控。为了解决显示功能和触控功能集成后带来的信号干扰，FIC技术采取“分时扫描”的方式，将单位时间分为两部分，一部分用于触控扫描，另一部分用于显示扫描，互不干扰。
参照图1，显示面板可以包括阵列基板1、对置基板7和位于阵列基板1与对置基板7之间的液晶层9，对置基板7和阵列基板1相对设置。
对于非触控的常规显示面板而言，对置基板7位于显示面板的出光侧，为了防止静电，通常会在对置基板7的背面涂覆一层透明导电层(例如ITO层)。
对于采用FIC技术的触控显示面板而言，如果使对置基板7位于显示面板的出光侧，那么，当手指触控显示面板时，上述用于防止静电的透明导电层会影响触控效果。
在本公开的实施例中，阵列基板1位于显示面板的出光侧，对置基板7位于显示面板的入光侧。具体地，显示面板还包括背光模组8，对置基板7比阵列基板1更靠近背光模组8。
发明人经研究发现，用户对显示产品外观的审美越来越高，无边框显示产品因外观精致美观，尤其是4边无边框显示产品，其外观更让人感受高端，深受客户的喜爱。4边无边框显示产品包括显示区和围绕显示区的周边区(即非显示区)。周边区内设置有扇出线、栅极驱动电路和公共电极总线等较大块金属，这些大块金属会反射环境光造成金属亮边，影响显示效果。通过在周边区用油墨涂覆，可以避免大块金属反光。然而，受油墨涂覆精度的限制，例如，涂覆的油墨通常存在±0.15mm偏移，为避免油墨侵入显示区，油墨设计中心值需与显示区之间距离0.15mm，因此在距离显示区边界0～0.3mm的区域内油墨可能无覆盖，在此区域内所漏出公共电极总线的大块金属依然会造成金属亮边。
也就是说，显示产品使用时采用阵列基板面向使用者，而阵列基板上通常会设置较大块金属，如果金属的分布密度过高，那么极易发生反光现象。特别是阵列基板的栅极驱动电路和/或公共电极总线所在的区域，容易存在较大块金属，导致金属的分布密度过高，从而发生反光现象。对于显示区而言，大块金属的分布密度及宽度不会很大，所以反光现象不是特别明显。针对四边窄边框或四边无边框设计，可以涂覆一层油墨来遮挡金属反光。例如，油墨涂覆可以在显示面板的对盒完成后进行，具体地，可以在朝着用户的阵列基板的四个周边区涂覆油墨，油墨沿着阵列基板的外边缘往阵列基板的中心进行涂覆，涂覆的终结点在距离显示区的一定距离处，这一定距离范围内的周边区靠着油墨扩散来遮盖。涂覆完油墨后，采用涂覆完油墨的设备(自带UV固化)照射油墨，使油墨凝固，然后进行偏光片的贴附。然而，发明人经研究发现，实际情况下油墨可能不会完全覆盖一定距离范围内的周边区。结果是，阵列基板的非显示区中的较大块金属仍会反射环境光造成金属亮边，影响显示效果。
结合参照图3A、图3B、图12和图15，阵列基板1可以包括：衬底基板10，衬底基板10包括相反设置的第一表面101和第二表面102，衬底基板10包括显示区AA和环绕显示区的周边区NA，周边区NA包括第一周边区NA1和第二周边区NA2，第一周边区NA1环绕显示区AA，第二周边区NA2环绕第一周边区NA1。即，第一周边区NA1为周边区NA靠近显示区AA的一部分，第二周边区NA2为周边区NA远离显示区AA的一部分。
需要说明的是，在本文中，表述“显示区”表示有效显示像素的区域。
如上所述，在涂覆油墨的过程中，可以在朝着用户的阵列基板的四个周边区涂覆油墨，油墨沿着阵列基板的外边缘往阵列基板的中心进行涂覆，涂覆的终结点在距离显示区的一定距离处，这一定距离范围内的周边区靠着油墨扩散来遮盖。例如，所述一定距离可以为约300微米。在本公开的实施例中，第一周边区NA1可以对应一定距离内的周边区，即，第一周边区NA1的宽度可以为约300微米。换句话说，第一周边区NA1可以为自显示区AA的外边界向外扩展一定距离(例如约300微米)的环形区域。
阵列基板还可以包括遮光层2，遮光层2位于衬底基板的第一表面101上，遮光层2在衬底基板10上的正投影位于周边区NA内，遮光层2的至少一部分在衬底基板10上的正投影位于第二周边区NA2内。
可选地，遮光层2的材料可以为油墨，结合参照图3A和图3B，b为油墨的设计 中心值，a、c分别为油墨可能偏移设计中心值的最大范围，例如约±150微米。在可选的实施例中，遮光层2在衬底基板10上的正投影环绕显示区AA设置，且遮光层2在衬底基板10上的正投影与显示区AA之间存在间隙d。例如，该间隙d的取值范围可以大于0小于等于300微米。
在本公开的实施例中，显示面板可以采用竖向的ADS结构，以提升像素单元的开口率。参照图2A和图2B，阵列基板可以包括设置在衬底基板10上的公共电极CE和像素电极PE。在一个示例中，如图2A所示，公共电极CE可以位于更靠近用户的一侧。在另一个示例中，如图2B所示，像素电极PE可以位于更靠近用户的一侧。
在阵列基板中，公共电极CE和像素电极PE能够在驱动信号的驱动下产生相应的液晶电场。液晶层中的液晶能够在液晶电场的作用下偏转，从而实现相应的显示功能。
可选地，参照图4和图5，像素单元P可以包括多个子像素23。多个子像素23划分为多组，至少一组包括相邻的两行子像素23，不同组的子像素23属于不同行，换句话说，在本公开实施例中，多行子像素23以两行为周期，重复地布设在阵列基板中，并且，对于任意一组子像素23而言，其中一行子像素23的像素电极PE朝向第一方向延伸，另一行子像素23的像素电极PE朝向第二方向延伸，也就是说，在本公开实施例中，阵列基板可以采用两像两畴的子像素结构设计。
在本公开实施例中，触控电极22可以复用为子像素的公共电极，具体地下文将做详细介绍，在此先不赘述。如图4和图5所示，触控电极22包括多个触控单元221，至少一个触控单元221与至少一条触控线24连接，不同的触控单元221连接不同的触控线24，例如，每个触控单元221与一条触控线24连接，或者，每个触控单元221与多条触控线24连接，具体可以根据实际需要确定，在此不做限制。每个触控单元221可以通过触控线24与触控识别模块连接，例如，每个触控单元221通过触控线24与触控识别模块的一个引脚连接。
在本公开实施例中，显示基板的非显示区NA中包括信号输入侧(图4中显示区AA的下侧)，在信号输入侧，可以设置驱动芯片IC，触控识别模块可以集成在驱动芯片IC中，例如，驱动芯片IC可以为TDDI芯片。多条触控线24可以沿第二方向D2延伸到显示区AA的下侧，从而与触控识别模块连接。在显示阶段，TDDI芯片能够通过触控线24向触控单元221提供用于显示的驱动信号，此时的触控单元221复用为公共电极，像素电极和公共电极之间能够形成相应的电场，以实现显示功能；在触控阶段，TDDI芯片能够提供用于进行触控识别的触控信号，以实现触控功能。
结合参照图2A、图2B和图12，阵列基板可以包括：设置在衬底基板10上的第二金属导电层12，设置在第二金属导电层12远离衬底基板10一侧的第一金属导电层11，设置在第一金属导电层11远离衬底基板10一侧的第二透明导电层14，和设置在第二透明导电层14远离衬底基板10一侧的第一透明导电层13。
例如，阵列基板还可以包括多个绝缘层，例如，设置在衬底基板10与第二金属导电层12之间的缓冲层BFL，设置在第二金属导电层12与第一金属导电层11之间的第一绝缘层IL1，设置在第一金属导电层11与第二透明导电层14之间的第二绝缘层IL2，设置在第二透明导电层14与第一透明导电层13之间的第三绝缘层IL3。
在本公开的实施例中，像素单元包括像素驱动电路，像素驱动电路包括至少一个薄膜晶体管，薄膜晶体管包括有源层、栅极、源极和漏极。例如，薄膜晶体管的栅极位于第二金属导电层12，薄膜晶体管的源极和漏极位于第一金属导电层11。像素电极PE和公共电极CE中的一个可以位于第一透明导电层13，像素电极PE和公共电极CE中的另一个可以位于第二透明导电层14。
参照图6至图11以及图14，阵列基板包括数据信号线DL和扫描信号线GL。数据信号线DL用于给各个像素单元P传输数据信号。扫描信号线GL用于给各个像素单元P传输栅极扫描信号。例如，数据信号线DL可以从周边区NA延伸至显示区AA，扫描信号线GL可以从周边区NA延伸至显示区AA。在一些示例性的实施例中，扫描信号线GL可以主要沿第一方向D1延伸，数据信号线DL可以主要沿第二方向D2延伸。例如，扫描信号线GL可以位于第二金属导电层12中，数据信号线DL可以位于第一金属导电层11中。
参照图14，阵列基板还可以包括公共电极线CL。公共电极线CL用于给公共电极传输公共电压信号。例如，公共电极线CL可以从周边区NA延伸至显示区AA。在一些示例性的实施例中，公共电极线CL可以主要沿第一方向D1延伸。例如，公共电极线CL可以位于第二金属导电层12中。
例如，在第二周边区NA2中，可以设置多个第二过孔VH2，公共电极线CL可以通过多个第二过孔VH2与公共电极总线电连接，例如，公共电极线CL可以通过多个第二过孔VH2与第一公共电极总线3电连接。
阵列基板还可以包括第一公共电极总线3，第一公共电极总线3位于衬底基板10的第二表面102上，第一公共电极总线3在衬底基板10上的正投影至少部分位于第二周边区NA2内，第一公共电极总线3与公共电极CE电连接。第一公共电极总线3用 于给公共电极CE提供第一电压信号。
在本公开的实施例中，第一公共电极总线3可以位于第一金属导电层11中。第一公共电极总线3在第一周边区NA1内的分布密度小于第一公共电极总线3在第二周边区NA2内的分布密度。在一些示例性的实施例中，第一公共电极总线3可以包括位于第一周边区NA1内的第一部分31和位于第二周边区NA2内的第二部分32，第一公共电极总线3位于第一周边区NA1内的第一部分31的分布密度小于第一公共电极总线3位于第二周边区NA2内的第二部分32的分布密度。在另一些示例性的实施例中，第一公共电极总线3不包括位于第一周边区NA1内的部分，第一公共电极总线3可以仅包括位于第二周边区NA2内的部分，在此情况下，第一公共电极总线3在第一周边区NA1内的分布密度基本为0，第一公共电极总线3在第二周边区NA2内的分布密度大于0，同样可以认为：第一公共电极总线3在第一周边区NA1内的分布密度小于第一公共电极总线3在第二周边区NA2内的分布密度。
例如，公共电极线CL可以通过多个第二过孔VH2与第一公共电极总线3的第二部分32电连接。
需要说明的是，此处的表述“分布密度”表示由第一公共电极总线的外边缘围成的区域内单位面积内的第一公共电极总线的部分所占区域的面积。
在本公开实施例提供的阵列基板中，通过将可能未被遮光层2遮挡的周边区中公共电极总线3的分布密度设计得较小，极大地减小了该区域中公共电极总线3的反射面积，从而能够有效改善金属亮边问题。
参照图6至图10D，第一公共电极总线3位于第二周边区NA2内的第二部分32包括块状金属部。第一公共电极总线3位于第一周边区NA1内的第一部分31包括条状金属部312。具体地，第一公共电极总线3位于第一周边区NA1内的第一部分31包括多个条状金属部312和多个条状狭缝311，多个条状金属部312和多个条状狭缝311沿衬底基板10的边缘指向显示区AA的方向交替排列。
例如，第二部分32为块状金属部。在本文中，表述“块状金属部”可以表示连续的一整块金属，中间不具有镂空结构。
在本公开的实施例中，多个条状狭缝在其延伸方向上的长度与该条状狭缝在垂直于其延伸方向的方向上的宽度之比在10以上。多个条状金属部在其延伸方向上的长度与该条状金属部在垂直于其延伸方向的方向上的宽度之比在10以上。即，在第一周边区NA1中，第一公共电极总线3的狭缝或金属部具有较大的长宽比，从而呈现条状结 构。
在本公开的实施例中，在第一公共电极总线3位于第一周边区NA1内的部分中形成多个条状狭缝，通过这样的方式，可以避免在第一周边区NA1中形成大块金属，能够有效改善金属亮边问题；同时，无需在第一公共电极总线3中形成孔洞等面积较大的缺材料部分，从而可以避免第一公共电极总线3的总电阻过大，另外，在后续涂覆PI工艺时，可以避免PI聚集在条状狭缝周围，从而能够避免由于PI聚集而导致的局部显示偏黑的现象。
在本公开的实施例提供的阵列基板中，衬底基板10可以包括第一侧、第二侧、第三侧和第四侧，第一侧和第二侧相对设置，第三侧和第四侧相对设置。例如，扫描信号线GL从第一侧朝向第二侧延伸，数据信号线DL从第三侧朝向第四侧延伸。例如，第一侧和第二侧可以分别为衬底基板10的左侧和右侧，第三侧和第四侧可以分别为衬底基板10的上侧和下侧。
在阵列基板的第一侧和第二侧，多个条状金属部312和多个条状狭缝311沿左右方向交替排列。在阵列基板的第三侧和第四侧，多个条状金属部312和多个条状狭缝311沿上下方向交替排列。
条状狭缝311包括沿第一方向的第一宽度W1，条状金属部312包括沿第一方向的第二宽度W2，第一方向基本垂直于条状狭缝或条状金属部的延伸方向。例如，在阵列基板的第一侧和第二侧，第一方向为左右方向；在阵列基板的第三侧和第四侧，第一方向为上下方向。
在本公开的实施例中，第一宽度W1除以第一宽度W1和第二宽度W2之和的值在0.5以上。例如，第一宽度W1除以第一宽度W1和第二宽度W2之和的值在0.52以上，在0.52～0.9之间。
发明人经研究发现，在本公开的实施例中，只要保证条状狭缝的镂空比(即第一宽度W1除以第一宽度W1和第二宽度W2之和的值)在0.5以上，在视觉上可以觉察不到金属反光现象。
需要说明的是，对于条状狭缝的延伸方向、倾斜角度等设计参数，本公开的实施例不做特别的限制。
参照图11，在本公开的实施例中，第一公共电极总线3靠近显示区AA的边界33在衬底基板10上的正投影位于第一周边区NA1和第二周边区NA2的交界处。
第一公共电极总线3靠近显示区AA的边界33在衬底基板10上的正投影位于遮 光层2在衬底基板10上的正投影内。
在该实施例中，在第一周边区NA1中基本不布置第一公共电极总线，也就是说，通过将可能未被遮光层2遮挡的周边区中不布置公共电极总线3，将该区域中公共电极总线3的反射面积减小至基本为0，从而能够有效改善金属亮边问题。
参照图13和图15，在本公开的实施例中，在第一侧和第二侧中至少一个的第一周边区NA1内，设置有至少两列虚拟像素单元DPX，虚拟像素单元DPX可以是虚拟子像素单元，例如是RGB三个子像素中的一个。
例如，参照图15，在本公开的实施例中，在第三侧和第四侧中至少一个的第一周边区NA1内，设置有至少一行虚拟像素单元DPX。
参照图14，所述阵列基板上可以设置像素驱动电路，所述像素驱动电路可以包括晶体管。例如，对于像素单元P而言，图14示意性图示出了一个晶体管的源极TS和漏极TD，该晶体管的漏极TD可以通过第一过孔VH1与像素单元电连接，例如，与一个子像素的像素电极电连接。对于虚拟像素单元DPX而言，在与第一过孔VH1对应的位置P5处，并没有形成用于电连接晶体管的漏极TD与像素单元的过孔，也就是说，对于虚拟像素单元DPX而言，其像素驱动电路没有与像素电极电连接。
结合参照图6至图13，阵列基板还可以包括第二公共电极总线4，第二公共电极总线4位于衬底基板的第二表面102上，第二公共电极总线4在衬底基板上的正投影位于第一周边区NA1和第二周边区NA2内，第二公共电极总线4与第一公共电极总线3电连接。例如，第二公共电极总线4位于第一透明导电层13中。
在本公开的实施例中，第二公共电极总线4包括块状导电部。例如，第二公共电极总线4可以采用氧化铟锡等透明导电材料制作，因此，具有块状结构的第二公共电极总线4可以直接透射光线而不会反射光线，也就不会导致亮边问题。另外，第二公共电极总线4和第一公共电极总线3电连接，用于并行地传输第一电压信号，可以有效地降低公共电极总线上的总电阻，从而降低IR drop的影响。
示例性地，在第一侧和第二侧的至少一个中，第一公共电极总线3位于第一周边区NA1内的第一部分31包括多个第一条状金属部3121和多个第二条状金属部3122，多个第一条状金属部3121沿第二方向D2延伸，多个第二条状金属部3122沿第三方向D3延伸，第二方向D2和第三方向D3交叉。例如，第一方向D1和第三方向D3交叉。多个第一条状金属部3121和多个第二条状金属部3122构成网格状，网格状内部具有多个镂空狭缝。通过这样的方式，可以避免在第一周边区NA1中形成大块金属， 能够有效改善金属亮边问题；同时，无需在第一公共电极总线3中形成面积较大的缺材料部分，从而可以有效地避免第一公共电极总线3的总电阻过大。进一步地，第三方向D3和第一方向D1交叉，可以使得狭缝沿第一方向非规整排列，避免对光线的透射和/或反射造成的摩尔纹等问题。
参照图6、图7和图10D，第二公共电极总线4包括至少一个第二开孔41，至少一个第二开孔41位于第一周边区NA1中，多个第一条状金属部3121和多个第二条状金属部3122之间的至少一个相交部分在衬底基板上的正投影与至少一个第二开孔41在衬底基板上的正投影至少部分交叠。
在第一侧和第二侧的至少一个中，扫描信号线GL位于周边区中的部分包括第一扫描信号子部GL1和第二扫描信号子部GL2，第一扫描信号子部GL1沿第一方向D1延伸，第二扫描信号子部GL2沿第二方向D2延伸，第一方向D1和第二方向D2交叉。
在本公开的实施例中，第二扫描信号子部GL2和数据信号线DL的延伸方向基本平行。通过这样的设计，可以使得第二扫描信号子部GL2与相邻的位于第一金属导电层11中的公共电极总线不交叠，从而可以尽量减小位于第二金属导电层12中的扫描信号线GL与位于第一金属导电层11中的公共电极总线的交叠面积，这样，可以减小产生的寄生电容，减小扫描信号线和公共电极总线上的负载。
例如，第一扫描信号子部GL1在衬底基板上的正投影与至少一个第二开孔41在衬底基板上的正投影至少部分交叠。在该实施例中，在第一透明导电层13中设置至少一个第二开孔41，可以减小位于第一透明导电层13的第二公共电极总线4与下方的第一扫描信号子部GL1的交叠面积，这样，可以减小产生的寄生电容，减小扫描信号线和公共电极总线上的负载。
再例如，第一条状金属部3121、第二条状金属部3122和第一扫描信号子部GL1三者之间的至少一个相交部分在衬底基板上的正投影与至少一个第二开孔41在衬底基板上的正投影至少部分交叠。在该实施例中，位于第一透明导电层13中的至少一个第二开孔41暴露下方的第一公共电极总线和扫描信号线，可以减小三者之间的交叠面积，这样，可以减小产生的寄生电容，减小扫描信号线和公共电极总线上的负载。
例如，第一公共电极总线3位于第二周边区NA2内的第二部分32包括至少一个第一开孔321，第一公共电极总线的至少一个第一开孔321在衬底基板上的正投影与第一扫描信号子部GL1在衬底基板上的正投影至少部分交叠。在该实施例中，在第一金属导电层11中设置至少一个第一开孔321，可以减小位于第一金属导电层11的第 一公共电极总线3与下方的第一扫描信号子部GL1的交叠面积，这样，可以减小产生的寄生电容，减小扫描信号线和公共电极总线上的负载。
例如，第一透明导电层13还可以包括至少一个第三开孔42，第二扫描信号子部GL2在衬底基板上的正投影与至少一个第三开孔42在衬底基板上的正投影至少部分交叠。在该实施例中，在第一透明导电层13中设置至少一个第三开孔42，可以减小位于第一透明导电层13的第二公共电极总线4与下方的第二扫描信号子部GL2的交叠面积，这样，可以减小产生的寄生电容，减小扫描信号线和公共电极总线上的负载。
例如，第一透明导电层13还可以包括至少一个第四开孔43，第四开孔43的位置可以与第一开孔321的位置对应，即，第四开孔43在衬底基板上的正投影可以与第一开孔321在衬底基板上的正投影至少部分交叠，例如，第四开孔43在衬底基板上的正投影可以与第一开孔321在衬底基板上的正投影基本重合。在该实施例中，在第一透明导电层13中设置至少一个第四开孔43，可以减小位于第一透明导电层13的第二公共电极总线4与下方的第一扫描信号子部GL1的交叠面积，这样，可以减小产生的寄生电容，减小扫描信号线和公共电极总线上的负载。
本公开的实施例还提供一种显示装置，该显示装置包括上述的阵列基板或显示面板。例如，显示装置的示例包括平板个人计算机(PC)、智能手机、个人数字助理(PDA)、便携式多媒体播放器、游戏机或腕表式电子装置等。然而，本公开的实施例并不意图限制显示装置的类型。在一些示例性实施例中，显示装置不仅可用于诸如电视机(TV)或外部广告牌等大型电子装置中，而且可用于诸如PC、笔记本式计算机、汽车导航装置或相机等中型或小型电子装置中。
本领域技术人员可以理解，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合或结合，即使这样的组合或结合没有明确记载于本公开中。特别地，在不脱离本公开精神和教导的情况下，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本公开的范围。以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。本公开的范围由所附权利要求及其等同物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (25)

  1. 一种阵列基板，其特征在于，包括：
    衬底基板，所述衬底基板包括相反设置的第一表面和第二表面，所述衬底基板包括显示区和环绕所述显示区的周边区，所述周边区包括第一周边区和第二周边区，所述第一周边区环绕所述显示区，所述第二周边区环绕所述第一周边区；
    多个像素单元，所述多个像素单元位于所述衬底基板的第二表面上，所述多个像素单元在所述衬底基板上的正投影位于所述显示区内，且呈阵列分布，至少一部分所述像素单元包括公共电极；
    遮光层，所述遮光层位于所述衬底基板的第一表面上，所述遮光层在所述衬底基板上的正投影位于所述周边区内，所述遮光层的至少一部分在所述衬底基板上的正投影位于所述第二周边区内；以及
    第一公共电极总线，所述第一公共电极总线位于所述衬底基板的第二表面上，所述第一公共电极总线在所述衬底基板上的正投影至少部分位于所述第二周边区内，所述第一公共电极总线与所述公共电极电连接，
    其中，所述第一公共电极总线的材料包括金属材料，所述第一公共电极总线在所述第一周边区内的分布密度小于所述第一公共电极总线在所述第二周边区内的分布密度。
  2. 根据权利要求1所述的阵列基板，其中，所述第一公共电极总线包括位于所述第一周边区内的第一部分和位于所述第二周边区内的第二部分，所述第二部分包括块状金属部；以及
    所述第一部分包括条状金属部。
  3. 根据权利要求2所述的阵列基板，其中，所述第一公共电极总线位于所述第一周边区内的第一部分包括多个条状金属部和至少一个条状狭缝，所述多个条状金属部和所述至少一个条状狭缝沿所述衬底基板的边缘指向所述显示区的方向交替排列。
  4. 根据权利要求3所述的阵列基板，其中，所述条状狭缝包括沿第一方向的第一宽度，所述条状金属部包括沿第一方向的第二宽度，所述第一方向基本垂直于所述条 状狭缝或所述条状金属部的延伸方向；以及
    所述第一宽度除以所述第一宽度和所述第二宽度之和的值在0.5以上。
  5. 根据权利要求1所述的阵列基板，其中，所述第一公共电极总线靠近所述显示区的边界在所述衬底基板上的正投影位于所述第一周边区和所述第二周边区的交界处。
  6. 根据权利要求5所述的阵列基板，其中，所述第一公共电极总线靠近所述显示区的边界在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影内。
  7. 根据权利要求1、5或6所述的阵列基板，其中，所述衬底基板包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧相对设置，所述第三侧和所述第四侧相对设置；
    所述阵列基板还包括设置在所述衬底基板的第二表面上的数据信号线和扫描信号线，所述扫描信号线从所述第一侧朝向所述第二侧延伸，所述数据信号线从所述第三侧朝向所述第四侧延伸；
    在所述第一侧和所述第二侧中至少一个的第一周边区内，设置有至少两列虚拟像素单元。
  8. 根据权利要求1、5或6所述的阵列基板，其中，所述衬底基板包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧相对设置，所述第三侧和所述第四侧相对设置；
    所述阵列基板还包括设置在所述衬底基板的第二表面上的数据信号线和扫描信号线，所述扫描信号线从所述第一侧朝向所述第二侧延伸，所述数据信号线从所述第三侧朝向所述第四侧延伸；
    在所述第一侧和所述第二侧中至少一个的第一周边区内，在所述第一部分和所述显示区之间至少设置有一列虚拟像素单元。
  9. 根据权利要求7所述的阵列基板，其中，在所述第三侧和所述第四侧中至少一个的第一周边区内，设置有至少一行虚拟像素单元。
  10. 根据权利要求1-9中任一项所述的阵列基板，其中，所述阵列基板还包括第二公共电极总线，所述第二公共电极总线位于所述衬底基板的第二表面上，所述第二公共电极总线在所述衬底基板上的正投影位于所述第一周边区和所述第二周边区内，所述第二公共电极总线与所述第一公共电极总线电连接。
  11. 根据权利要求10所述的阵列基板，其中，所述阵列基板包括设置在所述衬底基板的第二表面上的第一金属导电层和第一透明导电层，所述第一公共电极总线位于所述第一金属导电层中，所述第二公共电极总线位于所述第一透明导电层中。
  12. 根据权利要求7所述的阵列基板，其中，在所述第一侧和所述第二侧的至少一个中，所述第一公共电极总线位于所述第一周边区内的第一部分包括多个第一条状金属部和多个第二条状金属部，所述多个第一条状金属部沿第二方向延伸，所述多个第二条状金属部沿第三方向延伸，所述第二方向和所述第三方向交叉。
  13. 根据权利要求12所述的阵列基板，其中，所述第一方向和所述第三方向交叉。
  14. 根据权利要求10所述的阵列基板，其中，在所述第一侧和所述第二侧的至少一个中，所述第一公共电极总线位于所述第一周边区内的第一部分包括多个第一条状金属部和多个第二条状金属部，所述多个第一条状金属部沿第二方向延伸，所述多个第二条状金属部沿第三方向延伸，所述第二方向和所述第三方向交叉。
  15. 根据权利要求14所述的阵列基板，其中，所述第二公共电极总线包括至少一个第二开孔，所述至少一个第二开孔位于所述第一周边区中，所述多个第一条状金属部和所述多个第二条状金属部之间的至少一个相交部分在所述衬底基板上的正投影与所述至少一个第二开孔在所述衬底基板上的正投影至少部分交叠。
  16. 根据权利要求1、5或6所述的阵列基板，其中，所述衬底基板包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧相对设置，所述第三侧和所述第四侧相对设置；
    所述阵列基板还包括设置在所述衬底基板的第二表面上的数据信号线和扫描信号线，所述扫描信号线从所述第一侧朝向所述第二侧延伸，所述数据信号线从所述第三侧朝向所述第四侧延伸；
    在所述第一侧和所述第二侧中至少一个的第一周边区内，在所述第一部分和所述显示区之间至少设置有一列虚拟像素单元。
  17. 根据权利要求16所述的阵列基板，其中，所述阵列基板还包括第二公共电极总线，所述第二公共电极总线位于所述衬底基板的第二表面上，所述第二公共电极总线在所述衬底基板上的正投影位于所述第一周边区和所述第二周边区内，所述第二公共电极总线与所述第一公共电极总线电连接。
  18. 根据权利要求17所述的阵列基板，其中，在所述第一侧和所述第二侧的至少一个中，所述第一公共电极总线位于所述第一周边区内的第一部分包括多个第一条状金属部和多个第二条状金属部，所述多个第一条状金属部沿第二方向延伸，所述多个第二条状金属部沿第三方向延伸，所述第二方向和所述第三方向交叉。
  19. 根据权利要求18所述的阵列基板，其中，所述第二公共电极总线包括至少一个第二开孔，所述至少一个第二开孔位于所述第一周边区中，所述多个第一条状金属部和所述多个第二条状金属部之间的至少一个相交部分在所述衬底基板上的正投影与所述至少一个第二开孔在所述衬底基板上的正投影至少部分交叠。
  20. 根据权利要求19所述的阵列基板，其中，在所述第一侧和所述第二侧的至少一个中，所述扫描信号线位于所述周边区中的部分包括第一扫描信号子部和第二扫描信号子部，所述第一扫描信号子部沿第一方向延伸，所述第二扫描信号子部沿第二方向延伸，所述第一方向和所述第二方向交叉；以及
    所述第二扫描信号子部和所述数据信号线的延伸方向基本平行。
  21. 根据权利要求20所述的阵列基板，其中，所述第一扫描信号子部在所述衬底基板上的正投影与所述至少一个第二开孔在所述衬底基板上的正投影至少部分交叠；和/或，
    所述第一条状金属部、所述第二条状金属部和所述第一扫描信号子部三者之间的至少一个相交部分在所述衬底基板上的正投影与所述至少一个第二开孔在所述衬底基板上的正投影至少部分交叠。
  22. 根据权利要求21所述的阵列基板，其中，所述第二部分包括至少一个第一开孔，所述至少一个第一开孔在所述衬底基板上的正投影与所述第一扫描信号子部在所述衬底基板上的正投影至少部分交叠。
  23. 根据权利要求3-4中任一项所述的阵列基板，其中，所述至少一个条状狭缝在其延伸方向上的长度与该条状狭缝在垂直于其延伸方向的方向上的宽度之比在10以上。
  24. 根据权利要求11所述的阵列基板，其中，所述阵列基板还包括设置在所述衬底基板的第二表面上的数据信号线和扫描信号线，所述阵列基板还包括：设置在所述衬底基板上的第二金属导电层；和设置在所述衬底基板上的第二透明导电层；
    所述数据信号线位于所述第一金属导电层，所述扫描信号线位于所述第二金属导电层；以及
    至少一部分所述像素单元还包括像素电极，所述像素电极位于所述第一透明导电层，所述公共电极位于所述第二透明导电层。
  25. 一种显示装置，其特征在于，包括：
    如权利要求1-24中任一项所述的阵列基板；
    与所述阵列基板相对设置的对置基板；以及
    位于所述阵列基板与所述对置基板之间的液晶层，
    其中，所述显示装置的出光面为所述阵列基板中所述衬底基板的第一表面。
PCT/CN2022/134938 2022-11-29 2022-11-29 阵列基板和显示装置 WO2024113147A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130117103A (ko) * 2012-04-17 2013-10-25 엘지디스플레이 주식회사 내로우 베젤 타입 표시장치
CN106684100A (zh) * 2017-01-19 2017-05-17 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107238965A (zh) * 2017-06-22 2017-10-10 南京中电熊猫平板显示科技有限公司 一种显示面板及其制作方法
CN110794610A (zh) * 2018-08-02 2020-02-14 京东方科技集团股份有限公司 一种显示组件、显示装置
CN113192426A (zh) * 2021-04-27 2021-07-30 Oppo广东移动通信有限公司 显示面板、显示模组及电子设备
CN113467144A (zh) * 2021-06-29 2021-10-01 福州京东方光电科技有限公司 显示基板、显示面板及显示装置
CN216956909U (zh) * 2022-02-10 2022-07-12 昆山龙腾光电股份有限公司 一种显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130117103A (ko) * 2012-04-17 2013-10-25 엘지디스플레이 주식회사 내로우 베젤 타입 표시장치
CN106684100A (zh) * 2017-01-19 2017-05-17 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107238965A (zh) * 2017-06-22 2017-10-10 南京中电熊猫平板显示科技有限公司 一种显示面板及其制作方法
CN110794610A (zh) * 2018-08-02 2020-02-14 京东方科技集团股份有限公司 一种显示组件、显示装置
CN113192426A (zh) * 2021-04-27 2021-07-30 Oppo广东移动通信有限公司 显示面板、显示模组及电子设备
CN113467144A (zh) * 2021-06-29 2021-10-01 福州京东方光电科技有限公司 显示基板、显示面板及显示装置
CN216956909U (zh) * 2022-02-10 2022-07-12 昆山龙腾光电股份有限公司 一种显示面板及显示装置

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