WO2024092497A1 - 阵列基板、触控显示面板、显示装置和车载显示屏 - Google Patents

阵列基板、触控显示面板、显示装置和车载显示屏 Download PDF

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Publication number
WO2024092497A1
WO2024092497A1 PCT/CN2022/128932 CN2022128932W WO2024092497A1 WO 2024092497 A1 WO2024092497 A1 WO 2024092497A1 CN 2022128932 W CN2022128932 W CN 2022128932W WO 2024092497 A1 WO2024092497 A1 WO 2024092497A1
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Prior art keywords
sub
data signal
leads
lead
area
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PCT/CN2022/128932
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English (en)
French (fr)
Inventor
张亚东
李挺
臧鹏程
吴博
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/128932 priority Critical patent/WO2024092497A1/zh
Publication of WO2024092497A1 publication Critical patent/WO2024092497A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a touch display panel, a display device and a vehicle-mounted display screen.
  • Liquid crystal display screens have been widely used in consumer electronic products such as mobile phones, laptops and personal computers.
  • Liquid crystal display screens generally include three parts: active matrix array substrate, color filter substrate and liquid crystal layer.
  • the active matrix array substrate and the color filter substrate are assembled opposite to each other, and the liquid crystal layer is located between the active matrix array substrate and the color filter substrate.
  • the active elements in the active matrix array substrate can adjust the direction of the liquid crystal molecules in the liquid crystal layer, that is, the intensity of the light beam passing through the liquid crystal layer can be adjusted to display the image.
  • an array substrate comprising:
  • a base substrate comprising a display area and a peripheral area at least located on at least one side of the display area;
  • a plurality of pixel units wherein the plurality of pixel units are arranged in the display area, and the pixel units include a pixel driving circuit;
  • a plurality of touch electrodes wherein the plurality of touch electrodes are arranged in the display area;
  • a plurality of data signal lines at least partly located in the display area, the plurality of data signal lines being electrically connected to the pixel driving circuits of the plurality of pixel units, respectively, for transmitting data signals to the plurality of pixel units, respectively;
  • a plurality of touch signal lines at least partly located in the display area, the plurality of touch signal lines being electrically connected to the plurality of touch electrodes respectively and used for transmitting touch signals to the plurality of touch electrodes respectively;
  • the driving chip located in the peripheral area, the driving chip being used to at least provide the data signal and the touch signal,
  • the peripheral area includes a fan-out area, the fan-out area is located between the display area and the driving chip, the fan-out area includes a first sub-area and a second sub-area, and the first sub-area is closer to the display area than the second sub-area;
  • the array substrate further comprises a plurality of data signal leads and a plurality of touch signal leads located in the fan-out region, one end of the plurality of data signal leads being electrically connected to the driving chip, and the other ends of the plurality of data signal leads being electrically connected to the plurality of data signal lines respectively, one end of the plurality of touch signal leads being electrically connected to the driving chip, and the other ends of the plurality of touch signal leads being electrically connected to the plurality of touch signal lines respectively;
  • At least one of the data signal leads includes a first data signal sub-lead located in the first sub-area and a second data signal sub-lead located in the second sub-area
  • at least one of the touch signal leads includes a first touch signal sub-lead located in the first sub-area and a second touch signal sub-lead located in the second sub-area;
  • the plurality of data signal lines and the plurality of touch signal lines are located in the same conductive layer;
  • a portion of the second data signal sub-leads among the plurality of second data signal sub-leads and another portion of the second data signal sub-leads among the plurality of second data signal sub-leads are located in a different conductive layer.
  • the fan-out region further includes a third sub-region, and the third sub-region is closer to the driving chip than the second sub-region;
  • At least one of the data signal leads further includes a third data signal sub-lead located in the third sub-area, and at least one of the touch signal leads further includes a third touch signal sub-lead located in the third sub-area;
  • the driving chip comprises a plurality of contact pins, one end of each of the plurality of third data signal sub-leads is electrically connected to a portion of the contact pins of the driving chip, and one end of each of the plurality of third touch signal sub-leads is electrically connected to another portion of the contact pins of the driving chip;
  • the arrangement order of the third data signal sub-leads and the third touch signal sub-leads corresponds to the arrangement order of the plurality of contact pins of the driving chip.
  • a portion of the plurality of second data signal sub-leads are located in the first conductive layer, and another portion of the plurality of second data signal sub-leads are located in the second conductive layer;
  • the plurality of second touch signal sub-lines are all located in the first conductive layer.
  • At least one sub-lead in the combination of the plurality of second data signal sub-leads and the plurality of second touch signal sub-leads and the sub-leads adjacent thereto are located in different conductive layers.
  • At least one second data signal sub-lead and at least one data signal line electrically connected to each other are located in different conductive layers, and the second touch signal sub-lead and touch signal line electrically connected to each other are both located in different conductive layers.
  • the first touch signal sub-lead and the touch signal line electrically connected to each other are located in different conductive layers, and the first touch signal sub-lead and the second touch signal sub-lead electrically connected to each other are located in the same conductive layer.
  • the first touch signal sub-lead, the second touch signal sub-lead and the third touch signal sub-lead that are electrically connected to each other are all located in the same conductive layer.
  • the plurality of data signal lines include at least one first-category data signal line
  • the data signal line, the first data signal sub-lead and the second data signal sub-lead that are electrically connected to each other are located in the same conductive layer.
  • the plurality of data signal lines include at least one second-type data signal line
  • the electrically connected data signal line and the first data signal sub-lead are located in the same conductive layer, and the electrically connected first data signal sub-lead and the second data signal sub-lead are located in different conductive layers.
  • the electrically connected data signal line, the first data signal sub-lead, the second data signal sub-lead and the third data signal sub-lead are located in the same conductive layer.
  • the data signal line and the first data signal sub-lead electrically connected to each other are located in the same conductive layer, the first data signal sub-lead and the second data signal sub-lead electrically connected to each other are located in different conductive layers, the first data signal sub-lead and the third data signal sub-lead electrically connected to each other are located in different conductive layers, and the second data signal sub-lead and the third data signal sub-lead electrically connected to each other are located in the same conductive layer.
  • the touch signal line is electrically connected to the first touch signal sub-lead through a first via.
  • the first data signal sub-lead is electrically connected to the second data signal sub-lead through a second via.
  • the first via hole is located on a side of the first sub-region close to the display region, and the second via hole is located on a side of the first sub-region close to the second sub-region.
  • an orthographic projection of each of at least one first touch signal sub-lead on the substrate substrate does not intersect with an orthographic projection of any first data signal sub-lead on the substrate substrate;
  • an orthographic projection of each of at least one first touch signal sub-lead on the base substrate intersects with an orthographic projection of at least two first data signal sub-leads on the base substrate.
  • a plurality of groups of first touch signal sub-leads are periodically arranged;
  • a group of first touch signal sub-leads includes k first touch signal sub-leads, where k is a positive integer greater than or equal to 3;
  • the orthographic projection of the 1st first touch signal sub-lead on the substrate substrate does not intersect with the orthographic projection of any first data signal sub-lead on the substrate substrate
  • the orthographic projection of each of the 2nd to k-1th first touch signal sub-leads on the substrate substrate respectively intersects with the orthographic projections of two first data signal sub-leads on the substrate substrate
  • the orthographic projection of the kth first touch signal sub-lead on the substrate substrate respectively intersects with the orthographic projections of four first data signal sub-leads on the substrate substrate.
  • At least a portion of an orthographic projection of each of the plurality of first touch signal sub-leads on the substrate is located between orthographic projections of two first data signal sub-leads electrically connected to the first type of data signal lines on the substrate;
  • the orthographic projection of the first data signal sub-lead electrically connected to the second-type data signal line on the substrate is located between the orthographic projections of two first data signal sub-leads electrically connected to the first-type data signal line on the substrate.
  • any two of the plurality of second data signal sub-leads and the plurality of second touch signal sub-leads are parallel to each other.
  • an orthographic projection of the leads in the first conductive layer on the base substrate and an orthographic projection of the leads in the second conductive layer on the base substrate are arranged alternately;
  • the orthographic projection of the lead located in the first conductive layer on the base substrate and the orthographic projection of at least one lead adjacent to the lead on the base substrate at least partially overlap.
  • the plurality of contact pins of the driving chip include a first contact pin for providing a data signal and a second contact pin for providing a touch signal;
  • the plurality of contact pins are periodically arranged in the order of M first contact pins and N second contact pins, wherein M is greater than or equal to 2, and N is equal to 1 or 2;
  • the third data signal sub-leads and the third touch signal sub-leads are periodically arranged in the order of m third data signal sub-leads and n third touch signal sub-leads, where m is equal to M, and n is equal to 1.
  • the pixel driving circuit includes at least one thin film transistor disposed on the base substrate, the thin film transistor includes an active layer, a gate, a source electrode and a drain electrode, and the array substrate includes a pixel electrode and a common electrode;
  • the array substrate comprises:
  • a first conductive layer is provided on the base substrate, wherein the gate is located in the first conductive layer;
  • An active layer disposed on a side of the first conductive layer away from the substrate;
  • a third conductive layer is disposed on a side of the active layer away from the base substrate, and the pixel electrode is located on the third conductive layer;
  • a second conductive layer is arranged on a side of the third conductive layer away from the base substrate, wherein the source electrode and the drain electrode are located in the second conductive layer;
  • a fourth conductive layer is disposed on a side of the second conductive layer away from the base substrate, and the common electrode is located on the fourth conductive layer.
  • the multiple data signal lines and the multiple touch signal lines are located in the second conductive layer
  • the multiple touch signal leads are located in the first conductive layer
  • the second data signal sub-leads electrically connected to the first type of data signal lines are located in the second conductive layer
  • the second data signal sub-leads electrically connected to the second type of data signal lines are located in the first conductive layer.
  • a touch display panel comprising the above-mentioned array substrate.
  • a display device comprising the above-mentioned array substrate or the above-mentioned touch display panel.
  • a vehicle-mounted display screen comprising the above-mentioned array substrate or the above-mentioned touch display panel.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • FIG2 is a cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along line AA′ in FIG1 , which schematically shows a cross-sectional structure of the array substrate in a display area.
  • FIG. 3 is a partial enlarged view of a portion II of the array substrate in FIG. 1 according to an embodiment of the present disclosure, which schematically shows a wiring design of a fan-out area.
  • FIG. 4 is a partial enlarged view of a first sub-region of a fan-out region of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a partial enlarged view of a first sub-region of a fan-out region of an array substrate according to some other embodiments of the present disclosure.
  • FIG. 6 is a partial enlarged view of the array substrate at the second sub-region of the fan-out region according to an embodiment of the present disclosure.
  • FIG. 7 is a partial enlarged view of the second sub-region of the fan-out region of the array substrate according to some other embodiments of the present disclosure.
  • FIG. 8 is a partial enlarged view of the array substrate at the third sub-region of the fan-out region according to an embodiment of the present disclosure.
  • FIG. 9 is a partial enlarged view of a driving chip of an array substrate according to an embodiment of the present disclosure.
  • Figures 10A to 10C are cross-sectional views of the array substrate according to an embodiment of the present disclosure taken along line CC' in Figure 6, which schematically illustrate the double-layer wiring design in the array substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • connection may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection.
  • the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense.
  • the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ.
  • the term “and/or” includes any and all combinations of one or more of the listed associated items.
  • first the terms “first”, “second”, etc. may be used herein to describe various parts, components, elements, regions, layers and/or parts, these parts, components, elements, regions, layers and/or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and/or part from another.
  • first part, first member, first element, first region, first layer and/or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and/or second part without departing from the teachings of the present disclosure.
  • spatial relational terms such as “upper”, “lower”, “left”, “right”, etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that the spatial relational terms are intended to cover other different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the figure is turned upside down, elements described as “below” or “beneath” other elements or features will be oriented “above” or “above” other elements or features.
  • the expression “height” or “thickness” refers to the dimension of the surface of each film layer arranged perpendicular to the array substrate, that is, the dimension along the light emitting direction of the array substrate, or the dimension along the normal direction of the display device.
  • patterning process generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc.
  • one-time patterning process means a process of forming patterned layers, components, members, etc. using one mask.
  • the expressions “same layer”, “same layer arrangement” or similar expressions refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process.
  • a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.
  • the expression “electrically connected” may mean that two parts or elements are directly electrically connected, for example, part or element A is in direct contact with part or element B, and electrical signals can be transmitted between the two parts; it may also mean that two parts or elements are electrically connected through a conductive medium such as a conductive wire, for example, part or element A is electrically connected to part or element B through a conductive wire to transmit electrical signals between the two parts or elements; it may also mean that two parts or elements are electrically connected through at least one electronic component, for example, part or element A is electrically connected to part or element B through at least one thin film transistor to transmit electrical signals between the two parts or elements.
  • the embodiments of the present disclosure at least provide an array substrate, a touch display panel, a display device and a vehicle-mounted display screen.
  • the array substrate includes: a base substrate, the base substrate includes a display area and a peripheral area at least located on at least one side of the display area; a plurality of pixel units, the plurality of pixel units are arranged in the display area, and the pixel units include a pixel driving circuit; a plurality of touch electrodes, the plurality of touch electrodes are arranged in the display area; a plurality of data signal lines located in the display area, the plurality of data signal lines are respectively electrically connected to the pixel driving circuits of the plurality of pixel units, and are used to transmit data signals to the plurality of pixel units respectively; a plurality of touch signal lines located in the display area, the plurality of touch signal lines are respectively electrically connected to the plurality of touch electrodes, and are used to transmit touch signals to the plurality of touch electrodes respectively; a driving chip located in the peripheral area, the
  • the data signal leads in the second sub-area are arranged in two layers. In this way, the width of the frame occupied by the data signal leads in the second sub-area can be effectively reduced, thereby being conducive to realizing a display device with a narrow frame.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional view of an array substrate according to an embodiment of the present disclosure taken along line AA' in FIG. 1, which schematically shows the cross-sectional structure of the array substrate in the display area.
  • FIG. 3 is a partial enlarged view of the array substrate at part II in FIG. 1 according to an embodiment of the present disclosure, which schematically shows the wiring design of the fan-out area.
  • FIG. 4 is a partial enlarged view of the array substrate at the first sub-area of the fan-out area according to an embodiment of the present disclosure.
  • FIG. 5 is a partial enlarged view of the array substrate at the first sub-area of the fan-out area according to some other embodiments of the present disclosure.
  • FIG. 6 is a partial enlarged view of the array substrate at the second sub-area of the fan-out area according to an embodiment of the present disclosure.
  • FIG. 7 is a partial enlarged view of the array substrate at the second sub-area of the fan-out area according to some other embodiments of the present disclosure.
  • FIG. 8 is a partial enlarged view of the array substrate at the third sub-area of the fan-out area according to an embodiment of the present disclosure.
  • FIG. 9 is a partial enlarged view of the driver chip of the array substrate according to an embodiment of the present disclosure.
  • FIGS. 10A to 10C are cross-sectional views of an array substrate according to an embodiment of the present disclosure taken along line CC' in FIG6 , which schematically illustrate a double-layer wiring design in an array substrate according to a portion of exemplary embodiments of the present disclosure.
  • FIG11 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the array substrate may include: a base substrate 10, for example, the base substrate 10 may be formed of glass, plastic, polyimide, etc.
  • the base substrate 10 includes a display area AA and a peripheral area (or non-display area) NA located on at least one side of the display area AA.
  • the array substrate may include a plurality of pixel units P (schematically shown in a dotted box in FIG. 1 ) disposed in the display area AA, and the plurality of pixel units P may be arranged in an array on the substrate 10 along directions X and Y.
  • Each pixel unit P may further include a plurality of sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels. In FIG. 1 , one sub-pixel SP is schematically shown.
  • the array substrate includes a signal input side IN1 (the lower side shown in FIG. 1 ).
  • a driver chip IC may be provided on the signal input side IN1, and the driver chip IC may be electrically connected to the pixel unit P located in the display area through a plurality of signal wires, and the pixel driving circuit may be electrically connected to the driver chip IC.
  • signals such as data signals, scanning signals, and touch signals may be transmitted from the signal input side IN1 to the plurality of pixel units P.
  • the peripheral area NA may be located on four sides of the display area AA, that is, it surrounds the display area AA.
  • the pixel units and sub-pixels are schematically shown in a rectangular shape, but this does not constitute a limitation on the shapes of the pixel units and sub-pixels included in the array substrate provided in the embodiments of the present disclosure.
  • the array substrate may be an array substrate applied to a TFT-LCD.
  • the array substrate may be an array substrate of a liquid crystal display panel.
  • the array substrate may include: a pixel electrode 40 disposed on a base substrate 10; an insulating layer PVX disposed on the pixel electrode 40; and a common electrode 50 disposed on the insulating layer PVX.
  • the common electrode 50 is used to cooperate with the pixel electrode 40 to form an electric field that drives the liquid crystal molecules to deflect, thereby realizing the display of a specific gray scale.
  • the pixel electrode 40 , the insulating layer PVX and the common electrode 50 are sequentially arranged on the base substrate 10 in a direction away from the base substrate 10 , that is, the pixel electrode 40 is at the bottom and the common electrode 50 is at the top.
  • the pixel electrode 40 may be a planar electrode, that is, the pixel electrode 40 of one sub-pixel P is a planar electrode.
  • the common electrode 50 may be a comb-shaped electrode with a plurality of slits 502, that is, one common electrode 50 may include a plurality of electrode portions 501 and a plurality of slits 502, and the plurality of electrode portions 501 are spaced apart by the plurality of slits 502.
  • the comb-shaped common electrode 50 and the planar pixel electrode 50 are stacked on the base substrate of the array substrate, and a multi-dimensional electric field is formed by the electric field generated by the edge of the comb-shaped common electrode in the same plane and the electric field generated between the comb-shaped common electrode and the planar pixel electrode, so that all oriented liquid crystal molecules between the comb-shaped common electrodes in the liquid crystal cell and directly above the common electrodes can rotate, thereby realizing the display of various gray levels.
  • the array substrate according to the embodiment of the present disclosure is particularly suitable for ADS (ADvanced Super Dimension Switch) mode, and the embodiment described in this article is also described by taking the ADS mode display panel as an example.
  • ADS Advanced Super Dimension Switch
  • the embodiment of the present disclosure is not limited to this, and it can also be applied to display devices of various other modes, such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode and other modes.
  • each of the pixel units P may include a pixel driving circuit.
  • the pixel driving circuit of each sub-pixel of the array substrate may include at least one thin film transistor located on the base substrate 10.
  • the thin film transistor may include a gate electrode TG, a source electrode TS, and a drain electrode TD, and may also include a gate insulating layer, an active layer, and a passivation layer.
  • the specific structure of the thin film transistor may refer to the structure of the thin film transistor in the related art, and will not be repeated here.
  • the array substrate may include: a first conductive layer 20 arranged on the base substrate 10, the gate TG is located in the first conductive layer 20; an active layer ACT arranged on the side of the first conductive layer 20 away from the base substrate 10; a third conductive layer arranged on the side of the active layer ACT away from the base substrate 10, the pixel electrode 40 is located in the third conductive layer; a second conductive layer 30 arranged on the side of the third conductive layer away from the base substrate, the source TS and the drain TD are located in the second conductive layer 30; and a fourth conductive layer arranged on the side of the second conductive layer 30 away from the base substrate 10, the common electrode 50 is located in the fourth conductive layer.
  • a first insulating layer GI may be disposed between the first conductive layer 20 and the second conductive layer 30, for example, the first insulating layer GI may be a gate insulating layer.
  • a second insulating layer PVX may be disposed between the second conductive layer 30 and the fourth conductive layer, for example, the second insulating layer PVX may be a passivation layer.
  • the array substrate may further include various signal lines arranged on the base substrate 10, wherein the various signal lines include data signal lines, gate scanning signal lines, touch signal lines, first power supply lines, second power supply lines, etc., so as to provide various signals such as data signals, scanning signals, touch signals, first power supply voltages, and second power supply voltages to the pixel driving circuit in each sub-pixel.
  • the gate scanning signal lines GL and the data signal lines DL are schematically shown.
  • the gate scanning signal lines GL and the data signal lines DL may be electrically connected to each pixel unit P.
  • the array substrate according to the embodiment of the present disclosure has a display area AA and a peripheral area NA surrounding the display area AA.
  • the peripheral area NA includes a first frame area NA1, a second frame area NA2, a third frame area NA3 and a fourth frame area NA4.
  • the first frame area NA1, the second frame area NA2, the third frame area NA3 and the fourth frame area NA4 can be respectively regarded as the lower frame, the upper frame, the left frame and the right frame of the array substrate.
  • the array substrate has a display area and a peripheral area.
  • the display area of the array substrate is arranged with luminous pixels and can display images.
  • the display area is surrounded by a peripheral area.
  • the display area is surrounded by a frame area.
  • the frame area is as narrow as possible from the perspective of aesthetics. Therefore, in applications such as full-screen mobile phones, the display area may not be provided with a frame area on the left, right and top. Nevertheless, the array substrate still needs to have at least one frame area for centrally accommodating circuits that are difficult to bend but necessary, and this frame area is usually located below the display area.
  • the driver chip IC may be disposed in the first border area NA1.
  • TDDI technology i.e., touch control and display driver integration technology
  • the touch control chip and the display chip are integrated into a single chip (e.g., the driver chip IC).
  • the driver chip IC includes a plurality of contact pins, and the plurality of contact pins of the driver chip include a first contact pin PIN1 for providing a data signal and a second contact pin PIN2 for providing a touch signal.
  • the leads labeled with Arabic numerals 1, 2, 3, etc. are leads electrically connected to the data signal line, and they are respectively electrically connected to the first contact pin PIN1 for providing the data signal;
  • the leads labeled with English letters A, B, C, etc. are leads electrically connected to the touch signal line, and they are respectively electrically connected to the second contact pin PIN2 for providing the touch signal.
  • the array substrate may include a first touch layer, a second touch layer, and a touch insulating layer disposed on the base substrate 10.
  • the array substrate may include a first touch electrode and a second touch electrode, for example, the first touch electrode may be a touch drive electrode, and the second touch electrode may be a touch sensing electrode.
  • a plurality of first touch electrodes may be arranged along a first direction X, and a plurality of second touch electrodes may be arranged along a second direction intersecting the first direction.
  • the first direction is perpendicular to the second direction.
  • the first direction may be a width direction of the array substrate
  • the second direction may be a length direction of the array substrate.
  • a plurality of first touch electrodes located in the same row may be electrically connected via the second connection portion, and a plurality of second touch electrodes located in the same column may be electrically connected via the first connection portion.
  • first touch electrode and the second touch electrode are in a rhombus shape
  • first connecting portion and the second connecting portion are in a rectangular shape.
  • the embodiments of the present disclosure are not limited thereto, and those skilled in the art should understand that in other embodiments, the shapes of the first touch electrode and the second touch electrode and the shapes of the first connecting portion and the second connecting portion may be other shapes.
  • the orthographic projections of the first connection portion for connecting the first touch electrode and the second connection portion for connecting the second touch electrode on the base substrate at least partially overlap, that is, the first connection portion and the second connection portion have an overlapping area.
  • the first touch electrode and the second touch electrode may be located in the same layer, for example, they may be located in the first touch layer.
  • the first connecting portion may also be located in the first touch layer.
  • the second connecting portion may be located in the second touch layer, that is, the second connecting portion forms a conductive bridge portion.
  • the touch insulating layer is located between the first touch layer and the second touch layer, and covers the first touch electrode and the second touch electrode. At least one pair of first via holes is provided in the touch insulating layer, and the first via holes penetrate the touch insulating layer, so as to expose a part of the first touch electrode, which can be called a bridge area.
  • One via hole in each pair of first via holes is located on one of the two adjacent first touch electrodes, and the other via hole is located on the other of the two adjacent first touch electrodes.
  • a portion of the second connection portion is disposed on a side of the touch insulating layer away from the base substrate, and the remaining portion is located in the first via hole.
  • the orthographic projection of the second connection portion on the base substrate at least partially overlaps with the orthographic projection of at least one pair of first via holes in the touch insulating layer on the base substrate, so that the second connection portion can be electrically connected to the first touch electrode through the first via hole overlapping with the second connection portion, thereby achieving electrical connection between adjacent first touch electrodes.
  • the array substrate includes: a plurality of data signal lines DL, at least a portion of which is located in the display area AA, and the plurality of data signal lines DL are respectively electrically connected to the pixel driving circuits of the plurality of pixel units P, and are used to transmit data signals to the plurality of pixel units P respectively; a plurality of touch signal lines TL, at least a portion of which is located in the display area AA, and the plurality of touch signal lines TL are respectively electrically connected to the plurality of touch electrodes (for example, first touch electrodes), and are used to transmit touch signals to the plurality of touch electrodes respectively.
  • the plurality of touch signal lines DL at least a portion of which is located in the display area AA
  • the plurality of touch signal lines TL are respectively electrically connected to the plurality of touch electrodes (for example, first touch electrodes), and are used to transmit touch signals to the plurality of touch electrodes respectively.
  • the peripheral area includes a fan-out area 80, for example, the fan-out area 80 may be a part of the first frame area NA1.
  • the fan-out area 80 is located between the display area AA and the driver chip IC, and the fan-out area 80 includes a first sub-area 81 and a second sub-area 82, wherein the first sub-area 81 is closer to the display area AA than the second sub-area 82.
  • the fan-out area 80 further includes a third sub-area 83, and the third sub-area 83 is closer to the driver chip IC than the second sub-area 82. That is, the fan-out area 80 may include a first sub-area 81, a second sub-area 82, and a third sub-area 83, and the first sub-area 81, the second sub-area 82, and the third sub-area 83 are arranged in a direction away from the display area AA in sequence.
  • the array substrate also includes a plurality of data signal leads DLL and a plurality of touch signal leads TLL located in the fan-out area 80, one end of the plurality of data signal leads DLL (for example, an end away from the display area AA) is electrically connected to the driver chip IC, the other end of the plurality of data signal leads DLL (for example, an end close to the display area AA) is respectively electrically connected to the plurality of data signal lines DL, one end of the plurality of touch signal leads TLL (for example, an end away from the display area AA) is electrically connected to the driver chip IC, and the other end of the plurality of touch signal leads TLL (for example, an end close to the display area AA) is respectively electrically connected to the plurality of touch signal lines TL.
  • one end of the plurality of data signal leads DLL for example, an end away from the display area AA
  • the other end of the plurality of data signal leads DLL for example, an end close to the display area AA
  • At least one of the data signal lead lines DLL includes a first data signal sub-lead line DLL1 located in the first sub-area 81 and a second data signal sub-lead line DLL2 located in the second sub-area 82
  • at least one of the touch signal lead lines TLL includes a first touch signal sub-lead line TLL1 located in the first sub-area 81 and a second touch signal sub-lead line TLL2 located in the second sub-area 82.
  • At least one of the data signal lead lines DLL further includes a third data signal sub-lead line DLL3 located in the third sub-area 83
  • at least one of the touch signal lead lines TLL further includes a third touch signal sub-lead line TLL3 located in the third sub-area 83 .
  • the plurality of data signal lines DL and the plurality of touch signal lines TL are located in the same conductive layer, for example, they are all located in the second conductive layer 30. That is, in the display area AA, the plurality of data signal lines DL and the plurality of touch signal lines TL are all located in the second conductive layer 30, for example, the plurality of data signal lines DL and the plurality of touch signal lines TL are all extended along the direction Y, and the plurality of data signal lines DL and the plurality of touch signal lines TL located in the same conductive layer 30 are arranged at intervals in the direction X.
  • the plurality of data signal lines DL extending longitudinally can conveniently provide data signals to multiple columns of sub-pixels, respectively
  • the plurality of touch signal lines TL extending longitudinally can conveniently provide touch signals to multiple columns of touch units, respectively.
  • a part of the second data signal sub-leads DLL2 and another part of the second data signal sub-leads DLL2 are located in different conductive layers.
  • a part of the second data signal sub-leads DLL2 are located in the first conductive layer 20, and another part of the second data signal sub-leads DLL2 are located in the second conductive layer 30.
  • the data signal leads located in the second sub-area 82 are arranged in two layers. In this way, the width of the frame occupied by the data signal leads located in the second sub-area 82 can be effectively reduced, which is conducive to realizing a display device with a narrow frame.
  • the plurality of second touch signal sub-lines TLL2 are all located in the same conductive layer, for example, they are all located in the first conductive layer 20 .
  • the second sub-area 82 all the second touch signal sub-lines TLL2 and a part of the second data signal sub-leads DLL2 are located in the first conductive layer 20, and another part of the second data signal sub-leads DLL2 are located in the second conductive layer 30. That is, for the combination of multiple second data signal leads and multiple second touch signal leads in the second sub-area, a part of the signal leads are located in the first conductive layer, and another part of the signal leads are located in the second conductive layer.
  • the signal leads in the second sub-area 82 are arranged in two layers. In this way, the width of the frame occupied by the signal leads in the second sub-area 82 can be effectively reduced, which is conducive to realizing a display device with a narrow frame.
  • each driver chip IC needs to lead out 1920 data signal leads and 640 touch signal leads. It can be seen that in the fan-out area 80, especially in the second sub-area 82, the area occupied by the data signal leads is the area that mainly occupies space.
  • the width of the frame occupied by the signal leads in the second sub-area 82 can be minimized while minimizing the adjustment of the wiring design of the signal leads, thereby facilitating the realization of a display device with a narrow frame.
  • 640 of the 1920 data signal leads may be adjusted to be routed in the first conductive layer 20, and the other 1280 data signal leads may still be routed in the second conductive layer 30.
  • 640 data signal leads and 640 touch signal leads may be arranged in the first conductive layer 20, that is, a total of 1280 signal leads may be arranged in the first conductive layer 20; and 1280 data signal leads may be arranged in the second conductive layer 30.
  • the number of signal leads (for example, a part of which are data signal leads and the other part of which are touch signal leads) arranged in the first conductive layer 20 is substantially equal to the number of signal leads (for example, all of which are data signal leads) arranged in the second conductive layer 30.
  • the width of the frame occupied by the signal leads in the second sub-area 82 can be reduced to the maximum extent while minimizing the adjustment of the wiring design of the signal leads, thereby facilitating the realization of a display device with a narrow frame.
  • any sub-lead in the combination of a plurality of second data signal sub-leads DLL2 and a plurality of second touch signal sub-leads TLL2 and a sub-lead adjacent to it are located in different conductive layers.
  • any sub-lead in the combination of a plurality of second data signal sub-leads DLL2 and a plurality of second touch signal sub-leads TLL2 and a sub-lead adjacent to it are located in different conductive layers.
  • any sub-lead here means that the sub-lead can be the second data signal sub-lead DLL2 or the second touch signal sub-lead TLL2.
  • the signal leads located in the first conductive layer 20 and the signal leads located in the second conductive layer 30 are arranged alternately. 4, 5, 6 and 7, the data leads wired in two layers are alternately arranged as follows: from the left side to the right side of FIG.
  • At least one second data signal sub-lead e.g., a portion of the second data signal sub-lead DLL2 located in the first conductive layer 20
  • at least one data signal line DL that are electrically connected to each other are located in different conductive layers.
  • the second touch signal sub-lead TLL2 and the touch signal line TL that are electrically connected to each other are both located in different conductive layers, for example, the second touch signal sub-lead TLL2 is located in the first conductive layer 20, and the touch signal line TL is located in the second conductive layer 30.
  • the first touch signal sub-lead TTL1 and the touch signal line TL electrically connected to each other are located in different conductive layers, and the first touch signal sub-lead TTL1 and the second touch signal sub-lead TTL2 electrically connected to each other are located in the same conductive layer.
  • the first touch signal sub-lead TTL1 and the second touch signal sub-lead TTL2 are both located in the first conductive layer 20, and the touch signal line TL is located in the second conductive layer 30.
  • first touch signal sub-lead TTL1, the second touch signal sub-lead TTL2 and the third touch signal sub-lead TTL3 electrically connected to each other are all located in the same conductive layer.
  • first touch signal sub-lead TTL1, the second touch signal sub-lead TTL2 and the third touch signal sub-lead TTL3 are all located in the first conductive layer 20.
  • the plurality of data signal lines DL may include at least one first-category data signal line and at least one second-category data signal line.
  • the data signal lead electrically connected thereto will be arranged in the same conductive layer as the data signal line;
  • the second-category data signal line a portion of the data signal lead electrically connected thereto will be arranged in a conductive layer on a different layer from the data signal line.
  • the data signal line DL, the first data signal sub-lead DLL1, and the second data signal sub-lead DLL2 that are electrically connected to each other are located in the same conductive layer.
  • the 1st, 3rd, 4th, 5th, and 7th data signal lines are all first-category data signal lines.
  • the data signal line DL and the first data signal sub-lead DLL1 electrically connected to each other are located in the same conductive layer, and the first data signal sub-lead DLL1 and the second data signal sub-lead DLL2 electrically connected to each other are located in different conductive layers.
  • the data signal line DL and the first data signal sub-lead DLL1 electrically connected to each other are located in the second conductive layer 30, and the second data signal sub-lead DLL2 is located in the first conductive layer 20.
  • the 2nd and 6th data signal lines are both second-category data signal lines.
  • first-type data signal line for at least one first-type data signal line, the data signal line DL, the first data signal sub-lead DLL1 , the second data signal sub-lead DLL2 and the third data signal sub-lead DLL3 that are electrically connected to each other are located in the same conductive layer, for example, are all located in the second conductive layer 30 .
  • the data signal line DL and the first data signal sub-lead DLL1 electrically connected to each other are located in the same conductive layer
  • the first data signal sub-lead DLL1 and the second data signal sub-lead DLL2 electrically connected to each other are located in different conductive layers
  • the first data signal sub-lead DLL1 and the third data signal sub-lead DLL3 electrically connected to each other are located in different conductive layers
  • the second data signal sub-lead DLL2 and the third data signal sub-lead DLL3 electrically connected to each other are located in the same conductive layer.
  • the data signal line DL and the first data signal sub-lead DLL1 are located in the second conductive layer 30, and the second data signal sub-lead DLL2 and the third data signal sub-lead DLL3 are located in the first conductive layer 20.
  • the touch signal line TL is electrically connected to the first touch signal sub-lead TLL1 through the first via hole VH1.
  • the first data signal sub-lead DLL1 and the second data signal sub-lead DLL2 which are electrically connected to each other and are located in different conductive layers, the first data signal sub-lead DLL1 is electrically connected to the second data signal sub-lead DLL1 through the second via hole VH2.
  • the boundary between the first sub-area 81 and the second sub-area 82 passes through the first via hole VH1 of the touch line. Accordingly, the data signal line DL and the touch signal line TL both extend from the display area AA to the peripheral area NA.
  • the first via hole VH1 is located on a side of the first sub-area 81 close to the display area AA
  • the second via hole VH2 is located on a side of the first sub-area 81 close to the second sub-area 82. That is, in the embodiment of the present disclosure, the touch signal line and the touch signal lead are switched at a position on a side of the first sub-area 81 close to the display area AA, and part of the data signal line and the data signal lead are switched at a position on a side of the first sub-area 81 away from the display area AA.
  • the array substrate may further include a first power line VCOM extending along a direction X, for example, the first power line VCOM may be a line for transmitting a voltage signal to a common electrode.
  • the first via hole VH1 may be located on a side of the first power line VCOM away from the display area AA, and the first via hole VH1 is close to the first power line VCOM.
  • the first sub-area 81 at least most of the first data signal sub-leads are located in the second conductive layer 30, so that the first touch signal sub-leads TLL1 located in the first conductive layer 20 can be wound and wired.
  • part of the first touch signal sub-leads TLL1 (the 2nd to 8th first touch signal sub-leads, counting from the left) can cross multiple first data signal sub-leads.
  • the signal leads located in the first conductive layer 20 and the signal leads located in the second conductive layer 30 can be arranged alternately.
  • the orthographic projection of each of at least one first touch signal sub-lead TLL1 (for example, in the embodiment shown in FIG. 4 , counting from the left, the 1st and 9th first touch signal sub-leads) on the base substrate 10 does not intersect with the orthographic projection of any first data signal sub-lead DLL1 on the base substrate 10.
  • the orthographic projection of each of at least one first touch signal sub-lead (for example, in the embodiment shown in FIG. 4 , counting from the left, the 2nd to 8th first touch signal sub-leads) on the base substrate 10 intersects with the orthographic projections of at least two first data signal sub-leads DLL1 on the base substrate 10.
  • a plurality of groups of first touch signal sub-leads TLL1 are periodically arranged.
  • a group of first touch signal sub-leads includes k first touch signal sub-leads TLL1, where k is a positive integer greater than or equal to 3.
  • the orthographic projection of the first first touch signal sub-lead on the substrate substrate does not intersect with the orthographic projection of any first data signal sub-lead on the substrate substrate
  • the orthographic projection of each of the second to k-1 first touch signal sub-leads on the substrate substrate intersects with the orthographic projections of two first data signal sub-leads on the substrate substrate
  • the orthographic projection of the kth first touch signal sub-lead on the substrate substrate intersects with the orthographic projections of four first data signal sub-leads on the substrate substrate.
  • the orthographic projection of each of the 2nd to 7th first touch signal sub-leads on the base substrate 10 intersects with the orthographic projections of two first data signal sub-leads DLL1 on the base substrate 10
  • the orthographic projection of each of the 8th first touch signal sub-leads on the base substrate 10 intersects with the orthographic projections of four first data signal sub-leads DLL1 on the base substrate 10.
  • the first sub-area 81 at least a portion of an orthographic projection of each of the plurality of first touch signal sub-leads TLL1 on the base substrate 10 is located between orthographic projections of two first data signal sub-leads DLL1 electrically connected to the first-type data signal line on the base substrate 10.
  • an orthographic projection of a first data signal sub-lead DLL1 electrically connected to the second-type data signal line on the base substrate 10 is located between orthographic projections of two first data signal sub-leads DLL1 electrically connected to the first-type data signal line on the base substrate 10.
  • any two of the plurality of second data signal sub-leads DLL2 and the plurality of second touch signal sub-leads TLL2 are parallel to each other.
  • any two of the plurality of second data signal sub-leads DLL2 are parallel to each other
  • any two of the plurality of second touch signal sub-leads TLL2 are parallel to each other
  • any one of the plurality of second data signal sub-leads DLL2 is parallel to any one of the plurality of second touch signal sub-leads TLL2.
  • the main parts of the first data signal sub-lead DLL1 and the first touch signal sub-lead TLL1 basically extend along the direction Y; in the second sub-area 82, the main parts of the second data signal sub-lead DLL2 and the second touch signal sub-lead TLL2 basically extend along a direction inclined relative to the direction Y, so as to converge multiple data signal leads and multiple touch signal leads toward the direction of the driver chip IC.
  • the orthographic projections of the leads in the first conductive layer 20 on the base substrate 10 and the orthographic projections of the leads in the second conductive layer 30 on the base substrate 10 are alternately arranged.
  • the “leads in the first conductive layer 20” herein may include all the second touch signal sub-leads TLL2 and part of the second data signal sub-leads DLL2 in the first conductive layer 20; the “leads in the second conductive layer 30” herein may include part of the second data signal sub-leads DLL2 in the second conductive layer 30.
  • the orthographic projection of the leads in the first conductive layer 20 on the base substrate 10 and the orthographic projection of at least one lead adjacent to the leads on the base substrate 10 at least partially overlap.
  • the orthographic projection of the leads in the first conductive layer 20 on the base substrate 10 and the orthographic projection of a lead adjacent to the leads on the base substrate 10 completely overlap.
  • one end of the plurality of third data signal sub-leads DLL3 is electrically connected to a portion of the contact pins PIN1 of the driver chip IC
  • one end of the plurality of third touch signal sub-leads TLL3 is electrically connected to another portion of the contact pins PIN2 of the driver chip IC.
  • the arrangement order of the third data signal sub-leads DLL3 and the third touch signal sub-leads TLL3 corresponds to the arrangement order of the plurality of contact pins PIN1 and PIN2 of the driver chip IC.
  • the plurality of contact pins may be periodically arranged in the order of M first contact pins PIN1 and N second contact pins PIN2, wherein M is greater than or equal to 2, and N is equal to 1 or 2.
  • the plurality of contact pins may be periodically arranged in the order of 2 to 3 first contact pins PIN1 and 1 to 2 second contact pins PIN2. Specifically, starting from the left side in FIG9 , 3 first contact pins PIN1 and 1 second contact pin PIN2, 3 first contact pins PIN1 and 1 second contact pin PIN2, and 2 first contact pins PIN1 and 2 second contact pins PIN2 are arranged in sequence as an arrangement period.
  • the third data signal sub-lead DLL3 and the third touch signal sub-lead TLL3 are periodically arranged in the order of m third data signal sub-leads DLL3 and n third touch signal sub-leads TLL3, where m is equal to M and n is equal to 1.
  • the third data signal sub-lead DLL3 and the third touch signal sub-lead TLL3 are periodically arranged in the order of 2 to 3 third data signal sub-leads DLL3 and 1 third touch signal sub-lead TLL3, where m is equal to M and n is equal to 1.
  • 3 third data signal sub-leads DLL3 and 1 third touch signal sub-lead TLL3, 3 third data signal sub-leads DLL3 and 1 third touch signal sub-lead TLL3, and 2 third data signal sub-leads DLL3 and 1 third touch signal sub-lead TLL3 are arranged in sequence as one arrangement period.
  • the number N of the second contact pins PIN2 may be greater than the number n of the third touch signal sub-leads TLL3, wherein some of the second contact pins PIN2 may be dummy contact pins, which are not connected to the actual touch signal leads.
  • the second contact pins PIN2 labeled D, H, and L may be dummy contact pins, which are not connected to the actual touch signal leads.
  • FIG11 is a schematic diagram of a display device according to a part of exemplary embodiments of the present disclosure.
  • the display device 100 includes the above-mentioned array substrate. For example, it includes a display area AA and a peripheral area NA.
  • the film layer structures in the display area AA and the peripheral area NA can refer to the description of the above-mentioned various embodiments, which will not be repeated here.
  • the display device may include any device or product having a display function.
  • the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic garment, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.
  • PDA personal digital assistant
  • PMP portable multimedia player
  • a digital audio player a mobile medical device
  • a camera a wearable device (such as a head-mounted device, an electronic garment, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.
  • An embodiment of the present disclosure further provides a vehicle-mounted display screen, comprising the array substrate as described above or the touch display panel as described above.
  • the display device and the vehicle-mounted display screen according to the embodiments of the present disclosure have all the characteristics and advantages of the above-mentioned array substrate, and the details can be found in the above description.

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Abstract

本公开提供一种阵列基板、触控显示面板、显示装置和车载显示屏。阵列基板包括：衬底基板，包括显示区和周边区；多个数据信号线；多个触控信号线；驱动芯片，周边区包括扇出区，扇出区包括第一子区和第二子区，第一子区比第二子区更靠近显示区；阵列基板还包括位于扇出区的多个数据信号引线和多个触控信号引线；数据信号引线包括位于第一子区的第一数据信号子引线和位于第二子区的第二数据信号子引线，触控信号引线包括位于第一子区的第一触控信号子引线和位于第二子区的第二触控信号子引线；多个数据信号线和多个触控信号线位于同一导电层；多个第二数据信号子引线中的一部分与另一部分位于不同的导电层。

Description

阵列基板、触控显示面板、显示装置和车载显示屏 技术领域
本公开涉及显示技术领域，并且具体地涉及一种阵列基板、触控显示面板、显示装置和车载显示屏。
背景技术
由于具有轻薄、低能耗、体积小等一系列优点，液晶显示屏幕目前已被大量地用作于手机、笔记本电脑及个人电脑等消费电子产品中。液晶显示屏幕一般包括有源矩阵阵列基板、彩色滤光基板以及液晶层三部分，其中，有源矩阵阵列基板与彩色滤光基板对向组装，液晶层位于有源矩阵阵列基板及彩色滤光基板之间，通过有源矩阵阵列基板中的有源元件可以调节液晶层的液晶分子的指向，即可调整透过液晶层的光束强度以显示出影像。
目前，由于显示面板的分辨率越来越高，各种信号线也越来越密集，从而，阵列基板四周区域的走线也越来越密集，为了保持各走线的良好导电性以及均匀性，现有技术采用又宽又长且呈蛇形延伸的密集走线，然而，这种设计非常不利于窄边框显示面板的实现，并且，又宽又密集的走线布置使得相邻信号线之间很容易发生短路或者集中断路，从而容易导致工艺良率降低。
在本部分中公开的以上信息仅用于对本公开的技术构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
根据本公开的第一个方面，提供一种阵列基板，所述阵列基板包括：
衬底基板，所述衬底基板包括显示区和至少位于所述显示区的至少一侧的周边区；
多个像素单元，所述多个像素单元设置在所述显示区中，所述像素单元包括像素驱动电路；
多个触控电极，所述多个触控电极设置在所述显示区中；
至少一部分位于所述显示区的多个数据信号线，所述多个数据信号线分别与所述多个像素单元的像素驱动电路电连接，用于分别给所述多个像素单元传输数 据信号；
至少一部分位于所述显示区的多个触控信号线，所述多个触控信号线分别与所述多个触控电极电连接，用于分别给所述多个触控电极传输触控信号；
位于所述周边区的驱动芯片，所述驱动芯片用于至少提供所述数据信号和所述触控信号，
其中，所述周边区包括扇出区，所述扇出区位于所述显示区和所述驱动芯片之间，所述扇出区包括第一子区和第二子区，所述第一子区比所述第二子区更靠近所述显示区；
所述阵列基板还包括位于所述扇出区的多个数据信号引线和多个触控信号引线，所述多个数据信号引线的一端与所述驱动芯片电连接，所述多个数据信号引线的另一端分别与所述多个数据信号线电连接，所述多个触控信号引线的一端与所述驱动芯片电连接，所述多个触控信号引线的另一端分别与所述多个触控信号线电连接；
至少一个所述数据信号引线包括位于所述第一子区的第一数据信号子引线和位于所述第二子区的第二数据信号子引线，至少一个所述触控信号引线包括位于所述第一子区的第一触控信号子引线和位于所述第二子区的第二触控信号子引线；
所述多个数据信号线和所述多个触控信号线位于同一导电层；以及
多个第二数据信号子引线中的一部分第二数据信号子引线与多个第二数据信号子引线中的另一部分第二数据信号子引线位于不同的导电层。
根据本公开的实施例，所述扇出区还包括第三子区，所述第三子区比所述第二子区更靠近所述驱动芯片；
至少一个所述数据信号引线还包括位于所述第三子区的第三数据信号子引线，至少一个所述触控信号引线还包括位于所述第三子区的第三触控信号子引线；
所述驱动芯片包括多个接触引脚，多个所述第三数据信号子引线的一端分别与所述驱动芯片的一部分接触引脚电连接，多个所述第三触控信号子引线的一端分别与所述驱动芯片的另一部分接触引脚电连接；
所述第三数据信号子引线和所述第三触控信号子引线的排列顺序与所述驱动芯片的多个接触引脚的排列顺序对应。
根据本公开的实施例，多个第二数据信号子引线中的一部分第二数据信号子 引线位于第一导电层，多个第二数据信号子引线中的另一部分第二数据信号子引线位于第二导电层；以及
多个第二触控信号子线全部位于第一导电层。
根据本公开的实施例，多个第二数据信号子引线和多个第二触控信号子引线的组合中的至少一个子引线和与它相邻的子引线位于不同的导电层。
根据本公开的实施例，彼此电连接的至少一个第二数据信号子引线和至少一个数据信号线位于不同的导电层，彼此电连接的第二触控信号子引线和触控信号线均位于不同的导电层。
根据本公开的实施例，彼此电连接的第一触控信号子引线和触控信号线均位于不同的导电层，彼此电连接的第一触控信号子引线和第二触控信号子引线均位于同一导电层。
根据本公开的实施例，彼此电连接的第一触控信号子引线、第二触控信号子引线和第三触控信号子线均位于同一导电层。
根据本公开的实施例，所述多个数据信号线包括至少一个第一类数据信号线；
对于至少一个第一类数据信号线而言，彼此电连接的数据信号线、第一数据信号子引线和第二数据信号子引线三者位于同一导电层。
根据本公开的实施例，所述多个数据信号线包括至少一个第二类数据信号线；
对于至少一个第二类数据信号线而言，彼此电连接的数据信号线和第一数据信号子引线位于同一导电层，彼此电连接的第一数据信号子引线和第二数据信号子引线位于不同的导电层。
根据本公开的实施例，对于至少一个第一类数据信号线而言，彼此电连接的数据信号线、第一数据信号子引线、第二数据信号子引线和第三数据信号子引线四者位于同一导电层。
根据本公开的实施例，对于至少一个第二类数据信号线而言，彼此电连接的数据信号线和第一数据信号子引线位于同一导电层，彼此电连接的第一数据信号子引线和第二数据信号子引线位于不同的导电层，彼此电连接的第一数据信号子引线和第三数据信号子引线位于不同的导电层，彼此电连接的第二数据信号子引线和第三数据信号子引线位于同一导电层。
根据本公开的实施例，对于彼此电连接的第一触控信号子引线和触控信号线而言，所述触控信号线通过第一过孔与所述第一触控信号子引线电连接。
根据本公开的实施例，对于位于不同导电层的彼此电连接的第一数据信号子引线和第二数据信号子引线而言，所述第一数据信号子引线通过第二过孔与所述第二数据信号子引线电连接。
根据本公开的实施例，所述第一过孔位于所述第一子区靠近所述显示区的一侧，所述第二过孔位于所述第一子区靠近所述第二子区的一侧。
根据本公开的实施例，在所述第一子区中，至少一个第一触控信号子引线中的每一个在所述衬底基板上的正投影与任一个第一数据信号子引线在所述衬底基板上的正投影均不交叉；和/或，
在所述第一子区中，至少一个第一触控信号子引线中的每一个在所述衬底基板上的正投影与至少两个第一数据信号子引线在所述衬底基板上的正投影交叉。
根据本公开的实施例，在所述第一子区中，多组第一触控信号子引线周期性地排列；
一组第一触控信号子引线包括k个第一触控信号子引线，k为大于等于3的正整数；以及
在一组第一触控信号子引线中，第1个第一触控信号子引线在所述衬底基板上的正投影与任一个第一数据信号子引线在所述衬底基板上的正投影均不交叉，第2个至第k-1个第一触控信号子引线中的每一个在所述衬底基板上的正投影分别与两个第一数据信号子引线在所述衬底基板上的正投影交叉，第k个第一触控信号子引线在所述衬底基板上的正投影分别与四个第一数据信号子引线在所述衬底基板上的正投影交叉。
根据本公开的实施例，在所述第一子区中，多个第一触控信号子引线中的每一个在所述衬底基板上的正投影的至少一部分位于与所述第一类数据信号线电连接的两个第一数据信号子引线在所述衬底基板上的正投影之间；和/或，
在所述第一子区中，与所述第二类数据信号线电连接的第一数据信号子引线在所述衬底基板上的正投影位于与所述第一类数据信号线电连接的两个第一数据信号子引线在所述衬底基板上的正投影之间。
根据本公开的实施例，在所述第二子区中，多个第二数据信号子引线和多个第二触控信号子引线中的任意两者彼此平行。
根据本公开的实施例，在所述第二子区中，对于多个第二数据信号引线和多个第二触控信号引线的组合而言，位于第一导电层中的引线在所述衬底基板上的 正投影和位于第二导电层中的引线在所述衬底基板上的正投影交替布置；和/或，
在所述第二子区中，对于多个第二数据信号引线和多个第二触控信号引线的组合而言，位于第一导电层中的引线在所述衬底基板上的正投影和与该引线相邻的至少一个引线在所述衬底基板上的正投影至少部分重叠。
根据本公开的实施例，所述驱动芯片的多个接触引脚包括用于提供数据信号的第一接触引脚和用于提供触控信号的第二接触引脚；
所述多个接触引脚按照M个第一接触引脚和N个第二接触引脚的顺序周期性排列，其中，M大于等于2，N等于1或2；
在所述第三子区中，所述第三数据信号子引线和所述第三触控信号子引线按照m个第三数据信号子引线和n个第三触控信号子引线的顺序周期性排列，其中，m等于M，n等于1。
根据本公开的实施例，所述像素驱动电路包括设置在所述衬底基板上的至少一个薄膜晶体管，所述薄膜晶体管包括有源层、栅极、源极和漏极，所述阵列基板包括像素电极和公共电极；
其中，所述阵列基板包括：
设置于所述衬底基板上的第一导电层，所述栅极位于所述第一导电层；
设置于所述第一导电层远离所述衬底基板一侧的有源层；
设置于所述有源层远离所述衬底基板一侧的第三导电层，所述像素电极位于所述第三导电层；
设置于所述第三导电层远离所述衬底基板一侧的第二导电层，所述源极和所述漏极位于所述第二导电层；
设置于所述第二导电层远离所述衬底基板一侧的第四导电层，所述公共电极位于所述第四导电层，
其中，所述多个数据信号线和所述多个触控信号线位于所述第二导电层，所述多个触控信号引线位于所述第一导电层，与第一类数据信号线电连接的第二数据信号子引线位于第二导电层，与第二类数据信号线电连接的第二数据信号子引线位于第一导电层。
根据本公开的第二个方面，提供一种触控显示面板，包括上述的阵列基板。
根据本公开的第三个方面，提供一种显示装置，包括上述的阵列基板或上述的触控显示面板。
根据本公开的第四个方面，提供一种车载显示屏，包括上述的阵列基板或上述的触控显示面板。
附图说明
通过参照附图详细描述本公开的示例性实施例，本公开的特征及优点将变得更加明显。
图1是根据本公开的实施例的阵列基板的平面示意图。
图2是根据本公开的实施例的阵列基板沿图1中的线AA’截取的截面图，其示意性示出了所述阵列基板在显示区的截面结构。
图3是根据本公开的实施例的阵列基板在图1中的部分II处的局部放大图，其示意性示出了扇出区的布线设计。
图4是根据本公开的实施例的阵列基板在扇出区的第一子区处的局部放大图。
图5是根据本公开的另一些实施例的阵列基板在扇出区的第一子区处的局部放大图。
图6是根据本公开的实施例的阵列基板在扇出区的第二子区处的局部放大图。
图7是根据本公开的另一些实施例的阵列基板在扇出区的第二子区处的局部放大图。
图8是根据本公开的实施例的阵列基板在扇出区的第三子区处的局部放大图。
图9是根据本公开的实施例的阵列基板的驱动芯片的局部放大图。
图10A至图10C分别是根据本公开的实施例的阵列基板沿图6中的线CC’截取的截面图，其分别示意性示出了根据本公开的一部分示例性实施例的阵列基板中的双层布线设计。
图11是根据本公开的实施例的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公 开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在......之间”对“直接在......之间”、“相邻”对“直接相邻”或“在......上”对“直接在......上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XY、YZ和XZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
本领域技术人员应该理解，在本文中，除非另有说明，表述“高度”或“厚度”指的是沿垂直于阵列基板设置的各个膜层的表面的尺寸，即沿阵列基板的出光方向的尺寸，或称为沿显示装置的法线方向的尺寸。
在本文中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
需要说明的是，表述“同一层”，“同层设置”或类似表述，指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本文中，除非另有说明，表述“电连接”可以表示两个部件或元件直接电连接，例如，部件或元件A与部件或元件B直接接触，并且二者之间可以传递电信号；也可以表示两个部件或元件通过例如导电线的导电媒介电连接，例如，部件或元件A通过导电线与部件或元件B电连接，以在两个部件或元件之间传递电信号；还可以表示两个部件或元件通过至少一个电子元器件电连接，例如，部件或元件A通过至少一个薄膜晶体管与部件或元件B电连接，以在两个部件或元件之间传递电信号。
本公开的实施例至少提供一种阵列基板、触控显示面板、显示装置和车载显示屏。所述阵列基板包括：衬底基板，所述衬底基板包括显示区和至少位于所述显示区的至少一侧的周边区；多个像素单元，所述多个像素单元设置在所述显示区中，所述像素单元包括像素驱动电路；多个触控电极，所述多个触控电极设置在所述显示区中；位于所述显示区的多个数据信号线，所述多个数据信号线分别与所述多个像素单元的像素驱动电路电连接，用于分别给所述多个像素单元传输数据信号；位于所述显示区的多个触控信号线，所述多个触控信号线分别与所述多个触控电极电连接，用于分别给所述多个触控电极传输触控信号；位于所述周边区的驱动芯片，所述驱动芯片用于至少提供所述数据信号和所述触控信号，其中，所述周边区包括扇出区，所述扇出区位于所述显示区和所述驱动芯片之间，所述扇出区包括第一子区和第二子区，所述第一子区比所述第二子区更靠近所述显示区；所述触控显示基板阵列基板还包括位于所述扇出区的多个数据信号引线 和多个触控信号引线，所述多个数据信号引线的一端与所述驱动芯片电连接，所述多个数据信号引线的另一端分别与所述多个数据信号线电连接，所述多个触控信号引线的一端与所述驱动芯片电连接，所述多个触控信号引线的另一端分别与所述多个触控信号线电连接；至少一个所述数据信号引线包括位于所述第一子区的第一数据信号子引线和位于所述第二子区的第二数据信号子引线，至少一个所述触控信号引线包括位于所述第一子区的第一触控信号子引线和位于所述第二子区的第二触控信号子引线；所述多个数据信号线和所述多个触控信号线位于同一导电层；以及多个第二数据信号子引线中的一些一部分第二数据信号子引线与多个第二数据信号子引线中的另一些一部分第二数据信号子引线位于不同的导电层。在本公开的实施例中，通在本公开的实施例中，位于第二子区中的数据信号引线分两层设置。这样，可以有效减小位于第二子区中的数据信号引线占用边框的宽度，从而有利于实现窄边框的显示装置。
图1是根据本公开的实施例的阵列基板的平面示意图。图2是根据本公开的实施例的阵列基板沿图1中的线AA’截取的截面图，其示意性示出了所述阵列基板在显示区的截面结构。图3是根据本公开的实施例的阵列基板在图1中的部分II处的局部放大图，其示意性示出了扇出区的布线设计。图4是根据本公开的实施例的阵列基板在扇出区的第一子区处的局部放大图。图5是根据本公开的另一些实施例的阵列基板在扇出区的第一子区处的局部放大图。图6是根据本公开的实施例的阵列基板在扇出区的第二子区处的局部放大图。图7是根据本公开的另一些实施例的阵列基板在扇出区的第二子区处的局部放大图。图8是根据本公开的实施例的阵列基板在扇出区的第三子区处的局部放大图。图9是根据本公开的实施例的阵列基板的驱动芯片的局部放大图。图10A至图10C分别是根据本公开的实施例的阵列基板沿图6中的线CC’截取的截面图，其分别示意性示出了根据本公开的一部分示例性实施例的阵列基板中的双层布线设计。图11是根据本公开的实施例的显示装置的示意图。
参照图1，根据本公开的实施例的阵列基板可以包括：衬底基板10，例如，所述衬底基板10可以由玻璃、塑料、聚酰亚胺等材料形成。该衬底基板10包括显示区AA和位于显示区AA的至少一侧的周边区(或称为非显示区)NA。
阵列基板可以包括设置在显示区AA中的多个像素单元P(在图1中以虚线框示意性示出)，多个像素单元P可以沿方向X和方向Y成阵列地排布在衬底 基板10上。每一个像素单元P可以进一步包括多个子像素，例如红色子像素、绿色子像素、蓝色子像素。在图1中，示意性地示出了一个子像素SP。
例如，所述阵列基板包括信号输入侧IN1(图1中示出的下侧)。在该信号输入侧IN1，可以设置驱动芯片IC，该驱动芯片IC可以通过多根信号走线电连接至位于显示区的像素单元P，并且像素驱动电路可以电连接至该驱动芯片IC。以此方式，例如数据信号、扫描信号、触控信号等信号可以从该信号输入侧IN1传输至多个像素单元P。
例如，如图1所示，周边区NA可以位于显示区AA的四侧，即它围绕显示区AA。
需要说明的是，在附图中，以矩形形状示意性示出像素单元和子像素，但是，这并不构成对本公开的实施例提供的阵列基板包括的像素单元和子像素的形状的限制。
示例性地，在本公开的一部分实施例中，所述阵列基板可以为应用于TFT-LCD的阵列基板。例如，所述阵列基板可以为液晶显示面板的阵列基板。参照图2，所述阵列基板可以包括：设置在衬底基板10上像素电极40；设置在像素电极40上的绝缘层PVX；和设置在绝缘层PVX上的公共电极50。公共电极50用于与像素电极40配合，形成驱动液晶分子偏转的电场，实现特定灰阶的显示。
在图示的实施例中，像素电极40、绝缘层PVX和公共电极50沿远离衬底基板10的方向依次设置在衬底基板10上，即，像素电极40在下，公共电极50在上。
例如，像素电极40可以为面状电极，即，一个子像素P的像素电极40为一个面状电极。
再例如，公共电极50可以为带有多个狭缝502的梳状电极，即，一个公共电极50可以包括多个电极部501和多个狭缝502，多个狭缝502分别将多个电极部501间隔开。在该阵列基板中，梳状的公共电极50和面状的像素电极50叠置在阵列基板的衬底基板上，通过同一平面内梳状的公共电极边缘产生的电场以及梳状的公共电极与面状的像素电极间产生的电场形成多维电场，使得液晶盒内梳状的公共电极间、公共电极正上方所有取向的液晶分子都能够产生旋转，从而实现各个灰阶的显示。
需要说明的是，根据本公开实施例的阵列基板特别适用于ADS(ADvanced Super Dimension Switch，高级超维场转换技术)模式，本文中描述的实施例也以ADS模式显示面板为例进行说明。但是，本公开的实施例并不限于此，它还可以适用于各种其他模式的显示装置，例如TN(Twisted Nematic，扭曲向列)模式、VA(Vertical Alignment，垂直取向)模式等模式。
在本公开的实施例中，每一个所述像素单元P可以包括像素驱动电路。例如，阵列基板的每个子像素的像素驱动电路可以包括位于衬底基板10上的至少一个薄膜晶体管。结合参照图2，薄膜晶体管可以包括栅极TG、源极TS和漏极TD，还可以包括栅绝缘层、有源层、钝化层。薄膜晶体管的具体结构可以参照相关技术中的薄膜晶体管的结构，在此不再赘述。
继续参照图2，所述阵列基板可以包括：设置于所述衬底基板10上的第一导电层20，所述栅极TG位于所述第一导电层20；设置于所述第一导电层20远离所述衬底基板10一侧的有源层ACT；设置于所述有源层ACT远离所述衬底基板10一侧的第三导电层，所述像素电极40位于所述第三导电层；设置于所述第三导电层远离所述衬底基板一侧的第二导电层30，所述源极TS和所述漏极TD位于所述第二导电层30；和设置于所述第二导电层30远离所述衬底基板10一侧的第四导电层，所述公共电极50位于所述第四导电层。
例如，第一导电层20与第二导电层30之间可以设置有第一绝缘层GI，例如，第一绝缘层GI可以是栅绝缘层。第二导电层30与第四导电层之间可以设置有第二绝缘层PVX，例如，第二绝缘层PVX可以是钝化层。
例如，阵列基板还可以包括设置在衬底基板10上的各种信号线，所述各种信号线包括数据信号线、栅极扫描信号线、触控信号线、第一电源走线、第二电源走线等，以便为每个子像素中的像素驱动电路提供数据信号、扫描信号、触控信号、第一电源电压、第二电源电压等各种信号。在图1示出的实施例中，示意性示出了栅极扫描信号线GL和数据信号线DL。栅极扫描信号线GL和数据信号线DL可以电连接到各个像素单元P。
结合参照图1，根据本公开实施例的阵列基板具有显示区AA和围绕显示区AA的周边区NA。周边区NA包括第一边框区NA1、第二边框区NA2、第三边框区NA3和第四边框区NA4，例如，第一边框区NA1、第二边框区NA2、第三 边框区NA3和第四边框区NA4可以分别视为所述阵列基板的下边框、上边框、左边框和右边框。
从阵列基板正面观察，根据本公开实施例的阵列基板具有显示区和周边区。阵列基板的显示区布置有发光像素并且可以显示图像。在显示区周围围绕有周边区。典型地，从正面观察时，显示区四周都具有边框区。不过，一部分阵列基板从美观角度考虑，希望边框区越窄越好。因此，例如全面屏手机等应用中，显示区在左、右和上方可以不设置边框区。尽管如此，阵列基板仍需具有至少一个边框区，用于集中容纳难以弯曲的但必要的电路，并且此边框区通常位于显示区下方。例如，即使在目前的全面屏手机应用中，手机下方仍有不显示图像的下边框区。应当理解，本文中的“上”、“下”、“左”、“右”、“前”、“后”都是仅为了描述部件之间的相对位置而非绝对位置。在本公开中，下边框仅为了便于描述相对位置，但并不表示其必然位于显示画面的下方。此外，尽管常规的阵列基板为矩形并且下边框区是其四边之一的矩形区域，但其他外轮廓形状的阵列基板也可以具有其中集中容纳电路的任意形状的边框区。阵列基板中任何具有集中电路布线的边框均可以认为是下边框，并且在本公开中对其描述时规定其处于下方，显示区相应地位于上方。
在本公开的实施例中，驱动芯片IC可以设置在第一边框区NA1中。例如，在本公开的一部分实施例中，可以使用TDDI技术，即触控、显示驱动一体化技术。也就是说，将触控芯片与显示芯片整合进单一芯片(例如驱动芯片IC)中。
例如，参照图9，所述驱动芯片IC包括多个接触引脚，所述驱动芯片的多个接触引脚包括用于提供数据信号的第一接触引脚PIN1和用于提供触控信号的第二接触引脚PIN2。例如，在图9所示的实施例中，标号为阿拉伯数字1、2、3等的引线为与数据信号线电连接的引线，它们分别与用于提供数据信号的第一接触引脚PIN1电连接；标号为英文字母A、B、C等的引线为与触控信号线电连接的引线，它们分别与用于提供触控信号的第二接触引脚PIN2电连接。
例如，在本公开的实施例中，所述阵列基板可以包括设置在衬底基板10上的第一触控层、第二触控层以及设置在所述第一触控层与第二触控层之间的触控绝缘层。例如，在显示区AA中，所述阵列基板可以包括第一触控电极和第二触控电极，例如，第一触控电极可以是触控驱动电极，第二触控电极可以是触控感应电极。多个第一触控电极可以沿第一方向X排列，多个第二触控电极可以沿 与第一方向相交的第二方向排列。在一部分实施例中，第一方向垂直于第二方向。例如，如图1中所示例的，第一方向可以是阵列基板的宽度方向，第二方向可以是阵列基板的长度方向。
位于同一行的多个第一触控电极可以通过第二连接部电连接，位于同一列的多个第二触控电极可以通过第一连接部电连接。
作为示例，第一触控电极和第二触控电极的形状为菱形，第一连接部、第二连接部的形状为矩形。但是，本公开的实施例不局限于此，本领域技术人员应该理解，在其他的实施例中，第一触控电极和第二触控电极的形状以及第一连接部、第二连接部的形状可以为其他的形状。
用于连接第一触控电极的第一连接部和用于连接第二触控电极的第二连接部在衬底基板上的正投影至少部分重叠，即，第一连接部和第二连接部具有重叠区域。
在本公开的实施例中，第一触控电极和第二触控电极可以位于同一层，例如，它们可以位于第一触控层中。第一连接部可以也位于第一触控层中。第二连接部可以位于第二触控层中，即，第二连接部形成导电的桥接部。
触控绝缘层位于第一触控层和第二触控层之间，并覆盖第一触控电极和第二触控电极。触控绝缘层中设置有至少一对第一过孔，第一过孔贯穿触控绝缘层，从而能够暴露第一触控电极的部分区域，可称为桥接区域。每对第一过孔中的一个过孔位于相邻的两个第一触控电极中的一个上，另一个过孔位于所述相邻的两个第一触控电极中的另一个上。
在一部分实施例中，第二连接部的一部分设置在触控绝缘层的远离衬底基板的一侧，其余部分位于第一过孔中。第二连接部在衬底基板上的正投影与触控绝缘层中的至少一对第一过孔在衬底基板上的正投影至少部分重叠，以使得第二连接部能够通过与其重叠的第一过孔与第一触控电极电连接，从而实现相邻的第一触控电极之间的电连接。
在本公开的实施例中，结合参照图1和图3，所述阵列基板包括：至少一部分位于所述显示区AA的多个数据信号线DL，所述多个数据信号线DL分别与所述多个像素单元P的像素驱动电路电连接，用于分别给所述多个像素单元P传输数据信号；至少一部分位于所述显示区AA的多个触控信号线TL，所述多 个触控信号线TL分别与所述多个触控电极(例如第一触控电极)电连接，用于分别给所述多个触控电极传输触控信号。
所述周边区包括扇出区80，例如，扇出区80可以是第一边框区NA1的一部分。所述扇出区80位于所述显示区AA和所述驱动芯片IC之间，所述扇出区80包括第一子区81和第二子区82，所述第一子区81比所述第二子区82更靠近所述显示区AA。
例如，所述扇出区80还包括第三子区83，所述第三子区83比所述第二子区82更靠近所述驱动芯片IC。也就是说，所述扇出区80可以包括第一子区81、第二子区82和第三子区83，第一子区81、第二子区82和第三子区83沿依次远离显示区AA的方向布置。
结合参照图1、图2和图3，所述阵列基板还包括位于所述扇出区80的多个数据信号引线DLL和多个触控信号引线TLL，所述多个数据信号引线DLL的一端(例如远离显示区AA的一端)与所述驱动芯片IC电连接，所述多个数据信号引线DLL的另一端(例如靠近显示区AA的一端)分别与所述多个数据信号线DL电连接，所述多个触控信号引线TLL的一端(例如远离显示区AA的一端)与所述驱动芯片IC电连接，所述多个触控信号引线TLL的另一端(例如靠近显示区AA的一端)分别与所述多个触控信号线TL电连接。
结合参照图3、图4、图6和图8，至少一个所述数据信号引线DLL包括位于所述第一子区81的第一数据信号子引线DLL1和位于所述第二子区82的第二数据信号子引线DLL2，至少一个所述触控信号引线TLL包括位于所述第一子区81的第一触控信号子引线TLL1和位于所述第二子区82的第二触控信号子引线TLL2。
至少一个所述数据信号引线DLL还包括位于所述第三子区83的第三数据信号子引线DLL3，至少一个所述触控信号引线TLL还包括位于所述第三子区83的第三触控信号子引线TLL3。
在本公开的实施例中，所述多个数据信号线DL和所述多个触控信号线TL位于同一导电层，例如，它们都位于第二导电层30中。也就是说，在显示区AA中，所述多个数据信号线DL和所述多个触控信号线TL都位于第二导电层30中，例如，所述多个数据信号线DL和所述多个触控信号线TL均沿方向Y延伸，且位于同一导电层30中的所述多个数据信号线DL和所述多个触控信号线TL 在方向X上间隔布置。通过这样的排布方式，纵向延伸的多个数据信号线DL可以方便地给多列子像素分别提供数据信号，且纵向延伸的多个触控信号线TL可以方便地给多列触控单元分别提供触控信号。
在本公开的实施例中，多个第二数据信号子引线DLL2中的一部分第二数据信号子引线与多个第二数据信号子引线DLL2中的另一部分第二数据信号子引线位于不同的导电层。例如，一部分第二数据信号子引线DLL2位于第一导电层20，另一部分第二数据信号子引线DLL2位于第二导电层30。也就是说，在本公开的实施例中，位于第二子区82中的数据信号引线分两层设置。这样，可以有效减小位于第二子区82中的数据信号引线占用边框的宽度，从而有利于实现窄边框的显示装置。
在本公开的实施例中，多个第二触控信号子线TLL2全部位于同一导电层，例如，它们都位于第一导电层20。
在本公开的实施例中，在第二子区82中，全部第二触控信号子线TLL2和一部分第二数据信号子引线DLL2均位于第一导电层20，另一部分第二数据信号子引线DLL2位于第二导电层30。即，对于位于第二子区中的多个第二数据信号引线和多个第二触控信号引线的组合而言，一部分信号引线位于第一导电层，另一部分信号引线位于第二导电层。通过这样的排布方式，使得位于第二子区82中的信号引线分两层设置。这样，可以有效减小位于第二子区82中的信号引线占用边框的宽度，从而有利于实现窄边框的显示装置。
在一部分示例性的实施例中，以分辨率为1920*1080的显示装置为例，设置有1920*3列子像素，设置有1920列触控单元。示例性地，可以设置3个驱动芯片IC，在该示例中，每个驱动芯片IC需要引出1920个数据信号引线和640个触控信号引线。由此可见，在扇出区80中，特别是在第二子区82中，数据信号引线占用的区域为主要占据空间的区域。在本公开的实施例中，通过将一部分数据信号引线调整为在第一导电层布线，另一部分数据信号引线和全部的触控信号引线仍保持在各自的导电层中布线，可以在最小化调整信号引线的布线设计的情况下最大限度地减小位于第二子区82中的信号引线占用边框的宽度，从而有利于实现窄边框的显示装置。
例如，在示例性实施例中，可以将1920个数据信号引线中的640个数据信号引线调整为在第一导电层20中布线，另外的1280个数据信号引线仍保持在第 二导电层30中布线。这样，在扇出区80中，特别是在第二子区82中，可以在第一导电层20中布置640个数据信号引线和640个触控信号引线，即，在第一导电层20中共布置1280个信号引线；可以在第二导电层30中布置1280个数据信号引线。即，在扇出区80中，特别是在第二子区82中，在第一导电层20中布置的信号引线(例如，一部分为数据信号引线，另一部分为触控信号引线)的数量与在第二导电层30中布置的信号引线(例如，全部为数据信号引线)的数量基本相等。以此方式，可以在最小化调整信号引线的布线设计的情况下最大限度地减小位于第二子区82中的信号引线占用边框的宽度，从而有利于实现窄边框的显示装置。
在本公开的实施例中，对于位于第二子区82中的多个第二数据信号子引线DLL2和多个第二触控信号子引线TLL2的组合而言，多个第二数据信号子引线DLL2和多个第二触控信号子引线TLL2的组合中的至少一个子引线和与它相邻的子引线位于不同的导电层。例如，多个第二数据信号子引线DLL2和多个第二触控信号子引线TLL2的组合中的任一个子引线和与它相邻的子引线位于不同的导电层。需要说明的是，此处的“任一个子引线”表示该子引线可以是第二数据信号子引线DLL2，也可以是第二触控信号子引线TLL2。例如，在第二子区82中，位于第一导电层20中的信号引线和位于第二导电层30中的信号引线交替布置。参照图4、图5、图6和图7，分两层布线的数据引线按照如下的方式交替布置：从图4的左侧往右侧，位于第二导电层30中的第二数据信号子引线DLL2、位于第一导电层20中的第二数据信号子引线DLL2、位于第二导电层30中的第二数据信号子引线DLL2、位于第一导电层20中的第二触控信号子引线TLL2、位于第二导电层30中的第二数据信号子引线DLL2、位于第一导电层20中的第二触控信号子引线TLL2、位于第二导电层30中的第二数据信号子引线DLL2、位于第一导电层20中的第二数据信号子引线DLL2，以此类推。
在本公开的实施例中，彼此电连接的至少一个第二数据信号子引线(例如，位于第一导电层20中的一部分第二数据信号子引线DLL2)和至少一个数据信号线DL位于不同的导电层。在本公开的实施例中，彼此电连接的第二触控信号子引线TLL2和触控信号线TL均位于不同的导电层，例如，第二触控信号子引线TLL2位于第一导电层20，触控信号线TL位于第二导电层30。
在本公开的实施例中，彼此电连接的第一触控信号子引线TTL1和触控信号线TL均位于不同的导电层，彼此电连接的第一触控信号子引线TTL1和第二触控信号子引线TTL2均位于同一导电层。例如，第一触控信号子引线TTL1和第二触控信号子引线TTL2均位于第一导电层20，触控信号线TL位于第二导电层30。
进一步地，彼此电连接的第一触控信号子引线TTL1、第二触控信号子引线TTL2和第三触控信号子线TTL3均位于同一导电层。例如，第一触控信号子引线TTL1和第二触控信号子引线TTL2和第三触控信号子线TTL3均位于第一导电层20。
在本公开的实施例中，所述多个数据信号线DL可以包括至少一个第一类数据信号线和至少一个第二类数据信号线。例如，对于第一类数据信号线而言，与其电连接的数据信号引线将被布置在与数据信号线的同一层的导电层中；对于第二类数据信号线而言，与其电连接的数据信号引线的一部分将被布置在与数据信号线的不同层的导电层中。需要说明的是，在本文中，除非另有特别说明，使用第一类、第二类这样的前缀修饰数据信号线，仅是便于说明与其电连接的数据信号引线的布线的不同，不意图区分数据信号线本身。
例如，对于至少一个第一类数据信号线而言，彼此电连接的数据信号线DL、第一数据信号子引线DLL1和第二数据信号子引线DLL2三者位于同一导电层。例如，在图4中，从左侧开始数，第1、3、4、5、7个数据信号线均为第一类数据信号线。
例如，对于至少一个第二类数据信号线而言，彼此电连接的数据信号线DL和第一数据信号子引线DLL1位于同一导电层，彼此电连接的第一数据信号子引线DLL1和第二数据信号子引线DLL2位于不同的导电层。例如，彼此电连接的数据信号线DL和第一数据信号子引线DLL1位于第二导电层30，第二数据信号子引线DLL2位于第一导电层20。例如，在图4中，从左侧开始数，第2、6个数据信号线均为第二类数据信号线。
结合参照图3、图4和图8，对于至少一个第一类数据信号线而言，彼此电连接的数据信号线DL、第一数据信号子引线DLL1、第二数据信号子引线DLL2和第三数据信号子引线DLL3四者位于同一导电层，例如，均位于第二导电层30。
对于至少一个第二类数据信号线而言，彼此电连接的数据信号线DL和第一数据信号子引线DLL1位于同一导电层，彼此电连接的第一数据信号子引线DLL1和第二数据信号子引线DLL2位于不同的导电层，彼此电连接的第一数据信号子引线DLL1和第三数据信号子引线DLL3位于不同的导电层，彼此电连接的第二数据信号子引线DLL2和第三数据信号子引线DLL3位于同一导电层。例如，数据信号线DL和第一数据信号子引线DLL1位于第二导电层30，第二数据信号子引线DLL2和第三数据信号子引线DLL3位于第一导电层20。
参照图4，对于彼此电连接的第一触控信号子引线TLL1和触控信号线TL而言，所述触控信号线TL通过第一过孔VH1与所述第一触控信号子引线TLL1电连接。对于位于不同导电层的彼此电连接的第一数据信号子引线DLL1和第二数据信号子引线DLL2而言，所述第一数据信号子引线DLL1通过第二过孔VH2与所述第二数据信号子引线DLL1电连接。
需要说明的是，在本文中，除非另有特别说明，第一子区81与第二子区82毗邻的边界经过触控线的所述第一过孔VH1，相应地，数据信号线DL和触控信号线TL均从显示区AA延伸至周边区NA。
在图4所示的实施例中，所述第一过孔VH1位于所述第一子区81靠近所述显示区AA的一侧，所述第二过孔VH2位于所述第一子区81靠近所述第二子区82的一侧。也就是说，在本公开的实施例中，触控信号线与触控信号引线在第一子区81靠近所述显示区AA的一侧的位置实现换层转接，部分数据信号线与数据信号引线在第一子区81远离显示区AA的一侧的位置实现换层转接。例如，所述阵列基板还可以包括沿方向X延伸的第一电源走线VCOM，例如，所述第一电源走线VCOM可以为用于给公共电极传输电压信号的走线。第一过孔VH1可以位于第一电源走线VCOM远离显示区AA的一侧，并且第一过孔VH1靠近第一电源走线VCOM。
通过这样的换层转接方式，在第一子区81中，第一数据信号子引线的至少大部分均位于第二导电层30中，这样，位于第一导电层20的第一触控信号子引线TLL1可以进行绕线布线，例如，在图4所示的实施例中，部分第一触控信号子引线TLL1(从左侧开始数，第2～8个第一触控信号子引线)可以横跨多个第一数据信号子引线。这样，在后续的第二子区82中，可以实现位于第一导电层20的信号引线和位于第二导电层30的信号引线的交替布置。
在本公开的一部分实施例中，在所述第一子区81中，至少一个第一触控信号子引线TLL1(例如，在图4所示的实施例中，从左侧开始数，第1、9个第一触控信号子引线)中的每一个在所述衬底基板10上的正投影与任一个第一数据信号子引线DLL1在所述衬底基板10上的正投影均不交叉。在所述第一子区81中，至少一个第一触控信号子引线(例如，在图4所示的实施例中，从左侧开始数，第2～8个第一触控信号子引线)中的每一个在所述衬底基板10上的正投影与至少两个第一数据信号子引线DLL1在所述衬底基板10上的正投影交叉。
在一些示例性的实施例中，在所述第一子区81中，多组第一触控信号子引线TLL1周期性地排列。一组第一触控信号子引线包括k个第一触控信号子引线TLL1，k为大于等于3的正整数。在一组第一触控信号子引线TLL1中，第1个第一触控信号子引线在所述衬底基板上的正投影与任一个第一数据信号子引线在所述衬底基板上的正投影均不交叉，第2个至第k-1个第一触控信号子引线中的每一个在所述衬底基板上的正投影分别与两个第一数据信号子引线在所述衬底基板上的正投影交叉，第k个第一触控信号子引线在所述衬底基板上的正投影分别与四个第一数据信号子引线在所述衬底基板上的正投影交叉。
例如，在图4所示的实施例中，从左侧开始数，第2～7个第一触控信号子引线中的每一个在所述衬底基板10上的正投影与两个第一数据信号子引线DLL1在所述衬底基板10上的正投影交叉，第8个第一触控信号子引线中的每一个在所述衬底基板10上的正投影与四个第一数据信号子引线DLL1在所述衬底基板10上的正投影交叉。通过这样的绕线布线设计，在后续的第二子区82中，可以实现位于第一导电层20的信号引线和位于第二导电层30的信号引线的交替布置。
在本公开的一部分实施例中，在所述第一子区81中，多个第一触控信号子引线TLL1中的每一个在所述衬底基板10上的正投影的至少一部分位于与所述第一类数据信号线电连接的两个第一数据信号子引线DLL1在所述衬底基板10上的正投影之间。在所述第一子区81中，与所述第二类数据信号线电连接的第一数据信号子引线DLL1在所述衬底基板10上的正投影位于与所述第一类数据信号线电连接的两个第一数据信号子引线DLL1在所述衬底基板10上的正投影之间。
参照图6，在所述第二子区82中，多个第二数据信号子引线DLL2和多个第二触控信号子引线TLL2中的任意两者彼此平行。例如，在所述第二子区82 中，多个第二数据信号子引线DLL2中的任意两个彼此平行，多个第二触控信号子引线TLL2中的任意两者彼此平行，多个第二数据信号子引线DLL2中的任意一个与多个第二触控信号子引线TLL2中的任意一个彼此平行。
在本公开的一部分实施例中，在第一子区81中，第一数据信号子引线DLL1和第一触控信号子引线TLL1的主体部分基本沿方向Y延伸；在第二子区82中，第二数据信号子引线DLL2和第二触控信号子引线TLL2的主体部分基本沿相对于方向Y倾斜的方向延伸，以便将多个数据信号引线和多个触控信号引线朝着驱动芯片IC的方向汇聚。
结合参照图10A至图10C，在所述第二子区82中，对于多个第二数据信号引线DLL2和多个第二触控信号引线TLL2的组合而言，位于第一导电层20中的引线在所述衬底基板10上的正投影和位于第二导电层30中的引线在所述衬底基板10上的正投影交替布置。结合上文的描述，此处的“位于第一导电层20中的引线”可以包括全部的第二触控信号子引线TLL2和位于第一导电层20中的部分第二数据信号子引线DLL2；此处的“位于第二导电层30中的引线”可以包括位于第二导电层30中的部分第二数据信号子引线DLL2。
例如，在所述第二子区82中，对于多个第二数据信号引线DLL2和多个第二触控信号引线TLL2的组合而言，位于第一导电层20中的引线在所述衬底基板10上的正投影和与该引线相邻的至少一个引线在所述衬底基板10上的正投影至少部分重叠。示例性地，位于第一导电层20中的引线在所述衬底基板10上的正投影和与该引线相邻的一个引线在所述衬底基板10上的正投影全部重叠。通过这样的布线方式，可以最大限度地减小位于第二子区82中的信号引线占用边框的宽度，从而有利于实现窄边框的显示装置。
结合参照图8和图9，在本公开的实施例中，多个所述第三数据信号子引线DLL3的一端分别与所述驱动芯片IC的一部分接触引脚PIN1电连接，多个所述第三触控信号子引线TLL3的一端分别与所述驱动芯片IC的另一部分接触引脚PIN2电连接。所述第三数据信号子引线DLL3和所述第三触控信号子引线TLL3的排列顺序与所述驱动芯片IC的多个接触引脚PIN1、PIN2的排列顺序对应。
例如，所述多个接触引脚可以按照M个第一接触引脚PIN1和N个第二接触引脚PIN2的顺序周期性排列，其中，M大于等于2，N等于1或2。例如，在图9所示的实施例中，多个接触引脚可以按照2～3个第一接触引脚PIN1和1～2 个第二接触引脚PIN2的顺序周期性排列。具体地，从图9中的左侧开始，按照3个第一接触引脚PIN1和1个第二接触引脚PIN2、3个第一接触引脚PIN1和1个第二接触引脚PIN2、2个第一接触引脚PIN1和2个第二接触引脚PIN2作为一个排列周期，顺序排列。
在图8所示的实施例中，在所述第三子区83中，所述第三数据信号子引线DLL3和所述第三触控信号子引线TLL3按照m个第三数据信号子引线DLL3和n个第三触控信号子引线TLL3的顺序周期性排列，其中，m等于M，n等于1。例如，所述第三数据信号子引线DLL3和所述第三触控信号子引线TLL3按照2～3个第三数据信号子引线DLL3和1个第三触控信号子引线TLL3的顺序周期性排列，其中，m等于M，n等于1。具体地，从图8中的左侧开始，按照3个第三数据信号子引线DLL3和1个第三触控信号子引线TLL3、3个第三数据信号子引线DLL3和1个第三触控信号子引线TLL3、2个第三数据信号子引线DLL3和1个第三触控信号子引线TLL3作为一个排列周期，顺序排列。
需要说明的是，在图8和图9所示的实施例中，在部分排列周期中，第二接触引脚PIN2的数量N可以大于第三触控信号子引线TLL3的数量n，其中部分第二接触引脚PIN2可以是虚设的接触引脚，它们不与实际的触控信号引线连接。例如，在图9所示的实施例中，标号为D、H、L的第二接触引脚PIN2可以是虚设的接触引脚，它们不与实际的触控信号引线连接。
图11是根据本公开的一部分示例性实施例的显示装置的示意图。所述显示装置100包括上述的阵列基板。例如，它包括显示区AA和周边区NA，显示区AA和周边区NA中的膜层结构可以参照上述各个实施例的描述，在此不再赘述。
所述显示装置可以包括任何具有显示功能的设备或产品。例如，所述显示装置可以是智能电话、移动电话、电子书阅读器、台式电脑(PC)、膝上型PC、上网本PC、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字音频播放器、移动医疗设备、相机、可穿戴设备(例如头戴式设备、电子服饰、电子手环、电子项链、电子配饰、电子纹身、或智能手表)、电视机等。
本公开的实施例还提供一种车载显示屏，包括根据如上所述的阵列基板或如上所述的触控显示面板。
应该理解，根据本公开实施例的显示装置和车载显示屏具有上述阵列基板的所有特点和优点，具体可以参见上文的描述。
虽然本公开的总体技术构思的一部分实施例已被显示和说明，本领域普通技术人员将理解，在不背离所述总体技术构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (24)

  1. 一种阵列基板，其特征在于，所述阵列基板包括：
    衬底基板，所述衬底基板包括显示区和至少位于所述显示区的至少一侧的周边区；
    多个像素单元，所述多个像素单元设置在所述显示区中，所述像素单元包括像素驱动电路；
    多个触控电极，所述多个触控电极设置在所述显示区中；
    至少一部分位于所述显示区的多个数据信号线，所述多个数据信号线分别与所述多个像素单元的像素驱动电路电连接，用于分别给所述多个像素单元传输数据信号；
    至少一部分位于所述显示区的多个触控信号线，所述多个触控信号线分别与所述多个触控电极电连接，用于分别给所述多个触控电极传输触控信号；
    位于所述周边区的驱动芯片，所述驱动芯片用于至少提供所述数据信号和所述触控信号，
    其中，所述周边区包括扇出区，所述扇出区位于所述显示区和所述驱动芯片之间，所述扇出区包括第一子区和第二子区，所述第一子区比所述第二子区更靠近所述显示区；
    所述阵列基板还包括位于所述扇出区的多个数据信号引线和多个触控信号引线，所述多个数据信号引线的一端与所述驱动芯片电连接，所述多个数据信号引线的另一端分别与所述多个数据信号线电连接，所述多个触控信号引线的一端与所述驱动芯片电连接，所述多个触控信号引线的另一端分别与所述多个触控信号线电连接；
    至少一个所述数据信号引线包括位于所述第一子区的第一数据信号子引线和位于所述第二子区的第二数据信号子引线，至少一个所述触控信号引线包括位于所述第一子区的第一触控信号子引线和位于所述第二子区的第二触控信号子引线；
    所述多个数据信号线和所述多个触控信号线位于同一导电层；以及
    多个第二数据信号子引线中的一部分第二数据信号子引线与多个第二数据信号子引线中的另一部分第二数据信号子引线位于不同的导电层。
  2. 根据权利要求1所述的阵列基板，其中，所述扇出区还包括第三子区，所述第三子区比所述第二子区更靠近所述驱动芯片；
    至少一个所述数据信号引线还包括位于所述第三子区的第三数据信号子引线，至少一个所述触控信号引线还包括位于所述第三子区的第三触控信号子引线；
    所述驱动芯片包括多个接触引脚，多个所述第三数据信号子引线的一端分别与所述驱动芯片的一部分接触引脚电连接，多个所述第三触控信号子引线的一端分别与所述驱动芯片的另一部分接触引脚电连接；
    所述第三数据信号子引线和所述第三触控信号子引线的排列顺序与所述驱动芯片的多个接触引脚的排列顺序对应。
  3. 根据权利要求1或2所述的阵列基板，其中，多个第二数据信号子引线中的一部分第二数据信号子引线位于第一导电层，多个第二数据信号子引线中的另一部分第二数据信号子引线位于第二导电层；以及
    多个第二触控信号子线全部位于第一导电层。
  4. 根据权利要求3所述的阵列基板，其中，多个第二数据信号子引线和多个第二触控信号子引线的组合中的至少一个子引线和与它相邻的子引线位于不同的导电层。
  5. 根据权利要求3所述的阵列基板，其中，彼此电连接的至少一个第二数据信号子引线和至少一个数据信号线位于不同的导电层，彼此电连接的第二触控信号子引线和触控信号线均位于不同的导电层。
  6. 根据权利要求4所述的阵列基板，其中，彼此电连接的第一触控信号子引线和触控信号线均位于不同的导电层，彼此电连接的第一触控信号子引线和第二触控信号子引线均位于同一导电层。
  7. 根据权利要求6所述的阵列基板，其中，彼此电连接的第一触控信号子引线、第二触控信号子引线和第三触控信号子线均位于同一导电层。
  8. 根据权利要求5所述的阵列基板，其中，所述多个数据信号线包括至少一个第一类数据信号线；
    对于至少一个第一类数据信号线而言，彼此电连接的数据信号线、第一数据信号子引线和第二数据信号子引线三者位于同一导电层。
  9. 根据权利要求8所述的阵列基板，其中，所述多个数据信号线包括至少一个第二类数据信号线；
    对于至少一个第二类数据信号线而言，彼此电连接的数据信号线和第一数据信号子引线位于同一导电层，彼此电连接的第一数据信号子引线和第二数据信号子引线位于不同的导电层。
  10. 根据权利要求8或9所述的阵列基板，其中，对于至少一个第一类数据信号线而言，彼此电连接的数据信号线、第一数据信号子引线、第二数据信号子引线和第三数据信号子引线四者位于同一导电层。
  11. 根据权利要求9所述的阵列基板，其中，对于至少一个第二类数据信号线而言，彼此电连接的数据信号线和第一数据信号子引线位于同一导电层，彼此电连接的第一数据信号子引线和第二数据信号子引线位于不同的导电层，彼此电连接的第一数据信号子引线和第三数据信号子引线位于不同的导电层，彼此电连接的第二数据信号子引线和第三数据信号子引线位于同一导电层。
  12. 根据权利要求7所述的阵列基板，其中，对于彼此电连接的第一触控信号子引线和触控信号线而言，所述触控信号线通过第一过孔与所述第一触控信号子引线电连接。
  13. 根据权利要求12所述的阵列基板，其中，对于位于不同导电层的彼此电连接的第一数据信号子引线和第二数据信号子引线而言，所述第一数据信号子引线通过第二过孔与所述第二数据信号子引线电连接。
  14. 根据权利要求13所述的阵列基板，其中，所述第一过孔位于所述第一子 区靠近所述显示区的一侧，所述第二过孔位于所述第一子区靠近所述第二子区的一侧。
  15. 根据权利要求7所述的阵列基板，其中，在所述第一子区中，至少一个第一触控信号子引线中的每一个在所述衬底基板上的正投影与任一个第一数据信号子引线在所述衬底基板上的正投影均不交叉；和/或，
    在所述第一子区中，至少一个第一触控信号子引线中的每一个在所述衬底基板上的正投影与至少两个第一数据信号子引线在所述衬底基板上的正投影交叉。
  16. 根据权利要求15所述的阵列基板，其中，在所述第一子区中，多组第一触控信号子引线周期性地排列；
    一组第一触控信号子引线包括k个第一触控信号子引线，k为大于等于3的正整数；以及
    在一组第一触控信号子引线中，第1个第一触控信号子引线在所述衬底基板上的正投影与任一个第一数据信号子引线在所述衬底基板上的正投影均不交叉，第2个至第k-1个第一触控信号子引线中的每一个在所述衬底基板上的正投影分别与两个第一数据信号子引线在所述衬底基板上的正投影交叉，第k个第一触控信号子引线在所述衬底基板上的正投影分别与四个第一数据信号子引线在所述衬底基板上的正投影交叉。
  17. 根据权利要求9所述的阵列基板，其中，在所述第一子区中，多个第一触控信号子引线中的每一个在所述衬底基板上的正投影的至少一部分位于与所述第一类数据信号线电连接的两个第一数据信号子引线在所述衬底基板上的正投影之间；和/或，
    在所述第一子区中，与所述第二类数据信号线电连接的第一数据信号子引线在所述衬底基板上的正投影位于与所述第一类数据信号线电连接的两个第一数据信号子引线在所述衬底基板上的正投影之间。
  18. 根据权利要求7所述的阵列基板，其中，在所述第二子区中，多个第二数据信号子引线和多个第二触控信号子引线中的任意两者彼此平行。
  19. 根据权利要求18所述的阵列基板，其中，在所述第二子区中，对于多个第二数据信号引线和多个第二触控信号引线的组合而言，位于第一导电层中的引线在所述衬底基板上的正投影和位于第二导电层中的引线在所述衬底基板上的正投影交替布置；和/或，
    在所述第二子区中，对于多个第二数据信号引线和多个第二触控信号引线的组合而言，位于第一导电层中的引线在所述衬底基板上的正投影和与该引线相邻的至少一个引线在所述衬底基板上的正投影至少部分重叠。
  20. 根据权利要求2所述的阵列基板，其中，所述驱动芯片的多个接触引脚包括用于提供数据信号的第一接触引脚和用于提供触控信号的第二接触引脚；
    所述多个接触引脚按照M个第一接触引脚和N个第二接触引脚的顺序周期性排列，其中，M大于等于2，N等于1或2；
    在所述第三子区中，所述第三数据信号子引线和所述第三触控信号子引线按照m个第三数据信号子引线和n个第三触控信号子引线的顺序周期性排列，其中，m等于M，n等于1。
  21. 根据权利要求1-6中任一项所述的阵列基板，其特征在于，所述像素驱动电路包括设置在所述衬底基板上的至少一个薄膜晶体管，所述薄膜晶体管包括有源层、栅极、源极和漏极，所述阵列基板包括像素电极和公共电极；
    其中，所述阵列基板包括：
    设置于所述衬底基板上的第一导电层，所述栅极位于所述第一导电层；
    设置于所述第一导电层远离所述衬底基板一侧的有源层；
    设置于所述有源层远离所述衬底基板一侧的第三导电层，所述像素电极位于所述第三导电层；
    设置于所述第三导电层远离所述衬底基板一侧的第二导电层，所述源极和所述漏极位于所述第二导电层；
    设置于所述第二导电层远离所述衬底基板一侧的第四导电层，所述公共电极位于所述第四导电层，
    其中，所述多个数据信号线和所述多个触控信号线位于所述第二导电层，所 述多个触控信号引线位于所述第一导电层，与第一类数据信号线电连接的第二数据信号子引线位于第二导电层，与第二类数据信号线电连接的第二数据信号子引线位于第一导电层。
  22. 一种触控显示面板，包括根据权利要求1至21中任一项所述的阵列基板。
  23. 一种显示装置，包括根据权利要求1至21中任一项所述的阵列基板或根据权利要求22所述的触控显示面板。
  24. 一种车载显示屏，包括根据权利要求1至21中任一项所述的阵列基板或根据权利要求22所述的触控显示面板。
PCT/CN2022/128932 2022-11-01 2022-11-01 阵列基板、触控显示面板、显示装置和车载显示屏 WO2024092497A1 (zh)

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CN106775124A (zh) * 2017-01-20 2017-05-31 上海天马微电子有限公司 一种触控显示面板及显示装置
US20170185190A1 (en) * 2015-12-27 2017-06-29 Lg Display Co., Ltd. Display Device with Touch Sensor
CN206470722U (zh) * 2017-02-23 2017-09-05 上海中航光电子有限公司 阵列基板、显示面板和显示装置
CN114509886A (zh) * 2022-02-08 2022-05-17 广州华星光电半导体显示技术有限公司 显示面板和显示装置

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US20170185190A1 (en) * 2015-12-27 2017-06-29 Lg Display Co., Ltd. Display Device with Touch Sensor
CN106775124A (zh) * 2017-01-20 2017-05-31 上海天马微电子有限公司 一种触控显示面板及显示装置
CN206470722U (zh) * 2017-02-23 2017-09-05 上海中航光电子有限公司 阵列基板、显示面板和显示装置
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