WO2024108524A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2024108524A1
WO2024108524A1 PCT/CN2022/134227 CN2022134227W WO2024108524A1 WO 2024108524 A1 WO2024108524 A1 WO 2024108524A1 CN 2022134227 W CN2022134227 W CN 2022134227W WO 2024108524 A1 WO2024108524 A1 WO 2024108524A1
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WIPO (PCT)
Prior art keywords
area
display area
gate
line
array substrate
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Application number
PCT/CN2022/134227
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English (en)
French (fr)
Inventor
边若梅
金红贵
段智龙
王佩佩
孙平原
刘洋
张勇
王建
杨越
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/134227 priority Critical patent/WO2024108524A1/zh
Publication of WO2024108524A1 publication Critical patent/WO2024108524A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a display device.
  • Special-shaped display panels are specially shaped display panels modified on the basis of traditional display panels, so that the characteristics of the display panel can better adapt to the overall structure and environment.
  • Special-shaped display panels have been successfully applied to wearable electronic devices such as watches, glasses or smart bracelets, and common special-shaped display panels mainly include fan-shaped, arc-shaped, circular, cylindrical, polygonal and other shapes.
  • an array substrate comprising:
  • a base substrate comprising a display area and a frame area surrounding the display area, wherein the display area comprises a first display area and a second display area sequentially arranged along a first direction, and the second display area is a non-rectangular display area;
  • the frame area comprises a first frame area surrounding the first display area, and a second frame area surrounding the second display area;
  • a plurality of gate lines are arranged along the first direction and extend along the second direction in the first display area and the second display area, wherein the gate lines in the first display area extend to the first frame area, and the gate lines in the second display area extend to the second frame area, and the second direction intersects with the first direction;
  • a plurality of data lines which are insulated from the plurality of gate lines, and are arranged along the second direction in the first display area and the second display area and extend along the first direction, and the plurality of data lines extend to the second frame area and are arranged around the second display area in the second frame area;
  • a plurality of antistatic structures are electrically connected to the plurality of gate lines, and the plurality of antistatic structures include a plurality of first antistatic structures located in the first border area, and a plurality of second antistatic structures located in the second border area, wherein at least a portion of the first antistatic structures extend along the first direction, and at least a portion of the second antistatic structures extend along the winding direction of the data lines.
  • the anti-static structures electrically connecting two adjacent gate lines are located on both sides of the display area.
  • the above-mentioned array substrate provided in the embodiments of the present disclosure also includes a plurality of first floating anti-static structures and a plurality of second floating anti-static structures, wherein the plurality of first floating anti-static structures are electrically connected to the plurality of first anti-static structures in the first border area, and the plurality of first floating anti-static structures and the two first anti-static structures in the first border area that are farthest from the second border area are arranged side by side in the second direction; the second floating anti-static structure is electrically connected to the plurality of second anti-static structures in the second border area, and the plurality of second floating anti-static structures and the two second anti-static structures in the second border area that are farthest from the first border area are arranged side by side in the winding direction of the data line.
  • a short-circuit ring is further included, and the short-circuit ring is located in the first frame area and the second frame area;
  • the plurality of anti-static structures are electrically connected to the plurality of first floating anti-static structures and the plurality of second floating anti-static structures respectively through the short-circuit ring.
  • the array substrate provided in the embodiments of the present disclosure further includes a common electrode line and a common electrode, wherein the common electrode line is located in the first frame area and the second frame area, and the common electrode extends from the first display area and the second display area to the first frame area and the second frame area;
  • the plurality of first floating anti-static structures are electrically connected to the common electrode line, and the plurality of second floating anti-static structures are electrically connected to the common electrode.
  • the array substrate provided in the embodiments of the present disclosure further includes a first connecting line, which is in the same layer as the plurality of gate lines, and which connects the second floating antistatic structure with the common electrode.
  • the short-circuit ring and the common electrode line are both in the same layer as the plurality of data lines.
  • the second border area includes a binding area extending substantially along the second direction on a side of the second display area away from the first display area, a non-rectangular area connecting the binding area and the first border area, and a routing area located between the binding area and the second display area;
  • the array substrate also includes a second connecting line, which is in the same layer as the multiple gate lines.
  • the second connecting line is connected between the common electrode line and the binding area.
  • the second connecting line includes a widened portion, which is arranged adjacent to the connection between the routing area and the non-rectangular area, and the widened portion is a grid-like structure.
  • At least part of the gate lines are electrically connected to the antistatic structure after being bent in the first border area and the second border area.
  • the above array substrate provided by the embodiments of the present disclosure, it further includes a plurality of gate leads, wherein the plurality of gate leads are electrically connected to the plurality of anti-static structures at a side of the plurality of anti-static structures away from the first display area and the second display area;
  • the plurality of gate leads include a plurality of first gate leads and a plurality of second gate leads, the plurality of first gate leads are in the same layer as the plurality of gate lines, and the plurality of second gate leads are in the same layer as the plurality of data lines.
  • the anti-static structure includes a first transistor and a second transistor, wherein the gate of the first transistor is electrically connected to the gate line and the gate lead respectively, the first electrode of the first transistor is electrically connected to the gate of the first transistor, the second electrode of the first transistor is integrally arranged with the first electrode of the second transistor, the second electrode of the second transistor is integrally arranged with the first electrode of the first transistor, and the gate of the second transistor is electrically connected to the first electrode of the second transistor and the short-circuit ring.
  • the array substrate provided in the embodiments of the present disclosure further includes a plurality of first transfer electrodes and a plurality of second transfer electrodes, wherein the plurality of first transfer electrodes and the plurality of second transfer electrodes are arranged in the same layer on the layer where the plurality of gate lines are located and on a side of the layer where the plurality of data lines are located away from the base substrate;
  • the gate of the first transistor is electrically connected to the gate line and the gate lead respectively through the first switching electrode
  • the gate of the second transistor is electrically connected to the first electrode of the second transistor and the short-circuit ring respectively through the second switching electrode.
  • the second border area includes a binding area extending substantially along the second direction on a side of the second display area away from the first display area, a non-rectangular area connecting the binding area and the first border area, and a routing area located between the binding area and the second display area;
  • the gate lead includes a first gate lead section located in the non-rectangular area, a second gate lead section located in the routing area, and a third gate lead section connecting the first gate lead section and the second gate lead section; the sum of the line width of the first gate lead section and the line spacing of the first gate lead section adjacent to the same layer is a first distance, the sum of the line width of the second gate lead section and the line spacing of the second gate lead section adjacent to the same layer is a second distance, the sum of the line width of the third gate lead section and the line spacing of the third gate lead section adjacent to the same layer is a third distance, and the ratio of the first distance to the second distance is greater than 1 and less than or equal to 1.5.
  • the array substrate provided in the embodiments of the present disclosure further includes a grounding line, which is arranged in the same layer as the multiple gate lines and is located on a side of the multiple gate lines away from the multiple anti-static structures.
  • the array substrate provided in the embodiments of the present disclosure further includes a plurality of floating blocks, which are arranged in the same layer as the plurality of gate lines, and are roughly evenly distributed between the ground lines and the plurality of gate leads.
  • the above array substrate provided by the embodiments of the present disclosure, it further includes a plurality of third connecting lines, and the plurality of third connecting lines are in the same layer as the plurality of gate lines;
  • the second border area includes a binding area extending substantially along a second direction on a side of the second display area away from the first display area, and a non-rectangular area connecting the binding area and the first border area;
  • the multiple data lines include alternately arranged first data lines and second data lines, the first data lines extend from the first display area and the second display area across the non-rectangular area and to the binding area, and the second data lines extend from the first display area and the second display area across the non-rectangular area and are connected to the binding area via the third connecting line.
  • the orthographic projection of the third connection line on the base substrate at least partially overlaps with the orthographic projection of the adjacent first data line on the base substrate.
  • the array substrate provided in the embodiments of the present disclosure further includes a plurality of third transfer electrodes, a first insulating layer and a second insulating layer, wherein the layer where the plurality of third transfer electrodes are located is located on a side of the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located away from the base substrate, the first insulating layer is located between the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located, and the second insulating layer is located between the layer where the plurality of data lines are located and the layer where the plurality of third transfer electrodes are located;
  • the third transfer electrode is electrically connected to the third connection line through at least one first via hole penetrating the first insulating layer and the second insulating layer, and the third transfer electrode is electrically connected to the second data line through at least one second via hole penetrating the second insulating layer; the at least one first via hole and the at least one second via hole corresponding to the same third transfer electrode are arranged along the first direction.
  • the above array substrate provided by the embodiments of the present disclosure, it further includes a plurality of fourth connection lines and a plurality of fifth connection lines, wherein the plurality of fourth connection lines are in the same layer as the plurality of gate lines, and the plurality of fifth connection lines are in the same layer as the plurality of data lines;
  • the second frame area also includes a wiring area between the binding area and the second display area;
  • the multiple data lines include a third data line and a fourth data line that are alternately arranged, the third data line extends from the first display area and the second display area to the routing area and is connected to the binding area via the fourth connecting line, and the fourth data line extends from the first display area and the second display area to the routing area and is connected to the binding area via the fifth connecting line.
  • the orthographic projection of the fourth connecting line on the base substrate at least partially overlaps with the orthographic projection of the fifth connecting line on the base substrate.
  • the array substrate provided in the embodiments of the present disclosure further includes a plurality of fourth transfer electrodes, a plurality of fifth transfer electrodes, a first insulating layer and a second insulating layer, wherein the plurality of fourth transfer electrodes and the plurality of fifth transfer electrodes are arranged in the same layer on the layer where the plurality of gate lines are located and on a side of the layer where the plurality of data lines are located away from the base substrate, the first insulating layer is located between the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located, and the second insulating layer is located between the layer where the plurality of data lines are located and the layer where the plurality of fourth transfer electrodes are located;
  • the fourth transfer electrode is electrically connected to the fourth connection line through at least one third via hole penetrating the first insulating layer and the second insulating layer, and the fourth transfer electrode is electrically connected to the third data line through at least one fourth via hole penetrating the second insulating layer; the at least one third via hole and the at least one fourth via hole corresponding to the same fourth transfer electrode are respectively arranged along the second direction;
  • the fifth transfer electrode is electrically connected to the fifth connection line through at least one fifth via hole penetrating the second insulating layer, and the fifth transfer electrode is electrically connected to the fourth data line through at least one sixth via hole penetrating the second insulating layer; the at least one fifth via hole and the at least one sixth via hole corresponding to the same fifth transfer electrode are respectively arranged along the second direction.
  • the first data line includes a first data line section located in the non-rectangular area, and a second data line section located in the routing area, the sum of the line width of the first data line section and the line distance of the adjacent first data line section is the fourth distance, the sum of the line width of the second data line section and the line distance of the adjacent second data line section is the fifth distance, and the ratio of the first distance to the second distance is greater than 1 and less than or equal to 1.5.
  • the second antistatic structure extends in a direction and has an acute angle with the first direction, or the second antistatic structure extends along an arc with an arc angle of 110° to 180°.
  • the first display area includes a first sub-display area arranged in contact with the second display area, and a second sub-display area located on a side of the first sub-display area away from the second display area;
  • the first frame area includes a first sub-frame area arranged side by side with the first sub-display area in the second direction, and a second sub-frame area arranged side by side with the second sub-display area in the second direction, and the second sub-frame area and the second sub-display area have a stepped boundary line;
  • the first anti-static structures in the first sub-frame area are arranged side by side along the first direction, and the first anti-static structures in the second sub-frame area are arranged at the steps of the stepped boundary line.
  • an embodiment of the present disclosure further provides a display device, the array substrate provided by the embodiment of the present disclosure, and a driving chip, wherein the driving chip is electrically connected to the plurality of gate lines and the plurality of data lines.
  • FIG1 is a schematic diagram of an array substrate provided in an embodiment of the present disclosure.
  • FIG2 is another schematic diagram of an array substrate provided in an embodiment of the present disclosure.
  • FIG3 is another schematic diagram of an array substrate provided in an embodiment of the present disclosure.
  • FIG4 is an enlarged structural schematic diagram of area a in FIG2 ;
  • FIG5 is an enlarged structural schematic diagram of area b in FIG2;
  • FIG6 is an enlarged schematic diagram of the structure of region c in FIG2 ;
  • FIG7 is a schematic diagram of an arrangement of a second anti-static structure provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of another arrangement of the second anti-static structure provided in an embodiment of the present disclosure.
  • FIG9 is an enlarged structural schematic diagram of area d in FIG2 ;
  • FIG10 is a schematic diagram of the enlarged structure of the region e in FIG2 ;
  • FIG11 is a schematic diagram of the enlarged structure of the f region in FIG10 ;
  • FIG12 is a schematic diagram of the enlarged structure of the g area in FIG10;
  • FIG13 is a schematic diagram of the enlarged structure of the h area in FIG6;
  • FIG14 is an equivalent circuit diagram of an antistatic structure provided in an embodiment of the present disclosure.
  • FIG15a is a schematic diagram of an enlarged structure of region i in FIG10;
  • FIG15b is another enlarged structural schematic diagram of the region i in FIG10;
  • FIG16a is a schematic diagram of an enlarged structure of the j area in FIG10;
  • FIG16b is another enlarged structural schematic diagram of the j region in FIG10;
  • FIG17a is a schematic diagram of an enlarged structure of the k region in FIG10;
  • FIG17b is another enlarged structural schematic diagram of the k region in FIG10;
  • FIG18 is an enlarged structural schematic diagram of area 1 in FIG10;
  • FIG19 is a cross-sectional view along line I-II in FIG18;
  • FIG20 is a schematic diagram of the enlarged structure of the m region in FIG10;
  • FIG21 is a schematic diagram of the enlarged structure of the n region in FIG10;
  • FIG22 is a schematic diagram of the enlarged structure of the o area in FIG10;
  • FIG23 is a schematic diagram of the enlarged structure of the p region in FIG10;
  • FIG24 is a schematic diagram of the enlarged structure of the q region in FIG10;
  • FIG. 25 is a schematic diagram of a display device provided in an embodiment of the present disclosure.
  • LCD liquid crystal display
  • GAA gate drive circuit
  • IC driver chip
  • Gateway gate lead
  • the gate lead drive scheme is different from the gate drive circuit scheme.
  • the difference is that in the gate drive circuit scheme, the size of each shift register is the same, while in the gate lead drive scheme, as the distance from the driver chip decreases, the space occupied by the gate lead wiring becomes larger and larger.
  • the wiring space required for the data line is also larger the closer to the driver chip. Therefore, in the rounded corner area close to the driver chip of the special-shaped display product using the gate lead (Gateway) drive scheme, the fanout line occupies a large space, which is not conducive to achieving a narrow frame.
  • an array substrate provided in an embodiment of the present disclosure includes:
  • a base substrate 101 includes a display area AA and a frame area BB surrounding the display area AA, wherein the display area AA includes a first display area AA 1 and a second display area AA 2 sequentially arranged along a first direction Y, and the second display area AA 2 is a non-rectangular display area;
  • the frame area BB includes a first frame area BB 1 surrounding the first display area AA 1 , and a second frame area BB 2 surrounding the second display area AA 2 ; in the present disclosure, “surrounding” can be understood as full surrounding or partial surrounding, and is not specifically limited here;
  • a plurality of gate lines 102 are arranged along a first direction Y in the first display area AA 1 and the second display area AA 2 and extend along a second direction X, and the gate lines 102 of the first display area AA 1 extend to the first frame area BB 1 , and the gate lines 102 of the second display area AA 2 extend to the second frame area BB 2 , and the second direction X intersects the first direction Y;
  • the plurality of data lines 103 are insulated from the plurality of gate lines 102, and the plurality of data lines 103 are arranged along the second direction X in the first display area AA 1 and the second display area AA 2 and extend along the first direction Y, and the plurality of data lines 103 extend to the second frame area BB 2 and are arranged around the second display area AA 2 in the second frame area BB 2 ;
  • Multiple anti-static structures 104 are electrically connected to multiple gate lines 102, and the multiple anti-static structures 104 include multiple first anti-static structures 1041 located in the first border area BB 1 , and multiple second anti-static structures 1042 located in the second border area BB 2 , wherein at least part of the first anti-static structures 1041 extend along the first direction Y, and at least part of the second anti-static structures 1042 extend along the winding direction of the data line 103.
  • a plurality of data lines 103 extend to the second frame area BB 2 and are arranged in the second display area AA 2 in the second frame area BB 2 , so that the second frame area BB 2 is more difficult to be narrow frame than the first frame area BB 1.
  • the number of wirings in the first frame area BB 1 is small, there is enough space in the first frame area BB 1 for arranging the first antistatic structure 1041. Based on this, at least part of the first antistatic structure 1041 in the first frame area BB 1 can be extended along the first direction Y; when the first antistatic structure 1041 is extended in the first direction Y, it is more convenient to complete the design and manufacture of the first antistatic structure 1041.
  • the extension direction of the second antistatic structure 1042 may be substantially parallel (for example, within an angle range of 5°) or parallel to the winding direction of the data line 103.
  • the winding direction of the data line 103 forms an acute angle ⁇ with the first direction Y, and accordingly, the second antistatic structure 1042 extends in a directional manner and the angle with the first direction Y is an acute angle ⁇ ; or, as shown in FIG8 , the winding direction of the data line 103 is an arc extension direction of 110° to 180°, and accordingly, the second antistatic structure 1042 extends along an arc with an arc angle ⁇ of 110° to 180°.
  • the first display area AA1 includes a first sub-display area AA11 arranged in contact with the second display area AA2 , and a second sub-display area AA12 located on the side of the first sub-display area AA11 away from the second display area AA2
  • the second sub-display area AA12 is a non-rectangular display area symmetrical with the second display area AA2 about the symmetry axis MN extending along the second direction X of the display area AA, optionally, in the direction away from the first sub-display area AA11 , the width of the second sub-display area AA12 along the second direction X gradually decreases
  • the first border area BB1 includes a first sub-border area BB11 arranged side by side with the first sub-display area AA11 in the second direction X, and a second sub-border area BB12
  • the first antistatic structure 1041 in the first sub-border area BB11 can be arranged side by side along the first direction Y, and the first antistatic structure 1041 in the second sub-border area BB12 can be arranged at the step of the stepped boundary line.
  • the distances between two adjacent first antistatic structures 1041 in the first direction Y and the second direction X are d1 and d2 , respectively.
  • the distance d1 between two adjacent first antistatic structures 1041 in the first direction Y may be substantially equal to (i.e., equal to or within a reasonable error range caused by factors such as manufacturing and measurement) the sum d3 of the lengths of the two pixels in the first direction Y (which may be equivalent to the sum of the lengths of the two pixel electrodes in the first direction Y), and the distance d2 between two adjacent first antistatic structures 1041 in the second direction X may be substantially equal to (i.e., equal to or within a reasonable error range caused by factors such as manufacturing and measurement) the sum d3 of the widths of the two pixels in the second direction X (which may be equivalent to the sum of the widths of the six pixel electrodes in the second direction X when a single pixel includes three sub-pixels).
  • At least part of the gate line 102 is electrically connected to the anti-static structure 104 after being bent in the first border area BB1 and the second border area BB2 , so that the electrostatic current on the gate line 102 flows smoothly, thereby improving the anti-static capability.
  • the antistatic structure 104 electrically connected to two adjacent gate lines 102 can be separated on both sides of the display area AA.
  • the first frame area BB1 on both sides of the display area AA can be made narrower, which is conducive to realizing the narrow frame of the first frame area BB1 .
  • a plurality of first floating anti-static structures 106 and a plurality of second floating anti-static structures 107 may also be included, wherein the plurality of first floating anti-static structures 106 are electrically connected to the plurality of first anti-static structures 1041 in the first border area BB 1 , and the plurality of first floating anti-static structures 106 are arranged side by side with the two first anti-static structures 1041 farthest from the second border area BB 2 in the first border area BB 1 (equivalent to the first anti-static structures 1041 electrically connected to the first two gate lines 102 in the direction from the first display area AA 1 to the second display area AA 2 ) in the second direction X; the second floating anti-static structure 107 is electrically connected to the plurality of second anti-static structures 1042 in the second border area BB 2 , and the plurality of second floating anti-static structures 107 are
  • first floating anti-static structure 106 and the second floating anti-static structure 107 By setting the first floating anti-static structure 106 and the second floating anti-static structure 107, a large current can be quickly evacuated when static electricity occurs, thereby preventing static electricity from damaging the product; and, since the first floating anti-static structure 106 and the second floating anti-static structure 107 are arranged in the second sub-frame area BB 12 and the second frame area BB 2 with relatively large wiring space on the left and right sides of the second sub-display area AA 12 and the second display area AA 2 , compared with setting the first floating anti-static structure 106 and the second floating anti-static structure 107 in the first sub-frame area BB 11 with relatively small wiring space on the left and right sides of the first sub-display area BB 11 , it is more conducive to making the overall width of the frame area BB smaller.
  • a short-circuit ring 108 may also be included.
  • the short-circuit ring 108 is located in the first border area BB 1 and the second border area BB 2 , and can be set in the same layer as the data line 103; multiple anti-static structures 104 can be electrically connected to multiple first floating anti-static structures 106 and multiple second floating anti-static structures 107 through the short-circuit ring 108, so that static electricity is dispersed to the anti-static structure 104, the first floating anti-static structure 106 and the second floating anti-static structure 107 through the short-circuit ring 108, thereby improving the anti-static ability of the product.
  • “same layer” refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.
  • the present disclosure further provides a common electrode line 109 and a common electrode 110, wherein the common electrode line 109 is located in the first frame area BB 1 and the second frame area BB 2 , and can be attached to the boundary winding of the display area AA in the first frame area BB 1 and the second frame area BB 2.
  • the common electrode line 109 and the data line 103 are arranged in the same layer, and can optionally be the same layer of material.
  • the same layer includes the same layer and the same material, and can also be different materials in the same layer, which is not limited here;
  • the common electrode 110 extends from the first display area AA 1 and the second display area AA 2 to the first frame area BB 1 and the second frame area BB 2 , so as to be electrically connected to the common electrode line 109.
  • multiple first floating anti-static structures 106 are electrically connected to the common electrode line 109
  • multiple second floating anti-static structures 107 are electrically connected to the common electrode 110, so that the anti-static structure 104 can be connected to the common electrode line 109 and the common electrode 110 through the first floating anti-static structure 106, the second floating anti-static structure 107 and the short-circuit ring 108.
  • the short-circuit ring 108 can also be connected to the ground line (GND) through the first floating anti-static structure 106 and the second floating anti-static structure 107, which is not limited here.
  • the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 10 to 12, it can also include a first connecting line 111, which is arranged on the same layer as the multiple gate lines 102, and the first connecting line 111 is used to connect the second floating anti-static structure 107 and the common electrode 110; optionally, the first connecting line 111 is arranged on the same layer and with the same material as the multiple gate lines 102.
  • the second frame area BB 2 includes a binding area BB 21 extending approximately along the second direction X on the side of the second display area AA 2 away from the first display area AA 1 , a non-rectangular area BB 22 connecting the binding area BB 21 and the first frame area BB 1 , and a routing area BB 23 between the binding area BB 21 and the second display area AA 2 , wherein the function of the binding area BB 21 is to bind the signal lines of the display panel (such as the gate lines 102, the data lines 103, etc.) to the flexible circuit board or the circuit after extending to the binding area BB 21 , so as to provide display signals to the signal lines of the display panel; and as can be seen from FIG.
  • the array substrate also includes a second connecting line 112, the second connecting line 112 is in the same layer as the plurality of gate lines 102 (optionally in the same layer and the same material), and the second connecting line 112 is connected between the common electrode line 109 and the binding area BB 21 , so as to connect the binding area BB 21 to the data line 103 through the second connecting line 112.
  • the common electrode signal output by the driving chip of the second connecting line 112 is provided to the common electrode line 109.
  • the second connecting line 112 includes a widened portion W, the widened portion W is arranged adjacent to the connection between the wiring area BB 23 and the non-rectangular area BB 22 , and the widened portion W is a grid-like structure.
  • the widened portion W of the grid-like structure has good light transmittance, which is conducive to enhancing the curing effect of light (such as ultraviolet light) on the frame sealing glue.
  • the multiple gate leads 113 can also include multiple gate leads 113, which are electrically connected to the multiple anti-static structures 104 on the side of the multiple anti-static structures 104 away from the first display area AA 1 and the second display area AA 2 , and only part of the gate leads 113 extends from the second frame area BB 2 to the first frame area BB 1 ;
  • the multiple gate leads 113 include multiple first gate leads 1131 and multiple second gate leads 1132, the multiple first gate leads 1131 are in the same layer with the multiple gate lines 102, the multiple second gate leads 1132 are in the same layer with the multiple data lines 103, and the orthographic projection of the first gate leads 1131 on the base substrate 101 overlaps with the orthographic projection of the second gate leads 1132 on the base substrate 101 to a maximum extent.
  • the signal on the gate lead 113 can be ⁇ 12V and the gate lead 113 is relatively long, if the orthographic projection of the first gate lead 1131 overlaps with the orthographic projection of the second gate lead 1132, a parasitic capacitance will be formed between the first gate lead 1131 and the second gate lead 1132, causing mutual interference.
  • the orthographic projection of the first gate lead 1131 on the substrate 101 and the orthographic projection of the second gate lead 1132 on the substrate 101 are arranged to overlap at most parts; optionally, under the premise that the wiring space permits, the orthographic projection of the first gate lead 1131 on the substrate 101 and the orthographic projection of the second gate lead 1132 on the substrate 101 can be arranged not to overlap with each other (that is, staggered with each other), and the orthographic projection of the first gate lead 1131 on the substrate 101 and the orthographic projection of the second gate lead 1132 on the substrate 101 can be arranged alternately, as shown in Figures 15b, 16b and 17b.
  • the anti-static structure 104 includes a first transistor T1 and a second transistor T2 , wherein the gate GT1 of the first transistor T1 is electrically connected to the gate line 102 and the gate lead 113 respectively, the first electrode ST1 of the first transistor T1 is electrically connected to the gate GT1 of the first transistor T1 , the second electrode DT1 of the first transistor T1 is integrally arranged with the first electrode ST2 of the second transistor T2 , the second electrode DT2 of the second transistor T2 is integrally arranged with the first electrode ST1 of the first transistor T1 , and the gate GT2 of the second transistor T2 is electrically connected to the first electrode ST2 of the second transistor T2 and the short-circuit ring 108.
  • the first transistor T1 When there is a lot of static electricity on the gate line 102, the first transistor T1 is turned on to guide the static electricity to the short-circuit ring 108 and then output it to the common electrode line 109 for release; when there is a lot of static electricity on the short-circuit ring 108, on the one hand, the static electricity can be directly released to the common electrode line 109, and on the other hand, the second transistor T2 is turned on to disperse the static electricity to the gate line 102 and the gate lead 113. In this way, the first transistor T1 and the second transistor T2 can effectively avoid excessive concentration of static electricity, thereby improving the anti-static effect.
  • the extension direction of the anti-static structure 104 in the present disclosure can be understood as the extension direction of the active layer of the transistor (in the extension direction of the active layer, the length of the active layer is longer), that is, the first anti-static structure 1041 extends along the first direction Y, which is equivalent to the active layer AT1 of the first transistor T1 and the active layer AT2 of the second transistor T2 extending along the first direction Y, and the second anti-static structure 1042 extends along the winding direction of the data line 103, which is equivalent to the active layer AT1 of the first transistor T1 and the active layer AT2 of the second transistor T2 extending along the winding direction of the data line 103.
  • first floating anti-static structure 106 and the second floating anti-static structure 107 in the present disclosure may also include a first transistor T1 and a second transistor T2 , but the difference from the anti-static structure 104 is that in the first floating anti-static structure 106 and the second floating anti-static structure 107, the gate GT1 of the first transistor T1 is electrically connected to the common electrode line 109.
  • first transistor T1 and the second transistor T2 in the present disclosure may be bottom-gate transistors, that is, the layer where the gate is located is located between the active layer and the base substrate 101; of course, in some embodiments, the first transistor T1 and the second transistor T2 may be top-gate transistors, that is, the active layer is located between the layer where the gate is located and the base substrate 101.
  • a plurality of first transfer electrodes 114 and a plurality of second transfer electrodes 115 may also be included.
  • the plurality of first transfer electrodes 114 and the plurality of second transfer electrodes 115 are arranged in the same layer on the layer where the plurality of gate lines 102 are located and the layer where the plurality of data lines 103 are located, on a side away from the base substrate 101; the gate GT1 of the first transistor T1 is electrically connected to the gate line 102 and the gate lead 113 respectively through the first transfer electrode 114, and the gate GT1 of the second transistor T2 is electrically connected to the first electrode ST2 of the second transistor T2 and the short-circuit ring 108 respectively through the second transfer electrode 115.
  • the transfer electrode may have the same width as the gate of the transistor and be wider than the gate line 102, for example, at least greater than or equal to 1.5 times the width of the gate line 102.
  • the gate lead 113 includes a first gate lead section G1 located in the non-rectangular area BB22 , a second gate lead section G2 located in the routing area BB23 , and a third gate lead section G3 connecting the first gate lead section G1 and the second gate lead section G2 ;
  • the sum of the line width of the first gate lead section G1 and the line spacing of the adjacent first gate lead section G1 in the same layer is a first distance P1
  • the sum of the line width of the second gate lead section G2 and the line spacing of the adjacent second gate lead section G2 in the same layer is a second distance P2
  • the sum of the line width of the third gate lead section G3 and the line spacing of the adjacent third gate lead section G3 in the same layer is a third distance P3
  • the second distance P2 is substantially the same as the third distance P3 , that is, the same or within an error range (e.g., ⁇ 5%) caused by factors such as manufacturing and measurement.
  • the first distance P1 is 6.5 ⁇ m, 7 ⁇ m, 7.5 ⁇ m, 8 ⁇ m, 8.5 ⁇ m, 9 ⁇ m, etc.
  • the second distance P2 is 6 ⁇ m, 6.1 ⁇ m, 6.2 ⁇ m, 6.3 ⁇ m, 6.4 ⁇ m, 6.5 ⁇ m, etc.
  • the wiring angles of the plurality of gate leads 113 in the non-rectangular area BB 22 are relatively large, compensation design is required to ensure that the line width uniformity of different gate leads 113 is good when the line width is small, and when the compensation angle is large, compensation errors are prone to occur, resulting in short circuit (Short) or open circuit (Open) defects in the product.
  • the second anti-static structure 1042 is provided in the present disclosure to extend along the winding direction of the data line 103, it is beneficial to reduce the space occupied by the second anti-static structure 1042, and the saved space can be used to increase the wiring size (pitch), increase the process margin (Margin), and avoid defects.
  • the wiring size (i.e., the first distance P1 ) of the first gate lead section G1 is increased in the present disclosure.
  • the wiring size of the first gate lead section G1 can be increased by increasing the line width of the first gate lead section G1 and/or the line spacing of adjacent first gate lead sections G1 on the same layer; illustratively, the line width of the first gate lead section G1 is increased from 3.7 ⁇ m to 4.8 ⁇ m, and the line spacing of adjacent first gate lead sections G1 on the same layer is increased from 2.5 ⁇ m to 3.2 ⁇ m.
  • a plurality of third connection lines 116 may also be included, and the plurality of third connection lines 116 are in the same layer as the plurality of gate lines 102;
  • the plurality of data lines 103 include first data lines 1031 and second data lines 1032 that are alternately arranged, the first data lines 1031 span the non-rectangular area BB 21 from the first display area AA 1 and the second display area AA 2 and extend to the binding area BB 21 , and the second data lines 1032 span the non-rectangular area BB 22 from the first display area AA 1 and the second display area AA 2 and are connected to the binding area BB 21 via the third connection lines 116.
  • the third connection lines 116 in the same layer as the gate lines 102 to transfer the second data lines 1032 to the binding area BB 21 , the total amount of wiring in the layer where the data lines 103 are located is reduced, which is conducive to the narrow frame design.
  • the orthographic projection of the third connection line 116 on the base substrate 101 at least partially overlaps with the orthographic projection of the adjacent first data line 1031 on the base substrate 101. Since the signal on the data line 103 is small, for example, ⁇ 5V, and the data line 103 is short, even if the orthographic projection of the first data line 1031 overlaps with the orthographic projection of the third connection line 116, no large parasitic capacitance will be generated between the two. Based on this, in the present disclosure, the orthographic projection of the third connection line 116 on the base substrate 101 can be set to at least partially overlap with the orthographic projection of the adjacent first data line 1031 on the base substrate 101.
  • the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in FIG. 18 and FIG. 19, it further includes a plurality of third transfer electrodes 117, a first insulating layer 118 and a second insulating layer 119, the layer where the plurality of third transfer electrodes 117 are located is located on the side of the layer where the plurality of gate lines 102 are located and the layer where the plurality of data lines 103 are located away from the base substrate 101, the first insulating layer 118 is located between the layer where the plurality of gate lines 102 are located and the layer where the plurality of data lines 103 are located, and the second insulating layer 119 is located between the layer where the plurality of data lines 103 are located and the layer where the plurality of third transfer electrodes 117 are located; and the third transfer electrode 117 is electrically connected to the third connection line 116 through at least one first via hole h1 penetrating the first insulating layer 118 and the second insulating layer 119
  • the multiple fourth connection lines 120 are in the same layer as the multiple gate lines 102, and the multiple fifth connection lines 121 are in the same layer as the multiple data lines 103;
  • the multiple data lines 103 include third data lines 1033 and fourth data lines 1034 that are alternately arranged, the third data lines 1033 extend from the first display area AA 1 and the second display area AA 2 to the routing area BB 23 and are connected to the binding area BB 21 through the fourth connection lines 120, and the fourth data lines 1034 extend from the first display area AA 1 and the second display area AA 2 to the routing area BB 23 and are connected to the binding area BB 21 through the fifth connection lines 121.
  • the wiring space of the routing area BB 23 is sufficient, so the third data line 1033 and the fourth data line 1034 can be connected to the binding area BB 21 by using the fourth connection line 120 and the fifth connection line 121.
  • the fourth connection line 120 on the same layer as the gate line 102 to transfer the third data line 1033 to the binding area BB 21 , the total amount of wiring on the layer where the data line 103 is located is reduced, which is conducive to the narrow frame design.
  • the orthographic projection of the fourth connection line 120 on the base substrate 101 overlaps with the orthographic projection of the fifth connection line 121 on the base substrate 101 at least partially. Since the fourth connection line 120 and the fifth connection line 121 transmit relatively small data signals, such as ⁇ 5V, and the fourth connection line 120 and the fifth connection line 121 are relatively short, even if the orthographic projection of the fourth connection line 120 overlaps with the orthographic projection of the fifth connection line 121, the two will not interfere with each other due to the large parasitic capacitance.
  • the orthographic projection of the fourth connection line 120 on the base substrate 101 can be set to overlap with the orthographic projection of the fifth connection line 121 on the base substrate 101 at least partially. And because the number of the fourth connection line 120 and the fifth connection line 121 is large, the wiring space can be reduced by overlapping the wiring of the two, which is conducive to the narrow frame design.
  • a plurality of fourth transfer electrodes 122 and a plurality of fifth transfer electrodes 123 may also be included.
  • the plurality of fourth transfer electrodes 122 and the plurality of fifth transfer electrodes 123 may be arranged in the same layer on the side of the layer where the plurality of gate lines 102 are located and the layer where the plurality of data lines 103 are located away from the base substrate 101; the fourth transfer electrode 122 is electrically connected to the fourth connection line 120 through at least one third via hole h3 penetrating the first insulating layer 118 and the second insulating layer 119, and the fourth transfer electrode 122 is electrically connected to the third data line 1033 through at least one fourth via hole h4 penetrating the second insulating layer 119; and since the wiring space of the routing area BB 23 is sufficient, the at least one third via hole h3 and the at least one fourth via hole h4 corresponding to the same
  • the fifth transfer electrode 123 is electrically connected to the fourth data line 1034 through at least one sixth via hole h5 penetrating the second insulating layer 119; and since the wiring space of the routing area BB 23 is sufficient, the at least one fifth via hole h5 and the at least one sixth via hole h6 corresponding to the same fifth transfer electrode 123 can be arranged along the second direction X respectively.
  • the first transfer electrode 114, the second transfer electrode 115, the third transfer electrode 117, the fourth transfer electrode 122 and the fifth transfer electrode 123 in the present disclosure can be arranged in the same layer, for example, each transfer electrode is arranged in the same layer as the common electrode 110.
  • the first via hole h1 and the third via hole h3 penetrating the first insulating layer 118 and the second insulating layer 119, and the second via hole h2 , the fourth via hole h4 , the fifth via hole h5 and the sixth via hole h6 penetrating the second insulating layer 119 can be formed by a single patterning process.
  • the first data line 1031 includes a first data line section S 1 located in the non-rectangular area BB 22 and a second data line section S 2 located in the routing area BB 23 , the sum of the line width of the first data line section S 1 and the line distance of the adjacent first data line section S 1 is a fourth distance P 4 , the sum of the line width of the second data line section S 2 and the line distance of the adjacent second data line section S 2 is a fifth distance P 5 , and the ratio of the fourth distance P 4 to the fifth distance P 5 is greater than 1 and less than or equal to 1.5.
  • the fourth distance P 4 is 6.5 ⁇ m, 7 ⁇ m, 7.5 ⁇ m, 8 ⁇ m, etc.
  • the fifth distance P 5 is 6 ⁇ m, 6.1 ⁇ m, 6.2 ⁇ m, 6.3 ⁇ m, 6.4 ⁇ m, etc.
  • the first data line section S 1 is distributed in oblique stripes, and the first data line sections S 1 on the left and right sides of the second display area AA 2 are tilted in the opposite direction.
  • the line width and line spacing of each first data line section S 1 are mutually balanced. When the line spacing is small, short circuit is prone to occur, and when the line width is small, open circuit is prone to occur.
  • the second anti-static structure 1042 is provided in the present disclosure to extend along the winding direction of the data line 103, it is beneficial to reduce the space occupied by the second anti-static structure 1042.
  • the saved space can be used to increase the wiring size (pitch), increase the process margin (Margin), and avoid defects.
  • the wiring size of the first data line section S 1 i.e., the fourth distance P 4
  • the wiring size of the first data line portion S1 can be increased by increasing the line width of the first data line portion S1 and/or the line spacing of the adjacent first gate lead portion G1 on the same layer; illustratively, the line width of the first data line portion S1 is increased from 3.3 ⁇ m to 4.2 ⁇ m, and the line spacing of the adjacent first data line portion S1 is increased from 2.7 ⁇ m to 2.8 ⁇ m.
  • a grounding line 124 may also be included.
  • the grounding line 124 is arranged in the same layer as the plurality of gate lines 102.
  • the grounding line 124 is located on the side of the plurality of gate leads 113 away from the plurality of anti-static structures 104, and a blank is arranged on the side of the grounding line 124 away from the plurality of gate leads 113.
  • the grounding line 124 is arranged at the outermost periphery of the frame area BB.
  • a common electrode line is also arranged outside the grounding line 124.
  • the common electrode line is saved in the present disclosure, so that the frame sealant can wrap all the wirings in the frame area BB in consideration of process fluctuations, and all the wirings in the frame area BB can be well protected, so as to avoid oxidation and other defects of all the wirings in the frame area BB.
  • the grounding line 124 can also prevent external static electricity from entering the display area AA, thereby achieving an anti-static effect.
  • the above-mentioned array substrate provided in the embodiments of the present disclosure also includes a plurality of floating blocks 125, and the plurality of floating blocks 125 are arranged on the same layer as the plurality of gate lines 102, and the plurality of floating blocks 125 are roughly evenly distributed between the ground line 124 and the plurality of gate leads 113, that is, the distribution density of the plurality of floating blocks 125 in the area between the ground line 124 and the plurality of gate leads 113 is the same or within a reasonable error range caused by factors such as manufacturing and measurement.
  • the supporting effect of the frame sealant in the area between the grounding wire 124 and the plurality of gate leads 113 is reduced; and since the number of wirings in the first border area BB1 is less than the number of wirings in the second border area BB2 , the supporting effect of the frame sealant in the first border area BB1 is not ideal.
  • the frame sealant can be effectively supported, and the floating blocks 125 can also play a certain anti-static role.
  • the above array substrate may also include a pixel electrode 126 located in the display area AA, a switch transistor 127 connecting the pixel electrode 126 and the data line 103, etc.;
  • the pixel electrode 126 is a block electrode at the pixel opening area, and the common electrode 110 has a slit at the pixel opening area.
  • the pixel electrode 126 is located between the first insulating layer 118 and the second insulating layer 119, and the common electrode 110 is located on the side of the second insulating layer 119 away from the base substrate 101.
  • Other essential components in the array substrate should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.
  • an embodiment of the present disclosure provides a display device, as shown in FIG. 25, including the above-mentioned array substrate 001 provided in the embodiment of the present disclosure, and a driver chip 002, which can be electrically connected to a plurality of gate lines 102 and a plurality of data lines 103.
  • the driver chip 002 is also electrically connected to the flexible circuit board 003.
  • the number of driver chips 002 can be one or more, which is not limited here. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned array substrate, the implementation of the display device can refer to the embodiment of the above-mentioned array substrate, and the repeated parts will not be repeated.
  • the display device may be a liquid crystal display screen.
  • the liquid crystal display screen may include a backlight module and a display panel located on the light-emitting side of the backlight module.
  • the display panel includes a display substrate and an opposing substrate disposed opposite to each other, a liquid crystal layer located between the display substrate and the opposing substrate, a sealant surrounding the liquid crystal layer between the display substrate and the opposing substrate, a first polarizer located on the side of the display substrate away from the liquid crystal layer, and a second polarizer located on the side of the opposing substrate away from the liquid crystal layer; wherein the polarization direction of the first polarizer is perpendicular to the polarization direction of the second polarizer;
  • the backlight module may be a direct-type backlight module or an edge-entry backlight module.
  • the edge-entry backlight module may include a light bar, a reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate.
  • the direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film, etc., which are stacked on the light-emitting side of the matrix light source, and the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source.
  • the lamp beads in the light strip and the lamp beads in the matrix light source can be light emitting diodes (LEDs), such as micro light emitting diodes (Mini LED, Micro LED, etc.).
  • Submillimeter or even micron-scale micro-LEDs are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting diodes is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare caused by traditional dynamic backlighting between bright and dark areas of the screen, optimizing the visual experience.
  • OLEDs organic light-emitting diodes
  • the above-mentioned display device may be any product or component with a display function, such as a smart watch, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a fitness wristband, a personal digital assistant, etc.
  • the display device may include, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip.
  • control chip is a central processing unit, a digital signal processor, a system chip (SoC), etc.
  • the control chip may also include a memory, and may also include a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc.
  • the control chip may also include a hardware circuit and a computer executable code, etc.
  • the hardware circuit may include a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, etc.
  • VLSI very large scale integration
  • the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure.
  • the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

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Abstract

本公开提供的阵列基板及显示装置，包括沿第一方向依次设置的第一显示区和非矩形的第二显示区，边框区包括包围第一显示区的第一边框区和包围第二显示区的第二边框区；多条栅线，在显示区内沿第一方向排列并沿第二方向延伸至边框区，第二方向与第一方向交叉；多条数据线，与多条栅线相互绝缘，多条数据线在显示区内沿第二方向排列并沿第一方向延伸至第二边框区，且在第二边框区内绕设于第二显示区；多个防静电结构，与多条栅线电连接，多个防静电结构包括位于第一边框区的多个第一防静电结构、以及位于第二边框区的多个第二防静电结构，至少部分第一防静电结构沿第一方向延伸，至少部分第二防静电结构沿数据线的绕设方向延伸。

Description

阵列基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
随着显示技术的飞速发展，显示面板除了传统的信息展示等作用外，为了更好的适应环境的整体结构和使用要求，在外形上的要求也在逐步提升，随之产生了异形显示面板。异形显示面板是在传统显示面板的基础上改造成的特殊形状的显示面板，以使显示面板的特点能更好的适应整体结构和环境。异形显示面板已经可以成功应用到诸如手表、眼镜或智能手环之类的可穿戴的电子设备上，并且常见的异形显示面板主要有扇形、弧形、圆形、圆柱形、多边形等形状。
发明内容
本公开实施例提供的阵列基板及显示装置，具体方案如下：
一方面，本公开实施例提供的一种阵列基板，包括：
衬底基板，所述衬底基板包括显示区和包围所述显示区的边框区，其中，所述显示区包括沿第一方向依次设置的第一显示区和第二显示区，所述第二显示区为非矩形显示区；所述边框区包括包围所述第一显示区的第一边框区，以及包围所述第二显示区的第二边框区；
多条栅线，在所述第一显示区和所述第二显示区内沿所述第一方向排列并沿第二方向延伸，且所述第一显示区的所述栅线延伸至所述第一边框区，所述第二显示区的所述栅线延伸至所述第二边框区，所述第二方向与所述第一方向交叉设置；
多条数据线，与所述多条栅线相互绝缘，所述多条数据线在所述第一显示区和所述第二显示区内沿所述第二方向排列并沿所述第一方向延伸，且所 述多条数据线延伸至所述第二边框区并在所述第二边框区内绕设于所述第二显示区设置；
多个防静电结构，与所述多条栅线电连接，所述多个防静电结构包括位于所述第一边框区的多个第一防静电结构、以及位于所述第二边框区的多个第二防静电结构，其中，至少部分所述第一防静电结构沿所述第一方向延伸，至少部分所述第二防静电结构沿所述数据线的绕设方向延伸。
在一些实施例中，在本公开实施例提供的上述阵列基板中，相邻两条所述栅线电连接的所述防静电结构分居在所述显示区的两侧。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括多个第一浮空防静电结构和多个第二浮空防静电结构，其中，所述多个第一浮空防静电结构在所述第一边框区与所述多个第一防静电结构电连接，且所述多个第一浮空防静电结构与所述第一边框区内距离所述第二边框区最远的两个所述第一防静电结构在所述第二方向上并排设置；所述第二浮空防静电结构在所述第二边框区与所述多个第二防静电结构电连接，且所述多个第二浮空防静电结构与所述第二边框区内距离所述第一边框区最远的两个所述第二防静电结构在所述数据线的绕设方向上并排设置。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括短路环，所述短路环位于所述第一边框区和所述第二边框区；
所述多个防静电结构通过所述短路环与所述多个第一浮空防静电结构、以及所述多个第二浮空防静电结构分别电连接。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括公共电极线和公共电极，其中，所述公共电极线位于所述第一边框区和所述第二边框区，所述公共电极自所述第一显示区和所述第二显示区延伸至所述第一边框区和所述第二边框区；
所述多个第一浮空防静电结构与所述公共电极线电连接，所述多个第二浮空防静电结构与所述公共电极电连接。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括第一 连接线，所述第一连接线与所述多条栅线同层，所述第一连接线连接所述第二浮空防静电结构与所述公共电极。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述短路环和所述公共电极线均与所述多条数据线同层。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述第二边框区包括在所述第二显示区远离所述第一显示区一侧大致沿第二方向延伸的绑定区，连接所述绑定区与所述第一边框区的非矩形区，以及位于所述绑定区与所述第二显示区之间的走线区；
所述阵列基板还包括第二连接线，所述第二连接线与所述多条栅线同层，所述第二连接线连接在所述公共电极线与所述绑定区之间，所述第二连接线包括加宽部，所述加宽部邻近所述走线区与所述非矩形区的连接处设置，且所述加宽部为网格状结构。
在一些实施例中，在本公开实施例提供的上述阵列基板中，至少部分所述栅线在所述第一边框区和所述第二边框区弯折后与所述防静电结构电连接。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括多条栅引线，所述多条栅引线在所述多个防静电结构远离所述第一显示区与所述第二显示区的一侧与所述多个防静电结构电连接；
所述多条栅引线包括多条第一栅引线和多条第二栅引线，所述多条第一栅引线与所述多条栅线同层，所述多条第二栅引线与所述多条数据线同层。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述防静电结构包括第一晶体管和第二晶体管，其中，所述第一晶体管的栅极与所述栅线、以及所述栅引线分别电连接，所述第一晶体管的第一极与所述第一晶体管的栅极电连接，所述第一晶体管的第二极与所述第二晶体管的第一极一体设置，所述第二晶体管的第二极与所述第一晶体管的第一极一体设置，所述第二晶体管的栅极与所述第二晶体管的第一极、以及所述短路环电连接。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括多个第一转接电极和多个第二转接电极，所述多个第一转接电极和所述多个第二 转接电极同层设置在所述多条栅线所在层、以及所述多条数据线所在层远离所述衬底基板的一侧；
所述第一晶体管的栅极通过所述第一转接电极与所述栅线、以及所述栅引线分别电连接，所述第二晶体管的栅极通过所述第二转接电极与所述第二晶体管的第一极、以及所述短路环分别电连接。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述第二边框区包括在所述第二显示区远离所述第一显示区一侧大致沿第二方向延伸的绑定区，连接所述绑定区与所述第一边框区的非矩形区，以及位于所述绑定区与所述第二显示区之间的走线区；
所述栅引线包括位于所述非矩形区的第一栅引线分部、位于所述走线区的第二栅引线分部、以及连接所述第一栅引线分部与所述第二栅引线分部的第三栅引线分部；所述第一栅引线分部的线宽与同层相邻所述第一栅引线分部的线距之和为第一距离，所述第二栅引线分部的线宽与同层相邻所述第二栅引线分部的线距之和为第二距离，所述第三栅引线分部的线宽与同层的相邻所述第三栅引线分部的线距之和为第三距离，所述第一距离与所述第二距离之比大于1且小于等于1.5。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括接地线，所述接地线与所述多条栅线同层设置，所述接地线位于所述多条栅引线远离所述多个防静电结构的一侧。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括多个浮空块，所述多个浮空块与所述多条栅线同层设置，且所述多个浮空块在所述接地线与所述多条栅引线之间大致均匀分布。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括多条第三连接线，所述多条第三连接线与所述多条栅线同层；
所述第二边框区包括在所述第二显示区远离所述第一显示区一侧大致沿第二方向延伸的绑定区，以及连接所述绑定区与所述第一边框区的非矩形区；
所述多条数据线包括交替设置的第一数据线和第二数据线，所述第一数 据线自所述第一显示区、所述第二显示区跨越所述非矩形区并延伸至所述绑定区，所述第二数据线自所述第一显示区、所述第二显示区跨越所述非矩形区并经所述第三连接线连接至所述绑定区。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述第三连接线在所述衬底基板上的正投影与相邻所述第一数据线在所述衬底基板上的正投影至少部分交叠。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括多个第三转接电极、第一绝缘层和第二绝缘层，所述多个第三转接电极所在层位于所述多条栅线所在层、以及所述多条数据线所在层远离所述衬底基板的一侧，所述第一绝缘层位于所述多条栅线所在层与所述多条数据线所在层之间，所述第二绝缘层位于所述多条数据线所在层与所述多个第三转接电极所在层之间；
所述第三转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的至少一个第一过孔与所述第三连接线电连接，所述第三转接电极通过贯穿所述第二绝缘层的至少一个第二过孔与所述第二数据线电连接；同一所述第三转接电极对应的所述至少一个第一过孔和所述至少一个第二过孔沿所述第一方向排列。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括多条第四连接线和多条第五连接线，所述多条第四连接线与所述多条栅线同层，所述多条第五连接线与所述多条数据线同层；
所述第二边框区还包括位于所述绑定区与所述第二显示区之间的走线区；
所述多条数据线包括交替设置的第三数据线和第四数据线，所述第三数据线自所述第一显示区、所述第二显示区延伸至所述走线区并经所述第四连接线连接至所述绑定区，所述第四数据线自所述第一显示区、所述第二显示区延伸至所述走线区并经所述第五连接线连接至所述绑定区。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述第四连接线在所述衬底基板上的正投影与所述第五连接线在所述衬底基板上的正投 影至少部分交叠。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括多个第四转接电极、多个第五转接电极、第一绝缘层和第二绝缘层，所述多个第四转接电极和所述多个第五转接电极同层设置在所述多条栅线所在层、以及所述多条数据线所在层远离所述衬底基板的一侧，所述第一绝缘层位于所述多条栅线所在层与所述多条数据线所在层之间，所述第二绝缘层位于所述多条数据线所在层与所述多个第四转接电极所在层之间；
所述第四转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的至少一个第三过孔与所述第四连接线电连接，所述第四转接电极通过贯穿所述第二绝缘层的至少一个第四过孔与所述第三数据线电连接；同一所述第四转接电极对应的所述至少一个第三过孔和所述至少一个第四过孔分别沿所述第二方向排列；
所述第五转接电极通过贯穿所述第二绝缘层的至少一个第五过孔与所述第五连接线电连接，所述第五转接电极通过贯穿所述第二绝缘层的至少一个第六过孔与所述第四数据线电连接；同一所述第五转接电极对应的所述至少一个第五过孔和所述至少一个第六过孔分别沿所述第二方向排列。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述第一数据线包括位于所述非矩形区的第一数据线分部、以及位于所述走线区的第二数据线分部，所述第一数据线分部的线宽与相邻所述第一数据线分部的线距之和为第四距离，所述第二数据线分部的线宽与相邻所述第二数据线分部的线距之和为第五距离，所述第一距离与所述第二距离之比大于1且小于等于1.5。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述第二防静电结构定向延伸且与所述第一方向的夹角为锐角，或者，所述第二防静电结构沿弧度为110°～180°的弧线延伸。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述第一显示区包括与所述第二显示区接触设置的第一子显示区、以及位于所述第一子 显示区远离所述第二显示区一侧的第二子显示区；
所述第一边框区包括在所述第二方向上与所述第一子显示区并排设置的第一子边框区，以及在所述第二方向上与所述第二子显示区并排设置的第二子边框区，所述第二子边框区与所述第二子显示区具有阶梯状交界线；
所述第一子边框区内的所述第一防静电结构沿所述第一方向并排设置，所述第二子边框区内的所述第一防静电结构设置在所述阶梯状交界线的台阶处。
另一方面，本公开实施例还提供了一种显示装置，本公开实施例提供的上述阵列基板，以及驱动芯片，所述驱动芯片与所述多条栅线、以及所述多条数据线电连接。
附图说明
图1为本公开实施例提供的阵列基板的一种示意图；
图2为本公开实施例提供的阵列基板的又一种示意图；
图3为本公开实施例提供的阵列基板的又一种示意图；
图4为图2中a区域的放大结构示意图；
图5为图2中b区域的放大结构示意图；
图6为图2中c区域的放大结构示意图；
图7为本公开实施例提供的第二防静电结构的一种排布示意图；
图8为本公开实施例提供的第二防静电结构的又一种排布示意图；
图9为图2中d区域的放大结构示意图；
图10为图2中e区域的放大结构示意图；
图11为图10中f区域的放大结构示意图；
图12为图10中g区域的放大结构示意图；
图13为图6中h区域的放大结构示意图；
图14为本公开实施例提供的防静电结构的等效电路图；
图15a为图10中i区域的一种放大结构示意图；
图15b为图10中i区域的又一种放大结构示意图；
图16a为图10中j区域的一种放大结构示意图；
图16b为图10中j区域的又一种放大结构示意图；
图17a为图10中k区域的一种放大结构示意图；
图17b为图10中k区域的又一种放大结构示意图；
图18为图10中l区域的放大结构示意图；
图19为沿图18中I-II线的截面图；
图20为图10中m区域的放大结构示意图；
图21为图10中n区域的放大结构示意图；
图22为图10中o区域的放大结构示意图；
图23为图10中p区域的放大结构示意图；
图24为图10中q区域的放大结构示意图；
图25为本公开实施例提供的显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并 非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在下面的描述中，当元件或层被称作“在”另一元件或层“上”或“连接到”另一元件或层时，该元件或层可以直接在所述另一元件或层上、直接连接到所述另一元件或层，或者可以存在中间元件或中间层。当元件或层被称作“设置于”另一元件或层“的一侧”时，该元件或层可以直接在所述另一元件或层的一侧，直接连接到所述另一元件或层，或者可以存在中间元件或中间层。然而，当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”另一元件或层时，不存在中间元件或中间层。术语“和/或”包括一个或更多个相关列出项的任意和全部组合。
显示行业发展迅速，行业内呈现多元化趋势；随着各类显示产品的崛起，液晶显示(LCD)产品地位受到冲击，为应对此变化，液晶显示行业不断挑战工艺极限。小尺寸产品一直以来对窄边框异形结构感兴趣，该需求对设计人员提出了挑战。
液晶显示产品的栅线驱动方式分为两种方案：其中一种方案是通过包括多个级联设置的移位寄存器的栅极驱动电路(GOA)进行驱动，具体表现为通过栅极驱动电路将驱动芯片(IC)输出的时序信号逐级提供给各行栅线；另一种方案为栅引线(Gateway)驱动，驱动芯片输出的时序信号由不同的栅引线直接提供给各行栅线。
栅引线驱动方案不同于栅极驱动电路方案，区别在于栅极驱动电路方案中每级移位寄存器的结构大小尺寸相同，而栅引线驱动方案中随着与驱动芯片距离的缩小，栅引线布线所占空间越来越大。而且在异形显示产品中靠近驱动芯片距的圆角(R角)区域内，数据线所需的布线空间也是越接近驱动芯片所占布线空间越大。因此采用栅引线(Gateway)驱动方案的异形显示产品距离驱动芯片较近的圆角区域内扇出线(fanout)占用空间大，不利于实现窄边框。
为了改善相关技术中存在的上述技术问题，本公开实施例提供的一种阵列基板，如图1至图6所示，包括：
衬底基板101，该衬底基板101包括显示区AA和包围显示区AA的边框区BB，其中，显示区AA包括沿第一方向Y依次设置的第一显示区AA 1和第二显示区AA 2，第二显示区AA 2为非矩形显示区；边框区BB包括包围第一显示区AA 1的第一边框区BB 1，以及包围第二显示区AA 2的第二边框区BB 2；本公开中“包围”可理解为全部包围或部分包围，在此不做具体限定；
多条栅线102，在第一显示区AA 1和第二显示区AA 2内沿第一方向Y排列并沿第二方向X延伸，且第一显示区AA 1的栅线102延伸至第一边框区BB 1，第二显示区AA 2的栅线102延伸至第二边框区BB 2，第二方向X与第一方向Y交叉设置；
多条数据线103，与多条栅线102相互绝缘，多条数据线103在第一显示区AA 1和第二显示区AA 2内沿第二方向X排列并沿第一方向Y延伸，且多条数据线103延伸至第二边框区BB 2并在第二边框区BB 2内绕设于第二显示区AA 2设置；
多个防静电结构104，与多条栅线102电连接，多个防静电结构104包括位于第一边框区BB 1的多个第一防静电结构1041、以及位于第二边框区BB 2的多个第二防静电结构1042，其中，至少部分第一防静电结构1041沿第一方向Y延伸，至少部分第二防静电结构1042沿数据线103的绕设方向延伸。
在本公开实施例提供的上述阵列基板中，多条数据线103延伸至第二边框区BB 2并在第二边框区BB 2内绕设于第二显示区AA 2设置，使得相较于第一边框区BB 1，第二边框区BB 2窄边框化的难度较大。通过将第二边框区BB 2内的至少部分第二防静电结构1042沿数据线103的绕设方向延伸设置，可以保证第二防静电结构1042所占用空间较小，从而可减小第二边框区BB 2，利于实现窄边框设计。同时由于第一边框区BB 1内的布线数量较少，因此，在第一边框区BB 1内有足够的空间用于布设第一防静电结构1041，基于此，可将第一边框区BB 1内的至少部分第一防静电结构1041沿第一方向Y延伸设置； 在第一防静电结构1041沿第一方向Y定向延伸的情况下，更便于完成第一防静电结构1041的设计与制作。
在一些实施例中，在本公开实施例提供的上述阵列基板中，第二防静电结构1042的延伸方向可以与数据线103的绕设方向大致平行(例如在5°的夹角范围内)或平行。示例性的，如图7所示，数据线103的绕设方向与第一方向Y成锐角α，相应地，第二防静电结构1042定向延伸且与第一方向Y的夹角为锐角α；或者，如图8所示，数据线103的绕设方向为110°～180°的弧线延伸方向，相应地，第二防静电结构1042沿弧度β为110°～180°的弧线延伸。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图1至图3所示，第一显示区AA 1包括与第二显示区AA 2接触设置的第一子显示区AA 11、以及位于第一子显示区AA 11远离第二显示区AA 2一侧的第二子显示区AA 12，第二子显示区AA 12为与第二显示区AA 2关于显示区AA沿第二方向X延伸的对称轴MN对称的非矩形显示区，可选地，在远离第一子显示区AA 11的方向上，第二子显示区AA 12沿第二方向X的宽度逐渐减小；第一边框区BB 1包括在第二方向X上与第一子显示区AA 11并排设置的第一子边框区BB 11，以及在第二方向X上与第二子显示区AA 12并排设置的第二子边框区BB 12，第二子边框区BB 12与第二子显示区AA 12具有阶梯状交界线。且参见图3至图5可知，为减小第一子边框区BB 11和第二子边框区BB 12的宽度，可以使得第一子边框区BB 11内的第一防静电结构1041沿第一方向Y并排设置，第二子边框区BB 12内的第一防静电结构1041设置在阶梯状交界线的台阶处。
继续参见图4可知，在第二子显示区AA 12单侧的第二子边框区BB 12内，相邻两个第一防静电结构1041在第一方向Y和第二方向X上的距离分别为d 1和d 2，在一些实施例中，相邻两个第一防静电结构1041在第一方向Y上的距离d 1可以大致等于(即等于或在因制作、测量等因素造成的合理误差范围内)两个像素在第一方向Y上的长度之和d 3(可以相当于2个像素电极在第一方向Y上的长度之和)，相邻两个第一防静电结构1041在第二方向X上的 距离d 2可以大致等于(即等于或在因制作、测量等因素造成的合理误差范围内)两个像素在第二方向X上的宽度之和d 3(在单个像素包括三个子像素的情况下，可以相当于6个像素电极在第二方向X上的宽度之和)。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图4至图6所示，至少部分栅线102在第一边框区BB 1和第二边框区BB 2弯折后与防静电结构104电连接，以使得栅线102上的静电电流平缓流动，提高防静电能力。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3所示，相邻两条栅线102电连接的防静电结构104可以分居在显示区AA的两侧。相较于防静电结构104在显示区AA的同侧设置的方案，通过将相邻两条栅线102电连接的防静电结构104分别设置在显示区AA的两侧，可使得显示区AA两侧的第一边框区BB 1均较窄，利于实现第一边框区BB 1的窄边框化。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3、图9至图11所示，还可以包括多个第一浮空防静电结构106和多个第二浮空防静电结构107，其中，多个第一浮空防静电结构106在第一边框区BB 1与多个第一防静电结构1041电连接，且多个第一浮空防静电结构106与第一边框区BB 1内距离第二边框区BB 2最远的两个第一防静电结构1041(相当于在由第一显示区AA 1指向第二显示区AA 2的方向上的前两条栅线102电连接的第一防静电结构1041)在第二方向X上并排设置；第二浮空防静电结构107在第二边框区BB 2与多个第二防静电结构1042电连接，且多个第二浮空防静电结构107与第二边框区BB 2内距离第一边框区BB 1最远的两个第二防静电结构1042(相当于在由第一显示区AA 1指向第二显示区AA 2的方向上的最后两条栅线102电连接的第二防静电结构1042)在数据线103的绕设方向上并排设置。通过设置第一浮空防静电结构106和第二浮空防静电结构107，可在发生静电时快速疏散大电流，起到防止静电损坏产品的效果；并且，由于第一浮空防静电结构106和第二浮空防静电结构107设置在第二子显示区AA 12和第二显示区AA 2左右两侧布线空间相对较大的第二子边框区BB 12和第二边框区 BB 2内，相较于将第一浮空防静电结构106和第二浮空防静电结构107设置在第一子显示区BB 11左右两侧布线空间相对较小的第一子边框区BB 11内，更利于使得边框区BB的整体宽度较小。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图4至图6、图9至图11所示，还可以包括短路环108，该短路环108位于第一边框区BB 1和第二边框区BB 2内，且可以与数据线103同层设置；多个防静电结构104可以通过短路环108与多个第一浮空防静电结构106、以及多个第二浮空防静电结构107分别电连接，从而通过短路环108将静电分散至防静电结构104、第一浮空防静电结构106和第二浮空防静电结构107上，提高产品的防静电能力。
需要说明的是，在本公开中，“同层”指的是采用同一成膜工艺形成用于制作特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而所形成层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形可能处于相同的高度或者具有相同的厚度、也可能处于不同的高度或者具有不同的厚度。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图4至图6，图9至图11所示，本公开还设置有公共电极线109和公共电极110，其中，公共电极线109位于第一边框区BB 1和第二边框区BB 2内，并可在第一边框区BB 1和第二边框区BB 2内依附于显示区AA的边界绕线，可选地，公共电极线109与数据线103同层设置，可选的可以是同层材料，本案中所有的是实施例中，涉及到同层即包括同层同材料，也可以是同层不同材料，在此不做限定；公共电极110自第一显示区AA 1和第二显示区AA 2内延伸至第一边框区BB 1和第二边框区BB 2内，以与公共电极线109电连接，可选地，多个第一浮空防静电结构106与公共电极线109电连接，多个第二浮空防静电结构107与公共电极110电连接，从而可通过第一浮空防静电结构106、第二浮空防静电结构107和短路环108将防静电结构104连接至公共电极线109和 公共电极110上，在发生静电时可引导大电流流向公共电极线109和公共电极110，起到防止静电损坏产品的效果。当然，在一些实施例中，也可以将短路环108通过第一浮空防静电结构106、第二浮空防静电结构107连接至接地线(GND)上，在此不做限定。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10至图12所示，还可以包括第一连接线111，该第一连接线111与多条栅线102同层设置，且第一连接线111用于连接第二浮空防静电结构107与公共电极110；可选的，第一连接线111与多条栅线102同层同材料设置。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图1至图3所示，第二边框区BB 2包括在第二显示区AA 2远离第一显示区AA 1一侧大致沿第二方向X延伸的绑定区BB 21，连接绑定区BB 21与第一边框区BB 1的非矩形区BB 22，以及绑定区BB 21与第二显示区AA 2之间的走线区BB 23，其中，绑定区BB 21的作用，是为了将显示面板的信号线(例如栅线102、数据线103等)在延伸至绑定区BB 21后与柔性电路板或者电路实现绑定，给显示面板的信号线提供显示信号；且由图10可见，阵列基板还包括第二连接线112，第二连接线112与多条栅线102同层(可选的同层同材料)，第二连接线112连接在公共电极线109与绑定区BB 21之间，以通过第二连接线112将绑定区BB 21的驱动芯片输出的公共电极信号提供给公共电极线109。可选地，第二连接线112包括加宽部W，加宽部W邻近走线区BB 23与非矩形区BB 22的连接处设置，且加宽部W为网格状结构，该网格状结构的加宽部W透光性较好，利于增强光线(例如紫外光)对封框胶的固化效果。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10、图15a、图15b、图16a、图16b、图17a和图17b所示，还可以包括多条栅引线113，这些栅引线113在多个防静电结构104远离第一显示区AA 1与第二显示区AA 2的一侧与多个防静电结构104电连接，并且仅部分栅引线113由第二边框区BB 2延伸至了第一边框区BB 1内；可选地，多条栅引线113包括多条第一栅引线1131和多条第二栅引线1132，多条第一栅引线1131与多条栅线 102同层，多条第二栅引线1132与多条数据线103同层，第一栅引线1131在衬底基板101上的正投影与第二栅引线1132在衬底基板101上的正投影至多部分交叠。由于栅引线113上的信号可为±12V，且栅引线113较长，若第一栅引线1131的正投影与第二栅引线1132的正投影相互交叠，则会使得第一栅引线1131与第二栅引线1132形成寄生电容而相互干扰。因此，本公开中为了减小第一栅引线1131与第二栅引线1132之间的寄生电容，设置了第一栅引线1131在衬底基板101上的正投影与第二栅引线1132在衬底基板101上的正投影至多部分交叠；可选地，在布线空间允许的前提下，可设置第一栅引线1131在衬底基板101上的正投影与第二栅引线1132在衬底基板101上的正投影互不交叠(即相互错开)，且第一栅引线1131在衬底基板101上的正投影与第二栅引线1132在衬底基板101上的正投影可以交替设置，如图15b、图16b和图17b所示。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10、图11、图13和图14所示，防静电结构104包括第一晶体管T 1和第二晶体管T 2，其中，第一晶体管T 1的栅极G T1与栅线102、以及栅引线113分别电连接，第一晶体管T 1的第一极S T1与第一晶体管T 1的栅极G T1电连接，第一晶体管T 1的第二极D T1与第二晶体管T 2的第一极S T2一体设置，第二晶体管T 2的第二极D T2与第一晶体管T 1的第一极S T1一体设置，第二晶体管T 2的栅极G T2与第二晶体管T 2的第一极S T2、以及短路环108电连接。当栅线102上的静电较多时，第一晶体管T 1打开，将静电引导至短路环108后输出至公共电极线109上进行释放；在短路环108上的静电较多时，一方面可以直接将静电释放至公共电极线109上，另一方面第二晶体管T 2打开，将静电分散至栅线102和栅引线113上。如此，通过第一晶体管T 1和第二晶体管T 2可以有效避免静电过于集中，从而提高防静电效果。
需要说明的时，在本公开中的防静电结构104包括第一晶体管T 1和第二晶体管T 2的情况下，本公开中防静电结构104的延伸方向可理解为是晶体管的有源层延伸方向(在有源层的延伸方向上，有源层的长度更长)，即第一防 静电结构1041沿第一方向Y延伸相当于是第一晶体管T 1的有源层A T1和第二晶体管T 2的有源层A T2沿第一方向Y延伸，第二防静电结构1042沿数据线103的绕设方向延伸相当于是第一晶体管T 1的有源层A T1和第二晶体管T 2的有源层A T2沿数据线103的绕设方向延伸。另外，本公开中第一浮空防静电结构106和第二浮空防静电结构107也可以包括第一晶体管T 1和第二晶体管T 2，但与防静电结构104的不同之处在于，在第一浮空防静电结构106和第二浮空防静电结构107中，第一晶体管T 1的栅极G T1与公共电极线109电连接。此外，本公开中第一晶体管T 1和第二晶体管T 2可以为底栅型晶体管，即栅极所在层位于有源层与衬底基板101之间；当然，在一些实施例中，第一晶体管T 1和第二晶体管T 2可以为顶栅型晶体管，即有源层位于栅极所在层与衬底基板101之间。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图13所示，还可以包括多个第一转接电极114和多个第二转接电极115，多个第一转接电极114和多个第二转接电极115同层设置在多条栅线102所在层、以及多条数据线103所在层远离衬底基板101的一侧；第一晶体管T 1的栅极G T1通过第一转接电极114与栅线102、以及栅引线113分别电连接，第二晶体管T 2的栅极G T1通过第二转接电极115与第二晶体管T 2的第一极S T2、以及短路环108分别电连接。在一些实施例中，转接电极可以和晶体管的栅极同宽度，且比栅线102更宽，例如至少大于等于栅线102宽度的1.5倍。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10、图15a、图15b、图16a、图16b、图17a和图17b所示，栅引线113包括位于非矩形区BB 22的第一栅引线分部G 1、位于走线区BB 23的第二栅引线分部G 2、以及连接第一栅引线分部G 1与第二栅引线分部G 2的第三栅引线分部G 3；第一栅引线分部G 1的线宽与同层相邻第一栅引线分部G 1的线距之和为第一距离P 1，第二栅引线分部G 2的线宽与同层相邻第二栅引线分部G 2的线距之和为第二距离P 2，第三栅引线分部G 3的线宽与同层的相邻第三栅引线分部G 3的线距之和为第三距离P 3，第一距离P 1与第二距离P 2之比大于1且小于等 于1.5，可选的，第二距离P 2与第三距离P 3大致相同，即相同或在因制作、测量等因素造成的误差范围(例如±5％)内。可选地，第一距离P 1为6.5μm、7μm、7.5μm、8μm、8.5μm、9μm等，第二距离P 2为6μm、6.1μm、6.2μm、6.3μm、6.4μm、6.5μm等。
由于多条栅引线113在非矩形区BB 22的布线角度较多，在线宽较小时需进行补偿设计以保证不同栅引线113的线宽均一性较好，而当补偿角度较多时易发生补偿错误导致产品出现短路(Short)或断路(Open)不良。考虑到本公开中设置第二防静电结构1042沿数据线103的绕设方向延伸，利于减小第二防静电结构1042占用的空间，节省出的空间可利用于布线尺寸(pitch)的增加，增大工艺裕量(Margin)，避免不良。基于此，本公开中增大了第一栅引线分部G 1的布线尺寸(即第一距离P 1)。在一些实施例中，可通过增大第一栅引线分部G 1的线宽和/或同层相邻第一栅引线分部G 1的线距来增大第一栅引线分部G 1的布线尺寸；示例性的，第一栅引线分部G 1的线宽由3.7μm增大至4.8μm，同层的相邻第一栅引线分部G 1的线距由2.5μm增大至3.2μm。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10和图18所示，还可以包括多条第三连接线116，多条第三连接线116与多条栅线102同层；多条数据线103包括交替设置的第一数据线1031和第二数据线1032，第一数据线1031自第一显示区AA 1、第二显示区AA 2跨越非矩形区BB 21并延伸至绑定区BB 21，第二数据线1032自第一显示区AA 1、第二显示区AA 2跨越非矩形区BB 22并经第三连接线116连接至绑定区BB 21。通过采用与栅线102同层的第三连接线116将第二数据线1032转接至绑定区BB 21，减少了数据线103所在层的布线总量，利于窄边框设计。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10和图18所示，第三连接线116在衬底基板101上的正投影与相邻第一数据线1031在衬底基板101上的正投影至少部分交叠。由于数据线103上的信号较小，例如可为±5V，且数据线103较短，因此即使第一数据线1031的正投影与第三连接线116的正投影相互交叠，二者之间也不会产生较大的寄生电容。基 于此，本公开中可以设置第三连接线116在衬底基板101上的正投影与相邻第一数据线1031在衬底基板101上的正投影至少部分交叠。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图18和图19所示，还包括多个第三转接电极117、第一绝缘层118和第二绝缘层119，多个第三转接电极117所在层位于多条栅线102所在层、以及多条数据线103所在层远离衬底基板101的一侧，第一绝缘层118位于多条栅线102所在层与多条数据线103所在层之间，第二绝缘层119位于多条数据线103所在层与多个第三转接电极117所在层之间；并且，第三转接电极117通过贯穿第一绝缘层118和第二绝缘层119的至少一个第一过孔h 1与第三连接线116电连接，第三转接电极117通过贯穿第二绝缘层119的至少一个第二过孔h 2与第二数据线1032电连接；同一第三转接电极117对应的至少一个第一过孔h 1和至少一个第二过孔h 2沿第一方向Y排列，以节约布线空间。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10和图20所示，还可以包括多条第四连接线120和多条第五连接线121，多条第四连接线120与多条栅线102同层，多条第五连接线121与多条数据线103同层；多条数据线103包括交替设置的第三数据线1033和第四数据线1034，第三数据线1033自第一显示区AA 1、第二显示区AA 2延伸至走线区BB 23并经第四连接线120连接至绑定区BB 21，第四数据线1034自第一显示区AA 1、第二显示区AA 2延伸至走线区BB 23并经第五连接线121连接至绑定区BB 21。走线区BB 23的布线空间充足，因此，可利用第四连接线120和第五连接线121分别将第三数据线1033和第四数据线1034连接至绑定区BB 21。并且通过采用与栅线102同层的第四连接线120将第三数据线1033转接至绑定区BB 21，减少了数据线103所在层的布线总量，利于窄边框设计。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10和图20所示，第四连接线120在衬底基板101上的正投影与第五连接线121在衬底基板101上的正投影至少部分交叠。由于第四连接线120和第五连接线121上传输的均是较小的数据信号，例如可为±5V，且第四连接线120和第五连 接线121较短，因此即使第四连接线120的正投影与第五连接线121的正投影相互交叠，二者之间也不会因寄生电容较大而相互干扰。基于此，本公开中可以设置第四连接线120在衬底基板101上的正投影与第五连接线121在衬底基板101上的正投影至少部分交叠。且因第四连接线120和第五连接线121的数量较多，通过使二者交叠布线可以减小布线空间，利于窄边框设计。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图20所示，还可以包括多个第四转接电极122和多个第五转接电极123，多个第四转接电极122和多个第五转接电极123可以同层设置在多条栅线102所在层、以及多条数据线103所在层远离衬底基板101的一侧；第四转接电极122通过贯穿第一绝缘层118和第二绝缘层119的至少一个第三过孔h 3与第四连接线120电连接，第四转接电极122通过贯穿第二绝缘层119的至少一个第四过孔h 4与第三数据线1033电连接；且由于走线区BB 23的布线空间充足，因此，同一第四转接电极122对应的至少一个第三过孔h 3和至少一个第四过孔h 4分别沿第二方向X排列；第五转接电极123通过贯穿第二绝缘层119的至少一个第五过孔h 5与第五连接线121电连接，第五转接电极123通过贯穿第二绝缘层119的至少一个第六过孔h 6与第四数据线1034电连接；且由于走线区BB 23的布线空间充足，因此，同一第五转接电极123对应的至少一个第五过孔h 5和至少一个第六过孔h 6可以分别沿第二方向X排列。
在一些实施例中，为减少膜层数量，节约构图次数，本公开中的第一转接电极114、第二转接电极115、第三转接电极117、第四转接电极122和第五转接电极123可以同层设置，例如，各转接电极与公共电极110同层设置。另外，可通过一次构图工艺形成贯穿第一绝缘层118和第二绝缘层119的第一过孔h 1和第三过孔h 3，以及贯穿第二绝缘层119的第二过孔h 2、第四过孔h 4、第五过孔h 5和第六过孔h 6。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10、图21至图23所示，第一数据线1031包括位于非矩形区BB 22的第一数据线分部S 1、以及位于走线区BB 23的第二数据线分部S 2，第一数据线分部S 1的线宽 与相邻第一数据线分部S 1的线距之和为第四距离P 4，第二数据线分部S 2的线宽与相邻第二数据线分部S 2的线距之和为第五距离P 5，第四距离P 4与第五距离P 5之比大于1且小于等于1.5。可选地，第四距离P 4为6.5μm、7μm、7.5μm、8μm等，第五距离P 5为6μm、6.1μm、6.2μm、6.3μm、6.4μm等。
由于需要从显示区AA引出栅线102跨越第一数据线分部S 1连接至防静电结构104上，因此第一数据线分部S 1呈斜向条纹分布，且第二显示区AA 2左右两侧的第一数据线分部S 1倾斜方向恰好相反。各条第一数据线分部S 1的线宽、线距相互制衡，当线距较小时，易发生短路，线宽较小时，易发生断路。考虑到本公开中设置第二防静电结构1042沿数据线103的绕设方向延伸，利于减小第二防静电结构1042占用的空间，节省出的空间可利用于布线尺寸(pitch)的增加，增大工艺裕量(Margin)，避免不良。基于此，本公开中增大了第一数据线分部S 1的布线尺寸(即第四距离P 4)。在一些实施例中，可通过增大第一数据线分部S 1的线宽和/或同层相邻第一栅引线分部G 1的线距来增大第一数据线分部S 1的布线尺寸；示例性的，第一数据线分部S 1的线宽由3.3μm增大至4.2μm，相邻第一数据线分部S 1的线距由2.7μm增大至2.8μm。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图10所示，还可以包括接地线124，接地线124与多条栅线102同层设置，接地线124位于多条栅引线113远离多个防静电结构104的一侧，且在接地线124远离多条栅引线113的一侧空白设置，换言之，接地线124是在边框区BB的最外围布线。相关技术中在接地线124之外还设置有一条公共电极线，本公开中节省了该条公共电极线，可以确保考虑工艺波动的情况下封框胶包裹边框区BB内的全部走线，对边框区BB内的全部走线实现较好的保护，避免边框区BB内的全部走线发生氧化等不良。并且，接地线124还可以防止外界静电进入显示区AA内，起到防静电效果。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图4和图5所示，还包括多个浮空块125，多个浮空块125与多条栅线102同层设置，且多个浮空块125在接地线124与多条栅引线113之间大致均匀分布，即多个 浮空块125在接地线124与多条栅引线113之间区域内的分布密度相同或在因制作、测量等因素造成的合理误差范围内。由于接地线124到最近一条栅引线113之间的距离大于相邻两条栅引线113之间的距离，会导致在接地线124与多条栅引线113之间区域内对降低封框胶的支撑效果；且由于第一边框区BB 1的布线数量小于第二边框区BB 2的布线数量内，导致第一边框区BB 1内对封框胶的支撑效果不理想，本公开中通过在接地线124与多条栅引线113之间区域内均匀布设浮空块125，可以有效支撑封框胶，同时浮空块125还可以起到一定的防静电作用。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图24所示，还可以包括位于显示区AA的像素电极126、连接像素电极126与数据线103的开关晶体管127等；可选地，像素电极126为在像素开口区处的块状电极，公共电极110在像素开口区处具有狭缝。可选地，像素电极126位于第一绝缘层118和第二绝缘层119之间，公共电极110位于第二绝缘层119远离衬底基板101的一侧。对于阵列基板中其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开实施例提供了一种显示装置，如图25所示，包括本公开实施例提供的上述阵列基板001，以及驱动芯片002，该驱动芯片002可与多条栅线102和多条数据线103电连接。在一些实施例中，驱动芯片002还与柔性电路板003电连接。可选地，驱动芯片002的数量可以为一个，也可以为多个，在此不做限定。由于该显示装置解决问题的原理与上述阵列基板解决问题的原理相似，因此，该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
在一些实施例中，本公开实施例提供的上述显示装置可以为液晶显示屏。该液晶显示屏可以包括背光模组、以及位于背光模组出光侧的显示面板。其中，显示面板包括相对而置的显示基板和对向基板，位于显示基板和对向基板之间的液晶层，在显示基板和对向基板之间包围液晶层的密封胶，位于显示基板远离液晶层一侧的第一偏光片、以及位于对向基板远离液晶层一侧的 第二偏光片等；其中，第一偏光片的偏振方向与第二偏光片的偏振方向相互垂直；背光模组可以为直下式背光模组，也可以为侧入式背光模组。可选地，侧入式背光模组可以包括灯条、层叠设置的反射片、导光板、扩散片、棱镜组等，灯条位于导光板厚度方向的一侧。直下式背光模组可以包括矩阵光源、在矩阵光源出光侧层叠设置的反射片、扩散板和增亮膜等，反射片包括与矩阵光源中各灯珠的位置正对设置的开孔。灯条中的灯珠、矩阵光源中的灯珠可以为发光二极管(LED)，例如微型发光二极管(Mini LED、Micro LED等)。
亚毫米量级甚至微米量级的微型发光二极管和有机发光二极管(OLED)一样属于自发光器件。其与有机发光二极管一样，有着高亮度、超低延迟、超大可视角度等一系列优势。并且由于无机发光二极管发光是基于性质更加稳定、电阻更低的金属半导体实现发光，因此它相比基于有机物实现发光的有机发光二极管来说，有着功耗更低、更耐高温和低温、使用寿命更长的优势。且在微型发光二极管作为背光源时，能够实现更精密的动态背光效果，在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区域之间造成的眩光现象，优化视觉体验。
在一些实施例中，本公开实施例提供的上述显示装置可以为：智能手表、投影仪、3D打印机、虚拟现实设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置可以包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结 构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (25)

  1. 一种阵列基板，其中，包括：
    衬底基板，所述衬底基板包括显示区和包围所述显示区的边框区，其中，所述显示区包括沿第一方向依次设置的第一显示区和第二显示区，所述第二显示区为非矩形显示区；所述边框区包括包围所述第一显示区的第一边框区，以及包围所述第二显示区的第二边框区；
    多条栅线，在所述第一显示区和所述第二显示区内沿所述第一方向排列并沿第二方向延伸，且所述第一显示区的所述栅线延伸至所述第一边框区，所述第二显示区的所述栅线延伸至所述第二边框区，所述第二方向与所述第一方向交叉设置；
    多条数据线，与所述多条栅线相互绝缘，所述多条数据线在所述第一显示区和所述第二显示区内沿所述第二方向排列并沿所述第一方向延伸，且所述多条数据线延伸至所述第二边框区并在所述第二边框区内绕设于所述第二显示区设置；
    多个防静电结构，与所述多条栅线电连接，所述多个防静电结构包括位于所述第一边框区的多个第一防静电结构、以及位于所述第二边框区的多个第二防静电结构，其中，至少部分所述第一防静电结构沿所述第一方向延伸，至少部分所述第二防静电结构沿所述数据线的绕设方向延伸。
  2. 如权利要求1所述的阵列基板，其中，相邻两条所述栅线电连接的所述防静电结构分居在所述显示区的两侧。
  3. 如权利要求2所述的阵列基板，其中，还包括多个第一浮空防静电结构和多个第二浮空防静电结构，其中，所述多个第一浮空防静电结构在所述第一边框区与所述多个第一防静电结构电连接，且所述多个第一浮空防静电结构与所述第一边框区内距离所述第二边框区最远的两个所述第一防静电结构在所述第二方向上并排设置；所述第二浮空防静电结构在所述第二边框区与所述多个第二防静电结构电连接，且所述多个第二浮空防静电结构与所述 第二边框区内距离所述第一边框区最远的两个所述第二防静电结构在所述数据线的绕设方向上并排设置。
  4. 如权利要求3所述的阵列基板，其中，还包括短路环，所述短路环位于所述第一边框区和所述第二边框区；
    所述多个防静电结构通过所述短路环与所述多个第一浮空防静电结构、以及所述多个第二浮空防静电结构分别电连接。
  5. 如权利要求4所述的阵列基板，其中，还包括公共电极线和公共电极，其中，所述公共电极线位于所述第一边框区和所述第二边框区，所述公共电极自所述第一显示区和所述第二显示区延伸至所述第一边框区和所述第二边框区；
    所述多个第一浮空防静电结构与所述公共电极线电连接，所述多个第二浮空防静电结构与所述公共电极电连接。
  6. 如权利要求5所述的阵列基板，其中，还包括第一连接线，所述第一连接线与所述多条栅线同层，所述第一连接线连接所述第二浮空防静电结构与所述公共电极。
  7. 如权利要求5或6所述的阵列基板，其中，所述短路环和所述公共电极线均与所述多条数据线同层。
  8. 如权利要求5～7任一项所述的阵列基板，其中，所述第二边框区包括在所述第二显示区远离所述第一显示区一侧大致沿第二方向延伸的绑定区，连接所述绑定区与所述第一边框区的非矩形区，以及位于所述绑定区与所述第二显示区之间的走线区；
    所述阵列基板还包括第二连接线，所述第二连接线与所述多条栅线同层，所述第二连接线连接在所述公共电极线与所述绑定区之间，所述第二连接线包括加宽部，所述加宽部邻近所述走线区与所述非矩形区的连接处设置，且所述加宽部为网格状结构。
  9. 如权利要求1～8任一项所述的阵列基板，其中，至少部分所述栅线在所述第一边框区和所述第二边框区弯折后与所述防静电结构电连接。
  10. 如权利要求4～8任一项所述的阵列基板，其中，还包括多条栅引线，所述多条栅引线在所述多个防静电结构远离所述第一显示区与所述第二显示区的一侧与所述多个防静电结构电连接；
    所述多条栅引线包括多条第一栅引线和多条第二栅引线，所述多条第一栅引线与所述多条栅线同层，所述多条第二栅引线与所述多条数据线同层。
  11. 如权利要求10所述的阵列基板，其中，所述防静电结构包括第一晶体管和第二晶体管，其中，所述第一晶体管的栅极与所述栅线、以及所述栅引线分别电连接，所述第一晶体管的第一极与所述第一晶体管的栅极电连接，所述第一晶体管的第二极与所述第二晶体管的第一极一体设置，所述第二晶体管的第二极与所述第一晶体管的第一极一体设置，所述第二晶体管的栅极与所述第二晶体管的第一极、以及所述短路环电连接。
  12. 如权利要求11所述的阵列基板，其中，还包括多个第一转接电极和多个第二转接电极，所述多个第一转接电极和所述多个第二转接电极同层设置在所述多条栅线所在层、以及所述多条数据线所在层远离所述衬底基板的一侧；
    所述第一晶体管的栅极通过所述第一转接电极与所述栅线、以及所述栅引线分别电连接，所述第二晶体管的栅极通过所述第二转接电极与所述第二晶体管的第一极、以及所述短路环分别电连接。
  13. 如权利要求10～12任一项所述的阵列基板，其中，所述第二边框区包括在所述第二显示区远离所述第一显示区一侧大致沿第二方向延伸的绑定区，以及连接所述绑定区与所述第一边框区的非矩形区；
    所述栅引线包括位于所述非矩形区的第一栅引线分部、位于所述绑定区与所述第二显示区之间的第二栅引线分部、以及连接所述第一栅引线分部与所述第二栅引线分部的第三栅引线分部；所述第一栅引线分部的线宽与同层相邻所述第一栅引线分部的线距之和为第一距离，所述第二栅引线分部的线宽与同层相邻所述第二栅引线分部的线距之和为第二距离，所述第三栅引线分部的线宽与同层的相邻所述第三栅引线分部的线距之和为第三距离，所述 第一距离与所述第二距离之比大于1且小于等于1.5。
  14. 如权利要求10～13任一项所述的阵列基板，其中，还包括接地线，所述接地线与所述多条栅线同层设置，所述接地线位于所述多条栅引线远离所述多个防静电结构的一侧。
  15. 如权利要求14所述的阵列基板，其中，还包括多个浮空块，所述多个浮空块与所述多条栅线同层设置，且所述多个浮空块在所述接地线与所述多条栅引线之间大致均匀分布。
  16. 如权利要求1～15任一项所述的阵列基板，其中，还包括多条第三连接线，所述多条第三连接线与所述多条栅线同层；
    所述第二边框区包括在所述第二显示区远离所述第一显示区一侧大致沿第二方向延伸的绑定区，以及连接所述绑定区与所述第一边框区的非矩形区；
    所述多条数据线包括交替设置的第一数据线和第二数据线，所述第一数据线自所述第一显示区、所述第二显示区跨越所述非矩形区并延伸至所述绑定区，所述第二数据线自所述第一显示区、所述第二显示区跨越所述非矩形区并经所述第三连接线连接至所述绑定区。
  17. 如权利要求16所述的阵列基板，其中，所述第三连接线在所述衬底基板上的正投影与相邻所述第一数据线在所述衬底基板上的正投影至少部分交叠。
  18. 如权利要求16或17所述的阵列基板，其中，还包括多个第三转接电极、第一绝缘层和第二绝缘层，所述多个第三转接电极所在层位于所述多条栅线所在层、以及所述多条数据线所在层远离所述衬底基板的一侧，所述第一绝缘层位于所述多条栅线所在层与所述多条数据线所在层之间，所述第二绝缘层位于所述多条数据线所在层与所述多个第三转接电极所在层之间；
    所述第三转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的至少一个第一过孔与所述第三连接线电连接，所述第三转接电极通过贯穿所述第二绝缘层的至少一个第二过孔与所述第二数据线电连接；同一所述第三转接电极对应的所述至少一个第一过孔和所述至少一个第二过孔沿所述第一方向排 列。
  19. 如权利要求16～18任一项所述的阵列基板，其中，还包括多条第四连接线和多条第五连接线，所述多条第四连接线与所述多条栅线同层，所述多条第五连接线与所述多条数据线同层；
    所述第二边框区还包括连接所述绑定区与所述第二显示区的走线区；
    所述多条数据线包括交替设置的第三数据线和第四数据线，所述第三数据线自所述第一显示区、所述第二显示区延伸至所述走线区并经所述第四连接线连接至所述绑定区，所述第四数据线自所述第一显示区、所述第二显示区延伸至所述走线区并经所述第五连接线连接至所述绑定区。
  20. 如权利要求19所述的阵列基板，其中，所述第四连接线在所述衬底基板上的正投影与所述第五连接线在所述衬底基板上的正投影至少部分交叠。
  21. 如权利要求19或20所述的阵列基板，其中，还包括多个第四转接电极、多个第五转接电极、第一绝缘层和第二绝缘层，所述多个第四转接电极和所述多个第五转接电极同层设置在所述多条栅线所在层、以及所述多条数据线所在层远离所述衬底基板的一侧，所述第一绝缘层位于所述多条栅线所在层与所述多条数据线所在层之间，所述第二绝缘层位于所述多条数据线所在层与所述多个第四转接电极所在层之间；
    所述第四转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的至少一个第三过孔与所述第四连接线电连接，所述第四转接电极通过贯穿所述第二绝缘层的至少一个第四过孔与所述第三数据线电连接；同一所述第四转接电极对应的所述至少一个第三过孔和所述至少一个第四过孔分别沿所述第二方向排列；
    所述第五转接电极通过贯穿所述第二绝缘层的至少一个第五过孔与所述第五连接线电连接，所述第五转接电极通过贯穿所述第二绝缘层的至少一个第六过孔与所述第四数据线电连接；同一所述第五转接电极对应的所述至少一个第五过孔和所述至少一个第六过孔分别沿所述第二方向排列。
  22. 如权利要求19～21任一项所述的阵列基板，其中，所述第一数据线 包括位于所述非矩形区的第一数据线分部、以及位于所述走线区的第二数据线分部，所述第一数据线分部的线宽与相邻所述第一数据线分部的线距之和为第四距离，所述第二数据线分部的线宽与相邻所述第二数据线分部的线距之和为第五距离，所述第一距离与所述第二距离之比大于1且小于等于1.5。
  23. 如权利要求1～22任一项所述的阵列基板，其中，所述第二防静电结构定向延伸且与所述第一方向的夹角为锐角，或者，所述第二防静电结构沿弧度为110°～180°的弧线延伸。
  24. 如权利要求1～23任一项所述的阵列基板，其中，所述第一显示区包括与所述第二显示区接触设置的第一子显示区、以及位于所述第一子显示区远离所述第二显示区一侧的第二子显示区；
    所述第一边框区包括在所述第二方向上与所述第一子显示区并排设置的第一子边框区，以及在所述第二方向上与所述第二子显示区并排设置的第二子边框区，所述第二子边框区与所述第二子显示区具有阶梯状交界线；
    所述第一子边框区内的所述第一防静电结构沿所述第一方向并排设置，所述第二子边框区内的所述第一防静电结构设置在所述阶梯状交界线的台阶处。
  25. 一种显示装置，其中，包括如权利要求1～24任一项所述的阵列基板，以及驱动芯片，所述驱动芯片与所述多条栅线、以及所述多条数据线电连接。
PCT/CN2022/134227 2022-11-25 2022-11-25 阵列基板及显示装置 WO2024108524A1 (zh)

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WO2022109874A1 (zh) * 2020-11-25 2022-06-02 京东方科技集团股份有限公司 显示面板和显示装置
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US20080048934A1 (en) * 2006-08-23 2008-02-28 Tsunenori Yamamoto Display device
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