WO2024168566A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

Info

Publication number
WO2024168566A1
WO2024168566A1 PCT/CN2023/076086 CN2023076086W WO2024168566A1 WO 2024168566 A1 WO2024168566 A1 WO 2024168566A1 CN 2023076086 W CN2023076086 W CN 2023076086W WO 2024168566 A1 WO2024168566 A1 WO 2024168566A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel electrode
line
common electrode
layer
array substrate
Prior art date
Application number
PCT/CN2023/076086
Other languages
English (en)
French (fr)
Inventor
程敏
刘家庆
戴珂
杨海鹏
郭磊
周茂秀
张春旭
姜晓婷
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2023/076086 priority Critical patent/WO2024168566A1/zh
Publication of WO2024168566A1 publication Critical patent/WO2024168566A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • CRT cathode ray tube display
  • TFT-LCD has been widely used in various large, medium and small sized products, covering almost all major electronic products in today's information society, such as LCD TV, high-definition digital TV, computer (desktop and notebook), mobile phone, tablet computer, navigation system, car display, projection display, video camera, digital camera, electronic watch, calculator, electronic instrument, meter, public display and virtual display, etc.
  • the array substrate and display device provided by the present disclosure are specifically described as follows:
  • an array substrate comprising:
  • a base substrate comprising a display area
  • a plurality of pixel electrode groups are arranged in an array in the display area, the pixel electrode groups include first pixel electrodes and second pixel electrodes, and the first pixel electrodes and the second pixel electrodes are alternately arranged in a row direction and a column direction respectively;
  • connection structures are located at the row gaps between the pixel electrode groups, and the connection structures are connected between the second pixel electrodes and the data lines;
  • a plurality of common electrode lines which penetrate through the column gaps in the pixel electrode group, and a first capacitor is provided between the common electrode lines and the connection structure;
  • the compensation structures are located in the row gaps between the pixel electrode groups.
  • the compensation structures are coupled to the first pixel electrodes, and there is a second capacitor between the compensation structures and the common electrode lines.
  • the second capacitor includes a three-layer conductive layer structure that overlaps each other perpendicular to the base substrate.
  • the above-mentioned array substrate provided by the embodiments of the present disclosure further includes a plurality of gate lines located on both sides of the pixel electrode groups in each row, and the three-layer conductive layer structure includes a first conductive structure arranged on the same layer as the pixel electrode groups, a second conductive structure arranged on the same layer as the gate lines, and a third conductive structure arranged on the same layer as the data lines.
  • the common electrode line includes a protrusion arranged to cross the column direction, and the protrusion and the compensation structure form the second capacitor.
  • the common electrode line includes a main body extending along a column direction, and the main body and the compensation structure form the second capacitor.
  • the common electrode line and the data line are arranged in the same layer
  • the array substrate also includes a common electrode whose orthographic projection overlaps with the pixel electrode group
  • the second capacitor also includes a fourth conductive part arranged in the same layer as the common electrode.
  • the array substrate provided in the embodiments of the present disclosure further includes a plurality of transistors located at the row gaps of the pixel electrode groups in each row, and the second capacitor also includes a semiconductor structure arranged in the same layer as the active layer of the transistor.
  • connection structure and the compensation structure are arranged on at least one same layer.
  • the data line in the array substrate provided by the embodiments of the present disclosure, includes a widened portion, and at least part of the widened portion is used to support a spacer;
  • the array substrate further includes a plurality of transistors located at the row gaps of the pixel electrode groups in each row. And a plurality of gate lines located on both sides of the pixel electrode group in each row, wherein the gate of the transistor is separated on both sides of the data line, the partial reuse of the gate line is the gate of the transistor, the first electrode of the transistor is coupled to the widened portion, and the orthographic projection of the first electrode of the transistor on the substrate overlaps with the orthographic projection of the gate of the transistor on the substrate.
  • the above-mentioned array substrate provided by the embodiments of the present disclosure further includes a plurality of first routing lines running through the column gaps within the pixel electrode group, the first routing lines being in the same layer as the active layer of the transistor and being arranged in overlapping contact with the common electrode line, the orthographic projection of the common electrode line on the base substrate being within the orthographic projection of the first routing line on the base substrate, and the distance between the orthographic projection of the first routing line on the base substrate and the orthographic projection of the adjacent first pixel electrode on the base substrate and the orthographic projection of the adjacent second pixel electrode on the base substrate being greater than or equal to 1 ⁇ m and less than or equal to 5 ⁇ m.
  • the above-mentioned array substrate provided by the embodiments of the present disclosure further includes a plurality of gate lines running through the row gaps between the pixel electrode groups, and a common electrode located in an area enclosed by the gate lines and the data lines, the common electrode including a plurality of slits, the orthographic projections of the slits on the base substrate overlap with the orthographic projections of the common electrode lines on the base substrate, the orthographic projections of the first pixel electrodes on the base substrate, and the orthographic projections of the second pixel electrodes on the base substrate, respectively.
  • the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a plurality of second routing lines running through the column gaps within the pixel electrode group, the second routing lines are integrally arranged with the common electrode, the second routing lines are coupled to the common electrode line, and the orthographic projection of the common electrode line on the base substrate exceeds the orthographic projection of the second routing lines on the base substrate by a distance greater than or equal to 0.5 ⁇ m and less than or equal to 2 ⁇ m on one side.
  • the array substrate provided in the embodiments of the present disclosure further includes a plurality of jumper wires located at the column gaps between the pixel electrode groups, and the jumper wires are integrally arranged with the common electrodes adjacent to each other in the same row.
  • the base substrate further includes a frame area surrounding the display area, and the frame area includes a first frame area opposite to the display area. and a second border area, and a third border area and a fourth border area opposite to each other, wherein the first border area includes a binding area for binding a circuit board, the third border area connects the first border area and the second border area, and the fourth border area connects the first border area and the second border area;
  • the array substrate also includes a gate driving circuit located in the third border area and/or the fourth border area, a plurality of gate lines located on both sides of each row of the pixel electrode groups, and a gate driving signal line connecting the circuit board and the gate driving circuit, wherein the gate driving signal line is arranged on the same layer as the gate line.
  • the gate drive signal line includes a low-level power line.
  • the array substrate provided in the embodiments of the present disclosure further includes a common electrode bus that at least partially surrounds the display area in the frame area and is arranged in the same layer as the gate line, a common electrode whose orthographic projection overlaps with the pixel electrode group, a transfer structure arranged in the same layer as the common electrode, a conductive structure integrally arranged with the gate line, and an insulating layer located between the layer where the gate line is located and the layer where the common electrode is located, wherein:
  • the common electrode bus includes a main line located in the third frame area and/or the fourth frame area, and a bump located on the side of the main line facing the display area, the bump is coupled to the common electrode through a first via hole penetrating the insulating layer, the transfer structure is coupled to the gate signal output end of the gate drive circuit through a second via hole penetrating the insulating layer, and is coupled to the conductive structure through a third via hole penetrating the insulating layer, and the first via hole is substantially flush with the second via hole and/or the third via hole in the column direction.
  • two gate lines are arranged at the row gaps between two adjacent rows of pixel electrode groups
  • the common electrode bus also includes a first branch line located in the first border area, and the distance between the first branch line and the adjacent gate line is approximately equal to the distance between the two gate lines at the row gaps between two adjacent rows of pixel electrode groups, and the structure of the first branch line is approximately the same as the structure of the gate line.
  • the common electrode bus further includes a second branch line located in the first border area, and the second branch line is located in the first border area.
  • the first branch line is spaced apart from the first branch line on a side away from the display area
  • the second branch line has a first distance from the nearest gate line, the sum of the width of the row gap of each row of the pixel electrode groups in the column direction and the length of the pixel electrode groups in the column direction is the second distance, and the first distance is 1/10 to 1/2 of the second distance.
  • the array substrate provided in the embodiments of the present disclosure further includes a dummy common electrode located between the first branch line and the second branch line, wherein the dummy common electrode is arranged on the same layer as the common electrode and is electrically connected to the common electrode bus.
  • an embodiment of the present disclosure provides a display device, including an array substrate and an opposing substrate in relative positions, and a liquid crystal layer located between the array substrate and the opposing substrate, and the array substrate is the above-mentioned array substrate provided in the embodiment of the present disclosure.
  • the array substrate includes a plurality of gate lines located on both sides of each row of the pixel electrode groups, and the orthographic projection of the data line on the base substrate has an overlapping area with the orthographic projection of the gate line on the base substrate;
  • the opposing substrate includes a plurality of spacers, the orthographic projections of the spacers on the base substrate are located within the orthographic projections of the widened portion on the base substrate, and the distance between the orthographic projections of the spacers on the base substrate and the overlapping area is greater than or equal to 10 ⁇ m and less than or equal to 20 ⁇ m.
  • the opposing substrate further includes a plurality of color resists, at least some of the color resists include a first island structure corresponding to the widened portion, and the first island structure is spaced apart from adjacent color resists.
  • At least part of the color resist includes a second island-shaped structure whose orthographic projection overlaps with the common electrode line, and the second island-shaped structure is arranged spaced apart from the adjacent color resist.
  • adjacent color resists overlap each other in a region outside the first island-shaped structure and the second island-shaped structure.
  • FIG1 is a schematic diagram of a pixel arrangement of a dual gate product in the related art
  • FIG2 is a schematic diagram of an array substrate provided in an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of the enlarged structure of the Z1 region in FIG2;
  • FIG4 is a schematic diagram of the enlarged structure of the Z2 region in FIG3;
  • FIG5 is a schematic diagram of the enlarged structure of the Z3 region in FIG4;
  • FIG6 is a schematic diagram of a second capacitor provided in an embodiment of the present disclosure.
  • FIG7 is a schematic structural diagram of the layer where the pixel electrode is located in FIG3;
  • FIG8 is a schematic diagram of the structure of the layer where the gate lines are located in FIG3;
  • FIG9 is a schematic diagram of the structure of the layer where the active layer is located in FIG3;
  • FIG10 is a schematic diagram of the structure of the layer where the data line is located in FIG3;
  • FIG11 is a schematic structural diagram of the insulating layer in FIG3 ;
  • FIG12 is a schematic diagram of the structure of the layer where the common electrode is located in FIG3;
  • FIG13 is a schematic diagram of the enlarged structure of the Z4 region in FIG3 ;
  • FIG14 is a schematic diagram of the enlarged structure of the Z5 region in FIG3 ;
  • FIG15 is an enlarged structural diagram of a layer where data lines and a layer where common electrodes are located in the Z6 region in FIG3;
  • FIG16 is a schematic diagram of the enlarged structure of the Z7 region in FIG2;
  • FIG17 is a schematic diagram of the structure of the layer where the gate lines are located in FIG16;
  • FIG18 is a schematic diagram of the structure of the layer where the data line is located in FIG16;
  • FIG19 is a schematic diagram of the structure of the insulating layer in FIG16;
  • FIG20 is a schematic diagram of the structure of the layer where the common electrode is located in FIG16;
  • FIG21 is a schematic diagram of a structure of a display device provided in an embodiment of the present disclosure.
  • FIG22 is a schematic diagram of a structure of a color resist provided in an embodiment of the present disclosure.
  • FIG23 is a schematic diagram of another structure of a color resist provided by an embodiment of the present disclosure.
  • FIG. 24 is another schematic diagram of the structure of the color resist provided in an embodiment of the present disclosure.
  • the dual-gate product uses one data line to drive multiple columns of sub-pixels at the same time, thereby reducing the number of data lines, reducing the total number of driver chips (ICs), and greatly reducing material costs. It is especially suitable for medium and large-sized products such as car displays and TVs.
  • FIG1 is a schematic diagram of the pixel arrangement of a dual gate product in the related art.
  • a dual gate product uses a data line DL to control short-connected pixels and long-connected pixels adjacent to each other in the same row.
  • the short-connected pixels do not cross the common electrode line CL, while the long-connected pixels need to cross the common electrode line CL, the long-connected pixels generate additional capacitance, where "long” in FIG1 represents long-connected pixels, “short” represents short-connected pixels, " ⁇ ” represents brighter, “ ⁇ ” represents very bright, “ ⁇ ” represents darker, and “ ⁇ ” represents very dark.
  • the additional capacitance will cause the periodic vertical stripes of bright-bright and dark-dark arrangement to be clearly observed for a single frame (positive frame "+” or negative frame "-”) display screen when the pixel is driven by column flipping; after the frame polarity is reversed, the brightness and darkness are reversed and become dark-dark-bright, thereby achieving temporal brightness and darkness uniformity; however, when the user shakes his head to view the screen, if a positive frame or negative frame is lost, the brightness and darkness cannot be averaged in time, thereby generating bad shaking head stripes.
  • an array substrate as shown in FIGS. 2 to 12 , comprising:
  • a base substrate 101 wherein the base substrate 101 includes a display area AA; optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.;
  • a plurality of pixel electrode groups 102 are arranged in an array in the display area AA, and the pixel electrode group 102 includes a first pixel electrode P1 and a second pixel electrode P2 , and the first pixel electrode P1 and the second pixel electrode P2 are alternately arranged in the row direction X and the column direction Y, respectively; optionally, the first pixel electrode P1 and the second pixel electrode P2 are made of the same material, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). material;
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • a plurality of data lines 103 run through the column gaps between the pixel electrode groups 102, the first pixel electrode P1 is coupled to the adjacent data line 103, and the second pixel electrode P2 is connected to the data line 103 coupled to the first pixel electrode P1 in the same pixel electrode group 102;
  • the material of the data line 103 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the data line 103 may be a single-layer structure or a laminated structure, for example, the data line 103 is a laminated structure consisting of a titanium metal layer/an aluminum metal layer/a titanium metal layer;
  • connection structures 104 are located at the row gaps between the pixel electrode groups 102, and the connection structures 104 are connected between the second pixel electrode P2 and the data line 103;
  • a plurality of common electrode lines 105 pass through the column gaps within the pixel electrode group 102, and a first capacitor is provided between the common electrode lines 105 and the connection structure 104; optionally, the common electrode lines 105 and the data lines 103 are in the same layer and made of the same material; it should be noted that the capacitor structure in this case refers to a structure including two conductive layers and an insulating layer provided in the conductive layer.
  • a plurality of compensation structures 106 are located at the row gaps between the pixel electrode groups 102.
  • the compensation structures 106 are coupled to the first pixel electrode P1 , and a second capacitor is provided between the compensation structures 106 and the common electrode line 105.
  • the second capacitor includes a three-layer conductive layer structure C that overlaps each other perpendicular to the base substrate 101, so that the second capacitor is substantially the same as the first capacitor (i.e., the same, or within an error range of ⁇ 10% caused by factors such as manufacturing and measurement).
  • a compensation structure 106 coupled to the first pixel electrode P1 is additionally provided, and a second capacitor formed by the compensation structure 106 and the common electrode line 105 includes a three-layer conductive layer structure C, so that the second capacitor is substantially the same as the first capacitor (i.e., the additional capacitor of the second pixel electrode P2 caused by the overlap of the connection structure 104 and the common electrode line 105).
  • the voltage difference between the first pixel electrode P1 and the second pixel electrode P2 caused by the first capacitor can be reduced, and the brightness uniformity of the pixel areas where the first pixel electrode P1 and the second pixel electrode P2 are located can be improved, thereby effectively improving the bad shaking head pattern caused by uneven brightness.
  • the array substrate provided in the embodiment of the present disclosure may further include a plurality of gate lines 107 located on both sides of each row of pixel electrode groups 102, as shown in FIG. 3.
  • Each first pixel electrode P1 of 102 is connected to a gate line 107 on one side of the pixel electrode group 102 in the row
  • each second pixel electrode P2 is connected to a gate line 107 on the other side of the pixel electrode group 102 in the row, so that there are two gate lines 107 at the row gap between adjacent pixel electrode groups 102, forming a dual gate structure.
  • the material of the gate line 107 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni).
  • the gate line 107 may be a single-layer structure or a stacked-layer structure, for example, the gate line 107 is a single-layer structure composed of a copper metal layer.
  • a mask plate may be used to make patterns of the layer where the pixel electrode group 102 is located and the layer where the gate line 107 is located.
  • the pixel electrode group 102 layer is first prepared using a mask plate, and then the gate line 107 layer is prepared using the same mask plate, and then a gate insulating layer, such as a silicon nitride layer, is prepared.
  • a pattern similar to the gate line 107 and the connection structure 104 exists in the layer where the pixel electrode group 102 is located.
  • a portion M where one electrode of the transistor 109 is electrically connected to the second pixel electrode P2 includes a long connection portion N in the same layer as the pixel electrode group 102 and a connection structure 104 in the same layer as the gate line 107, and the two are in contact.
  • the three-layer conductive layer structure C includes a first conductive structure C1 which is arranged at the same layer and the same material as the pixel electrode group 102, a second conductive structure C2 which is arranged at the same layer and the same material as the gate line 107, and a third conductive structure C3 which is arranged at the same layer and the same material as the data line 103, wherein the first conductive structure C1 and the second conductive structure C2 are arranged in a stacked and contacting manner, the third conductive structure C3 is stacked and arranged on a side of the second conductive structure C2 away from the first conductive structure C1 , and the third conductive structure C3 and the second conductive structure C2 are insulated from each other; at this time, the three-layer conductive layer structure C can be used as a repair point.
  • the three-layer structure is easier to repair because the metal material at the same layer as the gate line is arranged.
  • welding repair is adopted. That is, when a bright spot or other problems occur in a pixel, the abnormal bright spot can be turned black by welding the third conductive structure C3 and the second conductive structure C2 together.
  • “same layer” refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be different. The patterns may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.
  • the capacitance compensation of the first pixel electrode P1 can be realized by the following two schemes; one of the schemes is shown in FIG5 , the common electrode line 105 includes a protrusion 1051 arranged to cross the column direction Y, and the protrusion 1051 and the compensation structure 106 form a second capacitor; the other scheme is shown in FIG6 , the common electrode line 105 includes a main body 1052 extending along the column direction Y, and the main body 1052 and the compensation structure 106 form a second capacitor.
  • the array substrate may further include a common electrode 108 whose orthographic projection overlaps with the pixel electrode group 102, and the second capacitor may further include a fourth conductive portion C 4 arranged in the same layer and the same material as the common electrode 108, and the fourth conductive portion C 4 is coupled to the common electrode line 105.
  • the material of the common electrode 108 includes a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).
  • the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 3, 5, 9 and 10, it can also include a plurality of transistors 109 located at the row gaps between the pixel electrode groups 102, and the transistors 109 coupled to the same data line 103 are separated on the left and right sides of the data line 103.
  • the second capacitor can also include a semiconductor structure C5 arranged on the same layer as the active layer 1091 of the transistor 109.
  • the semiconductor structure C5 and the third conductive structure C3 are arranged in stacked contact.
  • the pattern of the layer where the semiconductor structure C5 is located i.e., the active layer 1091
  • the layer where the third conductive structure C3 is located i.e., the layer where the data line 103 is located
  • one mask plate can be saved, thereby reducing costs and improving production efficiency.
  • the active layer 1091 has a pattern similar to the data line 103, the common electrode line 111, the first electrode 1093, and the second electrode 1094 of the transistor 109.
  • the semiconductor layer is first coated, and then the data line layer is coated.
  • a mask is used to pattern the data line layer to form the data line 103 and the semiconductor layer to form the active layer 1091.
  • an insulating layer PVX such as a silicon nitride layer, is coated, and then a common electrode layer is coated, and the common electrode layer is patterned to form a common electrode 108.
  • connection structure 104 can be set in the same layer and with the same material as at least one layer of the compensation structure 106.
  • the connection structure 104 and the compensation structure 106 are both set in the layer where the pixel electrode group 102 is located and the layer where the gate line 107 is located.
  • the data line 103 includes a widened portion 1031, and at least part of the widened portion 1031 is used to support the spacer PS; the gate 1092 of the transistor 109 is separated on both sides of the data line 103, and the gate line 107 is partially reused as the gate 1092 of the transistor 109, and the first electrode 1093 of the transistor 109 is coupled to the widened portion 1031.
  • the orthographic projection of the first electrode 1093 of the transistor 109 on the base substrate 101 overlaps with the orthographic projection of the gate 1092 of the transistor 109 on the base substrate 101, so that the first electrode 1093 of the transistor 109 and the gate 1092 form a double-layer metal, which can act as a barrier (PS Barrier) to prevent the spacer PS from sliding and causing scratches on the alignment film (PI) when the product is deformed by force.
  • PS Barrier a barrier
  • the transistors 109 connected to the same data line 103 are located on the left and right sides thereof, which may result in different overlapping areas between the gate line 107 and the second electrode 1094 when a process deviation (Shift) occurs, and vertical streak defects may appear on the left and right rows of the data line 103.
  • the present disclosure may set the second electrode 1094 of the transistor 109 to overlap the gate lines 107 on the left and right sides thereof, so as to ensure that the layer where the gate line 107 is located and the layer where the data line 103 is located still have the same overlapping area when there is a process deviation.
  • the transistor 109 may be a P-type transistor or an N-type transistor, and the transistor 109 may be a bottom-gate transistor, a top-gate transistor, or a double-gate transistor, etc., which is not limited here.
  • the first electrode 1093 of the transistor 109 may be a source electrode
  • the second electrode 1094 may be a drain electrode
  • the first electrode 1093 of the transistor 109 may be a drain electrode
  • the second electrode 1094 may be a source electrode, which is not limited here.
  • the material of the active layer 1091 of the transistor 109 may be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc.
  • a gate insulating layer may be provided between the layer where the gate 1092 of the transistor 109 is located and the active layer 1091, and a passivation layer (PVX) may be provided between the layer where the first electrode 1093 and the second electrode 1094 of the transistor 109 are located and the layer where the common electrode 108 is located, and the materials of the gate insulating layer and the passivation layer may be inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, as shown in FIGS.
  • a transfer electrode 110 of the same layer and the same material as the common electrode 108 may be provided, and the first pixel electrode P1 or the second pixel electrode P2 is electrically connected to the second electrode 1094 through the fourth via hole h4 .
  • the fourth via hole h4 penetrates the passivation layer in the region connected to the second electrode 1094, and penetrates the passivation layer and the gate insulating layer at the same time in the region connected to the first pixel electrode P1 or the second pixel electrode P2 .
  • the array substrate provided in the embodiments of the present disclosure also includes a plurality of first wirings 111 penetrating through the gaps between the columns of the pixel electrode group 102 .
  • the first wirings 111 are in the same layer and made of the same material as the active layer 1091 of the transistor 109 and are arranged in a stacked contact with the common electrode line 105 .
  • a mask plate may be used to produce patterns of the layer where the first wirings 111 and the layer where the common electrode lines 105 are located.
  • the orthographic projection of the common electrode lines 105 produced in the end on the base substrate 101 will be within the orthographic projection of the first wirings 111 on the base substrate 101 .
  • the first wiring 111 of the same layer and the same material as the active layer 1091 will be conductive when exposed to backlight
  • the storage capacitor (Cst) formed by the overlap of the first wiring 111 and the first pixel electrode P 1 and the second pixel electrode P 2 will be uncontrollable, resulting in a ripple (waterfall) defect.
  • the present disclosure needs to ensure that the orthographic projection of the first wiring 111 on the base substrate 101 and the orthographic projection of the adjacent first pixel electrode P 1 on the base substrate 101 and the orthographic projection of the adjacent second pixel electrode P 2 on the base substrate 101 do not overlap each other; at the same time, in order to make the pixel aperture ratio larger, it is necessary to ensure that the distance d 1 between the first wiring 111 and the first pixel electrode P 1 and the second pixel electrode P 2 is as small as possible, for example, to meet the device alignment accuracy.
  • the current equipment alignment accuracy is 1 ⁇ m to 5 ⁇ m.
  • the present disclosure can set the distance d 1 between the first wiring 111 and the first pixel electrode P 1 and the second pixel electrode P 2 to be greater than or equal to 1 ⁇ m and less than or equal to 5 ⁇ m, such as 1 ⁇ m, 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, etc.
  • the common electrode 108 includes a plurality of slits S, and the orthographic projections of the slits S on the base substrate 101 overlap with the orthographic projections of the common electrode lines 105 on the base substrate 101, the orthographic projections of the first pixel electrode P1 on the base substrate 101, and the orthographic projections of the second pixel electrode P2 on the base substrate 101, respectively, so that the slits S of the common electrode 108 cover the common electrode lines 103 to improve the light effect.
  • the orthographic projection of the common electrode line 105 on the base substrate 101 is located within the orthographic projection of the first wiring 111 on the base substrate 101, when the orthographic projection of the slit S on the base substrate 101 overlaps with the orthographic projection of the common electrode line 105 on the base substrate 101, the orthographic projection of the slit S on the base substrate 101 must also overlap with the orthographic projection of the first wiring 111 on the base substrate 101.
  • a plurality of second wirings 112 penetrating the column gaps in the pixel electrode group 102 may also be included, and the second wirings 112 and the common electrodes 108 are integrally arranged, so that the common electrodes 108 overlapped and arranged in the same column of the pixel electrode group 102 are connected together through the second wirings 112; and in order to provide the common voltage provided by the common electrode line 105 to the common electrode 108, the second wirings 112 and the common electrode line 105 may be arranged to pass through the fifth via hole h penetrating the passivation layer.
  • the orthographic projection of the common electrode line 105 on the base substrate 101 can be set to exceed the orthographic projection of the second wiring 112 on the base substrate 101 by a distance greater than or equal to 0.5 ⁇ m and less than or equal to 2 ⁇ m, such as 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, etc.
  • a plurality of jumper wires 113 located at the column gaps between the pixel electrode groups 102 may also be included, and the jumper wires 113 are integrally arranged with the common electrodes 108 adjacent to each other in the same row to reduce the overall resistance of the common electrodes 108 and improve the uniformity of the common voltage; and the parasitic capacitance of the common electrodes 108 with reduced resistance to the data lines 103 is reduced, thereby reducing the load of the data lines 103.
  • the jumper wires 113 may be arranged at the middle position, the two end positions, etc. of the common electrodes 108 in the column direction Y, as long as the electrical connection of the common electrodes 108 adjacent to each other in the same row can be achieved.
  • the base substrate 101 further includes a frame area surrounding the display area AA, and the frame area includes a first frame area BB1 and a second frame area BB2 that are opposite to each other, and a third frame area BB3 and a fourth frame area BB4 that are opposite to each other.
  • Area BB 4 wherein the first border area BB 1 includes a binding area for binding the circuit board IC, the third border area BB 3 connects the first border area BB 1 and the second border area BB 2 , and the fourth border area BB 4 connects the first border area BB 1 and the second border area BB 2.
  • a gate drive circuit GOA is provided in the third border area BB 3 and/or the fourth border area BB 4 , and the gate drive circuit GOA is connected to the circuit board IC through a gate drive signal line 114, and the gate drive signal line 114 is provided in the same layer and the same material as the gate line 107.
  • the binding area includes a pad electrically connected to the gate drive signal line 114, and the pad is electrically connected to the gold finger of the circuit board IC.
  • the gate drive signal line 114 extending from the pad to the third border area BB 3 or the fourth border area BB 4 is in the same layer and the same material as the gate line 107, and there is no need to change the layer wiring.
  • the gate drive signal line 114 enters the third frame area BB 3 or the fourth frame area BB 4 from the binding area and is transferred from the layer where the gate line 107 is located to the layer where the data line 103 is located.
  • the gate drive signal line 114 of the layer where the gate line 107 is located and the gate drive signal line 114 of the layer where the data line 103 is located are respectively connected to the transition part of the same layer and the same material of the common electrode 108 by punching. Since the via will cross the gate output signal (Gout) routing, static electricity (ESD) is prone to burn the transition part; in some embodiments, the annealing process of the layer where the transition part is located can be increased to improve it, but this will affect the production capacity.
  • the present disclosure sets the gate drive signal line 114 only in the layer where the gate line 107 is located, without punching and changing layers, avoiding the phenomenon that the transition part at the via is burned by static electricity, thereby improving the product reliability, life and production capacity.
  • the gate drive signal line 114 includes a low-level power line VSS.
  • the low-level power line VSS is used to reduce the noise of at least one of the pull-up node (PU), the pull-down node (PD), the gate signal output terminal or the gate signal cascade output terminal in the gate drive circuit GOA.
  • the low-level power line VSS is electrically connected to the adapter block 120 (the same layer and the same material as the common electrode 108) through the tenth via h10 penetrating the gate insulation layer and the passivation layer, and the adapter block 120 is electrically connected to the pull-up node (PU) or the pull-down node (PD) in the gate drive circuit GOA through the ninth via h9 penetrating the passivation layer.
  • the above array substrate provided in the embodiment of the present disclosure, as shown in FIG. 16 to FIG. 20, it also includes a common electrode bus 115 which at least partially surrounds the display area AA in the frame area and is provided in the same layer and material as the gate line 107, and a transfer structure which is provided in the same layer and material as the common electrode 108.
  • the common electrode bus 115 includes a main line 1151 located in the third frame area BB3 and/or the fourth frame area BB4 , and a bump 1152 located on the side of the main line 1151 facing the display area AA, the bump 1152 is coupled to the common electrode 108 correspondingly through a first via hole h1 penetrating the insulating layer (for example, the gate insulating layer and the passivation layer), the transfer structure 116 is coupled to the signal output terminal Gout of the gate driving circuit GOA through a second via hole h2 penetr
  • the flushing of the via holes in this case refers to the difference in the size and number of the via holes.
  • the flushing in this case refers to the flushing within a fluctuation range of 30um.
  • the first via hole h1 and the second via hole h2 and/or the third via hole h3 have an offset within 30um (e.g., 25um, 20um, 10um, etc.) in the column direction.
  • the first via hole h1 includes three columns of via holes in the column direction
  • the second via hole h2 includes one column of via holes in the column direction Y
  • the third via hole h3 includes one column of via holes in the column direction Y.
  • 3 includes a row of via holes in the column direction Y.
  • the conductive structure 117 is flush with at least one side of the bump 1152 extending in the column direction Y.
  • the conductive structure 117 is arranged in the same layer as the gate line 107 of the display area AA.
  • the connection structures 116 (the connection structure 116 can be arranged in the same layer as the common electrode 108) on both sides of the bump 1152 are flush with at least one side extending in the column direction Y.
  • the first via h1 and the second via h2 and the third via h3 are ensured to be flush in the column direction Y as much as possible.
  • the film layer below the alignment film (PI) can be prevented from having a break, the orientation (rubbing) effect of the alignment film (PI) can be improved, and the stripe (mura) caused by poor orientation can be improved.
  • some output terminals of the gate drive circuit GOA are not electrically connected to the gate line 107 of the display area AA, but serve as a virtual gate drive circuit to provide display
  • the gate drive circuit GOA of the signal performs the function of transmitting the start signal or the reset signal.
  • the gate drive circuit GOA can be arranged on the border of a non-display area (for example, the third border area BB 3 or the fourth border area BB 4 ), that is, to realize single-sided drive, or it can be arranged on the borders of two opposite non-display areas (for example, the third border area BB 3 and the fourth border area BB 4 ), that is, to realize double-sided drive (the gate drive circuit GOA arranged on both sides can be connected to the same gate line 107, or can be connected to different gate lines 107, for example, the odd-numbered gate lines 107 are driven by the gate drive circuit GOA on one side, and the even-numbered gate lines 107 are driven by the gate drive circuit GOA on the other side), which is not limited here.
  • a non-display area for example, the third border area BB 3 or the fourth border area BB 4
  • the gate drive circuit GOA arranged on both sides can be connected to the same gate line 107, or can be connected to different gate lines 107, for example, the odd-
  • the common electrode bus 115 also includes a first branch line 1153 located in the first border area BB1 , and the distance between the first branch line 1153 and the adjacent gate line 107 is approximately equal to the distance between the two gate lines 107 at the row gap between two adjacent rows of pixel electrode groups 102, and the structure of the first branch line 1153 is approximately the same as the structure of the gate line 107.
  • the first branch line 1153 is arranged in the same manner as the two gate lines 107 at the row gap between two adjacent rows of pixel electrode groups 102, so that the lateral capacitance of the gate line 107 adjacent to the first branch line 1153 and the lateral capacitance of each gate line 107 at the row gap between two adjacent rows of pixel electrode groups 102 can be ensured to be equivalent, thereby making the brightness uniformity of each row of pixel electrode groups 102 better.
  • the common electrode bus 115 also includes a second branch line 1154 located in the first border area BB1 , the second branch line 1154 is spaced apart from the first branch line 1153 on the side of the first branch line 1153 away from the display area AA, and there is a first distance d3 between the second branch line 1154 and the nearest gate line 107, and the sum of the width of the row gap of each row of pixel electrode groups 102 in the column direction Y and the length of the pixel electrode group 102 in the column direction Y is the second distance d4 , and the first distance d3 is 1/10 to 1/2 of the second distance d4 , for example, 1/3.
  • the second branch line 1154 can be electrically connected to the transfer pattern 118 (which is provided in the same layer and material as the common electrode 108) through the sixth via hole h6 penetrating the gate insulating layer and the passivation layer, and the transfer pattern 118 is coupled to the common electrode line 105 through the seventh via hole h7 penetrating the passivation layer.
  • the transfer pattern 118 is integrally provided with the second trace 112 .
  • a dummy common electrode 119 may be provided at the wider gap between the first branch line 1153 and the second branch line 1154.
  • the dummy common electrode 119 is provided in the same layer and material as the common electrode 108, and is electrically connected to the common electrode bus 108 through the eighth via hole h8 penetrating the gate insulating layer and the passivation layer. Referring to FIG. 16, in the area corresponding to the dummy common electrode 119, no pixel electrode layer is provided.
  • the portion corresponding to the first branch line 1153 is provided with a transistor 108, but in the direction perpendicular to the base substrate 101, the transistor 108 corresponding to the first branch line 1153 is not electrically connected to the pixel electrode or the pixel electrode layer.
  • the embodiment of the present disclosure provides a display device, as shown in FIG21, comprising an array substrate 001 and an opposite substrate 002 arranged opposite to each other, and a liquid crystal layer 003 located between the array substrate 001 and the opposite substrate 002, wherein the array substrate 001 is the above-mentioned array substrate provided in the embodiment of the present disclosure. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned array substrate, the implementation of the display device can refer to the embodiment of the above-mentioned array substrate, and the repeated parts will not be repeated.
  • the orthographic projection of the data line 103 on the base substrate 101 and the orthographic projection of the gate line 107 on the base substrate 101 have an overlapping area O.
  • the inventors found that when the distance d5 between the orthographic projection of the spacer PS of the counter substrate 002 on the base substrate 101 and the overlapping area O is less than 10 ⁇ m, the spacer PS cannot be restored after deformation. When the distance d5 between the orthographic projection of the spacer PS on the base substrate 101 and the overlapping area O is greater than 20 ⁇ m, the pixel aperture ratio will be affected.
  • the distance d5 between the orthographic projection of the spacer PS on the base substrate 101 and the overlapping area O is set to 5 is greater than or equal to 10 ⁇ m and less than or equal to 20 ⁇ m, for example, 10 ⁇ m, 11 ⁇ m, 12 ⁇ m, 13 ⁇ m, 14 ⁇ m, 15 ⁇ m, 16 ⁇ m, 17 ⁇ m, 18 ⁇ m, 19 ⁇ m, 20 ⁇ m, etc., to ensure that after the spacer PS is deformed, it is blocked by the double-layer metal formed by the data line 103 and the gate line 107 in the overlapping area O, so that the spacer PS can rebound; at the same time, it does not affect the pixel aperture ratio.
  • the opposing substrate 002 further includes a plurality of color resists 201, at least part of the color resists 201 includes a first island structure 2011 corresponding to the widened portion 1031, and the first island structure 2011 is spaced apart from adjacent color resists 201, for example, the first island structure 2011 is spaced apart from adjacent color resists 201 by a distance of 5 ⁇ m.
  • the widened portion 1031 is used to support the spacer PS, and by arranging the first island structure 2011 corresponding to the widened portion 1031 in the color resist 201, and arranging a gap between the first island structure 2011 and the adjacent color resist 201, it can be ensured that the first island structure 2011 does not have a non-uniform height due to the overlap of the color resist 201, so that the supporting surface of the spacer PS is relatively flat.
  • At least part of the color resist 201 includes a second island structure 2012 whose orthographic projection overlaps with the common electrode line 105, and the second island structure 2012 is arranged at intervals from the adjacent color resist 201, for example, the second island structure 2012 is spaced 5 ⁇ m from the adjacent color resist 201.
  • the second island structure 2012 is spaced 5 ⁇ m from the adjacent color resist 201.
  • the mask plate does not need to be switched, and the mask plate can be shifted according to different alignment marks of the red color resist R, the green color resist G, and the blue color resist B to realize the production of the red color resist R, the green color resist G, and the blue color resist B, thereby saving process time and reducing development costs.
  • the pattern of the red color resist R is consistent with that of the blue color resist B within one period T, but inconsistent with the pattern of the green color resist G, so the mask plate cannot be shared.
  • adjacent color resists 201 may overlap each other in the region outside the first island structure 2011 and the second island structure 2012. Since there is a black matrix 202 in the overlapping region of the color resists 201, even if the edges of the color resists 201 overlap each other, it will not affect the optical effects such as transmittance.
  • a backlight module 004 located on the light incident side of the array substrate 001 may also be included.
  • the backlight module 004 may be a direct-lit backlight module or an edge-lit backlight module.
  • the edge-lit backlight module may include a light bar, a stacked reflector, a light guide plate, a diffuser, a prism group, etc.
  • the light bar is located on the light guide side. One side in the thickness direction of the board.
  • the direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser plate and a brightness enhancement film, etc.
  • the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source.
  • the lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).
  • Submillimeter or even micron-scale micro-LEDs are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting diodes is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare caused by traditional dynamic backlighting between bright and dark areas of the screen, optimizing the visual experience.
  • OLEDs organic light-emitting diodes
  • the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and any other product or component with a display function.
  • the display device provided by the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip.
  • control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like.
  • the control chip may also include a memory, and may also include a power module, and the like, and realize power supply and signal input and output functions through additionally provided wires, signal lines, and the like.
  • the control chip may also include a hardware circuit and a computer executable code, and the like.
  • the hardware circuit may include a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, and the like.
  • VLSI very large scale integration
  • the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure.
  • the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开的阵列基板及显示装置，包括具有显示区的衬底基板；在显示区呈阵列排布的像素电极组，像素电极组包括第一、第二像素电极，第一、第二像素电极在行方向和列方向上分别交替设置；贯穿像素电极组间列间隙的数据线，第一像素电极与相邻数据线耦接，第二像素电极与同一像素电极组内第一像素电极耦接的数据线相连；在像素电极组间行间隙处连接第二像素电极与数据线的连接结构；贯穿像素电极组内列间隙的公共电极线，公共电极线与连接结构之间具有第一电容；在像素电极组间行间隙处且与第一像素电极耦接的补偿结构，补偿结构与公共电极线之间具有第二电容，第二电容包括在垂直于衬底基板上相互交叠的三层导电层结构。

Description

阵列基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)具有体积小、功耗低、画质高、无辐射和携带方便等特点，近年来得到了迅速地发展，已逐渐取代传统的阴极射线管显示装置(Cathode Ray Tube display，CRT)，在当前的平板显示器市场中占据了主导地位。目前，TFT-LCD在各种大中小尺寸的产品上得到了广泛的应用，几乎涵盖了当今信息社会的主要电子产品，如液晶电视、高清晰度数字电视、电脑(台式和笔记本)、手机、平板电脑、导航仪、车载显示、投影显示、摄像机、数码相机、电子手表、计算器、电子仪器、仪表、公共显示和虚幻显示等。
发明内容
本公开提供的阵列基板及显示装置，具体方案如下：
一方面，本公开提供了一种阵列基板，包括：
衬底基板，所述衬底基板包括显示区；
多个像素电极组，在所述显示区呈阵列排布，所述像素电极组包括第一像素电极和第二像素电极，所述第一像素电极和所述第二像素电极在行方向和列方向上分别交替设置；
多条数据线，贯穿所述像素电极组间的列间隙，所述第一像素电极与相邻所述数据线耦接，所述第二像素电极与同一所述像素电极组内所述第一像素电极耦接的所述数据线相连；
多个连接结构，位于所述像素电极组间的行间隙处，所述连接结构连接在所述第二像素电极与所述数据线之间；
多条公共电极线，贯穿所述像素电极组内的列间隙，所述公共电极线与所述连接结构之间具有第一电容；
多个补偿结构，位于所述像素电极组间的行间隙处，所述补偿结构与所述第一像素电极耦接，且所述补偿结构与所述公共电极线之间具有第二电容，所述第二电容包括在垂直于所述衬底基板上相互交叠的三层导电层结构。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括位于各行所述像素电极组两侧的多条栅线，所述三层导电层结构包括与所述像素电极组同层设置的第一导电结构、与所述栅线同层设置的第二导电结构、以及与所述数据线同层设置的第三导电结构。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述公共电极线包括与列方向交叉设置的凸出部，所述凸出部与所述补偿结构形成所述第二电容。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述公共电极线包括沿列方向延伸的主体部，所述主体部与所述补偿结构形成所述第二电容。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述公共电极线与所述数据线同层设置，所述阵列基板还包括正投影与所述像素电极组相互交叠的公共电极，所述第二电容还包括与所述公共电极同层设置的第四导电部。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括位于各行所述像素电极组的行间隙处的多个晶体管，所述第二电容还包括与所述晶体管的有源层同层设置的半导体结构。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述连接结构与所述补偿结构至少一层同层设置。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述数据线包括加宽部，至少部分所述加宽部用于支撑隔垫物；
所述阵列基板还包括位于各行所述像素电极组的行间隙处的多个晶体管， 以及位于各行所述像素电极组两侧的多条栅线，其中，所述晶体管的栅极分居在所述数据线的两侧，所述栅线的局部复用为所述晶体管的栅极，所述晶体管的第一极与所述加宽部耦接，所述晶体管的第一极在所述衬底基板上的正投影与所述晶体管的栅极在所述衬底基板上的正投影相互交叠。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括贯穿所述像素电极组内列间隙的多条第一走线，所述第一走线与所述晶体管的有源层同层且与所述公共电极线层叠接触设置，所述公共电极线在所述衬底基板上的正投影位于所述第一走线在所述衬底基板上的正投影内，所述第一走线在所述衬底基板的正投影与相邻所述第一像素电极在所述衬底基板上的正投影、以及相邻所述第二像素电极在所述衬底基板上的正投影之间的距离大于等于1μm且小于等于5μm。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括贯穿所述像素电极组间的行间隙的多条栅线，以及位于所述栅线与所述数据线围成区域内的公共电极，所述公共电极包括多个狭缝，所述狭缝在所述衬底基板上的正投影与所述公共电极线在所述衬底基板上的正投影、所述第一像素电极在所述衬底基板上的正投影、以及所述第二像素电极在所述衬底基板上的正投影分别相互交叠。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括贯穿所述像素电极组内的列间隙的多条第二走线，所述第二走线与所述公共电极一体设置，所述第二走线与所述公共电极线耦接，所述公共电极线在所述衬底基板上的正投影相对于所述第二走线在所述衬底基板上的正投影单侧超出距离大于等于0.5μm且小于等于2μm。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括位于所述像素电极组间的列间隙处的多个跨接线，所述跨接线与同行相邻的所述公共电极一体设置。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述衬底基板还包括包围所述显示区的边框区，所述边框区包括相对而置的第一边框区 和第二边框区、以及相对而置的第三边框区和第四边框区，其中，所述第一边框区包括用于绑定电路板的绑定区，所述第三边框区连接所述第一边框区和所述第二边框区，所述第四边框区连接所述第一边框区和所述第二边框区；
所述阵列基板还包括位于所述第三边框区和/或所述第四边框区的栅极驱动电路，位于各行所述像素电极组两侧的多条栅线，以及连接所述电路板与所述栅极驱动电路的栅极驱动信号线，所述栅极驱动信号线与所述栅线同层设置。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述栅极驱动信号线包括低电平电源线。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括在所述边框区内至少部分围绕所述显示区且与所述栅线同层设置的公共电极总线，正投影与所述像素电极组相互交叠的公共电极，与所述公共电极同层设置的转接结构，与所述栅线一体设置的导电结构，以及位于所述栅线所在层与所述公共电极所在层之间的绝缘层，其中，
所述公共电极总线包括位于所述第三边框区和/或所述第四边框区的主干线、以及位于所述主干线朝向所述显示区一侧的凸块，所述凸块通过贯穿所述绝缘层的第一过孔与所述公共电极对应耦接，所述转接结构通过贯穿所述绝缘层的第二过孔与所述栅极驱动电路的栅极信号输出端耦接、并通过贯穿所述绝缘层的第三过孔与所述导电结构耦接，所述第一过孔与所述第二过孔和/或所述第三过孔在列方向上大致齐平设置。
在一些实施例中，在本公开实施例提供的上述阵列基板中，相邻两行所述像素电极组的行间隙处设置有两条所述栅线，所述公共电极总线还包括位于所述第一边框区内的第一分支线，所述第一分支线与相邻所述栅线之间的距离大致等于相邻两行所述像素电极组行间隙处两条所述栅线之间的距离，且所述第一分支线的结构与所述栅线的结构大致相同。
在一些实施例中，在本公开实施例提供的上述阵列基板中，所述公共电极总线还包括位于所述第一边框区内的第二分支线，所述第二分支线在所述 第一分支线远离所述显示区的一侧与所述第一分支线间隔设置，所述第二分支线与最近的所述栅线之间具有第一距离，各行所述像素电极组的行间隙在列方向上的宽度与所述像素电极组在列方向上的长度之和为第二距离，所述第一距离是所述第二距离的1/10～1/2。
在一些实施例中，在本公开实施例提供的上述阵列基板中，还包括位于所述第一分支线与所述第二分支线之间的虚设公共电极，所述虚设公共电极与所述公共电极同层设置、且与所述公共电极总线电连接。
另一方面，本公开实施例提供了一种显示装置，包括相对位置的阵列基板和对向基板，以及位于所述阵列基板与所述对向基板之间的液晶层，所述阵列基板为本公开实施例提供的上述阵列基板。
在一些实施例中，在本公开实施例提供的上述显示装置中，所述阵列基板包括位于各行所述像素电极组两侧的多条栅线，所述数据线在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影具有交叠区域；
所述对向基板包括多个隔垫物，所述隔垫物在所述衬底基板上的正投影位于所述加宽部在所述衬底基板上的正投影内，且所述隔垫物在所述衬底基板上的正投影与所述交叠区域之间的距离大于等于10μm且小于等于20μm。
在一些实施例中，在本公开实施例提供的上述显示装置中，所述对向基板还包括多个色阻，至少部分所述色阻包括与所述加宽部对应的第一岛状结构，所述第一岛状结构与相邻所述色阻间隔设置。
在一些实施例中，在本公开实施例提供的上述显示装置中，至少部分色阻包括正投影与所述公共电极线交叠的第二岛状结构，所述第二岛状结构与相邻所述色阻间隔设置。
在一些实施例中，在本公开实施例提供的上述显示装置中，相邻所述色阻在所述第一岛状结构与所述第二岛状结构之外的区域内相互交叠。
附图说明
图1为相关技术中双栅(dual gate)产品的像素排布示意图；
图2为本公开实施例提供的阵列基板的示意图；
图3为图2中Z1区域的放大结构示意图；
图4为图3中Z2区域的放大结构示意图；
图5为图4中Z3区域的放大结构示意图；
图6为本公开实施例提供的第二电容的一种示意图；
图7为图3中像素电极所在层的结构示意图；
图8为图3中栅线所在层的结构示意图；
图9为图3中有源层所在层的结构示意图；
图10为图3中数据线所在层的结构示意图；
图11为图3中绝缘层的结构示意图；
图12为图3中公共电极所在层的结构示意图；
图13为图3中Z4区域的放大结构示意图；
图14为图3中Z5区域的放大结构示意图；
图15为图3中Z6区域的数据线所在层与公共电极所在层的放大结构示意图；
图16为图2中Z7区域的放大结构示意图；
图17为图16中栅线所在层的结构示意图；
图18为图16中数据线所在层的结构示意图；
图19为图16中绝缘层的结构示意图；
图20为图16中公共电极所在层的结构示意图；
图21为本公开实施例提供的显示装置的一种结构示意图；
图22为本公开实施例提供的色阻的一种结构示意图；
图23为本公开实施例提供的色阻的又一种结构示意图；
图24为本公开实施例提供的色阻的又一种结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公 开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，在附图中，为了清楚，放大了层、膜、面板、区域等的厚度。在本公开中参照作为理想化实施方式的示意图的横截面图描述示例性实施方式。这样，将预计到作为例如制造技术和/或公差的结果的与图的形状的偏差。因而，本公开中描述的实施方式不应解释为限于如本公开中所示的区域的具体形状，而是包括由例如制造所导致的形状方面的偏差。例如，图示或描述为平坦的区域可典型地具有粗糙的和/或非线性的特征；所图示的尖锐的角可为圆形的等。因而，图中所示的区域在本质上是示意性的，并且它们的尺寸和形状不意图图示区域的精确形状、不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在下面的描述中，当元件或层被称作“在”另一元件或层“上”或“连接到”另一元件或层时，该元件或层可以直接在所述另一元件或层上、直接连接到所述另一元件或层，或者可以存在中间元件或中间层。当元件或层被称作“设置于”另一元件或层“的一侧”时，该元件或层可以直接在所述另 一元件或层的一侧，直接连接到所述另一元件或层，或者可以存在中间元件或中间层。然而，当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”另一元件或层时，不存在中间元件或中间层。术语“和/或”包括一个或更多个相关列出项的任意和全部组合。
目前显示领域竞争日益激烈，成本降低思维贯彻整个显示领域。相较于采用一条数据线驱动一列子像素的常规方案，双栅(Dual Gate)产品采用一条数据线同时驱动多列子像素，由此减少了数据线的数量，减小了驱动芯片(IC)总数，大幅降低了材料成本，尤其适用于车载显示屏、电视等中大尺寸产品。
图1所示为相关技术中双栅(dual gate)产品的像素排布示意图。由图1可见，双栅(dual gate)产品采用一条数据线DL控制同行相邻的短连接像素和长连接像素，此时由于短连接像素未跨过公共电极线CL，而长连接像素需跨过公共电极线CL，致使长连接像素产生额外的电容，其中，图1中“长”表示长连接像素，“短”表示短连接像素，“↑”表示较亮，“↑↑”表示很亮，“↓”表示较暗，“↓↓”表示很暗。额外的电容会造成在采用列翻转的方式驱动像素时，对于单帧(正帧“+”或负帧“-”)显示画面，可明显观察到亮亮暗暗排布的周期性竖纹；帧极性反转后，亮暗发生反转，变为暗暗亮亮，从而实现时间上的亮暗均匀；然而，用户在摇头观看屏幕时，丢失某一正帧或者负帧，则会导致亮暗无法在时间上平均，从而产生摇头纹不良。
为了改善相关技术中存在的上述技术问题，本公开提供了一种阵列基板，如图2至图12所示，包括：
衬底基板101，该衬底基板101包括显示区AA；可选地，衬底基板101为允许可见光透过的基板，例如为玻璃、石英、塑料等材质；
多个像素电极组102，在显示区AA呈阵列排布，像素电极组102包括第一像素电极P1和第二像素电极P2，第一像素电极P1和第二像素电极P2在行方向X和列方向Y上分别交替设置；可选地，第一像素电极P1和第二像素电极P2的材料相同，例如为氧化铟锡(ITO)、氧化铟锌(IZO)等透明导电材 料；
多条数据线103，贯穿像素电极组102之间的列间隙，第一像素电极P1与相邻数据线103耦接，第二像素电极P2与同一像素电极组102内第一像素电极P1耦接的数据线103相连；可选地，数据线103的材料可以包括钼(Mo)、铝(Al)、钛(Ti)、铬(Cr)、镍(Ni)等金属，数据线103可以为单层结构或叠层结构，例如数据线103为由钛金属层/铝金属层/钛金属层构成的叠层结构；
多个连接结构104，位于像素电极组102之间的行间隙处，连接结构104连接在第二像素电极P2与数据线103之间；
多条公共电极线105，贯穿像素电极组102内的列间隙，公共电极线105与连接结构104之间具有第一电容；可选地，公共电极线105与数据线103同层、同材质；需要说明的是，本案中的电容结构指的是包括两层导电层以及导电层中设置有绝缘层的结构。
多个补偿结构106，位于像素电极组102之间的行间隙处，补偿结构106与第一像素电极P1耦接，且补偿结构106与公共电极线105之间具有第二电容，第二电容包括在垂直于衬底基板101上相互交叠的三层导电层结构C，使得第二电容与第一电容大致相同(即相同，或在因制作、测量等因素造成的±10％的误差范围内)。
在本公开实施例提供的上述阵列基板中，通过增设与第一像素电极P1耦接的补偿结构106，并设置补偿结构106与公共电极线105形成的第二电容包括三层导电层结构C，以使得第二电容与第一电容(即第二像素电极P2因连接结构104与公共电极线105交叠造成的额外电容)大致相同，可以减小第一像素电极P1和第二像素电极P2因第一电容造成的电压差异，提高第一像素电极P1和第二像素电极P2所在像素区的亮度均一性，从而有效改善了因亮暗不均造成的摇头纹不良。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3所示，还可以包括位于各行像素电极组102两侧的多条栅线107，每行像素电极组 102的各第一像素电极P1与该行像素电极组102一侧的一条栅线107对应相连，各第二像素电极P2与该行像素电极组102另一侧的一条栅线107对应相连，使得相邻像素电极组102之间的行间隙处具有两条栅线107，形成双栅(dual gate)结构。可选地，栅线107的材料可以包括钼(Mo)、铝(Al)、钛(Ti)、铬(Cr)、镍(Ni)等金属，栅线107可以为单层结构或叠层结构，例如栅线107为由铜金属层构成的单层结构。在一些实施例中，可利用一张掩膜板制作像素电极组102所在层与栅线107所在层的图案，在工艺上，首先用掩膜板制备像素电极组102层，然后再用同一掩膜板制备栅线107所在层，接下来制备栅极绝缘层，如氮化硅层。在此情况下，如图7和图8所示，在像素电极组102所在层存在与栅线107、连接结构104相似的图案。参考图7和图8，晶体管109的一极与第二像素电极P2电连接的部分M包括与像素电极组102同层的长连接部分N以及与栅线107同层的连接结构104，二者之间接触。
在一些实施例中，如图4至图8、图10所示，三层导电层结构C包括与像素电极组102同层、同材料设置的第一导电结构C1、与栅线107同层、同材料设置的第二导电结构C2、以及与数据线103同层、同材料设置的第三导电结构C3，其中，第一导电结构C1和第二导电结构C2层叠接触设置，第三导电结构C3层叠设置在第二导电结构C2远离第一导电结构C1的一侧，且第三导电结构C3和第二导电结构C2之间相互绝缘；此时三层导电层结构C可作为修复(repair)点，三层结构的设置相对两层结构，由于设置了与栅线同层的金属材料，更容易实现修复，例如采用焊接修复，即当像素出现亮点等问题的时候，通过将第三导电结构C3和第二导电结构C2焊接在一起，可使得异常亮点变黑。
需要说明的是，在本公开中，“同层”指的是采用同一成膜工艺形成用于制作特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而所形成层结构中的特定 图形可以是连续的也可以是不连续的，这些特定图形可能处于相同的高度或者具有相同的厚度、也可能处于不同的高度或者具有不同的厚度。
在一些实施例中，在本公开实施例提供的上述阵列基板中，可通过以下两种方案实现对第一像素电极P1的电容补偿；其中一种方案如图5所示，公共电极线105包括与列方向Y交叉设置的凸出部1051，凸出部1051与补偿结构106形成第二电容；另一种方案如图6所示，公共电极线105包括沿列方向Y延伸的主体部1052，主体部1052与补偿结构106形成第二电容。继续参见图6可知，阵列基板还可以包括正投影与像素电极组102相互交叠的公共电极108，第二电容还可以包括与公共电极108同层、同材料设置的第四导电部C4，该第四导电部C4与公共电极线105耦接。可选地，公共电极108的材料包括氧化铟锡(ITO)、氧化铟锌(IZO)等透明导电材料。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3、图5、图9和图10所示，还可以包括位于各像素电极组102之间的行间隙处的多个晶体管109，同一数据线103耦接的各晶体管109分居在该数据线103的左右两侧，第二电容还可以包括与晶体管109的有源层1091同层设置的半导体结构C5，可选地，半导体结构C5与第三导电结构C3层叠接触设置，这样就可以利用一张掩膜板制作半导体结构C5所在层(即有源层1091)与第三导电结构C3所在层(即数据线103所在层)的图案，相较于采用两张掩膜板分别制作半导体结构C5所在层与第三导电结构C3所在层的图案的方案，可节约一张掩膜板，由此降低了成本，提高了生产效率。并且，在利用一张掩膜板制作半导体结构C5所在层(即有源层1091)与第三导电结构C3所在层(即数据线103所在层)的图案的情况下，如图9和图10所示，在有源层1091存在与数据线103、公共电极线111、晶体管109的第一极1093、第二极1094相似的图案。在工艺上，首先涂布半导体层，然后涂布数据线层，接下来在用一张掩膜版分别对数据线层图案化形成数据线103，以及对半导体层图案化形成有源层1091，接下来涂布绝缘层PVX，例如氮化硅层，然后再涂布公共电极层，对公共电极层进行图案化，形成公共电极108。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图7和图8所示，连接结构104可以与补偿结构106的至少一层同层、同材料设置，例如在像素电极组102所在层、以及栅线107所在层均设置了连接结构104和补偿结构106。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3、图8和图10所示，数据线103包括加宽部1031，至少部分加宽部1031用于支撑隔垫物PS；晶体管109的栅极1092分居在数据线103的两侧，栅线107的局部复用为晶体管109的栅极1092，晶体管109的第一极1093与加宽部1031耦接，晶体管109的第一极1093在衬底基板101上的正投影与晶体管109的栅极1092在衬底基板101上的正投影相互交叠，使得晶体管109的第一极1093与栅极1092形成双层金属，该双层金属作为阻碍物(PS Barrier)可在产品受力形变时，防止隔垫物PS滑动对配向膜(PI)造成的划伤。
结合图3、图8至图10可见，同一数据线103连接的晶体管109位于其左右两侧，这会导致出现工艺偏差(Shift)时，栅线107与第二极1094的交叠(Overlay)面积不同而在数据线103左右行出现竖纹不良。为了改善竖纹不良，本公开可设置晶体管109的第二极1094与其左右两侧的栅线107均交叠，以保证栅线107所在层与数据线103所在层存在工艺偏差情况下依然具有相同的交叠面积。
在一些实施例中，晶体管109可以为P型晶体管或N型晶体管，晶体管109可以为底栅型晶体管、顶栅型晶体管或双栅型晶体管等，在此不做限定。本公开中晶体管109的第一极1093可以为源极，第二极1094为漏极，或者晶体管109的第一极1093为漏极，第二极1094为源极，在此不做限定。晶体管109的有源层1091的材料可以为非晶硅(a-Si)、多晶硅(poly)、氧化物(Oxide，如铟镓锌氧化物IGZO)等。可选地，晶体管109的栅极1092所在层与有源层1091之间可以设置有栅绝缘层(GI)，晶体管109的第一极1093、第二极1094所在层与公共电极108所在层之间可以设置钝化层(PVX)，该栅绝缘层和钝化层的材料均可以为氧化硅、氮化硅、氮氧化硅等无机绝缘材 料中的至少一种。在一些实施例中，如图7至图12所示，可设置与公共电极108同层、同材料的转接电极110、并通过第四过孔h4实现第一像素电极P1或第二像素电极P2与第二极1094的电连接，具体的，第四过孔h4在连接第二极1094的区域贯穿钝化层，且在连接第一像素电极P1或第二像素电极P2的区域同时贯穿钝化层和栅绝缘层。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3、图7、图9、图10和图14所示，还包括贯穿像素电极组102内列间隙的多条第一走线111，第一走线111与晶体管109的有源层1091同层、同材料且与公共电极线105层叠接触设置，在一些实施例中，可采用一张掩膜板制作第一走线111所在层和公共电极线105所在层的图案，因曝光衍射的作用，最终制作出的公共电极线105在衬底基板101上的正投影会位于第一走线111在衬底基板101上的正投影内。考虑到与有源层1091同层、同材料的第一走线111受到背光照射时会被导体化，若第一走线111与其两侧的第一像素电极P1、第二像素电极P2相互交叠，则会导致第一走线111与第一像素电极P1、第二像素电极P2相互交叠形成的存储电容(Cst)不可控，产生波纹(waterfall)不良。为了改善波纹不良，如图14所示，本公开需保证第一走线111在衬底基板101的正投影与相邻第一像素电极P1在衬底基板101上的正投影、以及相邻第二像素电极P2在衬底基板101上的正投影互不交叠；同时为了使得像素开口率较大，需保证第一走线111与第一像素电极P1、第二像素电极P2之间的距离d1尽可能地小，例如满足设备对位精度。当前设备对位精度为1μm～5μm，本公开可设置第一走线111与第一像素电极P1、第二像素电极P2之间的距离d1大于等于1μm且小于等于5μm，例如1μm、2μm、3μm、4μm、5μm等。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3、图14和图15所示，公共电极108包括多个狭缝S，狭缝S在衬底基板101上的正投影与公共电极线105在衬底基板101上的正投影、第一像素电极P1在衬底基板101上的正投影、以及第二像素电极P2在衬底基板101上的正投影分别相互交叠，使得公共电极108的狭缝S覆盖公共电极线103，以提升光效。
应当理解的是，因公共电极线105在衬底基板101上的正投影位于第一走线111在衬底基板101上的正投影内，故在狭缝S在衬底基板101上的正投影与公共电极线105在衬底基板101上的正投影相互交叠的情况下，狭缝S在衬底基板101上的正投影也必然与第一走线111在衬底基板101上的正投影相互交叠。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3、图12、图14和图15所示，还可以包括贯穿像素电极组102内的列间隙的多条第二走线112，第二走线112与公共电极108一体设置，使得同列像素电极组102交叠设置的各公共电极108通过第二走线112连接在一起；且为将公共电极线105提供的公共电压提供给公共电极108，可设置第二走线112与公共电极线105通过贯穿钝化层的第五过孔h5耦接；另外，考虑到公共电极108的狭缝S覆盖贯穿像素电极组102内列间隙的公共电极线105，会导致同列像素电极组102内列间隙处的第二走线112的线宽小于公共电极线105的线宽，为兼顾提升光效和保证同列公共电极108的电连接效果，可设置公共电极线105在衬底基板101上的正投影相对于第二走线112在衬底基板101上的正投影单侧超出距离大于等于0.5μm且小于等于2μm，例如0.5μm、1μm、1.5μm、2μm等。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图3、图12和图15所示，还可以包括位于像素电极组102之间列间隙处的多个跨接线113，跨接线113与同行相邻的公共电极108一体设置，以降低公共电极108的整体阻值，提升公共电压的均一性；并且，阻值降低的公共电极108对数据线103的寄生电容减小，由此减小了数据线103的负载。可选地，跨接线113可设置在公共电极108在列方向Y上的中间位置、两端位置等，只要可实现同行相邻公共电极108的电连接即可。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图2所示，衬底基板101还包括包围显示区AA的边框区，边框区包括相对而置的第一边框区BB1和第二边框区BB2、以及相对而置的第三边框区BB3和第四边框 区BB4，其中，第一边框区BB1包括用于绑定电路板IC的绑定区，第三边框区BB3连接第一边框区BB1和第二边框区BB2，第四边框区BB4连接第一边框区BB1和第二边框区BB2。且由图16至图20可见，在第三边框区BB3和/或第四边框区BB4设置有栅极驱动电路GOA，该栅极驱动电路GOA通过栅极驱动信号线114连接至电路板IC，栅极驱动信号线114与栅线107同层、同材料设置。可选地，绑定区包括与栅极驱动信号线114电连接的焊盘，且焊盘和电路板IC的金手指电连接，本公开中从焊盘一直延伸到第三边框区BB3或第四边框区BB4的栅极驱动信号线114都与栅线107同层、同材料，不需要换层布线。
相关技术中的栅极驱动信号线114由绑定区进入第三边框区BB3或第四边框区BB4后由栅线107所在层转成数据线103所在层，栅线107所在层的栅极驱动信号线114与数据线103所在层的栅极驱动信号线114通过打孔的方式分别与公共电极108同层、同材料的转接部相连，由于过孔会跨过栅极输出信号(Gout)走线，易发生静电(ESD)而烧毁转接部；在一些实施例中，可增加转接部所在层的退火工艺来改善，但这会影响产能。本公开通过将栅极驱动信号线114仅设置在栅线107所在层，无需打孔换层，避免了过孔处转接部被静电烧毁的现象，提高了产品信赖性寿命及产能。
在一些实施例中，在本公开实施例提供的上述阵列基板中，栅极驱动信号线114包括低电平电源线VSS。低电平电源线VSS用于给栅极驱动电路GOA中的上拉节点(PU)、下拉节点(PD)、栅极信号输出端或者栅极信号级联输出端的至少之一降噪。示例性地，如图16至图20所示，低电平电源线VSS通过贯穿栅绝缘层和钝化层的第十过孔h10与转接块120(与公共电极108同层、同材料)电连接，该转接块120通过贯穿钝化层的第九过孔h9与栅极驱动电路GOA中的上拉节点(PU)或下拉节点(PD)电连接。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图16至图20所示，还包括在边框区内至少部分围绕显示区AA且与栅线107同层、同材料设置的公共电极总线115，与公共电极108同层、同材料设置的转接结构 116，与栅线107一体设置的导电结构117，以及位于栅线107所在层与公共电极108所在层之间的绝缘层(包括位于栅线107所在层与数据线103所在层之间的栅绝缘层、以及位于数据线103所在层与公共电极108所在层之间的钝化层)，其中，公共电极总线115包括位于第三边框区BB3和/或第四边框区BB4的主干线1151、以及位于主干线1151朝向显示区AA一侧的凸块1152，凸块1152通过贯穿绝缘层(例如栅绝缘层和钝化层)的第一过孔h1与公共电极108对应耦接，转接结构116通过贯穿绝缘层(例如钝化层)的第二过孔h2与栅极驱动电路GOA的信号输出端Gout耦接、并通过贯穿绝缘层(例如栅绝缘层和钝化层)的第三过孔h3与导电结构117耦接，第一过孔h1与第二过孔h2和/或第三过孔h3在列方向Y上大致齐平设置，需要说明的是，本案中过孔的齐平指的是由于过孔大小以及数量的差异，本案的齐平指的是在30um以内的波动范围均属于齐平，例如，第一过孔h1与第二过孔h2和/或第三过孔h3在列方向上有30um以内(例如25um、20um、10um等)的偏移，参考图19，第一过孔h1在列方向上包括三列过孔，第二过孔h2在列方向Y上包括一列过孔，第三过孔h3在列方向Y上包括一列过孔，另外参考图17，本案中为了实现过孔的齐平设置，可选的，导电结构117在列方向Y延伸的至少一侧，与凸块1152在列方向Y延伸的至少一侧是齐平设置的，可选的，导电结构117与显示区AA的栅线107同层设置，可选的，在凸块1152两侧的连接结构116(连接结构116可以和公共电极108同层设置)在列方向Y延伸的至少一侧是齐平的。本公开中因第一过孔h1与第二过孔h2、第三过孔h3的大小不一致，导致第一过孔h1与第二过孔h2和/或第三过孔h3在列方向Y上有些许偏差，但在制作时尽可能保证第一过孔h1与第二过孔h2和/或第三过孔h3在列方向Y上齐平设置，这样就可以避免配向膜(PI)下方膜层出现断差，提高配向膜(PI)的取向(rubbing)效果，改善因取向不好而出现的条纹(mura)不良。参考图18，本案中，除了栅极驱动电路GOA的信号输出端GOut与显示面板显示区AA的栅线107电连接，有部分栅极驱动电路GOA的输出端未与显示区AA的栅线107电连接，而是作为虚拟栅极驱动电路，为提供显示 信号的栅极驱动电路GOA进行传递起始信号或者复位信号的功能。另外本案中栅极驱动电路GOA可以是设置在一个非显示区域的边框(例如第三边框区BB3或第四边框区BB4)上，即实现单边驱动，也可以设置在相对的两个非显示区域的边框(例如第三边框区BB3和第四边框区BB4)上，即实现双边驱动(双边设置的栅极驱动电路GOA可以连接同一栅线107，也可以连接不同的栅线107，例如奇数行栅线107由一侧栅极驱动电路驱动GOA，偶数行栅线107由另外一侧栅极驱动电路GOA驱动)，在此不限定。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图16至图20所示，公共电极总线115还包括位于第一边框区BB1内的第一分支线1153，第一分支线1153与相邻栅线107之间的距离大致等于相邻两行像素电极组102行间隙处两条栅线107之间的距离，且第一分支线1153的结构与栅线107的结构大致相同，换言之，第一分支线1153的设置方式与相邻两行像素电极组102行间隙处两条栅线107的设置方式相同，这样可以保证与第一分支线1153相邻的栅线107的侧向电容、以及相邻两行像素电极组102行间隙处每条栅线107的侧向电容相当，进而使得各行像素电极组102的亮度均一性较好。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图16和图17所示，公共电极总线115还包括位于第一边框区BB1内的第二分支线1154，第二分支线1154在第一分支线1153远离显示区AA的一侧与第一分支线1153间隔设置，第二分支线1154与最近的栅线107之间具有第一距离d3，各行像素电极组102的行间隙在列方向Y上的宽度与像素电极组102在列方向Y上的长度之和为第二距离d4，第一距离d3是第二距离d4的1/10～1/2，例如1/3，在此情况下，可保证第二分支线1154所在区域的布线空间较大，利于设置较宽的第二分支线1154来增强第二分支线1154与公共电极线105的电连接效果。具体的，如图16至图20所示，第二分支线1154可通过贯穿栅绝缘层和钝化层的第六过孔h6与转接图案118(与公共电极108同层、同材料设置)电连接，且转接图案118通过贯穿钝化层的第七过孔h7与公共电极线105耦 接，可选地，转接图案118与第二走线112一体设置。
在一些实施例中，在本公开实施例提供的上述阵列基板中，如图16至图20所示，为提高公共电极信号的均一性，可在第一分支线1153与第二分支线1154之间较宽的间隙处设置虚设(dummy)公共电极119，虚设公共电极119与公共电极108同层、同材料设置、并通过贯穿栅绝缘层和钝化层的第八过孔h8与公共电极总线108电连接。参考图16，在虚设公共电极119对应的区域，没有设置像素电极层，此时第一分支线1153对应的部分设置有晶体管108，但在垂直与衬底基板101的方向上，第一分支线1153对应的晶体管108不与像素电极或者像素电极层电连接。
基于同一发明构思，本公开实施例提供了一种显示装置，如图21所示，包括相对而置的阵列基板001和对向基板002，以及位于阵列基板001与对向基板002之间的液晶层003，其中，阵列基板001为本公开实施例提供的上述阵列基板。由于该显示装置解决问题的原理与上述阵列基板解决问题的原理相似，因此，该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图13所示，数据线103在衬底基板101上的正投影与栅线107在衬底基板101上的正投影具有交叠区域O，发明人发现在对向基板002的隔垫物PS在衬底基板101上的正投影与交叠区域O之间的距离d5小于10μm时，隔垫物PS变形后无法恢复，在对向基板002的隔垫物PS在衬底基板101上的正投影与交叠区域O之间的距离d5大于20μm时，会影响像素开口率，因此，本公开中设置隔垫物PS在衬底基板101上的正投影与交叠区域O之间的距离d5大于等于10μm且小于等于20μm，例如10μm、11μm、12μm、13μm、14μm、15μm、16μm、17μm、18μm、19μm、20μm等，以保证隔垫物PS形变后，通过交叠区域O内数据线103与栅线107构成的双层金属进行阻挡，使得隔垫物PS可以回弹；同时不影响像素开口率。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图22至图 24所示，对向基板002还包括多个色阻201，至少部分色阻201包括与加宽部1031对应的第一岛状结构2011，第一岛状结构2011与相邻色阻201间隔设置，例如第一岛状结构2011与相邻色阻201间隔5μm的距离。加宽部1031用于支撑隔垫物PS，通过在色阻201中设置与加宽部1031对应的第一岛状结构2011，并设置第一岛状结构2011与相邻色阻201之间具有缝隙，可保证第一岛状结构2011不因色阻201交叠而发生高度不均一情况，使得隔垫物PS的支撑面较为平坦。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图22和图23所示，至少部分色阻201包括正投影与公共电极线105交叠的第二岛状结构2012，第二岛状结构2012与相邻色阻201间隔设置，例如第二岛状结构2012与相邻色阻201间隔5μm的距离。由图22可见，通过在公共电极线105位置设置与相邻色阻201间隔的第二岛状结构2012，可使得在一个周期T内，红色色阻R、绿色色阻G、蓝色色阻B的形貌相同，因此，在实际工厂生产时可不切换掩膜板，仅根据红色色阻R、绿色色阻G、蓝色色阻B的不同对位标识(mark)平移掩膜板，即可实现红色色阻R、绿色色阻G、蓝色色阻B的制作，节省了制程时间，降低了开发成本。而由图24可见，若第二岛状结构2012与相邻色阻201之间未设置缝隙，则因仅在第一岛状结构2011与相邻色阻201之间预留了缝隙，导致一个周期T内红色色阻R与蓝色色阻B的图案一致，但与绿色色阻G的图案不一致，因此无法实现掩膜板共用。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图22和图23所示，相邻色阻201在第一岛状结构2011与第二岛状结构2012之外的区域内可以相互交叠。因在色阻201的交叠区域内有黑矩阵202，故即使色阻201的边缘相互交叠也不会对透过率等光学效果造成影响。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图21所示，还可以包括位于阵列基板001入光侧的背光模组004，该背光模组004可以为直下式背光模组，也可以为侧入式背光模组。可选地，侧入式背光模组可以包括灯条、层叠设置的反射片、导光板、扩散片、棱镜组等，灯条位于导光 板厚度方向的一侧。直下式背光模组可以包括矩阵光源、在矩阵光源出光侧层叠设置的反射片、扩散板和增亮膜等，反射片包括与矩阵光源中各灯珠的位置正对设置的开孔。灯条中的灯珠、矩阵光源中的灯珠可以为发光二极管(LED)，例如微型发光二极管(Mini LED、Micro LED等)。
亚毫米量级甚至微米量级的微型发光二极管和有机发光二极管(OLED)一样属于自发光器件。其与有机发光二极管一样，有着高亮度、超低延迟、超大可视角度等一系列优势。并且由于无机发光二极管发光是基于性质更加稳定、电阻更低的金属半导体实现发光，因此它相比基于有机物实现发光的有机发光二极管来说，有着功耗更低、更耐高温和低温、使用寿命更长的优势。且在微型发光二极管作为背光源时，能够实现更精密的动态背光效果，在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区域之间造成的眩光现象，优化视觉体验。
在一些实施例中，本公开实施例提供的上述显示装置可以为：投影仪、3D打印机、虚拟现实设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。可选地，本公开提供的显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (23)

  1. 一种阵列基板，其中，包括：
    衬底基板，所述衬底基板包括显示区；
    多个像素电极组，在所述显示区呈阵列排布，所述像素电极组包括第一像素电极和第二像素电极，所述第一像素电极和所述第二像素电极在行方向和列方向上分别交替设置；
    多条数据线，贯穿所述像素电极组间的列间隙，所述第一像素电极与相邻所述数据线耦接，所述第二像素电极与同一所述像素电极组内所述第一像素电极耦接的所述数据线相连；
    多个连接结构，位于所述像素电极组间的行间隙处，所述连接结构连接在所述第二像素电极与所述数据线之间；
    多条公共电极线，贯穿所述像素电极组内的列间隙，所述公共电极线与所述连接结构之间具有第一电容；
    多个补偿结构，位于所述像素电极组间的行间隙处，所述补偿结构与所述第一像素电极耦接，且所述补偿结构与所述公共电极线之间具有第二电容，所述第二电容包括在垂直于所述衬底基板上相互交叠的三层导电层结构。
  2. 如权利要求1所述的阵列基板，其中，还包括位于各行所述像素电极组两侧的多条栅线，所述三层导电层结构包括与所述像素电极组同层设置的第一导电结构、与所述栅线同层设置的第二导电结构、以及与所述数据线同层设置的第三导电结构。
  3. 如权利要求2所述的阵列基板，其中，所述公共电极线包括与列方向交叉设置的凸出部，所述凸出部与所述补偿结构形成所述第二电容。
  4. 如权利要求2所述的阵列基板，其中，所述公共电极线包括沿列方向延伸的主体部，所述主体部与所述补偿结构形成所述第二电容。
  5. 如权利要求4所述的阵列基板，其中，所述公共电极线与所述数据线同层设置，所述阵列基板还包括正投影与所述像素电极组相互交叠的公共电 极，所述第二电容还包括与所述公共电极同层设置的第四导电部。
  6. 如权利要求1～5任一项所述的阵列基板，其中，还包括位于各行所述像素电极组的行间隙处的多个晶体管，所述第二电容还包括与所述晶体管的有源层同层设置的半导体结构。
  7. 如权利要求1～6任一项所述的阵列基板，其中，所述连接结构与所述补偿结构至少一层同层设置。
  8. 如权利要求1～7任一项所述的阵列基板，其中，所述数据线包括加宽部，至少部分所述加宽部用于支撑隔垫物；
    所述阵列基板还包括位于各行所述像素电极组的行间隙处的多个晶体管，以及位于各行所述像素电极组两侧的多条栅线，其中，所述晶体管的栅极分居在所述数据线的两侧，所述栅线的局部复用为所述晶体管的栅极，所述晶体管的第一极与所述加宽部耦接，所述晶体管的第一极在所述衬底基板上的正投影与所述晶体管的栅极在所述衬底基板上的正投影相互交叠。
  9. 如权利要求8所述的阵列基板，其中，还包括贯穿所述像素电极组内列间隙的多条第一走线，所述第一走线与所述晶体管的有源层同层且与所述公共电极线层叠接触设置，所述公共电极线在所述衬底基板上的正投影位于所述第一走线在所述衬底基板上的正投影内，所述第一走线在所述衬底基板的正投影与相邻所述第一像素电极在所述衬底基板上的正投影、以及相邻所述第二像素电极在所述衬底基板上的正投影之间的距离大于等于1μm且小于等于5μm。
  10. 如权利要求1～9任一项所述的阵列基板，其中，还包括贯穿所述像素电极组间的行间隙的多条栅线，以及位于所述栅线与所述数据线围成区域内的公共电极，所述公共电极包括多个狭缝，所述狭缝在所述衬底基板上的正投影与所述公共电极线在所述衬底基板上的正投影、所述第一像素电极在所述衬底基板上的正投影、以及所述第二像素电极在所述衬底基板上的正投影分别相互交叠。
  11. 如权利要求10所述的阵列基板，其中，还包括贯穿所述像素电极组 内的列间隙的多条第二走线，所述第二走线与所述公共电极一体设置，所述第二走线与所述公共电极线耦接，所述公共电极线在所述衬底基板上的正投影相对于所述第二走线在所述衬底基板上的正投影单侧超出距离大于等于0.5μm且小于等于2μm。
  12. 如权利要求10或11所述的阵列基板，其中，还包括位于所述像素电极组间的列间隙处的多个跨接线，所述跨接线与同行相邻的所述公共电极一体设置。
  13. 如权利要求1～12任一项所述的阵列基板，其中，所述衬底基板还包括包围所述显示区的边框区，所述边框区包括相对而置的第一边框区和第二边框区、以及相对而置的第三边框区和第四边框区，其中，所述第一边框区包括用于绑定电路板的绑定区，所述第三边框区连接所述第一边框区和所述第二边框区，所述第四边框区连接所述第一边框区和所述第二边框区；
    所述阵列基板还包括位于所述第三边框区和/或所述第四边框区的栅极驱动电路，位于各行所述像素电极组两侧的多条栅线，以及连接所述电路板与所述栅极驱动电路的栅极驱动信号线，所述栅极驱动信号线与所述栅线同层设置。
  14. 如权利要求13所述的阵列基板，其中，所述栅极驱动信号线包括低电平电源线。
  15. 如权利要求13或14所述的阵列基板，其中，还包括在所述边框区内至少部分围绕所述显示区且与所述栅线同层设置的公共电极总线，正投影与所述像素电极组相互交叠的公共电极，与所述公共电极同层设置的转接结构，与所述栅线一体设置的导电结构，以及位于所述栅线所在层与所述公共电极所在层之间的绝缘层，其中，
    所述公共电极总线包括位于所述第三边框区和/或所述第四边框区的主干线、以及位于所述主干线朝向所述显示区一侧的凸块，所述凸块通过贯穿所述绝缘层的第一过孔与所述公共电极对应耦接，所述转接结构通过贯穿所述绝缘层的第二过孔与所述栅极驱动电路的栅极信号输出端耦接、并通过贯穿 所述绝缘层的第三过孔与所述导电结构耦接，所述第一过孔与所述第二过孔和/或所述第三过孔在列方向上大致齐平设置。
  16. 如权利要求15所述的阵列基板，其中，相邻两行所述像素电极组的行间隙处设置有两条所述栅线，所述公共电极总线还包括位于所述第一边框区内的第一分支线，所述第一分支线与相邻所述栅线之间的距离大致等于相邻两行所述像素电极组行间隙处两条所述栅线之间的距离，且所述第一分支线的结构与所述栅线的结构大致相同。
  17. 如权利要求16所述的阵列基板，其中，所述公共电极总线还包括位于所述第一边框区内的第二分支线，所述第二分支线在所述第一分支线远离所述显示区的一侧与所述第一分支线间隔设置，所述第二分支线与最近的所述栅线之间具有第一距离，各行所述像素电极组的行间隙在列方向上的宽度与所述像素电极组在列方向上的长度之和为第二距离，所述第一距离是所述第二距离的1/10～1/2。
  18. 如权利要求17所述的阵列基板，其中，还包括位于所述第一分支线与所述第二分支线之间的虚设公共电极，所述虚设公共电极与所述公共电极同层设置、且与所述公共电极总线电连接。
  19. 一种显示装置，其中，包括相对位置的阵列基板和对向基板，以及位于所述阵列基板与所述对向基板之间的液晶层，所述阵列基板为如权利要求1～18任一项所述的阵列基板。
  20. 如权利要求19所述的显示装置，其中，所述阵列基板包括位于各行所述像素电极组两侧的多条栅线，所述数据线在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影具有交叠区域；
    所述对向基板包括多个隔垫物，所述隔垫物在所述衬底基板上的正投影位于所述加宽部在所述衬底基板上的正投影内，且所述隔垫物在所述衬底基板上的正投影与所述交叠区域之间的距离大于等于10μm且小于等于20μm。
  21. 如权利要求19或20所述的显示装置，其中，所述对向基板还包括多个色阻，至少部分所述色阻包括与所述加宽部对应的第一岛状结构，所述 第一岛状结构与相邻所述色阻间隔设置。
  22. 如权利要求21所述的显示装置，其中，至少部分色阻包括正投影与所述公共电极线交叠的第二岛状结构，所述第二岛状结构与相邻所述色阻间隔设置。
  23. 如权利要求22所述的显示装置，其中，相邻所述色阻在所述第一岛状结构与所述第二岛状结构之外的区域内相互交叠。
PCT/CN2023/076086 2023-02-15 2023-02-15 阵列基板及显示装置 WO2024168566A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2023/076086 WO2024168566A1 (zh) 2023-02-15 2023-02-15 阵列基板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2023/076086 WO2024168566A1 (zh) 2023-02-15 2023-02-15 阵列基板及显示装置

Publications (1)

Publication Number Publication Date
WO2024168566A1 true WO2024168566A1 (zh) 2024-08-22

Family

ID=92421474

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/076086 WO2024168566A1 (zh) 2023-02-15 2023-02-15 阵列基板及显示装置

Country Status (1)

Country Link
WO (1) WO2024168566A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007293155A (ja) * 2006-04-27 2007-11-08 Epson Imaging Devices Corp 液晶表示装置
CN110658657A (zh) * 2018-06-29 2020-01-07 京东方科技集团股份有限公司 阵列基板和显示装置
CN112540487A (zh) * 2020-12-04 2021-03-23 Tcl华星光电技术有限公司 显示面板及其显示装置
CN113985671A (zh) * 2021-10-28 2022-01-28 京东方科技集团股份有限公司 阵列基板及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007293155A (ja) * 2006-04-27 2007-11-08 Epson Imaging Devices Corp 液晶表示装置
CN110658657A (zh) * 2018-06-29 2020-01-07 京东方科技集团股份有限公司 阵列基板和显示装置
CN112540487A (zh) * 2020-12-04 2021-03-23 Tcl华星光电技术有限公司 显示面板及其显示装置
CN113985671A (zh) * 2021-10-28 2022-01-28 京东方科技集团股份有限公司 阵列基板及显示装置

Similar Documents

Publication Publication Date Title
US10338443B2 (en) Amorphous silicon thin film transistor-liquid crystal display device and method of manufacturing the same
KR101885806B1 (ko) 액정표시장치 및 그 제조방법
US20190369452A1 (en) Array substrate, display panel and display apparatus
US10319316B2 (en) Electro-optical device including a plurality of scanning lines
US9971212B2 (en) Array substrate, liquid crystal display panel, and liquid crystal display
CN104950537A (zh) 显示装置的阵列基板
US9280025B2 (en) Active matrix substrate and display device
KR20090044467A (ko) 액정표시장치 및 그 제조방법
WO2024168566A1 (zh) 阵列基板及显示装置
US8064323B2 (en) Electro-optical device and electronic apparatus
US20240055440A1 (en) Array substrate and display device
WO2021082914A1 (zh) 显示装置及其制备方法、电子设备及控光面板
US7508480B2 (en) Liquid crystal display device with dummy portions
JP4052293B2 (ja) 液晶装置及び電子機器
WO2024182924A1 (zh) 阵列基板、其制作方法及显示装置
WO2024192775A1 (zh) 阵列基板、显示面板及显示装置
WO2024182965A1 (zh) 阵列基板及显示装置
KR20060028970A (ko) 박막 트랜지스터 표시판 및 액정 표시 장치
JP2001343913A (ja) 電気光学装置、その製造方法および電子機器
WO2023184426A1 (zh) 阵列基板、显示面板及显示装置
WO2012005198A1 (ja) アクティブマトリクス基板の製造方法
US11353762B2 (en) Display device
WO2024011858A1 (zh) 显示基板、显示面板及显示装置
WO2024192705A1 (zh) 阵列基板及显示装置
US20240319552A1 (en) Display substrate, display panel and display device