WO2024011858A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2024011858A1
WO2024011858A1 PCT/CN2022/141588 CN2022141588W WO2024011858A1 WO 2024011858 A1 WO2024011858 A1 WO 2024011858A1 CN 2022141588 W CN2022141588 W CN 2022141588W WO 2024011858 A1 WO2024011858 A1 WO 2024011858A1
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Prior art keywords
electrode
base substrate
orthographic projection
substrate
via hole
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PCT/CN2022/141588
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English (en)
French (fr)
Inventor
廖燕平
缪应蒙
刘冬
邵喜斌
江鹏
陈东川
赵盼辉
刘建涛
杨涛
曲莹莹
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280005252.6A priority Critical patent/CN117693712A/zh
Publication of WO2024011858A1 publication Critical patent/WO2024011858A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • CRT Cathode Ray Tube display
  • TFT-LCD has been widely used in various large, medium and small-sized products, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and notebooks), mobile phones, Tablet computers, navigators, vehicle displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays and virtual displays, etc.
  • Embodiments of the present disclosure provide a display substrate, a display panel and a display device.
  • the specific solutions are as follows:
  • a display substrate including:
  • a plurality of data lines located on the base substrate
  • a first insulating layer located on the side of the layer where the plurality of data lines are located away from the base substrate;
  • a plurality of gate lines located on a side of the first insulating layer away from the layer where the plurality of data lines are located, and the extension direction of the plurality of gate lines intersects the extension direction of the plurality of data lines;
  • a second insulating layer located on the side of the layer where the plurality of gate lines are located away from the first insulating layer
  • the first electrode is located on the side of the second insulating layer away from the layer where the gate line is located.
  • the orthographic projection of the first electrode on the base substrate is at least located on the side of each data line on the base substrate. The area enclosed by the orthographic projection on the substrate and the orthographic projection of each gate line on the base substrate.
  • the local orthographic projection of at least part of the data line on the base substrate is located at the position of the first electrode on the base substrate.
  • the first electrode includes a plurality of slits, and a minimum distance from the slits to the data line in the extending direction of the gate line is greater than 1.5 ⁇ m.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes: a transistor, the gate electrode of the transistor is in the same layer and made of the same material as the data line, and the first electrode and the third electrode of the transistor are arranged in the same layer and material.
  • the diode is in the same layer and made of the same material as the gate line; the gate electrode of the transistor is electrically connected to the gate line, and the first electrode of the transistor is electrically connected to the data line.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes: a first transfer electrode, the first transfer electrode is arranged in the same layer and the same material as the first electrode;
  • the first transfer electrode is electrically connected to the gate of the transistor through a first via hole penetrating the first insulating layer and the second insulating layer, and through a second through hole penetrating the second insulating layer.
  • the hole is electrically connected to the grid line.
  • the orthographic projection of the first via hole on the base substrate is located at the orthogonal position of the gate of the transistor on the base substrate.
  • the diameter of the first via hole gradually increases in the direction away from the base substrate
  • the first via hole includes a first port close to the base substrate
  • the first port is on the The length in the extension direction of the gate line is greater than or equal to 3 ⁇ m
  • the width of the first port in the extension direction of the data line is greater than or equal to 6 ⁇ m.
  • the orthographic projection of the second via hole on the base substrate is located within the orthographic projection of the gate line on the base substrate.
  • the diameter of the second via hole gradually increases in the direction away from the base substrate
  • the second via hole includes a second port close to the base substrate
  • the second port is on the gate line
  • the length in the extension direction is greater than or equal to 3 ⁇ m
  • the width of the second port in the extension direction of the data line is greater than or equal to 8 ⁇ m.
  • the gate line includes a protrusion arranged side by side with the first electrode of the transistor, and the first via hole is in the base substrate.
  • the orthographic projection of the second via hole on the base substrate does not overlap with the orthographic projection of the protruding portion on the base substrate.
  • the orthographic projection of the second via hole on the base substrate is located on the In orthographic projection on the base substrate.
  • the orthographic projection of the protrusion on the base substrate is the same as the orthographic projection of the gate of the transistor on the base substrate.
  • the minimum distance between the first electrode of the transistor and the protrusion is greater than or equal to 5 ⁇ m.
  • the gate line includes a wiring portion integrally provided with the protruding portion, and the wiring portion is in the extending direction of the data line.
  • Line width is greater than or equal to 5 ⁇ m.
  • the wiring portion and the protruding portion form an accommodation groove, and the first electrode of the transistor is located in the accommodation groove.
  • the orthographic projection of the gate of the transistor on the substrate is the same as the orthographic projection of the accommodating groove on the substrate. Projections partially overlap.
  • the first electrode of the transistor includes a first portion extending along the extending direction of the gate line, and the first portion is located on the substrate.
  • the orthographic projection on the base substrate partially overlaps with the orthographic projection of the gate of the transistor on the base substrate and does not overlap with the orthographic projection of the data line on the base substrate, and the third The distance between a branch part and the wiring part is greater than or equal to 5 ⁇ m.
  • the width of the first portion in the extending direction of the data line is greater than or equal to 3 ⁇ m.
  • the first via hole and the second via hole are integrally provided as a first through hole, and the first through hole is in the substrate.
  • the orthographic projection on the substrate is located within the orthographic projection of the first transfer electrode on the substrate substrate, and the orthographic projection of the first transfer electrode on the substrate substrate is in the extension direction of the data line and /Or the one-sided protrusion distance in the extension direction of the gate line relative to the orthographic projection of the first through hole on the base substrate is greater than or equal to 3 ⁇ m.
  • the orthographic projection of the first electrode of the transistor on the base substrate is the same as the orthographic projection of the first transfer electrode on the base substrate.
  • the minimum distance between orthographic projections is greater than or equal to 3 ⁇ m.
  • the above display substrate provided by the embodiment of the present disclosure further includes: a second transfer electrode, the second transfer electrode is arranged in the same layer and with the same material as the first electrode;
  • the second transfer electrode is electrically connected to the data line through a third via hole penetrating the first insulating layer and the second insulating layer, and is connected to the data line through a fourth via hole penetrating the second insulating layer.
  • the first pole of the transistor is electrically connected.
  • the data line includes a widened portion
  • the orthographic projection of the third via hole on the base substrate is located at the widened portion.
  • the diameter of the third via hole gradually increases in the direction away from the base substrate
  • the third via hole includes a third port close to the base substrate
  • the length of the third port in the extension direction of the gate line is greater than or equal to 6 ⁇ m
  • the width of the third port in the extension direction of the data line is greater than or equal to 3 ⁇ m.
  • the first pole of the transistor includes a second subsection, and the orthographic projection of the second subsection on the base substrate is located on the The widened portion is within the orthographic projection of the base substrate, and the orthographic projection of the fourth via hole on the base substrate is located within the orthographic projection of the second subsection on the base substrate,
  • the diameter of the fourth via hole gradually increases in the direction away from the base substrate.
  • the fourth via hole includes a fourth port close to the base substrate, and the fourth port extends on the gate line.
  • the length in the direction is greater than or equal to 8 ⁇ m, and the width of the fourth port in the extending direction of the data line is greater than or equal to 3 ⁇ m.
  • the distance between the widened portion and the gate of the transistor to which it is electrically connected is greater than or equal to 4.8 ⁇ m.
  • the distance between the widened portion and the adjacent and unconnected gate of the transistor is greater than or equal to 11 ⁇ m.
  • the orthographic projection of the second transfer electrode on the base substrate is located on the orthogonal projection of the widened portion on the base substrate. within the projection.
  • the gate line includes a wiring portion with a substantially uniform line width, and a protruding portion integrally provided with the wiring portion, and the wiring portion The portion and the protruding portion form a receiving groove, and the orthographic projection of the widened portion on the base substrate is located within the orthographic projection of the receiving groove on the base substrate.
  • the third via hole and the fourth via hole are integrally provided as a second through hole, and the second through hole is in the substrate.
  • the orthographic projection on the substrate is located within the orthographic projection of the second transfer electrode on the substrate substrate, and the orthographic projection of the second transfer electrode on the substrate substrate is in the extension direction of the data line and /Or the one-sided protrusion distance in the extension direction of the gate line relative to the orthographic projection of the second through hole on the base substrate is greater than or equal to 3 ⁇ m.
  • the above display substrate provided by the embodiment of the present disclosure further includes: a second electrode, the second electrode and the first electrode form a capacitor, and the capacitor is a storage capacitor or a liquid crystal capacitor, so
  • the first electrode of the storage capacitor is a pixel electrode
  • the first electrode or the second electrode of the liquid crystal capacitor is a pixel electrode
  • the pixel electrode is electrically connected to the second electrode of the transistor.
  • the orthographic projection of the second electrode on the base substrate is located between the orthographic projection of each of the data lines on the base substrate.
  • the orthographic projection of the second electrode on the base substrate is the same as the orthographic projection of the data line on the base substrate.
  • the distance between projections is greater than or equal to 6.4 ⁇ m.
  • the second electrode and the data line are in the same layer and made of different materials.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes a resistance-reducing line of the same layer and material as the second electrode, and the resistance-reducing line is electrically connected to the data line,
  • the distance between the orthographic projection of the resistance reducing line on the base substrate and the orthographic projection of the second electrode on the base substrate is greater than or equal to 4.8 ⁇ m.
  • the second electrode is a pixel electrode
  • the display substrate further includes: a third transfer electrode, the third transfer electrode is connected to the The first electrodes are arranged in the same layer and material;
  • the third transfer electrode is electrically connected to the second electrode through a fifth via hole penetrating the first insulating layer and the second insulating layer, and through a sixth via hole penetrating the second insulating layer. electrically connected to the second electrode of the transistor.
  • the orthographic projection of the fifth via hole on the base substrate is located at the orthographic projection of the second electrode on the base substrate.
  • the fifth via hole includes a fifth port close to the base substrate, and the fifth port is on the gate
  • the length in the line extension direction is greater than or equal to 3 ⁇ m
  • the width of the fifth port in the data line extension direction is greater than or equal to 6 ⁇ m.
  • the orthographic projection of the sixth via hole on the base substrate is located on the second electrode of the transistor on the base substrate.
  • the diameter of the sixth via hole gradually increases in the direction away from the base substrate.
  • the sixth via hole includes a sixth port close to the base substrate, and the sixth port is at the The length of the gate line in the extending direction is greater than or equal to 3 ⁇ m, and the width of the sixth port in the extending direction of the data line is greater than or equal to 8 ⁇ m.
  • the fifth via hole and the sixth via hole are integrally provided as a third through hole, and the third through hole is in the substrate.
  • the orthographic projection on the substrate is located within the orthographic projection of the third transfer electrode on the base substrate, and the orthographic projection of the third transfer electrode on the base substrate is in the extension direction of the data line and /Or the one-sided protrusion distance in the extension direction of the gate line relative to the orthographic projection of the third through hole on the base substrate is greater than or equal to 3 ⁇ m.
  • the first electrode includes an escape groove
  • the third transfer electrode is located in the avoidance slot
  • the third transfer electrode is connected to the escape groove.
  • the distance between the escape grooves is greater than or equal to 4 ⁇ m.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a connecting line, the connecting line is arranged in the same layer and the same material as the first electrode, and the connecting line extends from the data line.
  • the non-pixel electrodes in the direction are electrically connected.
  • the gate line includes a wiring portion with a substantially uniform line width, and a protruding portion integrally provided with the wiring portion, and the wiring portion
  • the connecting line and the protruding portion form an accommodating groove, and the connecting line spans the accommodating groove along the extension direction of the data line.
  • the orthographic projection of the connection line on the substrate substrate is the orthogonal projection of the protruding portion closest to the substrate substrate.
  • the distance between projections is greater than or equal to 3 ⁇ m.
  • the orthographic projection of the connection line on the substrate substrate is the orthographic projection of the data line closest to the substrate substrate. The distance between them is greater than or equal to 4 ⁇ m.
  • the width of the connection line in the extending direction of the gate line is greater than or equal to 4 ⁇ m.
  • the gate of the transistor is electrically connected to the gate line through a seventh via hole penetrating the first insulating layer.
  • the first electrode of the transistor is electrically connected to the data line through an eighth via hole penetrating the first insulating layer.
  • the second electrode of the transistor is electrically connected to the pixel electrode through a ninth via hole penetrating the first insulating layer.
  • the thickness of the first insulating layer is greater than or equal to and less than or equal to The thickness of the second insulating layer is greater than or equal to and less than or equal to
  • embodiments of the present disclosure provide a display panel, including an opposite display substrate and a counter substrate, and a liquid crystal layer located between the display substrate and the counter substrate, wherein the display substrate is The above display substrate provided by embodiments of the present disclosure.
  • the first electrode includes an electrode strip whose orthographic projection overlaps with the data line
  • the opposite substrate includes a black matrix
  • the black matrix includes black matrix strips extending along the extension direction of the data lines
  • a partial orthographic projection of the black matrix strips on the base substrate is located within the orthographic projection of the electrode strips on the base substrate
  • the width of the black matrix strip in the extending direction of the gate line is greater than or equal to 8 ⁇ m.
  • an embodiment of the present disclosure provides a display device, including the above display panel provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic structural diagram of a display substrate included in an advanced super-dimensional field switching liquid crystal display in the related art
  • Figure 2 is a schematic structural diagram of a display substrate included in a high aperture ratio-advanced super-dimensional field switching liquid crystal display in the related art
  • Figure 3 is a schematic structural diagram of a display substrate included in an in-plane switch-type liquid crystal display in the related art
  • Figure 4 is a schematic structural diagram of a vertical alignment liquid crystal display in the related art
  • Figure 5 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 6 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 7 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 8 is a cross-sectional view along line II' in Figure 1;
  • Figure 9 is a cross-sectional view along line II-II' in Figure 1;
  • Figure 10 is a cross-sectional view along line III-III' in Figure 7;
  • Figure 11 is a schematic structural diagram of the layer where the second electrode is located in Figure 5;
  • Figure 12 is a schematic structural diagram of the layer where the data line is located in Figure 5;
  • Figure 13 is a schematic structural diagram of the layer where the gate lines are located in Figure 5;
  • Figure 14 is a schematic structural diagram of the layer where the first electrode is located in Figure 5;
  • Figure 15 is a schematic structural diagram of the layer where the second electrode is located in Figure 6;
  • Figure 16 is a schematic structural diagram of the layer where the data line is located in Figure 6;
  • Figure 17 is a schematic structural diagram of the layer where the gate lines are located in Figure 6;
  • Figure 18 is a schematic structural diagram of the layer where the first electrode is located in Figure 6;
  • Figure 19 is a schematic structural diagram of the layer where the second electrode is located in Figure 7;
  • Figure 20 is a schematic structural diagram of the layer where the data line is located in Figure 7;
  • Figure 21 is a schematic structural diagram of the layer where the gate lines are located in Figure 7;
  • Figure 22 is a schematic structural diagram of the layer where the first electrode is located in Figure 7;
  • Figure 23 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 24 is a cross-sectional view along line IV-IV' in Figure 7;
  • Figure 25 is a cross-sectional view along line V-V' in Figure 7;
  • Figure 26 is a cross-sectional view along line VI-VI' in Figure 7;
  • Figure 27 is a schematic diagram of the electrical connection between the gate line and the gate of the transistor provided by an embodiment of the present disclosure
  • Figure 28 is a schematic diagram of the electrical connection between the data line and the first electrode of the transistor provided by an embodiment of the present disclosure
  • Figure 29 is a schematic diagram of the electrical connection between the second electrode and the second pole of the transistor provided by an embodiment of the present disclosure
  • Figure 30 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 31 is a cross-sectional view along line VII-VII' in Figure 30;
  • Figure 32 is a schematic structural diagram of the layer where the second electrode is located in Figure 30;
  • Figure 33 is a schematic structural diagram of the layer where the data lines are located in Figure 30;
  • Figure 34 is a schematic structural diagram of the layer where the gate lines are located in Figure 30;
  • Figure 35 is a schematic structural diagram of the layer where the first electrode is located in Figure 30;
  • Figure 36 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 37 is a schematic structural diagram of the layer where the second electrode is located in Figure 36;
  • Figure 38 is a schematic structural diagram of the layer where the data lines are located in Figure 36;
  • Figure 39 is a schematic structural diagram of the layer where the gate lines are located in Figure 36;
  • Figure 40 is a schematic structural diagram of the layer where the first electrode is located in Figure 36;
  • Figure 41 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 42 is a schematic structural diagram of the layer where the data line is located in Figure 41;
  • Figure 43 is a schematic structural diagram of the layer where the gate lines are located in Figure 41;
  • Figure 44 is a schematic structural diagram of the layer where the first electrode is located in Figure 41;
  • Figure 45 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 46 is a schematic structural diagram of the layer where the data line is located in Figure 48;
  • Figure 47 is a schematic structural diagram of the layer where the gate lines are located in Figure 48;
  • Figure 48 is a schematic structural diagram of the layer where the first electrode is located in Figure 48;
  • Figure 49 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 50 is a schematic structural diagram of the layer where the data line is located in Figure 49;
  • Figure 51 is a schematic structural diagram of the layer where the gate lines are located in Figure 49;
  • Figure 52 is a schematic structural diagram of the layer where the first electrode is located in Figure 49;
  • Figure 53 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 54 is a schematic structural diagram of the layer where the data line is located in Figure 53;
  • Figure 55 is a schematic structural diagram of the layer where the gate lines are located in Figure 53;
  • Figure 56 is a schematic structural diagram of the layer where the first electrode is located in Figure 53;
  • Figure 57 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 58 is a cross-sectional view along line VIII-VIII' in FIG. 57 .
  • Liquid crystal display devices in the related art include advanced super-dimensional field switching (ADS) type liquid crystal displays, high aperture ratio-advanced super-dimensional field switching (HADS) type liquid crystal displays, in-plane switching (IPS) type liquid crystal displays and vertical Alignment (VA) type LCD display.
  • ADS advanced super-dimensional field switching
  • HADS high aperture ratio-advanced super-dimensional field switching
  • IPS in-plane switching
  • VA vertical Alignment
  • Figure 1 shows a display substrate of an advanced super-dimensional field switching type liquid crystal display.
  • Figure 2 shows a display substrate of a high aperture ratio-advanced super-dimensional field switching type liquid crystal display.
  • Figure 3 shows an in-plane switching type liquid crystal display.
  • the display substrate of the display screen Figure 4 shows a vertical alignment liquid crystal display screen.
  • a display substrate as shown in Figures 5 to 22, including:
  • the base substrate 101 is a rigid substrate made of glass or other materials, or a flexible substrate made of polyimide or other materials;
  • a plurality of data lines (SD) 102 are located on the base substrate 101.
  • the material of the data lines 102 includes a metal material, such as a single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, copper, alloy, etc.
  • the data line 102 is a stacked structure composed of a titanium metal layer/aluminum metal layer/titanium metal layer;
  • the first insulating layer 103 is located on the side of the layer where the plurality of data lines 102 are located away from the base substrate 101.
  • the first insulating layer 103 is a gate insulating layer (GI).
  • the material of the first insulating layer 103 can be oxidized. Inorganic insulating materials such as silicon, silicon nitride, silicon nitride oxide, etc.;
  • a plurality of gate lines (G) 104 are located on the side of the first insulating layer 103 away from the layer where the plurality of data lines 102 are located, and the extension direction of the plurality of gate lines 104 intersects the extension direction of the plurality of data lines 102.
  • the material of the gate line 104 includes metal materials, such as a single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, copper, alloy, etc., for example, the gate line 104 is a titanium metal layer/aluminum metal layer/titanium metal A laminated structure composed of layers;
  • the second insulating layer 105 is located on the side of the layer where the plurality of gate lines 104 are located away from the first insulating layer 103.
  • the first insulating layer 103 is an inorganic insulating layer (PVX), and the material of the second insulating layer 105 is oxide.
  • Inorganic insulating materials such as silicon, silicon nitride, silicon nitride oxide, etc.;
  • the first electrode 106 is located on the side of the second insulating layer 105 away from the layer where the gate line 104 is located.
  • the orthographic projection of the first electrode 106 on the base substrate 101 is at least between the orthographic projection of each data line 102 on the base substrate 101.
  • Each gate line 104 is in an area surrounded by an orthographic projection on the base substrate 101; optionally, the first electrode 106 can be made of indium tin oxide (ITO), indium tin oxide (IZO), zinc oxide (ZnO), or other transparent materials. Made of conductive materials.
  • the layer where the data line 102 is located, the first insulating layer 103, the layer where the gate line 104 is located, the second insulating layer 105 and the first electrode 106 on the base substrate 101 layers so that there are two insulating layers, the first insulating layer 103 and the second insulating layer 105, between the layer where the data line 102 is located and the layer where the first electrode 106 is located far away from the base substrate 101.
  • the data line 102 The distance between the layer where the layer is located and the layer where the first electrode 106 is located is relatively large, which can reduce the coupling capacitance between the data line 102 and the first electrode 106, reduce the load caused by the coupling capacitance on the data line 102, and help improve the pixel charging rate. , lowering the temperature of the driving chip (IC); and, since the present disclosure uses the first insulating layer 103 and the second insulating layer 105 in the related art to reduce the coupling capacitance between the data line 102 and the first electrode 106, there is no need to An organic insulating layer is added to reduce the coupling capacitance between the data line 102 and the first electrode 106. Based on this, the process complexity will not be increased.
  • the thickness of the first insulating layer 103 is greater than or equal to and less than or equal to The thickness of the second insulating layer 105 is greater than or equal to and less than or equal to Optionally, the thickness of the first insulating layer 103 is The thickness of the second insulating layer 105 is At this time, the thickness of the insulation layer between the data line 102 and the first electrode 106 can reach The load on the data line 102 is greatly reduced and the pixel charging rate is improved.
  • the orthographic projection of at least part of the data line 102 on the base substrate 101 is located in the orthographic projection of the first electrode 106 on the base substrate 101, the first electrode 106 includes a plurality of slits S.
  • the first electrode 106 may include an electrode strip 106' between the two slits S closest to the data line 102, and the orthographic projection of the electrode strip 106' on the substrate 101 is relative to the position of the data line 102 on the substrate.
  • the orthographic projection on the substrate 101 exceeds 1.5 ⁇ m or more, for example, 2.2 ⁇ m. This arrangement ensures that the electrode strip 106' can still cover the data line 102 after process fluctuations; and, the orthographic projection of the electrode strip 106' on the base substrate 101 is relative to the orthographic projection of the data line 102 on the base substrate 101.
  • the thickness exceeds 2.2 ⁇ m, the optimal light effect design effect of the first electrode 106 can also be achieved.
  • the above display substrate provided by the embodiment of the present disclosure, as shown in Figures 5 to 7, Figure 9, Figure 12, Figure 13, Figure 16, Figure 17, Figure 20, Figure 21, Figure 30, Figure 33.
  • Figure 34, Figure 36, Figure 38, Figure 39, Figure 41 to Figure 43, Figure 45 to Figure 47, Figure 49 to Figure 51, Figure 53 to Figure 55 it can also include: a transistor 107, and the transistor 107
  • the gate electrode 71 and the data line 102 are arranged in the same layer and made of the same material.
  • the first electrode 72 and the second electrode 73 of the transistor 107 are arranged in the same layer and the same material as the gate line 104 , so that the transistor 107 is a bottom-gate transistor to pass the transistor 107
  • the gate 71 blocks the light to prevent the light from irradiating the channel of the transistor 107 and affecting the stability of the transistor 107 .
  • the gate electrode 71 of the transistor 107 is electrically connected to the gate line 104
  • the first electrode 72 of the transistor 107 is electrically connected to the data line 102
  • the second electrode 73 of the transistor 107 is electrically connected to the pixel electrode.
  • the material of the active layer 74 of the transistor 107 can be amorphous silicon, polysilicon, oxide, etc.; the first electrode 72 of the transistor 107 can be the source electrode, and the second electrode 73 can be the drain electrode, or the transistor 107 The first electrode 72 is the drain electrode, and the second electrode 73 is the source electrode; the transistor 107 can be a P-type transistor or an N-type transistor, which is not limited here.
  • the above display substrate provided by the embodiment of the present disclosure, as shown in Figures 5 to 7, Figure 14, Figure 18, Figure 22, Figure 23, Figure 24, Figure 30, Figure 35, Figure 36, Figure 40.
  • it can also include: a first transfer electrode 108, a first transfer electrode 108 and a first electrode 106 Set in the same layer and with the same material; the first transfer electrode 108 is electrically connected to the gate electrode 71 of the transistor 107 through the first via V 11 penetrating the first insulating layer 103 and the second insulating layer 105 , and is electrically connected to the gate electrode 71 of the transistor 107 by penetrating the second insulating layer 103 The second via V 12 of 105 is electrically connected to the gate line 104 , that is, the first transfer electrode 108 is used to realize the electrical connection between the gate line 104 and the gate electrode 71 of the transistor 107 .
  • the production of the first transfer electrode 108 can be completed while the first electrode 106 is being made, avoiding an additional process of manufacturing the first transfer electrode 108; and the penetrating second insulating layer can be formed simultaneously through one patterning process.
  • the gate electrode 71 of 107 is electrically connected to the first via V11 to avoid additional patterning process of the first insulating layer 103 . It should be understood that in some embodiments, as shown in FIG. 27 , the gate line 104 may also be electrically connected to the gate electrode 71 of the transistor 107 through the seventh via hole V 1 ′ penetrating the first insulating layer 103 .
  • the orthographic projection of the first via V 11 on the base substrate 101 is located at the gate 71 of the transistor 107 .
  • the diameter of the first via hole V 11 gradually increases in the direction Z away from the base substrate 101.
  • the first via hole V 11 includes a first port close to the base substrate 101. In order to ensure The overlapping resistance between the first transfer electrode 108 and the gate electrode 71 of the transistor 107 is small, and the shape of the first via V 11 is ensured to be good.
  • the length B of the first port in the extension direction X of the gate line 104 can be set.
  • the width F′ of the first port in the extension direction Y of the data line 102 is greater than or equal to 6 ⁇ m.
  • the length B is 5.75 ⁇ m
  • the width F′ is 6 ⁇ m.
  • the orthographic projection of the second via V 12 on the substrate 101 is located at the gate line 104 on the substrate 101 .
  • the diameter of the second via hole V 12 gradually increases in the direction Z away from the base substrate 101.
  • the second via hole V 12 includes a second port close to the base substrate 101.
  • the length C of the second port in the extension direction X of the gate line 104 can be set to be greater than or equal to 3 ⁇ m.
  • the width F of the port in the extension direction Y of the data line 102 is greater than or equal to 8 ⁇ m, the length C is 6.25 ⁇ m, and the width F is 8 ⁇ m.
  • the gate line 104 includes a protruding portion 41 arranged side by side with the first electrode 72 of the transistor 107 , and the first pass
  • the orthographic projection of the hole V 11 on the base substrate 101 and the orthographic projection of the protruding portion 41 on the base substrate 101 do not overlap with each other.
  • the orthographic projection of the second via hole V 12 on the base substrate 101 is located on the protruding portion. 41 in the orthographic projection on the base substrate 101 .
  • the protruding portion 41 has a larger area, which facilitates overlapping with the first transfer electrode 108 through the second via hole V 12.
  • the gate line 104 only increases the line width at the protruding portion 41. This avoids the overall line width of the gate line 104 being larger, reduces the blocking of the backlight by the gate line 104, and helps improve the transmittance.
  • the first via hole V 11 and the second via hole V 12 can be integrally provided as The first through hole V 1 .
  • the orthographic projection of the first through hole V 1 on the base substrate 101 is located within the orthographic projection of the first transfer electrode 108 on the base substrate 101 , and the first transfer electrode 108 is on the base substrate 101 .
  • the orthographic projection in the extension direction Y of the data line 102 and/or the extension direction X of the gate line 104 relative to the first through hole V 1 on the base substrate 101 exceeds the distance A/D/E/G on one side by more than or equal to 3 ⁇ m.
  • the single-side excess distances A, D, E, and G are 5.55 ⁇ m, 5.75 ⁇ m, 5.5 ⁇ m, and 5.5 ⁇ m respectively.
  • the orthographic projection of the first transfer electrode 108 on the base substrate 101 in the extension direction Y of the data line 102 and/or the extension direction X of the gate line 104 relative to the orthographic projection of the first through hole V 1 on the base substrate 101 When the distance A/D/E/G on one side is greater than or equal to 3 ⁇ m, even if process fluctuations occur, the first transfer electrode 108 can still cover the first through hole V 1 well, reducing the amount of water vapor passing through the first through hole. Hole V 1 contacts protrusion 41 and gate 71 posing a risk of corrosion thereto.
  • the orthographic projection of the protrusion 41 on the base substrate 101 is the same as the gate electrode 71 of the transistor 107 on the base substrate 101
  • the orthographic projection has an overlapping area OL, which is relatively flat and can be used to place spacers (PS) to improve the support effect of the spacers (PS) and effectively prevent the spacers (PS) from being supported due to If the surface is uneven, sliding damage occurs to the alignment film (PI), causing light leakage and other defects.
  • the spacer (PS) can also be disposed in other relatively flat areas.
  • the orthographic projection of the protruding portion 41 on the base substrate 101 can also be aligned with the transistor.
  • the orthographic projections of the gate electrode 71 of 107 on the base substrate 101 do not overlap with each other.
  • the minimum distance u between the first pole 72 of the transistor 107 and the protruding portion 41 may be greater than or equal to 5 ⁇ m, such as 9.55 ⁇ m. . Since the first electrode 72 of the transistor 107 and the protruding portion 41 are arranged in the same layer and with the same material, when the minimum distance u between the two is greater than or equal to 5 ⁇ m, process fluctuations, residual conductive foreign matter (particles), etc. can be avoided. The two are short-circuited.
  • the gate line 104 may also include a wiring portion 42 integrally provided with the protruding portion 41 , and the wiring portion 42 is on the data line.
  • the line width k in the extension direction Y of the gate line 102 is greater than or equal to 5 ⁇ m, such as 8 ⁇ m, to prevent the gate line 104 from disconnection failure.
  • the wiring portion 42 and the protruding portion 41 form an accommodating groove AG, and the first pole 72 of the transistor 107 is located in the accommodating groove AG.
  • the transistor 107 is prevented from occupying the pixel area too much, the pixel aperture ratio is improved, and the first electrode 72 of the transistor 107 is effectively prevented from being short-circuited with the gate line 104 of the same layer and material.
  • the opening of the accommodating groove AG faces the side of the pixel electrode controlled by the gate line 104 to which it belongs through the transistor 107, so that the second electrode 73 of the transistor 107 is in electrical contact with the pixel electrode on the opening side of the accommodating groove AG. connect.
  • the orthographic projection of the gate electrode 71 of the transistor 107 on the base substrate 101 and the accommodation groove AG are on the base substrate 101
  • the orthographic projections of the gate electrode 71 of the transistor 107 on the base substrate 101 and the orthographic projection of the first electrode 72 on the base substrate 101 overlap with each other in the accommodation groove AG, thereby This causes the channel region in the U-shaped structure of the first electrode 27 to form a conductive channel driven by the electric fields of the gate electrode 71 and the first electrode 72 .
  • the first electrode 72 of the transistor 107 includes a first portion 721 extending along the extension direction X of the gate line 104 .
  • the orthographic projection of the portion 721 on the base substrate 101 partially overlaps with the orthographic projection of the gate 71 of the transistor 107 on the base substrate 101 and does not overlap with the orthographic projection of the data line 102 on the base substrate 101, as
  • the distance j between the first sub-section 721 and the wiring section 42 can be set to be greater than or equal to 5 ⁇ m, for example, 9.25 ⁇ m.
  • the first branch 721 in order to prevent the first branch 721 from disconnection, as shown in FIG. 23 , can be set in the extension direction Y of the data line 102.
  • the width i is greater than or equal to 3 ⁇ m, such as 6 ⁇ m.
  • the orthographic projection of the first pole 72 of the transistor 107 on the substrate 101 and the first transfer electrode 108 on the substrate is greater than or equal to 3 ⁇ m, such as 6.55 ⁇ m, in order to prevent the channel area in the U-shaped structure of the first transfer electrode 108 and the first pole 72 from overlapping due to process fluctuations and other factors. Affects the switching characteristics of transistor 107.
  • the above display substrate provided by the embodiment of the present disclosure, as shown in Figures 5 to 7, Figure 14, Figure 18, Figure 22, Figure 23, Figure 25, Figure 30, Figure 35, Figure 36, Figure 40.
  • Figure 41, Figure 44, Figure 45, Figure 48, Figure 49, Figure 52, Figure 53 and Figure 56 it can also include: a second transfer electrode 109, the second transfer electrode 109 and the first electrode 106
  • the second transfer electrode 109 is arranged in the same layer and with the same material; the second transfer electrode 109 is electrically connected to the data line 102 through the third via hole V 21 penetrating the first insulating layer 103 and the second insulating layer 105 , and through the third via V 21 penetrating the second insulating layer 105 .
  • the four vias V 22 are electrically connected to the first pole 72 of the transistor 107 , that is, the second transfer electrode 109 is used to realize the electrical connection between the data line 102 and the first pole 72 of the transistor 107 .
  • the production of the second transfer electrode 109 can be completed while the first electrode 106 is being made, avoiding an additional process of making the second transfer electrode 109; and the second insulating layer can be formed simultaneously through one patterning process.
  • the first pole 72 of the transistor 107 may also be electrically connected to the data line 102 through the eighth via hole V 2 ′ penetrating the first insulating layer 103 .
  • the data line 102 includes a widened portion 21 to reduce the distance between the data line 102 and the second transfer electrode 109
  • the orthographic projection of the third via hole V 21 on the base substrate 101 can be located within the orthographic projection of the widened portion 21 on the base substrate 101.
  • the diameter of the third via hole V 21 gradually increases in the direction Z away from the base substrate 101 .
  • the third via hole V 21 includes a third port close to the base substrate 101 .
  • the third port is in the direction X in which the gate line 104 extends.
  • the length b' is greater than or equal to 6 ⁇ m, and the width e of the third port in the extension direction Y of the data line 102 is greater than or equal to 3 ⁇ m.
  • the length b' is 8 ⁇ m, and the width e is 5.75 ⁇ m.
  • the data line 102 is only at the widened part 21 Increasing the line width prevents the overall line width of the data line 102 from being too large, reduces the blocking of the backlight by the data line 102, and helps improve the transmittance.
  • the first pole 72 of the transistor 107 includes a second subsection 722 , and the second subsection 722 is on the base substrate.
  • the orthographic projection on 101 is located within the orthographic projection of the widened portion 21 on the base substrate 101, in order to reduce the overlapping resistance of the first pole 72 and the second transfer electrode 109 and ensure the shape of the fourth via hole V 22
  • the orthographic projection of the fourth via hole V 22 on the base substrate 101 can be located within the orthographic projection of the second subsection 722 on the base substrate 101 , and the fourth via hole V 22 is in a direction away from the base substrate 101
  • the diameter on Z gradually increases.
  • the fourth via V 22 includes a fourth port close to the base substrate 101 .
  • the length b of the fourth port in the extension direction X of the gate line 104 is greater than or equal to 8 ⁇ m.
  • the fourth port is on the data line 102
  • the width f in the extension direction Y is greater than or equal to 3 ⁇ m, optionally, the length b is 8 ⁇ m, and the width f is 6.25 ⁇ m.
  • the third via hole V 21 and the fourth via hole V 22 can be integrally provided as the second via hole V 21 .
  • Via V 2 the orthographic projection of the second through hole V 2 on the base substrate 101 is located within the orthographic projection of the second transfer electrode 109 on the base substrate 101 , and the second transfer electrode 109 is on the base substrate 101 .
  • the orthographic projection of the second transfer electrode 109 on the base substrate 101 in the extension direction Y of the data line 102 and/or the extension direction X of the gate line 104 relative to the orthographic projection of the second through hole V 2 on the base substrate 101 When the one-sided excess distance a/c/d/g is greater than or equal to 3 ⁇ m, even if process fluctuations occur, the second transfer electrode 109 can still cover the second through hole V 2 well, reducing the amount of water vapor passing through the second through hole.
  • the hole V 2 contacts the widened portion 21 and the first pole 72 posing a risk of corrosion thereto.
  • the distance h between the widened portion 21 and the gate electrode 71 of the transistor 107 to which it is electrically connected may be set to be greater than or equal to 4.8 ⁇ m, for example, 5 ⁇ m.
  • the gate electrode 71 of the transistor 107 is short-circuited, and the distance between the two can be increased.
  • the distance y between the widened portion 21 and the gate electrode 71 of the adjacent and unconnected transistor 107 is set to be greater than or equal to 11 ⁇ m.
  • the distance y y is 13 ⁇ m.
  • the orthographic projection of the second transfer electrode 109 on the base substrate 101 is located on the widened portion 21 on the base substrate 101 In the orthographic projection, there can be a sufficiently large overlapping area between the data line 102 and the second transfer electrode 109 to ensure a good electrical connection effect between the data line 102 and the second transfer electrode 109 .
  • the orthographic projection of the widened portion 21 on the base substrate 101 can be positioned within the orthographic projection of the accommodation groove AG on the base substrate 101 .
  • the above display substrate provided by the embodiment of the present disclosure, as shown in Figures 5 to 7, Figure 11, Figure 15, Figure 19, Figure 23, Figure 24, Figure 32, Figure 36, Figure 37, Figure 40.
  • Figure 41, Figure 44, Figure 45, Figure 48 to Figure 50, Figure 52 to Figure 54, and Figure 56 it can also include: a second electrode 110.
  • the second electrode 110 and the first electrode 106 form a capacitor.
  • the capacitor is the storage capacitor (Cst) or the liquid crystal capacitor (Clc)
  • the first electrode 106 of the storage capacitor (Cst) is the pixel electrode
  • the first electrode 106 or the second electrode 110 of the liquid crystal capacitor (Clc) is the pixel electrode (P)
  • the pixel The electrode is electrically connected to the second pole 73 of the transistor 107.
  • the pixel electrode is located in a pixel area surrounded by an orthographic projection of the data line 102 on the base substrate 101 and an orthographic projection of the gate line 104 on the base substrate 101.
  • the orthographic projection of the second pole 73 of the transistor 107 on the base substrate 101 can be set to extend from the U-shaped structure of the first pole 72 to the pixel area.
  • the pixel electrodes partially overlap.
  • the orthographic projection of the second electrode 110 on the base substrate 101 is located on each data line 102 on the substrate.
  • the orthographic projection of the second electrode 110 on the base substrate 101 and the data line 102 are on the base substrate 101
  • the distance d between the orthographic projections is greater than or equal to 6.4 ⁇ m.
  • the distance d 2 between the orthographic projection of the second electrode 110 on the base substrate 101 and the orthographic projection of the data line 102 on the base substrate 101 is greater than or equal to 6.4 ⁇ m, it is possible to prevent the third error due to process fluctuations.
  • the overlap between the two electrodes 110 and the data line 102 can prevent the dark field area at and near the data line 102 from being too large and resulting in a large transmittance loss.
  • the second electrode 110 and the data line 102 may be in the same layer and made of different materials.
  • one mask may first be used to form the pattern of the second electrode 110, and then another mask may be used to form the pattern of the data line 102.
  • the material of the second electrode 110 is a transparent conductive material such as indium tin oxide (ITO), indium tin oxide (IZO), zinc oxide (ZnO), etc.
  • a first conductive film layer for making the second electrode 110 and a second conductive film layer for making the data line 102 may also be formed in sequence. After that, a mask is used to pattern the first conductive film layer and the second conductive film layer to form the patterns of the second electrode 110 and the data line 102. In this case, the blocking effect of the data line 102 will cause There is a pattern of the first conductive film layer below the data line 102.
  • the display substrate also includes a resistance-reducing line 111 of the same layer and material as the second electrode 110. The resistance-reducing line 111 is in electrical contact with the data line 102.
  • the distance d between the orthographic projection of the resistance reducing line 111 on the base substrate 101 and the orthographic projection of the second electrode 110 on the base substrate 101 can be set.
  • 3 is greater than or equal to 4.8 ⁇ m, which means that the orthographic projection of the resistance reducing line 111 on the base substrate 101 exceeds the orthographic projection of the data line 102 on the base substrate 101 by 1.6 ⁇ m on one side.
  • the material of the second electrode 110 is a transparent conductive material such as indium tin oxide (ITO), indium tin oxide (IZO), zinc oxide (ZnO), etc.
  • the second electrode 110 is a pixel electrode
  • the display substrate further includes: a third transfer electrode 112, a third transfer electrode 112, and a third transfer electrode 112.
  • the connecting electrode 112 is in the same layer and made of the same material as the first electrode 106; the third connecting electrode 112 is electrically connected to the second electrode 106 through the fifth via V 31 penetrating the first insulating layer 103 and the second insulating layer 105, and The second electrode 73 of the transistor 107 is electrically connected through the sixth via hole V 32 penetrating the second insulating layer 105 .
  • the production of the third transfer electrode 112 can be completed while the first electrode 106 is being made, avoiding an additional process of making the third transfer electrode 112; and the through-through second insulating layer can be formed simultaneously through one patterning process.
  • 105 and is used to realize the electrical connection between the third transfer electrode 108 and the second pole 73, and the sixth via hole V 32 that penetrates the first insulating layer 103 and the second insulating layer 105 and is used to realize the electrical connection between the third transfer electrode 103 and the second pole 73.
  • the second electrode 73 of the transistor 107 is electrically connected to the fifth via V 31 to avoid additional patterning process of the first insulating layer 103 .
  • the second electrode 110 may also be electrically connected to the second pole 73 of the transistor 107 through the ninth via V 3 ′ penetrating the first insulating layer 103 .
  • the shape of the fifth via hole V 31 is better.
  • the orthographic projection of the fifth via hole V 31 on the base substrate 101 can be located within the orthographic projection of the second electrode 110 on the base substrate 101 .
  • the fifth via hole V 31 The diameter in the direction Z away from the base substrate 101 gradually increases.
  • the fifth via hole V 31 includes a fifth port close to the base substrate 101.
  • the length m of the fifth port in the extension direction X of the gate line 104 is greater than or equal to 3 ⁇ m.
  • the width r of the fifth port in the extension direction Y of the data line 102 is greater than or equal to 6 ⁇ m.
  • the length m is 4.75 ⁇ m and the width r is 6 ⁇ m.
  • the orthographic projection of the sixth via V 32 on the base substrate 101 can be set to be within the orthographic projection of the second pole 73 of the transistor 107 on the base substrate 101.
  • the diameter of the sixth via hole V 32 gradually increases in the direction Z away from the base substrate 101 .
  • the sixth via hole V 32 includes a sixth port close to the base substrate 101 .
  • the sixth port is in the direction X in which the gate line 104 extends.
  • the length n is greater than or equal to 3 ⁇ m, and the width r′ of the sixth port in the extension direction Y of the data line 102 is greater than or equal to 8 ⁇ m.
  • the length n is 6.25 ⁇ m, and the width r′ is 8 ⁇ m.
  • the fifth via hole V 31 and the sixth via hole V 32 can be integrally provided as the third via hole V 31 .
  • Via V 3 the orthographic projection of the third through hole V 3 on the base substrate 101 is located within the orthographic projection of the third transfer electrode 112 on the base substrate 101 , and the third transfer electrode 112 is on the base substrate 101 .
  • the orthographic projection in the extension direction Y of the data line 102 and/or the extension direction X of the gate line 104 relative to the orthographic projection of the third through hole V 3 on the base substrate 101 exceeds a distance l/o/q/s of more than or equal to 3 ⁇ m ; Under this condition, even if process fluctuations occur, the third transfer electrode 112 can still cover the third through hole V 3 well, reducing the damage caused by water vapor contacting the second pole 73 through the third through hole V 3 Risk of corrosion.
  • the first electrode 106 includes an escape groove AS.
  • the opening of the escape groove AS faces the accommodation groove AG.
  • the three transfer electrodes 112 are located in the escape groove AS, and the distance p between the third transfer electrode 112 and the escape groove AS is greater than or equal to 4 ⁇ m, so as to avoid the third transfer electrode 112 and the first electrode being arranged in the same layer and with the same material. 106 short circuit.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure may also include a first connection line 113 , which is in the same layer and made of the same material as the first electrode 106 , the first connection line 113 is electrically connected to the non-pixel electrode (such as the first electrode 106 in FIG. 23 ) in the extension direction Y of the data line 102, so that the overall resistance of the non-pixel electrode in the capacitor is smaller, and at the same time, the non-pixel electrode in the capacitor The voltage uniformity and stability of the electrode in the extension direction Y of the data line 102 are also improved.
  • the first connection line 113 may span the accommodation groove AG along the extension direction Y of the data line 102.
  • a connection line 113 spans the accommodation groove AG within the distance y between the protruding portion 41 and its adjacent and not electrically connected widened portion 21. This arrangement can ensure that there is a gap between the first connection line 113 and the gate line 104. The coupling capacitance is small.
  • the orthographic projection of the first connection line 113 on the base substrate 101 and the protrusion 41 closest to it are on the base substrate 101 .
  • the distance v between the orthographic projections on 101 is greater than or equal to 3 ⁇ m to prevent the first connection line 113 and the protruding portion 41 from overlapping due to process fluctuations and other factors.
  • the orthographic projection of the first connection line 113 on the base substrate 101 is the closest data line 102 (specifically, the data line 102 ).
  • the distance x between the orthographic projections of the widened portion 21) of 102 on the base substrate 101 is greater than or equal to 4 ⁇ m to prevent the first connection line 113 and the data line 102 from overlapping due to process fluctuations and other factors.
  • the width w of the first connection line 113 in the extension direction Y of the gate line X is greater than or equal to 4 ⁇ m to prevent the first connection line from 113 A disconnection failure occurred.
  • the first electrode 106 and the second electrode 110 are connected by the data line 102 and the gate line.
  • the liquid crystal capacitor (Clc) is formed by overlapping in the area surrounded by 104.
  • the first electrode 106 is a slit-shaped common electrode (Com)
  • the second electrode 110 is a block-shaped pixel electrode.
  • the first electrode 106 can be a dual domain electrode, and the extension direction of the remaining portion of the data line 102 outside the widened portion 21 can be the same as the extension direction of the dual domain electrode.
  • the extension direction Y of the data line 102 in this disclosure refers to the overall extension direction of the data line 102—the column direction.
  • the first electrode 106 and the second electrode 110 are overlappingly arranged in the area surrounded by the data line 102 and the gate line 104 to form a liquid crystal capacitor (Clc), where,
  • the first electrode 106 is a slit-shaped pixel electrode
  • the second electrode 110 is a block-shaped common electrode
  • the orthographic projections on 101 are only located in the area surrounded by the data line 102 and the gate line 104.
  • the second electrode 110 can be disposed in the same layer as the data line 102 with a gap between them, but their materials are different. Compared with the second electrode 110 and the data line 102 With the solution of different-layer insulation arrangement, the present disclosure can reduce the number of film layers and facilitate the realization of lightweight and thin design of the product.
  • the first electrode 106 and the second electrode 110 are arranged in the same layer and with the same material. Both the first electrode 106 and the second electrode 110 have a comb-shaped structure, and the first electrode The comb-tooth portions of 106 and the comb-tooth portions of the second electrode 110 are alternately arranged, so that the first electrode 106 and the second electrode 110 have opposite sides on the same layer, forming a liquid crystal capacitor (Clc).
  • the first electrode 106 is a pixel electrode electrically connected to the second electrode 73 of the transistor 107, and the second electrode 110 is a common electrode.
  • the orthographic projection of the first electrode 106 on the base substrate 101 is only located in the area surrounded by the data line 102 and the gate line 104 , and the orthographic projection of the second electrode 110 on the base substrate 101 is not only located in the area surrounded by the data line 102 and the gate line 104 .
  • the area surrounded by the line 102 and the gate line 104 also covers most of the orthographic projection of the data line 102 except the widened portion 21 on the base substrate 101, so that the area of the second electrode 110 is larger, so that the area of the second electrode 110 can be larger. More gaps between the comb teeth are provided on the second electrode 110 to increase transmittance and improve light efficiency.
  • the comb-tooth portion of the first electrode 106 and the comb-tooth portion of the second electrode 110 may be in the shape of a broken line, for example, a V-shape with an obtuse angle.
  • the extension direction of the remaining portion of the data line 102 outside the widened portion 21 may be the same as the extension direction of the comb tooth portion.
  • the extension direction Y of the data line 102 in this disclosure represents the overall extension of the data line 102 direction - column direction.
  • the common electrodes in the same row in the extension direction of the gate line 104 can also be connected through the second connection line 114 106, and the second electrode 110 in Figures 30 and 41) to reduce the overall resistance of the common electrode, and at the same time, the voltage uniformity and stability of the common electrode in the extension direction X of the gate line 104 are also improved.
  • the second connection line 114 may be on the same layer as the gate line 104 . Material settings.
  • the second connection line 114 is electrically connected to the common electrode through a via hole penetrating the second insulating layer 105; when the common electrode is the second electrode 110 (as shown in FIG. 30), the second connection line 114 is connected to the first electrode through a via hole.
  • the first connection lines 113 of the same layer and material are electrically connected to the common electrodes of the same row in the extension direction X of the gate lines 104 .
  • the first electrode 106 and the second electrode 110 form a storage capacitor (Cst).
  • the first electrode 106 is a slit electrode, and the first electrode 106 includes a "cross"-shaped main body MB.
  • the slits of the first electrode 106 are distributed in four areas defined by the "cross"-shaped main body MB.
  • the extending directions of the slits in two areas in the angular direction are the same, and the extending directions of the slits in two adjacent areas intersect.
  • the second electrode 110 and the data line 102 are arranged in the same layer and with the same material.
  • the second electrodes 110 in the same row in the extension direction The voltage uniformity and stability in the extension direction X of line 104 are also improved.
  • an embodiment of the present disclosure provides a display panel, as shown in FIGS. 57 and 58 , including a display substrate 001 and a counter substrate 002 facing each other, and a display panel 001 and a counter substrate 003 located between the display substrate 001 and the counter substrate 003 . There is a liquid crystal layer 003 between them, wherein the display substrate 001 is the above-mentioned display substrate 001 provided by the embodiment of the present disclosure.
  • the implementation of the display panel provided by the embodiment of the present disclosure can be referred to the implementation of the above-mentioned display substrate provided by the embodiment of the present disclosure, and duplication will not be repeated. Repeat.
  • the first electrode 106 includes an electrode strip 106 ′ in orthographic projection overlapping the data line 102 , facing the substrate.
  • 002 includes a black matrix 201.
  • the black matrix 201 includes a first black matrix strip 11 extending along the extension direction Y of the data line 102.
  • the partial orthographic projection of the first black matrix strip 11 on the base substrate 101 is located on the electrode strip 106' on the substrate. In the orthographic projection on the base substrate 101, since the electrode strip 106' is a dark field area, disposing the first black matrix strip 11 at the electrode strip 106' will not affect the transmittance.
  • the width of the first black matrix strip 11 in the extending direction Y of the gate line 104 is greater than or equal to 8 ⁇ m, so as to avoid cross-color problems at oblique viewing angles through the black matrix strip 11 .
  • the black matrix 201 may also include a second black matrix strip 12 extending along the extension direction 12 in the orthographic projection on the base substrate 101.
  • the above-mentioned display panel provided by the embodiment of the present disclosure may also include a sealant surrounding the liquid crystal layer 003 between the display substrate 001 and the counter substrate 002, located on the side of the display substrate close to the liquid crystal layer.
  • Polarizer, etc. wherein the polarization direction of the first polarizer and the polarization direction of the second polarizer are perpendicular to each other.
  • Other essential components in the display panel are all understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • an embodiment of the present disclosure provides a display device, including the above display panel provided by an embodiment of the present disclosure. Since the principle of solving the problem of the display device is similar to the principle of solving the problem of the above-mentioned display panel, therefore, the implementation of the display device provided by the embodiment of the present disclosure can be referred to the implementation of the above-mentioned display panel provided by the embodiment of the present disclosure, and the duplication will not be repeated. Repeat.
  • the above display device provided by the embodiments of the present disclosure may further include a backlight module, and the display panel is disposed on the light emitting side of the backlight module.
  • the backlight module can be a direct-type backlight module or an edge-type backlight module.
  • the edge-type backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffusion sheet, a prism group, etc.
  • the light bar is located on one side in the thickness direction of the light guide plate.
  • the direct backlight module may include a matrix light source, a reflective sheet stacked on the light exit side of the matrix light source, a diffusion plate, a brightness enhancement film, etc.
  • the reflective sheet includes openings positioned opposite the positions of each lamp bead in the matrix light source.
  • the lamp beads in the light strip and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro-light-emitting diodes (Mini LED, Micro LED, etc.).
  • Miniature light-emitting diodes at the submillimeter or even micron level are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have lower power consumption, better resistance to high and low temperatures, and longer service life than organic light-emitting diodes based on organic matter. Longer advantage. And when micro light-emitting diodes are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlights between bright and dark areas of the screen, optimizing the visual experience. .
  • the above-mentioned display device may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, Fitness wristbands, personal digital assistants, and any other product or component with a display function.
  • the display device includes but is not limited to: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, control chip and other components.
  • the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), etc.
  • control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additional wires, signal lines, etc.
  • control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays as well as existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits may also include field programmable gate arrays, programmable array logic, Programmable logic devices, etc.
  • VLSI very large scale integration
  • programmable gate arrays programmable array logic
  • Programmable logic devices etc.
  • the above structure does not constitute a limitation on the above display device provided by the embodiment of the present disclosure.
  • the above display device provided by the embodiment of the present disclosure may include more or less of the above. components, or combinations of certain components, or different arrangements of components.

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Abstract

本公开提供的显示基板、显示面板及显示装置，包括：衬底基板；多条数据线，位于衬底基板之上；第一绝缘层，位于多条数据线所在层远离衬底基板的一侧；多条栅线，位于第一绝缘层远离多条数据线所在层的一侧，且多条栅线的延伸方向与多条数据线的延伸方向交叉设置；第二绝缘层，位于多条栅线所在层远离第一绝缘层的一侧；第一电极，位于第二绝缘层远离栅线所在层的一侧，第一电极在衬底基板上的正投影至少位于各数据线在衬底基板上的正投影与各栅线在衬底基板上的正投影围成的区域内。

Description

显示基板、显示面板及显示装置
相关申请的交叉引用
本申请要求在2022年07月12日提交中国专利局、申请号为202210817485.8、申请名称为“显示基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示面板及显示装置。
背景技术
薄膜晶体管液晶显示装置(Thin Film Transistor Liquid Crystal Display，TFT-LCD)具有体积小、功耗低、画质高、无辐射和携带方便等特点，近年来得到了迅速地发展，已逐渐取代传统的阴极射线管显示装置(Cathode Ray Tube display，CRT)，在当前的平板显示器市场中占据了主导地位。
目前，TFT-LCD在各种大中小尺寸的产品上得到了广泛的应用，几乎涵盖了当今信息社会的主要电子产品，如液晶电视、高清晰度数字电视、电脑(台式和笔记本)、手机、平板电脑、导航仪、车载显示、投影显示、摄像机、数码相机、电子手表、计算器、电子仪器、仪表、公共显示和虚幻显示等。
发明内容
本公开实施例提供了一种显示基板、显示面板及显示装置，具体方案如下：
一方面，本公开实施例提供一种显示基板，包括：
衬底基板；
多条数据线，位于所述衬底基板之上；
第一绝缘层，位于所述多条数据线所在层远离所述衬底基板的一侧；
多条栅线，位于所述第一绝缘层远离所述多条数据线所在层的一侧，且所述多条栅线的延伸方向与所述多条数据线的延伸方向交叉设置；
第二绝缘层，位于所述多条栅线所在层远离所述第一绝缘层的一侧；
第一电极，位于所述第二绝缘层远离所述栅线所在层的一侧，所述第一电极在所述衬底基板上的正投影至少位于各所述数据线在所述衬底基板上的正投影与各所述栅线在所述衬底基板上的正投影围成的区域内。
在一些实施例中，在本公开实施例提供的上述显示基板中，至少部分所述数据线的局部在所述衬底基板上的正投影位于所述第一电极在所述衬底基板上的正投影内，所述第一电极包括多个狭缝，在所述栅线的延伸方向上，所述狭缝到所述数据线的最小距离大于1.5μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括：晶体管，所述晶体管的栅极与所述数据线同层、同材料设置，所述晶体管的第一极、第二极与所述栅线同层、同材料设置；所述晶体管的栅极与所述栅线电连接，所述晶体管的第一极与所述数据线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括：第一转接电极，所述第一转接电极与所述第一电极同层、同材料设置；
所述第一转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的第一过孔与所述晶体管的栅极电连接，并通过贯穿所述第二绝缘层的第二过孔与所述栅线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一过孔在所述衬底基板上的正投影位于所述晶体管的栅极在所述衬底基板上的正投影内，所述第一过孔在远离所述衬底基板方向上的口径逐渐增大，所述第一过孔包括靠近所述衬底基板的第一端口，所述第一端口在所述栅线延伸方向上的长度大于等于3μm，所述第一端口在所述数据线延伸方向上的宽度大于等于6μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二过 孔在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内，所述第二过孔在远离所述衬底基板方向上的口径逐渐增大，所述第二过孔包括靠近所述衬底基板的第二端口，所述第二端口在所述栅线延伸方向上的长度大于等于3μm，所述第二端口在所述数据线延伸方向上的宽度大于等于8μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述栅线包括与所述晶体管的第一极并排设置的凸出部，所述第一过孔在所述衬底基板上的正投影与所述凸出部在所述衬底基板上的正投影互不交叠，所述第二过孔在所述衬底基板上的正投影位于所述凸出部在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述凸出部在所述衬底基板上的正投影与所述晶体管的栅极在所述衬底基板上的正投影具有交叠区，所述交叠区被配置为设置隔垫物。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管的第一极与所述凸出部之间的最小距离大于等于5μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述栅线包括与所述凸出部一体设置的走线部，所述走线部在所述数据线延伸方向上的线宽大于等于5μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述走线部与所述凸出部形成容置凹槽，所述晶体管的第一极位于所述容置凹槽内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管的栅极在所述衬底基板上的正投影与所述容置凹槽在所述衬底基板上的正投影局部交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管的第一极包括沿所述栅线延伸方向延伸的第一分部，所述第一分部在所述衬底基板上的正投影与所述晶体管的栅极在所述衬底基板上的正投影局部交叠且与所述数据线在所述衬底基板上的正投影互不交叠，所述第一分部与所述走线部之间的距离大于等于5μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一分 部在所述数据线延伸方向上的宽度大于等于3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一过孔与所述第二过孔一体设置为第一通孔，所述第一通孔在所述衬底基板上的正投影位于所述第一转接电极在所述衬底基板上的正投影内，所述第一转接电极在所述衬底基板上的正投影在所述数据线延伸方向和/或所述栅线延伸方向上相对于所述第一通孔在所述衬底基板上的正投影单侧超出距离大于等于3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管的第一极在所述衬底基板上的正投影与所述第一转接电极在所述衬底基板上的正投影之间的最小距离大于等于3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括：第二转接电极，所述第二转接电极与所述第一电极同层、同材料设置；
所述第二转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的第三过孔与所述数据线电连接，并通过贯穿所述第二绝缘层的第四过孔与所述晶体管的第一极电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述数据线包括加宽部，所述第三过孔在所述衬底基板上的正投影位于所述加宽部在所述衬底基板上的正投影内，所述第三过孔在远离所述衬底基板方向上的口径逐渐增大，所述第三过孔包括靠近所述衬底基板的第三端口，所述第三端口在所述栅线延伸方向上的长度大于等于6μm，所述第三端口在所述数据线延伸方向上的宽度大于等于3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管的第一极包括第二分部，所述第二分部在所述衬底基板上的正投影位于所述加宽部在所述衬底基板上的正投影内，所述第四过孔在所述衬底基板上的正投影位于所述第二分部在所述衬底基板上的正投影内，所述第四过孔在远离所述衬底基板方向上的口径逐渐增大，所述第四过孔包括靠近所述衬底基板的第四端口，所述第四端口在所述栅线延伸方向上的长度大于等于8μm，所 述第四端口在所述数据线延伸方向上的宽度大于等于3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述加宽部与其电连接的所述晶体管的栅极之间的距离大于等于4.8μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述加宽部与其相邻且未连接的所述晶体管的栅极之间的距离大于等于11μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二转接电极在所述衬底基板上的正投影位于所述加宽部在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述栅线包括线宽大致均一的走线部、以及与所述走线部一体设置的凸出部，所述走线部与所述凸出部形成容置凹槽，所述加宽部在所述衬底基板上的正投影位于所述容置凹槽在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第三过孔与所述第四过孔一体设置为第二通孔，所述第二通孔在所述衬底基板上的正投影位于所述第二转接电极在所述衬底基板上的正投影内，所述第二转接电极在所述衬底基板上的正投影在所述数据线延伸方向和/或所述栅线延伸方向上相对于所述第二通孔在所述衬底基板上的正投影单侧超出距离大于等于3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括：第二电极，所述第二电极与所述第一电极构成电容，所述电容为存储电容或液晶电容，所述存储电容的所述第一电极为像素电极，所述液晶电容的所述第一电极或所述第二电极为像素电极，所述像素电极与所述晶体管的第二极电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二电极在所述衬底基板上的正投影位于各所述数据线在所述衬底基板上的正投影与各所述栅线在所述衬底基板上的正投影围成的区域内，所述第二电极在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影之间的距离 大于等于6.4μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二电极与所述数据线同层、不同材料。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括与所述第二电极同层、同材料的降阻线，所述降阻线与所述数据线接触电连接，所述降阻线在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影之间的距离大于等于4.8μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二电极为像素电极，所述显示基板还包括：第三转接电极，所述第三转接电极与所述第一电极同层、同材料设置；
所述第三转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的第五过孔与所述第二电极电连接，并通过贯穿所述第二绝缘层的第六过孔与所述晶体管的第二极电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第五过孔在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影内，所述第五过孔在远离所述衬底基板方向上的口径逐渐增大，所述第五过孔包括靠近所述衬底基板的第五端口，所述第五端口在所述栅线延伸方向上的长度大于等于3μm，所述第五端口在所述数据线延伸方向上的宽度大于等于6μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第六过孔在所述衬底基板上的正投影位于所述晶体管的第二极在所述衬底基板上的正投影内，所述第六过孔在远离所述衬底基板方向上的口径逐渐增大，所述第六过孔包括靠近所述衬底基板的第六端口，所述第六端口在所述栅线延伸方向上的长度大于等于3μm，所述第六端口在所述数据线延伸方向上的宽度大于等于8μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第五过孔与所述第六过孔一体设置为第三通孔，所述第三通孔在所述衬底基板上的 正投影位于所述第三转接电极在所述衬底基板上的正投影内，所述第三转接电极在所述衬底基板上的正投影在所述数据线延伸方向和/或所述栅线延伸方向上相对于所述第三通孔在所述衬底基板上的正投影单侧超出距离大于等于3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一电极包括避让槽，所述第三转接电极位于所述避让槽内，所述第三转接电极与所述避让槽之间的距离大于等于4μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括连接线，所述连接线与所述第一电极同层、同材料设置，所述连接线与所述数据线延伸方向上的非像素电极电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述栅线包括线宽大致均一的走线部、以及与所述走线部一体设置的凸出部，所述走线部与所述凸出部形成容置凹槽，所述连接线沿所述数据线的延伸方向跨越所述容置凹槽。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述连接线在所述衬底基板上的正投影与其距离最近的所述凸出部在所述衬底基板上的正投影之间的距离大于等于3μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述连接线在所述衬底基板上的正投影与其距离最近的所述数据线在所述衬底基板上的正投影之间的距离大于等于4μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述连接线在所述栅线延伸方向上的宽度大于等于4μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管的栅极通过贯穿所述第一绝缘层的第七过孔与所述栅线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管的第一极通过贯穿所述第一绝缘层的第八过孔与所述数据线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述晶体管 的第二极通过贯穿所述第一绝缘层的第九过孔与所述像素电极电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一绝缘层的厚度大于等于
Figure PCTCN2022141588-appb-000001
且小于等于
Figure PCTCN2022141588-appb-000002
所述第二绝缘层的厚度大于等于
Figure PCTCN2022141588-appb-000003
且小于等于
Figure PCTCN2022141588-appb-000004
另一方面，本公开实施例提供了一种显示面板，包括相对而置的显示基板和对向基板，以及位于所述显示基板和对向基板之间的液晶层，其中，所述显示基板为本公开实施例提供的上述显示基板。
在一些实施例中，在本公开实施例提供的上述显示面板中，所述第一电极包括正投影与所述数据线相互交叠的电极条，所述对向基板包括黑矩阵，所述黑矩阵包括沿所述数据线延伸方向延伸的黑矩阵条，所述黑矩阵条的局部在所述衬底基板上的正投影位于所述电极条在所述衬底基板上的正投影内，且所述黑矩阵条在所述栅线延伸方向上的宽度大于等于8μm。
另一方面，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示面板。
附图说明
图1为相关技术中高级超维场开关型液晶显示屏所含显示基板的结构示意图；
图2为相关技术中高开口率-高级超维场开关型液晶显示屏所含显示基板的结构示意图；
图3为相关技术中平面内开关型液晶显示屏所含显示基板的结构示意图；
图4为相关技术中垂直配向型液晶显示屏的结构示意图；
图5为本公开实施例提供的显示基板的一种结构示意图；
图6为本公开实施例提供的显示基板的又一种结构示意图；
图7为本公开实施例提供的显示基板的又一种结构示意图；
图8为沿图1中I-I'线的截面图；
图9为沿图1中II-II'线的截面图；
图10为沿图7中III-III'线的截面图；
图11为图5中第二电极所在层的结构示意图；
图12为图5中数据线所在层的结构示意图；
图13为图5中栅线所在层的结构示意图；
图14为图5中第一电极所在层的结构示意图；
图15为图6中第二电极所在层的结构示意图；
图16为图6中数据线所在层的结构示意图；
图17为图6中栅线所在层的结构示意图；
图18为图6中第一电极所在层的结构示意图；
图19为图7中第二电极所在层的结构示意图；
图20为图7中数据线所在层的结构示意图；
图21为图7中栅线所在层的结构示意图；
图22为图7中第一电极所在层的结构示意图；
图23为本公开实施例提供的显示基板的又一种结构示意图；
图24为沿图7中IV-IV'线的截面图；
图25为沿图7中V-V'线的截面图；
图26为沿图7中VI-VI'线的截面图；
图27为本公开实施例提供的栅线与晶体管的栅极电连接的一种示意图；
图28为本公开实施例提供的数据线与晶体管的第一极电连接的一种示意图；
图29为本公开实施例提供的第二电极与晶体管的第二极电连接的一种示意图；
图30为本公开实施例提供的显示基板的又一种结构示意图；
图31为沿图30中VII-VII'线的截面图；
图32为图30中第二电极所在层的结构示意图；
图33为图30中数据线所在层的结构示意图；
图34为图30中栅线所在层的结构示意图；
图35为图30中第一电极所在层的结构示意图；
图36为本公开实施例提供的显示基板的又一种结构示意图；
图37为图36中第二电极所在层的结构示意图；
图38为图36中数据线所在层的结构示意图；
图39为图36中栅线所在层的结构示意图；
图40为图36中第一电极所在层的结构示意图；
图41为本公开实施例提供的显示基板的又一种结构示意图；
图42为图41中数据线所在层的结构示意图；
图43为图41中栅线所在层的结构示意图；
图44为图41中第一电极所在层的结构示意图；
图45为本公开实施例提供的显示基板的又一种结构示意图；
图46为图48中数据线所在层的结构示意图；
图47为图48中栅线所在层的结构示意图；
图48为图48中第一电极所在层的结构示意图；
图49为本公开实施例提供的显示基板的又一种结构示意图；
图50为图49中数据线所在层的结构示意图；
图51为图49中栅线所在层的结构示意图；
图52为图49中第一电极所在层的结构示意图；
图53为本公开实施例提供的显示基板的又一种结构示意图；
图54为图53中数据线所在层的结构示意图；
图55为图53中栅线所在层的结构示意图；
图56为图53中第一电极所在层的结构示意图；
图57为本公开实施例提供的显示面板的结构示意图；
图58为沿图57中VIII-VIII'线的截面图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公 开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，在附图中，为了清楚，放大了层、膜、面板、区域等的厚度。在本公开中参照作为理想化实施方式的示意图的横截面图描述示例性实施方式。这样，将预计到作为例如制造技术和/或公差的结果的与图的形状的偏差。因而，本公开中描述的实施方式不应解释为限于如本公开中所示的区域的具体形状，而是包括由例如制造所导致的形状方面的偏差。例如，图示或描述为平坦的区域可典型地具有粗糙的和/或非线性的特征；所图示的尖锐的角可为圆形的等。因而，图中所示的区域在本质上是示意性的，并且它们的尺寸和形状不意图图示区域的精确形状、不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在下面的描述中，当元件或层被称作“在”另一元件或层“上”或“连接到”另一元件或层时，该元件或层可以直接在所述另一元件或层上、直接连接到所述另一元件或层，或者可以存在中间元件或中间层。当元件或层被称作“设置于”另一元件或层“的一侧”时，该元件或层可以直接在所述另 一元件或层的一侧，直接连接到所述另一元件或层，或者可以存在中间元件或中间层。然而，当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”另一元件或层时，不存在中间元件或中间层。术语“和/或”包括一个或更多个相关列出项的任意和全部组合。
相关技术中的液晶显示装置包括高级超维场开关(ADS)型液晶显示屏、高开口率-高级超维场开关(HADS)型液晶显示屏、平面内开关(IPS)型液晶显示屏和垂直配向(VA)型液晶显示屏。图1示出了高级超维场开关型液晶显示屏的显示基板，图2示出了高开口率-高级超维场开关型液晶显示屏的显示基板，图3示出了平面内开关型液晶显示屏的显示基板，图4示出了垂直配向型液晶显示屏。由图1和图4可见，数据线(SD)与其上层的电极(ITO)之间仅具有一个无机绝缘层(PVX)，导致二者之间的距离较小、耦合电容较大、数据线负载大；由图2和图3可见，数据线(SD)与其上层的电极(ITO)之间不仅具有无机绝缘层(PVX)，还增加了有机绝缘层(Org)，这样虽然可以通过有机绝缘层(Org)数据线(SD)与其上层的电极(ITO)之间的距离，从而减小二者的耦合电容、降低数据线(SD)的负载，但增加了制作有机绝缘层(Org)的工艺，由此增加了工艺复杂性。
为了改善相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图5至图22所示，包括：
衬底基板101，可选地，衬底基板101为玻璃等材质的刚性基板，或为聚酰亚胺等材质的柔性基板；
多条数据线(SD)102，位于衬底基板101之上，可选地，数据线102的材料包括金属材料，例如由钼、铝、钛、铜、合金等形成的单层或多层结构，示例性地，数据线102为钛金属层/铝金属层/钛金属层构成的叠层结构；
第一绝缘层103，位于多条数据线102所在层远离衬底基板101的一侧，可选地，第一绝缘层103为栅绝缘层(GI)，第一绝缘层103的材料可以为氧化硅、氮化硅、氮氧化硅等无机绝缘材料；
多条栅线(G)104，位于第一绝缘层103远离多条数据线102所在层的 一侧，且多条栅线104的延伸方向与多条数据线102的延伸方向交叉设置，可选地，栅线104的材料包括金属材料，例如由钼、铝、钛、铜、合金等形成的单层或多层结构，示例性地，栅线104为钛金属层/铝金属层/钛金属层构成的叠层结构；
第二绝缘层105，位于多条栅线104所在层远离第一绝缘层103的一侧，可选地，第一绝缘层103为无机绝缘层(PVX)，第二绝缘层105的材料为氧化硅、氮化硅、氮氧化硅等无机绝缘材料；
第一电极106，位于第二绝缘层105远离栅线104所在层的一侧，第一电极106在衬底基板101上的正投影至少位于各数据线102在衬底基板101上的正投影与各栅线104在衬底基板101上的正投影围成的区域内；可选地，第一电极106可以采用氧化铟锡(ITO)、氧化铟锡(IZO)、氧化锌(ZnO)等透明导电材料制作。
在本公开实施例提供的上述显示基板中，通过在衬底基板101上依次设置数据线102所在层、第一绝缘层103、栅线104所在层、第二绝缘层105和第一电极106所在层，使得数据线102所在层与距离衬底基板101较远的第一电极106所在层之间同时存在第一绝缘层103和第二绝缘层105这两个绝缘层，由此使得数据线102所在层与第一电极106所在层之间的距离较大，从而可减小数据线102与第一电极106之间的耦合电容，降低耦合电容对数据线102造成的负载，利于提高像素充电率，降低驱动芯片(IC)的温度；并且，由于本公开利用相关技术中的第一绝缘层103和第二绝缘层105减小了数据线102与第一电极106之间的耦合电容，因此无需增设有机绝缘层来减小数据线102与第一电极106之间的耦合电容，基于此，不会增加工艺复杂性。
在一些实施例中，在本公开实施例提供的上述显示基板中，第一绝缘层103的厚度大于等于
Figure PCTCN2022141588-appb-000005
且小于等于
Figure PCTCN2022141588-appb-000006
第二绝缘层105的厚度大于等于
Figure PCTCN2022141588-appb-000007
且小于等于
Figure PCTCN2022141588-appb-000008
可选地，第一绝缘层103的厚度为
Figure PCTCN2022141588-appb-000009
第二绝缘层105的厚度为
Figure PCTCN2022141588-appb-000010
此时，数据线102与第一电极106之间的 绝缘层厚度可达
Figure PCTCN2022141588-appb-000011
大大减小了数据线102负载，提高了像素充电率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5、图7、图8和图10所示，至少部分数据线102的局部在衬底基板101上的正投影位于第一电极106在衬底基板101上的正投影内，第一电极106包括多个狭缝S，在栅线104的延伸方向X上，狭缝S到数据线102的最小距离d 1大于1.5μm，换言之，第一电极106可以包括距离数据线102最近的两个狭缝S之间的电极条106’，电极条106’在衬底基板101上的正投影相对于数据线102在衬底基板101上的正投影超出1.5μm以上，例如超出2.2μm。这样设置，可以确保电极条106’在工艺波动后还能覆盖数据线102；并且，在电极条106’在衬底基板101上的正投影相对于数据线102在衬底基板101上的正投影超出2.2μm的情况下，还可以达到第一电极106的最佳光效设计效果。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5至图7、图9、图12、图13、图16、图17、图20、图21、图30、图33、图34、图36、图38、图39、图41至图43、图45至图47、图49至图51、图53至图55所示，还可以包括：晶体管107，晶体管107的栅极71与数据线102同层、同材料设置，晶体管107的第一极72、第二极73与栅线104同层、同材料设置，使得晶体管107为底栅型晶体管，以通过晶体管107的栅极71遮挡光线，避免光线照射晶体管107的沟道而影响晶体管107的稳定性。可选地，晶体管107的栅极71与栅线104电连接，晶体管107的第一极72与数据线102电连接，晶体管107的第二极73与像素电极电连接。在一些实施例中，晶体管107的有源层74的材料可以为非晶硅、多晶硅、氧化物等；晶体管107的第一极72可以为源极，第二极73为漏极，或者晶体管107的第一极72为漏极，第二极73为源极；晶体管107可以为P型晶体管或N型晶体管，在此不做限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5至图7、图14、图18、图22、图23、图24、图30、图35、图36、图40、图41、图44、图45、图48、图49、图52、图53和图56所示，还可以包括：第一转 接电极108，第一转接电极108与第一电极106同层、同材料设置；第一转接电极108通过贯穿第一绝缘层103和第二绝缘层105的第一过孔V 11与晶体管107的栅极71电连接，并通过贯穿第二绝缘层105的第二过孔V 12与栅线104电连接，即利用第一转接电极108实现了栅线104与晶体管107的栅极71的电连接。在此情况下，可在制作第一电极106的同时完成第一转接电极108的制作，避免额外增加制作第一转接电极108的工艺；且可通过一次构图工艺同时形成贯穿第二绝缘层105且用于实现第一转接电极108与栅线104电连接的第二过孔V 12，以及贯穿第一绝缘层103和第二绝缘层105且用于实现第一转接电极108与晶体管107的栅极71电连接的第一过孔V11，避免额外增加第一绝缘层103的构图工艺。应当理解的是，在一些实施例中，如图27所示，栅线104也可以通过贯穿第一绝缘层103的第七过孔V 1’与晶体管107的栅极71电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图24所示，第一过孔V 11在衬底基板101上的正投影位于晶体管107的栅极71在衬底基板101上的正投影内，第一过孔V 11在远离衬底基板101方向Z上的口径逐渐增大，第一过孔V 11包括靠近衬底基板101的第一端口，为确保第一转接电极108与晶体管107的栅极71的搭接电阻较小，且保证第一过孔V 11的形貌较好，可以设置第一端口在栅线104延伸方向X上的长度B大于等于3μm，第一端口在数据线102延伸方向Y上的宽度F'大于等于6μm，可选地，长度B为5.75μm，宽度F'为6μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图24所示，第二过孔V 12在衬底基板101上的正投影位于栅线104在衬底基板101上的正投影内，第二过孔V 12在远离衬底基板101方向Z上的口径逐渐增大，第二过孔V 12包括靠近衬底基板101的第二端口，为确保第一转接电极108与栅线104的搭接电阻较小，且保证第二过孔V 12的形貌较好，可以设置第二端口在栅线104延伸方向X上的长度C大于等于3μm，第二端口在数据线102延伸方向Y上的宽度F大于等于8μm，长度C为6.25μm，宽度F为8μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图24所示，栅线104包括与晶体管107的第一极72并排设置的凸出部41，第一过孔V 11在衬底基板101上的正投影与凸出部41在衬底基板101上的正投影互不交叠，第二过孔V 12在衬底基板101上的正投影位于凸出部41在衬底基板101上的正投影内。由图23可见，凸出部41的面积较大，便于通过第二过孔V 12实现与第一转接电极108的搭接，同时栅线104仅在凸出部41处增大线宽，避免了栅线104整体线宽较大，减少了栅线104对背光的遮挡，利于提升透过率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图24所示，为简化过孔设计，第一过孔V 11与第二过孔V 12可以一体设置为第一通孔V 1。可选地，第一通孔V 1在衬底基板101上的正投影位于第一转接电极108在衬底基板101上的正投影内，第一转接电极108在衬底基板101上的正投影在数据线102延伸方向Y和/或栅线104延伸方向X上相对于第一通孔V 1在衬底基板101上的正投影单侧超出距离A/D/E/G大于等于3μm，例如单侧超出距离A、D、E、G分别为5.55μm、5.75μm、5.5μm、5.5μm。在第一转接电极108在衬底基板101上的正投影在数据线102延伸方向Y和/或栅线104延伸方向X上相对于第一通孔V 1在衬底基板101上的正投影单侧超出距离A/D/E/G大于等于3μm的情况下，即使出现工艺波动，第一转接电极108依然可以很好地覆盖第一通孔V 1，减小了水汽通过第一通孔V 1接触凸出部41和栅极71而对其造成腐蚀的风险。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，凸出部41在衬底基板101上的正投影与晶体管107的栅极71在衬底基板101上的正投影具有交叠区OL，该交叠区OL相对平整，可用于放置隔垫物(PS)，以提高对隔垫物(PS)的支撑效果，有效防止隔垫物(PS)因支撑面不平整而发生滑动损伤配向膜(PI)造成漏光等不良。当然，在一些实施例中，隔垫物(PS)还可以设置在其他较平整的区域，此时，如图5所示，凸出部41在衬底基板101上的正投影也可以与晶体管107的栅极71在衬底基板101上的 正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，晶体管107的第一极72与凸出部41之间的最小距离u可以大于等于5μm，例如9.55μm。由于晶体管107的第一极72与凸出部41同层、同材料设置，在二者之间的最小距离u大于等于5μm的情况下，可以避免工艺波动、残留的导电异物(particle)等造成二者短接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，栅线104还可以包括与凸出部41一体设置的走线部42，走线部42在数据线102延伸方向Y上的线宽k大于等于5μm，例如8μm，以防止栅线104发生断线不良。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，走线部42与凸出部41形成容置凹槽AG，晶体管107的第一极72位于容置凹槽AG内，以避免晶体管107过多的占用像素区域，提高像素开口率，同时可有效避免晶体管107的第一极72与同层、同材料设置的栅线104短接。可选地，容置凹槽AG的开口朝向其所属栅线104通过晶体管107控制的像素电极的一侧，以便于晶体管107的第二极73在容置凹槽AG的开口侧与像素电极电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，晶体管107的栅极71在衬底基板101上的正投影与容置凹槽AG在衬底基板101上的正投影局部交叠，以便于晶体管107的栅极71在衬底基板101上的正投影与第一极72在衬底基板101上的正投影在容置凹槽AG相互交叠，从而使得第一极27的U型结构内的沟道区在栅极71与第一极72电场的驱动下形成导电通道。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，晶体管107的第一极72包括沿栅线104延伸方向X延伸的第一分部721，第一分部721在衬底基板101上的正投影与晶体管107的栅极71在衬底基板101上的正投影局部交叠且与数据线102在衬底基板101上的正投影互不交叠， 为防止第一分部721与同层、同材料设置的走线部42短接，可以设置第一分部721与走线部42之间的距离j大于等于5μm，例如9.25μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，为防止第一分部721断线，如图23所示，可以设置第一分部721在数据线102延伸方向Y上的宽度i大于等于3μm，例如6μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，晶体管107的第一极72在衬底基板101上的正投影与第一转接电极108在衬底基板101上的正投影之间的最小距离t大于等于3μm，例如6.55μm，以防止因工艺波动等因素造成第一转接电极108与第一极72的U型结构内沟道区交叠，影响晶体管107的开关特性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5至图7、图14、图18、图22、图23、图25、图30、图35、图36、图40、图41、图44、图45、图48、图49、图52、图53和图56所示，还可以包括：第二转接电极109，第二转接电极109与第一电极106同层、同材料设置；第二转接电极109通过贯穿第一绝缘层103和第二绝缘层105的第三过孔V 21与数据线102电连接，并通过贯穿第二绝缘层105的第四过孔V 22与晶体管107的第一极72电连接，即利用第二转接电极109实现了数据线102与晶体管107的第一极72的电连接。在此情况下，可在制作第一电极106的同时完成第二转接电极109的制作，避免额外增加制作第二转接电极109的工艺；且可通过一次构图工艺同时形成贯穿第二绝缘层105且用于实现第二转接电极109与晶体管107的第一极72电连接的过孔，以及贯穿第一绝缘层103和第二绝缘层105且用于实现第二转接电极109与数据线102电连接的过孔，避免额外增加第一绝缘层103的构图工艺。应当理解的是，在一些实施例中，如图28所示，晶体管107的第一极72也可以通过贯穿第一绝缘层103的第八过孔V 2'与数据线102电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图25所示，数据线102包括加宽部21，为减小数据线102与第二转接电极109 的搭接电阻且保证第三过孔V 21的形貌较好，可以设置第三过孔V 21在衬底基板101上的正投影位于加宽部21在衬底基板101上的正投影内，第三过孔V 21在远离衬底基板101方向Z上的口径逐渐增大，第三过孔V 21包括靠近衬底基板101的第三端口，第三端口在栅线104延伸方向X上的长度b'大于等于6μm，第三端口在数据线102延伸方向Y上的宽度e大于等于3μm，可选地，长度b'为8μm，宽度e为5.75μm。继续参见图23可见，加宽部21的面积较大，便于通过第三过孔V 21实现加宽部21与第二转接电极109的搭接，同时数据线102仅在加宽部21处增大线宽，避免了数据线102整体线宽较大，减少了数据线102对背光的遮挡，利于提升透过率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图25所示，晶体管107的第一极72包括第二分部722，第二分部722在衬底基板101上的正投影位于加宽部21在衬底基板101上的正投影内，为减小第一极72与第二转接电极109的搭接电阻且保证第四过孔V 22的形貌较好，可以设置第四过孔V 22在衬底基板101上的正投影位于第二分部722在衬底基板101上的正投影内，第四过孔V 22在远离衬底基板101方向Z上的口径逐渐增大，第四过孔V 22包括靠近衬底基板101的第四端口，第四端口在栅线104延伸方向X上的长度b大于等于8μm，第四端口在数据线102延伸方向Y上的宽度f大于等于3μm，可选地，长度b为8μm，宽度f为6.25μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，为简化过孔设计，如图23所示，可以使得第三过孔V 21与第四过孔V 22一体设置为第二通孔V 2。可选地，第二通孔V 2在衬底基板101上的正投影位于第二转接电极109在衬底基板101上的正投影内，第二转接电极109在衬底基板101上的正投影在数据线102延伸方向Y和/或栅线104延伸方向X上相对于第二通孔V 2在衬底基板101上的正投影单侧超出距离a/c/d/g大于等于3μm。在第二转接电极109在衬底基板101上的正投影在数据线102延伸方向Y和/或栅线104延伸方向X上相对于第二通孔V 2在衬底基板101上的正投影单侧超出距离a/c/d/g大于等于3μm的情况下，即使出现工艺波动，第二转接电极109依然 可以很好地覆盖第二通孔V 2，减小了水汽通过第二通孔V 2接触加宽部21和第一极72而对其造成腐蚀的风险。
在一些实施例中，在本公开实施例提供的上述显示基板中，为避免加宽部21与其同层、同材料设置的栅极71之间短接，且使得晶体管107的结构较紧凑，如图23所示，可以设置加宽部21与其电连接的晶体管107的栅极71之间的距离h大于等于4.8μm，例如5μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，在布线空间充足的情况下，为更好地避免加宽部21与其相邻且未连接的晶体管107的栅极71短接，可以加大二者之间的距离，例如设置加宽部21与其相邻且未连接的晶体管107的栅极71之间的距离y大于等于11μm，可选地，距离y为13μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，第二转接电极109在衬底基板101上的正投影位于加宽部21在衬底基板101上的正投影内，这样数据线102与第二转接电极109之间就可以具有足够大的交叠区域，保证数据线102与第二转接电极109的电连接效果较好。
考虑到数据线102设置加宽部21后，加宽部21若与栅线104交叠设置，则会造成数据线102与栅线104之间的耦合电容较大。基于此，为了减小数据线102与栅线104之间的耦合电容，降低数据线102与栅线104上的信号相互干扰，在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，可以设置加宽部21在衬底基板101上的正投影位于容置凹槽AG在衬底基板101上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5至图7、图11、图15、图19、图23、图24、图32、图36、图37、图40、图41、图44、图45、图48至图50、图52至图54、图56所示，还可以包括：第二电极110，第二电极110与第一电极106构成电容，电容为存储电容(Cst)或液晶电容(Clc)，存储电容(Cst)的第一电极106为像素电极，液晶电容(Clc)的第一电极106或第二电极110为像素电极(P)，像素电极与晶体管107的 第二极73电连接，可选地，像素电极位于数据线102在衬底基板101上的正投影与栅线104在衬底基板101上的正投影围成的像素区域内，为便于像素电极与晶体管107的第二极73搭接，可以设置晶体管107的第二极73在衬底基板101上的正投影自第一极72的U型结构内延伸至与像素区域的像素电极局部交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图8、图10和图23所示，第二电极110在衬底基板101上的正投影位于各数据线102在衬底基板101上的正投影与各栅线104在衬底基板101上的正投影围成的区域内，第二电极110在衬底基板101上的正投影与数据线102在衬底基板101上的正投影之间的距离d 2大于等于6.4μm。在满足第二电极110在衬底基板101上的正投影与数据线102在衬底基板101上的正投影之间的距离d 2大于等于6.4μm的条件下，既可以防止因工艺波动导致第二电极110和数据线102发生交叠，又可以避免数据线102处及其附近的暗场区域太大，透过率损失较大。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图8所示，第二电极110可以与数据线102同层、不同材料。在此情况下，可首先采用一张掩膜板(mask)制作第二电极110的图案，然后采用另一张掩膜板制作数据线102的图案。可选地，为保证透过率，第二电极110的材料为氧化铟锡(ITO)、氧化铟锡(IZO)、氧化锌(ZnO)等透明导电材料。
在一些实施例中，在本公开实施例提供的上述显示基板中，还可以在依次形成用于制作第二电极110的第一导电膜层、以及用于制作数据线102的第二导电膜层之后，采用一张掩膜板(mask)对第一导电膜层和第二导电膜层进行构图形成第二电极110和数据线102的图案，在此情况下，数据线102的遮挡作用会导致数据线102下方存在第一导电膜层的图案，具体如图10所示，显示基板还包括与第二电极110同层、同材料的降阻线111，降阻线111与数据线102接触电连接，为避免降阻线111与第二电极110短接，可以设置降阻线111在衬底基板101上的正投影与第二电极110在衬底基板101上的正 投影之间的距离d 3大于等于4.8μm，相当于降阻线111在衬底基板101上的正投影相对于数据线102在衬底基板101上的正投影单侧超出1.6μm。可选地，为保证透过率，第二电极110的材料为氧化铟锡(ITO)、氧化铟锡(IZO)、氧化锌(ZnO)等透明导电材料。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图26所示，第二电极110为像素电极，显示基板还包括：第三转接电极112，第三转接电极112与第一电极106同层、同材料设置；第三转接电极112通过贯穿第一绝缘层103和第二绝缘层105的第五过孔V 31与第二电极106电连接，并通过贯穿第二绝缘层105的第六过孔V 32与晶体管107的第二极73电连接。在此情况下，可在制作第一电极106的同时完成第三转接电极112的制作，避免额外增加制作第三转接电极112的工艺；且可通过一次构图工艺同时形成贯穿第二绝缘层105且用于实现第三转接电极108与第二极73电连接的第六过孔V 32，以及贯穿第一绝缘层103和第二绝缘层105且用于实现第三转接电极103与晶体管107的第二极73电连接的第五过孔V 31，避免额外增加第一绝缘层103的构图工艺。应当理解的是，在一些实施例中，如图29所示，第二电极110也可以通过贯穿第一绝缘层103的第九过孔V 3’与晶体管107的第二极73电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图26所示，为确保第三转接电极112与第二电极110的搭接电阻较小，且保证第五过孔V 31的形貌较好，可以设置第五过孔V 31在衬底基板101上的正投影位于第二电极110在衬底基板101上的正投影内，第五过孔V 31在远离衬底基板101方向Z上的口径逐渐增大，第五过孔V 31包括靠近衬底基板101的第五端口，第五端口在栅线104延伸方向X上的长度m大于等于3μm，第五端口在数据线102延伸方向Y上的宽度r大于等于6μm，可选地，长度m为4.75μm，宽度r为6μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23和图26所示，为确保第三转接电极112与晶体管107的第二极73的搭接电阻较小， 且保证第六过孔V 32的形貌较好，可以设置第六过孔V 32在衬底基板101上的正投影位于晶体管107的第二极73在衬底基板101上的正投影内，第六过孔V 32在远离衬底基板101方向Z上的口径逐渐增大，第六过孔V 32包括靠近衬底基板101的第六端口，第六端口在栅线104延伸方向X上的长度n大于等于3μm，第六端口在数据线102延伸方向Y上的宽度r'大于等于8μm，可选地，长度n为6.25μm，宽度r'为8μm。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，为简化过孔设计，可以将第五过孔V 31与第六过孔V 32一体设置为第三通孔V 3。可选地，第三通孔V 3在衬底基板101上的正投影位于第三转接电极112在衬底基板101上的正投影内，第三转接电极112在衬底基板101上的正投影在数据线102延伸方向Y和/或栅线104延伸方向X上相对于第三通孔V 3在衬底基板101上的正投影单侧超出距离l/o/q/s大于等于3μm；在此条件下，即使出现工艺波动，第三转接电极112依然可以很好地覆盖第三通孔V 3，减小了水汽通过第三通孔V 3接触第二极73而对其造成腐蚀的风险。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，第一电极106包括避让槽AS，可选地，避让槽AS的开口朝向容置凹槽AG，第三转接电极112位于避让槽AS内，且第三转接电极112与避让槽AS之间的距离p大于等于4μm，以避免同层、同材料设置的第三转接电极112与第一电极106短接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，还可以包括第一连接线113，该第一连接线113与第一电极106同层、同材料设置，第一连接线113与数据线102延伸方向Y上的非像素电极(例如图23中的第一电极106)电连接，以使得电容中非像素电极的整体电阻较小，同时电容中非像素电极在数据线102延伸方向Y上的电压均一性和稳定性也得到了提升。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，第一连接线113可以沿数据线102的延伸方向Y跨越容置凹槽AG，可选地， 第一连接线113跨越凸出部41与其相邻且未电连接的加宽部21之间的距离y范围内的容置凹槽AG，这样设置可以使得第一连接线113与栅线104之间的耦合电容较小。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，第一连接线113在衬底基板101上的正投影与其距离最近的凸出部41在衬底基板101上的正投影之间的距离v大于等于3μm，以避免因工艺波动等因素造成第一连接线113与凸出部41相互交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，第一连接线113在衬底基板101上的正投影与其距离最近的数据线102(具体为数据线102的加宽部21)在衬底基板101上的正投影之间的距离x大于等于4μm，以避免因工艺波动等因素造成第一连接线113与数据线102相互交叠。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图23所示，第一连接线113在栅线X延伸方向Y上的宽度w大于等于4μm，以防止第一连接线113发生断线不良。
在一些实施例中，如图5至图7、图11、图14、图15、图18、图19和图22所示，第一电极106和第二电极110在由数据线102与栅线104围成的区域内交叠设置构成液晶电容(Clc)，其中，第一电极106为狭缝(slit)状的公共电极(Com)，第二电极110为块状的像素电极，另外，由图16、图18、图20和图22可见，第一电极106可以为双畴电极，数据线102在加宽部21之外的其余部分的延伸方向可以与双畴电极的延伸方向相同，在此情况下，本公开中的数据线102的延伸方向Y即表示数据线102的整体延伸方向——列方向。
在一些实施例中，如图30至图40所示，第一电极106和第二电极110在由数据线102与栅线104围成的区域内交叠设置构成液晶电容(Clc)，其中，第一电极106为狭缝(slit)状的像素电极，第二电极110为块状的公共电极，并且第一电极106在衬底基板101上的正投影、以及第二电极110在衬底基 板101上的正投影均仅位于由数据线102和栅线104围成的区域内。在一些实施例中，如图31所示，第二电极110可以与数据线102同层设置，二者之间具有间隙，但二者的材料不同，相较于第二电极110与数据线102异层绝缘设置的方案，本公开可以减少膜层数量，利于实现产品的轻薄化设计。
在一些实施例中，如图41至图48所示，第一电极106与第二电极110同层、同材料设置，第一电极106、第二电极110均为梳状结构，且第一电极106的梳齿部与第二电极110的梳齿部交替排布，这样第一电极106与第二电极110在同层存在正对的侧面，形成液晶电容(Clc)。可选地，第一电极106为与晶体管107的第二极73电连接的像素电极，第二电极110为公共电极。在一些实施例中，第一电极106在衬底基板101上的正投影仅位于数据线102与栅线104围成的区域内，第二电极110在衬底基板101上的正投影不仅位于数据线102与栅线104围成的区域内，还覆盖数据线102中加宽部21之外的绝大部分在衬底基板101上的正投影，使得第二电极110的面积较大，从而可在第二电极110上开设更多的梳齿部之间的间隙，以提高透过率，并提升光效。可选地，第一电极106的梳齿部、以及第二电极110的梳齿部可以为折线形状，例如为呈钝角的V字形状。数据线102在加宽部21之外的其余部分的延伸方向可以与梳齿部的延伸方向相同，在此情况下，本公开中的数据线102的延伸方向Y即表示数据线102的整体延伸方向——列方向。
可选地，在图5至图7、图30和图41中，还可以通过第二连接线114连接栅线104延伸方向上的同排公共电极(即图5至图7中的第一电极106、以及图30和图41中的第二电极110)，以降低公共电极的整体电阻，同时公共电极在栅线104延伸方向X上的电压均一性和稳定性也得到了提升。在一些实施例中，如图13、图17、图21、图34、图39、图43、图47、图51和图55所示，第二连接线114可以与栅线104同层、同材料设置。在公共电极为第一电极106(如图5至图7所示)，或公共电极为第二电极110且与第一电极106同层、同材料设置(如图41所示)的情况下，第二连接线114通过贯穿第二绝缘层105的过孔与公共电极电连接；在公共电极为第二电极110(如 图30所示)的情况下，第二连接线114通过与第一电极106同层、同材料的第一连接线113与栅线104延伸方向X上的同排公共电极电连接。
在一些实施例中，如图49至图56所示，第一电极106与第二电极110构成存储电容(Cst)。第一电极106为狭缝电极，且第一电极106包括“十”字型主体部MB，第一电极106的狭缝分布在“十”字型主体部MB限定出的四个区域，在对角方向上的两个区域内狭缝延伸方向相同，相邻两个区域内的狭缝延伸方向相交。第二电极110与数据线102同层、同材料设置，第二电极110在衬底基板101上的正投影与“十”字型主体部MB在衬底基板101上的正投影相互交叠。在一些实施例中，在栅线104延伸方向X上的同排第二电极110之间可通过第一连接线113电连接，以降低第二电极110的整体电阻，同时第二电极110在栅线104延伸方向X上的电压均一性和稳定性也得到了提升。
基于同一发明构思，本公开实施例提供了一种显示面板，如图57和图58所示，包括相对而置的显示基板001和对向基板002，以及位于显示基板001和对向基板003之间的液晶层003，其中，显示基板001为本公开实施例提供的上述显示基板001。由于该显示面板解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示面板的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述显示面板中，如图57和图58所示，第一电极106包括正投影与数据线102相互交叠的电极条106'，对向基板002包括黑矩阵201，黑矩阵201包括沿数据线102延伸方向Y延伸的第一黑矩阵条11，第一黑矩阵条11的局部在衬底基板101上的正投影位于电极条106'在衬底基板101上的正投影内，因电极条106'处为暗场区域，故将第一黑矩阵条11设置在电极条106'处并不会影响透过率。可选地，第一黑矩阵条11在栅线104延伸方向Y上的宽度大于等于8μm，以通过黑矩阵条11避免斜视角串色问题。在一些实施例中，黑矩阵201还可以包括沿栅线104延伸方向X延伸的第二黑矩阵条12，可选地，栅线104在衬底基板101上的 正投影位于第二黑矩阵条12在衬底基板101上的正投影内。
在一些实施例中，在本公开实施例提供的上述显示面板中，还可以包括在显示基板001和对向基板002之间包围液晶层003的密封胶，位于显示基板靠近液晶层一侧的第一配向层，位于对向基板靠近液晶层一侧的第二配向层，位于显示基板001远离液晶层003一侧的第一偏光片，以及位于对向基板002远离液晶层003一侧的第二偏光片等，其中第一偏光片的偏振方向与第二偏光片的偏振方向相互垂直。对于显示面板中其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示面板。由于该显示装置解决问题的原理与上述显示面板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见本公开实施例提供的上述显示面板的实施，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述显示装置中，还可以包括背光模组，显示面板设置在背光模组的出光侧。背光模组可以为直下式背光模组，也可以为侧入式背光模组。可选地，侧入式背光模组可以包括灯条、层叠设置的反射片、导光板、扩散片、棱镜组等，灯条位于导光板厚度方向的一侧。直下式背光模组可以包括矩阵光源、在矩阵光源出光侧层叠设置的反射片、扩散板和增亮膜等，反射片包括与矩阵光源中各灯珠的位置正对设置的开孔。灯条中的灯珠、矩阵光源中的灯珠可以为发光二极管(LED)，例如微型发光二极管(Mini LED、Micro LED等)。
亚毫米量级甚至微米量级的微型发光二极管和有机发光二极管(OLED)一样属于自发光器件。其与有机发光二极管一样，有着高亮度、超低延迟、超大可视角度等一系列优势。并且由于无机发光二极管发光是基于性质更加稳定、电阻更低的金属半导体实现发光，因此它相比基于有机物实现发光的有机发光二极管来说，有着功耗更低、更耐高温和低温、使用寿命更长的优势。且在微型发光二极管作为背光源时，能够实现更精密的动态背光效果， 在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区域之间造成的眩光现象，优化视觉体验。
在一些实施例中，本公开实施例提供的上述显示装置可以为：投影仪、3D打印机、虚拟现实设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (45)

  1. 一种显示基板，其中，包括：
    衬底基板；
    多条数据线，位于所述衬底基板之上；
    第一绝缘层，位于所述多条数据线所在层远离所述衬底基板的一侧；
    多条栅线，位于所述第一绝缘层远离所述多条数据线所在层的一侧，且所述多条栅线的延伸方向与所述多条数据线的延伸方向交叉设置；
    第二绝缘层，位于所述多条栅线所在层远离所述第一绝缘层的一侧；
    第一电极，位于所述第二绝缘层远离所述栅线所在层的一侧，所述第一电极在所述衬底基板上的正投影至少位于各所述数据线在所述衬底基板上的正投影与各所述栅线在所述衬底基板上的正投影围成的区域内。
  2. 如权利要求1所述的显示基板，其中，至少部分所述数据线的局部在所述衬底基板上的正投影位于所述第一电极在所述衬底基板上的正投影内，所述第一电极包括多个狭缝，在所述栅线的延伸方向上，所述狭缝到所述数据线的最小距离大于1.5μm。
  3. 如权利要求1或2所述的显示基板，其中，还包括：晶体管，所述晶体管的栅极与所述数据线同层、同材料设置，所述晶体管的第一极、第二极与所述栅线同层、同材料设置；所述晶体管的栅极与所述栅线电连接，所述晶体管的第一极与所述数据线电连接。
  4. 如权利要求3所述的显示基板，其中，还包括：第一转接电极，所述第一转接电极与所述第一电极同层、同材料设置；
    所述第一转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的第一过孔与所述晶体管的栅极电连接，并通过贯穿所述第二绝缘层的第二过孔与所述栅线电连接。
  5. 如权利要求4所述的显示基板，其中，所述第一过孔在所述衬底基板上的正投影位于所述晶体管的栅极在所述衬底基板上的正投影内，所述第一 过孔在远离所述衬底基板方向上的口径逐渐增大，所述第一过孔包括靠近所述衬底基板的第一端口，所述第一端口在所述栅线延伸方向上的长度大于等于3μm，所述第一端口在所述数据线延伸方向上的宽度大于等于6μm。
  6. 如权利要求4或5所述的显示基板，其中，所述第二过孔在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内，所述第二过孔在远离所述衬底基板方向上的口径逐渐增大，所述第二过孔包括靠近所述衬底基板的第二端口，所述第二端口在所述栅线延伸方向上的长度大于等于3μm，所述第二端口在所述数据线延伸方向上的宽度大于等于8μm。
  7. 如权利要求6所述的显示基板，其中，所述栅线包括与所述晶体管的第一极并排设置的凸出部，所述第一过孔在所述衬底基板上的正投影与所述凸出部在所述衬底基板上的正投影互不交叠，所述第二过孔在所述衬底基板上的正投影位于所述凸出部在所述衬底基板上的正投影内。
  8. 如权利要求7所述的显示基板，其中，所述凸出部在所述衬底基板上的正投影与所述晶体管的栅极在所述衬底基板上的正投影具有交叠区，所述交叠区被配置为设置隔垫物。
  9. 如权利要求7或8所述的显示基板，其中，所述晶体管的第一极与所述凸出部之间的最小距离大于等于5μm。
  10. 如权利要求7～9任一项所述的显示基板，其中，所述栅线包括与所述凸出部一体设置的走线部，所述走线部在所述数据线延伸方向上的线宽大于等于5μm。
  11. 如权利要求10所述的显示基板，其中，所述走线部与所述凸出部形成容置凹槽，所述晶体管的第一极位于所述容置凹槽内。
  12. 如权利要求11所述的显示基板，其中，所述晶体管的栅极在所述衬底基板上的正投影与所述容置凹槽在所述衬底基板上的正投影局部交叠。
  13. 如权利要求11或12所述的显示基板，其中，所述晶体管的第一极包括沿所述栅线延伸方向延伸的第一分部，所述第一分部在所述衬底基板上的正投影与所述晶体管的栅极在所述衬底基板上的正投影局部交叠且与所述 数据线在所述衬底基板上的正投影互不交叠，所述第一分部与所述走线部之间的距离大于等于5μm。
  14. 如权利要求11或12所述的显示基板，其中，所述第一分部在所述数据线延伸方向上的宽度大于等于3μm。
  15. 如权利要求3～14任一项所述的显示基板，其中，所述第一过孔与所述第二过孔一体设置为第一通孔，所述第一通孔在所述衬底基板上的正投影位于所述第一转接电极在所述衬底基板上的正投影内，所述第一转接电极在所述衬底基板上的正投影在所述数据线延伸方向和/或所述栅线延伸方向上相对于所述第一通孔在所述衬底基板上的正投影单侧超出距离大于等于3μm。
  16. 如权利要求3～15任一项所述的显示基板，其中，所述晶体管的第一极在所述衬底基板上的正投影与所述第一转接电极在所述衬底基板上的正投影之间的最小距离大于等于3μm。
  17. 如权利要求3～16任一项所述的显示基板，其中，还包括：第二转接电极，所述第二转接电极与所述第一电极同层、同材料设置；
    所述第二转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的第三过孔与所述数据线电连接，并通过贯穿所述第二绝缘层的第四过孔与所述晶体管的第一极电连接。
  18. 如权利要求17所述的显示基板，其中，所述数据线包括加宽部，所述第三过孔在所述衬底基板上的正投影位于所述加宽部在所述衬底基板上的正投影内，所述第三过孔在远离所述衬底基板方向上的口径逐渐增大，所述第三过孔包括靠近所述衬底基板的第三端口，所述第三端口在所述栅线延伸方向上的长度大于等于6μm，所述第三端口在所述数据线延伸方向上的宽度大于等于3μm。
  19. 如权利要求18所述的显示基板，其中，所述晶体管的第一极包括第二分部，所述第二分部在所述衬底基板上的正投影位于所述加宽部在所述衬底基板上的正投影内，所述第四过孔在所述衬底基板上的正投影位于所述第二分部在所述衬底基板上的正投影内，所述第四过孔在远离所述衬底基板方 向上的口径逐渐增大，所述第四过孔包括靠近所述衬底基板的第四端口，所述第四端口在所述栅线延伸方向上的长度大于等于8μm，所述第四端口在所述数据线延伸方向上的宽度大于等于3μm。
  20. 如权利要求18或19所述的显示基板，其中，所述加宽部与其电连接的所述晶体管的栅极之间的距离大于等于4.8μm。
  21. 如权利要求18～20任一项所述的显示基板，其中，所述加宽部与其相邻且未连接的所述晶体管的栅极之间的距离大于等于11μm。
  22. 如权利要求18～21任一项所述的显示基板，其中，所述第二转接电极在所述衬底基板上的正投影位于所述加宽部在所述衬底基板上的正投影内。
  23. 如权利要求18～22任一项所述的显示基板，其中，所述栅线包括线宽大致均一的走线部、以及与所述走线部一体设置的凸出部，所述走线部与所述凸出部形成容置凹槽，所述加宽部在所述衬底基板上的正投影位于所述容置凹槽在所述衬底基板上的正投影内。
  24. 如权利要求17～23任一项所述的显示基板，其中，所述第三过孔与所述第四过孔一体设置为第二通孔，所述第二通孔在所述衬底基板上的正投影位于所述第二转接电极在所述衬底基板上的正投影内，所述第二转接电极在所述衬底基板上的正投影在所述数据线延伸方向和/或所述栅线延伸方向上相对于所述第二通孔在所述衬底基板上的正投影单侧超出距离大于等于3μm。
  25. 如权利要求3～24任一项所述的显示基板，其中，还包括：第二电极，所述第二电极与所述第一电极构成电容，所述电容为存储电容或液晶电容，所述存储电容的所述第一电极为像素电极，所述液晶电容的所述第一电极或所述第二电极为像素电极，所述像素电极与所述晶体管的第二极电连接。
  26. 如权利要求25所述的显示基板，其中，所述第二电极在所述衬底基板上的正投影位于各所述数据线在所述衬底基板上的正投影与各所述栅线在所述衬底基板上的正投影围成的区域内，所述第二电极在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影之间的距离大于等于6.4μm。
  27. 如权利要求26所述的显示基板，其中，所述第二电极与所述数据线 同层、不同材料。
  28. 如权利要求27所述的显示基板，其中，还包括与所述第二电极同层、同材料的降阻线，所述降阻线与所述数据线接触电连接，所述降阻线在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影之间的距离大于等于4.8μm。
  29. 如权利要求27或28所述的显示基板，其中，所述第二电极为像素电极，所述显示基板还包括：第三转接电极，所述第三转接电极与所述第一电极同层、同材料设置；
    所述第三转接电极通过贯穿所述第一绝缘层和所述第二绝缘层的第五过孔与所述第二电极电连接，并通过贯穿所述第二绝缘层的第六过孔与所述晶体管的第二极电连接。
  30. 如权利要求29所述的显示基板，其中，所述第五过孔在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影内，所述第五过孔在远离所述衬底基板方向上的口径逐渐增大，所述第五过孔包括靠近所述衬底基板的第五端口，所述第五端口在所述栅线延伸方向上的长度大于等于3μm，所述第五端口在所述数据线延伸方向上的宽度大于等于6μm。
  31. 如权利要求29或30所述的显示基板，其中，所述第六过孔在所述衬底基板上的正投影位于所述晶体管的第二极在所述衬底基板上的正投影内，所述第六过孔在远离所述衬底基板方向上的口径逐渐增大，所述第六过孔包括靠近所述衬底基板的第六端口，所述第六端口在所述栅线延伸方向上的长度大于等于3μm，所述第六端口在所述数据线延伸方向上的宽度大于等于8μm。
  32. 如权利要求29～31任一项所述的显示基板，其中，所述第五过孔与所述第六过孔一体设置为第三通孔，所述第三通孔在所述衬底基板上的正投影位于所述第三转接电极在所述衬底基板上的正投影内，所述第三转接电极在所述衬底基板上的正投影在所述数据线延伸方向和/或所述栅线延伸方向上相对于所述第三通孔在所述衬底基板上的正投影单侧超出距离大于等于3μm。
  33. 如权利要求29～32任一项所述的显示基板，其中，所述第一电极包 括避让槽，所述第三转接电极位于所述避让槽内，所述第三转接电极与所述避让槽之间的距离大于等于4μm。
  34. 如权利要求25～33任一项所述的显示基板，其中，还包括连接线，所述连接线与所述第一电极同层、同材料设置，所述连接线与所述数据线延伸方向上的非像素电极电连接。
  35. 如权利要求34所述的显示基板，其中，所述栅线包括线宽大致均一的走线部、以及与所述走线部一体设置的凸出部，所述走线部与所述凸出部形成容置凹槽，所述连接线沿所述数据线的延伸方向跨越所述容置凹槽。
  36. 如权利要求35所述的显示基板，其中，所述连接线在所述衬底基板上的正投影与其距离最近的所述凸出部在所述衬底基板上的正投影之间的距离大于等于3μm。
  37. 如权利要求34～36任一项所述的显示基板，其中，所述连接线在所述衬底基板上的正投影与其距离最近的所述数据线在所述衬底基板上的正投影之间的距离大于等于4μm。
  38. 如权利要求34～37任一项所述的显示基板，其中，所述连接线在所述栅线延伸方向上的宽度大于等于4μm。
  39. 如权利要求3所述的显示基板，其中，所述晶体管的栅极通过贯穿所述第一绝缘层的第七过孔与所述栅线电连接。
  40. 如权利要求3所述的显示基板，其中，所述晶体管的第一极通过贯穿所述第一绝缘层的第八过孔与所述数据线电连接。
  41. 如权利要求25所述的显示基板，其中，所述晶体管的第二极通过贯穿所述第一绝缘层的第九过孔与所述像素电极电连接。
  42. 如权利要求1～41任一项所述的显示基板，其中，所述第一绝缘层的厚度大于等于
    Figure PCTCN2022141588-appb-100001
    且小于等于
    Figure PCTCN2022141588-appb-100002
    所述第二绝缘层的厚度大于等于
    Figure PCTCN2022141588-appb-100003
    且小于等于
    Figure PCTCN2022141588-appb-100004
  43. 一种显示面板，其中，包括相对而置的显示基板和对向基板，以及位于所述显示基板和对向基板之间的液晶层，其中，所述显示基板为如权利 要求1～42任一项所述的显示基板。
  44. 如权利要求43所述的显示面板，其中，所述第一电极包括正投影与所述数据线相互交叠的电极条，所述对向基板包括黑矩阵，所述黑矩阵包括沿所述数据线延伸方向延伸的黑矩阵条，所述黑矩阵条的局部在所述衬底基板上的正投影位于所述电极条在所述衬底基板上的正投影内，且所述黑矩阵条在所述栅线延伸方向上的宽度大于等于8μm。
  45. 一种显示装置，其中，包括如权利要求43或44所述的显示面板。
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US20210327958A1 (en) * 2019-06-28 2021-10-21 Kunshan Go-Visionox Opto-Electronics Co., Ltd. Display substrate, display panel and display device
CN112639598A (zh) * 2019-07-24 2021-04-09 京东方科技集团股份有限公司 显示基板及显示面板
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