WO2024103981A1 - 显示面板及电子设备 - Google Patents

显示面板及电子设备 Download PDF

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Publication number
WO2024103981A1
WO2024103981A1 PCT/CN2023/122070 CN2023122070W WO2024103981A1 WO 2024103981 A1 WO2024103981 A1 WO 2024103981A1 CN 2023122070 W CN2023122070 W CN 2023122070W WO 2024103981 A1 WO2024103981 A1 WO 2024103981A1
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WO
WIPO (PCT)
Prior art keywords
sub
hole injection
layer
substrate
display panel
Prior art date
Application number
PCT/CN2023/122070
Other languages
English (en)
French (fr)
Inventor
余洪涛
李育豪
卜维亮
苏冬冬
童慧
张云颢
余忠祥
杨宗顺
黄冠达
王辉
Original Assignee
京东方科技集团股份有限公司
云南创视界光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 云南创视界光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024103981A1 publication Critical patent/WO2024103981A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/17—Carrier injection layers

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel and an electronic device.
  • microdisplays for example: Micro OLED silicon-based microdisplays
  • Micro OLED silicon-based microdisplays are widely used as near-eye displays in the VR/AR field.
  • the industry mostly uses two-layer light-emitting devices or three-layer light-emitting devices to improve device efficiency as a product platform for product development and production.
  • micro displays for example, Micro OLED silicon-based micro displays
  • the present application provides a display panel and an electronic device to solve all or part of the deficiencies in the related art.
  • the display panel also includes a stepped structure; the stepped structure is located between the first sub-hole injection part and the substrate; the first sub-hole injection part is located on the side of the stepped structure away from the substrate, and the stepped structure includes at least one step; part of the second sub-hole injection part is located on the surface of the step away from the substrate, and the stepped structure is configured to ensure that the second sub-hole injection parts located on the side of the step away from the substrate are isolated from each other, and to ensure that the first sub-hole injection part is isolated from the second sub-hole injection part.
  • each layer of the step includes a recessed portion, which is a portion of the step that is recessed in a direction away from the inscribed area; the recessed portion is located between the step and the second sub-hole injection portion corresponding to the step, or the recessed portion is located between the step and the second sub-charge generation portion corresponding to the step.
  • an electronic device comprising any one of the above-mentioned display panels.
  • FIG1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG2 is a schematic structural diagram of a light-emitting unit of a display panel according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display panel according to an embodiment of the present application.
  • Fig. 1 is a schematic diagram showing the structure of the display panel 10. As shown in Fig. 1, the display panel 10 has an inscribed area 102 and a partition area 101. The inscribed area 102 is adjacent to the partition area 101.
  • the display panel 10 includes a substrate 11 , a light emitting layer 16 and a hole injection layer 13 .
  • the portion of the light emitting layer 16 located in the inscribed region 102 is configured to perform a light emitting function.
  • the light emitting layer 16 is located on the substrate 11.
  • the hole injection layer 13 is located between the light emitting layer 16 and the substrate 11.
  • the light emitting layer 16 is located on the side of the hole injection layer 13 away from the substrate 11.
  • the hole injection layer 13 includes a first sub-hole injection portion 131 and a second sub-hole injection portion 132 .
  • the first sub-hole injection portion 131 is located in the partitioning region 101.
  • the second sub-hole injection portion 132 is located in the inscribed region 102 and between the light-emitting layer 16 and the substrate 11.
  • the distance between the second sub-hole injection portion 132 and the substrate 11 is smaller than the distance between the first sub-hole injection portion 131 and the substrate 11, and the first sub-hole injection portion 131 is partitioned from the second sub-hole injection portion 132.
  • the first direction X shows a first direction X and a second direction Z.
  • the second direction Z is a direction away from the substrate 11.
  • the partition area 101 and the inscribed area 102 of the display panel 10 are adjacent.
  • the distance between the first sub-hole injection portion 131 and the substrate 11 is the distance between the first sub-hole injection portion 131 and the substrate 11 in the second direction Z.
  • the distance between the second sub-hole injection portion 132 and the substrate 11 is the distance between the first sub-hole injection portion 131 and the substrate 11 in the second direction Z.
  • the distance between the second sub-hole injection portion 132 and the substrate 11 is smaller than the distance between the first sub-hole injection portion 131 and the substrate 11, that is, in the second direction Z, the second sub-hole injection portion 132 is closer to the substrate 11 than the first sub-hole injection portion 131.
  • the second sub-hole injection portion 132 is closer to the substrate 11 than the first sub-hole injection portion 131 in the second direction Z, the portions of the hole injection layer 13 located in different regions are not located on the same plane, that is, the first sub-hole injection portion 131 located in the partition area 101 and the second sub-hole injection portion 132 located in the inscribed area 102 are not located on the same plane.
  • the step difference allows the first sub-hole injection portion 131 and the second sub-hole injection portion 132 to be isolated from each other without being electrically connected when the first sub-hole injection portion 131 and the second sub-hole injection portion 132 are formed.
  • the plane mentioned here refers to a plane perpendicular to the second direction Z, and the meanings of other planes in this article are the same as here.
  • the display panel 10 includes sub-pixels 20 located on the substrate 11.
  • each film layer of the display panel 10 is a film layer formed by an evaporation process, and the hole injection layer 13 formed by the evaporation process is easy to make the hole injection layers 13 located in different sub-pixels 20 electrically connected due to the integral molding.
  • the hole injection layer 13 has the characteristic of high carrier mobility. Therefore, the carriers transmitted in the hole injection layers 13 of different sub-pixels 20 are easy to flow laterally in the hole injection layers 13 that are electrically connected due to the integral molding, so the carriers may flow laterally in the hole injection layer 13 formed by the entire layer.
  • the carriers flow laterally in the hole injection layer 13, the carriers transmitted in the hole injection layers 13 of each sub-pixel 20 are easy to transmit to each other, resulting in the carriers transmitted in the hole injection layers 13 of each sub-pixel 20 Crosstalk with each other, so that it is easy to The problem of lateral leakage occurs between the sub-pixels 20 , which in turn easily causes the problem of substandard electrical crosstalk and low color gamut of the product.
  • the parts of the hole injection layer 13 located in different regions are not located on the same plane, that is, the first sub-hole injection part 131 located in the partition area 101 and the second sub-hole injection part 132 located in the inscribed area 102 are not located on the same plane, so that the first sub-hole injection part 131 and the second sub-hole injection part 132 form a "concave" shaped structure. Since the parts of the hole injection layer 13 located in different regions are not located on the same plane, there is a step difference between the first sub-hole injection part 131 and the second sub-hole injection part 132.
  • the existing step difference allows the first sub-hole injection portion 131 and the second sub-hole injection portion 132 to be isolated from each other without being electrically connected when the first sub-hole injection portion 131 and the second sub-hole injection portion 132 are formed.
  • a "concave"-shaped structure formed by the first sub-hole injection portion 131 and the second sub-hole injection portion 132 can block the current flowing in the hole injection layer 13 that is electrically connected between the sub-pixels 20.
  • the hole injection layers 13 of the sub-pixels 20 can be prevented from generating current crosstalk with each other, thereby avoiding the problem of lateral leakage between the sub-pixels 20.
  • the problem of substandard electrical crosstalk and low color gamut caused by the lateral leakage between the sub-pixels 20 can also be avoided.
  • the portion of the light-emitting layer 16 located in the partition area 101 does not emit light due to the blocking of the first sub-hole injection portion 131 and the second sub-hole injection portion 132. Therefore, the portion of the light-emitting layer 16 located in the partition area 101 does not perform the light-emitting function but is only formed by whole-layer evaporation during formation, which facilitates the preparation of the film layers of the display panel 10.
  • the display panel 10 further includes an anode 17.
  • the anode 17 is at least partially located in the inscribed area 102, the anode 17 is also located between the hole injection layer 13 and the substrate 11, and the anode 17 is also located between the second hole injection portion 132 and the substrate 11.
  • the anode 17 is electrically connected to the second sub-hole injection portion 132.
  • the anode 17 is at least partially located in the inscribed area 102, that is, the anode 17 may be partially located in the inscribed area 102, or may be entirely located in the inscribed area 102.
  • the carriers flow laterally in the hole injection layer 13 formed as a whole layer, the The carriers transmitted in the hole injection layer 13 are easily transmitted to each other, resulting in the carriers transmitted in the hole injection layer 13 of each sub-pixel 20 crosstalking with each other, thereby easily causing lateral leakage problems between the sub-pixels 20, making it impossible for the anode 17 to accurately control the light-emitting layer 16 corresponding to it, and further, the lateral leakage problem between the sub-pixels 20 is likely to cause the product electrical crosstalk not meeting the standards and the low color gamut problem.
  • the first sub-hole injection part 131 and the second sub-hole injection part 132 form a "concave" shaped structure.
  • the first sub-hole injection part 131 can be well disconnected from the second sub-hole injection part 132 to block the transmission of carriers in the hole injection layer 13.
  • the other light-emitting layers 16 here refer to other light-emitting layers 16 other than the light-emitting layer 16 corresponding to the anode 17, thereby avoiding the leakage generated by the hole injection layer 13 of each sub-pixel 20.
  • the problem of lateral leakage between the sub-pixels 20 can be avoided, so that the anode 17 can accurately control the light-emitting layer 16 corresponding to it, and then, the problem of substandard product electrical crosstalk and low color gamut caused by the lateral leakage problem between the sub-pixels 20 can be avoided.
  • the area of the anode 17 in the inscribed area 102 is larger than the area of the anode in the partition area 101.
  • the area of the anode 17 in the inscribed area 102 is 3 to 5 times the area of the anode 17 in the partition area 101. In this way, the anode 17 can accurately control the corresponding light-emitting layer 16, thereby avoiding the problem of substandard product electrical crosstalk and low color gamut caused by lateral leakage between sub-pixels 20.
  • the display panel 10 further includes a step structure 18 .
  • the step structure 18 is located between the first sub-hole injection portion 131 and the substrate 11 .
  • the first sub-hole injection portion 131 is located on a side of the step structure 18 away from the substrate 11, and the step structure 18 includes at least one step 181.
  • Part of the second sub-hole injection portion 132 is located on a surface of the step 181 away from the substrate 11, and the step structure is configured to ensure that the second sub-hole injection portions 132 located on the side of the step 181 away from the substrate 11 are isolated from each other, and to ensure that the first sub-hole injection portion 131 is isolated from the second sub-hole injection portion 132.
  • the step 181 may include a first step 182.
  • the first step 182 further includes a first upper insulating layer 1821, a first middle insulating layer 1822 and a first lower insulating layer 1823.
  • the materials of the layer 1821 and the first lower insulating layer 1823 may include silicon oxide, and the first middle insulating layer 1822 may include silicon nitride.
  • the portion of the first lower insulating layer 1823 that is longer in the first direction X than the first upper insulating layer 1821 in the first direction X is the outer edge portion.
  • the length of the outer edge portion in the first direction X is greater than or equal to 0.15 microns and less than or equal to 0.35 microns.
  • the length of the outer edge portion in the first direction X may be 0.15 microns, or the length of the outer edge portion in the first direction X may be 0.2 microns, or the length of the outer edge portion in the first direction X may be 0.25 microns, or the length of the outer edge portion in the first direction X may be 0.3 microns, or the length of the outer edge portion in the first direction X may be 0.35 microns, but is not limited thereto.
  • the length of the outer edge portion in the first direction X is greater than or equal to 0.15 microns to ensure that the step 181 can effectively shield the electrical instability caused by the edge deformation during the deposition process, and the length of the outer edge portion in the first direction X is less than or equal to 0.35 microns to ensure that the total projection area of the outer edge portion is less than 15% of the partition area.
  • the thicknesses of the first upper insulating layer 1821, the first middle insulating layer 1822 and the first lower insulating layer 1823 are basically the same, Figure 1 is only for the convenience of intuitively displaying the film structure. In fact, the thickness of the first middle insulating layer 1822 is much thicker than that of the first upper insulating layer 1821 or the first lower insulating layer 1823.
  • the film structure of the step 181 shown in other embodiments can also refer to the description here.
  • the step structure 18 may further include a buffer layer 180, which is located between the step structure 18 and the anode 17. Since the material of the step structure 18 on the side of the buffer layer 180 away from the substrate 11 includes silicon oxide, and a gas with strong oxidizing properties is required when depositing silicon oxide, the buffer layer 180 is configured to avoid using a gas with strong oxidizing properties to produce a reduction reaction with the material of the anode 17 when depositing the step structure 18, thereby affecting the performance of the anode 17. After forming a film layer including silicon oxide, the buffer layer 180 may be etched to prevent the buffer layer 180 from affecting the electrical connection between the second hole injection portion 132 and the anode 17.
  • part of the second sub-hole injection portion 132 is located on the side of the step 181 away from the substrate 11, and the stepped structure 18 ensures that the second sub-hole injection portions 132 located on the side of the step 181 away from the substrate 11 are isolated from each other, and ensures that the first sub-hole injection portion 131 is isolated from the second sub-hole injection portion 132.
  • the step 181 includes an inner recess 1814, which is a portion of the step 181 that is recessed along the direction of the inscribed area 102 toward the partition area 101.
  • the inner recess 1814 is located between the step 181 and the second sub-hole injection portion 132.
  • the inner recess 1814 is provided corresponding to the second hole injection portion 132.
  • the step 181 may include a first step 182.
  • the first step 182 may include a first inner recess 1824.
  • the first inner recess 1824 is a portion of the first step 182 that is recessed along the direction of the inscribed area 102 toward the partition area 101, that is, the first inner recess 1824 is a portion of the first step 182 that is recessed along the first direction X.
  • the first middle insulating layer 1822 is recessed along the first direction X, so that the first middle insulating layer 1822 is more recessed than the first upper insulating layer 1821 and the first lower insulating layer 1823 in the first direction X, so as to form a recessed structure, that is, the first inner recess 1824.
  • the first inner concave portion 1824 is empty, that is, no other material is filled in the first inner concave portion 1824, and the empty space is maintained.
  • a film layer located on the side of the step structure 18 away from the substrate 11 is subsequently formed, for example, the hole injection layer 13, it is difficult for ions to enter the concave portion of the first step 182 along the second direction Z during evaporation. Therefore, no film layer will be formed in the first inner concave portion 1824.
  • the film material tends to be filled into the first recessed portion 1824 to generate a shear force at the first recessed portion 1824, thereby ensuring that the stepped structure 18 isolates the second sub-hole injection portion 132 located on the side of the step 181 away from the substrate 11, and ensuring that the first sub-hole injection portion 131 is isolated from the second sub-hole injection portion 132, thereby preventing leakage current generated by the hole injection layer 13 of each sub-pixel 20 from crosstalking with each other, avoiding the problem of lateral leakage current between the sub-pixels 20, and at the same time, avoiding the problem of substandard electrical crosstalk and low color gamut of the product caused by the lateral leakage current between the sub-pixels 20.
  • the display panel 10 further includes: at least two light emitting layers 16 and at least one charge generation layer 15 .
  • the light emitting layer 16 and the charge generation layer 15 are both located on a side of the hole injection layer 13 away from the substrate 11 .
  • Each charge generation layer 15 includes a first sub-charge generation unit 1501 and a second sub-charge generation unit 1502.
  • the first sub-charge generating portion 1501 is located in the partitioning region 101, and the second sub-charge generating portion 1502 is located in the inscribed region 102.
  • the light-emitting layer 16 and the second sub-charge generating portion 1502 are arranged alternately.
  • the first film layer and the last film layer in the direction away from the substrate 11 are both the light-emitting layer 16.
  • the distance between the second sub-charge generating portion 1502 and the substrate 11 is smaller than the distance between the first sub-charge generating portion 1501 and the substrate 11, and the first sub-charge generating portion 1501 is isolated from the second sub-charge generating portion 1502.
  • the display panel 10 may include three light-emitting layers 16 and two charge generation layers 15.
  • the display panel 10 may include a first charge generation layer 151, a second charge generation layer 152, a first light-emitting layer 161, a second light-emitting layer 162, and a third light-emitting layer 163.
  • the first charge generation layer 151 further includes a third sub-charge generating portion 1511 and a fourth sub-charge generating portion 1512
  • the second charge generation layer 152 further includes a fifth sub-charge generating portion 1521 and a sixth sub-charge generating portion 1522.
  • the third sub-charge generating portion 1511 and the fifth sub-charge generating portion 1521 are located in the partition area 101
  • the fourth sub-charge generating portion 1512 and the sixth sub-charge generating portion 1522 are located in the inscribed area 102.
  • the distance from the third sub-charge generating unit 1511 to the fifth sub-charge generating unit 1521 is smaller than the distance from the fourth sub-charge generating unit 1512 to the sixth sub-charge generating unit 1522.
  • Such a design is conducive to ensuring effective transfer between the multi-layer light-emitting layer 151 and the second charge generating layer 152, while slowing down the transfer in the inscribed area 102.
  • a stacked display can be realized, that is, when the first charge generation layer 151 and the second charge generation layer 152 are passed through in the second direction Z, the stacked first light-emitting layer 161, the second light-emitting layer 162 and the third light-emitting layer 163 are connected in series up and down to emit light in a stacked manner to improve the display efficiency and peak brightness.
  • the stacked first light-emitting layer 161, the second light-emitting layer 162 and the third light-emitting layer 163 can be configured to emit red light, green light and blue light, respectively.
  • the carriers transmitted in the hole injection layer 13 of different sub-pixels 20 are easy to flow laterally in the hole injection layer 13 or the charge generation layer 15 that are electrically connected due to integral molding, so the carriers may flow laterally in the hole injection layer 13 or the charge generation layer 15 formed by the entire layer. Since the carriers flow laterally in the hole injection layer 13 or the charge generation layer 15, the carriers transmitted in the hole injection layer 13 or the charge generation layer 15 of each sub-pixel 20 are easily transmitted to each other, causing the carriers transmitted in the hole injection layer 13 or the charge generation layer 15 of each sub-pixel 20 to crosstalk with each other, thereby easily causing the problem of lateral leakage between the sub-pixels 20. Furthermore, the problem of lateral leakage between the sub-pixels 20 is likely to cause the product electrical crosstalk to fail to meet the standards and the problem of low color gamut.
  • the portions of the hole injection layer 13 located in different regions are not located on the same plane, that is, the first sub-hole injection portion 131 located in the partition area 101 and the second sub-hole injection portion 132 located in the inscribed area 102 are not located on the same plane, so that the first sub-hole injection portion 131 and the second sub-hole injection portion 132 form a "concave"-shaped structure.
  • the third sub-charge generating portion 1511 and the fourth sub-charge generating portion 1512 and the fifth sub-charge generating portion 1521 and the sixth sub-charge generating portion 1522 also form a "concave"-shaped structure.
  • the "concave"-shaped structure enables the first sub-hole injection part 131 and the second sub-hole injection part 132, the third sub-charge generating part 1511 and the fourth sub-charge generating part 1512, and the fifth sub-charge generating part 1521 and the sixth sub-charge generating part 1522 to be isolated without being electrically connected, thereby blocking the current flowing in the hole injection layer 13 or the charge generation layer 15 that is electrically connected between the sub-pixels 20, and further avoiding the current crosstalk generated by the hole injection layers 13 of each sub-pixel 20, so as to further avoid the problem of lateral leakage between the sub-pixels 20. At the same time, it can also further avoid the problem of substandard product electrical crosstalk and low color gamut caused by the lateral leakage between the sub-pixels 20.
  • the display panel 10 further includes: a cathode 12, an electron injection layer 14, an encapsulation layer 21, a drive array 22, and a planar layer 23.
  • the electron injection layer 14 is located on a side of the third light emitting layer 163 away from the substrate 11.
  • the cathode 12 is located on a side of the electron injection layer 14 away from the substrate 11.
  • the encapsulation layer 21 is located on the side of the cathode 12 away from the substrate 11.
  • the encapsulation layer 21 is configured to perform an encapsulation function on the film structure of the display panel 10 to prevent substances such as oxygen and water vapor from entering the film structure of the display panel 10 and causing damage to the display panel 10. At the same time, the encapsulation layer 21 also protects the film structure of the display panel 10.
  • the drive array 22 is located between the anode 17 and the substrate 11.
  • the anode 17 is electrically connected to the drive array 22, and the drive array 22 is configured to transmit a drive signal.
  • the drive array 22 executes the drive signal indicating light emission, it controls the anode 17 to transmit carriers into the hole injection layer 13.
  • the drive array 22 is also configured to reflect light incident on the drive array 22.
  • the flat layer 23 is located between the stepped structure 18 and the substrate 11, and in the first direction X, the flat layer 23 is adjacent to the anode 17.
  • the thickness of the anode 17 is relatively thick, a large step difference is easily generated in the second direction Z, that is, the distance between the surface of the anode 17 away from the substrate 11 and the substrate 11 in the second direction Z is relatively large.
  • the large step difference can easily lead to problems such as fracture of the film layer in the display panel 10, thereby affecting the normal display of the display panel 10.
  • the flat layer 23 is configured to fill the portion between the step structure 18 and the substrate 11, so that the surface of the flat layer 23 away from the substrate 11 is flush with the surface of the anode 17 away from the substrate 11, thereby avoiding a large step difference from damaging the film layer located on the side of the flat layer 23 away from the substrate 11, such as the step structure 18.
  • the flat layer 23 is configured to fill the portion between the step structure 18 and the substrate 11, so that the surface of the flat layer 23 away from the substrate 11 is flush with the surface of the anode 17 away from the substrate 11, in other embodiments, it is not limited thereto, and the surface of the flat layer 23 away from the substrate 11 may not be flush with the surface of the anode 17 away from the substrate 11, but it can be ensured that the step difference between the surface of the flat layer 23 away from the substrate 11 and the surface of the anode 17 away from the substrate 11 can avoid damage to the film layer located on the side of the flat layer 23 away from the substrate 11.
  • FIG2 shows a schematic diagram of the structure of a light-emitting unit of a display panel 10, and the light-emitting unit includes: an electron injection layer 14, a first light-emitting layer 161, a second light-emitting layer 162, a third light-emitting layer 163, a first charge generation layer 151, a second charge generation layer 152, and a hole injection layer 13.
  • the first light-emitting layer 161 includes: a first hole transport layer 1611, a first composite light-emitting layer 1612, and a first electron transport layer 1613.
  • the second light-emitting layer 162 includes: a second hole transport layer 1621, a second composite light-emitting layer 1622, and a second electron transport layer 1623.
  • the third light-emitting layer 163 includes: a third hole transport layer 1631, a third composite light-emitting layer 1632, and a third electron transport layer 1633.
  • a first charge generation layer is provided between the first electron transport layer 1613 and the second hole transport layer 1621.
  • Layer 151, the first electron transport layer 1613 and the second hole transport layer 1621 are electrically connected through the first charge generation layer 151, so that the first light-emitting layer 161 is electrically connected to the second light-emitting layer 162.
  • a second charge generation layer 152 is provided between the second electron transport layer 1623 and the third hole transport layer 1631, and the second electron transport layer 1623 and the third hole transport layer 1631 are electrically connected through the second charge generation layer 152, so that the second light-emitting layer 162 and the third light-emitting layer 163 are electrically connected.
  • the cathode 12 transports electrons to the electron injection layer 14, and the anode 17 transports holes to the hole injection layer 13.
  • the input carriers cause the first charge generation layer 151 and the second charge generation layer 152 to generate electrons and holes.
  • the electrons generated by the first charge generation layer 151 are transmitted to the first composite light-emitting layer 1612 through the first electron transport layer 1613, and the holes generated by the first charge generation layer 151 are transmitted to the second composite light-emitting layer 1622 through the second hole transport layer 1621.
  • the flow direction of the electrons and holes generated by the first charge generation layer 151 is described here, the flow direction of the electrons and holes generated by the second charge generation layer 152 can refer to the first charge generation layer 151.
  • the first hole transport layer 1611 transmits holes to the first composite light-emitting layer 1612
  • the first electron transport layer 1613 transmits electrons to the first composite light-emitting layer 1612. Holes and electrons are recombined in the first composite light-emitting layer 1612 to form excitons and release energy, which causes the first composite light-emitting layer 1612 to emit light.
  • the light-emitting principle of the first composite light-emitting layer 1612 is described here, the light-emitting principle of the second composite light-emitting layer 1622 and the third composite light-emitting layer 1632 can refer to the first composite light-emitting layer 1612.
  • the inscribed area 102 mainly shows a partition structure, and for the sake of clarity, the portion of the light-emitting layer 16 located in the inscribed area 102 is not shown. However, since the entire layer is formed, the film structure of the light-emitting layer 16 located in the inscribed area 102 is the same as the film structure of the light-emitting layer 16 located in the partition area 101, and they can be referenced to each other.
  • the display panel 10 further includes a step structure 18 .
  • the step structure 18 is located between the first sub-hole injection portion 131 and the substrate 11 .
  • the first sub-hole injection portion 131 is located on a side of the step structure 18 away from the substrate 11, and the step structure 18 includes at least one step 181.
  • Part of the second sub-hole injection portion 132 is located on a surface of the step 181 away from the substrate 11, and the step structure 18 is configured to ensure that the second sub-hole injection portions 132 located on the side of the step 181 away from the substrate 11 are isolated from each other, and to ensure that the first sub-hole injection portion 131 is isolated from the second sub-hole injection portion 132.
  • the second sub-charge generating portion 1502 is located on the side of the second sub-hole injection portion 132 away from the substrate 11, and part of the second sub-charge generating portion 1502 is also located on the side of the step 181 away from the substrate 11.
  • the step structure 18 is configured to ensure that the second sub-charge generating portions 1502 located on the side of the step 181 away from the substrate 11 are isolated from each other, and to ensure that the first sub-hole injection portion 131 is isolated from the second sub-hole injection portion 132.
  • the display panel 10 may include two charge generation layers 15, that is, the display panel 10 may include a first charge generation layer 151 and a second charge generation layer 152.
  • the first charge generation layer 151 further includes a third sub-charge generation portion 1511 and a fourth sub-charge generation portion 1512
  • the second charge generation layer 152 further includes a fifth sub-charge generation portion 1521 and a sixth sub-charge generation portion 1522.
  • the third sub-charge generation portion 1511 and the fifth sub-charge generation portion 1521 are located in the partition area 101
  • the fourth sub-charge generation portion 1512 and the sixth sub-charge generation portion 1522 are located in the inscribed area 102.
  • the fourth sub-charge generating unit 1512 is located on the side of the second sub-hole injection unit 132 away from the substrate 11, and part of the sixth sub-charge generating unit 1522 is also located on the side of the step 181 away from the substrate 11.
  • the fourth sub-charge generating units 1512 located on the side of the step 181 away from the substrate 11 are isolated from each other and from the third sub-charge generating unit 1511.
  • the sixth sub-charge generating unit 1522 is located on the side of the fourth sub-charge generating unit 1512 away from the substrate 11, and part of the sixth sub-charge generating unit 1522 is also located on the side of the step 181 away from the substrate 11.
  • the sixth sub-charge generating unit 1522 located on the side of the step 181 away from the substrate 11 are isolated from each other and from the fifth sub-charge generating unit 1521.
  • the second sub-hole injection portion 132 is closer to the substrate 11 than the first sub-hole injection portion 131 in the second direction Z, a large step difference is likely to exist between the second sub-hole injection portion 132 and the first sub-hole injection portion 131.
  • the large step difference is likely to cause the portion of the second sub-hole injection portion 132 extending along the second direction Z to break, affecting the electrical connection relationship between the second sub-hole injection portion 132 and the first sub-hole injection portion 131.
  • the same is true for the fourth sub-charge generating portion 1512 and the sixth sub-charge generating portion 1522.
  • part of the second sub-hole injection part 132, part of the fourth sub-charge generating part 1512 and part of the sixth sub-charge generating part 1522 are located on the side of the step 181 away from the substrate 11, and part of the second sub-hole injection part 132 located on the side of the step 181 away from the substrate 11 is separated from the first sub-hole injection part 131, part of the fourth sub-charge generating part 1512 located on the side of the step 181 away from the substrate 11 is separated from the third sub-charge generating part 1511, and part of the sixth sub-charge generating part 1522 located on the side of the step 181 away from the substrate 11 is separated from the fifth sub-charge generating part 1521.
  • the step structure 18 can be used to interrupt the hole injection layer 13 so that the holes are not electrically connected to each other.
  • the second sub-hole injection portion 132 and the first sub-hole injection portion 131 when forming the first charge generation layer 151, divide the first charge generation layer 151 into the fourth sub-charge generation portion 1512 and the third sub-charge generation portion 1511, and when forming the second charge generation layer 152, divide the second charge generation layer 152 into the sixth sub-charge generation portion 1522 and the fifth sub-charge generation portion 1521.
  • the leakage current generated by the hole injection layer 13 of each sub-pixel 20 can be further avoided from crosstalking with each other, so as to avoid the problem of lateral leakage current between the sub-pixels 20.
  • the problem of substandard electrical crosstalk and low color gamut of the product caused by the lateral leakage current between the sub-pixels 20 can be avoided.
  • the total number of the hole injection layer 13 and the charge generation layer 15 is the same as the number of the steps 181.
  • One layer of the hole injection layer 13 or one layer of the charge generation layer 15 is provided corresponding to one layer of the step 181.
  • the display panel 10 includes one layer of the hole injection layer 13 and two layers of the charge generation layer 15, and the step structure 18 also includes three layers of the steps 181.
  • the step structure 18 may include a first step 182, a second step 183, and a third step 184 which are stacked.
  • the first step 182 may include a first upper insulating layer 1821, a first middle insulating layer 1822, and a first lower insulating layer 1823
  • the second step 183 may include a second upper insulating layer 1831, a second middle insulating layer 1832, and a second lower insulating layer 1833
  • the third step 184 may include a third upper insulating layer 1841, a third middle insulating layer 1842, and a third lower insulating layer 1843.
  • the second lower insulating layer 1833 has the same length as the first upper insulating layer 1821 in the first direction X
  • the third lower insulating layer 1843 has the same length as the second upper insulating layer 1831 in the first direction X. If the step structure 18 has more steps 181, the same can be applied.
  • the height of the first step 182, the second step 183, and the third step 184 in the second direction Z is defined as the thickness.
  • the thickness of the first step 182 is greater than or equal to 30 nanometers and less than or equal to 55 nanometers.
  • the thickness of the first step 182 may be 30 nanometers, or the thickness of the first step 182 may be 40 nanometers, or the thickness of the first step 182 may be 50 nanometers, or the thickness of the first step 182 may be 55 nanometers, but is not limited thereto.
  • the total thickness of the first step 182 and the second step 183 is greater than or equal to 100 nanometers and less than or equal to 150 nanometers.
  • the total thickness of the first step 182 and the second step 183 may be 100 nanometers, or the total thickness of the first step 182 and the second step 183 may be 110 nanometers, or the total thickness of the first step 182 and the second step 183 may be 120 nanometers, or the total thickness of the first step 182 and the second step 183 may be 130 nanometers, or the total thickness of the first step 182 and the second step 183 may be 140 nanometers, or the total thickness of the first step 182 and the second step 183 may be 150 nanometers, but is not limited thereto.
  • the total thickness of the step 183 and the third step 184 is greater than or equal to 200 nanometers and less than or equal to 300 nanometers.
  • the total thickness of the first step 182, the second step 183, and the third step 184 may be 200 nanometers, or the total thickness of the first step 182, the second step 183, and the third step 184 may be 225 nanometers, or the total thickness of the first step 182, the second step 183, and the third step 184 may be 250 nanometers, or the total thickness of the first step 182, the second step 183, and the third step 184 may be 275 nanometers, or the total thickness of the first step 182, the second step 183, and the third step 184 may be 300 nanometers, but is not limited thereto.
  • the angle of the first angle a between the line connecting the edges of the first step 182, the second step 183 and the third step 184 and the substrate 11 is greater than or equal to 15 degrees and less than or equal to 45 degrees.
  • the first angle a may be 15 degrees, or the first angle a may be 25 degrees, or the first angle a may be 35 degrees, or the first angle a may be 45 degrees, but is not limited thereto.
  • step 181 By setting the same number of steps 181 as the total number of hole injection layers 13 and charge generation layers 15, and setting one step 181 for each hole injection layer 13 or one charge generation layer 15, it can be ensured that the hole injection layer 13 and each charge generation layer 15 can be connected to one step 181. Therefore, it can be ensured that the hole injection layer 13 and each charge generation layer 15 can be separated by the steps 181, and it can also be avoided to set too many layers of steps 181. Furthermore, it can reduce costs while ensuring that the step structure 18 can effectively separate the hole injection layer 13 and the charge generation layer 15.
  • each step 181 includes an inner recess 1814, which is a portion of the step 181 that is recessed in a direction away from the inscribed region 102.
  • the inner recess 1814 is located between the step 181 and the second sub-hole injection portion 132 corresponding to the step 181, or the inner recess 1814 is located between the step 181 and the second sub-charge generation portion 1502 corresponding to the step 181.
  • the first step 182 may include a first recessed portion 1824
  • the second step 183 may include a second recessed portion 1834
  • the third step may include a third recessed portion 1844.
  • the first recessed portion 1824 is a portion of the step 181 that is recessed along the direction of the inscribed area 102 toward the partition area 101, that is, the first recessed portion 1824 is a portion of the first step 182 that is recessed along the first direction X.
  • the first middle insulating layer 1822 is recessed along the first direction X, so that the first middle insulating layer 1822 is more recessed in the first direction X than the first upper insulating layer 1821 and the first lower insulating layer 1823 to form a recessed structure, that is, the first recessed portion 1824.
  • the stepped structure 18 is provided with more layers of steps 181, then The same can be said for the second inner recess 1834 and the third inner recess 1844 , which can also refer to the description of the first inner recess 1824 .
  • the first inner recess 1824, the second inner recess 1834 and the third inner recess 1844 are all empty, that is, no other material is filled in the first inner recess 1824, the second inner recess 1834 and the third inner recess 1844, and the empty space is maintained.
  • a film layer located on the side of the step structure 18 away from the substrate 11 is subsequently formed, for example, the hole injection layer 13, it is difficult for ions to enter the recessed portion of the first step 182 along the second direction Z during evaporation. Therefore, no film layer will be formed in the first inner recess 1824, the second inner recess 1834 or the third inner recess 1844.
  • the hole injection layer 13 can be isolated from other highly conductive film layers through the recessed portion 1814.
  • the first charge generation layer 151 or the second charge generation layer 152 can be isolated from other highly conductive film layers through the recessed portion 1814.
  • FIG3 shows a schematic diagram of the structure of another display panel 10.
  • the step structure 18 includes an inscribed portion 201, the inscribed portion 201 is located in the inscribed area 102, and the inscribed portion 201 is a portion of the step structure 18 that is recessed toward the substrate 11.
  • the step 181 in the inscribed portion 201 is configured to separate at least one layer of the second hole injection portion 132 and the second sub-charge generation portion 1502.
  • the step 181 within the inscribed portion 201 may isolate only the second hole injection portion 132, or the step 181 within the inscribed portion 201 may isolate the second hole injection portion 132 and the fourth sub-charge generating portion 1512 at the same time, or the step 181 within the inscribed portion 201 may isolate the second hole injection portion 132, the fourth sub-charge generating portion 1512 and the sixth sub-charge generating portion 1522 at the same time.
  • the leakage current flowing in the hole injection layer 13 or the charge generating layer 15 formed in the entire layer between the sub-pixels 20 can be further blocked, and further, the leakage current generated by the hole injection layer 13 of each sub-pixel 20 can be further prevented from crosstalking with each other, so as to avoid the problem of lateral leakage between the sub-pixels 20.
  • the problem of substandard electrical crosstalk and low color gamut of the product caused by the lateral leakage problem between the sub-pixels 20 can be further avoided.
  • the inscribed area 102 may include a first inscribed area 1021, a second inscribed area 1022 and a third inscribed area 1023. Among them, the first inscribed area 1021 and the second inscribed area 1022 are both adjacent to the third inscribed area 1023. At the same time, the inscribed portion 201 of the stepped structure 18 may be located in the third inscribed area 1023.
  • the steps 181 in the first inscribed area 1021, the second inscribed area 1022 and the third inscribed area 1023 may be configured to isolate at least one layer of the second hole injection section 132, the fourth sub-charge generating section 1512 and the sixth sub-charge generating section 1522, respectively.
  • the display panel 10 may include two charge generation layers 15 and one hole injection layer 13, that is, the display panel 10 may include a first charge generation layer 151 and a second charge generation layer 152.
  • the first charge generation layer 151 further includes a third sub-charge generation portion 1511 and a fourth sub-charge generation portion 1512
  • the second charge generation layer 152 further includes a fifth sub-charge generation portion 1521 and a sixth sub-charge generation portion 1522
  • the hole injection layer 13 further includes a first sub-hole injection portion 131 and a second sub-hole injection portion 132.
  • the step 181 located in the first inscribed area 1021 is configured to separate the second sub-hole injection portion 132 from the fourth sub-charge generating portion 1512.
  • the step 181 located in the second inscribed area 1022 is configured to separate the second sub-hole injection portion 132, the fourth sub-charge generating portion 1512 and the sixth sub-charge generating portion 1522.
  • the step 181 located in the third inscribed area 1023 is configured to separate the second sub-hole injection portion 132.
  • step 181 in the adjacent first inscribed area 1021, the second inscribed area 1022 and the third inscribed area 1023, and the step 181 respectively isolates at least one layer of the second hole injection part 132, the fourth sub-charge generating part 1512 and the sixth sub-charge generating part 1522, the degree of crosstalk between different sub-pixels 20 can be adjusted according to actual needs, and then each sub-pixel 20 can choose to set a barrier effect with the surrounding sub-pixels 20 according to actual needs.
  • the width of the first inscribed area 1021 is smaller than the width of the second inscribed area 1022 and/or the third inscribed area 1023.
  • the sub-pixel 20 can be set to have a blocking effect with surrounding sub-pixels 20 according to actual needs.
  • the distance between adjacent first steps 182 is smaller than the distance between adjacent second steps 183 , and smaller than the distance between adjacent third steps 184 ; the step structure formed in this way is conducive to reducing crosstalk between different sub-pixels 20 .
  • the distance between adjacent sub-pixels 20 and adjacent buffer layers 180 is smaller than the distance between adjacent second lower insulating layers 1833, and smaller than the distance between adjacent third lower insulating layers 1843; further, smaller than the distance between adjacent third upper insulating layers 1841.
  • Such a design is conducive to reducing the degree of crosstalk between different sub-pixels 20.
  • the present application also provides an electronic device, including any of the above-mentioned display panels 10.
  • the electronic device may be a VR/AR device or other near-eye display device, but is not limited thereto.

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Abstract

本申请涉及一种显示面板及电子设备。其中，显示面板具有内切区与隔断区，内切区与隔断区相邻。显示面板包括：衬底、发光层与空穴注入层。发光层位于内切区的部分被配置执行发光功能，发光层位于衬底上。空穴注入层位于发光层与衬底之间，发光层位于空穴注入层远离衬底的一侧。空穴注入层包括第一子空穴注入部与第二子空穴注入部。第一子空穴注入部位于隔断区。第二子空穴注入部位于内切区，且位于发光层与衬底之间。第二子空穴注入部与衬底之间的距离小于第一子空穴注入部与衬底之间的距离，且第一子空穴注入部与第二子空穴注入部相隔断。

Description

显示面板及电子设备 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及电子设备。
背景技术
在相关技术中，微型显示器(例如：Micro OLED硅基微型显示器)作为近眼显示器广泛应用在VR/AR领域中，随着市场对产品高亮度以及低功耗的显示面板的需求日益提升，行业内多采用二叠层发光器件或者三叠层发光器件来提升器件效率来作为产品平台进行产品开发和生产。
但微型显示器(例如：Micro OLED硅基微型显示器)的显示面板存在产品电学串扰不达标的问题。
发明内容
本申请提供一种显示面板及电子设备，以解决相关技术中全部或部分不足。
根据本申请实施例的第一方面，提供一种显示面板，所述显示面板具有内切区与隔断区，所述内切区与所述隔断区相邻；所述显示面板包括：衬底、发光层与空穴注入层；所述发光层位于所述内切区的部分被配置执行发光功能，所述发光层位于所述衬底上；所述空穴注入层位于所述发光层与所述衬底之间，所述发光层位于所述空穴注入层远离所述衬底的一侧；所述空穴注入层包括第一子空穴注入部与第二子空穴注入部；所述第一子空穴注入部位于所述隔断区；所述第二子空穴注入部位于所述内切区，且位于所述发光层与所述衬底之间；所述第二子空穴注入部与所述衬底之间的距离小于所述第一子空穴注入部与所述衬底之间的距离，且所述第一子空穴注入部与所述第二子空穴注入部相隔断。
在一些实施例中，所述显示面板还包括阳极；所述阳极至少部分位于所述内切区，所述阳极还位于所述空穴注入层与所述衬底之间，且所述阳极还位于所述第二空穴注入部与所述衬底之间；所述阳极与所述第二子 空穴注入部电连接。
在一些实施例中，所述显示面板还包括阶梯结构；所述阶梯结构位于所述第一子空穴注入部与所述衬底之间；所述第一子空穴注入部位于所述阶梯结构远离所述衬底的一侧，所述阶梯结构包括至少一层阶梯；部分所述第二子空穴注入部位于所述阶梯远离所述衬底的一侧的表面，所述阶梯结构被配置为确保位于所述阶梯远离所述衬底一侧的所述第二子空穴注入部互相隔断，且确保所述第一子空穴注入部与所述第二子空穴注入部隔断。
在一些实施例中，所述阶梯包括内凹部，所述内凹部为所述阶梯沿所述内切区朝向所述隔断区的方向凹陷的部分；所述内凹部位于所述阶梯与所述第二子空穴注入部之间；所述内凹部对应于所述第二空穴注入部设置。
在一些实施例中，所述显示面板还包括：至少两层发光层与至少一层电荷生成层；所述发光层与所述电荷生成层均位于所述空穴注入层远离所述衬底的一侧；每一层所述电荷生成层均包括第一子电荷生成部与第二子电荷生成部；所述第一子电荷生成部位于所述隔断区，所述第二子电荷生成部位于所述内切区；在远离所述衬底的方向上，所述发光层与所述第二子电荷生成部交替排布；且在远离所述衬底的方向上的第一层膜层与最后一层膜层均为所述发光层；所述第二子电荷生成部与所述衬底之间的距离小于所述第一子电荷生成部与所述衬底之间的距离，且所述第一子电荷生成部与所述第二子电荷生成部相隔断。
在一些实施例中，所述显示面板还包括阶梯结构；所述阶梯结构位于所述第一子空穴注入部与所述衬底之间；所述第一子空穴注入部位于所述阶梯结构远离所述衬底的一侧，所述阶梯结构包括至少一层阶梯；部分所述第二子空穴注入部位于所述阶梯远离所述衬底的一侧的表面，所述阶梯结构被配置为确保位于所述阶梯远离所述衬底一侧的所述第二子空穴注入部互相隔断，且确保所述第一子空穴注入部与所述第二子空穴注入部隔断；所述第二子电荷生成部位于所述第二子空穴注入部远离所述衬底的一侧，部分所述第二子电荷生成部也位于所述阶梯远离所述衬底的一侧；所述阶梯结构被配置为确保位于所述阶梯远离所述衬底的一侧的所述第二子 电荷生成部互相隔断，且确保所述第一子空穴注入部与所述第二子空穴注入部隔断。
在一些实施例中，所述空穴注入层与所述电荷生成层的总层数与所述阶梯的层数相同；且一层所述空穴注入层或者一层所述电荷生成层对应一层所述阶梯设置。
在一些实施例中，每层所述阶梯均包括内凹部，所述内凹部为所述阶梯在沿远离内切区的方向凹陷的部分；所述内凹部位于所述阶梯与所述阶梯对应的所述第二子空穴注入部之间，或者，所述内凹部位于所述阶梯与所述阶梯对应的所述第二子电荷生成部之间。
在一些实施例中，所述阶梯结构包括内切部，所述内切部位于所述内切区，所述内切部为所述阶梯结构朝向所述衬底凹陷的部分；所述内切部内的所述阶梯被配置为隔断所述第二空穴注入部与所述第二子电荷生成部中的至少一层。
在一些实施例中，在相邻的所述内切区内，设有的所述阶梯隔断所述第二空穴注入部与所述第二子电荷生成部中的至少一层。
根据本申请实施例的第二方面，提供一种电子设备，包括上述任一种显示面板。
根据本申请实施例可知，由于第二子空穴注入部位于内切区，第一子空穴注入部位于隔断区，位于内切区的第二子空穴注入部与衬底之间的距离小于位于隔断区的第一子空穴注入部与衬底之间的距离，且第一子空穴注入部与第二子空穴注入部相隔断。因此，空穴注入层位于不同区域的部分并未位于同一平面上，即位于隔断区的第一子空穴注入部与位于内切区的第二子空穴注入部并未位于同一平面上，使得第一子空穴注入部与第二子空穴注入部形成了一个“凹”字形结构。而由于空穴注入层位于不同区域的部分并未位于同一平面上，使得第一子空穴注入部与第二子空穴注入部存在段差。而存在的段差则使得在形成第一子空穴注入部与第二子空穴注入部时，第一子空穴注入部与第二子空穴注入部能够隔断，而不电连接，从而，可以通过第一子空穴注入部与第二子空穴注入部形成的一个“凹”字形结构，阻隔子像素之间在存在电连接关系的空穴注入层内流动的电流， 进而，可以避免各子像素的空穴注入层产生电流互相串扰，以避免各子像素之间产生横向漏电的问题，同时，也可以避免各子像素之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本申请。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
图1是根据本申请实施例示出的一种显示面板的结构示意图；
图2是根据本申请实施例示出的一种显示面板的发光单元的结构示意图；
图3是根据本申请实施例示出的另一种显示面板的结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
本申请实施例提供一种显示面板10。图1示出的是该显示面板10的结构示意图。如图1所示，该显示面板10具有内切区102与隔断区101。内切区102与隔断区101相邻。
显示面板10包括：衬底11、发光层16与空穴注入层13。
发光层16位于内切区102的部分被配置执行发光功能，发光层16位于衬底11上。空穴注入层13位于发光层16与衬底11之间，发光层16位于空穴注入层13远离衬底11的一侧。
空穴注入层13包括第一子空穴注入部131与第二子空穴注入部132。 第一子空穴注入部131位于隔断区101。第二子空穴注入部132位于内切区102，且位于发光层16与衬底11之间。第二子空穴注入部132与衬底11之间的距离小于第一子空穴注入部131与衬底11之间的距离，且第一子空穴注入部131与第二子空穴注入部132相隔断。
具体的，图1中示出了第一方向X与第二方向Z。其中，第二方向Z为远离衬底11的方向。在第一方向X上，显示面板10所具有的隔断区101与内切区102相邻。
第一子空穴注入部131与衬底11之间的距离，即为在第二方向Z上，第一子空穴注入部131与衬底11之间的距离。同样，第二子空穴注入部132与衬底11之间的距离，即为在第二方向Z上，第一子空穴注入部131与衬底11之间的距离。而第二子空穴注入部132与衬底11之间的距离小于第一子空穴注入部131与衬底11之间的距离，也即在第二方向Z上，第二子空穴注入部132相较于第一子空穴注入部131更接近衬底11。而由于在第二方向Z上，第二子空穴注入部132相较于第一子空穴注入部131更接近衬底11，那么，空穴注入层13位于不同区域的部分也就并未位于同一平面上，即位于隔断区101的第一子空穴注入部131与位于内切区102的第二子空穴注入部132并未位于同一平面上。由此，也使得第一子空穴注入部131与第二子空穴注入部132存在段差。而存在的段差则使得在形成第一子空穴注入部131与第二子空穴注入部132时，第一子空穴注入部131与第二子空穴注入部132能够隔断，而不电连接。需要说明的是，此处所提到的平面是指与第二方向Z相垂直的平面，在本文中其他的平面所指的含义也与本处相同。
由于在本申请中，显示面板10包括位于衬底11上的子像素20。同时，显示面板10的各个膜层均为通过蒸镀工艺整层形成的膜层，而蒸镀工艺整层形成的空穴注入层13，就容易因一体成型而使位于不同子像素20的空穴注入层13之间存在电连接关系。而由于空穴注入层13具有高载流子迁移率的特点。因此，在不同子像素20的空穴注入层13内传输的载流子，就容易在因一体成型而存在电连接关系的空穴注入层13内横向流动，因此载流子便可能在整层形成的空穴注入层13内横向流动。而由于载流子在空穴注入层13内横向流动，各子像素20的空穴注入层13内传输的载流子就容易互相传输，导致各子像素20的空穴注入层13内传输的载流子互相串扰，从而，容易在 各子像素20之间产生横向漏电的问题，进而，各子像素20之间横向漏电的问题又容易造成产品电学串扰不达标以及色域低的问题。
而根据上述实施例可知，由于第二子空穴注入部132位于内切区102，第一子空穴注入部131位于隔断区101，位于内切区102的第二子空穴注入部132与衬底11之间的距离小于位于隔断区101的第一子空穴注入部131与衬底11之间的距离，且第一子空穴注入部131与第二子空穴注入部132相隔断。因此，空穴注入层13位于不同区域的部分并未位于同一平面上，即位于隔断区101的第一子空穴注入部131与位于内切区102的第二子空穴注入部132并未位于同一平面上，使得第一子空穴注入部131与第二子空穴注入部132形成了一个“凹”字形结构。而由于空穴注入层13位于不同区域的部分并未位于同一平面上，使得第一子空穴注入部131与第二子空穴注入部132存在段差。而存在的段差则使得在形成第一子空穴注入部131与第二子空穴注入部132时，第一子空穴注入部131与第二子空穴注入部132能够隔断，而不电连接，从而，可以通过第一子空穴注入部131与第二子空穴注入部132形成的一个“凹”字形结构，阻隔子像素20之间在存在电连接关系的空穴注入层13内流动的电流，进而，可以避免各子像素20的空穴注入层13产生电流互相串扰，以避免各子像素20之间产生横向漏电的问题，同时，也可以避免各子像素20之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
需要说明的是，虽然，显示面板10的各个膜层均为通过蒸镀工艺整层形成的膜层，但是，发光层16位于隔断区101的部分由于第一子空穴注入部131与第二子空穴注入部132相阻隔的原因而不会发光。因此，发光层16位于隔断区101的部分并不执行发光功能而仅是在形成时整层蒸镀形成，便于显示面板10的膜层制备。
在一些实施例中，如图1所示，显示面板10还包括阳极17。阳极17至少部分位于内切区102，阳极17还位于空穴注入层13与衬底11之间，且阳极17还位于第二空穴注入部132与衬底11之间。阳极17与第二子空穴注入部132电连接。而阳极17至少部分位于内切区102，即阳极17可以部分位于内切区102，也可以全部位于内切区102。
由于载流子在整层形成的空穴注入层13内横向流动，各子像素20的 空穴注入层13内传输的载流子就容易互相传输，导致各子像素20的空穴注入层13内传输的载流子互相串扰，从而，容易在各子像素20之间产生横向漏电的问题，使得阳极17无法准确控制与其对应的发光层16，进而，使得各子像素20之间横向漏电的问题又容易造成产品电学串扰不达标以及色域低的问题。
通过第二空穴注入部132与阳极17电连接，可以确保第一子空穴注入部131与第二子空穴注入部132形成“凹”字形结构。同时，由于在显示面板10内的各子像素20之间形成的“凹”字形结构可以很好地使第一子空穴注入部131与第二子空穴注入部132断开，以阻隔空穴注入层13内载流子的传输。因此，可以避免阳极17传输至空穴注入层13的载流子传输至其他发光层16，而此处的其他发光层16指的是除与该阳极17对应的发光层16之外的其他发光层16，从而，可以避免各子像素20的空穴注入层13产生的漏电互相串扰，以避免各子像素20之间产生横向漏电的问题，使阳极17可以准确控制与其对应的发光层16，进而，可以避免各子像素20之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
在一些示例中，阳极17位于内切区102的面积大于阳极在隔断区101的面积。例如，阳极17位于内切区102的面积是阳极17在隔断区101的面积的3～5倍。如此使阳极17可以准确控制与其对应的发光层16，进而，可以避免各子像素20之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
在一些实施例中，如图1所示，显示面板10还包括阶梯结构18。阶梯结构18位于第一子空穴注入部131与衬底11之间。
第一子空穴注入部131位于阶梯结构18远离衬底11的一侧，阶梯结构18包括至少一层阶梯181。部分第二子空穴注入部132位于阶梯181远离衬底11的一侧的表面，所述阶梯结构被配置为确保位于阶梯181远离衬底11一侧的第二子空穴注入部132互相隔断，且确保第一子空穴注入部131与第二子空穴注入部132隔断。
具体的，阶梯181可以包括第一阶梯182。第一阶梯182又包括第一上绝缘层1821、第一中绝缘层1822与第一下绝缘层1823。其中，第一上绝缘 层1821与第一下绝缘层1823的材料可以包括氧化硅，第一中绝缘层1822可以包括氮化硅。第一下绝缘层1823在第一方向X上的长度较第一上绝缘层1821在第一方向X上的长度更长的部分为外沿部分。外沿部分在第一方向X上的长度大于等于0.15微米且小于等于0.35微米。例如，外沿部分在第一方向X上的长度可以为0.15微米，或者，外沿部分在第一方向X上的长度可以为0.2微米，或者，外沿部分在第一方向X上的长度可以为0.25微米，或者，外沿部分在第一方向X上的长度可以为0.3微米，或者，外沿部分在第一方向X上的长度可以为0.35微米，但不限于此。外沿部分在第一方向X上的长度大于等于0.15微米可以确保该阶梯181可以有效屏蔽在沉积过程中的边缘型变造成的电性不稳定问题，而外沿部分在第一方向X上的长度小于等于0.35微米为确保外沿部分投影总面积小于隔断区域的15％。需要说明的是，虽然在图1中示出的第一阶梯182内，第一上绝缘层1821、第一中绝缘层1822与第一下绝缘层1823的厚度基本相同，但图1仅是为了便于直观展现膜层结构，实际上第一中绝缘层1822的厚度远厚于第一上绝缘层1821或是第一下绝缘层1823，其他实施例中示出的阶梯181的膜层结构也同样可以参考此处的说明。
阶梯结构18还可以包括缓冲层180，该缓冲层180位于阶梯结构18与阳极17之间。由于缓冲层180远离衬底11的一侧的阶梯结构18的材料包括氧化硅，而沉积氧化硅时需要采用氧化性较强的气体，而缓冲层180则被配置为在沉积形成阶梯结构18时，避免采用氧化性较强的气体与阳极17的材料产生还原反应，而影响阳极17的性能。在形成材料包括氧化硅的膜层后，可以对缓冲层180进行刻蚀，以避免缓冲层180影响第二空穴注入部132与阳极17的电连接关系。
通过设置阶梯结构18，使部分第二子空穴注入部132位于阶梯181远离衬底11的一侧，且通过该阶梯结构18确保位于阶梯181远离衬底11一侧的第二子空穴注入部132互相隔断，且确保第一子空穴注入部131与第二子空穴注入部132隔断，从而，可以通过设置阶梯结构18，而在形成空穴注入层13时，将空穴注入层13打断为互不电连接的第二子空穴注入部132与第一子空穴注入部131，进而，可以进一步避免各子像素20的空穴注入层13产生的漏电互相串扰，以避免各子像素20之间产生横向漏电的问题，同时，可 以避免各子像素20之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
在一些实施例中，如图1所示，阶梯181包括内凹部1814，内凹部1814为阶梯181沿内切区102朝向隔断区101的方向凹陷的部分。内凹部1814位于阶梯181与第二子空穴注入部132之间。内凹部1814对应于第二空穴注入部132设置。
具体的，以图1所示的实施例为例，阶梯181可以包括第一阶梯182。第一阶梯182可以包括第一内凹部1824。第一内凹部1824为第一阶梯182沿内切区102朝向隔断区101的方向凹陷的部分，即第一内凹部1824为第一阶梯182沿第一方向X凹陷的部分。并且，第一内凹部1824所包括的第一上绝缘层1821、第一中绝缘层1822与第一下绝缘层1823中，第一中绝缘层1822沿第一方向X凹陷，从而，使得第一中绝缘层1822在第一方向X上相较第一上绝缘层1821与第一下绝缘层1823更为凹陷，以形成凹陷结构，即第一内凹部1824。
第一内凹部1824内为空隙，即第一内凹部1824内不填充其他材料，保持空隙。而在后续形成位于阶梯结构18远离衬底11一侧的膜层，例如，空穴注入层13时，由于蒸镀时离子难以进入第一阶梯182沿第二方向Z凹陷的部分。因此，也不会在第一内凹部1824内形成膜层。而通过内部保持空隙的第一内凹部1824，使得在形成第二空穴注入部132时，膜层材料存在填充入第一内凹部1824的趋势，以在第一内凹部1824处产生剪切力，从而，可以确保阶梯结构18隔断位于阶梯181远离衬底11一侧的第二子空穴注入部132，且可以确保第一子空穴注入部131与第二子空穴注入部132隔断，进而，可以避免各子像素20的空穴注入层13产生的漏电互相串扰，以避免各子像素20之间产生横向漏电的问题，同时，可以避免各子像素20之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
在一些实施例中，如图1所示，显示面板10还包括：至少两层发光层16与至少一层电荷生成层15。发光层16与电荷生成层15均位于空穴注入层13远离衬底11的一侧。
每一层电荷生成层15均包括第一子电荷生成部1501与第二子电荷生 成部1502。第一子电荷生成部1501位于隔断区101，第二子电荷生成部1502位于内切区102。在远离衬底11的方向上，发光层16与第二子电荷生成部1502交替排布。且在远离衬底11的方向上的第一层膜层与最后一层膜层均为发光层16。第二子电荷生成部1502与衬底11之间的距离小于第一子电荷生成部1501与衬底11之间的距离，且第一子电荷生成部1501与第二子电荷生成部1502相隔断。
具体的，根据图1所示出的实施例，显示面板10可以包括三层发光层16与两层电荷生成层15。显示面板10可以包括第一电荷生成层151、第二电荷生成层152、第一发光层161、第二发光层162与第三发光层163。其中，第一电荷生成层151又包括第三子电荷生成部1511与第四子电荷生成部1512，第二电荷生成层152又包括第五子电荷生成部1521与第六子电荷生成部1522。第三子电荷生成部1511与第五子电荷生成部1521位于隔断区101，第四子电荷生成部1512与第六子电荷生成部1522位于内切区102。
示例性的，第三子电荷生成部1511到第五子电荷生成部1521的距离，小于第四子电荷生成部1512到第六子电荷生成部1522的距离。如此设计，有利于保证多层发光层在第一电荷生成层151和第二电荷生成层152之间有效传递，而减缓在内切区102传递。
通过设置第一电荷生成层151与第二电荷生成层152可以实现显示叠层显示，即在第二方向Z上通过第一电荷生成层151与第二电荷生成层152时叠层设置的第一发光层161、第二发光层162与第三发光层163上下串联起来叠层发光以提高显示效率及峰值亮度等。并且，在本实施例中，叠层设置的第一发光层161、第二发光层162与第三发光层163可以分别被配置为发红色光、绿色光与蓝色光。具体的，第一发光层161可以被配置为发红色光，第二发光层162可以被配置为发绿色光，第三发光层163可以被配置为发蓝色光，但在其他实施例中不限于此。通过使叠层设置的三层发光层16分别被配置为发出红色光、绿色光与蓝色光三种不同颜色的光，从而，可以使三种光实现混色，以实现叠层设置的三层发光层16整体发出的光为白色光。
需要说明的是，显示面板10包括三层发光层16与两层电荷生成层15仅是一种可行的实施例，但在其他实施例中不限于此，显示面板10可以根据实际需要设置显示面板10所包括的发光层16与电荷生成层15的层数。
由于在本申请中，显示面板10包括位于衬底11上的子像素20。同时，显示面板10的各个膜层均为通过蒸镀工艺整层形成的膜层，而蒸镀工艺整层形成的空穴注入层13与电荷生成层15，就容易因一体成型而使位于不同子像素20的空穴注入层13之间，或者，位于不同子像素20的电荷生成层15之间存在电连接关系。而由于空穴注入层13与电荷生成层15均具有高载流子迁移率的特点。因此，在不同子像素20的空穴注入层13内传输的载流子，就容易在因一体成型而存在电连接关系的空穴注入层13或者电荷生成层15内横向流动，因此载流子便可能在整层形成的空穴注入层13或者电荷生成层15内横向流动。而由于载流子在空穴注入层13或者电荷生成层15内横向流动，各子像素20的空穴注入层13或者电荷生成层15内传输的载流子就容易互相传输，导致各子像素20的空穴注入层13或者电荷生成层15内传输的载流子互相串扰，从而，容易在各子像素20之间产生横向漏电的问题，进而，各子像素20之间横向漏电的问题又容易造成产品电学串扰不达标以及色域低的问题。
而空穴注入层13位于不同区域的部分并未位于同一平面上，即位于隔断区101的第一子空穴注入部131与位于内切区102的第二子空穴注入部132并未位于同一平面上，使得第一子空穴注入部131与第二子空穴注入部132形成了一个“凹”字形结构。同理，第三子电荷生成部1511与第四子电荷生成部1512以及第五子电荷生成部1521与第六子电荷生成部1522也形成了“凹”字形结构。而“凹”字形结构使得第一子空穴注入部131与第二子空穴注入部132，第三子电荷生成部1511与第四子电荷生成部1512，第五子电荷生成部1521与第六子电荷生成部1522均能够隔断，而不电连接，从而，可以阻隔子像素20之间在存在电连接关系的空穴注入层13或者电荷生成层15内流动的电流，进而，可以进一步避免各子像素20的空穴注入层13产生电流互相串扰，以进一步避免各子像素20之间产生横向漏电的问题，同时，也可以进一步避免各子像素20之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
在一些实施例中，如图1所示，显示面板10还包括：阴极12、电子注入层14、封装层21、驱动阵列22与平坦层23。电子注入层14位于第三发光层163远离衬底11的一侧。阴极12位于电子注入层14远离衬底11的一侧。 封装层21位于阴极12远离衬底11的一侧。该封装层21被配置为对显示面板10的膜层结构起到封装功能，避免氧气与水汽等物质进入显示面板10的膜层结构中而对显示面板10造成损伤，同时，封装层21也对显示面板10的膜层结构起到保护作用。
驱动阵列22位于阳极17与衬底11之间。阳极17与驱动阵列22电连接，并且，驱动阵列22被配置为传输驱动信号。驱动阵列22在执行指示发光的驱动信号时，控制阳极17向空穴注入层13内传输载流子。同时，驱动阵列22还被配置为反射入射至驱动阵列22的光。平坦层23位于阶梯结构18与衬底11之间，且在第一方向X上，该平坦层23与阳极17相邻。在本申请中，由于阳极17的厚度较厚，因此，在第二方向Z上容易产生较大的段差，即阳极17远离衬底11一侧的表面与衬底11在第二方向Z上的距离较大。而较大的段差又容易导致显示面板10内的膜层产生断裂等问题，从而，影响显示面板10的正常显示。而平坦层23被配置为填充阶梯结构18与衬底11之间的部分，以达到平坦层23远离衬底11一侧的表面与阳极17远离衬底11一侧的表面齐平的效果，从而，可以避免较大的段差损伤位于平坦层23远离衬底11一侧的膜层，例如，阶梯结构18。需要说明的是，虽然在本申请中，平坦层23被配置为填充阶梯结构18与衬底11之间的部分，以达到平坦层23远离衬底11一侧的表面与阳极17远离衬底11一侧的表面齐平的效果，但在其他实施例中不限于此，平坦层23远离衬底11一侧的表面与阳极17远离衬底11一侧的表面也可以不齐平，但可以确保平坦层23远离衬底11一侧的表面与阳极17远离衬底11一侧的表面之间的段差可以避免位于平坦层23远离衬底11一侧的膜层的损伤即可。
在一些实施例中，图2示出的显示面板10的发光单元的结构示意图，该发光单元包括：电子注入层14、第一发光层161、第二发光层162、第三发光层163、第一电荷生成层151、第二电荷生成层152与空穴注入层13。如图2所示，第一发光层161包括：第一空穴传输层1611、第一复合发光层1612与第一电子传输层1613。第二发光层162包括：第二空穴传输层1621、第二复合发光层1622与第二电子传输层1623。第三发光层163包括：第三空穴传输层1631、第三复合发光层1632与第三电子传输层1633。
第一电子传输层1613与第二空穴传输层1621之间设有第一电荷生成 层151，第一电子传输层1613与第二空穴传输层1621通过第一电荷生成层151电连接，以使第一发光层161与第二发光层162电连接。第二电子传输层1623与第三空穴传输层1631之间设有第二电荷生成层152，第二电子传输层1623与第三空穴传输层1631通过第二电荷生成层152电连接，以使第二发光层162与第三发光层163电连接。
在子像素20发光时，阴极12向电子注入层14输送电子，阳极17向空穴注入层13输送空穴。而输入的载流子促使第一电荷生成层151与第二电荷生成层152产生电子与空穴。第一电荷生成层151产生电子通过第一电子传输层1613传输至第一复合发光层1612，第一电荷生成层151产生空穴则通过第二空穴传输层1621传输至第二复合发光层1622。需要说明的是，虽然此处说明的是第一电荷生成层151产生的电子与空穴的流向，但是第二电荷生成层152产生电子与空穴的流向可以参照第一电荷生成层151。并且，以第一复合发光层1612为例，第一空穴传输层1611将空穴传输至第一复合发光层1612，第一电子传输层1613将电子传输至第一复合发光层1612。空穴与电子在第一复合发光层1612内复合形成激子并释放能量，促使第一复合发光层1612发光。同样需要说明的是，虽然此处说明的是第一复合发光层1612的发光原理，但是第二复合发光层1622与第三复合发光层1632的发光原理可以参照第一复合发光层1612。
需要说明的是，在图1中，内切区102主要示出的是隔断结构，而为了图示的清楚，并未示出发光层16位于内切区102的部分。但是，由于是整层形成，因此，发光层16位于内切区102的膜层结构与发光层16位于隔断区101的膜层结构相同，可以互相参照。
在一些实施例中，显示面板10还包括阶梯结构18。阶梯结构18位于第一子空穴注入部131与衬底11之间。
第一子空穴注入部131位于阶梯结构18远离衬底11的一侧，阶梯结构18包括至少一层阶梯181。部分第二子空穴注入部132位于阶梯181远离衬底11的一侧的表面，阶梯结构18被配置为确保位于阶梯181远离衬底11一侧的第二子空穴注入部132互相隔断，且确保第一子空穴注入部131与第二子空穴注入部132隔断。
第二子电荷生成部1502位于第二子空穴注入部132远离衬底11的一侧，部分第二子电荷生成部1502也位于阶梯181远离衬底11的一侧。阶梯结构18被配置为确保位于阶梯181远离衬底11的一侧的第二子电荷生成部1502互相隔断，且确保第一子空穴注入部131与第二子空穴注入部132隔断。
具体的，根据图1所示出的实施例，显示面板10可以包括两层电荷生成层15，即显示面板10可以包括第一电荷生成层151与第二电荷生成层152。其中，第一电荷生成层151又包括第三子电荷生成部1511与第四子电荷生成部1512，第二电荷生成层152又包括第五子电荷生成部1521与第六子电荷生成部1522。第三子电荷生成部1511与第五子电荷生成部1521位于隔断区101，第四子电荷生成部1512与第六子电荷生成部1522位于内切区102。
第四子电荷生成部1512位于第二子空穴注入部132远离衬底11的一侧，且部分第六子电荷生成部1522也位于阶梯181远离衬底11的一侧。位于阶梯181远离衬底11的一侧的第四子电荷生成部1512互相隔断，且与第三子电荷生成部1511隔断。而第六子电荷生成部1522位于第四子电荷生成部1512远离衬底11的一侧，且部分第六子电荷生成部1522也位于阶梯181远离衬底11的一侧。位于阶梯181远离衬底11的一侧的第六子电荷生成部1522互相隔断，且与第五子电荷生成部1521隔断。
在未设置阶梯结构18时，由于在第二方向Z上，第二子空穴注入部132相较于第一子空穴注入部131更接近衬底11。因此，第二子空穴注入部132与第一子空穴注入部131之间容易存在较大的段差。而较大的段差就容易导致沿第二方向Z延伸的部分第二子空穴注入部132断裂，影响第二子空穴注入部132与第一子空穴注入部131之间的电连接关系。而对于第四子电荷生成部1512与第六子电荷生成部1522来说也同理。
通过设置阶梯结构18，使部分第二子空穴注入部132、部分第四子电荷生成部1512与部分第六子电荷生成部1522位于阶梯181远离衬底11的一侧，且位于阶梯181远离衬底11一侧的部分第二子空穴注入部132与第一子空穴注入部131隔断，位于阶梯181远离衬底11一侧的部分第四子电荷生成部1512与第三子电荷生成部1511隔断，位于阶梯181远离衬底11一侧的部分第六子电荷生成部1522与第五子电荷生成部1521隔断，从而，可以通过阶梯结构18在形成空穴注入层13时，将空穴注入层13打断为互不电连接的 第二子空穴注入部132与第一子空穴注入部131，在形成第一电荷生成层151时，将第一电荷生成层151打断为第四子电荷生成部1512与第三子电荷生成部1511，以及在形成第二电荷生成层152时，将第二电荷生成层152打断为第六子电荷生成部1522与第五子电荷生成部1521，进而，可以进一步避免各子像素20的空穴注入层13产生的漏电互相串扰，以避免各子像素20之间产生横向漏电的问题，同时，可以避免各子像素20之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
在一些实施例中，如图1所示，空穴注入层13与电荷生成层15的总层数与阶梯181的层数相同。且一层空穴注入层13或者一层电荷生成层15对应一层阶梯181设置。而根据图1所示出的实施例，显示面板10包括一层空穴注入层13与两层电荷生成层15，则阶梯结构18也就包括三层阶梯181。
具体的，阶梯结构18可以包括层叠设置的第一阶梯182、第二阶梯183与第三阶梯184。其中，第一阶梯182可以包括第一上绝缘层1821、第一中绝缘层1822与第一下绝缘层1823，第二阶梯183可以包括第二上绝缘层1831、第二中绝缘层1832与第二下绝缘层1833，第三阶梯184可以包括第三上绝缘层1841、第三中绝缘层1842与第三下绝缘层1843。并且，第二下绝缘层1833与第一上绝缘层1821在第一方向X上的长度相同，第三下绝缘层1843与第二上绝缘层1831在第一方向X上的长度相同，而阶梯结构18如果设有更多层阶梯181，那么也能够以此类推。
以第一阶梯182、第二阶梯183与第三阶梯184在第二方向Z上的高度为厚度。第一阶梯182的厚度大于等于30纳米且小于等于55纳米。例如，第一阶梯182的厚度可以为30纳米，或者，第一阶梯182的厚度可以为40纳米，或者，第一阶梯182的厚度可以为50纳米，或者，第一阶梯182的厚度可以为55纳米，但不限于此。第一阶梯182与第二阶梯183的总厚度大于等于100纳米且小于等于150纳米。例如，第一阶梯182与第二阶梯183的总厚度可以为100纳米，或者，第一阶梯182与第二阶梯183的总厚度可以为110纳米，或者，第一阶梯182与第二阶梯183的总厚度可以为120纳米，或者，第一阶梯182与第二阶梯183的总厚度可以为130纳米，或者，第一阶梯182与第二阶梯183的总厚度可以为140纳米，或者，第一阶梯182与第二阶梯183的总厚度可以为150纳米，但不限于此。第一阶梯182、第二阶 梯183与第三阶梯184的总厚度大于等于200纳米且小于等于300纳米。例如，第一阶梯182、第二阶梯183与第三阶梯184的总厚度可以为200纳米，或者，第一阶梯182、第二阶梯183与第三阶梯184的总厚度可以为225纳米，或者，第一阶梯182、第二阶梯183与第三阶梯184的总厚度可以为250纳米，或者，第一阶梯182、第二阶梯183与第三阶梯184的总厚度可以为275纳米，或者，第一阶梯182、第二阶梯183与第三阶梯184的总厚度可以为300纳米，但不限于此。
第一阶梯182、第二阶梯183与第三阶梯184边缘的连线与衬底11的第一夹角a的角度大于等于15度且小于等于45度。例如，第一夹角a的角度可以为15度，或者，第一夹角a的角度可以为25度，或者，第一夹角a的角度可以为35度，或者，第一夹角a的角度可以为45度，但不限于此。
通过设置与空穴注入层13以及电荷生成层15的总层数的层数相同的阶梯181，且一层空穴注入层13或者一层电荷生成层15对应一层阶梯181设置，可以确保空穴注入层13以及每一电荷生成层15均能够连接至一层阶梯181，从而，可以确保空穴注入层13以及各层荷生成层15均能够通过阶梯181进行隔断的同时，也可以避免设置过多层的阶梯181，进而，可以在保证阶梯结构18能够有效对空穴注入层13以及电荷生成层15进行隔断的同时，降低成本。
在一些实施例中，每层阶梯181均包括内凹部1814，内凹部1814为阶梯181在沿远离内切区102的方向凹陷的部分。内凹部1814位于阶梯181与阶梯181对应的第二子空穴注入部132之间，或者，内凹部1814位于阶梯181与阶梯181对应的第二子电荷生成部1502之间。
具体的，第一阶梯182可以包括第一内凹部1824，第二阶梯183可以包括第二内凹部1834，第三阶梯可以包括第三内凹部1844。第一内凹部1824为阶梯181沿内切区102朝向隔断区101的方向凹陷的部分，即第一内凹部1824为第一阶梯182沿第一方向X凹陷的部分。并且，第一内凹部1824所包括的第一上绝缘层1821、第一中绝缘层1822与第一下绝缘层1823中，第一中绝缘层1822沿第一方向X凹陷，从而，使得第一中绝缘层1822在第一方向X上相较第一上绝缘层1821与第一下绝缘层1823更为凹陷，以形成凹陷结构，即第一内凹部1824。而阶梯结构18如果设有更多层阶梯181，那么 也能够以此类推，即第二内凹部1834与第三内凹部1844也可以参考第一内凹部1824的描述。
第一内凹部1824、第二内凹部1834与第三内凹部1844内均为空隙，即第一内凹部1824、第二内凹部1834与第三内凹部1844内均不填充其他材料，保持空隙。而在后续形成位于阶梯结构18远离衬底11一侧的膜层，例如，空穴注入层13时，由于蒸镀时离子难以进入第一阶梯182沿第二方向Z凹陷的部分。因此，也不会在第一内凹部1824、第二内凹部1834或是第三内凹部1844内形成膜层。而通过内部保持空隙的第一内凹部1824、第二内凹部1834与第三内凹部1844，可以将空穴注入层13通过内凹部1814与其他高导电膜层隔绝开来，同样，也可以将第一电荷生成层151或者第二电荷生成层152通过内凹部1814与其他高导电膜层隔绝开来，从而，可以避免空穴注入层13、第一电荷生成层151或者第二电荷生成层152与其他高导电膜层之间形成异常的电连接关系，而影响显示面板10的正常显示。
在一些实施例中，图3示出的是另一种显示面板10的结构示意图。如图3所示，阶梯结构18包括内切部201，内切部201位于内切区102，内切部201为阶梯结构18朝向衬底11凹陷的部分。内切部201内的阶梯181被配置为隔断第二空穴注入部132与第二子电荷生成部1502中的至少一层。
具体的，内切部201内的阶梯181可以仅隔断第二空穴注入部132，或者，内切部201内的阶梯181可以同时隔断第二空穴注入部132与第四子电荷生成部1512，或者，内切部201内的阶梯181可以同时隔断第二空穴注入部132、第四子电荷生成部1512与第六子电荷生成部1522。
通过设置位于阶梯结构18内的内切部201，以及通过内切部201内的阶梯181隔断第二空穴注入部132、第四子电荷生成部1512与第六子电荷生成部1522中的至少一层，从而，可以进一步阻隔子像素20之间在整层形成的空穴注入层13或者电荷生成层15内流动的漏电电流，进而，可以进一步避免各子像素20的空穴注入层13产生的漏电互相串扰，以避免各子像素20之间产生横向漏电的问题，同时，也可以进一步避免各子像素20之间因横向漏电问题造成的产品电学串扰不达标以及色域低的问题。
在一些实施例中，如图3所示，在相邻的内切区102内，设有的阶梯 181隔断第二空穴注入部132与第二子电荷生成部1502中的至少一层。具体的，如图3中示出的，内切区102可以包括第一内切区1021、第二内切区1022与第三内切区1023。其中，第一内切区1021与第二内切区1022均与第三内切区1023相邻。同时，该阶梯结构18的内切部201可以位于第三内切区1023。在第一内切区1021、第二内切区1022与第三内切区1023内的阶梯181，可以被配置为各自隔断第二空穴注入部132、第四子电荷生成部1512与第六子电荷生成部1522中的至少一层。
在图3所示出的实施例中，显示面板10可以包括两层电荷生成层15与一层空穴注入层13，即显示面板10可以包括第一电荷生成层151与第二电荷生成层152。其中，第一电荷生成层151又包括第三子电荷生成部1511与第四子电荷生成部1512，第二电荷生成层152又包括第五子电荷生成部1521与第六子电荷生成部1522，空穴注入层13又包括第一子空穴注入部131与第二子空穴注入部132。
位于第一内切区1021内的阶梯181被配置为隔断第二子空穴注入部132与第四子电荷生成部1512。位于第二内切区1022内的阶梯181被配置为隔断第二子空穴注入部132、第四子电荷生成部1512与第六子电荷生成部1522。位于第三内切区1023内的阶梯181被配置为隔断第二子空穴注入部132。
而通过在相邻的第一内切区1021、第二内切区1022与第三内切区1023内设置阶梯181，而阶梯181各自隔断第二空穴注入部132、第四子电荷生成部1512与第六子电荷生成部1522中的至少一层，从而，可以根据实际需求对不同子像素20之间的串扰程度进行调节，进而，可以使各子像素20根据实际需求选择设置与周围子像素20之间的阻隔效果。
在一些实施例中，在第一内切区1021的宽度，小于第二内切区1022内和/或第三内切区1023的宽度。如此设计，可以使子像素20根据实际需求选择设置与周围子像素20之间的阻隔效果。
在一些实施例中，相邻子像素20之间，相邻的第一阶梯182的距离、小于相邻的第二阶梯183的距离，且小于相邻的第三阶梯184的距离；如此形成的台阶结构，有利于减缓不同子像素20之间的串扰。
在一些实施例中，相邻子像素20之间，相邻的缓冲层180之间的距离小于相邻的第二下绝缘层1833的距离，且小于相邻的第三下绝缘层1843之间的距离；进一步的，且小于相邻的第三上绝缘层1841之间的距离。如此设计，有利于减缓不同子像素20之间的串扰程度。
本申请还提供一种电子设备，包括上述任一种显示面板10。该电子设备可以为VR/AR设备或者其他近眼显示设备，但不限于此。
本申请的上述实施例，在不产生冲突的情况下，可互为补充。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
术语“多个”指两个或两个以上，除非另有明确的限定。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (11)

  1. 一种显示面板，其特征在于，所述显示面板具有内切区与隔断区，所述内切区与所述隔断区相邻；
    所述显示面板包括：衬底、发光层与空穴注入层；
    所述发光层位于所述内切区的部分被配置执行发光功能，所述发光层位于所述衬底上；所述空穴注入层位于所述发光层与所述衬底之间，所述发光层位于所述空穴注入层远离所述衬底的一侧；
    所述空穴注入层包括第一子空穴注入部与第二子空穴注入部；所述第一子空穴注入部位于所述隔断区；所述第二子空穴注入部位于所述内切区，且位于所述发光层与所述衬底之间；所述第二子空穴注入部与所述衬底之间的距离小于所述第一子空穴注入部与所述衬底之间的距离，且所述第一子空穴注入部与所述第二子空穴注入部相隔断。
  2. 根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括阳极；所述阳极至少部分位于所述内切区，所述阳极还位于所述空穴注入层与所述衬底之间，且所述阳极还位于所述第二空穴注入部与所述衬底之间；所述阳极与所述第二子空穴注入部电连接。
  3. 根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括阶梯结构；所述阶梯结构位于所述第一子空穴注入部与所述衬底之间；
    所述第一子空穴注入部位于所述阶梯结构远离所述衬底的一侧，所述阶梯结构包括至少一层阶梯；部分所述第二子空穴注入部位于所述阶梯远离所述衬底的一侧的表面，所述阶梯结构被配置为确保位于所述阶梯远离所述衬底一侧的所述第二子空穴注入部互相隔断，且确保所述第一子空穴注入部与所述第二子空穴注入部隔断。
  4. 根据权利要求3所述的显示面板，其特征在于，所述阶梯包括内凹部，所述内凹部为所述阶梯沿所述内切区朝向所述隔断区的方向凹陷的部分；所述内凹部位于所述阶梯与所述第二子空穴注入部之间；
    所述内凹部对应于所述第二空穴注入部设置。
  5. 根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括：至少两层发光层与至少一层电荷生成层；所述发光层与所述电荷生成层均位于所述空穴注入层远离所述衬底的一侧；
    每一层所述电荷生成层均包括第一子电荷生成部与第二子电荷生成部；所述第一子电荷生成部位于所述隔断区，所述第二子电荷生成部位于所述内切区；在远离所述衬底的方向上，所述发光层与所述第二子电荷生成部交替排布；且在远离所述衬底的方向上的第一层膜层与最后一层膜层均为所述发光层；所述第二子电荷生成部与所述衬底之间的距离小于所述第一子电荷生成部与所述衬底之间的距离，且所述第一子电荷生成部与所述第二子电荷生成部相隔断。
  6. 根据权利要求5所述的显示面板，其特征在于，所述显示面板还包括阶梯结构；所述阶梯结构位于所述第一子空穴注入部与所述衬底之间；
    所述第一子空穴注入部位于所述阶梯结构远离所述衬底的一侧，所述阶梯结构包括至少一层阶梯；部分所述第二子空穴注入部位于所述阶梯远离所述衬底的一侧的表面，所述阶梯结构被配置为确保位于所述阶梯远离所述衬底一侧的所述第二子空穴注入部互相隔断，且确保所述第一子空穴注入部与所述第二子空穴注入部隔断；
    所述第二子电荷生成部位于所述第二子空穴注入部远离所述衬底的一侧，部分所述第二子电荷生成部也位于所述阶梯远离所述衬底的一侧；所述阶梯结构被配置为确保位于所述阶梯远离所述衬底的一侧的所述第二子电荷生成部互相隔断，且确保所述第一子空穴注入部与所述第二子空穴注入部隔断。
  7. 根据权利要求6所述的显示面板，其特征在于，所述空穴注入层与所述电荷生成层的总层数与所述阶梯的层数相同；且一层所述空穴注入层或者一层所述电荷生成层对应一层所述阶梯设置。
  8. 根据权利要求7所述的显示面板，其特征在于，每层所述阶梯均包括内凹部，所述内凹部为所述阶梯在沿远离内切区的方向凹陷的部分；所述内凹部位于所述阶梯与所述阶梯对应的所述第二子空穴注入部之间，或者，所述内凹部位于所述阶梯与所述阶梯对应的所述第二子电荷生成部之间。
  9. 根据权利要求6所述的显示面板，其特征在于，所述阶梯结构包括内切部，所述内切部位于所述内切区，所述内切部为所述阶梯结构朝向所述衬底凹陷的部分；所述内切部内的所述阶梯被配置为隔断所述第二空穴注入部与所述第二子电荷生成部中的至少一层。
  10. 根据权利要求9所述的显示面板，其特征在于，在相邻的所述内切区 内，设有的所述阶梯隔断所述第二空穴注入部与所述第二子电荷生成部中的至少一层。
  11. 一种电子设备，其特征在于，包括权利要求1至权利要求10任一项所述的显示面板。
PCT/CN2023/122070 2022-11-15 2023-09-27 显示面板及电子设备 WO2024103981A1 (zh)

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