WO2024103589A1 - 一种基于相位误差自动校正的高频晶体振荡器 - Google Patents

一种基于相位误差自动校正的高频晶体振荡器 Download PDF

Info

Publication number
WO2024103589A1
WO2024103589A1 PCT/CN2023/083227 CN2023083227W WO2024103589A1 WO 2024103589 A1 WO2024103589 A1 WO 2024103589A1 CN 2023083227 W CN2023083227 W CN 2023083227W WO 2024103589 A1 WO2024103589 A1 WO 2024103589A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
phase
frequency
frequency crystal
control signal
Prior art date
Application number
PCT/CN2023/083227
Other languages
English (en)
French (fr)
Inventor
王子轩
王鑫
蔡志匡
郭宇锋
姚佳飞
张文京
殷允金
谢祖帅
Original Assignee
南京邮电大学
南京邮电大学南通研究院有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南京邮电大学, 南京邮电大学南通研究院有限公司 filed Critical 南京邮电大学
Publication of WO2024103589A1 publication Critical patent/WO2024103589A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/06—Modifications of generator to ensure starting of oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator

Definitions

  • the invention belongs to the technical field of integrated circuits.
  • Crystal oscillators are widely used in integrated circuits and are the basic components of the frequency multiplication operation of the phase-locked loop system. Their startup time affects the data transmission and reception time interval of the entire system and plays a decisive role in the power consumption of the system using the duty cycle working mode. With the rapid development of integrated circuits and the popularization of low-power application scenarios, it is very important to design a fast-starting high-frequency crystal oscillator.
  • the structures of fast-start high-frequency crystal oscillators are mainly divided into two types, one is a high-frequency crystal oscillator based on a traditional transconductance amplifier, and the other is a fast-start high-frequency crystal oscillator based on energy injection.
  • the startup of the fast-start high-frequency crystal oscillator based on the traditional transconductance amplifier mainly depends on the negative resistance of the circuit, and is supplemented by load regulation technology, so that the high-frequency crystal obtains a larger loop gain during the startup process to achieve fast startup.
  • the implementation of this method is limited by the initial energy state of the crystal.
  • the transconductance amplifier needs to amplify and select the weak noise signal in the crystal.
  • the fast-start high-frequency crystal oscillator based on energy injection uses energy injection to help the crystal establish an energy state and complete frequency selection in a shorter time. After the crystal amplitude reaches the expected amplitude, the energy injection is disconnected, and the crystal is connected to the amplifier to maintain the steady-state oscillation of the crystal.
  • the energy injection scheme is the current mainstream fast start-up scheme. Compared with traditional amplifiers, the advantage of energy injection is that it can greatly reduce the time of crystal frequency selection amplification, the energy growth is fast in a short time, and the start-up time is greatly reduced.
  • most energy injections currently use a double-end injection method, that is, differential injection is performed at both ends of the crystal. Since both ends of the crystal are square wave injection signals during the injection process, the injection effect cannot be determined before the injection is completed. Therefore, the current mainstream energy injection method is blind, and it is impossible to monitor the injection situation in real time during the injection process, and it is impossible to determine whether the injection is effective or the optimal injection duration.
  • the energy injection efficiency is related to the phase error between the injection signal and the oscillation signal.
  • the energy injection efficiency is significantly reduced. Since the injection signal frequency and the oscillation frequency cannot be exactly equal, the frequency difference between them will cause the phase error to accumulate over time. In the current mainstream energy injection scheme, the energy injection time is limited by the frequency difference between the injection signal frequency and the oscillation frequency. For larger frequency errors, the energy obtained by the crystal from the energy injection process is extremely small, because a larger frequency difference means rapid phase error accumulation and less energy injection.
  • the present invention provides a high-frequency crystal oscillator based on automatic correction of phase error.
  • the present invention provides a high-frequency crystal oscillator based on automatic phase error correction, comprising a high-frequency crystal, a first and a second load capacitor, a ring oscillator, an 8-frequency division circuit, a twisted ring counter, a peak detector, a buffer, a digital module, a multiplexer, an amplifier, and a first and a second single-pole double-throw switch; one end of the high-frequency crystal is recorded as XO IN , and the other end is recorded as XO OUT ; the fixed end of the first single-pole double-throw switch is connected to the XO IN end of the high-frequency crystal, the first moving end of the first single-pole double-throw switch is connected to the multiplexer, and the second moving end is connected to one end of the first capacitor and the input end of the amplifier; the fixed end of the second single-pole double-throw switch is connected to the XO OUT end of the high-frequency crystal, the first moving end of the second single-pole double-throw
  • a switch control signal EN INJ is generated by a digital module to control the fixed end of the first single-pole double-throw switch to be connected to the first moving end of the first single-pole double-throw switch, and to control the fixed end of the second single-pole double-throw switch to be connected to the first moving end of the second single-pole double-throw switch; at the same time, the ring oscillator generates a square wave signal F 64 ⁇ , and transmits the square wave signal to an 8-frequency division circuit and a peak detector; the 8-frequency division circuit divides the square wave signal to generate a frequency division signal F 8 ⁇ , and transmits F 8 ⁇ to a twisted ring counter, and the twisted ring counter divides F 8 ⁇ again to generate 8 signals Phase[7:0] with the same frequency and different phases, and transmits the signal Phase[7:0] to a multiplexer; the peak detector also receives a signal PKD IN outputted from the OUT end of the high
  • the digital module switches the control signal EN[7:0] by judging the edge relationship between the signal PD IN and the signal BUFF OUT , and transmits the switched control signal EN[7:0] to the multiplexer; the multiplexer selects a signal from the signal Phase[7:0] according to the size of the square wave signal F 64 ⁇ frequency and the control signal EN[7:0] and records it as the signal PD IN and inputs it into the digital module; the multiplexer also selects a signal from the signal Phase[7:0] according to the control signal EN[7:0] as the injection signal and injects it into the XO IN terminal of the high-frequency crystal through the first single-pole double-throw switch.
  • the injection signal is coupled to the XO OUT terminal through the high-frequency crystal, and is superimposed with the high-frequency oscillation signal F OSC generated by the high-frequency crystal at the XO OUT terminal to obtain the signal PKD IN .
  • the signal PKD IN is input to the peak detector through a second single-pole double-throw switch;
  • control signal EN INJ controls the fixed end of the first SPDT switch to be connected to the second movable end of the first SPDT switch, and controls the fixed end of the second SPDT switch to be connected to the second movable end of the second SPDT switch.
  • the twisted ring counter includes first to fourth triggers; the first to fourth triggers are all D triggers, Each of the triggers has a data input terminal, a clock control terminal, a first output terminal and a second output terminal, wherein the signal output by the second output terminal is an inverted signal of the signal output by the first output terminal; the clock control terminals of the first to fourth triggers are all connected to the signal F 8 ⁇ ;
  • the data input terminal of the first trigger is connected to the first output terminal of the fourth trigger.
  • the signal outputted from the first output terminal of the first trigger is recorded as the first bit signal in Phase[7:0] as Phase[0] and connected to the data input terminal of the second trigger.
  • the signal outputted from the first output terminal of the second trigger is recorded as the second bit signal in Phase[7:0] as Phase[1] and connected to the data input terminal of the third trigger.
  • the signal outputted from the first output terminal of the third trigger is recorded as the third bit signal in Phase[7:0] as Phase[2] and connected to the data input terminal of the fourth trigger.
  • the signal outputted from the first output terminal of the fourth trigger is recorded as the fourth bit signal in Phase[7:0] as Phase[3].
  • the peak detector includes a dynamic comparator, a third capacitor, a PMOS tube, an NMOS tube and a current source;
  • the inverting input end of the dynamic comparator is connected to the signal PKD IN as the input end of the peak detector;
  • the non-inverting input end of the dynamic comparator is connected to the drain of the NMOS tube and one end of the third capacitor;
  • the source of the NMOS tube and the other end of the third capacitor are both grounded;
  • the output end of the dynamic comparator is connected to the gate of the PMOS tube as the output end of the peak detector, the source of the PMOS tube is connected to the power supply voltage VDD through the current source, and the drain of the PMOS tube is connected to one end of the third capacitor;
  • the clock input signal of the dynamic comparator is the signal F 64 ⁇ .
  • the multiplexer selects a signal in the signal Phase[7:0] as an injection signal according to the control signal EN[7:0]: when the i-th signal EN[i] in the signal EN[7:0] is 1, the i-th signal Phase[i] in the signal Phase[7:0] is selected as the injection signal, 0 ⁇ i ⁇ 7.
  • the digital module switches the 8-bit control signal EN[7:0] by determining the edge relationship between the signal PD IN and the signal BUFF OUT . Specifically:
  • the multiplexer selects a signal from the signal Phase[7:0] according to the magnitude of the square wave signal F 64 ⁇ the frequency and the control signal EN[7:0] and records it as the signal PD IN .
  • the multiplexer selects a signal from the signal Phase[7:0] according to the magnitude of the square wave signal F 64 ⁇ the frequency and the control signal EN[7:0] and records it as the signal PD IN .
  • the digital module also receives an injection signal Phase SEL .
  • the switch control signal EN INJ is 1, and the falling edge of the Phase SEL signal is counted.
  • the digital module sets EN INJ to 0.
  • the present invention adopts single-ended injection, which can detect the injection situation in real time, avoid blind injection, and ensure continuous and efficient energy injection with a large amplitude; at the same time, combined with the current injection technology requirements for the frequency accuracy of the injection source, the present invention provides a phase error automatic correction technology, even for a large frequency error, the phase error can be automatically corrected through the technology of phase error, so that the phase error is always kept within 45°, extending the effective injection time and ensuring efficient energy injection, greatly reducing the frequency accuracy requirements of the signal source that generates the energy injection signal, breaking the previous strict restrictions on the frequency accuracy of the injection signal source on the high-frequency crystal start-up time, thereby reducing the accuracy requirements for the design and calibration of the injection signal source on the high-frequency crystal oscillator circuit chip, and significantly improving the chip yield.
  • Fig. 1 is an overall circuit diagram of the present invention
  • FIG2 is a circuit diagram of a twisted ring counter according to the present invention.
  • FIG3 is a circuit diagram of a peak detector according to the present invention.
  • FIG4 is a simulation waveform diagram of the ring oscillator, the 8-frequency division circuit and the twisted ring counter when the frequency of the high-frequency crystal oscillator of the present invention is 24 MHz and the frequency of the ring oscillator is 1.54368 GHz (>64 ⁇ 24 MHz);
  • FIG. 5 is a waveform diagram of the working timing simulation of the digital module detecting the phase error when the frequency of the high-frequency crystal oscillator of the present invention is 24 MHz and the frequency of the ring oscillator is 1.54368 GHz (>64 ⁇ 24 MHz);
  • FIG6 is a simulation waveform diagram of the digital module continuously changing the injection signal phase control word according to the preset logic when the frequency of the high-frequency crystal oscillator of the present invention is 24 MHz and the frequency of the ring oscillator is 1.54368 GHz (>64 ⁇ 24 MHz);
  • FIG. 7 shows a high frequency crystal oscillator of the present invention having a frequency of 24 MHz and a ring oscillator having a frequency of 1.54368 GHz (>64 ⁇ 24MHz), the simulation waveforms at both ends of the high-frequency crystal and the amplifier;
  • FIG8 is a simulation waveform diagram of the ring oscillator, the 8-frequency divider circuit and the twisted ring counter when the frequency of the high-frequency crystal oscillator of the present invention is 24 MHz and the frequency of the ring oscillator is 1.52832 GHz ( ⁇ 64 ⁇ 24 MHz);
  • FIG9 is a waveform diagram of the working timing simulation of the digital module detecting the phase error when the frequency of the high-frequency crystal oscillator of the present invention is 24 MHz and the frequency of the ring oscillator is 1.52832 GHz ( ⁇ 64 ⁇ 24 MHz);
  • FIG10 is a simulation waveform diagram of the digital module continuously changing the injection signal phase control word according to the preset logic when the frequency of the high-frequency crystal oscillator of the present invention is 24 MHz and the frequency of the ring oscillator is 1.52832 GHz ( ⁇ 64 ⁇ 24 MHz);
  • FIG. 11 is a simulation waveform diagram of the two ends of the high-frequency crystal and the two ends of the amplifier when the frequency of the high-frequency crystal oscillator of the present invention is 24 MHz and the frequency of the ring oscillator is 1.52832 GHz ( ⁇ 64 ⁇ 24 MHz).
  • this embodiment provides a high-frequency crystal oscillator based on automatic phase error correction, including a high-frequency crystal, load capacitors C L1 and C L2 , a ring oscillator RO, an 8-frequency division circuit, a twisted ring counter, a peak detector, a buffer Buffer, a digital module, a multiplexer MUX and an amplifier;
  • the high-frequency crystal is a two-terminal component, used to accurately generate a high-frequency oscillation signal with a frequency of F OSC , the left end of which is XO IN for energy injection, and the right end of which is XO OUT for phase detection;
  • the load capacitors C L1 and C L2 are both two-terminal components, used to calibrate the oscillation frequency of the high-frequency crystal, the lower plate of C L1 is grounded, the upper plate of C L1 is connected to the amplifier input terminal AMP IN , the lower plate of C L2 is grounded, and the upper plate of C L2 is connected to the amplifier output terminal AMP
  • the signal Phase[7:0] output by the output end of the twisted ring counter is connected to the 8 input ends of the multiplexer MUX respectively, becoming the selected signal of MUX;
  • the peak detector is used to detect the peak value of the input signal, the input signal of the peak detector is the high-frequency crystal XO OUT output signal PKD IN and the signal F 64 ⁇ output by RO, and the peak detector detects the peak value of the signal PKD IN
  • the peak detector uses the square wave signal F 64 ⁇ as the high-frequency working clock, reflects the peak position of the signal PKD IN by outputting the pulse signal PKD OUT , and transmits the pulse signal PKD OUT to the buffer;
  • the buffer Buffer is used to extend the negative pulse width of the signal PKD OUT to facilitate the processing of the digital module, the buffer Buffer obtains the extended pulse signal BUFF OUT , and transmits BUFF OUT to the digital module;
  • the digital module is used to identify the phase error between the injection signal and the oscil
  • the twisted ring counter includes four D flip-flops DFF1 to DFF4; each D flip-flop has a data input terminal D, a clock control terminal C, a first output terminal Q and a second output terminal Q n , the signal output by the second output terminal is an inverted signal of the signal output by the first output terminal; the clock control terminals of the first to fourth flip-flops are all connected to the signal F 8 ⁇ .
  • the data input terminal D1 of the first D flip-flop DFF1 is connected to the first output terminal Q4 of the fourth D flip-flop DFF4, the clock control terminal C1 is connected to the 8-frequency division circuit output signal F8 ⁇ , the first output terminal Q1 is connected to the data input terminal D2 of the second D flip-flop DFF2 and serves as the output signal Phase[0], and the second output terminal Qn1 of the first D flip-flop serves as the output signal Phase[4];
  • the data input terminal D2 of the second D flip-flop DFF2 is connected to the first output terminal Q1 of the first D flip-flop DFF1, the clock control terminal C2 is connected to the 8-frequency division circuit output signal F8 ⁇ , the first output terminal Q2 is connected to the data input terminal D3 of the third D flip-flop DFF3 and serves as the output signal Phase[1], and the second output terminal Qn2 serves as the output signal Phase[5];
  • the data input terminal D3 of the third D flip-flop DFF3 is connected to the first
  • Phase[7]; 4 D flip-flops complete the 8-frequency division of the input signal F 8 ⁇ , and simultaneously generate 8 channels of in-frequency but out-of-phase signals Phase[7:0], with a frequency of approximately F OSC .
  • the peak detector includes a dynamic comparator DCMP, a capacitor C PKD , a PMOS transistor M 1 , an NMOS transistor M 2 and a current source I ref .
  • the input terminal A (inverting input terminal) of the dynamic comparator is the input terminal of the peak detector
  • the input terminal B (non-inverting input terminal) of the dynamic comparator is connected to the drain of the NMOS tube M2 , the upper plate of the capacitor C PKD , and the drain of the PMOS tube M1
  • the RO output signal F 64 ⁇ is used as the clock input signal of the dynamic comparator
  • the output terminal of the dynamic comparator is connected to the gate of the PMOS tube M1 and serves as the output terminal of the peak detector
  • the lower plate of the capacitor C PKD is grounded, the upper plate is connected to the input terminal B of the dynamic comparator, the drain of the NMOS tube M2 , and the drain of the PMOS tube M1
  • the gate of the PMOS tube M1 is connected to the output terminal of the dynamic comparator DCMP
  • the drain is connected to the upper plate of the capacitor C PKD , the input terminal B of the dynamic comparator and the drain of the NMOS tube M2 , and
  • the peak detector has a variable operating frequency.
  • the peak detector can be set to detect the peak once every 1, 2, or 4 cycles according to specific needs.
  • the selected signal Phase[7:0] of the multiplexer MUX is provided by a twisted ring counter, and the control signal EN[7:0] is provided by a digital module; the control signal EN[7:0] corresponds one-to-one to the selected signal Phase[7:0], that is, EN[i] (0 ⁇ i ⁇ 7) controls the on and off of the Phase[i] (0 ⁇ i ⁇ 7) signal.
  • the other output terminal PD IN of the multiplexer depends not only on the control signal EN[7:0], but also on the size of the RO output frequency F 64 ⁇ .
  • F 64 ⁇ is approximately 64 times the crystal oscillation frequency F OSC , but the two are not exactly equal.
  • the output rule of the signal PD IN is as follows:
  • the multiplexer selects Phase[i+1] as the output PD IN .
  • the digital module determines the edge relationship between the input signal BUFF OUT and PD IN ; since BUFF OUT is obtained by peak detection of the waveform of the XO OUT output signal PKD IN , it reflects PKD IN , that is, the phase information of the crystal oscillation signal, and PD IN is a signal that differs from the injection signal Phase SEL by 45°, and indirectly contains the phase information of the injection signal Phase SEL , the digital module can identify the phase error between the injection signal Phase SEL and the oscillation signal PKD IN by determining the edge relationship between the input signal BUFF OUT and PD IN ; when the digital module detects that the phase difference between the injection signal Phase SEL and the oscillation signal PKD IN reaches 45°, the digital module changes the value of EN[7:0], selects a signal from Phase[7:0] according to the preset logic, and assigns it to the injection signal Phase SEL and the output signal PD IN , the phase error determination method and the EN[7:0] value
  • the digital module detects the value of BUFF OUT at the specified rising edge of PD IN .
  • EN[7] is set to 0 and EN[0] is set to 1.
  • the digital module detects the value of BUFF OUT at the specified falling edge of PD IN .
  • EN[0] is set to 0 and EN[7] is set to 1.
  • the digital module In the process of the digital module continuously switching the phase of the Phase SEL signal to inject into the XO IN end of the crystal, the digital module sets EN INJ to 1, controls SW 1 and SW 2 , connects Phase SEL to XO IN , and connects PKD IN to XO OUT .
  • This process is called the injection phase, which is the process of starting the high-frequency crystal.
  • the crystal oscillator After the injection is completed, the crystal oscillator enters the maintenance phase, and the digital module sets EN INJ to 0 (as shown in Figure 1, the input signal C[9:0] of the digital module is used to preset the number of injections, and the digital module counts the falling edge of the Phase SEL signal.
  • the digital module sets EN INJ to 0 and ends the injection behavior), controls SW 1 and SW 2 , connects AMP IN to XO IN, and connects AMP OUT to XO OUT.
  • the digital module sets EN INJ to 0 (as shown in Figure 1, the input signal C[9:0] of the digital module is used to preset the number of injections, and the digital module counts the falling edge of the Phase SEL signal.
  • the digital module sets EN INJ to 0 and ends the injection behavior).
  • the capacitance of capacitors CL1 and CL2 can be adjusted automatically to stabilize the crystal oscillation frequency and optimize the phase noise and jitter performance; the amplifier maintains the crystal oscillation signal so that the oscillation signal will not decay and disappear after the energy injection is cut off, thus providing a stable oscillation signal.
  • the embodiment of the invention is a fast-start high-frequency crystal oscillator based on the phase error automatic correction technology, the high-frequency crystal frequency is 24 MHz and the ring oscillator frequency is 1.54368 GHz (>64 ⁇ 24 MHz), and the simulation waveforms are shown in FIGS. 4 , 5 , 6 and 7 .
  • the ring oscillator outputs a square wave signal F 64 ⁇ with a frequency of 1.54368 GHz.
  • the 8-divider circuit divides F 64 ⁇ by 8 to obtain a F 8 ⁇ signal.
  • the twisted ring counter further divides the F 8 ⁇ signal and generates 8 same-frequency but different-phase signals Phase[7:0] at the same time.
  • the frequency is approximately F OSC , and Phase[j] leads Phase[j+1] by 45° (i ⁇ 0).
  • PKD IN is the input signal of the peak detector.
  • the peak detector detects the peak value once every 4 cycles to obtain an output signal PKD OUT reflecting whether the peak value is increasing.
  • PKD OUT reflecting whether the peak value is increasing.
  • the peak detector monitors the peak growth.
  • the negative pulse width of PKD OUT and BUFF OUT is missing, it indicates that the peak value is no longer increasing.
  • phase of the injection signal Phase SEL needs to be switched; then, the digital module detects that BUFF OUT is 1 at the specified falling edge of PD IN , that is, the negative pulse width is missing, then the digital module sets EN[3] to 0, sets EN[4] to 1, selects Phase[4] as the injection signal and assigns it to Phase SEL , and continues energy injection.
  • EN[7:0] which is used to control the phase of the injection signal Phase SEL , keeps jumping to ensure continuous and efficient energy injection of the crystal.
  • the control signal EN INJ changes from 1 to 0, and the high-frequency crystal is connected to the amplifier to maintain steady-state oscillation.
  • the early stage of the energy injection process uses single-ended injection, XO IN is used for square wave injection, and XO OUT is used to detect phase error.
  • the last injection of the energy injection process uses double-ended injection, and both XO IN and XO OUT are square waves, in order to further improve the energy injection efficiency.
  • the control signal EN INJ changes from 1 to 0, the crystal is connected to the amplifier, and waveforms appear at the amplifier input AMP IN and output AMP OUT .
  • the simulation waveforms are shown in FIGS. 8 , 9 , 10 , and 11 .
  • the ring oscillator outputs a square wave signal F 64 ⁇ with a frequency of 1.52832 GHz.
  • the divide-by-8 circuit divides F 64 ⁇ by 8 to obtain a F 8 ⁇ signal.
  • the twisted ring counter further divides the F 8 ⁇ signal and generates 8 in-frequency but out-of-phase signals Phase[7:0] at the same time.
  • the frequency is approximately F OSC , and Phase[i] leads Phase[i+1] by 45°.
  • PKD IN is the input signal of the peak detector.
  • the peak detector detects the peak value once every 2 cycles to obtain an output signal PKD OUT reflecting whether the peak value increases.
  • the BUFF OUT value collected by PD IN at the specified falling edge is 0, it indicates that the phase error has accumulated to 45°. If Phase[5] is continued to be injected, the efficiency will be reduced and even the crystal energy growth will be inhibited. It is necessary to switch the phase of the injection signal Phase SEL .
  • the digital module sets EN[5] to 0 and EN[4] to 1, selects Phase[4] as the injection signal and assigns it to Phase SEL , and continues energy injection.
  • EN[7:0] which is used to control the phase of the injection signal Phase SEL , keeps jumping to ensure continuous and efficient energy injection of the crystal.
  • the control signal EN INJ changes from 1 to 0, and the crystal is connected to the amplifier to maintain steady-state oscillation.
  • the early stage of the energy injection process uses single-ended injection, XO IN is used for square wave injection, and XO OUT is used to detect phase error.
  • the last injection of the energy injection process uses double-ended injection, and both XO IN and XO OUT are square waves, in order to further improve the energy injection efficiency.
  • the control signal EN INJ changes from 1 to 0, the crystal is connected to the amplifier, and waveforms appear at the amplifier input AMP IN and output AMP OUT .

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本发明公开了一种基于相位误差自动校正的高频晶体振荡器，包括高频晶体、负载电容、两个单刀双掷开关、环形振荡器、8分频电路、扭环形计数器、峰值检测器、缓冲器、数字模块、多路选择器和放大器，本发明在电路对高频晶体进行能量注入的同时，检测注入信号与晶体振荡信号之间的相位误差并自动校正，使相位误差始终小于45°。本发明保证了高频晶体内部能量持续高效的线性增长，大大降低晶体达到稳定振荡幅度所需的启动时间，实现快速启动；且基于相位误差自动校正技术，本发明在极大地降低启动时间的同时，大幅降低了产生能量注入信号的信号源频率精度要求，本发明显著地提升了芯片良率。

Description

一种基于相位误差自动校正的高频晶体振荡器 技术领域
本发明属于集成电路技术领域。
背景技术
晶体振荡器在集成电路中有着广泛的应用，是锁相环系统倍频操作的基础部件，其启动时间影响了整个系统的数据收发时间间隔，对于采用占空比工作方式的系统功耗具有决定性作用。随着集成电路的飞速发展与低功耗应用场景的普及，设计一款快速启动的高频晶体振荡器至关重要。
目前，快速启动高频晶体振荡器的结构主要分为两种，一种是基于传统跨导放大器的高频晶体振荡器，另一种是基于能量注入的快速启动高频晶体振荡器。其中，基于传统跨导放大器的快速启动高频晶体振荡器的启动主要依赖电路的负阻，同时辅以负载调节技术，使高频晶体在启动过程中获得较大的环路增益以实现快速启动，但是，该方法的实施受限于晶体的初始能量状态，跨导放大器需要将晶体中微弱的噪声信号进行放大与选频，即使有其他辅助技术，其启动时间也只能相对减小，无法实现大幅降低。基于能量注入的快速启动高频晶体振荡器采用能量注入的方式在较短的时间内帮助晶体建立能量状态并完成选频，在晶体振幅达到预期振幅之后，断开能量注入，将晶体与放大器相连，用于维持晶体的稳态振荡。
能量注入方案是目前主流的快速启动方案，与传统放大器相比，能量注入的优点在于，能够大幅降低晶体选频放大的时间，短时间内能量增长快，大幅降低启动时间。但是，目前大多数能量注入都采用双端注入方式，即在晶体的两端进行差分注入，由于注入过程中晶体两端均为方波注入信号，在注入结束之前，注入效果无法确定，因此目前主流的能量注入方法具有盲目性，无法在注入过程中实时监测注入情况，无法判断注入是否有效，无法判断最优注入持续时间。此外，能量注入效率与注入信号和振荡信号之间的相位误差相关，当相位误差大于45°，能量注入效率明显降低。由于注入信号频率和振荡频率不可能精确相等，它们之间的频率差会导致相位误差随时间的累积，目前的主流能量注入方案，能量注入时间都受限于注入信号频率和振荡频率之间的频率差，对于较大的频率误差，晶体从能量注入过程获取的能量极小，原因是较大的频率差意味着快速的相位误差累积与较少的能量注入。
发明内容
发明目的：为了解决上述现有技术存在的问题，本发明提供了一种基于相位误差自动校正的高频晶体振荡器。
技术方案：本发明提供了一种基于相位误差自动校正的高频晶体振荡器，包括高频晶体、第一、第二负载电容、环形振荡器、8分频电路、扭环形计数器、峰值检测器、缓冲器、数字模块、多路选择器、放大器以及第一、第二单刀双掷开关；将高频晶体一端记为XOIN，另一端记为XOOUT；所述第一单刀双掷开关的不动端与高频晶体XOIN端连接，第一单刀双掷开关的第一动端连接多路选择器，第二动端连接第一电容的一端和放大器的输入端；所述第二单刀双掷开关的不动端与高频晶体的XOOUT端连接，第二单刀双掷开关的第一动端连接峰值检测器，第二动端连接第二电容的一端和放大器的输出端，第一、第二电容的另外一端均接地；
在启动高频晶体振荡器时，采用数字模块产生开关控制信号ENINJ，控制第一单刀双掷开关的不动端连接第一单刀双掷开关的第一动端，控制第二单刀双掷开关的不动端连接第二单刀双掷开关的第一动端；同时所述环形振荡器产生方波信号F64×，并将该方波信号传送至8分频电路和峰值检测器；8分频电路对方波信号进行分频，产生一个分频信号F8×，并将F8×传送至扭环形计数器，所述扭环形计数器对F8×进行再分频，产生8个频率相同相位不同的信号Phase[7:0]，并将信号Phase[7:0]传送至多路选择器中；所述峰值检测器还接受高频晶体XOOUT端输出的信号PKDIN，所述峰值检测器以方波信号F64×作为高频工作时钟，通过输出脉冲信号PKDOUT反映信号PKDIN的峰值位置，并将脉冲信号PKDOUT传送至缓冲器中，所述缓冲器扩展脉冲信号PKDOUT的负脉宽，得到扩展后的脉冲信号BUFFOUT，并将BUFFOUT传送至数字模块；所述数字模块产生初始的控制信号EN[7:0]，该控制信号为8位控制信号，所述数字模块通过判别信号PDIN和信号BUFFOUT之间的边沿关系，对控制信号EN[7:0]进行切换，并将切换后的控制信号EN[7:0]传送至多路选择器；所述多路选择器根据方波信号F64×频率的大小以及控制信号EN[7:0]，在信号Phase[7:0]中选择一个信号并记为信号PDIN输入至数字模块；多路选择器还根据控制信号EN[7:0]在信号Phase[7:0]中选择一个信号作为注入信号通过第一单刀双掷开关注入至高频晶体的XOIN端，该注入信号通过高频晶体耦合到XOOUT端，并与高频晶体产生的高频振荡信号FOSC在XOOUT端叠加后得到信号PKDIN，信号PKDIN通过第二单刀双掷开关输入至峰值检测器；
在维持阶段，控制信号ENINJ控制第一单刀双掷开关的不动端与第一单刀双掷开关的第二动端连接，控制第二单刀双掷开关的不动端与第二单刀双掷开关的第二动端连接。
进一步的，所述扭环形计数器包括第一～四触发器；第一～四触发器均为D触发器， 均具有数据输入端，时钟控制端，第一输出端和第二输出端，所述第二输出端输出的信号为第一输出端输出信号的反相信号；所述第一～四触发器的时钟控制端均连接信号F8×；
第一触发器的数据输入端连接第四触发器的第一输出端，第一触发器第一输出端输出的信号作为Phase[7:0]中的第一位信号记为Phase[0]，并连接第二触发器的数据输入端；第二触发器第一输出端输出的信号作为Phase[7:0]中的第二位信号记为Phase[1]，并连接第三触发器的数据输入端；第三触发器的第一输出端输出的信号作为Phase[7:0]中的第三位信号记为Phase[2]，并与第四触发器的数据输入端连接；第四触发器的第一输出端输出的信号作为Phase[7:0]中的第四位信号记为Phase[3]；第一～四触发器的第二输出端输出的信号依次作为Phase[7:0]中的第五、第六、第七以及第八位信号，依次记为Phase[4]、Phase[5]、Phase[6]、Phase[7]；信号Phase[j]的相位超前信号Phase[j+1]的相位45°，j＝0,1,2,…6。
进一步的，所述峰值检测器包括动态比较器、第三电容、PMOS管、NMOS管和电流源；所述动态比较器的反相输入端作为峰值检测器的输入端连接信号PKDIN；动态比较器的同相输入端与NMOS管的漏极以及第三电容的一端连接；所述NMOS管的源极和第三电容另外一端均接地；动态比较器的输出端作为峰值检测器的输出端与PMOS管的栅极连接，所述PMOS管的源极通过电流源与电源电压VDD连接，PMOS管的漏极连接第三电容的一端；所述动态比较器的时钟输入信号为信号F64×。
进一步的，所述多路选择器根据控制信号EN[7:0]在信号Phase[7:0]中选择一个信号作为注入信号具体为：当信号EN[7:0]中第i位信号EN[i]为1时，则在信号Phase[7:0]中选择第i个信号Phase[i]作为注入信号，0≤i≤7。
进一步的，所述数字模块还通过判别信号PDIN和信号BUFFOUT之间的边沿关系，对8位控制信号EN[7:0]进行切换具体为：
若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×>64×FOSC时，数字模块在PDIN的指定上升沿处检测信号BUFFOUT的值，若BUFFOUT为1，则将EN[i]置0，同时将EN[i+1]置1，如果i＝7时，则将EN[7]置0，同时将EN[0]置1；若BUFFOUT为0，则EN[i]＝1保持不变；0≤i≤7；
若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×<64×FOSC时，数字模块在PDIN的指定下降沿处检测BUFFOUT的值，若BUFFOUT为1，则EN[i]＝1保持不变，若BUFFOUT为0，则将EN[i]置0，同时将EN[i-1]置1，如果i＝0，则将EN[0]置0，EN[7]置1；
若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×＝64×FOSC时，则在启动高 频晶体振荡器的过程中，一直保持EN[i]＝1不变。
进一步的，所述多路选择器根据方波信号F64×频率的大小以及控制信号EN[7:0]，在信号Phase[7:0]中选择一个信号并记为信号PDIN具体为：
若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×>64×FOSC时，多路选择器在信号Phase[7:0]中选择第i+1个信号Phase[i+1]作为信号PDIN，如果i＝7，多路选择器选择信号Phase[0]作为信号PDIN；0≤i≤7；
若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×＜64×FOSC时，多路选择器选择信号Phase[i-1]作为信号PDIN；如果i＝0，多路选择器选择信号Phase[7]作为信号PDIN。
进一步的，所述数字模块还接受注入信号PhaseSEL，在启动高频晶体振荡器时，开关控制信号ENINJ为1，并对PhaseSEL信号的下降沿进行计数，当计数值到达预设的次数，则数字模块将ENINJ置0。
有益效果：本发明采用单端注入，能够实时检测注入情况，能够避免注入的盲目性，保证持续高效的能量注入与较大的振幅；同时，结合目前注入技术对于注入源频率精度的要求，本发明提供了相位误差自动校正技术，即使对于较大的频率误差，也能通过自动校正相位误差的技术，使相位误差始终保持在45°以内，延长有效注入时间并保证高效的能量注入，大幅降低了产生能量注入信号的信号源频率精度要求，打破了以往注入信号源频率精度对于高频晶体启动时间的严格限制，从而降低了高频晶体振荡器电路片上注入信号源设计和校准的精度要求，显著地提升了芯片良率。
附图说明
图1为本发明的整体电路图；
图2为本发明扭环形计数器电路图；
图3为本发明峰值检测器电路图；
图4为本发明高频晶体振荡器频率为24MHz且环形振荡器频率为1.54368GHz(>64×24MHz)时，环形振荡器、8分频电路和扭环形计数器的仿真波形图；
图5为本发明高频晶体振荡器频率为24MHz且环形振荡器频率为1.54368GHz(>64×24MHz)时，数字模块检测相位误差的工作时序仿真波形图；
图6为本发明高频晶体振荡器频率为24MHz且环形振荡器频率为1.54368GHz(>64×24MHz)时，数字模块按预设逻辑不断变更注入信号相位控制字的仿真波形图；
图7为本发明高频晶体振荡器频率为24MHz且环形振荡器频率为1.54368GHz(>64× 24MHz)时，高频晶体两端与放大器两端的仿真波形图；
图8为本发明高频晶体振荡器频率为24MHz且环形振荡器频率为1.52832GHz(＜64×24MHz)时，环形振荡器、8分频电路和扭环形计数器的仿真波形图；
图9为本发明高频晶体振荡器频率为24MHz且环形振荡器频率为1.52832GHz(＜64×24MHz)时，数字模块检测相位误差的工作时序仿真波形图；
图10为本发明高频晶体振荡器频率为24MHz且环形振荡器频率为1.52832GHz(＜64×24MHz)时，数字模块按预设逻辑不断变更注入信号相位控制字的仿真波形图；
图11为本发明高频晶体振荡器频率为24MHz且环形振荡器频率为1.52832GHz(＜64×24MHz)时，高频晶体两端与放大器两端的仿真波形图。
具体实施方式
构成本发明的一部分的附图用来提供对本发明的进一步理解，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。
如图1所示，本实施例提供一种基于相位误差自动校正的高频晶体振荡器，包括高频晶体、负载电容CL1和CL2、环形振荡器RO、8分频电路、扭环形计数器、峰值检测器、缓冲器Buffer、数字模块、多路选择器MUX和放大器；所述高频晶体为二端元件，用于精确产生频率为FOSC的高频振荡信号，其左端为XOIN用于注入能量，其右端为XOOUT用于检测相位；所述负载电容CL1和CL2均为二端元件，用于校准高频晶体的振荡频率，CL1下极板接地，CL1上极板与放大器输入端AMPIN相连，CL2下极板接地，CL2上极板与放大器输出端AMPOUT相连；所述单刀双掷开关SW1和SW2用于切换能量注入和维持振荡两种模式，SW1的不动端与高频晶体XOIN端相连，SW1上动端与多路选择器MUX其中一个输出端相连，SW1下动端与CL1上极板和放大器输入端AMPIN相连，SW2的不动端与高频晶体晶体XOOUT端相连，SW2上动端与峰值检测器输入端相连，SW2下动端与CL2上极板和放大器输出端AMPOUT相连；所述环形振荡器RO用于产生频率约为64×FOSC的方波信号F64×，其输出端与8分频电路的输入端和峰值检测器的一个输入端相连；所述8分频电路用于对输入信号F64×进行分频(本实施例中8分频电路由3个2分频电路级联得到)，8分频电路的输出端输出一个分频信号F8×，8分频电路的输出端与扭环形计数器输入端相连；所述扭环形计数器用于对输入信号再次进行分频，并且输出8个频率相同相位不同的信号Phase[7:0]，扭环形计数器输出端输出的信号Phase[7:0]与多路选择器MUX的8个输入端相应相连，成为MUX的待选信号；所述峰值检测器用于检测输入信号的峰值，峰值检测器的输入信号为高频晶体XOOUT输出信号PKDIN和RO输出的信号F64×，峰值检测器检测的是信号PKDIN的 峰值，所述峰值检测器以方波信号F64×作为高频工作时钟，通过输出脉冲信号PKDOUT反映信号PKDIN的峰值位置，并将脉冲信号PKDOUT传送至缓冲器中；所述缓冲器Buffer用于扩展信号PKDOUT的负脉宽，便于数字模块处理，缓冲器Buffer得到扩展后的脉冲信号BUFFOUT，并将BUFFOUT传送至数字模块；所述数字模块用于鉴别注入信号与振荡信号之间的相位误差并控制高频晶体的注入时序，数字模块的输入信号为缓冲器Buffer的输出信号BUFFOUT、多路选择器MUX的输出信号PDIN，PhaseSEL和从外部输入的注入次数控制字C[9:0]，数字模块的一个输出端输出开关控制信号ENINJ，开关控制信号ENINJ与单刀双掷开关SW1和SW2的控制端相连，另外一个输出端输出多比特控制字(也即控制信号)EN[7:0]，该多比特控制字EN[7:0]与多路选择器MUX电路的一个输入端相连；所述多路选择器根据方波信号F64×频率的大小以及控制信号EN[7:0]，在信号Phase[7:0]中选择一个信号并记为信号PDIN输入至数字模块，参与控制数字模块的输出信号EN[7:0]；多路选择器还根据控制信号EN[7:0]在信号Phase[7:0]中选择一个信号作为注入信号通过第一单刀双掷开关注入至高频晶体振荡器的XOIN端，用于启动高频晶体。所述放大器用于维持晶体快速启动后的稳定振荡，输入端与、CL1的上极板和SW1的下动端相连，输出端与CL2的上极板和SW2的下动端相连。
如图2所示，所述扭环形计数器包括4个D触发器DFF1～DFF4；每个D触发器均具有数据输入端D，时钟控制端C，第一输出端Q和第二输出端Qn，所述第二输出端输出的信号为第一输出端输出信号的反相信号；第一～四触发器的时钟控制端均连接信号F8×。
所述第一D触发器DFF1的数据输入端D1与第四D触发器DFF4的第一输出端Q4相连，时钟控制端C1与8分频电路输出信号F8×相连，第一输出端Q1与第二D触发器DFF2的数据输入端D2相连并且作为输出信号Phase[0]，第一D触发器的第二输出端Qn1作为输出信号Phase[4]；所述第二D触发器DFF2的数据输入端D2与第一D触发器DFF1的第一输出端Q1相连，时钟控制端C2与8分频电路输出信号F8×相连，第一输出端Q2与第三D触发器DFF3的数据输入端D3相连并且作为输出信号Phase[1]，第二输出端Qn2作为输出信号Phase[5]；所述第三D触发器DFF3的数据输入端D3与第二D触发器DFF2的第一输出端Q2相连，时钟控制端C3与8分频电路输出信号F8×相连，第一输出端Q3与第四D触发器DFF4的数据输入端D4相连并且作为输出信号Phase[2]，第二输出端Qn3作为输出信号Phase[6]；所述第四D触发器DFF4的数据输入端D4与第三D触发器DFF3的第一输出端Q3相连，时钟控制端C4与8分频电路输出信号F8×相连，第一输出端Q4与第一D触发器DFF1的数据输入端D1相连并且作为输出信号Phase[3]，第二输出端Qn4作为输出信号 Phase[7]；4个D触发器完成对输入信号F8×的8分频，同时产生8路同频异相信号Phase[7:0]，频率约为FOSC，信号Phase[j]的相位超前信号Phase[j+1]的相位45°，j＝0,1,2,…6。
如图3所示，所述峰值检测器包括动态比较器DCMP、电容CPKD、PMOS管M1、NMOS管M2和电流源Iref。
所述动态比较器的输入端A(反相输入端)即为峰值检测器的输入端，动态比较器的输入端B(同相输入端)与NMOS管M2的漏极、电容CPKD的上极板、PMOS管M1的漏极相连，RO输出信号F64×作为动态比较器的时钟输入信号，动态比较器的输出端与PMOS管M1的栅极相连并且作为峰值检测器的输出端；所述电容CPKD的下极板接地，上极板与动态比较器的输入端B、NMOS管M2的漏极、PMOS管M1的漏极相连；所述PMOS管M1的栅极与动态比较器DCMP的输出端相连，漏极与电容CPKD的上极板、动态比较器的输入端B以及NMOS管M2的漏极相连，源极与电流源Iref的下端相连；所述NMOS管M2的栅极连接复位信号RST，漏极与电容CPKD的上极板、动态比较器的输入端B以及PMOS管M1的漏极相连，源极接地；所述电流源Iref的上端连接电源电压VDD，下端连接PMOS管M1的源极。所述峰值检测器检测输入信号PKDIN的峰值大小，此外，由于高频工作时钟F64×，峰值检测器能够以脉冲信号PKDOUT精准反映峰值位置。
按照功耗与检测精度等方面的考量，峰值检测器工作频率可变，可根据具体需求，将峰值检测器设置为每1或2或4个周期对峰值进行一次检测。
所述多路选择器MUX的待选信号Phase[7:0]由扭环形计数器提供，控制信号EN[7:0]由数字模块提供；控制信号EN[7:0]与待选信号Phase[7:0]一一对应，即EN[i](0≤i≤7)控制Phase[i](0≤i≤7)信号的通断，当EN[i]＝1(0≤i≤7)，多路选择器选择Phase[i]作为注入信号PhaseSEL。
多路选择器的另一输出端PDIN不仅取决于控制信号EN[7:0]，还取决于RO输出频率F64×的大小，F64×约为晶体振荡频率FOSC的64倍，但两者并不精确相等；信号PDIN的输出规则如下：
本实施例中在初始时刻给定数字模块输出一个初始的控制信号EN[7:0]为：10000000，也即EN[0]＝1，其余的为0。
若当前时刻EN[i]＝1(0≤i≤6)且F64×>64×FOSC时，多路选择器选择Phase[i+1]作为输出PDIN，特殊的；当EN[7]＝1且F64×>64×FOSC时，多路选择器选择Phase[0]作为输出PDIN。若当前时刻EN[i]＝1(1≤i≤7)且F64×＜64×FOSC时，多路选择器选择Phase[i-1]作 为输出PDIN；特殊的，当EN[0]＝1且F64×＜64×FOSC时，多路选择器选择Phase[7]作为输出PDIN；需要注意的是，本实施例中EN[7:0]同一时刻最多只有一位控制字置1，其余均为0。
所述数字模块判别输入信号BUFFOUT和PDIN之间的边沿关系；由于BUFFOUT是对XOOUT输出信号PKDIN的波形进行峰值检测所得，反映了PKDIN，即晶体振荡信号的相位信息，PDIN是与注入信号PhaseSEL相差45°的信号，间接包含了注入信号PhaseSEL的相位信息，数字模块可以通过判别输入信号BUFFOUT和PDIN之间的边沿关系来鉴别注入信号PhaseSEL与振荡信号PKDIN之间的相位误差；当数字模块检测到注入信号PhaseSEL与振荡信号PKDIN之间的相位差达到45°时，数字模块变动EN[7:0]取值，按照预设的逻辑从Phase[7:0]中选出信号赋值给注入信号PhaseSEL和输出信号PDIN，相位误差判别方法与EN[7:0]取值变动逻辑如下：
相位误差检测与注入信号切换：
当EN[i]＝1(0≤i≤6)且F64×>64×FOSC时，数字模块在PDIN的指定上升沿处检测BUFFOUT的值，当检测到BUFFOUT为0，则EN[i]＝1保持不变，当检测到BUFFOUT为1，则将EN[i]置0，同时将EN[i+1]置1；特殊的，当EN[7]＝1且F64×>64×FOSC时，数字模块在PDIN的指定上升沿处检测BUFFOUT的值，当检测到BUFFOUT为0，则EN[7]＝1保持不变，当检测到BUFFOUT为1，则将EN[7]置0，同时将EN[0]置1。
当EN[i]＝1(1≤i≤7)且F64×<64×FOSC时，数字模块在PDIN的指定下降沿处检测BUFFOUT的值，当检测到BUFFOUT为1，则EN[i]＝1保持不变，当检测到BUFFOUT为0，则将EN[i]置0，同时将EN[i-1]置1；特殊的，当EN[0]＝1且F64×<64×FOSC时，数字模块在PDIN的下降沿处检测BUFFOUT的值，当检测到BUFFOUT为1，则EN[0]＝1保持不变，当检测到BUFFOUT为0，则将EN[0]置0，同时将EN[7]置1。
当EN[i]＝1(0≤i≤7)且F64×＝64×FOSC时，注入信号与振荡信号之间相位误差极小，无需切换注入信号PhaseSEL的相位，EN[i]＝1一直保持不变，直至注入行为结束。
注入与的切换：
数字模块不断切换PhaseSEL信号的相位对晶体的XOIN端进行注入的过程中，数字模块将ENINJ置1，控制SW1和SW2，将PhaseSEL与XOIN相连，将PKDIN与XOOUT相连，这一过程称为注入阶段，是启动高频晶体的过程；注入完成后，晶体振荡器转入维持阶段，数字模块将ENINJ置0(如图1所示，数字模块的输入信号C[9:0]用来预设注入次数，数字模块对PhaseSEL信号的下降沿进行计数，当计数值达到C[9:0]预设次数，数字模块将ENINJ置0，结束注入行为)，控制SW1和SW2，将AMPIN与XOIN相连，将AMPOUT与XOOUT相连；在维 持阶段，电容CL1和CL2的电容大小可自行调整，起到稳定晶体振荡频率、优化相位噪声和抖动性能的作用；放大器起到维持晶体振荡信号的作用，使晶体在断开能量注入后，振荡信号不会衰减消失，提供稳定的振荡信号。
本实施例的一种基于相位误差自动校正技术的快速启动高频晶体振荡器，高频晶体频率为24MHz且环形振荡器频率为1.54368GHz(>64×24MHz)，仿真波形图如图4、5、6、7所示。
如图4所示，环形振荡器输出方波信号F64×频率为1.54368GHz，8分频电路对F64×进行8分频，得到F8×信号，扭环形计数器对F8×信号进一步分频，同时产生8路同频异相信号Phase[7:0]，频率约为FOSC，Phase[j]超前Phase[j+1]45°(i≥0)。
如图5所示，PKDIN为峰值检测器的输入信号，峰值检测器每4个周期对峰值进行一次检测，得到反映峰值是否增长的输出信号PKDOUT。如图5所示，以EN[3]＝1、EN[4]＝0向EN[3]＝0、EN[4]＝1变更控制字为例，首先，EN[3]＝1，选定Phase[3]为注入信号赋值给PhaseSEL；与此同时，峰值检测器监测峰值增长情况，当PKDOUT和BUFFOUT的负脉宽缺失，表明峰值不再增长，继续以Phase[3]进行注入，效率会降低甚至出现抑制晶体能量增长的情况，需要切换注入信号PhaseSEL的相位；接着，数字模块在PDIN的指定下降沿处检测到BUFFOUT为1，即负脉宽缺失，则数字模块将EN[3]置0，将EN[4]置1，选定Phase[4]为注入信号赋值给PhaseSEL，继续进行能量注入。
如图6所示，用于控制注入信号PhaseSEL相位的EN[7:0]不断跳变，保证晶体持续高效的能量注入，直至注入结束，控制信号ENINJ从1变0，将高频晶体接入放大器维持稳态振荡；如图7所示，能量注入过程的前期采用单端注入，XOIN用于方波注入，XOOUT用于检测相位误差；能量注入过程的最后一次注入采用双端注入，XOIN与XOOUT均为方波，目的是进一步提高能量注入效率。注入结束后，控制信号ENINJ从1变0，将晶体接入放大器，放大器输入AMPIN与输出AMPOUT出现波形。
高频晶体频率为24MHz且环形振荡器频率为1.52832GHz(<64×24MHz)时，仿真波形图如图8、9、10、11所示。
如图8所示，环形振荡器输出方波信号F64×频率为1.52832GHz，8分频电路对F64×进行8分频，得到F8×信号，扭环形计数器对F8×信号进一步分频，同时产生8路同频异相信号Phase[7:0]，频率约为FOSC，Phase[i]超前Phase[i+1]45°。
如图9所示，PKDIN为峰值检测器的输入信号，峰值检测器每2个周期对峰值进行一次检测，得到反映峰值是否增长的输出信号PKDOUT。如图9所示，以EN[5]＝1、EN[4]＝0 向EN[5]＝0、EN[4]＝1变更控制字为例，首先，EN[5]＝1，选定Phase[5]为注入信号赋值给PhaseSEL；与此同时，峰值检测器监测峰值情况，当PDIN在指定下降沿处采集BUFFOUT值为0，表明相位误差累积达到45°，继续以Phase[5]进行注入，效率会降低甚至出现抑制晶体能量增长的情况，需要切换注入信号PhaseSEL的相位，则数字模块将EN[5]置0，将EN[4]置1，选定Phase[4]为注入信号赋值给PhaseSEL，继续进行能量注入。
如图10所示，用于控制注入信号PhaseSEL相位的EN[7:0]不断跳变，保证晶体持续高效的能量注入，直至注入结束，控制信号ENINJ从1变0，将晶体接入放大器维持稳态振荡；如图11所示，能量注入过程的前期采用单端注入，XOIN用于方波注入，XOOUT用于检测相位误差；能量注入过程的最后一次注入采用双端注入，XOIN与XOOUT均为方波，目的是进一步提高能量注入效率。注入结束后，控制信号ENINJ从1变0，将晶体接入放大器，放大器输入AMPIN与输出AMPOUT出现波形。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合。为了避免不必要的重复，本发明对各种可能的组合方式不再另行说明。

Claims (7)

  1. 一种基于相位误差自动校正的高频晶体振荡器，其特征在于，包括高频晶体、第一、第二负载电容、环形振荡器、8分频电路、扭环形计数器、峰值检测器、缓冲器、数字模块、多路选择器、放大器以及第一、第二单刀双掷开关；将高频晶体一端记为XOIN，另一端记为XOOUT；所述第一单刀双掷开关的不动端与高频晶体XOIN端连接，第一单刀双掷开关的第一动端连接多路选择器，第二动端连接第一电容的一端和放大器的输入端；所述第二单刀双掷开关的不动端与高频晶体的XOOUT端连接，第二单刀双掷开关的第一动端连接峰值检测器，第二动端连接第二电容的一端和放大器的输出端，第一、第二电容的另外一端均接地；
    在启动高频晶体振荡器时，采用数字模块产生开关控制信号ENINJ，控制第一单刀双掷开关的不动端连接第一单刀双掷开关的第一动端，控制第二单刀双掷开关的不动端连接第二单刀双掷开关的第一动端；同时所述环形振荡器产生方波信号F64×，并将该方波信号传送至8分频电路和峰值检测器；所述8分频电路对方波信号进行分频，产生一个分频信号F8×，并将F8×传送至扭环形计数器，所述扭环形计数器对F8×进行再分频，产生8个频率相同相位不同的信号Phase[7:0]，并将信号Phase[7:0]传送至多路选择器中；所述峰值检测器还接受高频晶体XOOUT端输出的信号PKDIN，所述峰值检测器以方波信号F64×作为高频工作时钟，通过输出脉冲信号PKDOUT反映信号PKDIN的峰值位置，并将脉冲信号PKDOUT传送至缓冲器中，所述缓冲器扩展脉冲信号PKDOUT的负脉宽，得到扩展后的脉冲信号BUFFOUT，并将BUFFOUT传送至数字模块；所述数字模块产生初始的控制信号EN[7:0]，该控制信号为8位控制信号，所述数字模块通过判别信号PDIN和信号BUFFOUT之间的边沿关系，对控制信号EN[7:0]进行切换，并将切换后的控制信号EN[7:0]传送至多路选择器；所述多路选择器根据方波信号F64×频率的大小以及控制信号EN[7:0]，在信号Phase[7:0]中选择一个信号并记为信号PDIN输入至数字模块；多路选择器还根据控制信号EN[7:0]在信号Phase[7:0]中选择一个信号作为注入信号通过第一单刀双掷开关注入至高频晶体的XOIN端，该注入信号通过高频晶体耦合到XOOUT端，并与高频晶体产生的高频振荡信号FOSC在XOOUT端叠加后得到信号PKDIN，信号PKDIN通过第二单刀双掷开关输入至峰值检测器；
    在维持阶段，控制信号ENINJ控制第一单刀双掷开关的不动端与第一单刀双掷开关的第二动端连接，控制第二单刀双掷开关的不动端与第二单刀双掷开关的第二动端连接。
  2. 根据权利要求1所述的一种基于相位误差自动校正的高频晶体振荡器，其特征在于，所述扭环形计数器包括第一～四触发器；第一～四触发器均为D触发器，均具有数据输入端，时钟控制端，第一输出端和第二输出端，所述第二输出端输出的信号为第一输出端输出信号 的反相信号；所述第一～四触发器的时钟控制端均连接信号F8×；
    第一触发器的数据输入端连接第四触发器的第一输出端，第一触发器第一输出端输出的信号作为Phase[7:0]中的第一位信号记为Phase[0]，并连接第二触发器的数据输入端；第二触发器第一输出端输出的信号作为Phase[7:0]中的第二位信号记为Phase[1]，并连接第三触发器的数据输入端；第三触发器的第一输出端输出的信号作为Phase[7:0]中的第三位信号记为Phase[2]，并与第四触发器的数据输入端连接；第四触发器的第一输出端输出的信号作为Phase[7:0]中的第四位信号记为Phase[3]；第一～四触发器的第二输出端输出的信号依次作为Phase[7:0]中的第五、第六、第七以及第八位信号，依次记为Phase[4]、Phase[5]、Phase[6]、Phase[7]；信号Phase[j]的相位超前信号Phase[j+1]的相位45°，j＝0,1,2,…6。
  3. 根据权利要求1所述的一种基于相位误差自动校正的高频晶体振荡器，其特征在于，所述峰值检测器包括动态比较器、第三电容、PMOS管、NMOS管和电流源；所述动态比较器的反相输入端作为峰值检测器的输入端连接信号PKDIN；动态比较器的同相输入端与NMOS管的漏极以及第三电容的一端连接；所述NMOS管的源极和第三电容另外一端均接地；动态比较器的输出端作为峰值检测器的输出端与PMOS管的栅极连接，所述PMOS管的源极通过电流源与电源电压VDD连接，PMOS管的漏极连接第三电容的一端；所述动态比较器的时钟输入信号为信号F64×。
  4. 根据权利要求1所述的一种基于相位误差自动校正的高频晶体振荡器，其特征在于，所述多路选择器根据控制信号EN[7:0]在信号Phase[7:0]中选择一个信号作为注入信号具体为：当信号EN[7:0]中第i位信号EN[i]为1时，则在信号Phase[7:0]中选择第i个信号Phase[i]作为注入信号，0≤i≤7。
  5. 根据权利要求1所述的一种基于相位误差自动校正的高频晶体振荡器，其特征在于，所述数字模块还通过判别信号PDIN和信号BUFFOUT之间的边沿关系，对8位控制信号EN[7:0]进行切换具体为：
    若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×>64×FOSC时，数字模块在PDIN的指定上升沿处检测信号BUFFOUT的值，若BUFFOUT为1，则将EN[i]置0，同时将EN[i+1]置1，如果i＝7时，则将EN[7]置0，同时将EN[0]置1；若BUFFOUT为0，则EN[i]＝1保持不变；0≤i≤7；
    若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×<64×FOSC时，数字模块在PDIN的指定下降沿处检测BUFFOUT的值，若BUFFOUT为1，则EN[i]＝1保持不变，若BUFFOUT为0，则将EN[i]置0，同时将EN[i-1]置1，如果i＝0，则将EN[0]置0，EN[7]置 1；
    若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×＝64×FOSC时，则在启动高频晶体振荡器的过程中，一直保持EN[i]＝1不变。
  6. 根据权利要求1所述的一种基于相位误差自动校正的高频晶体振荡器，其特征在于，所述多路选择器根据方波信号F64×频率的大小以及控制信号EN[7:0]，在信号Phase[7:0]中选择一个信号并记为信号PDIN具体为：
    若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×>64×FOSC时，多路选择器在信号Phase[7:0]中选择第i+1个信号Phase[i+1]作为信号PDIN，如果i＝7，多路选择器选择信号Phase[0]作为信号PDIN；0≤i≤7；
    若当前时刻控制信号EN[7:0]中第i个控制信号EN[i]＝1，且F64×＜64×FOSC时，多路选择器选择信号Phase[i-1]作为信号PDIN；如果i＝0，多路选择器选择信号Phase[7]作为信号PDIN。
  7. 根据权利要求1所述的一种基于相位误差自动校正的高频晶体振荡器，其特征在于，所述数字模块还接受注入信号PhaseSEL，在启动高频晶体振荡器时，开关控制信号ENINJ为1，并对PhaseSEL信号的下降沿进行计数，当计数值到达预设的次数，则数字模块将ENINJ置0。
PCT/CN2023/083227 2022-11-14 2023-03-23 一种基于相位误差自动校正的高频晶体振荡器 WO2024103589A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211419950.9 2022-11-14
CN202211419950.9A CN115498998B (zh) 2022-11-14 2022-11-14 一种基于相位误差自动校正的高频晶体振荡器

Publications (1)

Publication Number Publication Date
WO2024103589A1 true WO2024103589A1 (zh) 2024-05-23

Family

ID=85115669

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/083227 WO2024103589A1 (zh) 2022-11-14 2023-03-23 一种基于相位误差自动校正的高频晶体振荡器

Country Status (2)

Country Link
CN (1) CN115498998B (zh)
WO (1) WO2024103589A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115498998B (zh) * 2022-11-14 2023-02-21 南京邮电大学 一种基于相位误差自动校正的高频晶体振荡器
CN115800927B (zh) * 2023-01-31 2023-04-25 南京邮电大学 一种基于占空比检测的晶体振荡器
CN116614114B (zh) * 2023-04-13 2023-12-19 浙江力积存储科技有限公司 延迟锁相环路时钟信号占空比检测方法、占空比检测器
CN117478130B (zh) * 2023-12-28 2024-04-02 南京美辰微电子有限公司 一种时间交织adc的多相采样时钟产生电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646562A (en) * 1993-07-21 1997-07-08 Seiko Epson Corporation Phase synchronization circuit, one-shot pulse generating circuit and signal processing system
CN102158208A (zh) * 2011-04-02 2011-08-17 东南大学 基于振荡环电路的全程可调数字脉宽调制器
CN112217476A (zh) * 2020-09-08 2021-01-12 南京低功耗芯片技术研究院有限公司 一种自激注入晶体振荡器
CN114584133A (zh) * 2020-11-30 2022-06-03 恩智浦有限公司 晶体振荡器启动电路和方法
CN115498998A (zh) * 2022-11-14 2022-12-20 南京邮电大学 一种基于相位误差自动校正的高频晶体振荡器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2837105B2 (ja) * 1994-01-05 1998-12-14 三星電子株式会社 テレビ信号中に埋め込まれたディジタル信号に対するシグマ−デルタ・アナログ−ディジタル変換機能を備えた受信器
CN100349378C (zh) * 2002-04-19 2007-11-14 陈为怀 网同步可集成从时钟锁相环
CN1729615A (zh) * 2002-12-19 2006-02-01 皇家飞利浦电子股份有限公司 具有振幅、共模和相位校正的混频器系统
GB2430090B (en) * 2005-09-08 2007-10-17 Motorola Inc RF synthesizer and RF transmitter or receiver incorporating the synthesizer
TW200844704A (en) * 2007-01-02 2008-11-16 Exar Corp Apparatus and method for controlling the propagation delay of a circuit by controlling the voltage applied to the circuit
US9974038B2 (en) * 2016-06-30 2018-05-15 Macom Technology Solutions Holdings, Inc. Circuits and operating methods thereof for correcting phase errors caused by gallium nitride devices
CN109547052B (zh) * 2018-12-05 2020-07-07 北京理工大学 一种用于通信和测距的超宽带调频复合型收发机
CN111082831B (zh) * 2019-12-30 2021-03-26 中国科学院电子学研究所 一种星载同步收发装置及信号处理方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646562A (en) * 1993-07-21 1997-07-08 Seiko Epson Corporation Phase synchronization circuit, one-shot pulse generating circuit and signal processing system
CN102158208A (zh) * 2011-04-02 2011-08-17 东南大学 基于振荡环电路的全程可调数字脉宽调制器
CN112217476A (zh) * 2020-09-08 2021-01-12 南京低功耗芯片技术研究院有限公司 一种自激注入晶体振荡器
CN114584133A (zh) * 2020-11-30 2022-06-03 恩智浦有限公司 晶体振荡器启动电路和方法
CN115498998A (zh) * 2022-11-14 2022-12-20 南京邮电大学 一种基于相位误差自动校正的高频晶体振荡器

Also Published As

Publication number Publication date
CN115498998A (zh) 2022-12-20
CN115498998B (zh) 2023-02-21

Similar Documents

Publication Publication Date Title
WO2024103589A1 (zh) 一种基于相位误差自动校正的高频晶体振荡器
US9170564B2 (en) Time-to-digital converter and PLL circuit using the same
KR101456966B1 (ko) 비-중첩 클록 발생을 위한 방법 및 장치
US8138843B2 (en) Gated ring oscillator for a time-to-digital converter with shaped quantization noise
US6392456B1 (en) Analog mixed digital DLL
JP4357538B2 (ja) 半導体集積回路装置
JP4446070B2 (ja) Ｄｌｌ回路、それを使用する半導体装置及び遅延制御方法
US6366150B1 (en) Digital delay line
Wang et al. An all-digital 50% duty-cycle corrector
CN108063618B (zh) 一种vco自动校准电路和方法
CN110635803A (zh) 一种基于电平宽度提取的锁相加速电路及锁相环系统
CN114244353B (zh) 一种基于二次注入及锁相环技术的快速启动晶体振荡器
TW202333456A (zh) 自適應時鐘工作週期控制器
CN114244354B (zh) 一种基于二次注入及数字锁频环的快速启动晶体振荡器
CN117940854A (zh) 自适应时钟占空比控制器
EP3262759B1 (en) Power-up system comprising a voltage comparator
JP4000215B2 (ja) 充放電電流発生回路、チャージポンプ回路、ｐｌｌ回路およびパルス幅変調回路
CN114944833B (zh) 弛豫振荡器、时钟电路及电子芯片
CN115276615B (zh) 一种输出无毛刺的低占空比误差的时钟信号倍频电路
JP2008060895A (ja) 位相同期回路
JP2001264397A (ja) 遅延時間測定装置、遅延時間測定方法および半導体集積回路
CN111722520B (zh) 一种时间数字转换器、相位差的检测方法
US20240137197A1 (en) Push-start crystal oscillator, associated electronic device and push-start method for performing start-up procedure of crystal oscillator
US20240235803A9 (en) Push-start crystal oscillator, associated electronic device and push-start method for performing start-up procedure of crystal oscillator
US20210286400A1 (en) Semiconductor circuit apparatus and system equipped with semiconductor circuit apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23890035

Country of ref document: EP

Kind code of ref document: A1