WO2024101130A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024101130A1
WO2024101130A1 PCT/JP2023/038174 JP2023038174W WO2024101130A1 WO 2024101130 A1 WO2024101130 A1 WO 2024101130A1 JP 2023038174 W JP2023038174 W JP 2023038174W WO 2024101130 A1 WO2024101130 A1 WO 2024101130A1
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WIPO (PCT)
Prior art keywords
gate
electrode
pad
region
resistor
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Ceased
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PCT/JP2023/038174
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
弘章 白神
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024557289A priority Critical patent/JPWO2024101130A1/ja
Publication of WO2024101130A1 publication Critical patent/WO2024101130A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Definitions

  • Patent document 1 discloses a semiconductor device including a semiconductor substrate, a MOS gate, a p-type region, an interlayer insulating film, a gate polysilicon layer, a gate pad, and a contact electrode.
  • the MOS gate includes a plurality of gate electrodes embedded in a plurality of trenches formed in the semiconductor substrate.
  • the p-type region is formed in the surface layer of the semiconductor substrate at a distance from the MOS gate.
  • the interlayer insulating film covers the MOS gate and the p-type region on the semiconductor substrate.
  • the gate polysilicon layer is provided as a gate resistor.
  • the gate polysilicon layer is disposed on a portion of the interlayer insulating film that covers the p-type region, at a distance from the MOS gate, and faces the p-type region across the interlayer insulating film.
  • the gate pad is disposed on the gate polysilicon layer and is electrically connected to the gate polysilicon layer.
  • the contact electrode is disposed on the gate polysilicon layer at a distance from the gate pad, and is electrically connected to the gate polysilicon layer.
  • the present disclosure provides a semiconductor device having a novel layout associated with a resistor.
  • the present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface and having a resistor portion; a pad electrode arranged on the main surface so as to overlap the resistor portion and having a first electrical connection portion to the resistor portion; and a wiring electrode arranged on the main surface so as to overlap the resistor portion at a position different from the pad electrode, having a second electrical connection portion to the resistor portion, and electrically connected to the pad electrode via the resistor portion.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type first gate structure formed on the main surface and having a resistor portion, a trench electrode type second gate structure formed on the main surface at a distance from the first gate structure and not having the resistor portion, and a pad electrode disposed on the main surface so as to overlap the resistor portion of the first gate structure and the second gate structure, having an electrical connection portion to the resistor portion and not having an electrical connection portion to the second gate structure.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type first gate structure formed on the main surface and having a resistor portion, a trench electrode type second gate structure formed on the main surface at a distance from the first gate structure and not having the resistor portion, and a pad electrode arranged on the main surface so as to overlap the resistor portion of the first gate structure and not overlap the second gate structure, having an electrical connection portion to the resistor portion and not having an electrical connection portion to the second gate structure.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a first gate structure of a trench electrode type formed on the main surface and having a resistor portion, a second gate structure of a trench electrode type formed on the main surface at a distance from the first gate structure and not having the resistor portion, a third gate structure of a trench electrode type formed on the main surface at a distance from the first gate structure and the second gate structure and not having the resistor portion, and a pad electrode arranged on the main surface overlapping the resistor portion of the first gate structure and the second gate structure but not overlapping the third gate structure, having an electrical connection portion to the resistor portion, and not having an electrical connection portion to the second gate structure and the third gate structure.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a mesa portion defined on the main surface by a first surface portion located inside the main surface, a second surface portion recessed in the thickness direction outside the first surface portion, and a connection surface portion connecting the first surface portion and the second surface portion, and a trench electrode type gate structure having a resistor portion formed on the first surface portion.
  • the present disclosure provides a semiconductor device including: a chip having a main surface; a plurality of trench electrode type gate structures formed on the main surface; an interlayer film covering the plurality of gate structures on the main surface; a pad electrode disposed on the interlayer film so as to overlap at least one of the gate structures and electrically connected to at least one of the gate structures through the interlayer film; and a wiring electrode disposed on the interlayer film at a distance from the pad electrode, electrically connected to at least one of the gate structures through the interlayer film, and electrically connected to the pad electrode via a portion of at least one of the gate structures.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type gate structure having a resistor formed on the main surface, and a trench electrode type source structure formed on the main surface adjacent to the gate structure.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type gate structure formed in a strip shape extending in a first direction on the main surface and having a resistor, and a trench electrode type electrode structure formed on the main surface at a distance from the gate structure in the first direction and to which a potential different from that of the gate structure is applied.
  • the present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface and having a resistor portion; a trench electrode type first electrode structure formed on the main surface at a distance from the gate structure in one direction and to which a potential different from that of the gate structure is applied; and a trench electrode type second electrode structure formed on the main surface at a distance from the gate structure in an orthogonal direction perpendicular to the one direction and to which a potential different from that of the gate structure is applied.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type gate structure formed on the main surface and partially including a resistor portion, a pad electrode arranged on the main surface so as to overlap the resistor portion and having an electrical connection portion to the resistor portion, and a pad insulating film covering the connection portion of the pad electrode and having a pad opening that exposes an area of the pad electrode outside the connection portion.
  • the present disclosure provides a semiconductor device including a gate pad, a gate wiring physically separated from the gate pad, and a gate resistor having a parallel resistance circuit including a plurality of resistance elements and electrically interposed between the gate pad and the gate wiring.
  • FIG. 1 is a plan view showing a semiconductor device according to a specific embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing an example of the layout of the first main surface.
  • FIG. 4 is an enlarged plan view showing an example of the layout of active regions.
  • FIG. 5 is an enlarged plan view showing an example of the layout of the first side end region.
  • FIG. 6 is an enlarged plan view showing an example layout of the first termination region.
  • FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG.
  • FIG. 8 is a cross-sectional view taken along the line VIII-VIII shown in FIG.
  • FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG.
  • FIG. 10 is a cross-sectional view taken along line X-X shown in FIG.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG.
  • FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG.
  • FIG. 13 is a cross-sectional view taken along the line XIII-XIII shown in FIG.
  • FIG. 14 is a cross-sectional view showing the structure of the outer periphery region.
  • FIG. 15 is a plan view showing the pad region.
  • FIG. 16 is a plan view showing an example of the layout of gate electrodes and source electrodes.
  • FIG. 17 is an enlarged plan view showing a main part of FIG. 16 together with a gate structure.
  • FIG. 18 is an enlarged plan view showing an example of the layout of the region XVIII shown in FIG.
  • FIG. 19 is an enlarged plan view showing a first gate structure according to the first layout example.
  • FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 19.
  • FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 19.
  • FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII shown in FIG. 19.
  • FIG. 24 is a circuit diagram showing the electrical configuration of the gate resistor.
  • FIG. 22 is a cross-sectional view taken along line X
  • FIG. 25 is an enlarged plan view showing a first gate structure according to the second layout example.
  • FIG. 26 is an enlarged plan view showing a first gate structure according to the third layout example.
  • FIG. 27 is a cross-sectional view showing another example of the chip.
  • FIG. 28 is a cross-sectional view showing another example of the chip.
  • this phrase includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the words “first,” “second,” “third,” etc. are used, but these are symbols attached to the names of each structure to clarify the order of explanation, and are not used with the intention of limiting the names of each structure.
  • the conductivity type of a semiconductor region is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1 according to a specific embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing an example layout of a first main surface 3.
  • the semiconductor device 1 is a semiconductor switching device including an insulated gate type transistor structure.
  • the transistor structure may be referred to as a MISFET structure (Metal Insulator Semiconductor Field Effect Transistor structure).
  • semiconductor device 1 includes chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape).
  • semiconductor device 1 is a "wide bandgap semiconductor device.”
  • Chip 2 may also be referred to as a “semiconductor chip,” a "wide bandgap semiconductor chip,” or the like.
  • a wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).
  • the chip 2 is a "SiC chip” that includes hexagonal SiC single crystal as an example of a wide band gap semiconductor.
  • the semiconductor device 1 is a "SiC semiconductor device.”
  • the semiconductor device 1 may also be referred to as a "SiC-MISFET.”
  • the hexagonal SiC single crystal has multiple polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like.
  • the chip 2 includes 4H-SiC single crystal, but the chip 2 may include other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").
  • the normal direction Z is also the thickness direction of the chip 2.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane.
  • the off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the off angle may be greater than 0° and less than or equal to 10°.
  • the off angle is preferably less than or equal to 5°.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, perpendicular to) the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y may be the a-axis direction of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the third side surface 5C side in the first direction X may be referred to as one side of the first direction X
  • the fourth side surface 5D side in the first direction X may be referred to as the other side of the first direction X
  • the first side surface 5A side in the second direction Y may be referred to as one side of the second direction Y
  • the second side surface 5B side in the second direction Y may be referred to as the other side of the second direction Y.
  • the chip 2 may have a thickness of 5 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the chip 2 may be set to a value belonging to any one of the following ranges: 5 ⁇ m or more and 25 ⁇ m or less, 25 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 75 ⁇ m or less, 75 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 125 ⁇ m or less, 125 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 175 ⁇ m or less, and 175 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the chip 2 is preferably 100 ⁇ m or less.
  • the first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in plan view.
  • the length of the first to fourth sides 5A to 5D may be set to a value that falls within any one of the following ranges: 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. It is preferable that the length of the first to fourth sides 5A to 5D is 5 mm or more.
  • the semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2.
  • a drain potential is applied to the first semiconductor region 6 as a high potential (first potential).
  • the first semiconductor region 6 may also be referred to as a "drain region", a “drift region”, etc.
  • the first semiconductor region 6 is formed in a layer extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).
  • the first semiconductor region 6 may have a thickness of 1 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the first semiconductor region 6 is preferably 3 ⁇ m or more and 30 ⁇ m or less. It is particularly preferable that the thickness of the first semiconductor region 6 is 5 ⁇ m or more and 25 ⁇ m or less.
  • the semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side in the chip 2.
  • a drain potential is applied to the second semiconductor region 7.
  • the second semiconductor region 7 may also be referred to as a "drain region.”
  • the second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 in the chip 2.
  • the second semiconductor region 7 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer.
  • the second semiconductor region 7 may have a thickness of 1 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the second semiconductor region 7 may be 150 ⁇ m or less, 100 ⁇ m or less, 50 ⁇ m or less, or 40 ⁇ m or less.
  • the thickness of the second semiconductor region 7 may be 5 ⁇ m or more.
  • the thickness of the second semiconductor region 7 is preferably 10 ⁇ m or more. In this embodiment, the thickness of the second semiconductor region 7 is greater than the thickness of the first semiconductor region 6.
  • the semiconductor device 1 includes an active surface 8 formed on the first main surface 3, an outer surface 9, and first to fourth connecting surfaces 10A to 10D.
  • the active surface 8, outer surface 9, and first to fourth connecting surfaces 10A to 10D define an active plateau 11 on the first main surface 3.
  • the active surface 8 may be referred to as the "first surface portion”
  • the outer peripheral surface 9 may be referred to as the "second surface portion”
  • the first to fourth connection surfaces 10A to 10D may be referred to as the "connection surface portion”
  • the active plateau 11 may be referred to as the “mesa portion”.
  • the active surface 8, the outer peripheral surface 9, and the first to fourth connection surfaces 10A to 10D may be considered to be components of the chip 2 (first main surface 3).
  • the active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the active surface 8 has a flat surface extending in the first direction X and the second direction Y.
  • the active surface 8 is formed by a c-plane (Si-plane).
  • the active surface 8 is formed in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the outer peripheral surface 9 is located outside the active surface 8 and is recessed in the thickness direction of the chip 2 (towards the second main surface 4) relative to the active surface 8. Specifically, the outer peripheral surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6.
  • the outer peripheral surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically a square ring shape) surrounding the active surface 8.
  • the outer peripheral surface 9 has a flat surface extending in the first direction X and the second direction Y, and is formed approximately parallel to the active surface 8.
  • the outer peripheral surface 9 is formed by a c-plane (Si-plane).
  • the outer peripheral surface 9 is continuous with the first to fourth side surfaces 5A to 5D.
  • the outer peripheral surface 9 has a outer peripheral depth DO.
  • the outer peripheral depth DO may be 0.1 ⁇ m or more and 5 ⁇ m or less. It is preferable that the outer peripheral depth DO is 2.5 ⁇ m or less.
  • the first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer peripheral surface 9.
  • the first connection surface 10A is located on the first side surface 5A side
  • the second connection surface 10B is located on the second side surface 5B side
  • the third connection surface 10C is located on the third side surface 5C side
  • the fourth connection surface 10D is located on the fourth side surface 5D side.
  • the first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y.
  • the third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X.
  • the first to fourth connection surfaces 10A to 10D may extend approximately vertically between the active surface 8 and the outer peripheral surface 9 so as to define a square-prism-shaped active plateau 11.
  • the first to fourth connection surfaces 10A to 10D may be inclined obliquely downward from the active surface 8 toward the outer peripheral surface 9 so as to define a square-prism-shaped active plateau 11.
  • the active plateau 11 is defined in a protruding shape in the first semiconductor region 6 on the first main surface 3.
  • the active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.
  • the semiconductor device 1 includes an active region 12, a first side end region 13, a second side end region 14, a first termination region 15, a second termination region 16, and a peripheral region 17 on the first main surface 3.
  • the active region 12 is a region where the output current (drain current) of the transistor is generated.
  • the active region 12 is provided on the inner side of the active surface 8 and spaced apart from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D).
  • the active region 12 is provided in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the proportion of the active region 12 in the active surface 8 is preferably 50% or more and 95% or less.
  • the proportion of the active region 12 may be a value belonging to any one of the following ranges: 50% or more and 60% or more, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and 95% or less.
  • the proportion of the active region 12 is preferably 70% or more.
  • the first side end region 13 is provided as a non-active region on one side of the active region 12 in the first direction X (the third connection surface 10C side) on the active surface 8.
  • the first side end region 13 is provided in a band shape extending in the second direction Y in a plan view.
  • the second side end region 14 is provided as a non-active region on the active surface 8 on the other side in the first direction X (the fourth connection surface 10D side) of the active region 12, and faces the first side end region 13 across the active region 12 in the first direction X.
  • the second side end region 14 is provided in a band shape extending in the second direction Y in a plan view.
  • the first termination region 15 is provided as an inactive region on one side of the active region 12 in the second direction Y (the first connection surface 10A side).
  • the first termination region 15 is provided in a band shape extending in the first direction X in a plan view, and faces the active region 12, the first side end region 13, and the second side end region 14 in the second direction Y.
  • the second termination region 16 is provided as an inactive region on the other side in the second direction Y (the second connection surface 10B side) of the active region 12.
  • the second termination region 16 is provided in a band shape extending in the first direction X in a plan view, and faces the active region 12, the first side end region 13, and the second side end region 14 in the second direction Y.
  • the outer peripheral region 17 is provided on the outer peripheral surface 9 as a non-active region.
  • the outer peripheral region 17 is provided in a ring shape (specifically, a rectangular ring shape) surrounding the active surface 8 (active plateau 11) in a plan view.
  • the outer peripheral region 17 surrounds the active region 12, the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 in a plan view.
  • FIG. 4 is an enlarged plan view showing an example layout of the active region 12.
  • FIG. 5 is an enlarged plan view showing an example layout of the first side end region 13.
  • FIG. 6 is an enlarged plan view showing an example layout of the first termination region 15.
  • FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 4.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 4.
  • Figure 9 is a cross-sectional view taken along line IX-IX in Figure 5.
  • Figure 10 is a cross-sectional view taken along line X-X in Figure 5.
  • Figure 11 is a cross-sectional view taken along line XI-XI in Figure 5.
  • Figure 12 is a cross-sectional view taken along line XII-XII in Figure 5.
  • Figure 13 is a cross-sectional view taken along line XIII-XIII in Figure 6.
  • Figure 14 is a cross-sectional view showing the structure of the peripheral region 17.
  • the semiconductor device 1 includes a p-type body region 18 (first impurity region) formed in a surface layer portion of the first main surface 3 (active surface 8).
  • the body region 18 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8.
  • the body region 18 is formed in a layer extending along the active surface 8.
  • the body region 18 is preferably formed over the entire active surface 8 and exposed from the first to fourth connection surfaces 10A to 10D.
  • the semiconductor device 1 includes an n-type source region 19 (second impurity region) formed in the surface layer of the body region 18 in the active region 12.
  • the source region 19 is formed at a distance from the bottom of the body region 18 toward the active surface 8. In other words, the source region 19 is formed in a region on the active surface 8 side of the body region 18.
  • the source region 19 has a higher n-type impurity concentration than the first semiconductor region 6.
  • the source region 19 forms a transistor channel with the first semiconductor region 6 in the body region 18.
  • the source region 19 is not formed in the first side end region 13, the second side end region 14, the first termination region 15, or the second termination region 16.
  • the source region 19 may be formed in at least one of the first side end region 13, the second side end region 14, the first termination region 15, or the second termination region 16, to the extent that it does not affect the electrical characteristics of the channel.
  • the source region 19 may also be formed over the entire active surface 8.
  • the semiconductor device 1 includes a plurality of trench electrode type gate structures 20 formed on the first main surface 3 (active surface 8).
  • the gate structures 20 may be referred to as "trench gate structures.”
  • a gate potential is applied to the gate structures 20 as a control potential.
  • the plurality of gate structures 20 control the inversion and non-inversion of the channel in the body region 18 in response to the gate potential.
  • the multiple gate structures 20 are arranged in the active region 12 at intervals inward from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D), and define the active region 12 in the inner part of the active surface 8.
  • the multiple gate structures 20 are each formed in a band shape extending in the first direction X in a plan view, and are arranged at intervals in the second direction Y.
  • the multiple gate structures 20 penetrate the body region 18 and source region 19 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • Each gate structure 20 has a first width W1 in the second direction Y and a first depth D1 in the normal direction Z.
  • the first width W1 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the first width W1 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the first depth D1 is less than the aforementioned peripheral depth DO.
  • the first depth D1 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the first depth D1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • Each gate structure 20 includes a first trench 21, a first insulating film 22, and a first buried electrode 23.
  • the first trench 21 is formed in the active surface 8 and defines the wall surface of the gate structure 20.
  • the first insulating film 22 covers the wall surface of the first trench 21.
  • the first insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the first insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 22 includes a silicon oxide film made of an oxide of the chip 2.
  • the first buried electrode 23 is embedded in the first trench 21 across the first insulating film 22, and faces the channel across the first insulating film 22.
  • the first buried electrode 23 may include p-type or n-type conductive polysilicon.
  • the semiconductor device 1 includes a plurality of trench electrode type source structures 25 formed on the first main surface 3 (active surface 8) in the active region 12.
  • a source potential is applied to the plurality of source structures 25 as a low potential (a second potential lower than the drain potential).
  • the source structures 25 may be referred to as a "trench source structure", a "first source structure”, a “first trench source structure”, etc.
  • the multiple source structures 25 are each formed on the active surface 8 so as to be adjacent to the multiple gate structures 20 in the second direction Y in the active region 12. Specifically, the multiple source structures 25 are each disposed in regions between pairs of adjacent gate structures 20, and face the multiple gate structures 20 in the second direction Y. In other words, the multiple source structures 25 are arranged alternately with the multiple gate structures 20 in the second direction Y.
  • the multiple source structures 25 are each formed in a band shape extending in the first direction X in a plan view. In this embodiment, the multiple source structures 25 are drawn out from the active region 12 to at least one of the first side end region 13 and the second side end region 14 (in this embodiment, both). The multiple source structures 25 face the gate structure 20 in the second direction Y in the active region 12, but do not face the gate structure 20 in the second direction Y in the first side end region 13 (second side end region 14).
  • the multiple source structures 25 penetrate at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment) and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment).
  • the multiple source structures 25 penetrate the body region 18 and the source region 19 to reach the first semiconductor region 6 in the active region 12, and penetrate the body region 18 to reach the first semiconductor region 6 in the first side end region 13 (second side end region 14).
  • the multiple source structures 25 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • Each source structure 25 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z.
  • the second width W2 may be approximately equal to the first width W1 described above.
  • the second width W2 may be equal to or greater than the first width W1.
  • the second width W2 may be greater than the first width W1.
  • the second width W2 may be greater than or equal to 0.1 ⁇ m and less than or equal to 3 ⁇ m. It is preferable that the second width W2 be greater than or equal to 0.5 ⁇ m and less than or equal to 2 ⁇ m.
  • the second depth D2 is equal to or greater than the first depth D1 described above. In this embodiment, the second depth D2 is greater than the first depth D1. It is preferable that the second depth D2 is 1.5 to 3 times the first depth D1. In this embodiment, the second depth D2 is approximately equal to the outer circumferential depth DO described above.
  • the second depth D2 may be 0.1 ⁇ m to 5 ⁇ m. It is particularly preferable that the second depth D2 is 2.5 ⁇ m or less.
  • Each source structure 25 is disposed in the second direction Y from the gate structure 20 at a first interval I1. It is preferable that the first interval I1 is 0.5 to 2 times the first width W1 (second width W2). It is particularly preferable that the first interval I1 is less than the first width W1 (second width W2).
  • the first interval I1 may be 0.1 ⁇ m to 2.5 ⁇ m. It is preferable that the first interval I1 is 0.5 ⁇ m to 1.5 ⁇ m.
  • Each source structure 25 includes a second trench 26, a second insulating film 27, and a second buried electrode 28.
  • the second trench 26 is formed in the active surface 8 and defines the wall surface of the source structure 25.
  • the sidewall of the second trench 26 is in communication with the third connection surface 10C and the fourth connection surface 10D.
  • the bottom wall of the second trench 26 is in communication with the outer peripheral surface 9.
  • the second insulating film 27 covers the wall surface of the second trench 26.
  • the second insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the second insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 27 includes a silicon oxide film made of an oxide of the chip 2.
  • the second buried electrode 28 is buried in the second trench 26 with the second insulating film 27 in between.
  • the second buried electrode 28 may include p-type or n-type conductive polysilicon.
  • the semiconductor device 1 includes a plurality of trench electrode type side end structures 30 formed on the first main surface 3 (active surface 8) in the first side end region 13.
  • a source potential is applied to the plurality of side end structures 30.
  • the side end structures 30 may be referred to as “trench side end structures", “second source structures”, “second trench source structures”, etc.
  • the plurality of side end structures 30 are also formed in the second side end region 14.
  • the configuration on the second side end region 14 side is similar to the configuration on the first side end region 13 side.
  • the description of the first side end region 13 side applies to the description of the second side end region 14 side.
  • the multiple side end structures 30 are respectively arranged in the first side end region 13 on the periphery of the active surface 8 (third connection surface 10C) and in the region between the multiple gate structures 20.
  • the multiple side end structures 30 face the multiple gate structures 20 in a one-to-one correspondence in the first direction X.
  • the multiple side end structures 30 are respectively arranged in the regions between pairs of source structures 25 adjacent to each other in the second direction Y, and face the multiple source structures 25 in the second direction Y.
  • the multiple side end structures 30 are arranged alternately with the multiple source structures 25 in the second direction Y.
  • the multiple side end structures 30 are each formed in a band shape extending in the first direction X in a plan view.
  • the multiple side end structures 30 on the first side end region 13 side penetrate the third connection surface 10C and are exposed from the third connection surface 10C.
  • the multiple side end structures 30 on the second side end region 14 side penetrate the fourth connection surface 10D and are exposed from the fourth connection surface 10D.
  • the multiple side end structures 30 penetrate the body region 18 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • Each side end structure 30, like the source structure 25, has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z.
  • Each side end structure 30 is disposed at a second distance I2 from the gate structure 20 in the first direction X, and at a third distance I3 from the source structure 25 in the second direction Y.
  • the second interval I2 is preferably 0.5 to 2 times the first width W1 (second width W2).
  • the second interval I2 is preferably 0.5 to 2 times the first interval I1. It is particularly preferable that the second interval I2 is 1.5 times or less the first interval I1.
  • the second interval I2 may be approximately equal to the first interval I1.
  • the second interval I2 may be 0.1 ⁇ m to 2.5 ⁇ m. It is preferable that the second interval I2 is 0.5 ⁇ m to 1.5 ⁇ m.
  • the third interval I3 is preferably 0.5 to 2 times the first width W1 (second width W2).
  • the third interval I3 may be less than the first width W1 (second width W2).
  • the third interval I3 is preferably approximately equal to the aforementioned first interval I1.
  • the third interval I3 may be 0.1 ⁇ m to 2.5 ⁇ m.
  • the third interval I3 is preferably 0.5 ⁇ m to 1.5 ⁇ m.
  • Each side end structure 30 includes a third trench 31, a third insulating film 32, and a third buried electrode 33.
  • the third trench 31 is formed in the active surface 8 and defines the wall surface of the side end structure 30.
  • the side wall of the third trench 31 is connected to the third connection surface 10C.
  • the bottom wall of the third trench 31 is connected to the outer peripheral surface 9.
  • the third insulating film 32 covers the wall surface of the third trench 31.
  • the third insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the third insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.
  • the third buried electrode 33 is buried in the third trench 31 with the third insulating film 32 sandwiched therebetween.
  • the third buried electrode 33 may include p-type or n-type conductive polysilicon.
  • the semiconductor device 1 includes a plurality of trench electrode type termination structures 35 formed on the first main surface 3 (active surface 8) in the first termination region 15. A source potential is applied to the plurality of termination structures 35.
  • the termination structures 35 may be referred to as “trench termination structures", “third source structures”, “third trench source structures”, etc.
  • the plurality of termination structures 35 are also formed in the second termination region 16.
  • the configuration on the second termination region 16 side is similar to the configuration on the first termination region 15 side.
  • the description of the second termination region 16 side is the same as the description of the first termination region 15 side.
  • the multiple termination structures 35 are each formed in a band extending in the first direction X, and are arranged at intervals in the second direction Y.
  • the multiple termination structures 35 are continuously arranged at equal intervals in the second direction Y so as to face each other with a part of the chip 2 in between. In other words, the multiple termination structures 35 face each other without sandwiching the gate structure 20 between them.
  • the multiple termination structures 35 face the multiple gate structures 20 and the multiple source structures 25 in the second direction Y.
  • the multiple termination structures 35 penetrate at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment) and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment).
  • the multiple termination structures 35 face the multiple gate structures 20, the multiple source structures 25, and the multiple side end structures 30 in the second direction Y.
  • the multiple termination structures 35 penetrate the body region 18 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.
  • Each termination structure 35 like the source structure 25, has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z.
  • the termination structure 35 is disposed at the aforementioned first distance I1 from the gate structure 20.
  • the termination structure 35 is disposed at the aforementioned first distance I1 from the source structure 25.
  • Each termination structure 35 includes a fourth trench 36, a fourth insulating film 37, and a fourth buried electrode 38.
  • the fourth trench 36 is formed in the active surface 8 and defines the wall surface of the termination structure 35.
  • the side wall of the fourth trench 36 is connected to the third connection surface 10C.
  • the bottom wall of the fourth trench 36 is connected to the outer peripheral surface 9.
  • the fourth insulating film 37 covers the wall surface of the fourth trench 36.
  • the fourth insulating film 37 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the fourth insulating film 37 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the fourth insulating film 37 includes a silicon oxide film made of an oxide of the chip 2.
  • the fourth buried electrode 38 is buried in the fourth trench 36 with the fourth insulating film 37 in between.
  • the fourth buried electrode 38 may include p-type or n-type conductive polysilicon.
  • the semiconductor device 1 includes a plurality of p-type first well regions 41 formed in a region along a plurality of gate structures 20 in a surface layer portion of the active surface 8 of the active region 12.
  • the first well regions 41 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 18.
  • the p-type impurity concentration of the first well regions 41 may be lower than the p-type impurity concentration of the body region 18.
  • the multiple first well regions 41 cover the wall surfaces of the corresponding gate structures 20 at intervals from the adjacent source structures 25, and are electrically connected to the body region 18 at the surface portion of the active surface 8.
  • the multiple first well regions 41 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with a part of the first semiconductor region 6 in between.
  • the multiple first well regions 41 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of p-type second well regions 42 formed in a region along the plurality of source structures 25 in the surface layer portion of the active surface 8 of the active region 12.
  • the second well regions 42 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 18.
  • the p-type impurity concentration of the second well regions 42 may be lower than the p-type impurity concentration of the body region 18. It is preferable that the p-type impurity concentration of the second well regions 42 is approximately equal to the p-type impurity concentration of the first well region 41.
  • the second well regions 42 cover the wall surfaces of the corresponding source structures 25 at intervals from the adjacent gate structures 20, and are electrically connected to the body region 18 at the surface portion of the active surface 8.
  • the second well regions 42 cover the wall surfaces of the corresponding source structures 25 in the active region 12, the first side end region 13, and the second side end region 14, and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment).
  • the multiple second well regions 42 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple second well regions 42 are located on the bottom side of the first semiconductor region 6 relative to the depth positions of the bottoms of the multiple first well regions 41.
  • the multiple second well regions 42 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of p-type third well regions 43 formed in a region along the plurality of side end structures 30 in the surface layer portion of the active surface 8 of the first side end region 13 (second side end region 14).
  • the third well region 43 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 18.
  • the p-type impurity concentration of the third well region 43 may be lower than the p-type impurity concentration of the body region 18. It is preferable that the p-type impurity concentration of the third well region 43 is approximately equal to the p-type impurity concentration of the first well region 41 (second well region 42).
  • the multiple third well regions 43 cover the wall surfaces of the corresponding side end structures 30 at intervals from the adjacent gate structures 20 and source structures 25, and are electrically connected to the body region 18 in the surface portion of the active surface 8.
  • the third well regions 43 may be integrated with the first well region 41 in the region between the gate structures 20 and the side end structures 30.
  • the multiple third well regions 43 are exposed from the third connection surface 10C (fourth connection surface 10D).
  • the multiple third well regions 43 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple third well regions 43 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple first well regions 41.
  • the bottoms of the multiple third well regions 43 are formed at approximately the same depth as the bottoms of the multiple second well regions 42.
  • the multiple third well regions 43 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes at least one (in this embodiment, multiple) fourth well region 44 of p-type formed in a region along the multiple termination structures 35 in the first termination region 15 (second termination region 16).
  • the fourth well region 44 has a higher p-type impurity concentration than the body region 18.
  • the p-type impurity concentration of the fourth well region 44 may be lower than the body region 18. It is preferable that the p-type impurity concentration of the fourth well region 44 is approximately equal to the p-type impurity concentration of the first well region 41 (second well region 42).
  • the multiple fourth well regions 44 cover the wall surfaces of the corresponding termination structures 35 at intervals from the adjacent termination structures 35, and are electrically connected to the body region 18 at the surface portion of the active surface 8.
  • the multiple fourth well regions 44 extend in a band shape along the corresponding termination structures 35 in a plan view, and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment).
  • the multiple fourth well regions 44 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottoms of the multiple fourth well regions 44 are located on the bottom side of the first semiconductor region 6 relative to the depth position of the bottoms of the multiple first well regions 41. It is preferable that the bottoms of the multiple fourth well regions 44 are formed at a depth approximately equal to the bottoms of the multiple second well regions 42.
  • the multiple fourth well regions 44 form pn junctions with the first semiconductor region 6.
  • the semiconductor device 1 includes a plurality of p-type contact regions 45 formed in a region along the plurality of source structures 25 in the surface layer portion of the active surface 8 of the active region 12.
  • the contact regions 45 may be referred to as "backgate regions.”
  • the contact regions 45 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 18.
  • the p-type impurity concentration of the contact regions 45 is higher than the p-type impurity concentration of the second well region 42.
  • the multiple contact regions 45 cover the wall surfaces of the corresponding source structures 25 in the corresponding second well regions 42.
  • the multiple contact regions 45 are formed in a one-to-many correspondence with each source structure 25.
  • the multiple contact regions 45 are formed at intervals along the corresponding source structures 25.
  • the multiple contact regions 45 are extended from within the corresponding second well region 42 along the wall surface of the corresponding source structure 25 to the surface layer of the body region 18 and exposed from the active surface 8.
  • the multiple contact regions 45 are formed in the active region 12, and are not formed in the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16. In other words, the contact regions 45 are not formed in the third well region 43 and the fourth well region 44.
  • the multiple contact regions 45 face the gate structure 20 in the second direction Y, and do not face the side end structure 30 in the second direction Y.
  • the multiple contact regions 45 are each formed in a band shape extending in the first direction X in a plan view.
  • the length of the multiple contact regions 45 in the first direction X is preferably equal to or greater than the second width W2 described above.
  • the length of the multiple contact regions 45 is preferably greater than the distance between two adjacent contact regions 45 in the first direction X.
  • the multiple contact regions 45 along one source structure 25 face the multiple contact regions 45 along the other source structure 25 in the second direction Y.
  • the multiple contact regions 45 are arranged in a matrix shape with gaps in between in the first direction X and the second direction Y as a whole when viewed in a plan view.
  • the multiple contact regions 45 along one source structure 25 may be arranged offset in the first direction X so as to face the second direction Y in the region between the multiple contact regions 45 along the other source structure 25.
  • the multiple contact regions 45 may be arranged in a staggered manner overall in a plan view with intervals in the first direction X and the second direction Y.
  • the semiconductor device 1 includes a p-type outer well region 46 formed in a surface layer portion of the outer peripheral surface 9.
  • the outer well region 46 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 45.
  • the p-type impurity concentration of the outer well region 46 is higher than the p-type impurity concentration of the body region 18.
  • the p-type impurity concentration of the outer well region 46 may be lower than that of the body region 18. It is preferable that the outer well region 46 has a p-type impurity concentration approximately equal to that of the first well region 41 (second well region 42).
  • the outer well region 46 is formed at a distance from the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8 in a plan view, and extends in a band shape along the active surface 8.
  • the outer well region 46 is formed in a ring shape (specifically, a square ring shape) that surrounds the active surface 8 in a plan view.
  • the outer well region 46 extends from the surface portion of the outer peripheral surface 9 toward the surface portions of the first to fourth connection surfaces 10A to 10D, covering the first to fourth connection surfaces 10A to 10D.
  • the outer well region 46 is electrically connected to the body region 18 at the surface portion of the active surface 8.
  • the outer well region 46 is connected to the second well region 42, the third well region 43, and the fourth well region 44 at the third connection surface 10C (fourth connection surface 10D).
  • the outer well region 46 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer peripheral surface 9, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the bottom of the outer well region 46 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the gate structure 20.
  • the bottom of the outer well region 46 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the source structure 25.
  • the bottom of the outer well region 46 is located closer to the bottom of the first semiconductor region 6 than the bottom of the contact region 45. It is preferable that the bottom of the outer well region 46 is formed at a depth position approximately equal to the bottom of the second well region 42.
  • the outer well region 46 forms a pn junction with the first semiconductor region 6.
  • the semiconductor device 1 includes a p-type outer contact region 47 formed in the surface layer of the outer peripheral surface 9.
  • the outer contact region 47 has a higher p-type impurity concentration than the body region 18.
  • the p-type impurity concentration of the outer contact region 47 is higher than the outer well region 46. It is preferable that the p-type impurity concentration of the outer contact region 47 is approximately equal to the p-type impurity concentration of the contact region 45.
  • the outer contact region 47 is formed in the surface layer of the outer well region 46 at a distance from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) in a plan view, and is formed in a band shape extending along the active surface 8.
  • the outer contact region 47 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in a plan view.
  • the outer contact region 47 is formed at a distance from the bottom of the outer well region 46 towards the outer peripheral surface 9, and faces the first semiconductor region 6 across a portion of the outer well region 46.
  • the outer contact region 47 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the source structure 25. It is preferable that the bottom of the outer contact region 47 is formed at a depth position approximately equal to the bottom of the contact region 45.
  • the semiconductor device 1 includes at least one (preferably 2 to 20) p-type field region 48 formed in the surface layer of the outer peripheral surface 9.
  • the semiconductor device 1 includes four field regions 48.
  • the multiple field regions 48 are formed in an electrically floating state and reduce the electric field within the chip 2 at the outer peripheral surface 9.
  • the number, width, depth, p-type impurity concentration, etc. of the field regions 48 are arbitrary and can take various values depending on the electric field to be relaxed.
  • the field regions 48 may have a lower p-type impurity concentration than the outer contact region 47.
  • the field regions 48 may have a higher p-type impurity concentration than the outer well region 46.
  • the field regions 48 may have a lower p-type impurity concentration than the outer well region 46.
  • the multiple field regions 48 are formed in the region between the periphery of the outer peripheral surface 9 and the outer well region 46.
  • the multiple field regions 48 are arranged at intervals from the outer well region 46 side to the periphery of the outer peripheral surface 9.
  • the multiple field regions 48 are formed in a band shape extending along the active surface 8 in a plan view.
  • the multiple field regions 48 are formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in a plan view.
  • the multiple field regions 48 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and face the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the multiple field regions 48 are located closer to the bottom of the first semiconductor region 6 than the bottom wall of the source structure 25.
  • the bottoms of the multiple field regions 48 are located closer to the bottom of the first semiconductor region 6 than the bottom of the contact region 45.
  • the bottoms of the multiple field regions 48 may be formed at a depth position approximately equal to the bottom of the second well region 42.
  • the semiconductor device 1 includes a main surface insulating film 50 that covers the first main surface 3.
  • the main surface insulating film 50 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the main surface insulating film 50 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 50 includes a silicon oxide film made of an oxide of the chip 2.
  • the main surface insulating film 50 selectively covers the active surface 8, the outer peripheral surface 9, and the first to fourth connection surfaces 10A to 10D.
  • the main surface insulating film 50 is connected to the first insulating film 22, the second insulating film 27, the third insulating film 32, and the fourth insulating film 37 on the active surface 8, and exposes the first buried electrode 23, the second buried electrode 28, the third buried electrode 33, and the fourth buried electrode 38.
  • the main surface insulating film 50 covers the outer well region 46, the outer contact region 47, and the multiple field regions 48 on the outer peripheral surface 9.
  • the main surface insulating film 50 is continuous with the first to fourth side surfaces 5A to 5D.
  • the main surface insulating film 50 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.
  • the main surface insulating film 50 is connected to the second insulating film 27, the third insulating film 32, and the fourth insulating film 37 at the first to fourth connection surfaces 10A to 10D, exposing the second buried electrode 28, the third buried electrode 33, and the fourth buried electrode 38.
  • the semiconductor device 1 includes a sidewall wiring 51 formed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connection surfaces 10A to 10D. Specifically, the sidewall wiring 51 is disposed on the main surface insulating film 50. The sidewall wiring 51 also functions as a "sidewall structure" that reduces the step formed between the active surface 8 and the outer peripheral surface 9.
  • the sidewall wiring 51 is preferably formed in a band shape extending along at least one of the third connection surface 10C and the fourth connection surface 10D.
  • the sidewall wiring 51 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 10A to 10D so as to surround the active surface 8 in a plan view.
  • the portions of the sidewall wiring 51 that cover the four corners of the active surface 8 are formed in a curved shape toward the outer circumferential surface 9.
  • the sidewall wiring 51 includes a portion that extends in a film-like manner along the outer peripheral surface 9, and a portion that extends in a film-like manner along the first to fourth connection surfaces 10A to 10D.
  • the portion of the sidewall wiring 51 located on the outer peripheral surface 9 may cover the outer peripheral surface 9 in a film-like manner in the region on the outer peripheral surface 9 side relative to the active surface 8.
  • the portion of the sidewall wiring 51 located on the outer peripheral surface 9 may have a thickness less than the thickness of the active plateau 11 (outer peripheral depth DO).
  • the sidewall wiring 51 faces the outer well region 46 on the outer peripheral surface 9, sandwiching the main surface insulating film 50 therebetween.
  • the sidewall wiring 51 may also face the outer contact region 47, sandwiching the main surface insulating film 50 therebetween.
  • the sidewall wiring 51 is formed at a distance from the field region 48 toward the active surface 8 in a plan view.
  • the sidewall wiring 51 covers the first to fourth connection surfaces 10A to 10D, sandwiching the main surface insulating film 50 between them.
  • the sidewall wiring 51 faces the second well region 42, the third well region 43, the fourth well region 44, and the outer well region 46 at the first to fourth connection surfaces 10A to 10D, sandwiching the main surface insulating film 50 between them.
  • the sidewall wiring 51 also faces the body region 18, sandwiching the main surface insulating film 50 between them.
  • the sidewall wiring 51 covers the exposed portion (second buried electrode 28) of the source structure 25, the exposed portion (third buried electrode 33) of the side end structure 30, and the exposed portion (fourth buried electrode 38) of the termination structure 35 on the first to fourth connection surfaces 10A to 10D.
  • the sidewall wiring 51 is electrically connected to the source structure 25, the side end structure 30, and the termination structure 35, and applies a source potential from the outer peripheral surface 9 side.
  • the sidewall wiring 51 has an overlapping portion 52 that extends from at least one of the first to fourth connection surfaces 10A to 10D onto the edge of the active surface 8.
  • the overlapping portion 52 covers the active surface 8 in a film-like manner in a plan view, and is formed in a band shape extending along the edge of the active surface 8.
  • the overlapping portion 52 is formed in a ring shape (specifically, a square ring shape) that surrounds the inner part of the active surface 8 in a plan view.
  • the overlapping portion 52 is formed on the active surface 8 at a distance from the multiple gate structures 20 toward the peripheral side of the active surface 8, and covers the exposed portion (second buried electrode 28) of the source structure 25, the exposed portion (third buried electrode 33) of the side end structure 30, and the exposed portion (fourth buried electrode 38) of the termination structure 35.
  • the sidewall wiring 51 is electrically connected to the source structure 25, the side end structure 30, and the termination structure 35 on the active surface 8.
  • the sidewall wiring 51 includes p-type or n-type conductive polysilicon and is formed integrally with the second buried electrode 28, the third buried electrode 33, and the fourth buried electrode 38.
  • the sidewall wiring 51 may be formed separately from the second buried electrode 28, the third buried electrode 33, and the fourth buried electrode 38.
  • the semiconductor device 1 includes a plurality of gate connection electrodes 53 that cover the plurality of gate structures 20 in the active region 12 in a film-like manner.
  • the gate connection electrodes 53 may be referred to as “connection electrodes,” “connection electrode films,” “gate connection electrode films,” etc.
  • the gate connection electrodes 53 may be considered to be one component of the gate structure 20.
  • the gate connection electrode 53 is formed as an external connection portion (contact portion) of the gate structure 20, and at least one gate connection electrode 53 is provided for each gate structure 20.
  • multiple gate connection electrodes 53 are provided at intervals in a one-to-many corresponding relationship with each gate structure 20.
  • the multiple gate connection electrodes 53 selectively cover the inner portion and both ends of the corresponding gate structure 20.
  • Each gate connection electrode 53 is connected to the first buried electrode 23 in a portion covering the corresponding gate structure 20, and has a portion that is pulled out from above the first buried electrode 23 onto the main surface insulating film 50.
  • each gate connection electrode 53 is formed integrally with the corresponding first buried electrode 23.
  • each gate connection electrode 53 includes a portion where a part of the first buried electrode 23 is pulled out in the form of a film into an area outside the gate structure 20 (above the main surface insulating film 50).
  • the gate connection electrode 53 may be formed separately from the first buried electrode 23.
  • the multiple gate connection electrodes 53 are formed at intervals in the first direction X from the multiple side end structures 30 in a plan view, and are formed at intervals in the second direction Y from the multiple source structures 25. In other words, the multiple gate connection electrodes 53 expose the multiple source structures 25 and the multiple side end structures 30.
  • the multiple gate connection electrodes 53 are arranged alternately with the multiple source structures 25 in the second direction Y in a planar view.
  • the multiple gate connection electrodes 53 are each formed in a strip shape extending in the first direction X.
  • the multiple gate connection electrodes 53 do not face the multiple side end structures 30 in the second direction Y in a planar view.
  • the gate connection electrode 53 has an electrode surface that extends along the active surface 8.
  • the gate connection electrode 53 is formed in a tapered shape (quadratic pyramid shape) from the active surface 8 toward the electrode surface in a cross-sectional view.
  • the electrode surface is preferably formed to be wider than the gate structure 20 in the second direction Y.
  • the electrode surface preferably has a portion that faces the gate structure 20 in the normal direction Z, and a portion that faces an area outside the gate structure 20 (i.e., the main surface insulating film 50) in the normal direction Z.
  • the gate connection electrode 53 includes p-type or n-type conductive polysilicon.
  • the gate connection electrode 53 has an electrode thickness TE.
  • the electrode thickness TE is preferably 0.5 times or more the first width W1 (second width W2) described above.
  • the electrode thickness TE is preferably equal to or less than the outer circumferential depth DO described above.
  • the electrode thickness TE is preferably equal to or less than the second depth D2 described above. It is particularly preferable that the electrode thickness TE is less than the second depth D2 (outer circumferential depth DO).
  • the electrode thickness TE is preferably equal to or less than the first depth D1 described above. Of course, the electrode thickness TE may be greater than the first depth D1. It is particularly preferable that the electrode thickness TE is less than the first depth D1.
  • the electrode thickness TE may be equal to or greater than 0.05 ⁇ m and equal to or less than 2.5 ⁇ m. It is preferable that the electrode thickness TE is equal to or greater than 0.5 ⁇ m and equal to or less than 1.5 ⁇ m.
  • FIG. 15 is a plan view showing pad region 55.
  • FIG. 16 is a plan view showing an example layout of gate electrode 80 and source electrode 100.
  • FIG. 17 is an enlarged plan view showing a main part of FIG. 16 together with gate structure 20.
  • FIG. 18 is an enlarged plan view showing an example layout of region XVIII shown in FIG. 17.
  • FIG. 19 is an enlarged plan view showing a main portion of FIG. 18 together with a first gate structure 20A according to a first layout example.
  • FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 19.
  • FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 19.
  • FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 19.
  • FIG. 23 is a cross-sectional view taken along line XXIII-XXIII shown in FIG. 19.
  • the semiconductor device 1 includes a pad region 55 set on the first main surface 3.
  • the pad region 55 is a region in which a pad electrode (gate pad 81 described below) for the gate structure 20 is disposed.
  • the pad region 55 is set on the active surface 8 with a space from the outer peripheral surface 9.
  • the pad region 55 is set in the active region 12.
  • the pad region 55 is also a region that partially shields the current path of the output current generated in the active region 12.
  • a structure located directly below the pad region 55 on the active surface 8 functions as a voltage-resistant structure.
  • the pad region 55 is set in the active region 12 at a distance from the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 in a plan view.
  • the pad region 55 is set in an area on one side in the second direction Y of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view.
  • the pad region 55 is located on an imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.
  • the pad region 55 faces the center of the first side surface 5A (first connection surface 10A) in the second direction Y in a plan view.
  • the pad region 55 has a planar area less than the planar area of the active surface 8 (first main surface 3).
  • the proportion of the pad region 55 in the active surface 8 (first main surface 3) is preferably 1% or more and 25% or less.
  • the proportion of the pad region 55 may be a value belonging to any one of the following ranges: 1% or more and 5% or more, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, and 20% or more and 25% or less.
  • the proportion of the pad region 55 is preferably 10% or less.
  • the semiconductor device 1 includes a first gate region 56, a second gate region 57, and a third gate region 58 as arrangement regions for a plurality of gate structures 20.
  • the first gate region 56 is a region in the active region 12 that passes through the pad region 55 in the first direction X.
  • the first gate region 56 is provided in a region on one side (the first side surface 5A side) of the middle portion of the pad region 55 in the second direction Y.
  • the width of the first gate region 56 is less than 1/2 the width of the pad region 55.
  • the width of the first gate region 56 may be 1/2 or more the width of the pad region 55.
  • the first gate region 56 may have a portion located in a region on the other side (second side surface 5B side) in the second direction Y with respect to the middle portion of the pad region 55.
  • the second gate region 57 is a region in the active region 12 that passes through the pad region 55 in the first direction X and is adjacent to the first gate region 56 in the second direction Y.
  • the second gate region 57 is provided in a region on the other side (the second side surface 5B side) of the first gate region 56 in the second direction Y.
  • the width of the second gate region 57 is greater than the width of the first gate region 56 and less than the width of the pad region 55.
  • the width of the second gate region 57 may be greater than 1/2 the width of the pad region 55.
  • the width of the first gate region 56 is 1/2 or more the width of the pad region 55, the width of the second gate region 57 may be less than 1/2 the width of the pad region 55.
  • the third gate region 58 is a region in the active region 12 that does not pass through the pad region 55.
  • the third gate region 58 is the entire region of the active region 12 that is located on the other side of the pad region 55 in the second direction Y.
  • the third gate region 58 is provided on the other side of the second gate region 57 in the second direction Y (the second side surface 5B side), and faces the first gate region 56 across the second gate region 57 in the second direction Y.
  • the width of the third gate region 58 is greater than the width of the first gate region 56.
  • the width of the third gate region 58 is greater than the width of the second gate region 57.
  • the width of the third gate region 58 is greater than the sum of the widths of the first gate region 56 and the second gate region 57 (i.e., the width of the pad region 55).
  • the aforementioned multiple gate structures 20 include multiple gate structures 20 that pass through the pad region 55 in the active region 12, and multiple gate structures 20 that are located outside the pad region 55 in the active region 12.
  • the multiple gate structures 20 are classified into at least one (multiple in this embodiment) first gate structure 20A, at least one (multiple in this embodiment) second gate structure 20B, and at least one (multiple in this embodiment) third gate structure 20C, depending on their placement location in the active region 12 and their electrical properties.
  • the first gate structure 20A is disposed in the first gate region 56, and has at least one resistance portion 60 in the middle in the longitudinal direction (first direction X). In Figures 18 and 19, the resistance portion 60 is surrounded by a two-dot chain line. The resistance portion 60 is a portion that constitutes at least a part of the resistance (specifically, the gate resistance RG).
  • the number of first gate structures 20A disposed in the first gate region 56 may be one or more, and is not limited to a specific number. In this embodiment, multiple (two or more) first gate structures 20A are disposed in the first gate region 56.
  • each first gate structure 20A has a plurality of resistor portions 60.
  • Each resistor portion 60 is formed by utilizing a portion of the first gate structure 20A. That is, each resistor portion 60 is a trench electrode type resistor structure including a first trench 21, a first insulating film 22, and a first buried electrode 23. The main body of the resistor portion 60 is formed by a portion of the first buried electrode 23.
  • the resistance value of each resistor portion 60 can be adjusted by the resistance value (impurity concentration) of the first buried electrode 23, the length of the resistor portion 60 in the first direction X, the width of the resistor portion 60 in the second direction Y (the width of the first trench 21), the depth of the resistor portion 60 (the depth of the first trench 21), etc.
  • the multiple resistance portions 60 include a first resistance portion 60A on one longitudinal side (third side surface 5C side) and a second resistance portion 60B on the other longitudinal side (fourth side surface 5D side).
  • the first resistance portion 60A is provided at the intersection of one side of the pad region 55 (third side surface 5C side) and the first gate structure 20A.
  • the first resistance portion 60A is provided so as to straddle the regions inside and outside the pad region 55, and has a first electrical end portion 61 located within the pad region 55 and a second electrical end portion 62 located outside the pad region 55.
  • the second resistor portion 60B is provided at a distance from the first resistor portion 60A at the intersection of the other side (fourth side surface 5D side) of the pad region 55 and the first gate structure 20A.
  • the second resistor portion 60B is provided to straddle the inside and outside regions of the pad region 55, and has a first electrical end 61 located within the pad region 55 and a second electrical end 62 located outside the pad region 55.
  • the multiple first gate structures 20A are arranged at intervals in the second direction Y so that the multiple resistance portions 60 are positioned on the same straight line extending along the second direction Y.
  • the multiple first resistance portions 60A are arranged in a line in the second direction Y
  • the multiple second resistance portions 60B are arranged in a line in the second direction Y.
  • the multiple first gate structures 20A penetrate the body region 18 and source region 19 in the regions inside and outside the pad region 55. That is, the channel is formed in a region along the outside of the multiple resistor portions 60 in the surface layer portion of the first main surface 3. The channel is also formed in a region along the multiple resistor portions 60 in the surface layer portion of the first main surface 3. This configuration is effective in generating an output current near the boundary of the pad region 55 (near the resistor portions 60).
  • the second gate structure 20B is disposed in the second gate region 57 and does not have the aforementioned resistive portion 60.
  • the number of second gate structures 20B disposed in the second gate region 57 may be one or more and is not limited to a specific number. In this embodiment, multiple (two or more) second gate structures 20B are disposed in the second gate region 57.
  • the number of second gate structures 20B is preferably greater than the number of first gate structures 20A.
  • the generated current value controlled by the multiple second gate structures 20B (the amount of current generated in the second gate region 57) is preferably greater than the generated current value controlled by the multiple first gate structures 20A (the amount of current generated in the first gate region 56).
  • the number of second gate structures 20B may be less than the number of first gate structures 20A.
  • the combined resistance value of the multiple resistance sections 60 can also be adjusted by adjusting the ratio (number) of first gate structures 20A to the total number of first gate structures 20A and second gate structures 20B.
  • the multiple second gate structures 20B penetrate the body region 18 and the source region 19 in the regions inside and outside the pad region 55.
  • a channel is formed along the portion of the second gate structure 20B located inside and outside the pad region 55 in the surface layer portion of the first main surface 3. This configuration is effective in generating an output current near the boundary of the pad region 55.
  • the third gate structure 20C is disposed in the third gate region 58 and does not have the aforementioned resistive portion 60.
  • the number of third gate structures 20C disposed in the third gate region 58 may be one or more and is not limited to a specific number. In this embodiment, multiple (two or more) third gate structures 20C are disposed in the third gate region 58.
  • the number of third gate structures 20C is preferably greater than the number of first gate structures 20A.
  • the number of third gate structures 20C is preferably greater than the number of second gate structures 20B.
  • the generated current value controlled by the multiple third gate structures 20C (the amount of current generated in the third gate region 58) is preferably greater than the generated current value controlled by the multiple second gate structures 20B (the amount of current generated in the second gate region 57).
  • the number of third gate structures 20C is greater than the total number of first gate structures 20A and second gate structures 20B. In other words, it is preferable that the generated current value controlled by the multiple third gate structures 20C is greater than the generated current value controlled by the multiple first gate structures 20A and the multiple second gate structures 20B.
  • the multiple source structures 25 described above include multiple source structures 25 that pass through the pad region 55 and multiple source structures 25 that are located outside the pad region 55.
  • the multiple source structures 25 include at least one (multiple in this embodiment) source structure 25 that is adjacent to at least one (multiple in this embodiment) first gate structure 20A in the second direction Y in the first gate region 56.
  • the multiple source structures 25 are arranged alternately in the second direction Y with the multiple first gate structures 20A in the first gate region 56.
  • the multiple source structures 25 have a portion in the first gate region 56 that faces the resistor portion 60 of the first gate structure 20A across a portion of the chip 2, and a portion that faces a portion outside the resistor portion 60 of the first gate structure 20A across a portion of the chip 2. In this embodiment, the multiple source structures 25 face the entire first gate structure 20A across a portion of the chip 2 in the first gate region 56.
  • the multiple source structures 25 also include at least one (multiple in this embodiment) source structure 25 adjacent to at least one (multiple in this embodiment) second gate structure 20B in the second gate region 57 in the second direction Y.
  • the multiple source structures 25 also include a source structure 25 interposed between the first gate structure 20A and the second gate structure 20B.
  • the multiple source structures 25 are arranged alternately with the multiple second gate structures 20B in the second direction Y in the second gate region 57.
  • the multiple source structures 25 also include at least one (multiple in this embodiment) source structure 25 adjacent to at least one (multiple in this embodiment) third gate structure 20C in the third gate region 58 in the second direction Y.
  • the multiple source structures 25 also include a source structure 25 interposed between the second gate structure 20B and the third gate structure 20C.
  • the multiple source structures 25 are arranged alternately with the multiple third gate structures 20C in the second direction Y in the third gate region 58.
  • the first well region 41 described above is formed in a region along the multiple first gate structures 20A, the multiple second gate structures 20B, and the multiple third gate structures 20C inside and outside the pad region 55. Therefore, the bias of the electric field inside and outside the pad region 55 is suppressed, and the first well region 41 provides an electric field relaxation effect.
  • the second well region 42 is formed in a region that is aligned with the multiple source structures 25 inside and outside the pad region 55. Therefore, the bias of the electric field inside and outside the pad region 55 is suppressed, and the electric field relaxation effect is obtained by the second well region 42.
  • the contact region 45 is not formed in the pad region 55.
  • the contact regions 45 may be formed in the pad region 55 in a layout similar to that outside the pad region 55.
  • the multiple contact regions 45 may have at least one contact region 45 formed in a region along at least one resistor portion 60 (first resistor portion 60A and second resistor portion 60B) of the first gate structure 20A.
  • the aforementioned multiple side end structures 30 face the multiple first gate structures 20A, the multiple second gate structures 20B, and the multiple third gate structures 20C in a one-to-one correspondence in the first direction X in the first side end region 13 (second side end region 14).
  • the multiple side end structures 30 have a length in the first direction X that is smaller than the length of the multiple first gate structures 20A, the length of the multiple second gate structures 20B, and the length of the multiple third gate structures 20C. It is preferable that the length of the multiple side end structures 30 is larger than the length of the resistance portion 60 of the multiple first gate structures 20A in the first direction X. Of course, the length of the multiple side end structures 30 may be smaller than the length of the resistance portion 60 in the first direction X.
  • the configuration of the first resistor section 60A side of the first gate structure 20A will be described.
  • the configuration of the second resistor section 60B side of the first gate structure 20A is similar to the configuration of the first resistor section 60A side. Therefore, in the following, the description of the second resistor section 60B side will be omitted.
  • the description of the second resistor section 60B side can be obtained by replacing “first resistor section 60A" with “second resistor section 60B" in the following description.
  • the semiconductor device 1 includes at least one resistive electrode 65 that selectively covers the first resistive portions 60A of the multiple first gate structures 20A in a film-like manner.
  • the resistive electrode 65 may be referred to as an "electrode film,” “resistive film,” “resistive electrode film,” or the like.
  • Each resistive electrode 65 constitutes part of a resistor (specifically, a gate resistor RG) together with each first resistive portion 60A.
  • Each resistive electrode 65 may be regarded as one component of each first resistive portion 60A.
  • the resistance value of each resistive portion 60 can also be adjusted by the material and layout of the resistive electrode 65.
  • the resistive electrode 65 includes at least one of a conductive polysilicon film and an alloy crystal film.
  • the alloy crystal film includes alloy crystals composed of a metal element and a nonmetal element.
  • the alloy crystal film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film.
  • the resistive electrode 65 includes p-type or n-type conductive polysilicon.
  • the multiple resistive electrodes 65 are arranged in the same layer as the multiple gate connection electrodes 53 and spaced apart from the multiple gate connection electrodes 53.
  • the multiple resistive electrodes 65 are also arranged in the same layer as the overlapping portion 52 of the sidewall wiring 51 and spaced apart from the overlapping portion 52. In other words, the multiple resistive electrodes 65 are arranged in areas other than the overlapping portion 52 and the gate connection electrodes 53.
  • the multiple resistive electrodes 65 each partially cover a corresponding first resistive portion 60A.
  • the multiple resistive electrodes 65 are provided in a one-to-many correspondence with each corresponding first resistive portion 60A, and cover each corresponding first resistive portion 60A from multiple locations.
  • the multiple resistive electrodes 65 include multiple first resistive electrodes 65A and multiple second resistive electrodes 65B.
  • the multiple first resistive electrodes 65A are arranged in the pad region 55 at intervals from one another, and each covers the first end 61 of a corresponding one of the first resistive portions 60A.
  • each of the multiple first resistance electrodes 65A covers the first end 61 of a corresponding first resistance portion 60A in a film-like manner as a single covering object.
  • each first resistance electrode 65A is provided in one-to-one correspondence with the first end 61 of each first resistance portion 60A and is electrically connected to the first end 61.
  • Each first resistive electrode 65A exposes a region (first buried electrode 23) other than the first end 61 of the corresponding first gate structure 20A.
  • each first resistive electrode 65A is disposed at a distance from the second end 62 of the first resistive portion 60A toward the first end 61 of the first resistive portion 60A, exposing the first buried electrode 23 from the inner portion of the first resistive portion 60A.
  • the multiple first resistance electrodes 65A are each formed in a strip shape extending in the first direction X in a plan view, and face each other in the second direction Y. In other words, the multiple first resistance electrodes 65A are arranged in a stripe shape extending along the multiple first resistance portions 60A in a plan view.
  • the multiple first resistance electrodes 65A are arranged at intervals in the second direction Y so as to be positioned on the same straight line extending in the second direction Y.
  • each first resistance electrode 65A is positioned offset to the other side of the first direction X (the pad region 55 side) with respect to the straight line connecting the multiple gate connection electrodes 53 on the multiple second gate structures 20B side in the second direction Y, and does not face the multiple gate connection electrodes 53 in the second direction Y.
  • the multiple first resistance electrodes 65A may be arranged offset in the first direction X from at least one first resistance electrode 65A so as not to face at least one first resistance electrode 65A in the second direction Y. Such a configuration is effective when fine-tuning the resistance value of each first resistance section 60A.
  • the multiple first resistance electrodes 65A are arranged at intervals in the second direction Y from another first resistance electrode 65A that covers the first gate structure 20A (resistance portion 60) that is not to be covered.
  • the multiple first resistance electrodes 65A are arranged at intervals in the second direction Y from the multiple source structures 25, exposing the multiple source structures 25. In other words, the multiple first resistance electrodes 65A are arranged alternately with the multiple source structures 25 in the second direction Y in a plan view.
  • the second resistance electrodes 65B are arranged at intervals outside the pad region 55, and each covers the second end 62 of a corresponding one of the first resistance parts 60A (second resistance parts 60B). Specifically, the second resistance electrodes 65B each cover the second end 62 of a corresponding one of the first resistance parts 60A in a film-like manner, with the second end 62 being the single object to be covered. In other words, each second resistance electrode 65B is provided in one-to-one correspondence with the second end 62 of each of the first resistance parts 60A, and is electrically connected to the second end 62.
  • Each second resistive electrode 65B exposes a region (first buried electrode 23) other than the second end 62 of the corresponding gate structure 20. That is, each second resistive electrode 65B is disposed at a distance from the first resistive electrode 65A (first end 61 of the first resistive portion 60A) toward the second end 62 of the first resistive portion 60A, and exposes the first buried electrode 23 from the inner portion of the first resistive portion 60A. That is, each second resistive electrode 65B exposes the first buried electrode 23 from the region between the corresponding first resistive electrode 65A.
  • the second resistive electrodes 65B are each formed in a strip shape extending in the first direction X in a plan view, and face each other in the second direction Y. In other words, the second resistive electrodes 65B are arranged in stripes extending along the first resistive portions 60A in a plan view.
  • the second resistive electrodes 65B are arranged at intervals in the second direction Y so as to be positioned on the same straight line extending along the second direction Y.
  • each second resistive electrode 65B is positioned on an extension of a straight line connecting the gate connection electrodes 53 on the second gate structures 20B side in the second direction Y, and faces the gate connection electrodes 53 in the second direction Y.
  • the multiple second resistance electrodes 65B may be arranged offset in the first direction X from at least one second resistance electrode 65B so as not to face at least one second resistance electrode 65B in the second direction Y. Such a configuration is effective when fine-tuning the resistance value of each first resistance section 60A.
  • the multiple second resistance electrodes 65B may be arranged offset to one side or the other side in the first direction X with respect to a straight line connecting the multiple gate connection electrodes 53 in the second direction Y so as not to face the multiple gate connection electrodes 53 in the second direction Y.
  • the multiple second resistive electrodes 65B are arranged at intervals in the second direction Y from another second resistive electrode 65B that covers the first gate structure 20A (resistive portion 60) that is not to be covered.
  • the multiple second resistive electrodes 65B are arranged at intervals in the second direction Y from the multiple source structures 25, exposing the multiple source structures 25.
  • the multiple second resistive electrodes 65B are arranged alternately with the multiple source structures 25 in the second direction Y in a plan view.
  • Each resistive electrode 65 is connected to the first buried electrode 23 in the corresponding first resistive portion 60A, and has a portion that is extended from above the first buried electrode 23 onto the main surface insulating film 50. In other words, each resistive electrode 65 is formed wider than the corresponding first resistive portion 60A in the second direction Y. Each resistive electrode 65 faces the body region 18 and source region 19 in the stacking direction in an area outside the first resistive portion 60A.
  • each resistive electrode 65 is made of the same conductive material as the corresponding first buried electrode 23, and is formed integrally with the first buried electrode 23.
  • each resistive electrode 65 includes a portion of the first buried electrode 23 that is pulled out in the form of a film into an area outside the first resistor portion 60A (above the main surface insulating film 50).
  • each resistive electrode 65 may be formed separately from the first buried electrode 23.
  • Each resistive electrode 65 has a resistive surface extending along the active surface 8.
  • each resistive electrode 65 is formed in a tapered shape (quadratic pyramid shape) from the active surface 8 toward the resistive surface in a cross-sectional view.
  • the resistive surface is preferably formed to be wider than the first resistive portion 60A in the second direction Y.
  • the resistive surface preferably has a portion facing the first resistive portion 60A in the normal direction Z, and a portion facing an area outside the first resistive portion 60A (i.e., the main surface insulating film 50) in the normal direction Z.
  • the resistive electrode 65 has a resistive thickness TR.
  • the resistive thickness TR is adjusted as appropriate according to the resistance value to be achieved. It is preferable that the resistive thickness TR is 0.5 times or more the first width W1 described above. It is preferable that the resistive thickness TR is equal to or less than the outer circumferential depth DO (second depth D2) described above. It is particularly preferable that the resistive thickness TR is less than the outer circumferential depth DO (second depth D2).
  • the resistor thickness TR is preferably equal to or less than the first depth D1 described above. Most preferably, the resistor thickness TR is less than the first depth D1.
  • the resistor thickness TR may be approximately equal to the electrode thickness TE described above.
  • the resistor thickness TR may be equal to or greater than 0.05 ⁇ m and equal to or less than 2.5 ⁇ m.
  • the resistor thickness TR is preferably equal to or greater than 0.5 ⁇ m and equal to or less than 1.5 ⁇ m.
  • the resistor thickness TR may be greater than the first depth D1.
  • the resistor thickness TR may be greater than the outer circumferential depth DO (second depth D2).
  • the resistor thickness TR may be less than the first depth D1.
  • the resistor thickness TR may be 0.1 nm or more and 100 nm or less.
  • the semiconductor device 1 includes an insulating interlayer film 70 that covers the main surface insulating film 50.
  • the interlayer film 70 may be referred to as an "insulating film,” an "interlayer insulating film,” an “intermediate insulating film,” or the like.
  • the interlayer film 70 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer film 70 include a silicon oxide film.
  • the interlayer film 70 covers the gate structure 20 (first buried electrode 23), source structure 25 (second buried electrode 28), side end structure 30 (third buried electrode 33), and termination structure 35 (fourth buried electrode 38) on the active surface 8.
  • the interlayer film 70 also covers the multiple gate connection electrodes 53 and multiple resistive electrodes 65 on the active surface 8.
  • the interlayer film 70 covers the outer well region 46, the outer contact region 47, and the multiple field regions 48 on the outer peripheral surface 9, sandwiching the main surface insulating film 50 therebetween.
  • the interlayer film 70 covers the sidewall wiring 51 on the first to fourth connection surfaces 10A to 10D.
  • the interlayer film 70 is continuous with the first to fourth side surfaces 5A to 5D.
  • the interlayer film 70 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.
  • the semiconductor device 1 includes a plurality of gate openings 71 formed in an interlayer film 70.
  • the plurality of gate openings 71 are formed in portions of the interlayer film 70 that cover the plurality of gate structures 20, and penetrate the interlayer film 70 so as to selectively expose the plurality of gate structures 20.
  • the multiple gate openings 71 are formed in the interlayer film 70 in portions that cover the multiple gate connection electrodes 53, and expose the multiple gate connection electrodes 53. In other words, the multiple gate openings 71 expose portions of the multiple gate structures 20 via the multiple gate connection electrodes 53.
  • the multiple gate openings 71 are provided in a one-to-one correspondence with the multiple gate connection electrodes 53.
  • the semiconductor device 1 includes a plurality of resistor openings 72 formed in an interlayer film 70.
  • the plurality of resistor openings 72 penetrate the interlayer film 70 so as to selectively expose a plurality of resistor portions 60 (first resistor portion 60A and second resistor portion 60B).
  • the plurality of resistor openings 72 are provided in a one-to-many correspondence with each resistor portion 60, exposing each resistor portion 60 from a plurality of locations. In other words, the plurality of resistor openings 72 are provided corresponding to one resistor portion 60.
  • the multiple resistor openings 72 are spaced apart to expose the first ends 61 and second ends 62 of the multiple resistor portions 60. Specifically, the multiple resistor openings 72 are formed in the interlayer film 70 in portions that cover the multiple resistor electrodes 65 (first resistor electrode 65A and second resistor electrode 65B), and expose the multiple resistor electrodes 65.
  • the multiple resistor openings 72 include multiple first resistor openings 72A and multiple second resistor openings 72B.
  • the multiple first resistor openings 72A are provided in a one-to-one correspondence with the first ends 61 of the multiple resistor portions 60, exposing the first ends 61 of the multiple resistor portions 60, respectively.
  • the multiple first resistor openings 72A are provided in one-to-one correspondence with the multiple first resistor electrodes 65A, and expose each of the multiple first resistor electrodes 65A.
  • each first resistor opening 72A exposes the first end 61 of the corresponding resistor portion 60 via the corresponding first resistor electrode 65A.
  • Each first resistor opening 72A exposes the inner portion of each first resistor electrode 65A at a distance from the periphery of the first resistor electrode 65A.
  • the multiple first resistor openings 72A are formed in a band shape extending in the first direction X in a plan view, and are arranged in a row at intervals in the second direction Y.
  • the multiple first resistor openings 72A may be formed in a square, polygonal, circular, or other shape.
  • the multiple first resistor openings 72A face each other in the second direction Y.
  • the multiple first resistor openings 72A may be arranged offset in the first direction X from at least one first resistor opening 72A so as not to face at least one first resistor opening 72A in the second direction Y.
  • the multiple first resistor openings 72A are formed offset to the other side of the first direction X (pad region 55 side) from a straight line connecting in the second direction Y the multiple gate openings 71 exposing the multiple gate connection electrodes 53 on the multiple second gate structures 20B side, and do not face the multiple gate openings 71 in the second direction Y.
  • a plurality of first resistor openings 72A may be provided in a one-to-many correspondence with each of the first resistor electrodes 65A.
  • a plurality of first resistor openings 72A may be provided corresponding to one first resistor electrode 65A.
  • the plurality of first resistor openings 72A are formed at intervals in the first direction X so as to expose the inner portion of one corresponding first resistor electrode 65A (resistance electrode 65) from multiple locations.
  • the multiple second resistor openings 72B are provided in one-to-one correspondence with the second ends 62 of the multiple resistor portions 60, and expose the second ends 62 of the multiple resistor portions 60 at intervals from the multiple first resistor openings 72A.
  • the multiple second resistor openings 72B are provided in one-to-one correspondence with the multiple second resistor electrodes 65B, and expose the multiple second resistor electrodes 65B.
  • each second resistor opening 72B exposes the second end 62 of the corresponding resistor portion 60 via the corresponding second resistor electrode 65B.
  • Each second resistor opening 72B exposes an inner portion of each second resistor electrode 65B at a distance from the periphery of the second resistor electrode 65B.
  • the multiple second resistor openings 72B are formed in a band shape extending in the first direction X in a plan view, and are arranged in a row at intervals in the second direction Y.
  • the multiple second resistor openings 72B may be formed in a square, polygonal, circular, or other shape.
  • the second resistor openings 72B face the first resistor openings 72A in the first direction X and face each other in the second direction Y.
  • the second resistor openings 72B may be arranged offset in the first direction X from at least one second resistor opening 72B so as not to face at least one second resistor opening 72B in the second direction Y.
  • the second resistor openings 72B are located on an extension of a straight line connecting the gate openings 71 that expose the gate connection electrodes 53 on the second gate structures 20B side in the second direction Y, and face the gate openings 71 in the second direction Y.
  • the second resistor openings 72B may be formed shifted to one side or the other side in the first direction X with respect to the straight line connecting the gate openings 71 in the second direction Y so as not to face the gate openings 71 in the second direction Y.
  • a plurality of second resistor openings 72B may be provided in a one-to-many correspondence with each second resistor electrode 65B.
  • a plurality of second resistor openings 72B may be provided corresponding to one second resistor electrode 65B.
  • the plurality of second resistor openings 72B are formed at intervals in the first direction X so as to expose the inner portion of one corresponding second resistor electrode 65B (resistance electrode 65) from multiple locations.
  • the semiconductor device 1 includes a plurality of source openings 73 formed in the interlayer film 70.
  • the plurality of source openings 73 are formed in portions of the interlayer film 70 outside the pad region 55 that cover the plurality of source structures 25, and penetrate the interlayer film 70 to selectively expose the plurality of source structures 25.
  • the plurality of source openings 73 expose the corresponding source structure 25, and the source structures 25 and contact regions 45 located on both sides of the corresponding source structure 25.
  • the multiple source openings 73 may be formed in a band shape extending along the corresponding source structures 25.
  • the multiple source openings 73 may be formed in a one-to-many correspondence with the corresponding source structures 25.
  • the multiple source openings 73 may be formed at intervals along the corresponding source structures 25.
  • the semiconductor device 1 includes an outer opening 74 formed in the interlayer film 70.
  • the outer opening 74 penetrates the main surface insulating film 50 and the interlayer film 70 so as to selectively expose the outer contact region 47 and the sidewall wiring 51.
  • the outer opening 74 is formed in a strip or ring shape extending along the outer contact region 47 and the sidewall wiring 51 so as to surround the active surface 8 (active plateau 11) in a plan view.
  • the semiconductor device 1 includes a gate electrode 80 disposed on the active surface 8 (first main surface 3). Specifically, the gate electrode 80 has a resistance value lower than the resistance values of the multiple resistor sections 60 and the multiple resistor electrodes 65, and is disposed on the interlayer film 70.
  • the gate electrode 80 includes a gate pad 81.
  • the gate pad 81 may be referred to as a "pad electrode,” “gate pad electrode,” “control pad electrode,” etc.
  • the gate pad 81 is an external terminal electrode to which a gate potential is applied from the outside.
  • the gate pad 81 is disposed on a portion of the interlayer film 70 that covers the pad region 55.
  • the gate pad 81 is disposed on the active region 12 at a distance from the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 in a plan view.
  • the gate pad 81 is also disposed in a region on one side in the second direction Y of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view.
  • the gate pad 81 is located on an imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. In other words, the gate pad 81 faces the center of the first side surface 5A (first connection surface 10A) in the second direction Y in a plan view.
  • the gate pad 81 is spaced apart from the ends of the multiple side end structures 30 in the first direction X toward the inside of the active surface 8 in a plan view, and faces the multiple side end structures 30 in the first direction X. In this embodiment, the gate pad 81 does not face the multiple side end structures 30 in the stacking direction.
  • the gate pad 81 is spaced apart from the multiple termination structures 35 in the second direction Y in a plan view, and faces the multiple termination structures 35 in the second direction Y. In this embodiment, the gate pad 81 does not face the multiple termination structures 35 in the stacking direction.
  • the gate pad 81 partially faces the multiple gate structures 20 and multiple source structures 25 across the interlayer film 70. Specifically, the gate pad 81 is arranged so as to overlap the multiple first gate structures 20A and the multiple second gate structures 20B in a plan view, but not overlap the multiple third gate structures 20C.
  • the gate pad 81 is disposed inward of the active surface 8 at a distance from both ends of the first gate structures 20A in the first direction X in a plan view.
  • the gate pad 81 covers the inner parts of the first gate structures 20A with the interlayer film 70 in between, and exposes both ends of the first gate structures 20A.
  • the gate pad 81 is disposed inward of the active surface 8 at a distance from both ends of the second gate structures 20B in the first direction X in a plan view.
  • the gate pad 81 covers the inner parts of the second gate structures 20B across the interlayer film 70, and exposes both ends of the second gate structures 20B.
  • the gate pad 81 is disposed at a distance from the third gate structures 20C in a plan view, and does not face the third gate structures 20C in the stacking direction.
  • the gate pad 81 covers the inner parts of the multiple source structures 25 with the interlayer film 70 in between, and exposes both ends of the multiple source structures 25.
  • the gate pad 81 faces the body region 18, the source region 19, the multiple first well regions 41, and the multiple second well regions 42 with the interlayer film 70 in between. In this embodiment, the gate pad 81 does not face the contact region 45. Of course, if the contact region 45 is formed in the pad region 55, the gate pad 81 may face the contact region 45.
  • the gate pad 81 is disposed on the interlayer film 70 at a horizontal distance from the gate connection electrode 53, and does not face the gate connection electrode 53 in the stacking direction. In other words, the gate pad 81 faces a portion of the gate structure 20 exposed from the gate connection electrode 53. In this embodiment, the gate pad 81 faces in the first direction X an area between at least two gate connection electrodes 53 disposed on both sides of the gate structure 20 in the first direction X in a plan view.
  • the gate pad 81 faces at least one gate connection electrode 53 arranged on the inner side of the gate structure 20 in the second direction Y in a plan view.
  • the gate pad 81 may be arranged shifted to one side or the other side of the first direction X with respect to a virtual line that crosses in the second direction Y the gate connection electrode 53 arranged on the inner side of the gate structure 20 in a plan view.
  • the gate pad 81 is disposed on the interlayer film 70 at a horizontal distance from the overlapping portion 52 of the sidewall wiring 51, and does not face the overlapping portion 52 in the stacking direction. In other words, the gate pad 81 is disposed on the area surrounded by the sidewall wiring 51 in a plan view.
  • the planar area of the gate pad 81 is less than the planar area of the active region 12 and greater than the planar area of the resistive region.
  • the proportion of the gate pad 81 in the active surface 8 is preferably 1% or more and 25% or less.
  • the proportion of the gate pad 81 may be a value belonging to any one of the following ranges: 1% or more and 5% or more, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, and 20% or more and 25% or less.
  • the proportion of the gate pad 81 is preferably 10% or less.
  • the gate pad 81 covers the first ends 61 of the resistor portions 60 at a distance from the second ends 62 of the resistor portions 60, and penetrates the interlayer film 70 to be electrically connected to the first ends 61 of the resistor portions 60. Specifically, the gate pad 81 covers the first ends 61 of the first resistor portions 60A and the first ends 61 of the second resistor portions 60B, and penetrates the interlayer film 70 to be electrically connected to the first ends 61 of the first resistor portions 60A and the first ends 61 of the second resistor portions 60B.
  • the gate pad 81 is connected to a plurality of first resistance electrodes 65A and is electrically connected to the first ends 61 of the plurality of resistance sections 60 (the plurality of first resistance sections 60A and the plurality of second resistance sections 60B) via the plurality of first resistance electrodes 65A.
  • the gate pad 81 includes a pad main body 82, a first resistor connection portion 83, and a second resistor connection portion 84.
  • the pad main body 82 is formed as the main body of the gate pad 81 in a region of the interlayer film 70 outside the region that covers the multiple resistor portions 60.
  • the pad main body 82 forms the inner portion of the gate pad 81 in a plan view, and faces the multiple gate structures 20 and the multiple source structures 25 across the interlayer film 70.
  • the pad main body 82 has a pad width WP in the first direction X that is greater than the length of the multiple resistor portions 60.
  • the pad width WP may be less than the length of the multiple resistor portions 60.
  • the pad main body 82 is formed in a quadrangular shape when viewed from above.
  • the pad main body 82 may be formed in a polygonal shape other than a quadrangle, a circular shape, etc.
  • the first resistor connection portion 83 is pulled out in the form of a film from the pad body portion 82 onto a region of the interlayer film 70 that covers the first ends 61 of the first resistor portions 60A as an electrical connection portion to the first ends 61 of the first resistor portions 60A.
  • the first resistor connection portion 83 is formed as the peripheral portion of the gate pad 81 in a plan view.
  • the first resistor connection portion 83 forms a periphery (side) that extends in the second direction Y on one side of the periphery of the gate pad 81 in the first direction X.
  • the first resistor connection portion 83 may be drawn out in a finger shape (line shape) from the pad main body portion 82 toward the area above the multiple first resistor portions 60A.
  • the first resistor connection portion 83 penetrates the multiple first resistor openings 72A from above the interlayer film 70, and is connected to the multiple first resistor electrodes 65A on the multiple first resistor portions 60A side within the multiple first resistor openings 72A.
  • the first resistor connection portion 83 penetrates the interlayer film 70 and is mechanically and electrically connected to the multiple first resistor electrodes 65A.
  • the gate pad 81 is electrically connected to the first ends 61 of the multiple first resistor portions 60A via the multiple first resistor electrodes 65A.
  • the second resistor connection portion 84 is pulled out in the form of a film from the pad body portion 82 onto a region of the interlayer film 70 that covers the first ends 61 of the second resistor portions 60B as an electrical connection portion to the first ends 61 of the second resistor portions 60B.
  • the second resistor connection portion 84 is formed as the peripheral portion of the gate pad 81 in a plan view.
  • the second resistor connection portion 84 forms a periphery (side) that extends in the second direction Y on the other side of the first direction X of the peripheral portion of the gate pad 81.
  • the second resistor connection portion 84 may be drawn out in a finger shape (line shape) from the pad main body portion 82 toward the region above the multiple second resistor portions 60B.
  • the second resistor connection portion 84 penetrates the multiple first resistor openings 72A from above the interlayer film 70, and is connected to the multiple first resistor electrodes 65A on the multiple second resistor portions 60B side within the multiple first resistor openings 72A.
  • the second resistor connection portion 84 penetrates the interlayer film 70 and is mechanically and electrically connected to the multiple first resistor electrodes 65A.
  • the gate pad 81 is electrically connected to the first ends 61 of the multiple second resistor portions 60B via the multiple first resistor electrodes 65A.
  • the gate electrode 80 includes a gate wiring 85 disposed on the interlayer film 70 at a distance from the gate pad 81.
  • the gate wiring 85 may be referred to as a "wiring electrode,” a “gate wiring electrode,” a “control wiring electrode,” or the like.
  • the gate wiring 85 has a resistance value lower than the resistance values of the multiple resistor sections 60 and the multiple resistive electrodes 65.
  • the gate wiring 85 is disposed on a portion of the interlayer film 70 that covers the active surface 8, and is selectively routed within the active region 12.
  • the gate wiring 85 is spaced inward from the periphery of the active surface 8 and is not disposed on the outer periphery 9.
  • the gate wiring 85 is electrically connected to the resistor portions 60 of the first gate structures 20A at positions in the active region 12 that are different from the gate pad 81, and is electrically connected to the gate pad 81 via the resistor portions 60.
  • the gate wiring 85 is spaced apart from the first ends 61 of the multiple resistor sections 60 and penetrates the interlayer film 70 to be electrically connected to the second ends 62 of the multiple resistor sections 60.
  • the gate wiring 85 is mechanically and electrically connected to the multiple second resistor electrodes 65B. That is, the gate wiring 85 is electrically connected to the second ends 62 of the multiple resistor sections 60 via the multiple second resistor electrodes 65B.
  • the gate wiring 85 is routed from an area above the multiple resistor portions 60 to an area outside the multiple resistor portions 60, and is also electrically connected to the portions of the multiple first gate structures 20A that are outside the multiple resistor portions 60. Furthermore, the gate wiring 85 is electrically connected to the multiple second gate structures 20B and the multiple third gate structures 20C in addition to the multiple first gate structures 20A.
  • the gate wiring 85 transmits the gate potential applied to the gate pad 81 to the first gate structures 20A, the second gate structures 20B, and the third gate structures 20C.
  • the gate wiring 85 extends in a line shape so as to intersect (specifically, perpendicular to) the first gate structures 20A, the second gate structures 20B, and the third gate structures 20C, and penetrates the interlayer film 70 to be electrically connected to the first gate structures 20A, the second gate structures 20B, and the third gate structures 20C.
  • the gate wiring 85 is electrically connected to a plurality of first gate structures 20A and a plurality of second gate structures 20B located directly below the gate pad 81, as well as a plurality of third gate structures 20C located outside directly below the gate pad 81.
  • the gate wiring 85 is electrically connected to the first gate structure 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C via a plurality of gate connection electrodes 53.
  • the gate wiring 85 includes a first resistance wiring 86, a second resistance wiring 87, a first connection wiring 88, a second connection wiring 89, a first line wiring 90, a second line wiring 91, and a third line wiring 92.
  • the first resistance wiring 86 is provided as an electrical connection part for the second ends 62 of the multiple first resistance parts 60A.
  • the first resistance wiring 86 is disposed on the interlayer film 70 at a distance from the gate pad 81 on one side in the first direction X, and is formed in a line shape extending in the second direction Y.
  • the first resistance wiring 86 has a base end on one side in the second direction Y and a tip end on the other side in the second direction Y.
  • the base end of the first resistance wiring 86 protrudes further on one side in the second direction Y than the gate pad 81.
  • the tip end of the first resistance wiring 86 protrudes further on the other side in the second direction Y than the gate pad 81.
  • the first resistance wiring 86 intersects (specifically, perpendicular to) the multiple first gate structures 20A and the multiple second gate structures 20B. Specifically, the first resistance wiring 86 intersects (specifically, perpendicular to) the second ends 62 of the multiple first resistance portions 60A. The first resistance wiring 86 penetrates from above the interlayer film 70 into the multiple gate openings 71 and the multiple second resistance openings 72B.
  • the first resistance wiring 86 is mechanically and electrically connected to the gate connection electrodes 53 of the second gate structures 20B within the gate openings 71. As a result, the first resistance wiring 86 is electrically connected to the second gate structures 20B via the gate connection electrodes 53.
  • the first resistance wiring 86 is mechanically and electrically connected to the second resistance electrodes 65B within the second resistance openings 72B. As a result, the first resistance wiring 86 is electrically connected to the first gate structures 20A via the first resistance portions 60A, and is electrically connected to the gate pad 81 via the first resistance portions 60A.
  • the first resistance wiring 86 connects the multiple first resistance parts 60A in parallel between the gate pad 81.
  • the first resistance wiring 86 electrically connects the multiple first gate structures 20A and the multiple second gate structures 20B to the gate pad 81 via a parallel circuit of the multiple first resistance parts 60A.
  • the first resistance wiring 86 may cross (specifically, be perpendicular to) at least one (one or more) third gate structures 20C.
  • the first resistance wiring 86 may be mechanically and electrically connected to multiple gate connection electrodes 53 of at least one (one or more) third gate structures 20C within at least one (one or more) gate openings 71.
  • the second resistance wiring 87 is provided as an electrical connection to the second ends 62 of the multiple second resistance parts 60B.
  • the second resistance wiring 87 is disposed on the interlayer film 70 at a distance from the gate pad 81 to the other side in the first direction X, and is formed in a line extending in the second direction Y.
  • the second resistive wiring 87 has a base end on one side in the second direction Y and a tip end on the other side in the second direction Y.
  • the base end of the second resistive wiring 87 protrudes further on one side in the second direction Y than the gate pad 81.
  • the tip end of the second resistive wiring 87 protrudes further on the other side in the second direction Y than the gate pad 81.
  • the second resistance wiring 87 intersects (specifically, perpendicular to) the multiple first gate structures 20A and the multiple second gate structures 20B. Specifically, the second resistance wiring 87 intersects (specifically, perpendicular to) the second ends 62 of the multiple second resistance portions 60B. The second resistance wiring 87 penetrates from above the interlayer film 70 into the multiple second resistance openings 72B and the multiple gate openings 71.
  • the second resistance wiring 87 is mechanically and electrically connected to the gate connection electrodes 53 of the second gate structures 20B within the gate openings 71. As a result, the second resistance wiring 87 is electrically connected to the second gate structures 20B via the gate connection electrodes 53.
  • the second resistance wiring 87 is mechanically and electrically connected to the multiple second resistance electrodes 65B within the multiple second resistance openings 72B. As a result, the second resistance wiring 87 is electrically connected to the multiple first gate structures 20A via the multiple second resistance portions 60B, and is electrically connected to the gate pad 81 via the multiple second resistance portions 60B.
  • the second resistance wiring 87 connects the multiple second resistance parts 60B in parallel between the gate pad 81.
  • the second resistance wiring 87 electrically connects the multiple first gate structures 20A and the multiple second gate structures 20B to the gate pad 81 via a parallel circuit of the multiple second resistance parts 60B.
  • the second resistive wiring 87 may cross (specifically, be perpendicular to) at least one (one or more) third gate structures 20C.
  • the second resistive wiring 87 may be mechanically and electrically connected to multiple gate connection electrodes 53 of at least one (one or more) third gate structures 20C within at least one (one or more) gate openings 71.
  • the first connection wiring 88 is disposed on the other side (the second side surface 5B side) of the gate pad 81 in the second direction Y.
  • the first connection wiring 88 extends in a line in the first direction X through the region between the tip of the first resistance wiring 86 and the tip of the second resistance wiring 87, and mechanically and electrically connects the tip of the first resistance wiring 86 and the tip of the second resistance wiring 87.
  • the first connection wiring 88 electrically connects the multiple first resistance parts 60A and the multiple second resistance parts 60B. Specifically, the first connection wiring 88 connects in parallel a parallel circuit including the multiple first resistance parts 60A and a parallel circuit including the multiple second resistance parts 60B between the gate pad 81. In this embodiment, the first connection wiring 88 covers the multiple gate structures 20 (third gate structure 20C) and the multiple source structures 25.
  • the second connection wiring 89 is disposed on one side of the gate pad 81 in the second direction Y (the side of the first side surface 5A) and faces the first connection wiring 88 across the gate pad 81.
  • the second connection wiring 89 extends in a line in the first direction X through the region between the base end of the first resistance wiring 86 and the base end of the second resistance wiring 87, and mechanically and electrically connects the base end of the first resistance wiring 86 and the base end of the second resistance wiring 87.
  • the second connection wiring 89 electrically connects the multiple first resistance parts 60A and the multiple second resistance parts 60B. Specifically, the second connection wiring 89 connects in parallel a parallel circuit including the multiple first resistance parts 60A and a parallel circuit including the multiple second resistance parts 60B between the gate pad 81. In this embodiment, the second connection wiring 89 covers the multiple termination structures 35. Of course, the second connection wiring 89 may cover either one or both of at least one gate structure 20 and at least one source structure 25. The second connection wiring 89 does not necessarily have to be provided and may be removed as necessary.
  • the first line wiring 90 is pulled out from the first resistance wiring 86 to one side in the first direction X, and is electrically connected to the second ends 62 of the multiple first resistance parts 60A via the first resistance wiring 86.
  • the first line wiring 90 has a first extension portion 90a and a second extension portion 90b.
  • the first extension portion 90a is pulled out in a line shape from the base end of the first resistance wiring 86 to one side in the first direction X, and faces the multiple termination structures 35 across the interlayer film 70.
  • the first extension 90a may cover either one or both of at least one gate structure 20 and at least one source structure 25.
  • the tip of the first extension 90a is formed at a distance from the third connection surface 10C inwardly of the active surface 8 in a plan view.
  • the tip of the first extension 90a may be formed at a distance from the end positions of the multiple side end structures 30 in the first direction X inwardly of the active surface 8.
  • the tip of the first extension 90a may be drawn out to a portion facing the multiple side end structures 30 in the second direction Y.
  • the second extension portion 90b is pulled out from the tip of the first extension portion 90a in the second direction Y and extends in a line along the third side surface 5C (third connection surface 10C).
  • the second extension portion 90b intersects (specifically, perpendicular to) one end of the multiple gate structures 20 and one end of the multiple source structures 25 in the second direction Y.
  • the second extension portion 90b intersects (specifically, perpendicular to) one end of the multiple first gate structures 20A, one end of the multiple second gate structures 20B, one end of the multiple third gate structures 20C, and one end of the multiple source structures 25.
  • the second extension portion 90b is formed at a distance inward from the end positions of the multiple side end structures 30 in the first direction X in a plan view, toward the active surface 8, and does not face the multiple side end structures 30 in the stacking direction.
  • a portion of the second extension portion 90b may be drawn out from the active region 12 to the first side end region 13 and face the multiple side end structures 30 in the stacking direction.
  • the tip portion of the second extension portion 90b may be located above the active region 12 or above the second termination region 16.
  • the second extension 90b penetrates into the multiple gate openings 71 from above the interlayer film 70, and is electrically connected to one end of the multiple gate structures 20 within the multiple gate openings 71. Specifically, the second extension 90b is electrically connected to one end of the multiple first gate structures 20A, one end of the multiple second gate structures 20B, and one end of the multiple third gate structures 20C. In other words, the second extension 90b is electrically connected to one end of the multiple first gate structures 20A and one end of the multiple second gate structures 20B located directly below the gate pad 81.
  • the second extension 90b is mechanically and electrically connected to the multiple gate connection electrodes 53 within the multiple gate openings 71. As a result, the second extension 90b is electrically connected to one end of the multiple gate structures 20 via the multiple gate connection electrodes 53. In this way, the first line wiring 90 electrically connects the multiple first gate structures 20A, the multiple second gate structures 20B, and the multiple third gate structures 20C to the gate pad 81 via the multiple first resistance portions 60A and the multiple second resistance portions 60B.
  • the second line wiring 91 is pulled out from the second resistive wiring 87 to the other side in the first direction X, and is electrically connected to the second ends 62 of the multiple second resistive parts 60B via the second resistive wiring 87.
  • the second line wiring 91 has a third extension portion 91a and a fourth extension portion 91b.
  • the third extension portion 91a is pulled out in a line shape from the base end of the second resistive wiring 87 to the other side in the first direction X, and faces the multiple termination structures 35 across the interlayer film 70.
  • the third extension 91a may cover either one or both of at least one gate structure 20 and at least one source structure 25.
  • the tip of the third extension 91a is formed at a distance from the fourth connection surface 10D inwardly of the active surface 8 in a plan view.
  • the tip of the third extension 91a may be formed at a distance from the end positions of the multiple side end structures 30 in the first direction X inwardly of the active surface 8.
  • the tip of the third extension 91a may be drawn out to a portion facing the multiple side end structures 30 in the second direction Y.
  • the fourth extension portion 91b is pulled out from the tip of the third extension portion 91a in the second direction Y and extends in a line along the fourth side surface 5D (fourth connection surface 10D).
  • the fourth extension portion 91b intersects (specifically, perpendicular to) the other ends of the multiple gate structures 20 and the other ends of the multiple source structures 25 in the second direction Y.
  • the fourth extension portion 91b intersects (specifically, perpendicular to) the other ends of the multiple first gate structures 20A, the other ends of the multiple second gate structures 20B, the other ends of the multiple third gate structures 20C, and the other ends of the multiple source structures 25.
  • the fourth extension 91b is formed at a distance inward from the end positions of the multiple side end structures 30 in the first direction X in a plan view, toward the active surface 8, and does not face the multiple side end structures 30 in the stacking direction.
  • a portion of the fourth extension 91b may be drawn out from the active region 12 to the second side end region 14 and face the multiple side end structures 30 in the stacking direction.
  • the tip of the fourth extension 91b may be located above the active region 12 or above the second termination region 16.
  • the fourth extension 91b penetrates into the multiple gate openings 71 from above the interlayer film 70, and is electrically connected to the other ends of the multiple gate structures 20 within the multiple gate openings 71. Specifically, the fourth extension 91b is electrically connected to the other ends of the multiple first gate structures 20A, the other ends of the multiple second gate structures 20B, and the other ends of the multiple third gate structures 20C. In other words, the fourth extension 91b is electrically connected to the other ends of the multiple first gate structures 20A and the other ends of the multiple second gate structures 20B located directly below the gate pad 81.
  • the fourth extension 91b is mechanically and electrically connected to the multiple gate connection electrodes 53 within the multiple gate openings 71. As a result, the fourth extension 91b is electrically connected to the other ends of the multiple gate structures 20 via the multiple gate connection electrodes 53. In this way, the second line wiring 91 electrically connects the multiple first gate structures 20A, the multiple second gate structures 20B, and the multiple third gate structures 20C to the gate pad 81 via the multiple first resistance portions 60A and the multiple second resistance portions 60B.
  • the third line wiring 92 is disposed in a region on the other side (second side surface 5B side) of the gate pad 81 in the second direction Y, and extends in a line shape along the second direction Y in the region between the gate pad 81 and the second connection surface 10B.
  • the third line wiring 92 is drawn out from the first connection wiring 88 toward the inner part of the active region 12, and is electrically connected to the multiple first resistance parts 60A and the multiple second resistance parts 60B via the first resistance wiring 86, the second resistance wiring 87, and the first connection wiring 88.
  • the third line wiring 92 is electrically connected to the gate pad 81 via the multiple first resistance parts 60A and the multiple second resistance parts 60B.
  • the third line wiring 92 crosses (specifically, perpendicularly) the inner parts of the multiple gate structures 20 and the inner parts of the multiple source structures 25 in a plan view. Specifically, the third line wiring 92 crosses (specifically, perpendicularly) the multiple third gate structures 20C.
  • the third line wiring 92 enters the multiple gate openings 71 from above the interlayer film 70 and is electrically connected to the inner parts of the multiple third gate structures 20C within the multiple gate openings 71.
  • the third line wiring 92 is connected to the multiple gate connection electrodes 53 within the multiple gate openings 71, and is electrically connected to the inner parts of the multiple third gate structures 20C via the multiple gate connection electrodes 53. In this way, the third line wiring 92 electrically connects the multiple third gate structures 20C to the gate pad 81 via the multiple first resistance portions 60A and the multiple second resistance portions 60B.
  • the gate electrode 80 includes a gate subpad 93 disposed on the interlayer film 70 at a distance from the gate pad 81.
  • the gate subpad 93 may be referred to as a "subpad electrode” or the like.
  • the presence or absence of the gate subpad 93 is optional, and it may be omitted as necessary.
  • the gate subpad 93 has a planar area less than the planar area of the gate pad 81.
  • the gate subpad 93 is formed narrower than the gate pad 81 in the second direction Y, and wider than the first resistance wiring 86 (second resistance wiring 87) in the first direction X.
  • the gate subpad 93 is an electrical test pad (dummy pad) for measuring the gate resistance RG during the manufacturing process, and is electrically connected to the gate pad 81 via a plurality of resistor portions 60 (a plurality of first resistor portions 60A and a plurality of second resistor portions 60B). In the electrical test, a test signal is applied between the gate pad 81 and the gate subpad 93.
  • a gate potential may be applied to either the gate pad 81 or the gate subpad 93, and a ground potential may be applied to the other.
  • the gate subpad 93 is a terminal to which a potential different from that of the gate pad 81 is applied.
  • the gate subpad 93 is an open terminal after the manufacturing process, and is excluded from the targets for connection of conductive bonding members such as bonding wires.
  • the entire gate subpad 93 is directly or indirectly covered with an insulator (e.g., a sealing resin containing multiple fillers and a matrix resin) and is electrically insulated from other structures.
  • an insulator e.g., a sealing resin containing multiple fillers and a matrix resin
  • the gate subpad 93 may be electrically connected to a lead terminal of the semiconductor package via a bonding wire or the like, and configured so that a test signal can be input even after the semiconductor device 1 is mounted on the semiconductor package.
  • the gate subpad 93 may be disposed at any location.
  • the gate subpad 93 may be disposed on at least one of the active region 12, the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, and the outer periphery region 17.
  • the gate subpad 93 is disposed on the active region 12 at a distance from the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 in a plan view.
  • the gate subpad 93 is disposed at a distance from the gate pad 81 to one side in the first direction X (toward the third connection surface 10C) and faces the gate pad 81 in the first direction X.
  • the gate subpad 93 is disposed in an area on one side in the second direction Y (toward the first side surface 5A) of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view.
  • the gate subpad 93 is disposed shifted to one side or the other in the first direction X with respect to an imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.
  • the gate subpad 93 partially faces the multiple gate structures 20 and multiple source structures 25 across the interlayer film 70.
  • the gate subpad 93 is disposed inwardly of the active surface 8 at a distance from the ends of the multiple side end structures 30 in the first direction X in a plan view, and faces the multiple side end structures 30 in the first direction X.
  • the gate subpad 93 does not face the multiple side end structures 30 in the stacking direction.
  • the gate subpad 93 is disposed inward of the active surface 8 at a distance from both ends of the multiple gate structures 20 in the first direction X in a plan view.
  • the gate subpad 93 covers the inner parts of the multiple gate structures 20 with the interlayer film 70 in between, exposing both ends of the multiple gate structures 20.
  • the gate subpad 93 covers the inner parts of the multiple source structures 25 with the interlayer film 70 in between, exposing both ends of the multiple source structures 25.
  • the gate subpad 93 faces the body region 18, the source region 19, the multiple first well regions 41, and the multiple second well regions 42 across the interlayer film 70.
  • the gate subpad 93 may face the multiple contact regions 45 across the interlayer film 70.
  • the gate subpad 93 is disposed on the interlayer film 70 at a horizontal distance from the gate connection electrode 53, and does not face the gate connection electrode 53 in the stacking direction. In other words, the gate subpad 93 faces the portion of the gate structure 20 exposed from the gate connection electrode 53.
  • the gate subpad 93 is disposed on the interlayer film 70 at a horizontal distance from the overlapping portion 52 of the sidewall wiring 51, and does not face the overlapping portion 52 in the stacking direction. In other words, the gate subpad 93 is disposed on the area surrounded by the sidewall wiring 51 in a plan view.
  • the gate subpad 93 is connected to the gate wiring 85 and is electrically connected to the multiple gate structures 20, the multiple resistance portions 60, and the gate pad 81 via the gate wiring 85.
  • the gate subpad 93 is connected to a portion of the gate wiring 85 that is located near the multiple resistance portions 60.
  • the gate subpad 93 is preferably connected to the first resistance wiring 86, the second resistance wiring 87, the first connection wiring 88, the second connection wiring 89, etc.
  • the gate subpad 93 is connected to the first resistance wiring 86.
  • the gate subpad 93 overlaps a plurality of second gate structures 20B, but does not overlap a plurality of third gate structures 20C.
  • the gate subpad 93 may overlap some or all of the first gate structures 20A.
  • the gate subpad 93 may overlap at least one third gate structure 20C.
  • the gate electrode 80 preferably has a thickness greater than that of the resistive electrode 65 (the thickness of the gate connection electrode 53).
  • the thickness of the gate electrode 80 is preferably greater than that of the interlayer film 70.
  • the thickness of the gate electrode 80 may be 0.5 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the gate electrode 80 is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the gate electrode 80 has a layered structure including a first electrode film 94 and a second electrode film 95, which are layered in this order from the interlayer film 70 side.
  • the first electrode film 94 is formed as a barrier electrode.
  • the first electrode film 94 includes at least one of a Ti film, a TiN film, and a W film.
  • the first electrode film 94 includes a Ti film.
  • the second electrode film 95 has a thickness greater than that of the first electrode film 94, and forms the main body of the gate electrode 80.
  • the second electrode film 95 includes at least one of an Al film, a Cu film, an Al alloy film, and a Cu alloy film.
  • the second electrode film 95 may include at least one of a pure Cu film (a Cu film having a purity of 99% or more), a pure Al film (an Al film having a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the second electrode film 95 includes an Al alloy film (an AlSiCu alloy film in this embodiment).
  • the first electrode film 94 of the gate pad 81 covers the interlayer film 70 in the pad body 82, and penetrates into the first resistor openings 72A from above the interlayer film 70 in the first resistor connection portion 83 (second resistor connection portion 84).
  • the first electrode film 94 of the gate pad 81 covers the opening walls of the first resistor openings 72A in a film-like manner, and covers the first resistor electrodes 65A in a film-like manner.
  • the second electrode film 95 of the gate pad 81 covers the first electrode film 94 in the pad body 82 in a film-like manner, and faces the interlayer film 70 with the first electrode film 94 in between.
  • the second electrode film 95 of the gate pad 81 covers the first electrode film 94 in a film-like manner in the first resistor connection portion 83 (second resistor connection portion 84), and backfills the multiple first resistor openings 72A.
  • the second electrode film 95 of the gate pad 81 is electrically connected to the multiple first resistor electrodes 65A via the first electrode film 94 in the multiple first resistor openings 72A.
  • the first electrode film 94 of the gate wiring 85 covers the interlayer film 70 in a film-like manner, and penetrates into the multiple gate openings 71 and multiple second resistor openings 72B from above the interlayer film 70.
  • the first electrode film 94 of the gate wiring 85 covers the opening wall surfaces of the multiple gate openings 71 in a film-like manner, and covers the multiple gate connection electrodes 53 in a film-like manner.
  • the first electrode film 94 of the gate wiring 85 covers the opening wall surfaces of the multiple second resistor openings 72B in a film-like manner, and covers the multiple second resistor electrodes 65B in a film-like manner.
  • the second electrode film 95 of the gate wiring 85 backfills the multiple gate openings 71 and multiple second resistor openings 72B with the first electrode film 94 of the gate wiring 85 in between, and covers the first electrode film 94 in a film-like manner on the interlayer film 70.
  • the second electrode film 95 of the gate wiring 85 is electrically connected to the multiple gate connection electrodes 53 and multiple second resistor electrodes 65B via the first electrode film 94.
  • the semiconductor device 1 includes a source electrode 100 disposed on the interlayer film 70 at a distance from the gate electrode 80.
  • the source electrode 100 has a resistance value lower than the resistance values of the multiple resistor sections 60 and the multiple resistor electrodes 65.
  • the source electrode 100 includes at least one (multiple in this embodiment) source pad 101.
  • the source pad 101 may be referred to as a "low potential pad electrode,” “source pad electrode,” “channel pad,” “different potential pad,” etc.
  • the source pad 101 includes a first source pad 101A and a second source pad 101B.
  • the first source pad 101A is disposed in a region on one side of the first direction X on a portion of the interlayer film 70 that covers the active region 12. Specifically, the first source pad 101A is disposed in a region on one side of the first direction X that is partitioned by the gate wiring 85 (the first line wiring 90 and the third line wiring 92).
  • the first source pad 101A has a planar area smaller than the planar area of the active region 12.
  • the planar area of the first source pad 101A is larger than the planar area of the gate pad 81. It is preferable that the proportion of the first source pad 101A in the active surface 8 (first main surface 3) is 25% or more and 50% or less.
  • the first source pad 101A is disposed on the active region 12 at a distance from the first side end region 13 in a plan view. In other words, the first source pad 101A is disposed at a distance inward from the end positions of the multiple side end structures 30 in the first direction X on the active surface 8 in a plan view, and faces the multiple side end structures 30 in the first direction X. The first source pad 101A does not face the multiple side end structures 30 in the stacking direction.
  • the first source pad 101A partially faces the multiple gate structures 20 and the multiple source structures 25 across the interlayer film 70.
  • the first source pad 101A is disposed at a distance inward from the positions of both ends of the multiple gate structures 20 in the first direction X in a plan view, toward the inside of the active surface 8.
  • the first source pad 101A covers the inner parts of the multiple gate structures 20 with the interlayer film 70 in between, and exposes one end of the multiple gate structures 20.
  • the first source pad 101A covers the inner parts of the multiple source structures 25 with the interlayer film 70 in between, and exposes one end of the multiple source structures 25.
  • the first source pad 101A extends into the multiple source openings 73 from above the interlayer film 70, and is electrically connected to the multiple source structures 25, source regions 19, and multiple contact regions 45 within the multiple source openings 73.
  • the first source pad 101A includes a first pad portion 101a and a second pad portion 101b.
  • a source potential for the main source may be applied to the first pad portion 101a from the outside.
  • a source potential for source sensing may be applied to the second pad portion 101b from the outside.
  • a source potential for the main source may be applied to the second pad portion 101b.
  • the first pad portion 101a is located in a region on the other side (second side surface 5B side) of the gate pad 81 in the second direction Y, and faces the gate pad 81 in the second direction Y.
  • the first pad portion 101a covers the multiple third gate structures 20C, and is electrically connected to the multiple source structures 25, source regions 19, and multiple contact regions 45 adjacent to the multiple third gate structures 20C.
  • the second pad portion 101b is located in an area on one side (the third side surface 5C side) of the gate pad 81 in the first direction X, and faces the gate pad 81 in the first direction X. Specifically, the second pad portion 101b faces the gate pad 81 in the first direction X, sandwiching a part of the gate wiring 85 (the first resistance wiring 86) therebetween.
  • the second pad portion 101b faces the gate pad 81 across the gate subpad 93 in a plan view.
  • the portion of the second pad portion 101b that is along the gate subpad 93 is recessed in a rectangular shape along the gate subpad 93 in a plan view.
  • the second pad portion 101b may be extended from the active region 12 to the first termination region 15 and cover at least one termination structure 35.
  • the second pad portion 101b covers at least one (in this embodiment, multiple) first gate structures 20A.
  • the second pad portion 101b may cover all of the first gate structures 20A, or may cover only a portion of the first gate structures 20A.
  • the second pad portion 101b is electrically connected to at least one (in this embodiment, multiple) source structure 25, source region 19, and multiple contact regions 45 adjacent to at least one (in this embodiment, multiple) first gate structure 20A.
  • the second pad portion 101b also covers at least one (in this embodiment, multiple) second gate structures 20B.
  • the second pad portion 101b may cover all of the second gate structures 20B, or may cover a portion of the second gate structures 20B.
  • the second pad portion 101b is electrically connected to at least one (in this embodiment, multiple) source structure 25, source region 19, and multiple contact regions 45 adjacent to at least one (in this embodiment, multiple) second gate structure 20B. In this manner, the second pad portion 101b is electrically connected to multiple source structures 25 arranged directly below the gate pad 81.
  • the second source pad 101B is disposed in the region on the other side of the first direction X on the portion of the interlayer film 70 that covers the active region 12. Specifically, the second source pad 101B is disposed in a region on the other side of the first direction X that is partitioned by the gate wiring 85 (the second line wiring 91 and the third line wiring 92), and faces the first source pad 101A across a portion of the gate wiring 85 in the first direction X.
  • the second source pad 101B has a planar area smaller than the planar area of the active region 12.
  • the planar area of the second source pad 101B is larger than the planar area of the gate pad 81. It is preferable that the proportion of the second source pad 101B in the active surface 8 (first main surface 3) is 25% or more and 50% or less.
  • the second source pad 101B is disposed on the active region 12 at a distance from the second side end region 14 in a plan view.
  • the second source pad 101B is disposed at a distance inward from the ends of the multiple side end structures 30 in the first direction X on the active surface 8 in a plan view, and faces the multiple side end structures 30 in the first direction X.
  • the second source pad 101B does not face the multiple side end structures 30 in the stacking direction.
  • the second source pad 101B partially faces the multiple gate structures 20 and the multiple source structures 25 across the interlayer film 70.
  • the second source pad 101B is disposed at a distance inward from both ends of the multiple gate structures 20 in the first direction X in a plan view, toward the inside of the active surface 8.
  • the second source pad 101B covers the inner parts of the multiple gate structures 20 with the interlayer film 70 in between, and exposes the other ends of the multiple gate structures 20.
  • the second source pad 101B covers the inner parts of the multiple source structures 25 with the interlayer film 70 in between, and exposes the other ends of the multiple source structures 25.
  • the second source pad 101B extends into the multiple source openings 73 from above the interlayer film 70, and is electrically connected to the multiple source structures 25, source regions 19, and multiple contact regions 45 within the multiple source openings 73.
  • the second source pad 101B includes a third pad portion 101c and a fourth pad portion 101d.
  • a source potential for the main source may be applied to the third pad portion 101c from the outside.
  • a source potential for source sensing may be applied to the fourth pad portion 101d from the outside.
  • a source potential for the main source may be applied to the fourth pad portion 101d.
  • the third pad portion 101c is located in a region on the other side (second side surface 5B side) of the gate pad 81 in the second direction Y, faces the first pad portion 101a in the first direction X, and faces the gate pad 81 in the second direction Y.
  • the third pad portion 101c covers the multiple third gate structures 20C, and is electrically connected to the multiple source structures 25, source regions 19, and contact regions 45 adjacent to the multiple third gate structures 20C.
  • the fourth pad portion 101d is located in a region on the other side (fourth side surface 5D side) of the gate pad 81 in the first direction X, and faces the second pad portion 101b across the gate pad 81 in the first direction X. Specifically, the fourth pad portion 101d faces the gate pad 81 in the first direction X across a part of the gate wiring 85 (second resistance wiring 87).
  • the fourth pad portion 101d may be drawn out from the active region 12 to the first termination region 15 and cover at least one termination structure 35.
  • the fourth pad portion 101d covers at least one (in this embodiment, multiple) first gate structures 20A.
  • the fourth pad portion 101d may cover all of the first gate structures 20A, or may cover only a portion of the first gate structures 20A.
  • the fourth pad portion 101d is electrically connected to at least one (in this embodiment, multiple) source structure 25, source region 19, and multiple contact regions 45 adjacent to at least one (in this embodiment, multiple) first gate structure 20A.
  • the fourth pad portion 101d covers at least one (in this embodiment, multiple) second gate structures 20B.
  • the fourth pad portion 101d may cover all of the second gate structures 20B, or may cover a portion of the second gate structures 20B.
  • the fourth pad portion 101d is electrically connected to at least one (in this embodiment, multiple) source structure 25, source region 19, and multiple contact regions 45 adjacent to at least one (in this embodiment, multiple) second gate structure 20B. In this manner, the fourth pad portion 101d is electrically connected to multiple source structures 25 arranged directly below the gate pad 81.
  • the source electrode 100 includes a source wiring 102.
  • the source wiring 102 may be referred to as a "low potential wiring electrode,” “source wiring electrode,” “channel wiring,” “different potential wiring,” etc.
  • the source wiring 102 transmits the source potential applied to the source pad 101 to other regions.
  • the source wiring 102 is drawn out from the source pad 101 onto the interlayer film 70 so as to be located closer to the outer peripheral region 17 than the gate wiring 85.
  • the source wiring 102 is drawn out from the active surface 8 side to the outer peripheral surface 9 side, passing through the first to fourth connection surfaces 10A to 10D.
  • the source wiring 102 is formed in a strip shape extending along the first to fourth connection surfaces 10A to 10D, and faces the sidewall wiring 51 across the interlayer film 70.
  • the source wiring 102 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 10A to 10D.
  • the source wiring 102 covers the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 on the active surface 8, and surrounds the active region 12. In other words, the source wiring 102 surrounds the gate pad 81, the gate wiring 85, and the multiple source pads 101.
  • the source wiring 102 enters the outer opening 74 from above the interlayer film 70 in the peripheral region 17, and is electrically connected to the outer contact region 47 and the sidewall wiring 51 within the outer opening 74.
  • the source potential applied to the source pad 101 is transmitted to the sidewall wiring 51 via the source wiring 102.
  • the source potential applied to the sidewall wiring 51 is transmitted from the peripheral region 17 to the multiple source structures 25, the multiple side end structures 30, and the multiple termination structures 35.
  • the source electrode 100 preferably has a thickness greater than that of the resistive electrode 65 (the thickness of the gate connection electrode 53).
  • the thickness of the source electrode 100 is preferably greater than that of the interlayer film 70.
  • the thickness of the source electrode 100 is preferably approximately equal to that of the gate electrode 80.
  • the thickness of the source electrode 100 may be 0.5 ⁇ m or more and 10 ⁇ m or less.
  • the thickness of the source electrode 100 is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the source electrode 100 has a laminated structure including a first electrode film 103 and a second electrode film 104 laminated in this order from the interlayer film 70 side.
  • the first electrode film 103 is formed as a barrier electrode.
  • the first electrode film 103 includes at least one of a Ti film, a TiN film, and a W film.
  • the first electrode film 103 includes a Ti film. It is preferable that the first electrode film 103 has a thickness approximately equal to that of the first electrode film 94 of the gate electrode 80.
  • the second electrode film 104 has a thickness greater than that of the first electrode film 103, and forms the body of the source electrode 100. It is preferable that the second electrode film 104 has a thickness approximately equal to that of the second electrode film 95 of the gate electrode 80.
  • the second electrode film 104 includes at least one of an Al film, a Cu film, an Al alloy film, and a Cu alloy film.
  • the second electrode film 104 may include at least one of a pure Cu film (a Cu film having a purity of 99% or more), a pure Al film (an Al film having a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.
  • the second electrode film 104 includes an Al alloy film (an AlSiCu alloy film in this embodiment).
  • the semiconductor device 1 includes a pad insulating film 110 that selectively covers the gate electrode 80, the source electrode 100, and the interlayer film 70. With respect to the gate electrode 80, the pad insulating film 110 covers the periphery of the gate pad 81, the periphery of the gate subpad 93, and the entire area of the gate wiring 85.
  • the pad insulating film 110 covers the first resistor connection portion 83 and the second resistor connection portion 84 of the gate pad 81. In other words, the pad insulating film 110 covers the connection portions of the gate pad 81 to the multiple resistor portions 60 (the multiple first resistor electrodes 65A and the multiple second resistor electrodes 65B).
  • the pad insulating film 110 also covers the first resistive wiring 86 and the second resistive wiring 87 of the gate wiring 85. In other words, the pad insulating film 110 covers the connection portions of the gate wiring 85 to the multiple resistive sections 60 (the multiple first resistive electrodes 65A and the multiple second resistive electrodes 65B).
  • the pad insulating film 110 also covers the gap portion of the interlayer film 70 exposed from the region between the gate pad 81 and the gate wiring 85, and has a portion that covers the multiple resistor portions 60 across the gap portion. It is preferable that the pad insulating film 110 covers the entire area of the multiple resistor portions 60 in a plan view.
  • the pad insulating film 110 has a gate pad opening 111 that exposes the inner part of the gate pad 81.
  • the gate pad opening 111 exposes the area of the gate pad 81 other than the first resistor connection part 83 and the second resistor connection part 84. In other words, the gate pad opening 111 exposes the pad body part 82 of the gate pad 81.
  • the gate pad opening 111 is formed in a quadrangle shape in a plan view.
  • the gate pad opening 111 may be formed in a polygonal shape other than a quadrangle, a circle, etc. in a plan view.
  • the pad insulating film 110 has a gate subpad opening 112 that exposes the inner portion of the gate subpad 93.
  • the gate subpad opening 112 is formed in a rectangular shape in a plan view, and has a plan area that is less than the plan area of the gate pad opening 111.
  • the gate subpad opening 112 may be formed in a polygonal shape other than a rectangular shape, a circular shape, etc. in a plan view.
  • the pad insulating film 110 covers the periphery of the first source pad 101A, the periphery of the second source pad 101B, and the entire area of the source wiring 102.
  • the pad insulating film 110 includes a first source pad opening 113 exposing the first pad portion 101a, a second source pad opening 114 exposing the second pad portion 101b, a third source pad opening 115 exposing the third pad portion 101c, and a fourth source pad opening 116 exposing the fourth pad portion 101d.
  • the second source pad opening 114 exposes the second pad portion 101b at a distance from the first source pad opening 113
  • the fourth source pad opening 116 exposes the fourth pad portion 101d at a distance from the third source pad opening 115.
  • the first to fourth source pad openings 113 to 116 preferably have a planar area larger than the planar area of the gate subpad opening 112.
  • the planar areas of the first to fourth source pad openings 113 to 116 preferably are larger than the planar area of the gate pad opening 111.
  • the planar areas of the second source pad opening 114 and the fourth source pad opening 116 may be smaller than the planar area of the gate pad opening 111.
  • the planar area of the second source pad opening 114 is preferably less than the planar area of the first source pad opening 113.
  • the planar area of the third source pad opening 115 is preferably greater than the planar area of the second source pad opening 114.
  • the planar area of the third source pad opening 115 is preferably approximately equal to the planar area of the first source pad opening 113.
  • the planar area of the fourth source pad opening 116 is preferably less than the planar area of the third source pad opening 115.
  • the planar area of the fourth source pad opening 116 is preferably approximately equal to the planar area of the second source pad opening 114.
  • the first to fourth source pad openings 113 to 116 are formed in a rectangular shape in a plan view.
  • the first to fourth source pad openings 113 to 116 may also be formed in a polygonal shape other than a rectangular shape, a circular shape, etc. in a plan view.
  • the second source pad opening 114 is formed at a distance from the first source pad opening 113.
  • the second source pad opening 114 may be connected to the first source pad opening 113 and form one pad opening together with the first source pad opening 113.
  • the fourth source pad opening 116 may be connected to the third source pad opening 115 and form one pad opening together with the third source pad opening 115.
  • the pad insulating film 110 covers the outer well region 46, the outer contact region 47, and the multiple field regions 48 in the peripheral region 17, sandwiching the interlayer film 70 therebetween.
  • the pad insulating film 110 covers the sidewall wiring 51 at the first to fourth connection surfaces 10A to 10D, sandwiching the interlayer film 70 and the source wiring 102 therebetween.
  • the pad insulating film 110 is formed in the outer peripheral region 17 at a distance inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D), and defines a dicing street 117 between the periphery of the chip 2 and the pad insulating film 110.
  • the dicing street 117 is formed in a band shape extending along the periphery of the chip 2 in a plan view.
  • the dicing street 117 is formed in a ring shape (specifically, a square ring) surrounding the active surface 8 in a plan view.
  • the dicing street 117 exposes the interlayer film 70.
  • the dicing street 117 may also expose the outer peripheral surface 9.
  • the dicing street 117 may have a width of 1 ⁇ m or more and 200 ⁇ m or less.
  • the width of the dicing street 117 is the width in the direction perpendicular to the extension direction of the dicing street 117.
  • the width of the dicing street 117 is preferably 5 ⁇ m or more and 50 ⁇ m or less.
  • the pad insulating film 110 preferably has a thickness greater than the thickness of the gate electrode 80 and the thickness of the source electrode 100.
  • the thickness of the pad insulating film 110 is preferably greater than the total thickness of the gate electrode 80 and the source electrode 100.
  • the thickness of the pad insulating film 110 is preferably less than the thickness of the chip 2.
  • the thickness of the pad insulating film 110 may be 3 ⁇ m or more and 35 ⁇ m or less.
  • the thickness of the pad insulating film 110 is preferably 25 ⁇ m or less.
  • the pad insulating film 110 has a layered structure including an inorganic insulating film 118 and an organic insulating film 119, which are layered in this order from the chip 2 side (interlayer film 70 side).
  • the pad insulating film 110 needs to include at least one of the inorganic insulating film 118 and the organic insulating film 119, and does not necessarily need to include both the inorganic insulating film 118 and the organic insulating film 119 at the same time.
  • the inorganic insulating film 118 selectively covers the gate electrode 80, the source electrode 100, and the interlayer film 70, and defines a portion of the gate pad opening 111, a portion of the gate subpad opening 112, a portion of the first source pad opening 113, a portion of the second source pad opening 114, a portion of the third source pad opening 115, a portion of the fourth source pad opening 116, and a portion of the dicing street 117.
  • the inorganic insulating film 118 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the inorganic insulating film 118 preferably includes an insulating material different from that of the interlayer film 70.
  • the inorganic insulating film 118 preferably includes a silicon nitride film.
  • the inorganic insulating film 118 preferably has a thickness less than that of the interlayer film 70. The thickness of the inorganic insulating film 118 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the organic insulating film 119 selectively covers the inorganic insulating film 118 and defines a portion of the gate pad opening 111, a portion of the gate subpad opening 112, a portion of the first source pad opening 113, a portion of the second source pad opening 114, a portion of the third source pad opening 115, a portion of the fourth source pad opening 116, and a portion of the dicing street 117.
  • the organic insulating film 119 may expose the inorganic insulating film 118 on the wall surface of the gate pad opening 111.
  • the organic insulating film 119 may expose the inorganic insulating film 118 on the wall surface of the gate subpad opening 112.
  • the organic insulating film 119 may expose the inorganic insulating film 118 on the wall surface of the first source pad opening 113.
  • the organic insulating film 119 may expose the inorganic insulating film 118 on the wall surface of the second source pad opening 114.
  • the organic insulating film 119 may expose the inorganic insulating film 118 on the wall surface of the third source pad opening 115.
  • the organic insulating film 119 may expose the inorganic insulating film 118 on the wall surface of the fourth source pad opening 116.
  • the organic insulating film 119 may expose the inorganic insulating film 118 on the wall surface of the dicing street 117.
  • the organic insulating film 119 may cover the entire inorganic insulating film 118 so that the inorganic insulating film 118 is not exposed.
  • the organic insulating film 119 is preferably made of a resin film other than a thermosetting resin.
  • the organic insulating film 119 may be made of a light-transmitting resin or a transparent resin.
  • the organic insulating film 119 may be made of a negative-type or positive-type photosensitive resin film.
  • the organic insulating film 119 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film.
  • the organic insulating film 119 preferably has a thickness greater than that of the inorganic insulating film 118.
  • the organic insulating film 119 preferably has a thickness greater than that of the interlayer film 70. It is particularly preferable that the organic insulating film 119 has a thickness greater than that of the gate electrode 80 and that of the source electrode 100.
  • the thickness of the organic insulating film 119 may be 3 ⁇ m or more and 30 ⁇ m or less.
  • the thickness of the organic insulating film 119 is preferably 20 ⁇ m or less.
  • the semiconductor device 1 includes a drain electrode 120 covering the second main surface 4.
  • the drain electrode 120 may be referred to as a "drain pad,” “drain pad electrode,” “high potential pad electrode,” etc.
  • the drain electrode 120 forms an ohmic contact with the second semiconductor region 7 exposed from the second main surface 4.
  • the drain electrode 120 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2.
  • the drain electrode 120 may cover the second main surface 4 so as to partially expose the periphery of the chip 2.
  • the breakdown voltage that can be applied between the source electrode 100 and the drain electrode 120 (between the first major surface 3 and the second major surface 4) may be 500V or more.
  • the breakdown voltage may be 600V or more.
  • the breakdown voltage may be 1000V or more.
  • the breakdown voltage may be 3000V or more.
  • the breakdown voltage may be 5000V or less. Of course, the breakdown voltage may be 3000V or less.
  • FIG. 24 is a circuit diagram showing the electrical configuration of the gate resistor RG. As shown in FIG. 24, the gate wiring 85 is electrically connected to the gate pad 81 via the gate resistor RG.
  • the gate resistor RG is composed of a parallel circuit of a first parallel resistor circuit RC1 and a second parallel resistor circuit RC2.
  • the first parallel resistance circuit RC1 is electrically interposed between the gate pad 81 and the first resistance wiring 86 and is composed of a plurality of first resistance parts 60A connected in parallel.
  • the plurality of first resistance parts 60A may have the same resistance value or may have different resistance values.
  • the resistance value of each first resistance part 60A can be adjusted by adjusting the distance between the first resistance opening 72A and the second resistance opening 72B on the first resistance part 60A side.
  • the second parallel resistance circuit RC2 is electrically interposed between the gate pad 81 and the second resistance wiring 87 and is composed of a plurality of second resistance parts 60B connected in parallel.
  • the plurality of second resistance parts 60B may have the same resistance value or may have different resistance values.
  • the second resistor parts 60B may have the same resistance value as the first resistor parts 60A, or may have a different resistance value from the first resistor parts 60A.
  • the resistance value of each second resistor part 60B can also be adjusted by adjusting the distance between the first resistor opening 72A and the second resistor opening 72B on the second resistor part 60B side.
  • the resistance value of the gate resistor RG is determined by the combined resistance of the first parallel resistance circuit RC1 and the second parallel resistance circuit RC2.
  • the resistance value of the first parallel resistance circuit RC1 is determined by the combined resistance of the multiple first resistance sections 60A.
  • the resistance value of the first parallel resistance circuit RC1 may be adjusted by the resistance values of the multiple first resistance sections 60A, or by the number of multiple first resistance sections 60A.
  • the resistance value of the second parallel resistance circuit RC2 is determined by the combined resistance of the multiple second resistance sections 60B.
  • the resistance value of the second parallel resistance circuit RC2 may be adjusted by the resistance values of the multiple second resistance sections 60B, or by the number of multiple second resistance sections 60B.
  • the gate resistor RG does not necessarily have both the first parallel resistance circuit RC1 and the second parallel resistance circuit RC2 at the same time, and may be composed of only one of the first parallel resistance circuit RC1 and the second parallel resistance circuit RC2. This configuration is realized by adjusting the presence or absence of the first resistance opening 72A and the second resistance opening 72B, and the presence or absence of the first resistance wiring 86 and the second resistance wiring 87 at the layout level.
  • the gate resistor RG consists only of the second parallel resistor circuit RC2
  • the gate pad 81 and the gate wiring 85 are electrically disconnected from the multiple first resistor sections 60A.
  • at least the first resistor opening 72A is removed on the first resistor section 60A side.
  • either or both of the second resistor opening 72B and the first resistor wiring 86 may be removed.
  • the gate resistor RG is composed only of the first parallel resistor circuit RC1
  • the gate pad 81 and the gate wiring 85 are electrically separated from the second resistor units 60B.
  • at least the first resistor opening 72A is removed on the second resistor unit 60B side.
  • either or both of the second resistor opening 72B and the second resistor wiring 87 may be removed.
  • the gate resistor RG slows down the switching speed during switching operations to suppress surge currents. In other words, the gate resistor RG suppresses noise caused by surge currents. Since the gate resistor RG is formed on the first main surface 3 (active surface 8), it is not externally connected to the semiconductor device 1. This reduces the number of components mounted on the circuit board.
  • the gate resistor RG includes a portion of the multiple gate structures 20 (multiple first gate structures 20A) incorporated in the thickness direction of the chip 2, the area occupied by the gate resistor RG on the first main surface 3 is limited.
  • the gate resistor RG utilizes a portion of at least one (multiple in this embodiment) first gate structure 20A of the multiple gate structures 20 as a resistance portion 60, there is no need to provide a separate area dedicated to the gate resistor RG on the first main surface 3 (active surface 8). Therefore, the reduction in the area of the active region 12 resulting from the introduction of the gate resistor RG is suppressed.
  • the multiple gate structures 20 include multiple first gate structures 20A, multiple second gate structures 20B, and multiple third gate structures 20C.
  • the multiple first gate structures 20A each have a resistor portion 60 and are arranged in the pad region 55.
  • the multiple second gate structures 20B do not have a resistor portion 60 and are arranged in the pad region 55.
  • the multiple third gate structures 20C do not have a resistor portion 60 and are arranged outside the pad region 55.
  • the gate pad 81 is disposed in the pad region 55 at a distance from the plurality of third gate structures 20C, and covers the plurality of first gate structures 20A and the plurality of second gate structures 20B.
  • the gate pad 81 is electrically connected to the resistor portions 60 of the plurality of first gate structures 20A.
  • the gate wiring 85 covers the resistor portions 60 of the first gate structures 20A at a distance from the gate pad 81, and is electrically connected to the gate pad 81 via the resistor portions 60 of the first gate structures 20A.
  • the gate wiring 85 is further routed from the resistor portions 60 of the first gate structures 20A to an area outside the resistor portions 60, and is electrically connected to the first gate structures 20A, the second gate structures 20B, and the third gate structures 20C.
  • the multiple first gate structures 20A, the multiple second gate structures 20B, and the multiple third gate structures 20C are controlled by the gate potential inside and outside the pad region 55. Therefore, the electric field distribution caused by the multiple gate structures 20 inside the pad region 55 (directly below the gate pad 81) is similar to the electric field distribution caused by the multiple gate structures 20 outside the pad region 55 (outside directly below the gate pad 81). This suppresses a decrease in breakdown voltage caused by the layout of the multiple gate structures 20 inside and outside the pad region 55.
  • the semiconductor device 1 also includes a plurality of source structures 25 arranged adjacent to the plurality of gate structures 20 inside and outside the pad region 55.
  • the plurality of source structures 25 are controlled by the source potential inside and outside the pad region 55. Therefore, the electric field distribution caused by the plurality of source structures 25 inside the pad region 55 is similar to the electric field distribution caused by the plurality of source structures 25 outside the pad region 55. This suppresses a decrease in breakdown voltage caused by the layout of the plurality of source structures 25 in the pad region 55.
  • the semiconductor device 1 includes the chip 2, the trench electrode type first gate structure 20A (gate structure 20), the gate pad 81 (pad electrode), and the gate wiring 85 (wiring electrode).
  • the chip 2 has a first main surface 3.
  • the first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.
  • the gate pad 81 is disposed on the first main surface 3 so as to overlap the resistor portion 60, and has a first electrical connection portion (in this embodiment, a first resistor connection portion 83 and a second resistor connection portion 84) to the resistor portion 60.
  • the gate wiring 85 is disposed on the first main surface 3 so as to overlap the resistor portion 60 at a position different from the gate pad 81, and has a second electrical connection portion (in this embodiment, a first resistor wiring 86 and a second resistor wiring 87) to the resistor portion 60.
  • the gate wiring 85 is electrically connected to the gate pad 81 via the resistor portion 60.
  • This configuration makes it possible to provide a semiconductor device 1 having a new layout associated with a resistor.
  • this configuration makes it possible to avoid the need to provide a separate area for a resistor on the first main surface 3, since the resistor portion 60 is incorporated into a portion of the first gate structure 20A and the gate pad 81 overlaps the resistor portion 60. Therefore, it is possible to prevent the chip 2 from becoming too large in a configuration that includes a resistor.
  • the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), a trench electrode type second gate structure 20B (gate structure 20), and a gate pad 81 (pad electrode).
  • the chip 2 has a first main surface 3.
  • the first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.
  • the second gate structure 20B is formed on the first main surface 3 at a distance from the first gate structure 20A. Unlike the first gate structure 20A, the second gate structure 20B does not have a resistive portion 60.
  • the gate pad 81 is disposed on the first main surface 3 so as to overlap the resistive portion 60 of the first gate structure 20A and the second gate structure 20B.
  • the gate pad 81 has an electrical connection portion to the resistive portion 60, but does not have an electrical connection portion to the second gate structure 20B.
  • This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with resistors.
  • this configuration makes it possible to relax design rule restrictions resulting from the resistor portion 60 for the second gate structure 20B, since the resistor portion 60 is not incorporated in the second gate structure 20B. Therefore, this configuration makes it possible to provide a unique idea (layout) for the multiple gate structures 20 arranged in the region directly below the gate pad 81, while at the same time preventing the chip 2 from becoming too large in a configuration that includes resistors.
  • the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), a trench electrode type third gate structure 20C (gate structure 20), and a gate pad 81 (pad electrode).
  • the chip 2 has a first main surface 3.
  • the first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.
  • the third gate structure 20C is formed on the first main surface 3 at a distance from the first gate structure 20A, and unlike the first gate structure 20A, does not have a resistor portion 60.
  • the gate pad 81 is disposed on the first main surface 3 so as to overlap the resistor portion 60 of the first gate structure 20A and not overlap the third gate structure 20C.
  • the gate pad 81 has an electrical connection portion to the resistor portion 60, but does not have an electrical connection portion to the second gate structure 20B.
  • This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with resistors.
  • this configuration makes it possible to relax design rule restrictions resulting from the resistor portion 60 for the third gate structure 20C, since the resistor portion 60 is not incorporated in the third gate structure 20C. Therefore, this configuration makes it possible to provide a unique idea (layout) for multiple gate structures 20 arranged inside and outside the area directly below the gate pad 81, while at the same time preventing the chip 2 from becoming too large in a configuration that includes resistors.
  • the semiconductor device 1 includes a chip 2, a first gate structure 20A (gate structure 20) of a trench electrode type, a second gate structure 20B (gate structure 20) of a trench electrode type, a third gate structure 20C (gate structure 20) of a trench electrode type, and a gate pad 81 (pad electrode).
  • the chip 2 has a first main surface 3.
  • the first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.
  • the second gate structure 20B is formed on the first main surface 3 at a distance from the first gate structure 20A. Unlike the first gate structure 20A, the second gate structure 20B does not have a resistive portion 60.
  • the third gate structure 20C is formed on the first main surface 3 at a distance from the first gate structure 20A and the second gate structure 20B. Unlike the first gate structure 20A, the third gate structure 20C does not have a resistive portion 60.
  • the gate pad 81 is disposed on the first main surface 3 so as to overlap the resistor portion 60 of the first gate structure 20A and the second gate structure 20B, but not the third gate structure 20C.
  • the gate pad 81 has an electrical connection portion to the resistor portion 60, but does not have an electrical connection portion to the second gate structure 20B or the third gate structure 20C.
  • This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with resistors.
  • this configuration makes it possible to relax the design rule restrictions resulting from the resistor portion 60 for the second gate structure 20B and the third gate structure 20C, since the resistor portion 60 is not incorporated in the second gate structure 20B and the third gate structure 20C. Therefore, this configuration makes it possible to provide a unique idea (layout) for the multiple gate structures 20 arranged inside and outside the area directly below the gate pad 81, while at the same time preventing the chip 2 from becoming larger in a configuration that includes resistors.
  • the semiconductor device 1 includes a chip 2, an active plateau 11 (mesa portion), and a trench electrode type first gate structure 20A (gate structure 20).
  • the chip 2 has a first main surface 3.
  • the active plateau 11 is partitioned on the first main surface 3 by an active surface 8 (first surface portion), an outer peripheral surface 9 (second surface portion), and first to fourth connection surfaces 10A to 10D (connection surface portions).
  • the active surface 8 is located inside the first main surface 3.
  • the outer peripheral surface 9 is recessed in the thickness direction outside the active surface 8.
  • the first to fourth connection surfaces 10A to 10D connect the active surface 8 and the outer peripheral surface 9.
  • the first gate structure 20A is formed on the active surface 8 and has a resistor portion 60.
  • This configuration makes it possible to provide a semiconductor device 1 having a new layout associated with the resistor.
  • this configuration makes it possible to prevent the electrical characteristics and layout on the outer peripheral surface 9 side from being limited by the layout of the first gate structure 20A, since the first gate structure 20A is disposed on the active surface 8.
  • the semiconductor device 1 includes a chip 2, a plurality of trench electrode type gate structures 20, an interlayer film 70, a gate pad 81 (pad electrode), and a gate wiring 85 (wiring electrode).
  • the chip 2 has a first main surface 3.
  • the gate structure 20 is formed on the first main surface 3.
  • the interlayer film 70 covers the plurality of gate structures 20 on the first main surface 3.
  • the gate pad 81 is disposed on the interlayer film 70 so as to overlap at least one gate structure 20, and is electrically connected to at least one gate structure 20 through the interlayer film 70.
  • the gate wiring 85 is disposed on the interlayer film 70 at a distance from the gate pad 81, and is electrically connected to at least one gate structure 20 through the interlayer film 70.
  • the gate wiring 85 is electrically connected to the gate pad 81 via a portion of at least one gate structure 20.
  • This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with resistors.
  • this configuration makes it possible to adjust the resistance value between the gate pad 81 and the gate wiring 85 by adjusting the number of gate structures 20 electrically connected to the gate pad 81 and the gate wiring 85.
  • the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), and a trench electrode type source structure 25 (electrode structure).
  • the chip 2 has a first main surface 3.
  • the first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.
  • the source structure 25 is formed on the first main surface 3 so as to be adjacent to the first gate structure 20A.
  • This configuration provides a semiconductor device 1 with a novel layout associated with a resistor.
  • this configuration allows the electrical characteristics (e.g., electric field strength, etc.) around the gate structure 20 to be adjusted by the source structure 25.
  • the semiconductor device 1 preferably includes a resistive electrode 65 that covers the resistive portion 60 of the first gate structure 20A at a distance from the source structure 25.
  • a resistive electrode 65 that covers the resistive portion 60 of the first gate structure 20A at a distance from the source structure 25.
  • the source structure 25 functions as a resistor, the source structure 25 is required to have the same level of reliability as the first gate structure 20A.
  • the process difficulty of a relatively deep trench structure is higher than the process difficulty of a relatively shallow trench structure.
  • the process error that may occur in the relatively deep source structure 25 is larger than the process error that may occur in the relatively shallow first gate structure 20A.
  • process errors that may occur in the first gate structure 20A include process errors that may occur in the depth of the first trench 21 and the film thickness of the first insulating film 22.
  • process errors that may occur in the source structure 25 include process errors that may occur in the depth of the second trench 26 and the film thickness of the second insulating film 27.
  • the electrical characteristics of the source structure 25 may be inferior to the electrical characteristics of the first gate structure 20A due to process errors. This problem may be solved by imposing strict process conditions on the source structure 25. However, such a design change further increases the process difficulty, leading to increased costs.
  • the resistance portion 60 can be designed separately from the source structure 25, and the source structure 25 can be designed separately from the resistance portion 60. Therefore, it is possible to suppress the deterioration of the reliability of the resistance portion 60 caused by the source structure 25, and it is possible to suppress the deterioration of the reliability of the source structure 25 caused by the resistance portion 60.
  • the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), and a trench electrode type side end structure 30 (electrode structure).
  • the chip 2 has a first main surface 3.
  • the first gate structure 20A is formed in a strip shape extending in the first direction X on the first main surface 3, and has a resistor portion 60.
  • the side end structure 30 is formed on the first main surface 3 at a distance from the first gate structure 20A in the first direction X, and is given a potential (source potential) different from that of the first gate structure 20A.
  • This configuration provides a semiconductor device 1 with a novel layout associated with a resistor.
  • this configuration allows the electrical characteristics (e.g., electric field strength, etc.) around the first gate structure 20A to be adjusted by the side end structure 30.
  • the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), a trench electrode type source structure 25 (first electrode structure), and a trench electrode type side end structure 30 (second electrode structure).
  • the chip 2 has a first main surface 3.
  • the first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.
  • the source structure 25 is formed on the first main surface 3 at a distance from the first gate structure 20A in one direction (second direction Y), and is given a potential (source potential) different from that of the first gate structure 20A.
  • the side end structure 30 is formed on the first main surface 3 at a distance from the first gate structure 20A in an orthogonal direction (first direction X) perpendicular to the one direction, and is given a potential (source potential) different from that of the first gate structure 20A.
  • This configuration provides a semiconductor device 1 with a novel layout associated with a resistor.
  • this configuration allows the electrical characteristics (e.g., electric field strength, etc.) around the first gate structure 20A to be adjusted by the source structure 25 and the side end structure 30.
  • the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), a gate pad 81 (pad electrode), and a pad insulating film 110.
  • the chip 2 has a first main surface 3.
  • the first gate structure 20A is formed on the first main surface 3 and partially has a resistor portion 60.
  • the gate pad 81 is disposed on the first main surface 3 so as to overlap the resistor portion 60, and has a first resistor connection portion 83 (second resistor connection portion 84) which is an electrical connection portion to the resistor portion 60.
  • the pad insulating film 110 covers the first resistor connection portion 83 (second resistor connection portion 84) of the gate pad 81, and has a gate pad opening 111 which exposes the area outside the first resistor connection portion 83 (second resistor connection portion 84) of the gate pad 81.
  • This configuration makes it possible to provide a semiconductor device 1 having a new layout associated with the resistors.
  • this configuration makes it possible to protect the first resistor connection portion 83 (second resistor connection portion 84) by the pad insulating film 110. This prevents the first resistor connection portion 83 (second resistor connection portion 84) from peeling off, and prevents poor connection of the gate pad 81 to the resistor portion 60.
  • the semiconductor device 1 includes a gate pad 81, a gate wiring 85, and a gate resistor RG.
  • the gate wiring 85 is physically separated from the gate pad 81.
  • the gate resistor RG has a first parallel resistance circuit RC1 (second parallel resistance circuit RC2) including a plurality of resistance portions 60 (resistance elements), and is electrically interposed between the gate pad 81 and the gate wiring 85.
  • This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with resistors.
  • this configuration makes it possible to adjust the resistance value of the gate resistor RG by adjusting the resistance value and number of the multiple resistor sections 60.
  • the gate resistor RG may have a first parallel resistance circuit RC1 including multiple resistance sections 60 (first resistance section 60A), and a second parallel resistance circuit RC2 including multiple resistance sections 60 (second resistance section 60B) and connected in parallel to the first parallel resistance circuit RC1.
  • the layout of the semiconductor device 1 is particularly effective when a chip 2 including a SiC single crystal is employed.
  • the layout of the semiconductor device 1 provides various ideas that contribute to improving the electrical characteristics from various perspectives for the design associated with the resistance in a SiC semiconductor device (wide band gap semiconductor device).
  • FIG. 25 is an enlarged plan view showing a main portion of FIG. 19 together with a first gate structure 20A according to a second layout example.
  • the resistance portion 60 of each first gate structure 20A is covered with a plurality of resistance electrodes 65 (first resistance electrode 65A and second resistance electrode 65B).
  • the resistance portion 60 of each first gate structure 20A is covered by a single resistance electrode 65.
  • the configuration of the first resistance portion 60A side will be described, and the description of the second resistance portion 60B side will be omitted.
  • the description of the second resistance portion 60B side can be obtained by replacing "first resistance portion 60A" with “second resistance portion 60B" in the following description.
  • the multiple resistive electrodes 65 are provided on one side of one side (third side surface 5C side) of the pad region 55 and at the intersection with the first gate structure 20A.
  • the multiple resistive electrodes 65 are provided so as to straddle the inside and outside regions of the pad region 55, and have a first electrical electrode end 121 located within the pad region 55 and a second electrical electrode end 122 located outside the pad region 55.
  • the multiple resistive electrodes 65 cover a corresponding one of the first resistive sections 60A as a single covering object in the form of a film, and are electrically connected to the corresponding one of the first resistive sections 60A.
  • each resistive electrode 65 is provided in a one-to-one correspondence with each of the resistive sections 60.
  • the multiple resistive electrodes 65 are each formed in a band shape extending in the first direction X in a plan view, and face each other in the second direction Y.
  • the multiple resistive electrodes 65 are arranged in a stripe shape extending along the multiple first resistive sections 60A in a plan view.
  • Each resistive electrode 65 covers the first end 61 and the second end 62 of the corresponding first resistive portion 60A. Specifically, the first electrode end 121 of each resistive electrode 65 covers the first end 61 of the corresponding first resistive portion 60A, and the second electrode end 122 of each resistive electrode 65 covers the second end 62 of the corresponding first resistive portion 60A. In other words, each resistive electrode 65 has a layout in which the first resistive electrode 65A and the second resistive electrode 65B according to the first layout example are integrally formed.
  • the multiple resistive electrodes 65 are spaced apart in the second direction Y from another resistive electrode 65 that covers the resistive portion 60 that is not to be covered.
  • the multiple resistive electrodes 65 are spaced apart in the second direction Y from the multiple source structures 25, exposing the multiple source structures 25.
  • the multiple resistive electrodes 65 are arranged alternately with the multiple source structures 25 in the second direction Y in a plan view.
  • Each resistive electrode 65 exposes the area (first buried electrode 23) other than the resistive portion 60 of the corresponding first gate structure 20A. In other words, each resistive electrode 65 covers the corresponding first gate structure 20A at a distance from the gate connection electrode 53 in the first direction X, and faces the corresponding gate connection electrode 53 along the corresponding first gate structure 20A. Each resistive electrode 65 exposes the first buried electrode 23 from between the corresponding gate connection electrode 53.
  • the multiple resistive electrodes 65 have portions that face the multiple second gate structures 20B in the second direction Y.
  • the first electrode ends 121 of the multiple resistive electrodes 65 do not face the gate connection electrodes 53 on the second gate structure 20B side in the second direction Y.
  • the second electrode ends 122 of the multiple resistive electrodes 65 face the multiple gate connection electrodes 53 on the second gate structure 20B side in the second direction Y.
  • the multiple resistive electrodes 65 have portions that are located on the same straight line extending in the second direction Y as the multiple gate connection electrodes 53 on the second gate structure 20B side.
  • the multiple resistive electrodes 65 may be formed offset in the first direction X from the straight line connecting the multiple gate connection electrodes 53 in the second direction Y so as not to face the multiple gate connection electrodes 53 on the second gate structure 20B side in the second direction Y.
  • the other configuration of the resistive electrodes 65 is the same as in the first layout example.
  • the first resistor openings 72A expose the first electrode ends 121 of the resistor electrodes 65, respectively.
  • the second resistor openings 72B expose the second electrode ends 122 of the resistor electrodes 65, respectively.
  • the gate pad 81 is electrically connected to the first electrode ends 121 of the resistor electrodes 65 in the first resistor openings 72A, respectively.
  • the gate wiring 85 (first resistor wiring 86 and second resistor wiring 87) is electrically connected to the second electrode ends 122 of the resistor electrodes 65 in the second resistor openings 72B, respectively.
  • FIG. 26 is an enlarged plan view showing a main portion of FIG. 18 together with a first gate structure 20A according to a third layout example.
  • the resistance portion 60 of each first gate structure 20A is covered by a plurality of resistance electrodes 65 (first resistance electrode 65A and second resistance electrode 65B).
  • the resistance portion 60 of each first gate structure 20A is not covered by a resistance electrode 65.
  • Such a configuration may be adopted.
  • Fig. 27 is a cross-sectional view showing another example of the chip 2.
  • the semiconductor device 1 may include a second semiconductor region 7 inside the chip 2 that is thinner than the first semiconductor region 6.
  • the chip 2 may include an epitaxial layer that is thicker than the semiconductor substrate.
  • the first semiconductor region 6 may have a thickness of 1 ⁇ m or more and 50 ⁇ m or less (preferably 5 ⁇ m or more and 25 ⁇ m or less).
  • the second semiconductor region 7 may have a thickness of 0.1 ⁇ m or more and less than 50 ⁇ m.
  • the thickness of the second semiconductor region 7 may be 5 ⁇ m or more (preferably 10 ⁇ m or more).
  • FIG. 28 is a cross-sectional view showing another embodiment of the chip 2.
  • the semiconductor device 1 may not have a second semiconductor region 7 inside the chip 2 and may include only the first semiconductor region 6.
  • the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4, and the first to fourth side surfaces 5A to 5D of the chip 2. That is, in this embodiment, the chip 2 does not have a semiconductor substrate and has a single-layer structure made of an epitaxial layer.
  • the first semiconductor region 6 may have a thickness of 1 ⁇ m or more and 50 ⁇ m or less (preferably 5 ⁇ m or more and 25 ⁇ m or less).
  • the above-mentioned embodiment can be implemented in other embodiments.
  • the above-mentioned embodiment shows a configuration in which the pad region 55 (gate pad 81) is located on an imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.
  • the pad region 55 (gate pad 81) may be positioned offset to one side or the other in the first direction X with respect to the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.
  • the pad region 55 may be located at any corner of the active surface 8 in a plan view.
  • the pad region 55 may also be located in the center of the active surface 8 in a plan view.
  • the gate wiring 85 includes the third line wiring 92.
  • a gate wiring 85 that does not have the third line wiring 92 may be used.
  • the first source pad 101A and the second source pad 101B of the source pad 101 may be formed integrally.
  • the gate pad 81 penetrates the interlayer film 70 (through the resistor opening 72) and is connected to the resistor electrode 65.
  • the gate pad 81 may be connected to the resistor electrode 65 through a via electrode embedded in the interlayer film 70 (resistor opening 72).
  • the gate wiring 85 penetrates the interlayer film 70 (through the resistor opening 72) and is connected to the resistor electrode 65.
  • the gate wiring 85 may be connected to the resistor electrode 65 through a via electrode embedded in the interlayer film 70 (resistor opening 72).
  • the gate wiring 85 may be connected to the gate structure 20 (gate connection electrode 53) through a via electrode embedded in the interlayer film 70 (gate opening 71).
  • the source pad 101 penetrates the interlayer film 70 (through the source opening 73) and is connected to the source structure 25.
  • the source pad 101 may be connected to the source structure 25 through a via electrode embedded in the interlayer film 70 (source opening 73).
  • the via electrode may include a via body electrode (e.g., a W-based metal) embedded in the interlayer film 70 (resistor opening 72) through a barrier electrode film (e.g., a Ti-based metal film).
  • a via body electrode e.g., a W-based metal
  • a barrier electrode film e.g., a Ti-based metal film
  • a structure may be adopted in which the conductivity type of the "n-type” semiconductor region is inverted to "p-type” and the conductivity type of the "p-type” semiconductor region is inverted to "n-type".
  • a specific configuration in this case can be obtained by replacing “n-type” with “p-type” and at the same time replacing "p-type” with “n-type” in the above description and the attached drawings.
  • an n-type second semiconductor region 7 is shown.
  • a p-type second semiconductor region 7 may also be adopted.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed on the main surface (3) and having a resistor portion (60, 60A, 60B); a pad electrode (81) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) and having a first electrical connection portion (83, 84) to the resistor portion (60, 60A, 60B); and a wiring electrode (85) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) at a position different from the pad electrode (81), having a second electrical connection portion (86, 87) to the resistor portion (60, 60A, 60B), and electrically connected to the pad electrode (81) via the resistor portion (60, 60A, 60B).
  • the semiconductor device (1) described in A4 further includes a gate connection electrode (53) that selectively covers the portion of the gate structure (20, 20A) other than the resistance portion (60, 60A, 60B), and the wiring electrode (85) is electrically connected to the portion of the gate structure (20, 20A) other than the resistance portion (60, 60A, 60B) via the gate connection electrode (53).
  • a gate connection electrode (53) that selectively covers the portion of the gate structure (20, 20A) other than the resistance portion (60, 60A, 60B)
  • the wiring electrode (85) is electrically connected to the portion of the gate structure (20, 20A) other than the resistance portion (60, 60A, 60B) via the gate connection electrode (53).
  • the semiconductor device (1) described in A8 or A9 further includes a channel pad electrode (101) arranged on the main surface (3) at a distance from the pad electrode (81) and the wiring electrode (85) so as to overlap the channel, and having an electrical connection to the channel.
  • the semiconductor device (1) according to any one of A1 to A12, further comprising at least one resistive electrode (65, 65A, 65B) covering the resistive portion (60, 60A, 60B), the first connecting portion (83, 84) of the pad electrode (81) being electrically connected to the resistive portion (60, 60A, 60B) via the resistive electrode (65, 65A, 65B), and the second connecting portion (86, 87) of the wiring electrode (85) being electrically connected to the resistive portion (60, 60A, 60B) via the resistive electrode (65, 65A, 65B).
  • resistive electrode 65, 65A, 65B
  • the semiconductor device (1) described in any one of A1 to A13 further includes a trench electrode type source structure (25) formed on the main surface (3) adjacent to the gate structure (20, 20A), and the pad electrode (81) overlaps the source structure (25).
  • a semiconductor device (1) according to any one of A1 to A18, further comprising a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3), and an impurity region (18) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), and the gate structure (20, 20A) penetrates the impurity region (18) to reach the semiconductor region (6).
  • the semiconductor device (1) described in A19 further includes a well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the gate structure (20, 20A) in the surface layer portion of the main surface (3).
  • a well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the gate structure (20, 20A) in the surface layer portion of the main surface (3).
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type first gate structure (20A) formed on the main surface (3) and having a resistance portion (60, 60A, 60B); a trench electrode type second gate structure (20B) formed on the main surface (3) at a distance from the first gate structure (20A) and not having the resistance portion (60, 60A, 60B); and a pad electrode (81) arranged on the main surface (3) so as to overlap the resistance portion (60, 60A, 60B) of the first gate structure (20A) and the second gate structure (20B), having electrical connection portions (83, 84) to the resistance portion (60, 60A, 60B) and not having an electrical connection portion to the second gate structure (20B).
  • a trench electrode type third gate structure (20C) formed on the main surface (3) at a distance from the first gate structure (20A) and the second gate structure (20B) and not having the resistive portion (60, 60A, 60B), the pad electrode (81) being disposed on the main surface (3) so as not to overlap the third gate structure (20C), and not having an electrical connection portion to the third gate structure (20C).
  • a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3) and an impurity region (18) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6) the first gate structure (20A) penetrating the impurity region (18) to reach the semiconductor region (6)
  • the second gate structure (20B) penetrating the impurity region (18) to reach the semiconductor region (6).
  • the semiconductor device (1) described in B18 further includes a first well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the first gate structure (20A) in the surface layer portion of the main surface (3), and a second well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the second gate structure (20B) in the surface layer portion of the main surface (3).
  • a first well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the first gate structure (20A) in the surface layer portion of the main surface (3)
  • a second well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the second gate structure (20B) in the surface layer portion of the main surface (3).
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type first gate structure (20A) formed on the main surface (3) and having a resistance portion (60, 60A, 60B); a trench electrode type second gate structure (20C) formed on the main surface (3) at a distance from the first gate structure (20A) and not having the resistance portion (60, 60A, 60B); and a pad electrode (81) arranged on the main surface (3) so as to overlap the resistance portion (60, 60A, 60B) of the first gate structure (20A) and not overlap the second gate structure (20C), having electrical connection portions (83, 84) to the resistance portion (60, 60A, 60B), and not having an electrical connection portion to the second gate structure (20C).
  • [C2] A semiconductor device (1) according to C1, in which at least one of the first gate structures (20A) is formed on the main surface (3), and a greater number of the second gate structures (20C) than the number of the first gate structures (20A) are formed on the main surface (3).
  • [C3] A semiconductor device (1) described in C1 or C2, in which the second gate structure (20C) has a depth (D1) approximately equal to the depth (D1) of the first gate structure (20A).
  • [C4] A semiconductor device (1) described in any one of C1 to C3, in which the second gate structure (20C) has a width (W1) approximately equal to the width (W1) of the first gate structure (20A).
  • [C14] A semiconductor device (1) described in C12 or C13, in which the electrode structure (25) has a width (W2) that is equal to or greater than the width (W1) of the first gate structure (20A).
  • [C17] A semiconductor device (1) according to C16, in which the different potential pad electrode (101) overlaps the first gate structure (20A) at a position different from that of the pad electrode (81).
  • a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3) and an impurity region (18) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6) the first gate structure (20A) penetrating the impurity region (18) to reach the semiconductor region (6)
  • the second gate structure (20C) penetrating the impurity region (18) to reach the semiconductor region (6).
  • the semiconductor device (1) described in C18 further includes a first well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the first gate structure (20A) in the surface layer portion of the main surface (3), and a second well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the second gate structure (20C) in the surface layer portion of the main surface (3).
  • a first well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the first gate structure (20A) in the surface layer portion of the main surface (3)
  • a second well region (41) of a second conductivity type (p-type) formed in a region along the wall surface of the second gate structure (20C) in the surface layer portion of the main surface (3).
  • a chip (2) having a main surface (3), a trench electrode type first gate structure (20A) formed on the main surface (3) and having a resistance portion (60, 60A, 60B), a trench electrode type second gate structure (20B) formed on the main surface (3) at a distance from the first gate structure (20A) and not having the resistance portion (60, 60A, 60B), and a trench electrode type second gate structure (20B) formed on the main surface (3) at a distance from the first gate structure (20A) and the second gate structure (20B) and having the resistance portion (60, 60A, 60B).
  • a semiconductor device (1) including a chip (2) having a main surface (3), a first surface portion (8) located inside the main surface (3), a second surface portion (9) recessed in the thickness direction outside the first surface portion (8), and a mesa portion (11) defined on the main surface (3) by connection surface portions (10A-10D) connecting the first surface portion (8) and the second surface portion (9), and a trench electrode type gate structure (20, 20A) formed on the first surface portion (8) and having a resistor portion (60, 60A, 60B).
  • the semiconductor device (1) described in D1 including a pad electrode (81) arranged on the first surface portion (8) so as to be electrically connected to the resistor portion (60, 60A, 60B), and a wiring electrode (85) arranged on the first surface portion (8) so as to be electrically connected to the resistor portion (60, 60A, 60B) at a position different from the pad electrode (81).
  • [D4] A semiconductor device (1) described in D2 or D3, in which the wiring electrode (85) is arranged on the first surface portion (8) at a distance inward from the connection surface portion (10A to 10D).
  • [D8] A semiconductor device (1) described in D7, in which the electrode structure (25) has a length in the first direction (X) that is greater than the length of the gate structure (20, 20A).
  • [D13] A semiconductor device (1) described in D12, in which the electrode structure (30) has a length in the first direction (X) that is smaller than the length of the gate structure (20, 20A).
  • [D14] A semiconductor device (1) described in D12 or D13, in which the electrode structure (30) has a length in the first direction (X) that is greater than the length of the resistor portion (60, 60A, 60B).
  • [D15] A semiconductor device (1) described in any one of D11 to D14, in which the electrode structure (30) penetrates the connection surface portion (10A to 10D).
  • the semiconductor device (1) according to any one of D1 to D5, further including a trench electrode type first electrode structure (25) formed on the first surface portion (8) so as to be adjacent to the gate structure (20, 20A) in one direction (Y) and to which a potential different from that of the gate structure (20, 20A) is applied, and a trench electrode type second electrode structure (30) formed on the first surface portion (8) so as to be adjacent to the gate structure (20, 20A) in an orthogonal direction (X) perpendicular to the one direction (Y) and to which a potential different from that of the gate structure (20, 20A) is applied.
  • a trench electrode type first electrode structure (25) formed on the first surface portion (8) so as to be adjacent to the gate structure (20, 20A) in one direction (Y) and to which a potential different from that of the gate structure (20, 20A) is applied
  • a trench electrode type second electrode structure formed on the first surface portion (8) so as to be adjacent to the gate structure (20, 20A) in an orthogonal direction (X) perpendicular
  • [D20] A semiconductor device (1) according to D19, in which the sidewall structure (51) is made of wiring that transmits a potential different from that of the gate structure (20, 20A).
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a plurality of trench electrode type gate structures (20) formed on the main surface (3); an interlayer film (70) covering the plurality of gate structures (20) on the main surface (3); a pad electrode (81) arranged on the interlayer film (70) so as to overlap at least one of the gate structures (20) and electrically connected to at least one of the gate structures (20) through the interlayer film (70); and a wiring electrode (85) arranged on the interlayer film (70) at a distance from the pad electrode (81), electrically connected to at least one of the gate structures (20) through the interlayer film (70), and electrically connected to the pad electrode (81) through a part of at least one of the gate structures (20).
  • E2 The semiconductor device (1) described in E1, in which the pad electrode (81) is electrically connected to a plurality of the gate structures (20), and the wiring electrode (85) is electrically connected to the pad electrode (81) via a plurality of the gate structures (20).
  • [E4] A semiconductor device (1) according to E3, in which the first electrode films (65A) are arranged at intervals so as to be aligned in the same straight line.
  • [E5] A semiconductor device (1) described in E3 or E4, in which the second electrode films (65B) are arranged at intervals so as to be aligned in the same straight line.
  • a semiconductor device (1) including a chip (2) having a main surface (3), a trench electrode type gate structure (20, 20A) formed on the main surface (3) and having a resistor portion (60, 60A, 60B), and a trench electrode type source structure (25) formed on the main surface (3) adjacent to the gate structure (20, 20A).
  • the semiconductor device (1) described in F1 further includes a resistive electrode (65, 65A, 65B) covering the resistive portion (60, 60A, 60B) of the gate structure (20, 20A) at a distance from the source structure (25).
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed in a strip shape extending in a first direction (X) on the main surface (3) and having a resistance portion (60, 60A, 60B); and a trench electrode type electrode structure (30) formed on the main surface (3) at a distance from the gate structure (20, 20A) in the first direction (X) and to which a potential different from that of the gate structure (20, 20A) is applied.
  • G2 The semiconductor device (1) described in G1, including a gate pad (81) arranged on the main surface (3) so as to be electrically connected to the resistor portion (60, 60A, 60B), and a gate wiring (85) arranged on the main surface (3) so as to be electrically connected to the resistor portion (60, 60A, 60B) at a position different from the gate pad (81).
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed on the main surface (3) and having a resistance portion (60, 60A, 60B); a trench electrode type first electrode structure (25) formed on the main surface (3) at a distance from the gate structure (20, 20A) in one direction (Y) and given a potential different from that of the gate structure (20, 20A); and a trench electrode type second electrode structure (30) formed on the main surface (3) at a distance from the gate structure (20, 20A) in an orthogonal direction (X) perpendicular to the one direction (Y) and given a potential different from that of the gate structure (20, 20A).
  • H2 The semiconductor device (1) described in H1, including a gate pad (81) arranged on the main surface (3) so as to be electrically connected to the resistor portion (60, 60A, 60B), and a gate wiring (85) arranged on the main surface (3) so as to be electrically connected to the resistor portion (60, 60A, 60B) at a position different from the gate pad (81).
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed on the main surface (3) and partially having a resistor portion (60, 60A, 60B); a pad electrode (81) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) and having an electrical connection portion (83, 84) to the resistor portion (60, 60A, 60B); and a pad insulating film (110) covering the connection portion (83, 84) of the pad electrode (81) and having a pad opening (111) that exposes an area other than the connection portion (83, 84) of the pad electrode (81).
  • the semiconductor device (1) described in I1 or I2 further includes a wiring electrode (85) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) at a distance from the pad electrode (81), having an electrical connection wiring portion (86, 87) to the resistor portion (60, 60A, 60B), and electrically connected to the pad electrode (81) via the resistor portion (60, 60A, 60B).
  • a semiconductor device (1) including a gate pad (81), a gate wiring (85) physically separated from the gate pad (81), and a gate resistor (RG) having a parallel resistance circuit (R1, R2) including a plurality of resistance elements (60, 60A, 60B) and electrically interposed between the gate pad (81) and the gate wiring (85).
  • J2 A semiconductor device (1) described in J1, in which the multiple resistance elements (60, 60A, 60B) are each formed using a portion of multiple trench gate structures (20).
  • J3 A semiconductor device (1) described in J1 or J2, in which the gate resistor (RG) has a plurality of the parallel resistor circuits (R1, R2) connected in parallel.
  • Active plateau (mesa) 18 Body region (impurity region) 20 Gate structure 20A First gate structure 20B Second gate structure 20C Third gate structure 25 Source structure (electrode structure) 30 Side end structure (electrode structure) 41 First well region 51 Sidewall wiring (sidewall structure) 53 Gate connection electrode 60 Resistance portion (resistance element) 60A First resistor (resistance element) 60B Second resistance portion (resistance element) 65 Resistance electrode (electrode film) 65A First resistive electrode (electrode film) 65B Second resistive electrode (electrode film) 70 Interlayer film 81 Gate pad (pad electrode) 82 Pad body portion 83 First resistor connection portion (connection portion) 84 Second resistor connection portion (connection portion) 85 Gate wiring (wiring electrode) 86 First resistance wiring (connection wiring portion) 87 Second resistance wiring (connection wiring portion) 90 First line wiring (connection portion) 91 Second line wiring (connection part) 92 Third line wiring (connection part) 101 Source pad (channel pad electrode) 110 Pad insulating film 111 Gate pad opening

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PCT/JP2023/038174 2022-11-08 2023-10-23 半導体装置 Ceased WO2024101130A1 (ja)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6298670A (ja) * 1985-10-24 1987-05-08 Mitsubishi Electric Corp 電界効果型半導体装置
JP2015159329A (ja) * 2015-05-08 2015-09-03 三菱電機株式会社 半導体装置
WO2018008068A1 (ja) * 2016-07-04 2018-01-11 三菱電機株式会社 半導体装置の製造方法
WO2020235629A1 (ja) * 2019-05-22 2020-11-26 ローム株式会社 ＳｉＣ半導体装置
WO2021065722A1 (ja) * 2019-09-30 2021-04-08 ローム株式会社 半導体装置
WO2021200543A1 (ja) * 2020-03-30 2021-10-07 住友電気工業株式会社 トランジスタおよび半導体装置
WO2022024812A1 (ja) * 2020-07-31 2022-02-03 ローム株式会社 ＳｉＣ半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6298670A (ja) * 1985-10-24 1987-05-08 Mitsubishi Electric Corp 電界効果型半導体装置
JP2015159329A (ja) * 2015-05-08 2015-09-03 三菱電機株式会社 半導体装置
WO2018008068A1 (ja) * 2016-07-04 2018-01-11 三菱電機株式会社 半導体装置の製造方法
WO2020235629A1 (ja) * 2019-05-22 2020-11-26 ローム株式会社 ＳｉＣ半導体装置
WO2021065722A1 (ja) * 2019-09-30 2021-04-08 ローム株式会社 半導体装置
WO2021200543A1 (ja) * 2020-03-30 2021-10-07 住友電気工業株式会社 トランジスタおよび半導体装置
WO2022024812A1 (ja) * 2020-07-31 2022-02-03 ローム株式会社 ＳｉＣ半導体装置

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