WO2024099333A1 - 电源控制电路及服务器 - Google Patents

电源控制电路及服务器 Download PDF

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Publication number
WO2024099333A1
WO2024099333A1 PCT/CN2023/130306 CN2023130306W WO2024099333A1 WO 2024099333 A1 WO2024099333 A1 WO 2024099333A1 CN 2023130306 W CN2023130306 W CN 2023130306W WO 2024099333 A1 WO2024099333 A1 WO 2024099333A1
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WIPO (PCT)
Prior art keywords
power
signal
circuit
control circuit
state
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Application number
PCT/CN2023/130306
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English (en)
French (fr)
Inventor
付全龙
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杭州阿里云飞天信息技术有限公司
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Publication of WO2024099333A1 publication Critical patent/WO2024099333A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Definitions

  • the present application relates to the field of circuit technology, and in particular to a power control circuit and a server.
  • the server may include a power control circuit, which can control multiple power modules to ensure stable operation of the multiple power modules.
  • the power control circuit can determine the power state through the voltage output by each power module, and control each power module according to the power state.
  • the voltage is usually affected by other signals in the circuit and fluctuates, resulting in low accuracy in determining the power state, and further resulting in low reliability of the power control circuit in controlling multiple power modules.
  • Multiple aspects of the present application provide a power control circuit and a server, so as to improve the reliability of the power control circuit controlling multiple power modules.
  • an embodiment of the present application provides a power supply control circuit, comprising a master control circuit and at least one detection circuit, wherein the detection circuit comprises a controller and at least two filters, wherein the at least two filters are serially connected to the controller, and the controller is connected to the master control circuit; wherein:
  • the at least two filters are used to obtain an initial power signal of the detected power module, and filter the initial power signal to obtain a target power signal;
  • the controller is used to determine the power state of the detected power module according to the target power signal, and send the power state to the master control circuit;
  • the master control circuit is used to control the working state of the at least one detection circuit according to the received power state, and the working state includes a running state or a pause state.
  • the at least two filters include a first filter and a second filter, wherein:
  • the input end of the first filter is used to be connected to the detected power supply module, and the output end of the first filter is connected to the input end of the second filter;
  • An output end of the second filter is connected to the controller.
  • the first filter is used to filter the initial power signal based on the system clock frequency to obtain a first power signal
  • the second filter is used to filter the first power signal based on a preset clock frequency to obtain the target power signal.
  • the first filter is specifically used for:
  • the first sampling signal contains a first mutation signal
  • the first mutation signal is filtered out from the first sampling signal to obtain the first power supply signal, and the duration of the first mutation signal is less than or equal to the duration of M system clocks, where M is an integer greater than or equal to 1.
  • the second filter is specifically used for:
  • the second mutation signal is filtered out from the second sampling signal to obtain the target power signal, and the duration of the second mutation signal is less than or equal to the duration of N preset clocks, where N is an integer greater than or equal to 1.
  • the controller is specifically used to:
  • the power state is determined to be an abnormal state, where K is an integer greater than or equal to 1.
  • the master control circuit is specifically used for:
  • a lock signal is sent to the at least one detection circuit, where the lock signal is used to instruct the at least one detection circuit to switch the working state to the pause state.
  • the power control circuit is located in the daughter card circuit; and the master control circuit is further used for:
  • the power module in the daughter card circuit is controlled to be powered on or off according to the first electrical control signal and the second electrical control signal.
  • the master control circuit is specifically used for:
  • the power module in the daughter card circuit is controlled to power-off.
  • an embodiment of the present application provides a mainboard circuit, comprising the power control circuit described in any one of the first aspect and at least one power module, wherein at least one detection circuit in the power control circuit is respectively connected to the corresponding power module.
  • an embodiment of the present application provides a daughter card circuit, comprising the power control circuit described in any one of the first aspect and at least one power module, wherein at least one detection circuit in the power control circuit is respectively connected to the corresponding power module.
  • an embodiment of the present application provides a server, comprising the mainboard circuit described in the second aspect and at least one daughter card circuit described in the third aspect, wherein the power control circuit in the mainboard circuit is connected to the power control circuit in the daughter card circuit.
  • the embodiment of the present application provides a power control circuit and a server, wherein the power control circuit may include a master control circuit and at least one detection circuit, and the detection circuit may include a controller and at least two filters.
  • the at least two filters can obtain the initial power signal of the detected power module, and filter the initial power signal to obtain a target power signal.
  • the controller can determine the power state of the detected power module according to the target power signal, and send the power state to the master control circuit.
  • the master control circuit can control the working state of at least one detection circuit according to the received power state.
  • the initial power signal of the power module can be filtered by at least two filters, and then the power state is determined by the controller, compared with determining the power state by the voltage output by each power module, the accuracy of determining the power state is improved, thereby improving the reliability of the power control circuit to control multiple power modules.
  • FIG1 is a schematic diagram of an application scenario provided by an exemplary embodiment of the present application.
  • FIG2 is a schematic diagram of a power control circuit provided by an exemplary embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of another power supply control circuit provided by an exemplary embodiment of the present application.
  • FIG4 is a schematic structural diagram of a mainboard circuit provided by an exemplary embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of a daughter card circuit provided by an exemplary embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of a server provided by an exemplary embodiment of the present application.
  • FIG7 is a schematic diagram of a flow chart of a power-on method provided by an exemplary embodiment of the present application.
  • FIG. 8 is a schematic flow chart of a power-off method provided by an exemplary embodiment of the present application.
  • FIG1 is a schematic diagram of an application scenario provided by an exemplary embodiment of the present application.
  • a server may include multiple power modules and multiple components.
  • the multiple power modules may be power module 1, power module 2, power module 3, ..., power module i; the multiple components may be component 1, component 2, component 3, ..., component j.
  • the corresponding power module can supply power to the component.
  • power module 1 can supply power to component 1
  • power module 2 can supply power to component 2
  • power module i can supply power to component j.
  • the power control circuit can determine the power state according to the voltage output by each power module, and control each power module according to the power state.
  • the voltage is usually affected by other signals in the circuit and fluctuates, resulting in low accuracy in determining the power state, and further resulting in low reliability of the power control circuit in controlling multiple power modules.
  • the power control circuit may include a master control circuit and at least one detection circuit, and the detection circuit may include a controller and at least two filters. Since the initial power signal of the power module can be filtered by at least two filters, and then the power state is determined by the controller, the accuracy of determining the power state is improved compared to determining the power state by the voltage output by each power module, thereby improving the reliability of the power control circuit in controlling multiple power modules.
  • Fig. 2 is a schematic diagram of a power control circuit provided by an exemplary embodiment of the present application.
  • the power control circuit may include a master control circuit and at least one detection circuit.
  • the power control circuit can be a complex programmable logic device (CPLD). It is a digital integrated circuit that allows users to construct their own logical functions according to their needs.
  • CPLD complex programmable logic device
  • the at least one detection circuit may be detection circuit 1, detection circuit 2, . . . , detection circuit Q.
  • Q is an integer greater than or equal to 1.
  • the detection circuit may include a controller and at least two filters, the at least two filters are connected in series with the controller, and the controller is connected with the master control circuit.
  • the detection circuit 1 may include a filter 11, a filter 12 and a controller 13.
  • the filter 11 may be connected in series with the filter 12, the filter 12 may be connected to the controller 13, and the controller 13 may be connected to the master control circuit.
  • At least two filters may be used to obtain an initial power signal of the detected power module, and filter the initial power signal to obtain a target power signal.
  • the initial power signal may include a Power Good (PG) signal and/or a Power Fail (PF) signal.
  • PG Power Good
  • PF Power Fail
  • the PG signal is used to indicate that the power supply can work normally
  • the Power Fail signal is used to indicate that the power supply is abnormal.
  • the PG signal can be represented by “1” and the Power Fail signal can be represented by "0".
  • the target power signal may be a signal obtained by filtering the initial power signal.
  • the filter 11 in the detection circuit 1 can obtain the initial power signal 1, and filter the initial power signal 1 through the filters 11 and 12 to obtain the target power signal 1.
  • the target power signal 1 can be represented as “11111111111”.
  • the controller may be configured to determine the power status of the detected power module according to the target power signal, and send the power status to the master control circuit.
  • the power state may include a normal state or an abnormal state.
  • the controller can determine that the power state of the power module 1 is normal according to the target power signal 1, and send the power state to the main control circuit; if the target power signal 1 is "1111100000", the controller can determine that the power state of the power module 1 is abnormal according to the target power signal 1, and send the power state to the main control circuit.
  • the master control circuit may be used to control the working state of at least one detection circuit according to the received power state.
  • the working state may include a running state or a paused state.
  • the master control circuit can control the working state of the Q detection circuits to be an operating state according to the power state 1, that is, the Q detection circuits work normally; if the power state 2 sent by the controller 23 received by the master control circuit is an abnormal state, the master control circuit The circuit can control the working states of the Q detection circuits to be a pause state according to the power state 2, that is, the Q detection circuits pause working.
  • the power control circuit may include a master control circuit and at least one detection circuit
  • the detection circuit may include a controller and at least two filters.
  • the at least two filters may obtain the initial power signal of the detected power module, and filter the initial power signal to obtain a target power signal.
  • the controller may determine the power state of the detected power module according to the target power signal, and send the power state to the master control circuit.
  • the master control circuit may control the working state of at least one detection circuit according to the received power state.
  • the initial power signal of the power module can be filtered by at least two filters, and then the power state is determined by the controller, compared with determining the power state by the voltage output by each power module, the accuracy of determining the power state is improved, thereby improving the reliability of the power control circuit to control multiple power modules.
  • Fig. 3 is a schematic diagram of the structure of another power control circuit provided by an exemplary embodiment of the present application. Referring to Fig. 3, it may include at least one power module and a power control circuit.
  • the at least one power module may be power module 1 , power module 2 , . . . , power module Q.
  • the power control circuit may include a master control circuit and at least one detection circuit. Any detection circuit may include at least two filters and a controller.
  • the at least two filters may include a first filter and a second filter, wherein the input end of the first filter is connected to the detected power module, the output end of the first filter is connected to the input end of the second filter, and the output end of the second filter is connected to the controller.
  • the detection circuit 1 may include a first filter 11, a second filter 12 and a controller 13.
  • the input end of the first filter 11 may be connected to the power module 1, the output end may be connected to the input end of the second filter 12, and the output end of the second filter 12 may be connected to the controller 13.
  • the first filter may be used to filter the initial power signal based on the system clock frequency to obtain the first power signal.
  • the second filter may be used to filter the first power signal based on the preset clock frequency to obtain the target power signal.
  • the system clock frequency may be a manually preset frequency, for example, the system clock frequency may be 50 MHz.
  • the preset clock frequency may be a manually preset frequency, for example, the preset clock frequency may be 2KHz.
  • the first power supply signal may be obtained in the following manner: based on the system clock frequency, the initial power supply signal is sampled and processed by a first filter to obtain a first sampling signal; if the first mutation signal exists in the first sampling signal, the first mutation signal is filtered out from the first sampling signal to obtain the first power supply signal.
  • the duration of the first mutation signal is less than or equal to the duration of M system clocks, where M is an integer greater than or equal to 1.
  • the first sampling signal may include multiple initial power supply signals. For example, if the initial power supply signal can be represented by “0" and/or "1", if 5 samples are continuously taken, the first sampling signal may be "11101".
  • the first filter 11 can sample the initial power signal 1 every 50 MHz to obtain a first sampling signal. Assuming that five samplings are performed, the obtained first sampling signal is "11101".
  • the first mutation signal may be a Power Fail signal, and the first mutation signal may be represented by “0”.
  • obtaining the first power signal may include the following three situations:
  • the first sampling signal is the first power supply signal.
  • the first sampling signal is "11111"
  • there is no first mutation signal "0” there is no need to filter out the first mutation signal "0" in the first sampling signal
  • the first power signal is "11111”.
  • Case 2 There is a first mutation signal in the first sampling signal, and the duration of the first mutation signal is less than or equal to the duration of M system clocks.
  • the first mutation signal since the duration of the first mutation signal is less than or equal to the duration of M system clocks, the first mutation signal may be caused by the high-frequency influence of pulse width modulation (PWM) in the circuit, and is not caused by an abnormality in the detected power module. Therefore, the first mutation signal can be filtered out in the first sampling signal to remove the influence of the high-frequency pulse signal and obtain the first power signal.
  • PWM pulse width modulation
  • the system clock frequency can be 50MHz, and the duration of 3 system clocks can be 60ns (nanoseconds). If 5 consecutive samplings are performed, the first sampling signal is "11001", where the duration of the two first mutation signals "0" is 40ns. Since the duration of the two first mutation signals "0" of 40ns is less than the duration of 3 system clocks of 60ns, the first sampling signal can be filtered to obtain the first power supply signal of "11111".
  • Case 3 There is a first mutation signal in the first sampling signal, and the duration of the first mutation signal is greater than the duration of M system clocks.
  • the first mutation signal since the duration of the first mutation signal is greater than the duration of M system clocks, the first mutation signal is likely caused by an abnormality in the detected power module. In this case, the first mutation signal may not be filtered out in the first sampling signal to obtain the first power signal.
  • the system clock frequency can be 50MHz, and the duration of 3 system clocks can be 60ns. If 5 consecutive samplings are performed, the first sampling signal is "10000", and the duration of the 4 first mutation signals "0" is 80ns, then the duration of the 4 first mutation signals "0" 80ns is greater than the duration of 3 system clocks 60ns. Then, the first sudden change signal may not be filtered out in the first sampling signal, and the obtained first power supply signal is "10000".
  • the first filter After the first filter obtains the first power signal, it can output the first power signal to the second filter, so that the second filter obtains the target power signal from the first power signal.
  • the target power signal can be obtained in the following manner: based on a preset clock frequency, the first power signal is sampled and processed by a second filter to obtain a second sampling signal; if a second mutation signal exists in the second sampling signal, the second mutation signal is filtered out from the second sampling signal to obtain the target power signal, and the duration of the second mutation signal is less than or equal to the duration of N preset clocks, where N is an integer greater than or equal to 1.
  • the preset clock frequency may be 2KHz
  • the first power signal 1 is "10000”
  • the second filter 12 may sample the first power signal 1 every 2KHz to obtain a second sampling signal. Assuming that 4 samplings are performed, the obtained second sampling signal may be "1000".
  • the second mutation signal can be a Power Fail signal, and the second mutation signal can be represented by "0".
  • obtaining the target power signal may include the following three situations:
  • the second sampling signal is the target power supply signal.
  • the second sampling signal is "1111" and there is no second mutation signal "0", then there is no need to filter out the second mutation signal "0" in the second sampling signal, and the target power signal is "1111".
  • Case 2 There is a second mutation signal in the second sampling signal, and the duration of the second mutation signal is less than or equal to the duration of N preset clocks.
  • the second mutation signal since the duration of the second mutation signal is less than or equal to the duration of N preset clocks, the second mutation signal may be caused by interference caused by rapid jumps of high-drive capability signals in the circuit and/or interference from some low-speed signal interfaces.
  • the second mutation signal can be filtered out in the second sampling signal to obtain the target power supply signal.
  • the preset clock frequency is 20KHz
  • the duration of two preset clocks can be 100us (microseconds)
  • the second sampling signal is "1101”
  • the duration of one second mutation signal "0" is 50us. Since the duration of the second mutation signal "0" is 50us, which is less than the duration of two preset clocks, 100us, the second sampling signal can be filtered to obtain a target power signal of "1111".
  • Case 3 There is a second mutation signal in the second sampling signal, and the duration of the second mutation signal is greater than the duration of N preset clocks.
  • the second mutation signal since the duration of the second mutation signal is longer than the duration of N preset clocks, the second mutation signal is likely to be caused by the abnormality of the first power supply signal, and the second mutation signal may not be filtered out in the second sampling signal. Mutate the signal to get the target power signal.
  • the preset clock frequency is 20KHz
  • the duration of 2 preset clocks can be 100us (microseconds)
  • the second sampling signal is "1000”
  • the duration of 3 second mutation signals "0" is 150us. Since the duration of the second mutation signal "0" is 50us, which is greater than the duration of 2 preset clocks, 100us, the second mutation signal can be omitted from the second sampling signal, and the target power signal is "1000".
  • the target power signal can more accurately reflect the power state of the detected power module.
  • the second filter may output the target power signal to the controller, so that the controller determines the power state of the detected power module according to the target power signal.
  • the controller may determine the power state in the following two cases:
  • the preset signal may be represented by “0”.
  • K may be an integer greater than or equal to 1.
  • the controller may determine that the power state of the detected power module is a normal state according to the target power signal.
  • the controller 13 can determine that the power status of the power module 1 is normal.
  • the controller may determine, based on the target power signal, that the power state of the detected power module is an abnormal state.
  • the controller 13 can determine that the power status of the power module 1 is an abnormal state.
  • the controller After the controller determines the power state of the power module, it can output the power state to the master control circuit, and the master control circuit can control the working state of at least one detection circuit according to the power state.
  • different time windows can be set for the detection circuit, and within the time window, the first filter, the second filter and the controller in the detection circuit operate normally.
  • the duration of the time window of the detection circuit can be the duration between the start-up and shutdown of the device in which the detection circuit is located.
  • the master control circuit may control the working state of at least one detection circuit according to the power supply state, which may be divided into the following two situations:
  • the master control circuit may control the working state of at least one detection circuit to be an operating state.
  • the main control circuit receives the power state 1, since the power state 1 is a normal state, it means that there is no abnormality, and at least one detection circuit can continue to operate normally.
  • the master control circuit can send a lock signal to at least one detection circuit to instruct at least one detection circuit to switch the working state to a pause state, so that at least one detection circuit no longer sends the power state to the master control circuit, which facilitates the master control circuit to determine the first power module with an abnormality.
  • the lock signal may be represented by "lock”.
  • the main control circuit can send a lock signal lock to the Q detection circuits to instruct the Q detection circuits to switch the working state to the pause state, so that the Q detection circuits no longer send the power state to the main control circuit, so as to facilitate the main control circuit to determine that the first power module with an abnormality is power module 1.
  • the master control circuit can also comprehensively form fault information based on the priority of the power supply state sent by each controller, and send the fault information to the read-write module so that the read-write module records the power supply states of multiple power supply modules.
  • control process of the power control circuit can be implemented in the form of code.
  • the power control circuit may include a master control circuit and at least one detection circuit
  • the detection circuit may include a controller, a first filter, and a second filter.
  • the first filter may filter the initial power signal to obtain a first power signal
  • the second filter may filter the first power signal to obtain a target power signal.
  • the controller may determine the power state of the power module according to the target power signal, and send the power state to the master control circuit.
  • the master control circuit may control the working state of at least one detection circuit according to the received power state.
  • the initial power signal of the power module may be filtered by at least two filters, and then the power state is determined by the controller, the accuracy of determining the power state is improved compared to determining the power state by the voltage output by each power module, thereby improving the reliability of the power control circuit in controlling multiple power modules.
  • FIG. 4 a schematic diagram of the structure of a mainboard circuit is provided.
  • Fig. 4 is a schematic diagram of a mainboard circuit provided by an exemplary embodiment of the present application.
  • the mainboard circuit may include a power control circuit and at least one power module.
  • At least one power module may be power module 1, power module 2, ..., power module Q.
  • the power supply may generate an initial power signal.
  • power module 1 may generate initial power signal 1.
  • the initial power signal may include a PG signal and a Power Fail signal. If the voltage of the power module is a low voltage, a Power Fail signal "0" may be generated; if the voltage of the power module is a high voltage, a PG signal "1" may be generated. For example, if the voltage of the power module 1 is "high-high-low-low-high", the corresponding initial power signal 1 may be generated as "11001".
  • the power control circuit may include a master control circuit and at least one detection circuit.
  • the detection circuit can be connected to the corresponding power module respectively. As shown in FIG4 , detection circuit 1 can be connected to power module 1, detection circuit 2 can be connected to power module 2, ..., detection circuit Q can be connected to power module Q.
  • the detection circuit may include a first filter, a second filter and a controller, wherein the input end of the first filter is connected to the detected power module, the output end of the first filter is connected to the input end of the second filter, and the output end of the second filter is connected to the controller.
  • the first filter may be used to filter the initial power signal based on the system clock frequency to obtain the first power signal.
  • the second filter can be used to filter the first power signal based on a preset clock frequency to obtain a target power signal.
  • the specific execution process of obtaining the first power signal and obtaining the target power signal can refer to the specific execution process of obtaining the first power signal and obtaining the target power signal in FIG. 3 , which will not be described in detail here.
  • the second filter After the second filter determines the target power signal, it can output the target power signal to the controller.
  • the controller can determine the power state of the detected power module according to the target power signal.
  • the power state can be divided into a normal state and an abnormal state.
  • the controller After the controller determines the power state of the detected power module, it can output the power state to the master control circuit, and the master control circuit can control the working state of at least one detection circuit according to the power state.
  • the working state can be divided into a running state or a pause state.
  • the master control circuit may send a lock signal to at least one detection circuit according to the power state, instructing at least one detection circuit to switch the working state to a pause state, so that at least one detection circuit no longer sends the power state to the master control circuit, so that the master control circuit can determine the first The detected power module has an abnormality.
  • the mainboard circuit may include a power control circuit and at least one power module.
  • the power control circuit may include a master control circuit and at least one detection circuit, and the detection circuit may include a controller, a first filter, and a second filter.
  • the first filter may filter the initial power signal to obtain a first power signal
  • the second filter may filter the first power signal to obtain a target power signal.
  • the controller may determine the power state of the detected power module according to the target power signal, and send the power state to the master control circuit.
  • the master control circuit may control the working state of at least one detection circuit according to the received power state.
  • the initial power signal of the power module can be filtered by at least two filters, and then the power state is determined by the controller, the accuracy of determining the power state is improved compared to determining the power state by the voltage output by each power module, thereby improving the reliability of the power control circuit to control multiple power modules.
  • Fig. 5 is a schematic diagram of a daughter card circuit provided by an exemplary embodiment of the present application.
  • the daughter card circuit may include a power control circuit and at least one power module.
  • At least one power module may be respectively power module 1 , power module 2 , . . . power module P.
  • the power module may generate an initial power signal.
  • power module 1 may generate initial power signal 1 .
  • the power control circuit may include a master control circuit and at least one detection circuit.
  • the detection circuit can be connected to the corresponding power module respectively. As shown in FIG5 , detection circuit 1 can be connected to power module 1, detection circuit 2 can be connected to power module 2, ..., detection circuit P can be connected to power module P.
  • the detection circuit may include a first filter, a second filter and a controller, wherein the input end of the first filter is connected to the detected power module, the output end of the first filter is connected to the input end of the second filter, and the output end of the second filter is connected to the controller.
  • the first filter can be used to filter the initial power signal based on the system clock frequency to obtain the first power signal.
  • the second filter can be used to filter the first power signal based on a preset clock frequency to obtain a target power signal.
  • the specific execution process of obtaining the first power signal and obtaining the target power signal can refer to the specific execution process of obtaining the first power signal and obtaining the target power signal in FIG. 3 , which will not be described in detail here.
  • the second filter After the second filter determines the target power signal, it can output the target power signal to the controller.
  • the controller can determine the power state of the detected power module according to the target power signal.
  • the power state can be divided into a normal state and an abnormal state.
  • the controller After the controller determines the power state of the detected power module, it can output the power state to the master control circuit, and the master control circuit can control the working state of at least one detection circuit according to the power state.
  • the working state can be divided into a running state or a pause state.
  • the master control circuit may send a lock signal to at least one detection circuit based on the power status, instructing at least one detection circuit to switch the working state to a pause state, so that at least one detection circuit no longer sends the power status to the master control circuit, thereby facilitating the master control circuit to determine the first detected power module that has an abnormality.
  • the subcard circuit may include a power control circuit and at least one power module.
  • the power control circuit may include a master control circuit and at least one detection circuit, and the detection circuit may include a controller, a first filter, and a second filter.
  • the first filter may filter the initial power signal to obtain a first power signal
  • the second filter may filter the first power signal to obtain a target power signal.
  • the controller may determine the power state of the detected power module according to the target power signal, and send the power state to the master control circuit.
  • the master control circuit may control the working state of at least one detection circuit according to the received power state.
  • the initial power signal of the power module may be filtered by at least two filters, and then the power state is determined by the controller, the accuracy of determining the power state is improved compared to determining the power state by the voltage output by each power module, thereby improving the reliability of the power control circuit in controlling multiple power modules.
  • Fig. 6 is a schematic diagram of the structure of a server provided by an exemplary embodiment of the present application.
  • the server may include a mainboard circuit and at least one daughter card circuit.
  • the mainboard circuit may include a power control circuit and at least one power module.
  • the power control circuit may include at least one detection circuit and a master control circuit.
  • the at least one daughter card circuit may be daughter card circuit 1, ..., daughter card circuit S.
  • S is an integer greater than or equal to 1.
  • the daughter card circuit may include a power control circuit and at least one power module.
  • the power control circuit may include at least one detection circuit and a master control circuit.
  • the power control circuit in the main board circuit is connected to the power control circuit in the daughter card circuit.
  • the power control circuit 1 in the main board circuit can be connected to the power control circuit 2 in the daughter card circuit 1 .
  • the power control circuit may include a master control circuit and at least one detection circuit, and the detection circuit may include a controller, a first filter, and a second filter.
  • the first filter may filter the initial power signal to obtain a first power signal
  • the second filter may filter the first power signal.
  • the source signal is filtered to obtain a target power signal.
  • the controller can determine the power state of the detected power module according to the target power signal and send the power state to the master control circuit.
  • the master control circuit can control the working state of at least one detection circuit according to the received power state.
  • controller the first filter, the second filter, and the master control circuit can refer to the contents shown in any of the above embodiments, and will not be repeated here.
  • the master control circuit can be used to receive a first electrical control signal sent by the power control circuit in the main board circuit through the upper and lower point interfaces, and a second electrical control signal sent through the bus interface; according to the first electrical control signal and the second electrical control signal, the power module in the daughter card circuit is controlled to be powered on or off.
  • the upper and lower point interface refers to the communication interface between the main board circuit and the daughter card circuit.
  • the upper and lower point interface can be a serial general purpose input/output (Serial General Purpose Input/Output, SGPIO) interface.
  • SGPIO Serial General Purpose Input/Output
  • the first electrical control signal may be a communication signal between the main board circuit and the daughter card circuit.
  • the bus interface refers to the physical bus interface between the mainboard circuit and the daughter card circuit.
  • the second electrical control signal may be a power-up signal or a power-down signal.
  • the master control circuit 1 in the main board circuit can send a first electrical control signal to the master control circuit 2 in the daughter card circuit through the upper and lower point interfaces, and send a second electrical control signal to the master control circuit 2 through the bus interface.
  • the master control circuit 2 in the daughter card circuit can then control the power module in the daughter card circuit to power on or off according to the first electrical control signal and the second electrical control signal.
  • the power module in the daughter card circuit can be controlled to power on; if the first electrical control signal and the second electrical control signal respectively indicate power off, the power module in the daughter card circuit can be controlled to power off.
  • FIG7 is a flow chart of a power-on method provided by an exemplary embodiment of the present application. Referring to FIG7 , the method may include:
  • S701 Determine the initial state of the power module.
  • the master control circuit in the daughter card circuit can determine the initial state of the power module in the daughter card circuit.
  • the initial state can be divided into a power-off state and a power-on state.
  • S702 to S704 may be executed.
  • S702 Determine whether the first electrical control signal indicates power-on.
  • the master control circuit in the daughter card circuit may determine whether the first electrical control signal indicates power-on. If not, S703 may be executed; if so, S704 may be executed.
  • S703 Determine whether the second electrical control signal indicates power-on.
  • the master control circuit in the daughter card circuit can determine whether the second electrical control signal indicates power-on. If so, S704 can be executed; if not, it means that neither the first electrical control signal nor the second electrical control signal indicates power-on, so the initial state of the power module can be maintained, that is, the power-off state.
  • the master control circuit in the daughter card circuit can control the power module in the daughter card circuit to power on.
  • FIG8 is a flow chart of a power-off method provided by an exemplary embodiment of the present application. Referring to FIG8 , the method may include:
  • the master control circuit in the daughter card circuit can determine the initial state of the power module in the daughter card circuit.
  • the initial state can be divided into a power-off state and a power-on state.
  • S802 to S804 may be executed.
  • S802 Determine whether the first power control signal indicates power off.
  • the master control circuit in the daughter card circuit can determine whether the first electrical control signal indicates power-off. If so, S803 can be executed; if not, the initial state of the power module, ie, the power-on state, is maintained.
  • the master control circuit in the daughter card circuit can determine whether the second electrical control signal indicates power-off. If so, S804 can be executed; if not, the initial state of the power module, ie, the power-on state, can be maintained.
  • the master control circuit in the daughter card circuit can control the power module in the daughter card circuit to power off.
  • the master control circuit in the daughter card circuit can double-determine whether to control the power module to power off based on the first electrical control signal and the second electrical control signal, thereby improving the reliability of controlling the power module.
  • the master control circuit in the daughter card circuit may send fault information to the master control circuit in the motherboard circuit, and the fault information may include the power state.
  • the motherboard circuit may perform corresponding processing according to the system strategy and the fault information.
  • the server may include a mainboard circuit and at least one sub-card circuit.
  • the mainboard circuit and the sub-card circuit may include a power control circuit and at least one power module respectively.
  • Any power control circuit may include
  • the invention comprises a master control circuit and at least one detection circuit, wherein the detection circuit may comprise a controller, a first filter and a second filter.
  • the first filter may filter an initial power signal to obtain a first power signal
  • the second filter may filter the first power signal to obtain a target power signal.
  • the controller may determine the power state of the detected power module according to the target power signal, and send the power state to the master control circuit.
  • the master control circuit may control the working state of at least one detection circuit according to the received power state.
  • the master control circuit in the daughter card circuit may also control the power on and off of the power module in the daughter card circuit according to the first electrical control signal and the second electrical control signal. Since the initial power signal of the power module may be filtered by at least two filters, and then the power state may be determined by the controller, the accuracy of determining the power state is improved compared with determining the power state according to the voltage output by each power module; and the master control circuit in the daughter card circuit may double determine whether the power module is powered off according to the first electrical control signal and the second electrical control signal, thereby improving the reliability of the power control circuit in the server controlling multiple power modules.
  • embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • each process and/or box in the flowchart and/or block diagram, as well as the combination of the process and/or box in the flowchart and/or block diagram can be implemented by computer program instructions.
  • These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • a computing device includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.
  • processors CPU
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
  • RAM random access memory
  • ROM read-only memory
  • flash RAM flash memory
  • Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information.
  • Information can be computer readable instructions, data structures, program modules or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.
  • computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

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Abstract

一种电源控制电路及服务器，可提高电源控制电路对多个电源模块（1,2,……,Q）进行控制的可靠性。电路中包括总控电路和至少一个检测电路（1,2,……,Q），检测电路（1,2,……,Q）包括控制器（13,23,……,Q3）和至少两个滤波器（(11,12),(21,22),……, (Q1,Q2)），至少两个滤波器（(11,12),(21,22),……, (Q1,Q2)）与控制器（13,23,……,Q3）串行连接，控制器（13,23,……,Q3）与总控电路连接；其中，至少两个滤波器（(11,12),(21,22),……, (Q1,Q2)）用于获取被检测电源模块（1,2,……,Q）的初始电源信号，并对初始电源信号进行滤波处理，得到目标电源信号；控制器（13,23,……,Q3）用于根据目标电源信号确定被检测电源模块（1,2,……,Q）的电源状态，并向总控电路发送电源状态；总控电路用于根据接收到的电源状态控制至少一个检测电路（1,2,……,Q）的工作状态，工作状态包括运行状态或暂停状态。

Description

电源控制电路及服务器
本申请要求于2022年11月09日提交中国专利局、申请号为202211401072.8、申请名称为“电源控制电路及服务器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，尤其涉及一种电源控制电路及服务器。
背景技术
服务器中可以包括电源控制电路，电源控制电路可以对多个电源模块进行控制，以确保多个电源模块稳定运行。
在相关技术中，电源控制电路可以通过各个电源模块输出的电压，确定电源状态，并根据电源状态对各个电源模块进行控制。然而，在上述过程中，电压通常会受到电路中其他信号的影响而产生波动，导致确定电源状态的准确性低，进而导致电源控制电路对多个电源模块进行控制的可靠性低。
发明内容
本申请的多个方面提供一种电源控制电路及服务器，用以提高电源控制电路对多个电源模块进行控制的可靠性。
第一方面，本申请实施例提供一种电源控制电路，包括总控电路和至少一个检测电路，所述检测电路包括控制器和至少两个滤波器，所述至少两个滤波器串与所述控制器串行连接，所述控制器与所述总控电路连接；其中，
所述至少两个滤波器用于获取被检测电源模块的初始电源信号，并对所述初始电源信号进行滤波处理，得到目标电源信号；
所述控制器用于根据所述目标电源信号确定所述被检测电源模块的电源状态，并向所述总控电路发送所述电源状态；
所述总控电路用于根据接收到的电源状态控制所述至少一个检测电路的工作状态，所述工作状态包括运行状态或暂停状态。
一种可能的实施方式中，所述至少两个滤波器包括第一滤波器和第二滤波器，其中，
所述第一滤波器的输入端用于与所述被检测电源模块连接，所述第一滤波器的输出端与所述第二滤波器的输入端连接；
所述第二滤波器的输出端与所述控制器连接。
一种可能的实施方式中，
所述第一滤波器用于基于系统时钟频率对所述初始电源信号进行滤波处理，得到第一电源信号；
所述第二滤波器用于基于预设时钟频率对所述第一电源信号进行滤波处理，得到所述目标电源信号。
一种可能的实施方式中，所述第一滤波器具体用于：
基于所述系统时钟频率，对所述初始电源信号进行采样处理，得到第一采样信号；
若所述第一采样信号中存在第一突变信号，则在所述第一采样信号中滤除所述第一突变信号，得到所述第一电源信号，所述第一突变信号的持续时长小于或等于M个所述系统时钟的时长，所述M为大于或等于1的整数。
一种可能的实施方式中，所述第二滤波器具体用于：
基于所述预设时钟频率，对所述第一电源信号进行采样处理，得到第二采样信号；
若所述第二采样信号中存在第二突变信号，则在所述第二采样信号中滤除所述第二突变信号，得到所述目标电源信号，所述第二突变信号的持续时长小于或等于N个所述预设时钟的时长，所述N为大于或等于1的整数。
一种可能的实施方式中，所述控制器具体用于：
在确定所述目标电源信号中存在K位预设信号时，确定所述电源状态为异常状态，所述K为大于或等于1的整数。
一种可能的实施方式中，所述总控电路具体用于：
若接收到的所述电源状态为异常状态，则向所述至少一个检测电路发送加锁信号，所述加锁信号用于指示所述至少一个检测电路将工作状态切换为所述暂停状态。
一种可能的实施方式中，所述电源控制电路位于子卡电路中；所述总控电路还用于：
接收主板电路中的电源控制电路通过上下点接口发送的第一电控制信号、以及通过总线接口发送的第二电控制信号；
根据所述第一电控制信号和所述第二电控制信号，控制所述子卡电路中的电源模块上电或者下电。
一种可能的实施方式中，所述总控电路具体用于：
在所述第一电控制信号和/或所述第二电控制信号指示上电时，控制所述子卡电路中的电源模块上电；
在所述第一电控制信号和所述第二电控制信号分别指示下电时，控制所述子卡电路中的电源模块下电。
第二方面，本申请实施例提供一种主板电路，包括第一方面任一项所述的电源控制电路、至少一个电源模块，其中，所述电源控制电路中的至少一个检测电路分别与对应的电源模块连接。
第三方面，本申请实施例提供一种子卡电路，包括第一方面任一项所述的电源控制电路、至少一个电源模块，其中，所述电源控制电路中的至少一个检测电路分别与对应的电源模块连接。
第四方面，本申请实施例提供一种服务器，包括第二方面所述的主板电路和至少一个第三方面所述的子卡电路，其中，所述主板电路中的电源控制电路和所述子卡电路中的电源控制电路连接。
本申请实施例提供一种电源控制电路及服务器，电源控制电路中可以包括总控电路和至少一个检测电路，检测电路中可以包括控制器和至少两个滤波器。至少两个滤波器可以获取被检测电源模块的初始电源信号，并对初始电源信号进行滤波处理，得到目标电源信号。控制器可以根据目标电源信号确定被检测电源模块的电源状态，并向总控电路发送电源状态。总控电路可以根据接收到的电源状态控制至少一个检测电路的工作状态。由于可以通过至少两个滤波器对电源模块的初始电源信号进行滤波处理，进而通过控制器确定电源状态，相比通过各个电源模块输出的电压确定电源状态，提高了确定电源状态的准确性，进而提高了电源控制电路对多个电源模块进行控制的可靠性。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本申请示例性实施例提供的一种应用场景的示意图；
图2为本申请示例性实施例提供的一种电源控制电路的结构示意图；
图3为本申请示例性实施例提供的另一种电源控制电路的结构示意图；
图4为本申请示例性实施例提供的一种主板电路的结构示意图；
图5为本申请示例性实施例提供的一种子卡电路的结构示意图；
图6为本申请示例性实施例提供的一种服务器的结构示意图；
图7为本申请示例性实施例提供的一种上电方法的流程示意图；
图8为本申请示例性实施例提供的一种下电方法的流程示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施例及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1为本申请示例性实施例提供的一种应用场景的示意图。请参见图1，服务器中可以包括多个电源模块和多个组件。例如，多个电源模块可以分别为电源模块1、电源模块2、电源模块3、……、电源模块i；多个组件可以分别为组件1、组件2、组件3、……、组件j。
针对任意一个组件，可以通过对应的电源模块向组件进行供电。例如，电源模块1可以向组件1进行供电、电源模块2可以向组件2进行供电、……、电源模块i可以向组件j进行供电。
在相关技术中，电源控制电路可以根据各个电源模块输出的电压，确定电源状态，并根据电源状态对各个电源模块进行控制。然而，在上述过程中，电压通常会受到电路中其他信号的影响而产生波动，导致确定电源状态的准确性低，进而导致电源控制电路对多个电源模块进行控制的可靠性低。
在本申请实施例中，电源控制电路中可以包括总控电路和至少一个检测电路，检测电路中可以包括控制器和至少两个滤波器。由于可以通过至少两个滤波器对电源模块的初始电源信号进行滤波处理，进而通过控制器确定电源状态，相比通过各个电源模块输出的电压确定电源状态，提高了确定电源状态的准确性，进而提高了电源控制电路对多个电源模块进行控制的可靠性。
下面，通过具体实施例对本申请所示的技术方案进行详细说明。需要说明的是，下面几个实施例可以单独存在，也可以相互结合，对于相同或相似的内容，在不同的实施例中不再重复说明。
图2为本申请示例性实施例提供的一种电源控制电路的结构示意图。请参见图2，电源控制电路可以包括总控电路和至少一个检测电路。
电源控制电路可以为复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)， 是一种用户可以根据需求自行构造逻辑功能的数字集成电路。
可选地，至少一个检测电路可以分别为检测电路1、检测电路2、……、检测电路Q。Q为大于等于1的整数。
针对任意一个检测电路，检测电路中可以包括控制器和至少两个滤波器，至少两个滤波器与控制器串行连接，控制器与总控电路连接。
如图2中，检测电路1中可以包括滤波器11、滤波器12和控制器13。滤波器11可以与滤波器12串联，滤波器12可以与控制器13连接，控制器13可以与总控电路连接。
在一可选实施例中，至少两个滤波器可以用于获取被检测电源模块的初始电源信号，并对初始电源信号进行滤波处理，得到目标电源信号。
初始电源信号可以包括电源好(Power Good，PG)信号，和/或电源故障(Power Fail)信号。其中，PG信号用于表示电源可以正常工作，Power Fail信号用于表示电源异常。
可选地，PG信号可以用“1”表示，Power Fail信号可以用“0”表示。
目标电源信号可以是对初始电源信号进行滤波处理后得到的信号。
例如，如图2中，若被检测电源模块为电源模块1，初始电源信号1表示为“1110011110”，则检测电路1中的滤波器11可以获取该初始电源信号1，并通过滤波器11和滤波器12对初始电源信号1进行滤波处理，得到目标电源信号1。目标电源信号1可以表示为“1111111111”。
在一可选实施例中，控制器可以用于根据目标电源信号确定被检测电源模块的电源状态，并向总控电路发送电源状态。
可选地，电源状态可以包括正常状态或异常状态。
例如，若电源模块1对应的目标电源信号1为“1111111111”，则控制器可以根据该目标电源信号1确定电源模块1的电源状态为正常状态，并向总控电路发送该电源状态；若目标电源信号1为“1111100000”，则控制器可以根据该目标电源信号1确定电源模块1的电源状态为异常状态，并向总控电路发送该电源状态。
在一可选实施例中，总控电路可以用于根据接收到的电源状态控制至少一个检测电路的工作状态。
可选地，工作状态可以包括运行状态或暂停状态。
例如，如图2中，若总控电路接收到控制器13发送的电源状态1为正常状态，则总控电路可以根据该电源状态1，控制Q个检测电路的工作状态为运行状态，即该Q个检测电路正常工作；若总控电路接收到控制器23发送的的电源状态2为异常状态，则总控电 路可以根据该电源状态2，控制Q个检测电路的工作状态为暂停状态，即该Q个检测电路暂停工作。
在本申请实施例中，电源控制电路中可以包括总控电路和至少一个检测电路，检测电路中可以包括控制器和至少两个滤波器。至少两个滤波器可以获取被检测电源模块的初始电源信号，并对初始电源信号进行滤波处理，得到目标电源信号。控制器可以根据目标电源信号确定被检测电源模块的电源状态，并向总控电路发送电源状态。总控电路可以根据接收到的电源状态控制至少一个检测电路的工作状态。由于可以通过至少两个滤波器对电源模块的初始电源信号进行滤波处理，进而通过控制器确定电源状态，相比通过各个电源模块输出的电压确定电源状态，提高了确定电源状态的准确性，进而提高了电源控制电路对多个电源模块进行控制的可靠性。
下面，在图2所示实施例的基础上，结合图3，对上述电源控制电路进行进一步详细说明。
图3为本申请示例性实施例提供的另一种电源控制电路的结构示意图。请参见图3，可以包括至少一个电源模块和电源控制电路。
如图3中，至少一个电源模块可以分别为电源模块1、电源模块2、……、电源模块Q。
电源控制电路中可以包括总控电路和至少一个检测电路。任意一个检测电路中可以包括至少两个滤波器和控制器。至少两个滤波器中可以包括第一滤波器和第二滤波器，其中，第一滤波器的输入端与被检测电源模块连接，第一滤波器的输出端与第二滤波器的输入端连接，第二滤波器的输出端与控制器连接。
如图3中，检测电路1中可以包括第一滤波器11、第二滤波器12和控制器13。第一滤波器11的输入端可以与电源模块1连接，输出端可以与第二滤波器12的输入端连接，第二滤波器12的输出端可以与控制器13连接。
可选地，第一滤波器可以用于基于系统时钟频率对初始电源信号进行滤波处理，得到第一电源信号。第二滤波器可以用于基于预设时钟频率对第一电源信号进行滤波处理，得到目标电源信号。
系统时钟频率可以为人为预设的频率。例如，系统时钟频率可以为50MHz。
预设时钟频率可以为人为预设的频率。例如，预设时钟频率可以为2KHz。
在一可选实施例中，可以通过如下方式，得到第一电源信号：基于系统时钟频率，通过第一滤波器对初始电源信号进行采样处理，得到第一采样信号；若第一采样信号中存在第一突变信号，则在第一采样信号中滤除第一突变信号，得到第一电源信号， 第一突变信号的持续时长小于或等于M个系统时钟的时长，M为大于或等于1的整数。
第一采样信号中可以包括多个初始电源信号。例如，若初始电源信号可以用“0”和/或“1”表示，若连续进行5个采样，则第一采样信号可以为“11101”。
例如，若被检测电源模块为电源模块1，系统时钟频率为50MHz，则第一滤波器11可以每隔50MHz对初始电源信号1进行采样处理，得到第一采样信号。假设进行5次采样，得到的第一采样信号为“11101”。
第一突变信号可以是Power Fail信号，第一突变信号可以用“0”表示。
可选地，得到第一电源信号可以包括如下3种情况：
情况1：第一采样信号中不存在第一突变信号。
在该种情况下，则无需在第一采样信号中滤除第一突变信号，第一采样信号即为第一电源信号。
例如，若连续进行5次采样，第一采样信号为“11111”，不存在第一突变信号“0”，则无需在第一采样信号中滤除第一突变信号“0”，则第一电源信号为“11111”。
情况2：第一采样信号中存在第一突变信号，第一突变信号的持续时长小于或等于M个系统时钟的时长。
在该种情况下，由于第一突变信号的持续时长小于或等于M个系统时钟的时长，该第一突变信号可能是因为电路中脉冲宽度调制(Pulse width modulation，PWM)的高频影响所导致的，并非被检测电源模块存在异常所导致的，因此可以在第一采样信号滤除第一突变信号，以去除高频脉冲信号的影响，得到第一电源信号。
例如，若M为3，系统时钟频率可以为50MHz，3个系统时钟的时长可以为60ns(纳秒)，若连续进行5次采样，第一采样信号为“11001”，其中2个第一突变信号“0”的持续时长为40ns，则由于2个第一突变信号“0”的持续时长40ns小于3个系统时钟的时长60ns，则可以对第一采样信号进行滤除处理，得到第一电源信号为“11111”。
情况3：第一采样信号中存在第一突变信号，第一突变信号的持续时长大于M个系统时钟的时长。
在该种情况下，由于第一突变信号的持续时长大于M个系统时钟的时长，该第一突变信号很可能是被检测电源模块存在异常所导致的，则在第一采样信号中可以不滤除第一突变信号，得到第一电源信号。
例如，若M为3，系统时钟频率可以为50MHz，3个系统时钟的时长可以为60ns，若连续进行5次采样，第一采样信号为“10000”，其中4个第一突变信号“0”持续的时长为80ns，则4个第一突变信号“0”的持续时长80ns大于3个系统时钟的时长60ns， 则在第一采样信号中可以不滤除第一突变信号，得到第一电源信号为“10000”。
第一滤波器得到第一电源信号之后，可以向第二滤波器输出第一电源信号，以使第二滤波器对第一电源信号，得到目标电源信号。
在一可选实施例中，可以通过如下方式，得到目标电源信号：基于预设时钟频率，通过第二滤波器对第一电源信号进行采样处理，得到第二采样信号；若第二采样信号中存在第二突变信号，则在第二采样信号中滤除第二突变信号，得到目标电源信号，第二突变信号的持续时长小于或等于N个预设时钟的时长，N为大于或等于1的整数。
例如，若被检测电源模块为电源模块1，预设时钟频率可以为2KHz，如第一电源信号1为“10000”，则第二滤波器12可以每隔2KHz对第一电源信号1进行采样处理，得到第二采样信号。假设进行4次采样，得到的第二采样信号可以为“1000”。
第二突变信号可以是Power Fail信号，第二突变信号可以用“0”表示。
可选地，得到目标电源信号可以包括如下3种情况：
情况1：第二采样信号中不存在第二突变信号。
在该种情况下，则无需在第二采样信号中滤除第二突变信号，第二采样信号即为目标电源信号。
例如，若连续进行4次采样，第二采样信号为“1111”，不存在第二突变信号“0”，则无需在第二采样信号中滤除第二突变信号“0”，则目标电源信号为“1111”。
情况2：第二采样信号中存在第二突变信号，第二突变信号的持续时长小于或等于N个预设时钟的时长。
在该种情况下，由于第二突变信号的持续时长小于或等于N个预设时钟的时长，该第二突变信号可能是因为电路中高驱动能力信号的快速跳变造成的干扰，和/或一些低速信号接口的干扰所导致的，则可以在第二采样信号中滤除第二突变信号，得到目标电源信号。
例如，若N为2，预设时钟频率为20KHz，2个预设时钟的时长可以为100us(微秒)，若进行4次采样，第二采样信号为“1101”，其中1个第二突变信号“0”的持续时长为50us，则由于第二突变信号“0”的持续时长50us小于2个预设时钟的时长100us，则可以对第二采样信号进行滤波处理，得到目标电源信号为“1111”。
情况3：第二采样信号中存在第二突变信号，第二突变信号的持续时长大于N个预设时钟的时长。
在该种情况下，由于第二突变信号的持续时长大于N个预设时钟的时长，该第二突变信号很可能是第一电源信号异常所导致的，则在第二采样信号中可以不滤除第二 突变信号，得到目标电源信号。
例如，若N为2，预设时钟频率为20KHz，2个预设时钟的时长可以为100us(微秒)，若进行4次采样，第二采样信号为“1000”，其中3个第二突变信号“0”的持续时长为150us，则由于第二突变信号“0”的持续时长50us大于2个预设时钟的时长100us，则在第二采样信号中可以不滤除第二突变信号，得到目标电源信号为“1000”。
可选地，经过第一滤波器和第二滤波器的滤除处理，可以使得目标电源信号更准确地反映被检测电源模块的电源状态。
得到目标电源信号之后，第二滤波器可以向控制器输出目标电源信号，以使控制器根据目标电源信号，确定被检测电源模块的电源状态。
可选地，控制器确定电源状态可以包括如下2种情况：
情况1：目标电源信号中不存在K位预设信号。
可选地，预设信号可以用“0”表示。K可以为大于或等于1的整数。
在该种情况下，控制器可以根据目标电源信号，确定被检测电源模块的电源状态为正常状态。
例如，若K为1，被检测电源模块为电源模块1，对应的目标电源信号1为“1111”，则由于目标电源信号1中不存在预设信号“0”，则控制器13可以确定电源模块1的电源状态为正常状态。
情况2：确定目标电源信号中存在K位预设信号。
在该种情况下，控制器可以根据目标电源信号，确定被检测电源模块的电源状态为异常状态。
例如，若K为1，被检测电源模块为电源模块1，对应的目标电源信号1为“1000”，则由于目标电源信号1中存在3个预设信号“0”，则控制器13可以确定电源模块1的电源状态为异常状态。
控制器确定电源模块的电源状态之后，可以向总控电路输出该电源状态，总控电路可以根据电源状态，控制至少一个检测电路的工作状态。
可选地，针对任意一个检测电路，可以对检测电路设置不同的时间窗口，在时间窗口内，检测电路中的第一滤波器、第二滤波器和控制器进行正常运行。例如，检测电路的时间窗口的时长可以为检测电路所在设备启动直至关闭之间的时长。
可选地，总控电路可以根据电源状态，控制至少一个检测电路的工作状态可以分为如下2种情况：
情况1：接收到的电源状态为正常状态。
在该种情况下，总控电路可以控制至少一个检测电路的工作状态为运行状态。
例如，如图3中，若控制器13向总控电路输送的电源状态1为正常状态，则总控电路接收到电源状态1之后，由于电源状态1为正常状态，则说明不存在异常，则至少一个检测电路可以继续正常运行。
情况2：接收到的电源状态为异常状态。
在该种情况下，则说明至少一个电源模块存在异常。由于多个电源模块之间可能会互相影响，导致其他电源模块发生异常，进而导致其他电源模块对应的检测电路确定电源状态为异常状态，最终导致总控电路无法确定第一个发生异常的电源模块，因此当接收到至少一个电源状态为异常状态时，总控电路可以向至少一个检测电路发送加锁信号，以指示至少一个检测电路将工作状态切换为暂停状态，使至少一个检测电路不再向总控电路发送电源状态，便于总控电路确定第一个发生异常的电源模块。
可选地，加锁信号可以用“lock”表示。
例如，如图3中，若控制器13向总控电路输送的电源状态1为异常状态，则总控电路接收到电源状态1之后，可以向Q个检测电路发送加锁信号lock，以指示Q个检测电路将工作状态切换为暂停状态，使Q个检测电路不再向总控电路发送电源状态，便于总控电路确定第一个发生异常的电源模块为电源模块1。
可选地，若多个控制器同时向总控电路发送的多个电源状态均为异常状态，则总控电路还可以根据每个控制器发送的电源状态的优先级，综合形成故障信息，并向读写模块发送该故障信息，以使读写模块记录多个电源模块的电源状态。
可选地，电源控制电路的控制过程可以通过代码的方式实现。
在本申请实施例中，电源控制电路中可以包括总控电路和至少一个检测电路，检测电路中可以包括控制器、第一滤波器和第二滤波器。第一滤波器可以对初始电源信号进行滤波处理，得到第一电源信号，第二滤波器可以对第一电源信号进行滤波处理，得到目标电源信号。控制器可以根据目标电源信号确定电源模块的电源状态，并向总控电路发送电源状态。总控电路可以根据接收到的电源状态控制至少一个检测电路的工作状态。由于可以通过至少两个滤波器对电源模块的初始电源信号进行滤波处理，进而通过控制器确定电源状态，相比通过各个电源模块输出的电压确定电源状态，提高了确定电源状态的准确性，进而提高了电源控制电路对多个电源模块进行控制的可靠性。
下面，在上述任一实施例的基础上，结合图4，提供一种主板电路的结构示意图。
图4为本申请示例性实施例提供的一种主板电路的结构示意图。请参见图4，主板电路中可以包括电源控制电路和至少一个电源模块。
如图4，至少一个电源模块可以分别为电源模块1、电源模块2、……、电源模块Q。针对任意一个电源模块，电源可以生成初始电源信号。例如，电源模块1可以生成初始电源信号1。
可选地，初始电源信号中可以包括PG信号和Power Fail信号。若电源模块的电压为低电压，则可以生成Power Fail信号“0”；若电源模块的电压为高电压，则可以生成PG信号“1”。例如，若电源模块1的电压为“高高低低高”，则可以生成对应的初始电源信号1为“11001”。
电源控制电路中可以包括总控电路和至少一个检测电路。
针对任意一个检测电路，检测电路可以分别与对应的电源模块连接。如图4，检测电路1可以与电源模块1连接、检测电路2可以与电源模块2连接、……、检测电路Q可以与电源模块Q连接。
针对任意一个检测电路，检测电路中可以包括第一滤波器、第二滤波器和控制器。其中，第一滤波器的输入端与被检测电源模块连接，第一滤波器的输出端与第二滤波器的输入端连接；第二滤波器的输出端与控制器连接。
第一滤波器可以用于基于系统时钟频率对初始电源信号进行滤波处理，得到第一电源信号。
第二滤波器可以用于基于预设时钟频率对第一电源信号进行滤波处理，得到目标电源信号。
需要说明的是，得到第一电源信号和得到目标电源信号的具体执行过程，可以参见图3中得到第一电源信号和得到目标电源信号的具体执行过程，此处不再进行赘述。
第二滤波器确定目标电源信号之后，可以向控制器输出目标电源信号。控制器可以根据目标电源信号确定被检测电源模块的电源状态。电源状态可以分为正常状态和异常状态。
需要说明的是，控制器确定被检测电源模块的电源状态的具体执行过程，可以参见图3中控制器确定被检测电源模块的电源状态的具体执行过程，此处不再进行赘述。
控制器确定被检测电源模块的电源状态之后，可以向总控电路输出该电源状态，总控电路可以根据电源状态，控制至少一个检测电路的工作状态。工作状态可以分为运行状态或暂停状态。
可选地，若总控电路接收到的电源状态为异常状态，则总控电路可以根据电源状态，向至少一个检测电路发送加锁信号，指示至少一个检测电路将工作状态切换为暂停状态，使至少一个检测电路不再向总控电路发送电源状态，便于总控电路确定第一 个发生异常的被检测电源模块。
在本申请实施例中，主板电路中可以包括电源控制电路和至少一个电源模块。电源控制电路中可以包括总控电路和至少一个检测电路，检测电路中可以包括控制器、第一滤波器和第二滤波器。第一滤波器可以对初始电源信号进行滤波处理，得到第一电源信号，第二滤波器可以对第一电源信号进行滤波处理，得到目标电源信号。控制器可以根据目标电源信号确定被检测电源模块的电源状态，并向总控电路发送电源状态。总控电路可以根据接收到的电源状态控制至少一个检测电路的工作状态。由于可以通过至少两个滤波器对电源模块的初始电源信号进行滤波处理，进而通过控制器确定电源状态，相比通过各个电源模块输出的电压确定电源状态，提高了确定电源状态的准确性，进而提高了电源控制电路对多个电源模块进行控制的可靠性。
图5为本申请示例性实施例提供的一种子卡电路的结构示意图。请参见图5，子卡电路中可以包括电源控制电路和至少一个电源模块。
如图5，至少一个电源模块可以分别为电源模块1、电源模块2、……电源模块P。针对任意一个电源模块，电源模块可以生成初始电源信号。例如，电源模块1可以生成初始电源信号1。
电源控制电路中可以包括总控电路和至少一个检测电路。
针对任意一个检测电路，检测电路可以分别与对应的电源模块连接。如图5，检测电路1可以与电源模块1连接、检测电路2可以与电源模块2连接、……、检测电路P可以与电源模块P连接。
针对任意一个检测电路，检测电路中可以包括第一滤波器、第二滤波器和控制器。其中，第一滤波器的输入端与被检测电源模块连接，第一滤波器的输出端与第二滤波器的输入端连接；第二滤波器的输出端与控制器连接。
第一滤波器可以用于基于系统时钟频率对初始电源信号进行滤波处理，得到第一电源信号。
第二滤波器可以用于基于预设时钟频率对第一电源信号进行滤波处理，得到目标电源信号。
需要说明的是，得到第一电源信号和得到目标电源信号的具体执行过程，可以参见图3中得到第一电源信号和得到目标电源信号的具体执行过程，此处不再进行赘述。
第二滤波器确定目标电源信号之后，可以向控制器输出目标电源信号。控制器可以根据目标电源信号确定被检测电源模块的电源状态。电源状态可以分为正常状态和异常状态。
需要说明的是，控制器确定被检测电源模块的电源状态的具体执行过程，可以参见图3中控制器确定被检测电源模块的电源状态的具体执行过程，此处不再进行赘述。
控制器确定被检测电源模块的电源状态之后，可以向总控电路输出该电源状态，总控电路可以根据电源状态，控制至少一个检测电路的工作状态。工作状态可以分为运行状态或暂停状态。
可选地，若总控电路接收到的电源状态为异常状态，则总控电路可以根据电源状态，向至少一个检测电路发送加锁信号，指示至少一个检测电路将工作状态切换为暂停状态，使至少一个检测电路不再向总控电路发送电源状态，便于总控电路确定第一个发生异常的被检测电源模块。
在本申请实施例中，子卡电路中可以包括电源控制电路和至少一个电源模块。电源控制电路中可以包括总控电路和至少一个检测电路，检测电路中可以包括控制器、第一滤波器和第二滤波器。第一滤波器可以对初始电源信号进行滤波处理，得到第一电源信号，第二滤波器可以对第一电源信号进行滤波处理，得到目标电源信号。控制器可以根据目标电源信号确定被检测电源模块的电源状态，并向总控电路发送电源状态。总控电路可以根据接收到的电源状态控制至少一个检测电路的工作状态。由于可以通过至少两个滤波器对电源模块的初始电源信号进行滤波处理，进而通过控制器确定电源状态，相比通过各个电源模块输出的电压确定电源状态，提高了确定电源状态的准确性，进而提高了电源控制电路对多个电源模块进行控制的可靠性。
下面，在上述任一实施例的基础上，结合图6，提供一种服务器的结构示意图。
图6为本申请示例性实施例提供的一种服务器的结构示意图。请参见图6，服务器中可以包括主板电路和至少一个子卡电路。
主板电路中可以包括电源控制电路和至少一个电源模块。电源控制电路中可以包括至少一个检测电路和总控电路。
至少一个子卡电路可以分别为子卡电路1、……、子卡电路S。S为大于等于1的整数。
针对任意一个子卡电路，子卡电路中可以包括电源控制电路和至少一个电源模块。电源控制电路中可以包括至少一个检测电路和总控电路。
可选地，主板电路中的电源控制电路和子卡电路中的电源控制电路连接。例如，如图6中，主板电路中的电源控制电路1可以和子卡电路1中的电源控制电路2连接。
针对主板电路或子卡电路中的任意一个电源控制电路，电源控制电路中可以包括总控电路和至少一个检测电路，检测电路中可以包括控制器、第一滤波器和第二滤波器。第一滤波器可以对初始电源信号进行滤波处理，得到第一电源信号，第二滤波器可以对第一电 源信号进行滤波处理，得到目标电源信号。控制器可以根据目标电源信号确定被检测电源模块的电源状态，并向总控电路发送电源状态。总控电路可以根据接收到的电源状态控制至少一个检测电路的工作状态。
需要说明的是，控制器、第一滤波器和第二滤波器、以及总控电路的具体作用可以参见上述任一实施例中所示的内容，此处不再进行赘述。
当电源控制电路位于子卡电路中时，总控电路可以用于接收主板电路中的电源控制电路通过上下点接口发送的第一电控制信号、以及通过总线接口发送的第二电控制信号；根据第一电控制信号和第二电控制信号，控制子卡电路中的电源模块上电或者下电。
上下点接口是指主板电路与子卡电路之间的通信接口。例如，上下点接口可以为串行通用输入/输出(Serial General Purpose Input/Output，SGPIO)接口。
第一电控制信号可以是主板电路与子卡电路之间的通信信号。
总线接口是指主板电路与子卡电路之间的物理总线接口。
第二电控制信号可以为上电信号、或下电信号。
如图6中，主板电路中的总控电路1可以通过上下点接口，向子卡电路中的总控电路2发送第一电控制信号，并通过总线接口向总控电路2发送第二电控制信号，则子卡电路中的总控电路2可以根据第一电控制信号和第二电控制信号，控制子卡电路中的电源模块上电或者下电。
可选地，若第一电控制信号和/或第二电控制信号指示上电，则可以控制子卡电路中的电源模块上电；若第一电控制信号和第二电控制信号分别指示下电，则可以控制子卡电路中的电源模块下电。
下面，结合图7，对控制子卡电路中的电源模块上电的过程进行说明。
图7为本申请示例性实施例提供的一种上电方法的流程示意图。请参见图7，该方法可以包括：
S701、确定电源模块的初始状态。
子卡电路中的总控电路可以确定子卡电路中电源模块的初始状态。初始状态可以分为下电状态和上电状态。
若电源模块的初始状态为下电状态，则可以执行S702～S704。
S702、判断第一电控制信号是否指示上电。
子卡电路中的总控电路可以判断第一电控制信号是否指示上电，若否，则可以执行S703；若是，则可以执行S704。
S703、判断第二电控制信号是否指示上电。
子卡电路中的总控电路可以判断第二电控制信号是否指示上电，若是，则可以执行S704；若否，则说明第一电控制信号和第二电控制信号均不指示上电，则可以保持电源模块的初始状态，即下电状态。
S704、控制电源模块上电。
若步骤S702中判断第一电控制信号指示上电，和/或步骤S703中判断第二电控制信号为指示上电，两者满足其一，则子卡电路中的总控电路可以控制子卡电路中的电源模块上电。
下面，结合图8，对控制子卡电路中的电源模块下电的过程进行说明。
图8为本申请示例性实施例提供的一种下电方法的流程示意图。请参见图8，该方法可以包括：
S801、确定电源模块的初始状态。
子卡电路中的总控电路可以确定子卡电路中电源模块的初始状态。初始状态可以分为下电状态和上电状态。
若电源模块的初始状态为上电状态，则可以执行S802～S804。
S802、判断第一电控制信号是否指示下电。
子卡电路中的总控电路可以判断第一电控制信号是否指示下电，若是，则可以执行S803；若否，则保持电源模块的初始状态，即上电状态。
S803、判断第二电控制信号是否指示下电。
子卡电路中的总控电路可以判断第二电控制信号是否指示下电，若是，则可以执行S804；若否，则可以保持电源模块的初始状态，即上电状态。
S804、控制电源模块下电。
若步骤S802中判断第一电控制信号指示下电，并且步骤S803中判断第二电控制信号为指示下电，两者均满足，则子卡电路中的总控电路可以控制子卡电路中的电源模块下电。
通过图8所示的流程，子卡电路中的总控电路可以根据第一电控制信号和第二电控制信号，双重确定是否控制电源模块下电，提高了对电源模块进行控制的可靠性。
可选地，若子卡电路中的总控电路接收到控制器发送的电源状态为异常状态，子卡电路中的总控电路可以向主板电路中的总控电路，发送故障信息，该故障信息中可以包括电源状态。主板电路可以根据系统策略和故障信息，进行相应的处理。
在本申请实施例中，服务器中可以包括主板电路和至少一个子卡电路。主板电路和子卡电路中分别可以包括电源控制电路和至少一个电源模块。任意一个电源控制电路中可以 包括总控电路和至少一个检测电路，检测电路中可以包括控制器、第一滤波器和第二滤波器。第一滤波器可以对初始电源信号进行滤波处理，得到第一电源信号，第二滤波器可以对第一电源信号进行滤波处理，得到目标电源信号。控制器可以根据目标电源信号确定被检测电源模块的电源状态，并向总控电路发送电源状态。总控电路可以根据接收到的电源状态控制至少一个检测电路的工作状态。子卡电路中的总控电路还可以根据第一电控制信号和第二电控制信号，控制子卡电路中电源模块上下电。由于可以通过至少两个滤波器对电源模块的初始电源信号进行滤波处理，进而通过控制器确定电源状态，相比根据对各个电源模块输出的电压确定电源状态，提高了确定电源状态的准确性；并且子卡电路中的总控电路可以根据第一电控制信号和第二电控制信号，双重确定电源模块是否下电，提高了服务器中电源控制电路对多个电源模块进行控制的可靠性。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在一个典型的配置中，计算设备包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (12)

  1. 一种电源控制电路，其特征在于，包括总控电路和至少一个检测电路，所述检测电路包括控制器和至少两个滤波器，所述至少两个滤波器与所述控制器串行连接，所述控制器与所述总控电路连接；其中，
    所述至少两个滤波器用于获取被检测电源模块的初始电源信号，并对所述初始电源信号进行滤波处理，得到目标电源信号；
    所述控制器用于根据所述目标电源信号确定所述被检测电源模块的电源状态，并向所述总控电路发送所述电源状态；
    所述总控电路用于根据接收到的电源状态控制所述至少一个检测电路的工作状态，所述工作状态包括运行状态或暂停状态。
  2. 根据权利要求1所述的电路，其特征在于，所述至少两个滤波器包括第一滤波器和第二滤波器，其中，
    所述第一滤波器的输入端用于与所述被检测电源模块连接，所述第一滤波器的输出端与所述第二滤波器的输入端连接；
    所述第二滤波器的输出端与所述控制器连接。
  3. 根据权利要求2所述的电路，其特征在于，
    所述第一滤波器用于基于系统时钟频率对所述初始电源信号进行滤波处理，得到第一电源信号；
    所述第二滤波器用于基于预设时钟频率对所述第一电源信号进行滤波处理，得到所述目标电源信号。
  4. 根据权利要求3所述的电路，其特征在于，所述第一滤波器具体用于：
    基于所述系统时钟频率，对所述初始电源信号进行采样处理，得到第一采样信号；
    若所述第一采样信号中存在第一突变信号，则在所述第一采样信号中滤除所述第一突变信号，得到所述第一电源信号，所述第一突变信号的持续时长小于或等于M个所述系统时钟的时长，所述M为大于或等于1的整数。
  5. 根据权利要求3所述的电路，其特征在于，所述第二滤波器具体用于：
    基于所述预设时钟频率，对所述第一电源信号进行采样处理，得到第二采样信号；
    若所述第二采样信号中存在第二突变信号，则在所述第二采样信号中滤除所述第二突变信号，得到所述目标电源信号，所述第二突变信号的持续时长小于或等于N个所述预设时钟的时长，所述N为大于或等于1的整数。
  6. 根据权利要求1-5任一项所述的电路，其特征在于，所述控制器具体用于：
    在确定所述目标电源信号中存在K位预设信号时，确定所述电源状态为异常状态，所述K为大于或等于1的整数。
  7. 根据权利要求1-6任一项所述的电路，其特征在于，所述总控电路具体用于：
    若接收到的所述电源状态为异常状态，则向所述至少一个检测电路发送加锁信号，所述加锁信号用于指示所述至少一个检测电路将工作状态切换为所述暂停状态。
  8. 根据权利要求1-7任一项所述的电路，其特征在于，所述电源控制电路位于子卡电路中；所述总控电路还用于：
    接收主板电路中的电源控制电路通过上下点接口发送的第一电控制信号、以及通过总线接口发送的第二电控制信号；
    根据所述第一电控制信号和所述第二电控制信号，控制所述子卡电路中的电源模块上电或者下电。
  9. 根据权利要求8所述的电路，其特征在于，所述总控电路具体用于：
    在所述第一电控制信号和/或所述第二电控制信号指示上电时，控制所述子卡电路中的电源模块上电；
    在所述第一电控制信号和所述第二电控制信号分别指示下电时，控制所述子卡电路中的电源模块下电。
  10. 一种主板电路，其特征在于，包括权利要求1-9任一项所述的电源控制电路和至少一个电源模块，其中，所述电源控制电路中的至少一个检测电路分别与对应的电源模块连接。
  11. 一种子卡电路，其特征在于，包括权利要求1-9任一项所述的电源控制电路和至少一个电源模块，其中，所述电源控制电路中的至少一个检测电路分别与对应的电源模块连接。
  12. 一种服务器，其特征在于，包括权利要求10所述的主板电路和至少一个权利要求11所述的子卡电路，其中，所述主板电路中的电源控制电路和所述子卡电路中的电源控制电路连接。
PCT/CN2023/130306 2022-11-09 2023-11-07 电源控制电路及服务器 WO2024099333A1 (zh)

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