WO2024098686A1 - 半导体结构、半导体结构的形成方法及存储器 - Google Patents

半导体结构、半导体结构的形成方法及存储器 Download PDF

Info

Publication number
WO2024098686A1
WO2024098686A1 PCT/CN2023/092035 CN2023092035W WO2024098686A1 WO 2024098686 A1 WO2024098686 A1 WO 2024098686A1 CN 2023092035 W CN2023092035 W CN 2023092035W WO 2024098686 A1 WO2024098686 A1 WO 2024098686A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
support
layers
semiconductor structure
support layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/092035
Other languages
English (en)
French (fr)
Inventor
郭敬云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Publication of WO2024098686A1 publication Critical patent/WO2024098686A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure, a method for forming a semiconductor structure, and a memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell may be composed of a transistor and a capacitor structure controlled by the transistor.
  • the quality of the capacitor structure directly affects the performance of DRAM. In related technologies, the risk of collapse or bending of the capacitor structure is relatively high.
  • the embodiments of the present disclosure provide a semiconductor structure, a method for forming a semiconductor structure, and a memory, which can reduce the risk of collapse or bending of the capacitor structure and improve the overall stability and yield of the semiconductor structure.
  • An embodiment of the present disclosure provides a semiconductor structure, which includes: a plurality of lower electrodes, separated on a substrate; N supporting layers, arranged between the plurality of lower electrodes to support the lower electrodes, and arranged sequentially along their deposition direction; N is greater than or equal to 2; wherein the etching resistance of the supporting layers from the 1st layer to the Nth layer increases layer by layer.
  • the material of the N-th support layer includes: silicon carbon nitride material; wherein the carbon content of the support layer from the 1st layer to the Nth layer increases layer by layer.
  • the carbon content of the support layers from the first layer to the Nth layer is greater than or equal to 0.24% and less than or equal to 0.3%.
  • N 4; wherein the carbon content of the first support layer is 0.24%, the carbon content of the second support layer is 0.26%, the carbon content of the third support layer is 0.28%, and the carbon content of the fourth support layer is 0.3%.
  • the thickness of the Nth supporting layer is greater than the thickness of any layer among the 1st to the N-1th supporting layers; the sum of the thicknesses of the N supporting layers is less than or equal to a preset threshold.
  • the top height of the Nth support layer is less than or equal to the top height of any one of the lower electrodes.
  • the process technology of the semiconductor structure is less than or equal to 55nm.
  • An embodiment of the present disclosure also provides a method for forming a semiconductor structure, the method comprising: providing a substrate; forming a plurality of discrete lower electrodes on the substrate; alternately depositing N sacrificial layers and N supporting layers between the plurality of lower electrodes; N is greater than or equal to 2; wherein the etching resistance of the supporting layers from the 1st layer to the Nth layer increases layer by layer; and removing the N sacrificial layers in sequence along the reverse deposition direction, while retaining the N supporting layers.
  • the method for depositing N layers of the support layer includes: placing the substrate in a reaction chamber; introducing a mixed gas containing at least a first gas and a second gas into the reaction chamber and reacting to deposit and form each layer of the support layer; wherein the flow rate of the first gas decreases layer by layer.
  • the first gas includes: ammonia; the second gas includes: methane.
  • the flow rate of the first gas corresponding to each supporting layer is greater than or equal to 160 slm and less than or equal to 200 slm.
  • N 4; wherein, the flow rate of the first gas corresponding to the first supporting layer is 200slm; the flow rate of the first gas corresponding to the second supporting layer is 180slm; the flow rate of the first gas corresponding to the third supporting layer is 170slm; and the flow rate of the first gas corresponding to the fourth supporting layer is 160slm.
  • the material of the N-layer sacrificial layer includes borophosphosilicate glass and silicon oxide.
  • the embodiment of the present disclosure also provides a memory, which includes the semiconductor structure as described in the above solution.
  • the memory is DRAM.
  • the embodiments of the present disclosure provide a method for forming a semiconductor structure, a semiconductor structure and a memory.
  • the semiconductor structure includes: a plurality of lower electrodes and N supporting layers.
  • the plurality of lower electrodes are separated on the substrate.
  • the N supporting layers are arranged between the plurality of lower electrodes to support the lower electrodes, and are arranged sequentially along the deposition direction thereof; N is greater than or equal to 2.
  • the etching resistance of the 1st to the Nth supporting layers increases layer by layer. Since in the process of forming the semiconductor structure, the supporting layer at the top will be etched the most times, and the number of etchings received by the supporting layers below the top decreases successively. Therefore, the etching resistance of the 1st to the Nth supporting layers increases layer by layer, which can ensure that each supporting layer has better uniformity, reduce the risk of collapse or bending of the capacitor structure, and thus improve the overall stability and yield of the semiconductor structure.
  • FIG1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG2 is a second schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG3A is a third schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG3B is a fourth schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG4A is a fifth schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG4B is a sixth schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG5 is a flowchart 1 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG6 is a schematic diagram 1 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG7 is a second schematic diagram of a method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG8 is a third schematic diagram of a method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG9 is a second flow chart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG10 is a rendering of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a memory provided in an embodiment of the present disclosure.
  • first/second the terms “first/second/third” involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that “first/second/third” can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.
  • a layer/element when referred to as being "on" another layer/element, the layer/element can be directly on the other layer/element or there can be an intervening layer/element therebetween.
  • the layer/element if a layer/element is "on” another layer/element in one orientation, the layer/element can be "under” the other layer/element when the orientation is reversed.
  • FIG1 is an optional structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, and FIG1 is a cross-sectional view.
  • the semiconductor structure includes: a plurality of lower electrodes 20 and an N-layer support layer 30.
  • the plurality of lower electrodes 20 are separated on a substrate 10.
  • the N-layer support layer 30 is disposed between the plurality of lower electrodes 20 to support the lower electrodes 20.
  • the N-layer support layer 30 is arranged in sequence along its deposition direction Z, and N is greater than or equal to 2. Among them, the etching resistance of the first to N-th support layers 30 increases layer by layer.
  • the substrate 10 may be a silicon (Si) substrate, a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a germanium on insulator (GOI) substrate, a silicon germanium (SiGe) substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG).
  • Si silicon
  • SOI silicon on insulator
  • Ge germanium
  • GOI germanium on insulator
  • SiGe silicon germanium
  • III-V compound semiconductor substrate a III-V compound semiconductor substrate
  • SEG selective epitaxial growth
  • an active region, an interlayer dielectric layer, a bit line, a word line and other structures are formed on a substrate 10.
  • a lower electrode 20 can be formed above the active region.
  • a dielectric layer 11 is also formed on the substrate 10, and the dielectric layer 11 is located at the bottom of the lower electrode 20.
  • the material of the lower electrode 20 may be at least one of metal, conductive metal compound, and doped polysilicon, such as a high melting point metal (e.g., cobalt, titanium, nickel,
  • the present invention may include one or more of a conductive oxide (e.g., SrRuO3, RuO3, CaRuO3) and a conductive oxide (e.g., tungsten or molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN) or tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru) or i
  • a noble metal e.g., platinum
  • FIG2 is a three-dimensional structural diagram corresponding to FIG1.
  • a plurality of lower electrodes 20 are arranged separately, and each lower electrode 20 extends along a direction Z.
  • N layers of support layers 30 are disposed between the plurality of lower electrodes 20 to support the lower electrodes 20 and prevent the lower electrodes 20 from collapsing or bending; each layer of support layer 30 extends along a plane perpendicular to the direction Z.
  • four support layers 30 are arranged in sequence along the deposition direction Z, that is, the first to fourth support layers 30 are sequentially formed above the dielectric layer 11 , and the fourth support layer 30 is located at the top.
  • sacrificial layers will be deposited and formed simultaneously in the gaps between the N layers of support layers 30. After all the support layers 30 and sacrificial layers are formed, the sacrificial layers are sequentially etched and removed along the reverse deposition direction (i.e., the direction opposite to the deposition of the support layers 30), while the support layers 30 are retained. Therefore, the support layer 30 located at the top (i.e., the 4th support layer 30 in FIG. 1 and FIG. 2) will be etched the most times; the number of etchings received by the support layers 30 below the top will decrease in sequence. In other words, referring to FIG. 1 and FIG.
  • the 4th support layer 30 will be etched the most times, and then, the 3rd support layer 30 will be etched less than the 4th support layer 30, the 2nd support layer 30 will be etched less than the 3rd support layer 30, and the 1st support layer 30 will be etched less than the 2nd support layer 30.
  • the etching resistance of the first to fourth support layers 30 increases layer by layer, that is, the etching resistance of the first support layer 30 is the lowest, and the etching resistance of the fourth support layer 30 is the highest.
  • each support layer 30 has better WIW uniformity (with in wafer uniformity, thickness uniformity inside the wafer), so that it can effectively support the lower electrode 20, reduce the risk of collapse or bending of the lower electrode 20, that is, reduce the risk of collapse or bending of the capacitor structure, and improve stability.
  • it can reduce the occurrence of cell leakage (Cell LKG) between capacitors and improve overall performance and yield.
  • the shapes of the lower electrode 20 and the upper electrode 21 can both be cylindrical.
  • the lower electrode 20, the upper electrode 21, and the dielectric layer 22 together constitute a capacitor structure, wherein the lower electrode 20 and the upper electrode 21 constitute the two poles of the capacitor structure, and the dielectric layer 22 is filled between the lower electrode 20 and the upper electrode 21.
  • the shape of the lower electrode 20 may be a cylindrical shape
  • the shape of the upper electrode 21 may be a sleeve shape.
  • the lower electrode 20, the upper electrode 21, and the dielectric layer 22 together constitute a capacitor structure.
  • the lower electrode 20 and the upper electrode 21 may be cylindrical.
  • the lower electrode 20 and the upper electrode 21 constitute two electrodes of the capacitor structure, and the dielectric layer 22 is filled between the lower electrode 20 and the upper electrode 21 .
  • the material of the N-layer support layer 30 includes: silicon carbon nitride (SiCN) material, wherein the carbon content of the first to N-th support layers 30 increases layer by layer.
  • SiCN silicon carbon nitride
  • the support layer 30 formed of SiCN material has extremely high hardness, high temperature oxidation resistance, high temperature creep resistance, low friction coefficient, adjustable optical properties and many other excellent properties, and can effectively support the lower electrode 20.
  • the support layer 30 of SiCN material can be formed by LPCVD (low pressure chemical vapor deposition) process, PECVD (plasma enhanced chemical vapor deposition) process or ALD (atomic layer deposition) process.
  • the carbon content of the second to Nth support layers 30 increases layer by layer. Since in SiCN material, C-Si bonds are more stable than N-Si bonds. The higher the carbon content in the support layer 30, the higher the amount of carbon and silicon elements combined, the higher the proportion of C-Si bonds, and thus, the support layer 30 has stronger etching resistance.
  • the N-layer support layer 30 is formed with SiCN material, and at the same time, the carbon content of the 2nd to Nth support layers 30 increases layer by layer. In this way, the carbon content of the 2nd to Nth support layers 30 increases layer by layer, which ensures that after the sacrificial layer is etched away, each support layer 30 has better uniformity, thereby reducing the risk of collapse or bending of the lower electrode 20.
  • each support layer 30 is greater than or equal to 0.24% and less than or equal to 0.3%.
  • the carbon content of the first support layer is 0.24%
  • the carbon content of the second support layer is 0.26%
  • the carbon content of the third support layer is 0.28%
  • the carbon content of the fourth support layer is 0.3%.
  • the thickness of the Nth support layer 30 is greater than the thickness of any layer from the 1st to the N-1th support layers 30.
  • the thickness of the 4th support layer 30 in FIG1 is greater than the thickness of any layer from the 1st to the 3rd support layers 30.
  • the Nth support layer 30 located at the top will be etched the most times, setting the thickness of the Nth support layer 30 to be greater than the thickness of any other support layer 30 can improve the strength of the Nth support layer 30, ensure that each support layer 30 has better uniformity, and reduce the risk of collapse or bending of the lower electrode 20.
  • the sum of the thicknesses of N supporting layers 30 is less than or equal to a preset threshold.
  • the support layer 30 will affect the deposition of the dielectric layer 22 in the capacitor structure; if the sum of the thicknesses of the N-layer support layer 30 is too large, it will have a significant impact on the deposition of the dielectric layer 22, thereby affecting the performance of the formed capacitor structure. Therefore, in the process of forming the N-layer support layer 30 , the sum of the thicknesses of the N-layer support layer 30 is controlled to be less than or equal to a preset threshold value, so that a significant impact on the deposition of the dielectric layer 22 can be avoided, thereby ensuring the stable performance of the formed capacitor structure.
  • the Nth support layer in the deposition direction Z, is less than or equal to the top height of any lower electrode 20. In this way, it is possible to ensure that the N-layer support layer 30 effectively supports the lower electrode 20, thereby reducing the risk of collapse or bending of the lower electrode 20.
  • the semiconductor structure shown in FIG. 1 and FIG. 2 has a process technology less than or equal to 55 nm and a wafer size greater than or equal to 8 inches.
  • the process technology refers to the characteristic size of the device in the integrated circuit, which reflects the fineness and integration of the integrated circuit; the smaller the process technology, the higher the fineness and integration of the integrated circuit.
  • the wafer size reflects the size of the raw material wafer used to produce the integrated circuit, and the larger the wafer size, the higher the process level.
  • FIG. 5 is an optional schematic flow chart of a method for forming a semiconductor structure provided in an embodiment of the present disclosure, which will be described in conjunction with the steps shown in FIG. 5 .
  • the substrate 10 can be a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium (SiGe) substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG).
  • Si silicon
  • SOI silicon-on-insulator
  • Ge germanium
  • GOI germanium-on-insulator
  • SiGe silicon-germanium
  • III-V compound semiconductor substrate a III-V compound semiconductor substrate
  • SEG selective epitaxial growth
  • an active region, an interlayer dielectric layer, a bit line, a word line and other structures are formed on the substrate 10. Furthermore, a plurality of lower electrodes 20 can be formed above the active region. A dielectric layer 11 is also formed on the substrate 10, and the dielectric layer 11 is located at the bottom of the lower electrode 20. The plurality of lower electrodes 20 are arranged separately, and each lower electrode 20 extends along the direction Z.
  • the material of the lower electrode 20 may be at least one of a metal, a conductive metal compound, and doped polysilicon, such as a high melting point metal (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), or tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), a conductive noble metal oxide (e.g., PtO, RuO2, or IrO2), and/or a conductive oxide
  • a high melting point metal e.g.
  • FIG7 is a three-dimensional structural diagram corresponding to FIG6.
  • N layers of sacrificial layers 40 and N layers of supporting layers 30 are alternately deposited between the multiple lower electrodes 20.
  • Each layer of sacrificial layer 40 is located between two adjacent layers of supporting layers 30, or between the dielectric layer 11 and the first layer of supporting layer 30.
  • N layers of supporting layers 30 are arranged between the multiple lower electrodes 20 to support the lower electrodes 20 and prevent the lower electrodes 20 from collapsing or bending; each layer of supporting layer 30 extends along a plane perpendicular to the direction Z.
  • the etching resistance of the first to the Nth supporting layers 30 increases layer by layer. That is, in FIG. 6 and FIG. 7 , the etching resistance of the first to fourth supporting layers 30 increases layer by layer, the etching resistance of the first supporting layer 30 is the lowest, and the etching resistance of the fourth supporting layer 30 is the highest.
  • a plurality of etching holes 50 may be formed on the topmost 4th support layer 30, and then the 4th sacrificial layer 40 located between the 3rd and 4th support layers 30 may be removed by a wet etching process; then, a plurality of etching holes 50 may be formed on the 3rd support layer 30, and the 3rd sacrificial layer 40 located between the 2nd and 3rd support layers 30 may be removed by a wet etching process; and so on, until the 1st sacrificial layer 40 located between the dielectric layer 11 and the 1st support layer 30 is removed.
  • the N-layer sacrificial layer 40 is removed in sequence along the direction opposite to the deposition direction Z, and the N-layer support layer 30 is retained, so that the semiconductor structure shown in FIGS. 1 and 2 can be obtained.
  • the support layer 30 at the top i.e., the N-th support layer 30
  • the etching resistance of the first to N-th support layers 30 increases layer by layer, which can ensure that after removing the N-layer sacrificial layer 40, each support layer 30 has better uniformity, reducing the risk of collapse or bending of the lower electrode 20.
  • S201 and S202 shown in FIG. 9 may be used to form the N-layer support layer 30 in FIG. 6 , which will be described in conjunction with each step.
  • the process of forming the support layer needs to be completed in a reaction chamber.
  • the reaction chamber is a closed space, and the gas atmosphere, temperature, electromagnetic field and other conditions in the reaction chamber can be artificially controlled to achieve the process purpose.
  • the support layer 30 can be formed by using an LPCVD process, a PECVD process, or an ALD process.
  • the first gas and the second gas are two reactive gases.
  • the flow rate of the first gas By controlling the flow rate of the first gas, the ratio of elements in the support layer generated by the reaction can be controlled, thereby controlling the anti-etching performance of the support layer 30.
  • the material of the N-layer support layer 30 includes: silicon carbon nitride (SiCN) material.
  • the first gas includes: ammonia (NH3); and the second gas includes: methane (CH4).
  • the flow rate of the first gas ammonia can be controlled so that the flow rate of the first gas ammonia decreases layer by layer during the process of forming the first to Nth support layers 30. In this way, the carbon content of the first to Nth support layers 30 can be increased layer by layer.
  • the flow rate of the second gas methane can be controlled so that the flow rate of the second gas methane increases layer by layer during the process of forming the first to Nth support layers 30. In this way, the carbon content of the first to Nth support layers 30 can also increase layer by layer.
  • the C-Si bond in the SiCN material is more stable than the N-Si bond, the higher the carbon content in the support layer 30, the higher the amount of carbon and silicon combined, the higher the proportion of C-Si bonds, and the support layer 30 has stronger anti-etching performance.
  • the relationship between performance and nitride ratio As shown in FIG10 , the lower the nitride ratio, that is, the higher the carbon content, the higher the etching resistance.
  • the N-layer support layer 30 is formed with SiCN material, and at the same time, the carbon content of the 2nd to Nth support layers 30 increases layer by layer. In this way, the carbon content of the 2nd to Nth support layers 30 increases layer by layer, which ensures that after the sacrificial layer is etched away, each support layer 30 has better uniformity, thereby reducing the risk of collapse or bending of the lower electrode 20.
  • the flow rate of the first gas corresponding to each supporting layer is greater than or equal to 160 slm and less than or equal to 200 slm.
  • the first gas flow rate corresponding to the first support layer is 200 slm; the first gas flow rate corresponding to the second support layer is 180 slm; the first gas flow rate corresponding to the third support layer is 170 slm; the first gas flow rate corresponding to the fourth support layer is 160 slm.
  • the carbon content of the first support layer is 0.24%
  • the carbon content of the second support layer is 0.26%
  • the carbon content of the third support layer is 0.28%
  • the carbon content of the fourth support layer is 0.3%.
  • the material of the dielectric layer 11 may also include: silicon carbon nitride (SiCN) material.
  • SiCN silicon carbon nitride
  • a mixed gas containing at least the first gas ammonia and the second gas methane may also be introduced into the reaction chamber and reacted to deposit and form the dielectric layer 11.
  • the flow rate of the first gas ammonia corresponding to the dielectric layer 11 may be 20 slm.
  • the thickness of the Nth support layer 30 is greater than the thickness of any layer from the 1st to the N-1th support layers 30.
  • the thickness of the four layers of support layers 30 in FIG6 is greater than the thickness of any layer from the 1st to the 3rd support layers 30.
  • the Nth support layer 30 located at the top will be etched the most times, setting the thickness of the Nth support layer 30 to be greater than the thickness of any other support layer 30 can improve the strength of the Nth support layer 30, ensure that each support layer 30 has better uniformity, and reduce the risk of collapse or bending of the lower electrode 20.
  • the sum of the thicknesses of N supporting layers 30 is less than or equal to a preset threshold.
  • the support layer 30 will affect the deposition of the dielectric layer 22 in the capacitor structure, in the process of forming N layers of support layers 30, the sum of the thicknesses of the N layers of support layers 30 is controlled to be less than or equal to a preset threshold. In this way, a significant impact on the deposition of the dielectric layer 22 can be avoided, thereby ensuring the stable performance of the formed capacitor structure.
  • the top height of the N-th support layer 30 is less than or equal to the top height of any lower electrode 20. In this way, it is possible to ensure that the N-th support layer 30 effectively supports the lower electrode 20, reducing the risk of collapse or bending of the lower electrode 20.
  • the material of the N-layer sacrificial layer 40 includes borophosphosilicate glass (BPSG) and silicon oxide.
  • a layer of BPSG material may be deposited; then, a support layer 30 of the first layer of SiCN material is formed, and then a layer of BPSG material; then, a second support layer 30 of SiCN material is formed, and then a layer of silicon oxide material is deposited; then, a third support layer 30 of SiCN material is formed, and then a layer of silicon oxide material is deposited; finally, a fourth support layer 30 of SiCN material is formed.
  • the four support layers 30 and four sacrificial layers 40 shown in Figures 6 and 7 are formed.
  • the embodiment of the present disclosure further provides a memory, as shown in FIG11 , the memory 90 includes a semiconductor structure 80.
  • the semiconductor structure 80 includes the structure shown in FIG1 and FIG2 .
  • the memory 90 is a DRAM.
  • the serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.
  • the methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
  • the features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.
  • the features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.
  • the embodiments of the present disclosure provide a method for forming a semiconductor structure, a semiconductor structure and a memory.
  • the semiconductor structure includes: a plurality of lower electrodes and N supporting layers.
  • the plurality of lower electrodes are separated on a substrate.
  • the N supporting layers are arranged between the plurality of lower electrodes to support the lower electrodes and are arranged in sequence along the deposition direction thereof; N is greater than or equal to 2.
  • the etching resistance of the first to the Nth supporting layers increases layer by layer.
  • the topmost support layer is etched the most during the process of forming the semiconductor structure, the number of etchings on the support layers below the top decreases in sequence, the etching resistance of the first to the Nth support layers increases layer by layer, which can ensure that each support layer has better uniformity, reduce the risk of collapse or bending of the capacitor structure, and thus improve the overall stability and yield of the semiconductor structure.

Landscapes

  • Semiconductor Memories (AREA)

Abstract

本公开实施例公开了一种半导体结构的形成方法、半导体结构及存储器。其中，半导体结构包括：多个下电极和N层支撑层。多个下电极分立于基底之上。N层支撑层设置于多个下电极之间，以支撑下电极，且沿其沉积方向依次排布；N大于等于2。其中，第1层至第N层支撑层的抗刻蚀性能逐层递增。

Description

半导体结构、半导体结构的形成方法及存储器
相关申请的交叉引用
本公开基于申请号为202211398003.6、申请日为2022年11月09日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构、半导体结构的形成方法及存储器。
背景技术
动态随机存取存储器(DRAM，Dynamic Random Access Memory)是一种计算机中常用的半导体存储器件，包含排列成矩阵结构的多个存储单元，每个存储单元可由一个晶体管和一个由晶体管操控的电容结构组成，其中，电容结构的质量直接影响到DRAM的性能。相关技术中，电容结构出现倒塌或者弯曲的风险较大。
发明内容
有鉴于此，本公开实施例提供了一种半导体结构、半导体结构的形成方法及存储器，能够降低电容结构倒塌或者弯曲的风险，提高半导体结构整体的稳定性和良率。
本公开实施例的技术方案是这样实现的：
本公开实施例提供了一种半导体结构，所述半导体结构包括：多个下电极，分立于基底之上；N层支撑层，设置于多个所述下电极之间，以支撑所述下电极，且沿其沉积方向依次排布；N大于等于2；其中，第1层至第N层所述支撑层的抗刻蚀性能逐层递增。
上述方案中，N层所述支撑层的材料包括：硅碳氮材料；其中，第1层至第N层所述支撑层的碳含量逐层递增。
上述方案中，第1层至第N层所述支撑层的碳含量，均大于等于0.24％，且均小于等于0.3％。
上述方案中，N＝4；其中，第1层所述支撑层的碳含量为0.24％，第2层所述支撑层的碳含量为0.26％，第3层所述支撑层的碳含量为0.28％，第4层所述支撑层的碳含量为0.3％。
上述方案中，N层所述支撑层中，第N层所述支撑层的厚度，大于第1层至第N-1层所述支撑层中任一层的厚度；N层所述支撑层的厚度之和，小于等于预设阈值。
上述方案中，在所述沉积方向上，第N层所述支撑层的顶部高度小于等于任一个所述下电极的顶部高度。
上述方案中，所述半导体结构的制程工艺小于等于55nm。
本公开实施例还提供了一种半导体结构的形成方法，所述方法包括：提供基底；在所述基底上形成多个分立的下电极；在多个所述下电极之间，依次交替沉积N层牺牲层和N层支撑层；N大于等于2；其中，第1层至第N层所述支撑层的抗刻蚀性能逐层递增；沿逆沉积方向，依次去除N层所述牺牲层，保留N层所述支撑层。
上述方案中，沉积N层所述支撑层的方法包括：将所述基底置于反应腔内；向反应腔内通入至少含有第一气体和第二气体的混合气体，并进行反应，从而沉积形成每层所述支撑层；其中，所述第一气体的通入流量逐层递减。
上述方案中，所述第一气体包括：氨气；所述第二气体包括：甲烷。
上述方案中，每层所述支撑层对应的所述第一气体的通入流量，均大于等于160slm，且均小于等于200slm。
上述方案中，N＝4；其中，第1层所述支撑层对应的所述第一气体的通入流量为200slm；第2层所述支撑层对应的所述第一气体的通入流量为180slm；第3层所述支撑层对应的所述第一气体的通入流量为170slm；第4层所述支撑层对应的所述第一气体的通入流量为160slm。
上述方案中，N层所述牺牲层的材料包括：硼磷硅玻璃和氧化硅。
本公开实施例还提供了一种存储器，所述存储器包括如上述方案中所述的半导体结构。
上述方案中，所述存储器为DRAM。
由此可见，本公开实施例提供了一种半导体结构的形成方法、半导体结构及存储器。其中，半导体结构包括：多个下电极和N层支撑层。多个下电极分立于基底之上。N层支撑层设置于多个下电极之间，以支撑下电极，且沿其沉积方向依次排布；N大于等于2。其中，第1层至第N层支撑层的抗刻蚀性能逐层递增。由于在形成半导体结构的工艺过程中，位于最顶部的支撑层会受到最多次的刻蚀，最顶部以下的支撑层所受到的刻蚀次数则依次递减。因此，第1层至第N层支撑层的抗刻蚀性能逐层递增，能够保证各个支撑层具有更优的均匀度，降低了电容结构倒塌或者弯曲的风险，从而提高了半导体结构整体的稳定性和良率。
附图说明
图1为本公开实施例提供的半导体结构的示意图一；
图2为本公开实施例提供的半导体结构的示意图二；
图3A为本公开实施例提供的半导体结构的示意图三；
图3B为本公开实施例提供的半导体结构的示意图四；
图4A为本公开实施例提供的半导体结构的示意图五；
图4B为本公开实施例提供的半导体结构的示意图六；
图5为本公开实施例提供的半导体结构的形成方法的流程图一；
图6为本公开实施例提供的半导体结构的形成方法的示意图一；
图7为本公开实施例提供的半导体结构的形成方法的示意图二；
图8为本公开实施例提供的半导体结构的形成方法的示意图三；
图9为本公开实施例提供的半导体结构的形成方法的流程图二；
图10为本公开实施例提供的半导体结构的效果图；
图11为本公开实施例提供的存储器的示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面结合附图和实施例对本公开的技术方案进一步详细阐述，所描述的实施例不应视为对本公开的限制，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
如果申请文件中出现“第一/第二”的类似描述则增加以下的说明，在以下的描述中，所涉及的术语“第一/第二/第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一/第二/第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
在本文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中的层/元件。另外，在一种朝向中，一层/元件位于另一层/元件“上”，当调转朝向时，该层/元件可以位于该另一层/元件“下”。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
图1是本公开实施例提供的半导体结构的一个可选的结构示意图，图1为剖视图。如图1所示，半导体结构包括：多个下电极20和N层支撑层30。多个下电极20分立于基底10之上。N层支撑层30设置于多个下电极20之间，以支撑下电极20。N层支撑层30沿其沉积方向Z依次排布，N大于等于2。其中，第1层至第N层支撑层30的抗刻蚀性能逐层递增。
本公开实施例中，参考图1，基底10可以是硅(Si)衬底、绝缘体上硅(SOI)衬底、锗(Ge)衬底、绝缘体上锗(GOI)衬底、硅锗(SiGe)衬底、III-V族化合物半导体衬底或通过选择性外延生长(SEG)获得的外延薄膜衬底。
本公开实施例中，参考图1，基底10上形成了有源区、层间介质层、位线、字线等结构。下电极20可以形成于有源区的上方。基底10上还形成有介质层11，介质层11位于下电极20的底部。
本公开实施例中，参考图1，下电极20的材料可以是金属、导电金属化合物、掺杂多晶硅中的至少一种，比如，高熔点金属(例如，钴、钛、镍、 钨或钼)、金属氮化物(例如，钛氮化物(TiN)、钛硅氮化物(TiSiN)、钛铝氮化物(TiAlN)、钽氮化物(TaN)、钽硅氮化物(TaSiN)、钽铝氮化物(TaAlN)或钨氮化物(WN))、贵金属(例如，铂(Pt)、钌(Ru)或铱(Ir))、导电贵金属氧化物(例如，PtO、RuO2或IrO2)和/或导电氧化物(例如，SrRuO3、RuO3、CaRuO3)中的一种或多种。
图2为图1对应的立体结构图。结合图1和图2，多个下电极20分立排列，每个下电极20均沿方向Z延伸。N层支撑层30则设置于多个下电极20之间，以支撑下电极20，防止下电极20倒塌或者弯曲；每层支撑层30均沿垂直于方向Z的平面延伸。
需要说明的是，图1和图2示例出了N＝4的情况，即支撑层30的数量为4层，这并非是对本公开实施例的限制。本公开实施例中，支撑层30的的数量N还可以为其他大于等于2的整数，例如N＝3,5,6或7等。
参考图1和图2，4层支撑层30沿其沉积方向Z依次排布，也就是说，介质层11的上方依次形成了第1至4层支撑层30，第4层支撑层30位于最顶部。
需要说明的是，在形成N层支撑层30的过程中，会在N层支撑层30之间的空隙处同时沉积形成牺牲层。直至所有的支撑层30和牺牲层都形成后，再沿逆沉积方向(即与沉积支撑层30相反的方向)，依次刻蚀去除牺牲层，而保留支撑层30。因此，位于最顶部的支撑层30(即图1和图2中的第4层支撑层30)，会受到最多次的刻蚀；最顶部以下的支撑层30所受到的刻蚀次数则依次递减。也就是说，参考图1和图2，第4层支撑层30会受到最多次的刻蚀，进而，第3层支撑层30所受到的刻蚀次数小于第4层支撑层30，第2层支撑层30所受到的刻蚀次数则小于第3层支撑层30，第1层支撑层30所受到的刻蚀次数则小于第2层支撑层30。
本公开实施例中，参考图1和图2，第1层至第4层支撑层30的抗刻蚀性能逐层递增，也就是说，第1层支撑层30的抗刻蚀性能最低，第4层支撑层30的抗刻蚀性能最高。这样，保证了在刻蚀去除牺牲层后，各个支撑层30具有更优的WIW uniformity(with in wafer uniformity，晶圆内部厚度均匀度)，从而，能够对下电极20起到有效的支撑作用，降低了下电极20倒塌或者弯曲的风险，也即降低了电容结构倒塌或者弯曲的风险，提高稳定性。同时，能够减小电容间漏电(Cell leakage，Cell LKG)情况的发生，提高整体性能和良率。
在本公开的一些实施例中，参考图3A和图3B(图3A为剖视图，图3B为俯视图)，下电极20和上电极21的形状可以均为筒型。下电极20、上电极21和介质层22共同构成了电容结构，其中，下电极20和上电极21构成电容结构的两极，介质层22则填充于下电极20和上电极21之间。
在本公开的另一些实施例中，参考图4A和图4B(图4A为剖视图，图4B为俯视图)，下电极20的形状可以是筒型，上电极21的形状可以是套筒型。下电极20、上电极21和介质层22共同构成了电容结构，类似的，下电 极20和上电极21构成电容结构的两极，介质层22则填充于下电极20和上电极21之间。
在本公开的一些实施例中，参考图1，N层支撑层30的材料包括：硅碳氮(SiCN)材料。其中，第1层至第N层支撑层30的碳含量逐层递增。
本公开实施例中，以SiCN材料形成的支撑层30，具有极高的硬度、高温抗氧化性、高温蠕变抗力、低摩擦系数、可调的光学特性和许多其他的优良特性，能够对下电极20形成有效的支撑作用。进而，可以利用LPCVD(低压力化学气相沉积)工艺、PECVD(等离子体增强化学的气相沉积法)工艺或ALD(原子层沉积)工艺等，来形成SiCN材料的支撑层30。
本公开实施例中，参考图1，第2层至第N层支撑层30的碳含量逐层递增。由于在SiCN材料中，C-Si键比N-Si键更加稳定。而支撑层30中碳含量越高，则碳元素和硅元素的结合量越高，C-Si键的比例越高，从而，支撑层30具有更强的抗刻蚀性能。
可以理解的是，以SiCN材料形成N层支撑层30，同时，第2层至第N层支撑层30的碳含量逐层递增，这样，第2层至第N层支撑层30的碳含量逐层递增，保证了在刻蚀去除牺牲层后，各个支撑层30具有更优的均匀度，降低了下电极20倒塌或者弯曲的风险。
在本公开的一些实施例中，参考图1，每层支撑层30的碳含量，均大于等于0.24％，且均小于等于0.3％。
在本公开的一些实施例中，参考图1，在N＝4的情况下，第1层支撑层的碳含量为0.24％，第2层支撑层的碳含量为0.26％，第3层支撑层的碳含量为0.28％，第4层支撑层的碳含量为0.3％。
在本公开的一些实施例中，参考图1，N层支撑层30中，第N层支撑层30的厚度，大于第1层至第N-1层支撑层30中任一层的厚度。也就是说，图1中的第4层支撑层30的厚度，大于第1层至第3层支撑层30中任一层的厚度。
可以理解的是，由于位于顶部的第N层支撑层30，会受到最多次的刻蚀，因此，设置第N层支撑层30的厚度大于其他任一层支撑层30的厚度，能够提升第N层支撑层30的强度，保证了各个支撑层30具有更优的均匀度，降低了下电极20倒塌或者弯曲的风险。
在本公开的一些实施例中，参考图1，N层支撑层30的厚度之和，小于等于预设阈值。
结合图1、图3A和图3B，或者结合图1、图4A和图4B，支撑层30会对电容结构中的介质层22的沉积产生影响；若N层支撑层30的厚度之和过大，则会对介质层22的沉积产生较大影响，从而影响到所形成的电容结构的性能。因此，在形成N层支撑层30的过程中，控制N层支撑层30的厚度之和小于等于预设阈值，这样，能够避免对介质层22的沉积产生较大影响，从而保证了所形成的电容结构的性能稳定。
在本公开的一些实施例中，参考图1，在沉积方向Z上，第N层支撑层 30的顶部高度小于等于任一个下电极20的顶部高度。这样，能够保证N层支撑层30对下电极20形成有效的支撑，降低了下电极20倒塌或者弯曲的风险。
在本公开的一些实施例中，图1和图2示出的半导体结构，其制程工艺小于等于55nm，其晶圆(wafer)尺寸大于等于8英寸。这里，制程工艺是指集成电路中器件的特征尺寸，其反映了集成电路的精细度和集成度；制程工艺越小，则集成电路的精细度和集成度越高。晶圆尺寸则反映了生产集成电路所用的原材料晶圆的大小，晶圆尺寸越大则工艺水平越高。
图5是本公开实施例提供的半导体结构的形成方法的可选的流程示意图，将结合图5示出的步骤进行说明。
S101、提供基底。
本公开实施例中，参考图6(图6为剖视图)，基底10可以是硅(Si)衬底、绝缘体上硅(SOI)衬底、锗(Ge)衬底、绝缘体上锗(GOI)衬底、硅锗(SiGe)衬底、III-V族化合物半导体衬底或通过选择性外延生长(SEG)获得的外延薄膜衬底。
S102、在基底上形成多个分立的下电极。
本公开实施例中，参考图6，基底10上形成了有源区、层间介质层、位线、字线等结构。进而，多个下电极20可以形成于有源区的上方。基底10上还形成有介质层11，介质层11位于下电极20的底部。多个下电极20分立排列，每个下电极20均沿方向Z延伸。
本公开实施例中，继续参考图6，下电极20的材料可以是金属、导电金属化合物、掺杂多晶硅中的至少一种，比如，高熔点金属(例如，钴、钛、镍、钨或钼)、金属氮化物(例如，钛氮化物(TiN)、钛硅氮化物(TiSiN)、钛铝氮化物(TiAlN)、钽氮化物(TaN)、钽硅氮化物(TaSiN)、钽铝氮化物(TaAlN)或钨氮化物(WN))、贵金属(例如，铂(Pt)、钌(Ru)或铱(Ir))、导电贵金属氧化物(例如，PtO、RuO2或IrO2)和/或导电氧化物(例如，SrRuO3、RuO3、CaRuO3)中的一种或多种。每个下电极20均可以构成电容结构的一极。
S103、在多个下电极之间，依次交替沉积N层牺牲层和N层支撑层；其中，第1层至第N层支撑层的抗刻蚀性能逐层递增。
图7为图6对应的立体结构图。结合图6和图7，在多个下电极20之间，依次交替沉积了N层牺牲层40和N层支撑层30。其中，每层牺牲层40，位于相邻两层支撑层30之间，或者，位于介质层11和第1层支撑层30之间。N层支撑层30则设置于多个下电极20之间，以支撑下电极20，防止下电极20倒塌或者弯曲；每层支撑层30均沿垂直于方向Z的平面延伸。
需要说明的是，图6和图7示例出了N＝4的情况，即支撑层30的数量为4层，这并非是对本公开实施例的限制。本公开实施例中，数量N还可以为其他大于等于2的整数，例如N＝3,5,6或7等。
本公开实施例中，第1层至第N层支撑层30的抗刻蚀性能逐层递增。也 就是说，在图6和图7中，第1层至第4层支撑层30的抗刻蚀性能逐层递增，第1层支撑层30的抗刻蚀性能最低，第4层支撑层30的抗刻蚀性能最高。
S104、沿逆沉积方向，依次去除N层牺牲层，保留N层支撑层。
本公开实施例中，参考图8，可以在最顶部的第4层支撑层30上先形成若干个刻蚀孔50，再采用湿法刻蚀(Wet Etch)工艺，将位于第3层和第4层支撑层30之间的第4层牺牲层40去除；而后，可以在第3层支撑层30上形成若干个刻蚀孔50，并采用湿法刻蚀(Wet Etch)工艺，将位于第2层和第3层支撑层30之间的第3层牺牲层40去除；依此类推，直至将位于介质层11和第1层支撑层30之间的第1层牺牲层40去除。这样，便沿与沉积方向Z相逆的方向，依次去除了N层牺牲层40，保留N层支撑层30，从而，可以得到如图1和图2所示的半导体结构。
可以理解的是，由于在去除N层牺牲层40的过程中，位于最顶部的支撑层30(即第N层支撑层30)，会受到最多次的刻蚀；最顶部以下的支撑层30所受到的刻蚀次数则依次递减。因此，第1层至第N层支撑层30的抗刻蚀性能逐层递增，能够保证在去除了N层牺牲层40后，各个支撑层30具有更优的均匀度，降低了下电极20倒塌或者弯曲的风险。
在本公开的一些实施例中，可以采用图9示出的S201和S202来形成图6中的N层支撑层30，将结合各步骤进行说明。
S201、将基底置于反应腔内。
本公开实施例中，形成支撑层的过程需要在反应腔(chamber)中完成。反应腔为一密闭的空间，反应腔中的气体氛围、温度和电磁场等条件可以被人为控制，从而达到工艺目的。
S202、向反应腔内通入至少含有第一气体和第二气体的混合气体，并进行反应，从而沉积形成每层支撑层；其中，第一气体的通入流量逐层递减。
本公开实施例中，参考图6，可以利用LPCVD工艺、PECVD工艺或ALD工艺等，来形成支撑层30。其中，第一气体和第二气体为两种反应气体。通过控制第一气体的通入流量，可以控制反应生成的支撑层中的元素比例，从而控制支撑层30的抗刻蚀性能。
本公开实施例中，参考图6，N层支撑层30的材料包括：硅碳氮(SiCN)材料。第一气体包括：氨气(NH3)；第二气体包括：甲烷(CH4)。
在一些实施例中，可以控制第一气体氨气的通入流量，使得在形成第1层至第N层支撑层30的过程中，第一气体氨气的通入流量逐层递减。这样，能够使得第1层至第N层支撑层30的碳含量逐层递增。
在另一些实施例中，可以控制第二气体甲烷的通入流量，使得在形成第1层至第N层支撑层30的过程中，第二气体甲烷的通入流量逐层递增。这样，同样能够使得第1层至第N层支撑层30的碳含量逐层递增。
本公开实施例中，由于在SiCN材料中，C-Si键比N-Si键更加稳定，因此，支撑层30中碳含量越高，则碳元素和硅元素的结合量越高，C-Si键的比例越高，支撑层30具有更强的抗刻蚀性能。图10示出了SiCN材料的抗刻蚀 性能与氮化物比率的关系，由图10可知，氮化物比率越低，即碳含量越高，则抗刻蚀性能越高。
可以理解的是，以SiCN材料形成N层支撑层30，同时，第2层至第N层支撑层30的碳含量逐层递增，这样，第2层至第N层支撑层30的碳含量逐层递增，保证了在刻蚀去除牺牲层后，各个支撑层30具有更优的均匀度，降低了下电极20倒塌或者弯曲的风险。
在本公开的一些实施例中，每层支撑层对应的第一气体的通入流量，均大于等于160slm，且均小于等于200slm。
在本公开的一些实施例中，参考图6，第1层支撑层对应的第一气体的通入流量为200slm；第2层支撑层对应的第一气体的通入流量为180slm；第3层支撑层对应的第一气体的通入流量为170slm；第4层支撑层对应的第一气体的通入流量为160slm。相应的，第1层支撑层的碳含量为0.24％，第2层支撑层的碳含量为0.26％，第3层支撑层的碳含量为0.28％，第4层支撑层的碳含量为0.3％。
本公开实施例中，参考图6，介质层11的材料也可以包括：硅碳氮(SiCN)材料。也可以向反应腔内通入至少含有第一气体氨气和第二气体甲烷的混合气体，并进行反应，从而沉积形成介质层11。介质层11对应的第一气体氨气的通入流量可以为20slm。
在本公开的一些实施例中，参考图6，N层支撑层30中，第N层支撑层30的厚度，大于第1层至第N-1层支撑层30中任一层的厚度。也就是说，图6中的4层支撑层30的厚度，大于第1层至第3层支撑层30中任一层的厚度。
可以理解的是，由于位于顶部的第N层支撑层30，会受到最多次的刻蚀，因此，设置第N层支撑层30的厚度大于其他任一层支撑层30的厚度，能够提升第N层支撑层30的强度，保证了各个支撑层30具有更优的均匀度，降低了下电极20倒塌或者弯曲的风险。
在本公开的一些实施例中，参考图6，N层支撑层30的厚度之和，小于等于预设阈值。
可以理解的是，由于支撑层30会对电容结构中的介质层22的沉积产生影响，因此，在形成N层支撑层30的过程中，控制N层支撑层30的厚度之和小于等于预设阈值，这样，能够避免对介质层22的沉积产生较大影响，从而保证了所形成的电容结构的性能稳定。
在本公开的一些实施例中，参考图6，在沉积方向Z上，第N层支撑层30的顶部高度小于等于任一个下电极20的顶部高度。这样，能够保证N层支撑层30对下电极20形成有效的支撑，降低了下电极20倒塌或者弯曲的风险。
在本公开的一些实施例中，参考图6和图7，N层牺牲层40的材料包括：硼磷硅玻璃(BPSG)和氧化硅。
本公开实施例中，以图6和图7为例，可以在形成了介质层11之后，沉积一层BPSG材料；而后，形成第1层SiCN材料的支撑层30，再沉积一层 BPSG材料；而后，形成第2层SiCN材料的支撑层30，再沉积一层氧化硅材料；而后，形成第3层SiCN材料的支撑层30，再沉积一层氧化硅材料；最后，形成第4层SiCN材料的支撑层30。这样，便形成了图6和图7示出的4层支撑层30和4层牺牲层40。
本公开实施例还提供了一种存储器，如图11所示，存储器90包括半导体结构80。半导体结构80包括如图1和图2所示出的结构。
在本公开的一些实施例中，参考图11，存储器90为DRAM。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种半导体结构的形成方法、半导体结构及存储器。其中，半导体结构包括：多个下电极和N层支撑层。多个下电极分立于基底之上。N层支撑层设置于多个下电极之间，以支撑下电极，且沿其沉积方向依次排布；N大于等于2。其中，第1层至第N层支撑层的抗刻蚀性能逐层递增。
由于在形成半导体结构的工艺过程中，位于最顶部的支撑层会受到最多次的刻蚀，最顶部以下的支撑层所受到的刻蚀次数则依次递减。因此，第1层至第N层支撑层的抗刻蚀性能逐层递增，能够保证各个支撑层具有更优的均匀度，降低了电容结构倒塌或者弯曲的风险，从而提高了半导体结构整体的稳定性和良率。

Claims (15)

  1. 一种半导体结构，所述半导体结构包括：
    多个下电极(20)，分立于基底(10)之上；
    N层支撑层(30)，设置于多个所述下电极(20)之间，以支撑所述下电极(20)，且沿其沉积方向依次排布；N大于等于2；其中，第1层至第N层所述支撑层(30)的抗刻蚀性能逐层递增。
  2. 根据权利要求1所述的半导体结构，其中，N层所述支撑层(30)的材料包括：硅碳氮材料；其中，
    第1层至第N层所述支撑层(30)的碳含量逐层递增。
  3. 根据权利要求2所述的半导体结构，其中，每层所述支撑层(30)的碳含量，均大于等于0.24％，且均小于等于0.3％。
  4. 根据权利要求2或3所述的半导体结构，其中，N＝4；其中，第1层所述支撑层(30)的碳含量为0.24％，第2层所述支撑层(30)的碳含量为0.26％，第3层所述支撑层(30)的碳含量为0.28％，第4层所述支撑层(30)的碳含量为0.3％。
  5. 根据权利要求1至4任一项所述的半导体结构，其中，
    N层所述支撑层(30)中，第N层所述支撑层(30)的厚度，大于第1层至第N-1层所述支撑层(30)中任一层的厚度；
    N层所述支撑层(30)的厚度之和，小于等于预设阈值。
  6. 根据权利要求1至5任一项所述的半导体结构，其中，
    在所述沉积方向上，第N层所述支撑层(30)的顶部高度小于等于任一个所述下电极(20)的顶部高度。
  7. 根据权利要求1至6任一项所述的半导体结构，其中，
    所述半导体结构的制程工艺小于等于55nm。
  8. 一种半导体结构的形成方法，所述方法包括：
    提供基底(10)；
    在所述基底(10)上形成多个分立的下电极(20)；
    在多个所述下电极(20)之间，依次交替沉积N层牺牲层(40)和N层支撑层(30)；N大于等于2；其中，第1层至第N层所述支撑层(30)的抗刻蚀性能逐层递增；
    沿逆沉积方向，依次去除N层所述牺牲层(40)，保留N层所述支撑层(30)。
  9. 根据权利要求8所述的半导体结构的形成方法，其中，沉积N层所述支撑层(30)的方法包括：
    将所述基底(10)置于反应腔内；
    向反应腔内通入至少含有第一气体和第二气体的混合气体，并进行反应，从而沉积形成每层所述支撑层(30)；其中，所述第一气体的通入流量逐层递减。
  10. 根据权利要求9所述的半导体结构的形成方法，其中，所述第一气体包括：氨气；所述第二气体包括：甲烷。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，
    每层所述支撑层(30)对应的所述第一气体的通入流量，均大于等于160slm，且均小于等于200slm。
  12. 根据权利要求10或11所述的半导体结构的形成方法，其中，N＝4；其中，
    第1层所述支撑层(30)对应的所述第一气体的通入流量为200slm；
    第2层所述支撑层(30)对应的所述第一气体的通入流量为180slm；
    第3层所述支撑层(30)对应的所述第一气体的通入流量为170slm；
    第4层所述支撑层(30)对应的所述第一气体的通入流量为160slm。
  13. 根据权利要求8至12任一项所述的半导体结构的形成方法，其中，
    N层所述牺牲层(40)的材料包括：硼磷硅玻璃和氧化硅。
  14. 一种存储器(90)，所述存储器包括如权利要求1至7任一项所述的半导体结构(80)。
  15. 根据权利要求14所述的存储器(90)，其中，所述存储器(90)为DRAM。
PCT/CN2023/092035 2022-11-09 2023-05-04 半导体结构、半导体结构的形成方法及存储器 Ceased WO2024098686A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211398003.6A CN118076087A (zh) 2022-11-09 2022-11-09 半导体结构、半导体结构的形成方法及存储器
CN202211398003.6 2022-11-09

Publications (1)

Publication Number Publication Date
WO2024098686A1 true WO2024098686A1 (zh) 2024-05-16

Family

ID=91031858

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/092035 Ceased WO2024098686A1 (zh) 2022-11-09 2023-05-04 半导体结构、半导体结构的形成方法及存储器

Country Status (2)

Country Link
CN (1) CN118076087A (zh)
WO (1) WO2024098686A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235279A1 (en) * 2011-03-14 2012-09-20 Samsung Electronics Co., Ltd. Semiconductor devices and methods for fabricating the same
US20130228837A1 (en) * 2012-03-01 2013-09-05 Elpida Memory, Inc. Semiconductor device
KR20170134038A (ko) * 2016-05-27 2017-12-06 삼성전자주식회사 반도체 소자
CN112530948A (zh) * 2019-09-17 2021-03-19 三星电子株式会社 集成电路器件
CN112908968A (zh) * 2019-12-03 2021-06-04 长鑫存储技术有限公司 半导体存储器中的电容及其制备方法
CN113345835A (zh) * 2020-03-02 2021-09-03 爱思开海力士有限公司 半导体器件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235279A1 (en) * 2011-03-14 2012-09-20 Samsung Electronics Co., Ltd. Semiconductor devices and methods for fabricating the same
US20130228837A1 (en) * 2012-03-01 2013-09-05 Elpida Memory, Inc. Semiconductor device
KR20170134038A (ko) * 2016-05-27 2017-12-06 삼성전자주식회사 반도체 소자
CN112530948A (zh) * 2019-09-17 2021-03-19 三星电子株式会社 集成电路器件
CN112908968A (zh) * 2019-12-03 2021-06-04 长鑫存储技术有限公司 半导体存储器中的电容及其制备方法
CN113345835A (zh) * 2020-03-02 2021-09-03 爱思开海力士有限公司 半导体器件及其制造方法

Also Published As

Publication number Publication date
CN118076087A (zh) 2024-05-24

Similar Documents

Publication Publication Date Title
US11763856B2 (en) 3-D DRAM structure with vertical bit-line
US20210249415A1 (en) 3-d dram structures and methods of manufacture
US10797061B2 (en) Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same
JP6943922B2 (ja) 半導体メモリ素子
US20250338499A1 (en) Microelectronic devices with vertically recessed channel structures and discrete, spaced inter-slit structures, and related methods
TW425700B (en) Hemispherical grained polysilicon semiconductor structure and method
US12471283B2 (en) Microelectronic devices with source region vertical extension between upper and lower channel regions, and related methods
CN107731838A (zh) 一种nand存储器及其制备方法
JP5147183B2 (ja) ナノチューブを有するキャパシタ及びその製造方法
TWI310603B (en) Method for fabricating capacitor in semiconductor device
CN113991017B (zh) 一种电容器阵列结构、及其制造方法及半导体存储器件
US11411071B1 (en) Capacitor array structure and method for manufacturing a capacitor array structure, and semiconductor memory device
WO2024098686A1 (zh) 半导体结构、半导体结构的形成方法及存储器
KR20040069492A (ko) 나노 구조물을 이용한 커패시터를 포함하는 반도체 소자 및 그 제조 방법
CN113937090B (zh) 堆叠式电容器、半导体存储器件及制备方法
TW202349673A (zh) 半導體結構及其製作方法
US20210359083A1 (en) Semiconductor device and method for forming the same
CN115568209A (zh) 一种半导体结构及其制作方法
US8138572B2 (en) Semiconductor device and method for fabricating the same
CN116782757A (zh) 一种半导体结构及其制造方法
TW434890B (en) Method for forming multi-cylinder capacitor
US20260032979A1 (en) Electronic devices comprising epitaxial polysilicon source contacts and related systems and methods
US20050006690A1 (en) Capacitor of semiconductor device and method for fabricating the same
US11393828B2 (en) Electronic devices comprising digit line contacts and related systems and methods
WO2024000695A1 (zh) 半导体结构及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23887387

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23887387

Country of ref document: EP

Kind code of ref document: A1