WO2024098612A1 - 一种改善衬底抛光片外延后裂片的方法 - Google Patents

一种改善衬底抛光片外延后裂片的方法 Download PDF

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Publication number
WO2024098612A1
WO2024098612A1 PCT/CN2023/081608 CN2023081608W WO2024098612A1 WO 2024098612 A1 WO2024098612 A1 WO 2024098612A1 CN 2023081608 W CN2023081608 W CN 2023081608W WO 2024098612 A1 WO2024098612 A1 WO 2024098612A1
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Prior art keywords
cracking
edge
chamfer
peripheral
epitaxial
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PCT/CN2023/081608
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English (en)
French (fr)
Inventor
孙涛
胡久林
洪漪
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上海中欣晶圆半导体科技有限公司
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Publication of WO2024098612A1 publication Critical patent/WO2024098612A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

Definitions

  • the invention relates to the technical field of semiconductors, and in particular to a method for improving the cracking of a substrate polishing sheet after epitaxy.
  • substrate silicon wafers often crack due to excessive stress concentration at the chamfered edge of the silicon wafer. This has been difficult to control in the industry because products using conventional processes often use a fine grinding + rough grinding process for chamfering, and the chamfered surface state is relatively rough and difficult to control.
  • the length of the conventional chamfer is also one of the important factors affecting epitaxial cracking. If the chamfer width is too long, the silicon wafer is prone to edge hanging during the epitaxial growth process. Under the action of the deposition gas flow, a thin epitaxial layer will grow between the silicon wafer and the wafer pit at the edge to bond, which is prone to stress concentration and cracking when the wafer is taken out. If the chamfer width is too short, epitaxial self-doping is easy to occur.
  • the present invention provides a method for improving the post-epitaxial splitting of a polished substrate, which solves at least one of the above-mentioned technical problems.
  • the technical solution of the present invention is: a method for improving the post-epitaxial cracking of a polished substrate, characterized in that it comprises the following steps:
  • Step 1 Roughly grind the chamfered outer peripheral position and outer peripheral OF edge
  • Step 2 Perform the first fine grinding on the chamfered outer peripheral position and outer peripheral OF edge;
  • Step 3 perform a second fine grinding on the chamfered outer peripheral position and outer peripheral OF edge;
  • Step 4 Change the chamfer profile and select a chamfer width length suitable for the epitaxial process.
  • the embodiment of the present invention improves the chamfering grinding process and increases the number of fine grinding times, which is improved to rough grinding + fine grinding + fine grinding, and one more fine grinding process is performed than conventional products.
  • the present invention solves the problem of substrate polishing by researching and developing a new chamfering process.
  • the problem of high cracking rate after epitaxy has reduced the incidence of edge cracking of silicon wafers after epitaxy from about 3% to less than 0.5%. Due to the hanging edge of silicon wafers during epitaxy, a thin epitaxial layer will grow between the silicon wafers and the wafer pits at the hanging edge under the action of the deposition gas flow, which is prone to stress concentration and cracking when taking the wafers.
  • the present invention changes the chamfer profile to find the most suitable chamfer width length for the epitaxy process, avoiding the original stress concentration caused by the hanging edge of the silicon wafer during epitaxy due to the chamfer width being too long, which causes cracking.
  • the rough grinding speed at the peripheral position is m 1 -2
  • the original rough grinding speed at the peripheral position is m 1
  • the rough grinding speed at the peripheral OF edge is n 1 -2
  • the original rough grinding speed at the peripheral OF edge is n 1 .
  • the first lapping speed at the peripheral position is m 2 -5
  • the original lapping speed at the peripheral position is m 2
  • the first lapping speed at the peripheral OF edge is n 2 -8
  • the original lapping speed at the peripheral OF edge is n 2 .
  • the second lapping speed is consistent with the first lapping speed.
  • the grinding speed of fine grinding and rough grinding is reduced to improve the roughness of the chamfered surface and reduce the stress concentration generated at the chamfered edge of the silicon wafer.
  • the chamfer angle of the chamfered profile is 20-24° or 10-12°, which can reduce the chipping rate compared with the original chamfer angle of 10-12°.
  • the chamfer width of the chamfer profile is 350-450um or 400-500um. Compared with the original chamfer width of 600-700um, the grinding width is shortened and the chipping rate is reduced.
  • the experimental pieces processed by the chamfering grinding process of the present invention are respectively flowed to the polishing piece to observe whether the roughness state of the chamfered surface and the incidence rate of epitaxial end cracks are improved:
  • the chamfer surface of the experimental piece processed by the improved chamfering grinding process is rougher than that of the conventional grinding process.
  • the stress concentration caused by the chamfered edge of the silicon wafer is greatly reduced, and the incidence of cracking after epitaxy is reduced from 3% to about 1.8%.
  • Figure 1 is a comparison of the chamfer morphology of the chamfer profile process polished sheet
  • FIG. 2 is a schematic diagram of the chamfer surface width.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本发明涉及一种改善衬底抛光片外延后裂片的方法，包括如下步骤：步骤一，对倒角的外周位置和外周OF边进行粗研；步骤二，对倒角的外周位置和外周OF边进行第一次精研；步骤三，对倒角的外周位置和外周OF边进行第二次精研；步骤四，改变倒角轮廓形貌，选取适合外延工艺的倒角宽幅长度。本发明通过改善倒角研削工艺，增加精研次数，改进为粗研+精研+精研，较常规产品多进行一次精研过程。本发明通过对新型倒角工艺的研究与开发，解决了衬底抛光片外延后裂片率高的问题，使硅片外延后边缘裂片的发生率由3％左右降低至0.5％以下。

Description

一种改善衬底抛光片外延后裂片的方法 技术领域
本发明涉及半导体技术领域，具体涉及一种改善衬底抛光片外延后裂片的方法。
背景技术
目前市场上普遍采用常规硅片加工工艺，随着半导体行业的不断发展，线宽更小的芯片不断开发，晶圆衬底片也被要求应用于不同的外延工艺中，其对衬底片能适用于不同EPI工艺的通用性也提出了更高的要求，常规硅片加工过程的倒角工艺已不能满足于当前更高规格的EPI条件，其在外延过程中往往因衬底倒角处应力集中过大，而导致裂片发生，极大影响了下游端外延厂的产品良率。
衬底硅片在外延过程中，往往因硅片倒角边缘处存在应力集中过大导致裂片，业界一直很难控制，原因是使用常规工艺的产品，往往倒角采用的是精研+粗研的加工工艺，其倒角面状态相对粗糙，难以控制；常规倒角宽幅长短，也是影响外延裂片的重要因素之一，倒角宽幅太长，外延过程中容易发生硅片挂边，在沉积气流作用下，挂边处硅片与片坑之间会长出薄外延层粘结，取片时容易产生应力集中导致裂片，倒角宽幅太短，容易引发外延自掺杂。
发明内容
针对现有技术存在的问题，本发明提供一种改善衬底抛光片外延后裂片的方法，已解决上述至少一个技术问题。
本发明的技术方案是：一种改善衬底抛光片外延后裂片的方法，其特征在于，包括如下步骤：
步骤一，对倒角的外周位置和外周OF边进行粗研；
步骤二，对倒角的外周位置和外周OF边进行第一次精研；
步骤三，对倒角的外周位置和外周OF边进行第二次精研；
步骤四，改变倒角轮廓形貌，选取适合外延工艺的倒角宽幅长度。
本发明的实施例通过改善倒角研削工艺，增加精研次数，改进为粗研+精研+精研，较常规产品多进行一次精研过程。本发明通过对新型倒角工艺的研究与开发，解决了衬底抛光片 外延后裂片率高的问题，使硅片外延后边缘裂片的发生率由3％左右降低至0.5％以下。由于外延过程中硅片挂边，在沉积气流作用下，挂边处硅片与片坑之间会长出薄外延层粘结，取片时容易产生应力集中导致裂片，所以本发明通过改变倒角轮廓形貌，来找到最适合外延工艺的倒角宽幅长度，避免原先因倒角宽幅太长，在外延时因硅片挂边产生应力集中引发裂片。
进一步优选，外周位置粗研速度为m1-2，原先外周位置粗研速度为m1，外周OF边粗研速度为n1-2，原先外周OF边的粗研速度为n1。
进一步优选，外周位置第一次精研速度为m2-5，原先外周位置精研速度为m2，外周OF边第一次精研速度为n2-8，原先外周OF边的精研速度为n2。
进一步优选，第二次精研速度与第一次精研速度一致。
相对常规产品降低精研和粗研的研削速度，来改善倒角面粗糙度，减小了硅片倒角边缘产生的应力集中。
进一步优选，所述倒角轮廓的倒角角度是20-24°或者10-12°。与原先倒角角度10-12°相比，可以降低裂片率。
进一步优选，所述倒角轮廓的倒角宽幅是350-450um或者400-500um。与原先倒角宽幅600-700um相比，缩短了研磨宽幅，降低了裂片率。
进一步优选，采用本发明倒角研削工艺加工的实验片分别流动至抛光片观察倒角面粗糙度状态及外延端裂片发生率有无改善：
由此可以看出改进后倒角研削工艺加工的实验片倒角面状态相较于常规研削工艺粗糙度 大大降低，减小了硅片倒角边缘产生的应力集中，外延后裂片发生率由3％降低至1.8％左右。
附图说明
图1是倒角轮廓工艺抛光片倒角形貌对比；
图2是倒角面幅宽示意图。
具体实施方式
下面结合实施例对本发明做进一步的说明。
具体实施例1
以我司F-P5N0089AFW系列产品为例，在改善倒角研削工艺的基础上，在设计如下2种实验方案，改变其产品倒角轮廓形貌，采用如下新倒角工艺加工的实验片，分别流动至抛光片确认倒角轮廓形貌、倒角宽幅长度以及流动至外延端确认裂片发生率有无改善。倒角轮廓工艺抛光片倒角形貌对比如图1所示。
从实际测量结果来看，方案一和方案二均大幅缩减了倒角面幅宽(X1)如图2所示，降低了外延过程中因挂壁导致裂片的可能，从客户端实际外延后裂片发生率来看，方案二改善效果最优，外延后裂片率降低至0.3％左右。
以上仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (7)

  1. 一种改善衬底抛光片外延后裂片的方法，其特征在于，包括如下步骤：
    步骤一，对倒角的外周位置和外周OF边进行粗研；
    步骤二，对倒角的外周位置和外周OF边进行第一次精研；
    步骤三，对倒角的外周位置和外周OF边进行第二次精研；
    步骤四，改变倒角轮廓形貌，选取适合外延工艺的倒角宽幅长度。
  2. 根据权利要求1所述的一种改善衬底抛光片外延后裂片的方法，其特征在于：外周位置粗研速度为m1-2，原先外周位置粗研速度为m1，外周OF边粗研速度为n1-2，原先外周OF边的粗研速度为n1。
  3. 根据权利要求1所述的一种改善衬底抛光片外延后裂片的方法，其特征在于：外周位置第一次精研速度为m2-5，原先外周位置精研速度为m2，外周OF边第一次精研速度为n2-8，原先外周OF边的精研速度为n2。
  4. 根据权利要求1所述的一种改善衬底抛光片外延后裂片的方法，其特征在于：第二次精研速度与第一次精研速度一致。
  5. 根据权利要求1所述的一种改善衬底抛光片外延后裂片的方法，其特征在于：所述倒角轮廓的倒角角度是20-24°或者10-12°。
  6. 根据权利要求1所述的一种改善衬底抛光片外延后裂片的方法，其特征在于：所述倒角轮廓的倒角宽幅是350-450um或者400-500um。
  7. 根据权利要求1所述的一种改善衬底抛光片外延后裂片的方法，其特征在于：采用本发明倒角研削工艺加工的实验片分别流动至抛光片观察倒角面粗糙度状态及外延端裂片发生率有无改善：

PCT/CN2023/081608 2022-11-10 2023-03-15 一种改善衬底抛光片外延后裂片的方法 WO2024098612A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174222B1 (en) * 1995-06-09 2001-01-16 Hitachi, Ltd. Process for fabrication of semiconductor device, semiconductor wafer for use in the process and process for the preparation of the wafer
CN1364107A (zh) * 2000-02-23 2002-08-14 信越半导体株式会社 晶片的周面倒角部分的抛光方法及其设备
US20040178477A1 (en) * 2003-03-14 2004-09-16 Renesas Technology Corp. Semiconductor wafer
WO2013024565A1 (ja) * 2011-08-12 2013-02-21 信越半導体株式会社 取代の評価方法及びウェーハの製造方法
CN110468446A (zh) * 2018-05-11 2019-11-19 硅晶体有限公司 倒角的碳化硅衬底以及倒角的方法
CN110625835A (zh) * 2019-09-12 2019-12-31 西安奕斯伟硅片技术有限公司 一种硅片成型加工方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174222B1 (en) * 1995-06-09 2001-01-16 Hitachi, Ltd. Process for fabrication of semiconductor device, semiconductor wafer for use in the process and process for the preparation of the wafer
CN1364107A (zh) * 2000-02-23 2002-08-14 信越半导体株式会社 晶片的周面倒角部分的抛光方法及其设备
US20040178477A1 (en) * 2003-03-14 2004-09-16 Renesas Technology Corp. Semiconductor wafer
WO2013024565A1 (ja) * 2011-08-12 2013-02-21 信越半導体株式会社 取代の評価方法及びウェーハの製造方法
CN110468446A (zh) * 2018-05-11 2019-11-19 硅晶体有限公司 倒角的碳化硅衬底以及倒角的方法
CN110625835A (zh) * 2019-09-12 2019-12-31 西安奕斯伟硅片技术有限公司 一种硅片成型加工方法

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