Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67017—Apparatus for fluid treatment
  • H01L21/67063—Apparatus for fluid treatment for etching
  • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J31/00—Cathode ray tubes; Electron beam tubes
  • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
  • H01J31/26—Image pick-up tubes having an input of visible light and electric output
  • H01J31/28—Image pick-up tubes having an input of visible light and electric output with electron ray scanning the image screen
  • H01J31/30—Image pick-up tubes having an input of visible light and electric output with electron ray scanning the image screen having regulation of screen potential at anode potential, e.g. iconoscope
  • H01J31/32—Tubes with image amplification section, e.g. image-iconoscope, supericonoscope
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/32532—Electrodes
  • H01J37/32541—Shape
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the present disclosure belongs to the technical field of semiconductor equipment, and specifically relates to a semiconductor process chamber and semiconductor process equipment.
• the uniformity requirements of semiconductor etching process are getting higher and higher.
• semiconductor etching process equipment such as ICP (Inductively Coupled Plasma) etching equipment
• the coil of the upper electrode generates plasma inside the chamber by inductive coupling.
• a certain frequency of radio frequency power is applied to the lower electrode.
• the radio frequency power acts on the plasma on the surface of the wafer by capacitive coupling, thereby controlling the ion energy reaching the surface of the wafer.
• High-energy ions bombard the wafer surface to destroy the CF film produced during the etching process that blocks the etching reaction, thereby accelerating the etching rate.
• the main factors affecting the uniformity of the etching process include: plasma uniformity on the wafer surface, uniformity of ion energy distribution controlled by the lower electrode loop, uniformity of density distribution of etching reactants reaching the wafer surface, etc.
• the symmetry of the lower electrode loop is an important factor in determining the uniformity of the etching process.
• the geometric structure of components such as the film transfer port, exhaust port, cantilever, etc. is asymmetric, which will have a great impact on the uniformity of etching.
• the purpose of the embodiments of the present disclosure is to provide a semiconductor process chamber and semiconductor process equipment, which can solve the problem that the asymmetric geometric structure of components in current etching equipment affects the etching uniformity.
• the embodiment of the present disclosure provides a semiconductor process chamber, comprising: a chamber and a lower electrode structure, wherein the liner and the lower electrode structure are both disposed in the chamber;
• the lower electrode structure comprises a base, an interface component, a carrier, a radio frequency feed-in component and a shielding component; the carrier is used to carry the wafer;
• the base is connected to the side wall of the cavity through a cantilever
• the interface member and the bearing member are sequentially stacked on the base along a first direction;
• the first end of the shielding member is connected to the interface member, and the second end of the shielding member is connected to the inner wall of the base; the axis of the first end of the shielding member does not coincide with the axis of the interface member, and the axis of the first end of the shielding member is offset in a direction away from the cantilever relative to the axis of the interface member;
• the radio frequency feeding component is disposed in the shielding component, and is connected to the supporting component after passing through the interface component along the first direction, so as to feed radio frequency power to the supporting component.
• the embodiment of the present disclosure also provides a semiconductor process equipment, including the above-mentioned semiconductor process chamber.
• a carrier is used to carry a wafer, and a radio frequency feedthrough is connected to the carrier for feeding radio frequency power into the carrier, so that the radio frequency power acts on the plasma on the surface of the wafer to control the energy of ions reaching the surface of the wafer.
• a shielding member is sleeved on the outside of the radio frequency feedthrough to play a shielding role, thereby reducing energy loss.
• a first end of the shielding member is connected to an interface member, and a second end of the shielding member is connected to an inner wall of a base.
• An axis of the first end of the shielding member does not coincide with an axis of the interface member, and an axis of the first end of the shielding member is offset in a direction away from the cantilever relative to the axis of the interface member, thereby increasing the inductance on the side away from the cantilever to compensate for the impedance difference between the lower electrode loop on the side close to the cantilever and the side away from the cantilever, thereby compensating for the asymmetry of the lower electrode loop caused by the inherent asymmetry of the geometric distribution of components in the semiconductor process chamber, thereby making the current density in the electrode loop more uniform to improve the uniformity of the etching process.
• FIG1 is a schematic structural diagram of a semiconductor process chamber disclosed in an embodiment of the present disclosure.
• FIG2 is a schematic diagram of the structure of the lower electrode disclosed in an embodiment of the present disclosure.
• FIG3 is a schematic diagram of the relative position relationship between the RF feedthrough and the carrier according to an embodiment of the present disclosure
• FIG. 4 is a schematic diagram of the relative positional relationship of structures such as an interface component, a shielding component, a second insulating component, a radio frequency feed-through component, a cantilever, and a matcher disclosed in an embodiment of the present disclosure;
• FIG5 is a schematic diagram of the relative position relationship of the shielding member, the RF feed-through member and one form of the second insulating member disclosed in the embodiment of the present disclosure
• FIG. 6 is a schematic diagram of the relative position relationship of the shielding member, the RF feed-through member and another form of the second insulating member disclosed in the embodiment of the present disclosure
• FIG7 is a current density distribution curve on both sides of a semiconductor process chamber when the distance difference between the first distance and the second distance disclosed in an embodiment of the present disclosure is 10 mm;
• FIG8 is a normalized current density distribution curve of both sides of the semiconductor process chamber when the second sub-insulating member is made of resin and the difference between the first distance and the second distance is 50 mm and 100 mm, respectively, in the embodiment of the present disclosure;
• 100-lower electrode structure 110-base; 111-first side wall; 120-interface; 121-through hole; 130- First insulating member; 140-carrying member; 150-RF feeding member; 160-shielding member; 170-second insulating member; 171-first sub-insulating member; 172-second sub-insulating member; 173-interface; 200-lining; 300-grounding ring; 400-Cavity; 500-cantilever; 600-matcher; a-first distance; b-second distance; e-third distance; f-fourth distance.
• first, second, etc. in the specification and claims of the present disclosure are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present disclosure can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first”, “second”, etc. are generally of one type, and the number of objects is not limited.
• the first object can be one or more.
• “and/or” in the specification and claims represents at least one of the connected objects, and the character “/" generally indicates that the objects associated with each other are in an "or” relationship.
• the RF power is loaded on the electrostatic chuck by the RF source through the RF matcher. Specifically, the RF power output by the RF matcher is fed into the center of the electrostatic chuck through the RF connection column.
• the RF connection column, electrostatic chuck, insulating ring, interface disk, shielding sleeve and other components are all concentrically arranged. Due to the existence of the cantilever, the chamber itself is not completely geometrically symmetrical, resulting in differences in the current paths on the cantilever side and the opposite side.
• the current on the lining is opposite to the current on the shielding sleeve, and there is a magnetic field cancellation effect, resulting in the loop inductance on the RF matcher side being smaller than the loop inductance on the opposite side, resulting in asymmetric currents on both sides, affecting the uniformity of the etching process.
• the embodiments of the present disclosure disclose an improved semiconductor process chamber, which comprehensively considers the influence of the asymmetry of geometric elements on the current, thereby effectively solving the asymmetry of the current and ensuring the uniformity of the etching process.
• the disclosed semiconductor process chamber includes a cavity 400 and a lower electrode structure 100.
• the lower electrode structure 100 is disposed in the cavity 400.
• the lower electrode structure 100 includes a base 110, an interface component 120, a carrier component 140, a radio frequency feed component 150, and a shielding component 160.
• the lower electrode structure 100 may also include other components to ensure the normal use of the lower electrode structure 100.
• the semiconductor process chamber may further include a liner 200, which is disposed in the cavity 400 and is disposed around the outer side of the lower electrode structure 100 to protect the cavity 400 from being etched by plasma.
• a liner 200 is electrically connected to the cavity 400, and the other end of the liner 200 is electrically connected to the interface 120, so that electrical conduction between the interface 120 and the cavity 400 can be achieved through the liner 200.
• the base 110 is the basic installation component of the lower electrode structure 100, which can provide a supporting foundation for components such as the interface component 120, the supporting component 140, and the shielding component 160.
• the base 110 can be connected to the side wall of the cavity 400 through the cantilever 500, so that the base 110 can be installed and supported by the cantilever 500.
• the carrier 140 is used to carry the wafer, and the interface member 120 is used to connect the shielding member 160 and can also support the carrier 140.
• the interface member 120 and the carrier 140 are sequentially stacked on the base 110 along the first direction.
• the interface member 120 can be installed on the top of the base 110, and the carrier 140 can be installed on the top of the interface member 120, so that the interface member 120 can be supported by the base 110, and the carrier 140 can be supported by the interface member 120.
• the above-mentioned first direction can be understood as a direction from bottom to top under actual use conditions, as shown in Figure 2.
• the carrier 140 may be a carrier plate, such as an electrostatic chuck.
• the carrier plate may be a disk having a carrier surface for carrying the wafer.
• the carrier 140 may allow the fed RF power to act on the plasma on the surface of the wafer to control the plasma to reach the wafer. Ion energy at the circular surface.
• the interface member 120 may be an interface disk, for example, a circular disk, which may provide a mounting base for the shielding member 160 and ensure the mounting stability of the shielding member 160.
• the interface disk may be provided with an opening to facilitate the passage of the RF feedthrough 150.
• the first end of the shielding member 160 is connected to the interface member 120, and the second end of the shielding member 160 is connected to the inner wall of the base 110; the RF feedthrough 150 is disposed in the shielding member 160, and is connected to the carrier 140 after passing through the interface member 120 in the first direction, so as to feed RF power to the carrier 140.
• the shielding member 160 by sleeve-arranging the shielding member 160 on the outside of the RF feedthrough 150, a section of the RF feedthrough 150 located in the cavity of the base 110 can be shielded to achieve a shielding effect, effectively alleviate energy loss, and reduce the impact on the etching process to a certain extent.
• the shielding member 160 may be a shielding cylinder, specifically, the shielding member 160 may include a straight section and a curved section that are connected or integrally arranged, wherein the end of the curved section that is away from the straight section is the first end of the shielding member 160, and the end of the straight section that is away from the curved section is the second end of the shielding member 160. Based on this, the shielding member 160 may shield the portion of the RF feedthrough 150 that penetrates the base 110, so as to play a shielding role.
• the RF feedthrough 150 is used to connect to the matcher 600, and the matcher 600 is arranged on a side outside the cavity 400, so that the matcher 600 is also located on a side of the lower electrode structure 100.
• the side wall of the base 110 close to the matcher 600 can be defined as the first side wall 111.
• an opening may be provided on the first side wall 111 of the base 110, so that the RF feedthrough 150 enters into the cavity of the base 110 through the opening, passes through the interface member 120 and extends toward the carrier 140, and finally is connected with the carrier 140, so as to transmit the RF power output by the RF source through the matcher 600 to the carrier 140, thereby controlling the ion energy reaching the surface of the wafer carried by the carrier 140.
• the lower electrode structure 100 is fixed to the cavity 400 by the cantilever 500.
• the cantilever 500 may be provided with a cantilever channel, and the shielding member 160 may penetrate into the cantilever channel after passing through the first side wall 111, and finally be connected to the side wall of the cavity 400, so that a section of the RF feed 150 located between the first side wall 111 of the base 110 and the side wall of the cavity 400 may be shielded to achieve a shielding effect, effectively alleviate energy loss, and reduce the impact on the etching process to a certain extent;
• the cantilever channel is mainly used to connect external cables and pipelines, and is also used to achieve grounding with the cavity 400 to form an electrical circuit.
• the geometric structure of the lower electrode structure 100 is asymmetric on the side close to the cantilever 500 and the side away from the cantilever 500, resulting in differences in current density in the respective loops of the lower electrode structure 100 on the side close to the cantilever 500 and the side away from the cantilever 500, which in turn affects the uniformity of etching.
• the axis of the first end of the shielding member 160 does not coincide with the axis of the interface member 120, and the axis of the first end of the shielding member 160 deviates from the axis of the interface member 120 in the direction away from the cantilever 500 to increase the inductance of this side, thereby compensating for the impedance difference between the lower electrode loop on the side close to the cantilever and the side away from the cantilever.
• the asymmetry of the lower electrode loop caused by the inherent asymmetry of the geometric distribution of components in the semiconductor process chamber can be compensated, thereby making the current density in the electrode loop more uniform, thereby improving the uniformity of the etching process.
• the axis of the feeding end of the RF feed 150 does not coincide with the axis of the first end of the shield 160, and the axis of the feeding end of the RF feed 150 is offset relative to the axis of the first end of the shield 160 toward the cantilever 500.
• the RF feed 150 and the shield 160 are non-concentric structures, and the distance from the axis of the first end of the shield 160 to the first side wall 111 is greater than the distance from the axis of the feeding end of the RF feed 150 to the first side wall 111.
• the distance from the edge of the first end of the shield 160 close to the first side wall 111 to the axis of the RF feed 150 is a third distance e
• the distance from the edge of the first end of the shield 160 far from the first side wall 111 is a third distance e.
• the distance from the edge of to the axis of the RF feedthrough 150 is a fourth distance f
• the third distance e is less than the fourth distance f.
• the axis of the feeding end of the RF feeding element 150 is located between the axis of the first end of the shielding element 160 and the axis of the interface element 120 .
• the inductance in the respective loops on the side close to the cantilever 500 and the side away from the cantilever 500 can be adjusted, so that the current density in the loops on both sides is also adjusted, that is, the current density difference in the loops on both sides is compensated, so that the current density in the loop close to the matcher side and the current density in the loop away from the matcher side can be made symmetrical, thereby ensuring the uniformity of the etching process.
• the lower electrode structure 100 may further include a second insulating member 170.
• the interface member 120 may be provided with a through hole 121
• the second insulating member 170 is disposed in the through hole 121
• the RF feedthrough 150 passes through the second insulating member 170. Based on this, by providing the through hole 121, an installation space can be provided for the second insulating member 170, and the RF feedthrough 150 can be separated from the interface member 120 by the second insulating member 170, so as to achieve insulation treatment of the RF feedthrough 150.
• the first end of the shielding member 160 is connected to the through hole 121 of the interface member 120, and the axis of the first end of the shielding member 160 is collinear with the axis of the second insulating member 170.
• the axis of the through hole 121, the axis of the first end of the shielding member 160 and the axis of the second insulating member 170 are collinear.
• the axis of the feeding end of the RF feed 150 is not collinear with the axis of the first end of the shielding member 160, the axis of the feeding end of the RF feed 150 is also not collinear with the axis of the second insulating member 170.
• the width dimension of the second insulating member 170 on the side of the RF feed 150 close to the cantilever 500 is smaller than the width dimension of the second insulating member 170 on the side of the RF feed 150 away from the cantilever 500, so as to ensure the assembly between the interface member 120 and the shielding member 160, and facilitate the assembly of the RF feed 150.
• the direction of the width dimension is parallel to the radial direction of the through hole 121 from the cantilever 500 to away from the cantilever 500 .
• the through hole 121 can be set at a position of the interface member 120 that is biased away from the cantilever 500 relative to the axis of the interface member 120, that is, the axis of the through hole 121 is located on the side of the axis of the interface member 120 that is away from the cantilever 500, so that the installation of the RF feedthrough 150 can be adapted through the second insulating member 170 installed therein to prevent assembly interference between the components.
• the distance from the edge of the interface member 120 on the side close to the cantilever 500 to the axis of the through hole 121 is the fifth distance
• the distance from the edge of the interface member 120 on the side away from the cantilever 500 to the axis of the through hole 121 is the sixth distance
• the fifth distance is greater than the sixth distance, that is, the width dimension of the portion of the interface member 120 close to the cantilever 500 is greater than the width dimension of the portion away from the cantilever 500, so as to facilitate the installation of the RF feed 150.
• the distance difference between the fifth distance and the sixth distance depends on the eccentricity of the RF feed 150 and the eccentricity of the second insulating member 170. In actual design, it is sufficient to ensure the assembly of the interface member 120 and the shielding member 160.
• the second insulating member 170 may include a first sub-insulating member 171 and a second sub-insulating member 172 that are matched, wherein the first sub-insulating member 171 is located on a side close to the cantilever 500, and the second sub-insulating member 172 is located on a side away from the cantilever 500, and the capacitance between the RF feedthrough 150 and the interface member 120 on the side where the first sub-insulating member 171 is located is greater than the capacitance between the interface member 120 on the side where the second sub-insulating member 172 is located.
• the projection area of the first sub-insulating member 171 is smaller than the projection area of the second sub-insulating member 172.
• This arrangement allows the first sub-insulating member 171 and the second sub-insulating member 172 to be asymmetrical, so as to adjust the capacitance between the side portion of the second insulating member 170 close to the cantilever 500 and the side portion away from the cantilever 500, thereby adjusting the impedance of the loops on both sides, and further adjusting the current density in the circuits on both sides, that is, compensating for the difference in current density in the circuits on both sides, making the current density in the circuits on both sides more uniform, and It is convenient to improve etching uniformity.
• the first sub-insulator 171 and the second sub-insulator 172 may also have different relative dielectric constants.
• the relative dielectric constant of the first sub-insulator 171 may be greater than the relative dielectric constant of the second sub-insulator 172, so that the capacitance between the interface component 120 and the RF feedthrough 150 on the side away from the cantilever 500 can be further ensured to be smaller, thereby reducing the impedance in the loop on the side away from the cantilever 500, and achieving a compensation effect for the inconsistent impedance in the loops on both sides.
• first sub-insulator 171 and the second sub-insulator 172 may also have the same relative dielectric constant, which may be selected according to actual working conditions.
• the projected area of the second insulating member 170 is smaller than the projected area of the through hole 121, and the second insulating member 170 is disposed on the side of the through hole 121 close to the cantilever 500.
• the part of the through hole 121 where the second insulating member 170 is not disposed can be filled with air.
• the air can also be used as a special medium to play a certain insulating role.
• the second insulating member 170 does not exist on the side of the through hole 121 away from the cantilever 500, and insulation is achieved by air.
• air can be regarded as an insulating medium with a relative dielectric constant of 1.
• the relative dielectric constant of the second insulating member 170 is greater than 1, so as to reduce the loop impedance away from the matching device side.
• the first sub-insulating member 171 may be made of ceramic
• the second sub-insulating member 172 may be made of resin, and the relative dielectric constant of ceramic is greater than that of resin.
• FIG8 is a current density distribution curve on both sides of the semiconductor process chamber when the first sub-insulator 171 is made of ceramic material and the second sub-insulator 172 is made of resin
• FIG9 is a current density distribution curve on both sides of the semiconductor process chamber when the second insulating member 170 made of ceramic material is set on one side of the through hole 121 close to the cantilever 500 and the other side is filled with air. It can be seen from FIG8 and FIG9 that air is more effective in improving the symmetry of the current density on both sides because the relative dielectric constant of air is lower.
• the air medium etching current density can be made more symmetrical.
• the internal structure such as the lower electrode structure 100 also has components such as a pin lifting motor and a chiller tube, it is difficult to ensure the symmetry of the current density in the loops on both sides under the condition of a large distance difference from the perspective of mechanical design.
• the width difference between the first sub-insulator 171 and the second sub-insulator 172 can be designed to be in the range of 5mm to 50mm, specifically including 5mm, 10mm, 20mm, 25mm, 30mm, 40mm, 50mm, etc., and of course, other values can also be used.
• the width difference can be selected as 25mm, so as to make the current density in the loops on both sides symmetrical.
• the interface 173 between the first sub-insulator 171 and the second sub-insulator 172 may be a curved surface, and the cavity 400 is a cylindrical structure, and the curved surface design may adapt to the cylindrical cavity 400.
• the interface 173 may be a circular arc convex toward the direction of the first sub-insulator 171, as shown in FIG5, and of course, it may also be a circular arc convex toward the direction of the second sub-insulator 172, as shown in FIG6.
• the interface 173 between the first sub-insulator 171 and the second sub-insulator 172 may be a plane.
• the second insulating member 170 may be a disc-shaped structure, which is divided into the first sub-insulator 171 and the second sub-insulator 172 by a plane, so that it can be divided into the first sub-insulator 171 and the second sub-insulator 172, which are respectively fan-shaped disc structures.
• the first sub-insulator 171 may be a less than half disc structure
• the second sub-insulator 172 may be a more than half disc structure.
• the specific shape of the interface 173 is not limited, as long as the projection area of the first sub-insulator 171 is smaller than the projection area of the second sub-insulator 172 on the plane perpendicular to the axis of the second insulating member 170 .
• the axis of the feeding end of the RF feedthrough 150 may be located on the interface 173 between the first sub-insulating member 171 and the second sub-insulating member 172, and may be located on the interface 173 which is a plane or a curved surface, as shown in FIGS. 4 and 6, so as to ensure that the projection area of the second sub-insulating member 172 on the plane perpendicular to the axis of the second insulating member 170 is greater than the projection area of the first sub-insulating member 171 on the plane perpendicular to the axis of the second insulating member 170. shadow area.
• the axis of the RF feed 150 may not be on the interface 173. Instead, the axis of the feeding end of the RF feed 150 may be located on the side of the first sub-insulating member 171 away from the cantilever 500, and the RF feed 150 is located on the second sub-insulating member 172. This method can also meet the process requirements.
• the interface 173 between the first sub-insulator 171 and the second sub-insulator 172 is an arc convex toward the first sub-insulator 171, and the axis of the first end of the RF feedthrough 150 is located on the side of the interface 173 away from the cantilever 500.
• a dielectric region with a relatively high dielectric constant i.e., a local region of the first sub-insulator 171 on the side of the RF feedthrough 150 away from the cantilever 500.
• the dielectric region with a relatively high dielectric constant can increase the capacitance between the interface 120 and the RF feedthrough 150.
• the interface 173 between the portion with a relatively high dielectric constant and the portion with a relatively low dielectric constant needs to be appropriately moved closer to the cantilever 500 to perform certain compensation, thereby reducing the average relative dielectric constant of the dielectric on the side of the RF feedthrough 150 away from the cantilever 500, and thereby reducing the capacitance between the interface 120 and the RF feedthrough 150 on the side away from the cantilever 500.
• the cavity 400 can be a cylindrical structure, and the best effect of relative dielectric constant compensation of the two insulating parts should be an axisymmetric structure. Therefore, the arc-shaped curved surface high and low relative dielectric constant interface 173 shown in Figures 5 and 6 has a better compensation effect than the plane high and low relative dielectric constant interface 173 shown in Figure 4, because the plane interface 173 forms a left-right symmetrical structure rather than an axisymmetric structure.
• the axis of the feeding end of the RF feedthrough 150 does not coincide with the axis of the carrier 140, and the axis of the feeding end of the RF feedthrough 150 is offset relative to the axis of the carrier 140 in a direction away from the cantilever 500.
• the feeding end of the RF feedthrough 150 can be made non-concentric (or non-coaxial) with the carrier 140, thereby compensating for the asymmetry of the two sides of the lower electrode structure 100 caused by the asymmetric geometric structure, so that the lower electrode structure 100 can be close to the cantilever 500.
• the current in the loop on the side of the cantilever 500 and the side away from the cantilever 500 is more uniform, thereby improving the uniformity of the etching process.
• FIG3 is a top view of the eccentric relationship between the carrier 140 and the RF feedthrough 150 . It can be seen from FIG3 that the distance b1 from the axis of the RF feedthrough 150 on the side away from the cantilever 500 to the edge of the carrier 140 is smaller than the distance a1 between the two on the side close to the cantilever 500 .
• the spacings c1 and d1 on the other two sides can be kept equal.
• c1 and d1 can also be made inconsistent, which can be determined according to actual working conditions.
• the lower electrode structure 100 may also include a first insulating component 130, which is connected between the supporting component 140 and the interface component 120.
• the first insulating component 130 can not only achieve a supporting effect on the supporting component 140, but also achieve an insulation effect between the supporting component 140 and the interface component 120.
• the first insulating member is provided with a through hole, and the feeding end of the RF feedthrough 150 passes through the through hole and is connected to the carrier 140 .
• the RF feedthrough 150 can be avoided through the through hole to ensure that the RF feedthrough 150 can be connected to the carrier 140 .
• the axis of the through hole does not coincide with the axis of the first insulating member 130, and the axis of the through hole is offset relative to the axis of the first insulating member 130 in a direction away from the cantilever 500.
• the distance from the side of the first insulating member 130 close to the cantilever 500 to the axis of the through hole is a first distance a
• the distance from the side of the first insulating member 130 away from the cantilever 500 to the axis of the through hole is a second distance b
• the first distance a is greater than the second distance b.
• the diameter of the first insulating member 130 is equal to the diameter of the carrier 140, and the two are coaxially arranged to ensure the symmetry of the installation of the two and also facilitate the installation between the two.
• the distance a1 from the side of the carrier 140 close to the cantilever 500 to the axis of the RF feed 150 is equal to the first distance a
• the distance b1 from the side of the carrier 140 away from the cantilever 500 to the axis of the RF feed 150 is equal to the second distance b.
• a1 is also greater than b1.
• the inductance in the respective loops on the side close to the cantilever 500 and the side away from the cantilever 500 can be adjusted, so that the current density in the loops on both sides can be adjusted accordingly, that is, the current density difference in the loops on both sides is compensated, so that the current density in the loop on the side close to the cantilever 500 can be made symmetrical with the current density in the loop on the side away from the cantilever 500, thereby ensuring the uniformity of the etching process.
• the distance difference between the first distance a and the second distance b ranges from 5 mm to 20 mm, including 5 mm, 8 mm, 10 mm, 12 mm, 15 mm, 18 mm, 20 mm, etc. Of course, it can also be other values.
• the specific value of the distance difference can be set according to the distribution of the geometric structure, and the embodiment of the present disclosure does not make specific limitations on this.
• the first distance a and the second distance b may differ by 10 mm.
• the current density distribution curves in the respective loops close to the cantilever 500 side and the side away from the cantilever 500 may be obtained through simulation, as shown in FIG7 . It can be seen from FIG7 that when the distance difference is 10 mm, the current density in the respective loops close to the cantilever 500 side and the side away from the cantilever 500 side is relatively symmetrical. This is because the current reverses on the side close to the cantilever 500, which results in a cancelling effect, resulting in the inductance being smaller than that on the side away from the cantilever 500. Therefore, by adjusting the inductance on both sides to be relatively balanced, the symmetry of the current can be improved, further ensuring the uniformity of the etching process.
• the first insulating member 130 may be an insulating disk, wherein the insulating disk may be a circular disk, which may support the carrier 140 and insulate the carrier 140.
• the insulating disk may also be provided with an opening to allow the RF feedthrough 150 to pass through.
• the embodiment of the present disclosure also discloses a semiconductor process equipment, and the disclosed semiconductor process equipment includes the above-mentioned semiconductor process chamber provided by the present disclosure.
• the semiconductor process chamber includes the above-mentioned lower electrode structure 100, and in addition, it can also include a cavity 400, a liner 200, a grounding ring 300, a cantilever 500, a matcher 600 and other parts.
• the liner 200 is arranged on the inner surface of the side wall of the cavity 400
• the cantilever 500 is connected to the side wall of the cavity 400
• the lower electrode structure 100 is arranged in the cavity 400 and connected to the cantilever 500
• the matcher 600 is arranged outside the cavity 400 and connected to the cantilever 500.
• the arm 500 is correspondingly arranged, and the grounding ring 300 is sleeved on the outer side of the lower electrode structure 100 and contacts the liner 200. It should be noted here that the specific structure and working principle of the semiconductor process equipment can refer to the relevant technology and will not be elaborated here.
• the current loop on the cantilever 500 side is: liner 200 - grounding ring 300 - interface component 120 - shielding component 160 - matcher 600; the current loop on the opposite side of the cantilever 500 is: liner 200 - grounding ring 300 - interface component 120 - shielding component 160 - matcher 600.
• the shielding member 160 and the interface member 120 are non-coaxially (or non-concentrically), so that the asymmetry of the lower electrode loop caused by the inherent asymmetry of the geometric distribution of components in the semiconductor process chamber can be compensated, so that the current density in the lower electrode loop can be more uniform, thereby improving the uniformity of the etching process.

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• 2022
  • 2022-10-31 CN CN202211347495.6A patent/CN115692263B/zh active Active
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