WO2024090143A1 - 装置、電気装置および基板 - Google Patents

装置、電気装置および基板 Download PDF

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Publication number
WO2024090143A1
WO2024090143A1 PCT/JP2023/035853 JP2023035853W WO2024090143A1 WO 2024090143 A1 WO2024090143 A1 WO 2024090143A1 JP 2023035853 W JP2023035853 W JP 2023035853W WO 2024090143 A1 WO2024090143 A1 WO 2024090143A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
substrate
solder
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/035853
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English (en)
French (fr)
Japanese (ja)
Inventor
大介 豊田
和孝 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to EP23882352.0A priority Critical patent/EP4611024A1/en
Priority to CN202380074396.1A priority patent/CN120092315A/zh
Priority to JP2024552908A priority patent/JPWO2024090143A1/ja
Publication of WO2024090143A1 publication Critical patent/WO2024090143A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02992—Details of bus bars, contact pads or other electrical connections for finger electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders or supports
    • H03H9/058—Holders or supports for surface acoustic wave devices
    • H03H9/059—Holders or supports for surface acoustic wave devices consisting of mounting pads or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads

Definitions

  • This disclosure relates to devices, electrical devices and substrates.
  • Devices that contain electronic components are mounted on the mounting board of the electrical device using solder.
  • the acoustic wave device described in Cited Document 1 includes a pad (electrode) provided on a piezoelectric substrate, and an under-bump metal provided on the pad to facilitate bonding with solder.
  • the device has a substrate having a first surface, an electrode located on the first surface of the substrate and containing Ni and Cu, and a joint located on the electrode, the joint including, in order from the electrode side, a barrier layer, a joint layer, and a solder layer, the barrier layer including Mo as a main component, and the joint layer including at least one of Ni, Ag, Au, and Cu.
  • FIG. 1 is a cross-sectional structural diagram of an apparatus according to a first embodiment of the present disclosure.
  • 1 is a cross-sectional structural view showing an electronic module according to a first embodiment of the present disclosure.
  • 1 is a micrograph of a joint according to a first embodiment of the present disclosure.
  • FIG. 4 is an enlarged view of a region R in FIG. 3 .
  • 11 is a cross-sectional view of an elastic wave device according to a second embodiment of the present disclosure.
  • FIG. 4 is a micrograph of a joint of an electronic module according to an example and a comparative example.
  • 13 is a graph showing the results of evaluation of bonding strength for the comparative example.
  • 13 is a graph showing the results of evaluation of bonding strength for the comparative example.
  • 13 is a graph showing the results of evaluation of bonding strength for the comparative example.
  • 1 is a graph showing the results of evaluation of bonding strength for examples.
  • sufficient interfacial strength can be ensured at the solder joint even after high-temperature processes such as reflow bonding.
  • the device 200 may be, for example, an electronic device including a substrate and an electronic component such as an electronic element mounted on the substrate.
  • FIG. 1 is a cross-sectional view showing a portion of device 200 according to embodiment 1 of the present disclosure.
  • FIG. 1 is an enlarged cross-sectional view of one electrode 21 provided in device 200, and does not show electronic components provided in device 200.
  • the device 200 includes a substrate 110 and a solder layer 33.
  • the substrate 110 includes a base 11, an electrode 21, a barrier layer 31, and a bonding layer 32.
  • the base 11 has an electrode 21 on a first surface 11a.
  • the barrier layer 31, the bonding layer 32, and the solder layer 33 are layered in this order from the electrode 21 side.
  • the barrier layer 31, the bonding layer 32, and the solder layer 33 are referred to as a bonding portion 30.
  • the bonding portion 30 is located on the electrode 21.
  • the barrier layer 31, the bonding layer 32, and the solder layer 33 are each elements that constitute the bonding portion 30.
  • FIG. 2 is a cross-sectional structural diagram showing a portion of an electronic module 300 including a device 200. As shown in FIG. 2, the device 200 can be mounted on a mounting board (module board) 120 to form an electronic module 300.
  • the electronic module 300 is an example of an electrical device according to the present disclosure.
  • the mounting substrate 120 comprises a base 12, an electrode 22, a barrier layer 31 and a bonding layer 32.
  • the base 12 has an electrode 22 on a first surface 12a.
  • the barrier layer 31 is located on the electrode 22, and the bonding layer 32 is located on the barrier layer 31.
  • the barrier layer 31, the bonding layer 32 and the solder layer 33 provided in the electronic module 300 are each elements that constitute a bonding portion 30. In other words, the bonding portion 30 is located on the electrode 22.
  • the substrate 110 and the mounting substrate 120 are an example of the substrate 100 according to the present disclosure.
  • content common to the substrate 110 and the mounting substrate 120 may be described as the substrate 100, which collectively refers to the substrate 110 and the mounting substrate 120.
  • the substrate 110 is a substrate on which electronic components are mounted, and may include internal wiring located inside the substrate 110, and through conductors that connect the internal wirings vertically.
  • the base 11 of the substrate 110 may be composed of a single layer or multiple layers.
  • the base 11 has a first surface 11a and a second surface 11b located on the opposite side of the first surface 11a.
  • An electronic component such as an electronic element may be mounted on either the first surface 11a or the second surface 11b.
  • the substrate 11 may be insulating.
  • the material of the substrate 11 may be a ceramic, such as an aluminum nitride sintered body, an aluminum oxide sintered body (alumina ceramics), a silicon nitride sintered body, a mullite sintered body, or a glass ceramic sintered body.
  • the material of the substrate 11 may be an epoxy resin, a polyimide resin, an acrylic resin, a phenolic resin, or a fluorine-based resin.
  • An example of the fluorine-based resin may be a resin such as a polyester resin or a polytetrafluoroethylene resin.
  • the mounting board 120 is a circuit board mounted on the electronic module and may include electrical circuits inside and/or outside the mounting board.
  • the electrodes 21 and 22 are examples of the electrode 20 according to the present disclosure. Regarding the content common to the electrodes 21 and 22, the electrodes 21 and 22 may be described as the electrode 20, which is a general term for the electrodes 21 and 22.
  • the electrode 21 on the substrate 110 electrically connects the device 200 to the circuit board.
  • the electrode 21 is located on the first surface 11a of the base 11.
  • the substrate 110 may have multiple electrodes 21 on the first surface 11a.
  • the substrate 110 may have a metallized layer on the surface of the base 11 in addition to the electrodes 21.
  • the metallized layer includes, for example, a metallized layer that is provided in a mounting area on the base 11 where an electronic component is mounted and that can be electrically connected to the electronic component.
  • the metallization layer is made of, for example, any one of W (tungsten), Mo (molybdenum), Mn (manganese), Ag (silver), Ni and Cu, or an alloy containing at least one of these.
  • the metallization layer is made of, for example, any one of Cu, Au (gold), Al (aluminum), Ni, Mo and Ti (titanium), or an alloy containing at least one of these.
  • the internal wiring and through conductors are also made of the same alloy as the metallization layer.
  • the electrodes 22 on the mounting board 120 electrically connect the mounting board 120 to an electronic device or the like.
  • the electrodes 22 are located on the first surface 12a of the base 12.
  • Electrode 20 may be made of an alloy containing Ni (nickel) and Cu (copper). Electrode 21 may contain metals other than Ni and Cu.
  • the barrier layer 31 is a layer containing Mo as a main component.
  • the manufacturing process of the device 200 and the electronic module 300 includes a soldering process, which is a high-temperature process.
  • a soldering process which is a high-temperature process.
  • molten high-temperature solder is applied onto the electrode 21.
  • the device 200 or the electronic module 300 with solder applied to the electrode portion is heated in a reflow furnace.
  • the soldered joint may be repeatedly or continuously exposed to a high-temperature state due to heat generation of the module during use of the electronic module 300.
  • the electrode metals such as Cu and Ni contained in the electrode 20 melt and react with metals such as Sn (tin) and Cu contained in the solder to form a metal compound.
  • the metal compound is hard and brittle, and is likely to become the starting point of cracks.
  • the thickness of the barrier layer 31 may be, for example, 0.1 ⁇ m or more. By having the barrier layer 31 have a thickness of 0.1 ⁇ m or more, the possibility of reaction between the electrode metal and the metal of the solder layer can be significantly reduced.
  • the bonding layer 32 is a layer that is located between the solder layer 33 and the barrier layer 31 and contains at least one of Ni, Ag, Au, and Cu. The presence of the bonding layer 32 ensures the wettability of the solder, thereby improving the interfacial strength of the solder interface.
  • the bonding layer 32 may contain Ni, a Ni-Sn compound, Cu, or a Cu-Sn compound as its main component. Ni and Cu have excellent wettability with solder, which can further improve the interfacial strength.
  • the thickness of the bonding layer 32 may be smaller than the thickness of the electrode 20.
  • the thickness of the bonding layer 32 may be 0.1 ⁇ m or more and 1 ⁇ m or less, or may be 0.1 ⁇ m.
  • the metal contained in the bonding layer 32 may react with the metal contained in the solder to form a metal compound.
  • the bonding layer 32 By making the bonding layer 32 have the thickness described above, the amount of metal eluted from the bonding layer 32 during solder bonding, etc., can be reduced, and the amount of metal compounds formed can be reduced.
  • the amount of metal eluted from a sufficiently thin bonding layer 32 is small, coarse particles of metal compounds are less likely to form and the layer is less likely to become brittle. In other words, a bonding portion 30 having excellent interfacial strength can be achieved while maintaining the wettability of the solder.
  • solder layer 33 is a layer containing a metal such as Sn, Ag, or Cu.
  • FIG. 3 is a micrograph of the joint 30 in the electronic module 300 shown in Fig. 2.
  • Fig. 4 is an enlarged view of region R in Fig. 3.
  • the micrographs shown in Figs. 3 and 4 are of the electronic module 300 after soldering in a reflow furnace.
  • the solder layer 33 melts due to heating during soldering in the manufacturing process.
  • at least a part of the metal in the joint layer 32 reacts with the metal contained in the solder layer 33 to form one or more compounds.
  • Region C in Fig. 4 is a region containing a large amount of the compound.
  • the one or more compounds include, for example, Ni-Sn compounds and Cu-Sn compounds.
  • region C contains at least one compound selected from the group consisting of Ni3Sn4 , Ni3Sn2 , Ni3Sn , (Cu,Ni) 3Sn4 , and (Cu, Ni ) 6Sn5 .
  • the bonding layer 32 may contain Ni, a Ni-Sn compound, Cu or a Cu-Sn compound as a main component.
  • the bonding layer 32 may be a layer defined between the upper surface of the barrier layer 31 and a surface that is approximately parallel to the upper surface of the barrier layer 31 and is located at the top of region C.
  • the bonding layer 32 may be a layer defined between the upper surface of the barrier layer 31 and the boundary of region C on the solder layer side.
  • the bonding layer 32 may be a layer having projections and recesses, and may have holes in some parts of it.
  • the substrate 100 can reduce the amount of Sn-containing compounds formed near the interface between the solder layer 33 and the bonding layer 32 while ensuring the wettability of the solder during solder bonding. As a result, the substrate 100 can provide a device or electronic module that has sufficient interfacial strength at the solder bonding portion even after undergoing high-temperature processes such as reflow bonding.
  • the device 200 and the electronic module 300 have the substrate 100 and the joint 30, sufficient interfacial strength can be ensured at the solder joint even after high-temperature processes such as reflow bonding.
  • FIG. 5 is a cross-sectional structural diagram of an elastic wave device 210 according to the second embodiment.
  • the elastic wave device 210 includes a substrate 130 and a solder layer 33.
  • the substrate 130 includes a base 13, an electrode layer 23, a barrier layer 31, and a bonding layer 32.
  • the elastic wave device 210 can be mounted on a circuit board (mounting board) of a communication device.
  • the base 13 includes a piezoelectric layer 13A and a support substrate 13B that supports the piezoelectric layer 13A.
  • the piezoelectric layer 13A has a first surface 13a that is located on the opposite side to the surface that is bonded to the support substrate 13B.
  • the electrode layer 23 is provided on the first surface 13a of the piezoelectric layer 13A.
  • the barrier layer 31, the bonding layer 32, and the solder layer 33 are layered in this order from the electrode layer 23 side.
  • the barrier layer 31, the bonding layer 32, and the solder layer 33 are referred to as a bonding portion 30.
  • the bonding portion 30 is located on the electrode layer 23.
  • the barrier layer 31, the bonding layer 32, and the solder layer 33 are each elements that constitute the bonding portion 30.
  • the base 13 is not limited to the above configuration.
  • the base 13 does not need to include the support substrate 13B.
  • the piezoelectric layer 13A itself also serves as the support substrate 13B.
  • the base 13 is an example of the base 10 according to the present disclosure
  • the substrate 130 is an example of the substrate 100 according to the present disclosure.
  • the electrode layer 23 includes an IDT (Interdigital Transducer) electrode 231 and a pad portion 232.
  • the pad portion 232 includes a first pad 232A and a second pad 232B.
  • the pad portion 232 in this embodiment is an example of an electrode 20 according to the present disclosure.
  • the first pad 232A and the second pad 232B are laminated in this order from the base 13 side. In other words, the pad portion 232 may include multiple layers.
  • the first pad 232A may have the same thickness as the IDT electrode 231.
  • the pad portion 232 has a laminated structure, which can reduce electrical resistance.
  • the IDT electrode 231 is a comb-shaped electrode that generates an elastic wave in the elastic wave device.
  • the IDT electrode 231 is composed of a pair of electrodes to which an AC voltage is applied.
  • the IDT electrode 231 is electrically connected to the pad portion 232.
  • the elastic wave device 210 has a feature that there are fewer joints that are bonded via the joints 30. Therefore, ensuring the interfacial strength at the joints 30 is more important. Because the elastic wave device 210 has the substrate 130 and the joints 30, it is possible to ensure sufficient interfacial strength at the solder joints even after high-temperature processes such as reflow bonding.
  • a SAW Surface Acoustic Wave
  • BAW Bulk Acoustic Wave
  • Fig. 6 is a micrograph of a joint of an electronic module.
  • Reference numeral 6001 in Fig. 6 is a micrograph of a joint 30 in an electronic module 300 according to an embodiment of the present disclosure.
  • Reference numeral 6002 in Fig. 6 is a micrograph of a joint of an electronic module as a comparative example.
  • a solder layer is located between the electrode on the electronic device side and the mounting substrate.
  • the electronic module does not have the barrier layer 31 and bonding layer 32 according to the present disclosure.
  • the heating conditions during solder bonding are the same for both the embodiment and the comparative example.
  • a region C containing a large amount of a compound formed by a reaction between the electrode metal and the metal contained in the solder layer exists as a coarse granular region near the interface of the joint.
  • a large amount of the electrode metal has dissolved toward the solder layer, forming a void P at the interface of the joint.
  • the area C near the interface of the joint 30 remains a relatively small area.
  • the void P observed in the comparative example was not observed.
  • barrier layer 31 and bonding layer 32 disclosed herein significantly reduces the formation of brittle compounds in the solder joint, even after high-temperature processes such as reflow bonding. It has also been demonstrated that the elution of the electrode metal into the solder layer is reduced, thereby reducing the possibility of voids occurring at the interface between the electrode and the joint.
  • Bond strength test 7 to 10 are graphs showing the results of evaluating the bonding strength when the metal used in the barrier layer is changed.
  • the evaluation test of the bonding strength was performed in accordance with the solder ball shear standard of JEDEC JESD22-B117.
  • Comparative Example 1 a Ni layer was laminated on the substrate as an electrode, a TaN (tantalum nitride) layer was laminated as a barrier layer, and a solder ball was placed on top of that.
  • Figure 7 shows the results of a test performed on the configuration of Comparative Example 1 after one reflow process and after three reflow processes.
  • Comparative Example 2 a Ni layer was laminated on the substrate as an electrode, a TiN (titanium nitride) layer was laminated on the substrate as a barrier layer, and solder balls were placed on top of the layers.
  • Figure 8 shows the results for Comparative Example 2.
  • Comparative Example 3 a Ni layer was laminated on the substrate as an electrode, a W (tungsten) layer was laminated on the substrate as a barrier layer, and solder balls were placed on top of the layers.
  • Figure 9 shows the results for Comparative Example 3.
  • a Ni layer was laminated on a substrate as an electrode, and a Mo (molybdenum) layer, the same as the barrier layer 31 of the present disclosure, was laminated as a barrier layer, and a solder ball was placed on top of the layer.
  • Figure 10 shows the results of the example.
  • the graphs show no sudden drop in load within the test range of displacement, whether the reflow process was performed once or three times. In other words, it was demonstrated that the interfacial strength was maintained within the test range of displacement.
  • a device of a first aspect of the present disclosure has a base having a first surface, an electrode located on the first surface of the base and including Ni and Cu, and a joint located on the electrode, the joint including, in order from the electrode side, a barrier layer, a joint layer, and a solder layer, the barrier layer including Mo as a main component, and the joint layer including at least one of Ni, Ag, Au, and Cu.
  • the second aspect of the device disclosed herein is the device of the first aspect, in which the thickness of the barrier layer is 0.1 ⁇ m or more.
  • the device of the third aspect of the present disclosure is the device of the first or second aspect, in which the bonding layer contains Ni, a Ni-Sn compound, Cu, or a Cu-Sn compound as a main component.
  • a fourth aspect of the device of the present disclosure is a device according to any one of the first to third aspects, in which the electrode is provided on the piezoelectric layer and connected to the IDT electrode.
  • An electrical device includes any one of the devices according to the first to fourth aspects of the present disclosure.
  • a substrate according to a sixth aspect of the present disclosure has a base having a first surface, an electrode located on the first surface of the base and containing Ni and Cu, a barrier layer located on the electrode, and a bonding layer located on the barrier layer, the barrier layer containing Mo as a main component, and the bonding layer containing at least one of Ni, Ag, Au, and Cu.
  • a seventh aspect of the substrate of the present disclosure is the substrate of the sixth aspect, in which the thickness of the bonding layer is smaller than the thickness of the electrode.
  • the eighth aspect of the substrate of the present disclosure is the substrate of the sixth or seventh aspect, in which the thickness of the bonding layer is 0.1 ⁇ m or more and 1 ⁇ m or less.

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  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
PCT/JP2023/035853 2022-10-27 2023-10-02 装置、電気装置および基板 Ceased WO2024090143A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP23882352.0A EP4611024A1 (en) 2022-10-27 2023-10-02 Device, electrical device, and substrate
CN202380074396.1A CN120092315A (zh) 2022-10-27 2023-10-02 装置、电气装置以及基板
JP2024552908A JPWO2024090143A1 (https=) 2022-10-27 2023-10-02

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Application Number Priority Date Filing Date Title
JP2022-172651 2022-10-27
JP2022172651 2022-10-27

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094224A (ja) * 2007-10-05 2009-04-30 Fujitsu Ltd 回路基板、半導体装置、及び半導体装置の製造方法
WO2015022931A1 (ja) 2013-08-14 2015-02-19 株式会社村田製作所 弾性波装置、電子部品、および弾性波装置の製造方法
US20210183828A1 (en) * 2019-12-17 2021-06-17 Seoul Viosys Co., Ltd. Method of repairing light emitting device and display panel having repaired light emitting device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094224A (ja) * 2007-10-05 2009-04-30 Fujitsu Ltd 回路基板、半導体装置、及び半導体装置の製造方法
WO2015022931A1 (ja) 2013-08-14 2015-02-19 株式会社村田製作所 弾性波装置、電子部品、および弾性波装置の製造方法
US20210183828A1 (en) * 2019-12-17 2021-06-17 Seoul Viosys Co., Ltd. Method of repairing light emitting device and display panel having repaired light emitting device

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CN120092315A (zh) 2025-06-03
EP4611024A1 (en) 2025-09-03

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