WO2024087695A1 - 电源噪声检测电路及工作方法、抖动限幅电路、电子设备 - Google Patents

电源噪声检测电路及工作方法、抖动限幅电路、电子设备 Download PDF

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Publication number
WO2024087695A1
WO2024087695A1 PCT/CN2023/103192 CN2023103192W WO2024087695A1 WO 2024087695 A1 WO2024087695 A1 WO 2024087695A1 CN 2023103192 W CN2023103192 W CN 2023103192W WO 2024087695 A1 WO2024087695 A1 WO 2024087695A1
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WIPO (PCT)
Prior art keywords
noise
power supply
phase
signal
sampling
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PCT/CN2023/103192
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English (en)
French (fr)
Inventor
陈焱沁
钟乃早
陈东
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华为技术有限公司
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Publication of WO2024087695A1 publication Critical patent/WO2024087695A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/26—Measuring noise figure; Measuring signal-to-noise ratio
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Definitions

  • the present application relates to the field of integrated circuit technology, and in particular to a power supply noise detection circuit and working method, a jitter limiting circuit, and an electronic device.
  • the embodiments of the present application provide a power supply noise detection circuit and working method, a jitter limiting circuit, and an electronic device for detecting clock jitter caused by power supply noise.
  • a power supply noise detection circuit for detecting the influence of power supply noise on the signal phase.
  • the power supply noise detection circuit includes a first data generation link, a sampling comparison circuit and a logic processor.
  • the first data generation link is coupled to the clock signal end, and is used to work under the noise power supply voltage, process the clock signal of the clock signal end, and output the noise signal.
  • the first data generation link is also used to work under the noise reduction power supply voltage, process the clock signal of the clock signal end, and output the noise reduction signal.
  • the sampling comparison circuit is coupled to the first data generation link, and is used to sample and compare the phase of the noise signal output by the first data generation link and the phase of the noise reduction signal.
  • the logic processor is coupled to the sampling comparison circuit, and the logic processor is used to perform logic processing on the sampling comparison result of the sampling comparison circuit, and output the processing result.
  • the power supply noise detection circuit provided by the embodiment of the present application, the first data generation link operates under the noise power supply voltage, and the generated signal is a noise signal interfered by the power supply noise.
  • the first data generation link operates under the noise reduction power supply voltage, and the generated signal is a noise reduction signal that is not interfered by the power supply noise, and the noise reduction signal is used as a reference signal.
  • the sampling comparison circuit compares the phase of the signal (noise signal and noise reduction signal) generated by the first data generation link, and outputs the comparison result after processing by the logic processor, so that the influence of the power supply noise on the phase of the clock signal can be quantified, and the phase fluctuation caused by the power supply noise can be detected as a phase advance or a phase lag.
  • the power supply noise detection circuit does not include structures such as off-chip capacitors and magnetic beads, so the hardware cost of the power supply noise detection circuit is relatively low. Moreover, the power supply noise detection circuit quantifies the power supply noise by a mixed method of analog circuit (first data generation link) and digital circuit (sampling comparison circuit, logic processor), and the signal of the digital process has only two signals of "0" and "1", and there is no intermediate fluctuation. Therefore, the process sensitivity of the power supply noise detection circuit is low, the process interference (PVT) is small, and the performance is stable. Furthermore, the noise reduction power supply voltage only needs to supply power to a first data generation link, and the power consumption of the first data generation link is less than the power consumption of the actual data generation link.
  • the power consumption and area of the power supply noise detection circuit are much smaller than the mature technical solution of placing all data generation links in the source drive circuit under the power supply denoising branch.
  • the power supply noise detection circuit provided in the embodiment of the present application can quantify the impact of power supply noise on phase under the premise of meeting low cost, low power consumption, and low process sensitivity.
  • the power supply noise detection circuit further includes a power supply noise reduction branch; the power supply voltage terminal and the first data generation link are both coupled to the power supply noise reduction branch, the power supply noise reduction branch is used to remove power supply noise in the noise power supply voltage, and input the noise reduction power supply voltage to the first data generation link.
  • the noise reduction power supply voltage is generated by the power supply noise reduction branch, and the noise reduction power supply voltage only needs to supply power to one first data generation link, and the power consumption is relatively small.
  • the first data generation link is used to operate at a noise reduction power supply voltage to output a first noise reduction signal and the second noise reduction signal;
  • the phase of the noise signal is the noise phase
  • the phase of the first noise reduction signal is the first leading phase
  • the phase of the second noise reduction signal is the first lagging phase;
  • the first leading phase and the first lagging phase are both M delay units away from the noise phase;
  • M is a positive integer.
  • the first data generation link includes a noise link and a noise reduction link; the noise link is used to work under the noise power supply voltage and output a noise signal; the noise reduction link is used to work under the noise reduction power supply voltage and output a first noise reduction signal and a second noise reduction signal.
  • the sampling and comparison circuit includes a first sampling comparator and a second sampling comparator; the noise link and the noise reduction link are both coupled to the first sampling comparator, and the first sampling comparator is used to sample and compare the noise phase of the noise signal and the first leading phase of the first noise reduction signal; the noise link and the noise reduction link are both coupled to the second sampling comparator, and the second sampling comparator is used to sample and compare the noise phase and the first lagging phase of the second noise reduction signal.
  • the logic processor has a first signal output terminal and a second signal output terminal, the first sampling comparator and the second sampling comparator are both coupled to the logic processor, the logic processor performs logic processing on the sampling comparison result of the first sampling comparator and the sampling comparison result of the second sampling comparator, and outputs the comparison result from the first signal output terminal and the second signal terminal.
  • the power supply noise reduction branch includes at least one of a low voltage dropout linear regulator, a power generator, or a filter. This is an implementation with a simple structure.
  • the noise link includes at least one first delay unit
  • the noise reduction link includes a plurality of second delay units connected in series
  • 2M second delay units are provided between the output end of the first noise reduction signal and the output end of the second noise reduction signal.
  • the noise reduction link is also used to work under the noise reduction power supply voltage and output a third noise reduction signal and a fourth noise reduction signal;
  • the phase of the third noise reduction signal is the second leading phase
  • the phase of the fourth noise reduction signal is the second lagging phase;
  • the second leading phase and the second lagging phase are both N delay units away from the noise phase;
  • N is a positive integer, N ⁇ M.
  • N ⁇ M on the basis of detecting that the jitter amplitude is ahead of or behind M delay units, it is also possible to detect whether the jitter amplitude is ahead of or behind N delay units.
  • the sampling and comparison circuit further includes a third sampling comparator and a fourth sampling comparator; the noise link, the third noise reduction link, and the logic processor are coupled to the third sampling comparator and the fourth sampling comparator respectively; the third sampling comparator is used to sample and compare the noise phase and the second leading phase; the fourth sampling comparator is used to sample and compare the noise phase and the second lagging phase.
  • the third sampling comparator and the fourth sampling comparator in the power supply noise detection circuit, the first sampling comparator and the second sampling comparator 32 detect the jitter of the phase ahead or behind the jitter of M delay units, and the third sampling comparator and the fourth sampling comparator can detect the jitter of the phase ahead or behind the jitter of N delay units, N ⁇ M. It is equivalent to comparing the noise phase with multiple leading or lagging reference phases, and different jitter amplitudes can be used as detection scales to improve the accuracy of phase jitter detection.
  • the logic processor has a third signal output terminal and a fourth signal output terminal; the third sampling comparator and the fourth sampling comparator are both coupled to the logic processor, and the logic processor performs logic processing on the sampling comparison result of the third sampling comparator and the sampling comparison result of the fourth sampling comparator, and outputs the comparison result from the third signal output terminal and the fourth signal terminal.
  • a jitter limiting circuit comprising a power supply noise detection circuit, a first jitter compensation circuit and a second data generation link;
  • the power supply noise detection circuit comprises the power supply noise detection circuit of any one of the first aspects;
  • the first jitter compensation circuit is coupled between a clock data signal terminal and the second data generation link;
  • the first jitter compensation circuit is also coupled to the power supply noise detection circuit, and is used to reversely compensate the phase of the data at the clock data signal terminal according to the output of the power supply noise detection circuit.
  • the jitter limiting circuit provided in the second aspect of the embodiment of the present application includes the power supply noise detection circuit in the first aspect, which has the beneficial effect of The beneficial effects are the same as those of the power supply noise detection circuit and will not be described in detail here.
  • the first jitter compensation circuit includes a third delay unit and a fourth delay unit connected in series, a first capacitor, a first switch, a second capacitor, and a second switch; the input end of the third delay unit is coupled to the clock data signal end, and the output end of the fourth delay unit is coupled to the second data generation link; there is a first node between the third delay unit and the fourth delay unit; the first capacitor and the first switch are coupled in series between the first node and the reference ground voltage end, and the second capacitor and the second switch are coupled in series between the first node and the reference ground voltage end; the control end of the first switch is coupled to the first signal output end, and the second switch is used to receive the reverse signal of the second signal output end.
  • the power supply noise detection circuit includes a third sampling comparator and a fourth sampling comparator;
  • the jitter limiting circuit also includes a second jitter compensation circuit, the second jitter compensation circuit is connected in series with the first jitter compensation circuit, and the second jitter compensation circuit is also coupled to the power supply noise detection circuit, and is used to reversely compensate the phase of the data output by the first jitter compensation circuit according to the output of the sampling comparison results of the third sampling comparator and the fourth sampling comparator by the logic processor.
  • the leading phase and the lagging phase are expanded into multiple delay units, and the delay modification signal will also be expanded into multiple.
  • multiple jitter compensation circuits are set in the jitter limiting circuit, and multiple delay modification signals control multiple jitter compensation circuits, which can expand the jitter optimization amplitude.
  • the jitter limiting circuit includes a plurality of second data generating links connected in parallel. This is a possible application.
  • an electronic device comprising the jitter limiting circuit and a circuit board according to any one of the second aspects, wherein the jitter limiting circuit is coupled to the circuit board.
  • the electronic device provided in the embodiment of the present application includes the jitter limiting circuit of the second aspect, and its beneficial effects are the same as those of the jitter limiting circuit, which will not be repeated here.
  • a working method of a power supply noise detection circuit including: a first data generating link operates at a noise power supply voltage and outputs a noise signal; the first data generating link also operates at a noise reduction power supply voltage and outputs a noise reduction signal; a sampling and comparison circuit samples and compares the phase of the noise signal output by the first data generating link and the phase of the noise reduction signal; a logic processor performs logic processing on the sampling and comparison results of the sampling and comparison circuit and outputs the processing results.
  • the working method of the power supply noise detection circuit provided in the fourth aspect of the embodiment of the present application has the same beneficial effects as the beneficial effects of the power supply noise detection circuit, which will not be repeated here.
  • FIG1A is a schematic diagram of a framework of an electronic device provided in an embodiment of the present application.
  • FIG1B is a schematic diagram of the layout of an electronic device provided in an embodiment of the present application.
  • FIG1C is a schematic diagram of a source driving circuit according to an embodiment of the present application.
  • FIG2A is a schematic diagram of a jitter cancellation solution according to an embodiment of the present application.
  • FIG2B is a schematic diagram of another jitter cancellation solution according to an embodiment of the present application.
  • FIG3A is a schematic diagram of a power supply noise detection circuit according to an embodiment of the present application.
  • FIG3B is a schematic diagram of a framework of another power supply noise detection circuit provided in an embodiment of the present application.
  • FIG4A is a schematic diagram of a framework of another power supply noise detection circuit provided in an embodiment of the present application.
  • FIG4B is a schematic diagram of the structure of a noise link and a noise reduction link provided in an embodiment of the present application;
  • FIGS. 5A-5C are schematic diagrams of phase contrast provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of a framework of another power supply noise detection circuit provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of another noise link and noise reduction link provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of a framework of a jitter limiting circuit provided in an embodiment of the present application.
  • FIG9 is a schematic structural diagram of a first jitter compensation circuit provided in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a framework of another jitter limiting circuit provided in an embodiment of the present application.
  • directional terms such as “up”, “down”, “left” and “right” may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • coupled can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • contact can be a direct contact or an indirect contact through an intermediate medium.
  • a and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • Power supply noise generally refers to the voltage fluctuation on the power supply voltage that changes over time.
  • Phase jitter Different voltages will produce different delays on the same clock path. Ultimately, different delays will cause different phases in the output, which is called phase jitter.
  • Phase It can be understood that there is an ideal clock with the same frequency as the target clock.
  • the ratio of the difference between the arrival time of the rising edge of the target clock and the arrival time of the rising edge of the ideal clock to the entire period multiplied by 2 ⁇ is called the phase difference. If the arrival time of the ideal clock is set to 0 (because it is an ideal clock, so the arrival time of its rising edge is always a fixed integer multiple of the period), then the phase difference is the value of the phase.
  • Jitter In clock and data links, it generally refers to the change of output phase over time.
  • Buffer A logic circuit whose output is equal to its input, mainly used to enhance driving capability.
  • Ferrite bead An off-chip device with properties similar to an inductor.
  • LDO Low dropout regulator
  • Link refers to a combinational logic path. Generally, jitter-sensitive links are composed of buffers.
  • the inverter in analog circuits, the inverter can be used as an amplifier.
  • Gate-source voltage difference (voltage between Gate and Source, VGS): The voltage difference between the gate and source of a transistor. For a transistor, the gate-source voltage difference determines its driving current.
  • Threshold voltage The threshold voltage of general digital logic means that the input voltage is judged as low when it is less than this threshold voltage, and it is judged as high when it is higher than this voltage. Therefore, the threshold voltage determines the time when the input rising and falling edges are sensed by the subsequent circuit. For the rising edge, the higher the threshold voltage, the later the rising edge is equivalent to, and for the falling edge, the lower the threshold voltage, the later the falling edge is equivalent to.
  • Transconductance refers to the derivative of the transistor output current with respect to the input gate-source voltage difference VGS.
  • Mismatch refers to the mismatch problem introduced by the transistor manufacturing process. Generally speaking, for an inverter, the slower the output edge, the more serious the output phase change caused by the mismatch.
  • Sampling comparator Its behavior is roughly to compare the input signal with 0 when the rising edge of the input clock arrives. If the input is greater than 0, the output is a high level, and if the input is less than 0, the output is a low level.
  • the electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, an electronic device for video transmission, etc.
  • consumer electronic products are, for example, mobile phones, tablet computers (pads), laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products are, for example, smart door locks, televisions, remote controls, etc. Controllers, refrigerators, rechargeable small household appliances (such as soybean milk machines, sweeping robots), etc.
  • Car-mounted electronic products such as car navigation systems, car high-density digital video discs (DVDs), etc.
  • Financial terminal products such as automated teller machines (ATMs) and self-service terminals.
  • Video transmission electronic devices such as network video recorders (NVRs), digital video recorders (DVRs), digital hard disk recorders (XVRs), encoders (DVS), all-in-one machines, industrial computers, gateways, industry hosts and other back-end products.
  • Electronic devices can also be set-top boxes and other electronic devices with audio/video transmission requirements.
  • the electronic device is taken as a tablet computer as an example.
  • the electronic device 1 mainly includes a cover plate 11, a display panel 12, a middle frame 13 and a rear shell 14.
  • the rear shell 14 and the display panel 12 are respectively located on both sides of the middle frame 13, and the middle frame 13 and the display panel 12 are arranged in the rear shell 14, the cover plate 11 is arranged on the side of the display panel 12 away from the middle frame 13, and the display surface of the display panel 12 faces the cover plate 11.
  • the display panel 12 may be a liquid crystal display (LCD).
  • the liquid crystal display includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is arranged between the cover plate 11 and the backlight module.
  • the backlight module is used to provide a light source for the liquid crystal display panel.
  • the display panel 12 may also be an organic light emitting diode (OLED) display. Since the OLED display is a self-luminous display, there is no need to set a backlight module.
  • OLED organic light emitting diode
  • the middle frame 13 includes a carrier plate 131 and a frame 132 surrounding the carrier plate 131.
  • the electronic device 1 may also include electronic components such as printed circuit boards (PCB), batteries, and cameras, and the printed circuit boards, batteries, and cameras may be arranged on the carrier plate 131.
  • PCB printed circuit boards
  • the display panel 12 includes an active display area (AA) A and a peripheral area B located around the active display area A.
  • the effective display area A of the display panel 12 serves as the display area of the electronic device 1
  • the peripheral area B of the display panel 12 serves as the non-display area of the electronic device 1 .
  • the effective display area A of the display panel 12 includes a plurality of sub-pixels P.
  • the plurality of sub-pixels P are described in the present application by taking a matrix arrangement as an example.
  • the sub-pixels P arranged in a row along the horizontal direction are called sub-pixels in the same row
  • the sub-pixels P arranged in a row along the vertical direction are called sub-pixels in the same column.
  • the electronic device 1 includes a gate driving circuit and a source driving circuit located in the peripheral area B of the display panel 12.
  • the gate driving circuit is used to provide a gate driving signal for the sub-pixel P
  • the source driving circuit is used to provide a source driving signal for the sub-pixel P.
  • the gate driving circuit can be integrated in the display panel 12 using a gate on array (GOA) technology.
  • the gate driving circuit includes a plurality of cascaded shift registers (SR).
  • the gate driving circuit may include one or more gate driving circuits.
  • the electronic device 1 includes two gate driving circuits, and the two gate driving circuits are arranged on both sides of the effective display area A along the horizontal direction.
  • the source driver circuit can be integrated into a driver chip (display driver integrated circuit, DDIC), for example.
  • DDIC display driver integrated circuit
  • the driver chip DDIC is directly attached to the display panel 12 in the form of a bare chip (die).
  • the electronic device also includes a timing controller (TCON), which, in some embodiments, as shown in FIG. 1B , is disposed on a flexible printed circuit (FPC).
  • TCON timing controller
  • FPC flexible printed circuit
  • the source driving circuit includes a receiving circuit and a data output circuit.
  • the receiving circuit may receive the transmission signal TD provided from the timing controller TCON shown in FIG1B, and may restore the data signal DT and the clock signal CK.
  • the data output circuit may convert the data signal DT outputted by the receiving circuit and the clock signal CK into a data driving signal D, and apply the data driving signal D to the sub-pixel P shown in FIG. 1B .
  • the data output circuit includes a data generation link.
  • the data generation link is easily interfered by power supply noise during the process of outputting the data driving signal, resulting in phase jitter in the output data driving signal D.
  • off-chip capacitors and magnetic beads are used for noise filtering to suppress the influence of power supply noise.
  • a low dropout regulator LDO is used to generate a power supply with less noise through a higher input voltage to power the data generation link, so as to suppress the influence of power supply noise.
  • the power supply voltage of the data generation link is 0.9V.
  • the input voltage of 1.8V is used to generate a 0.9V low-noise voltage through the low-dropout regulator LDO and then supply the data generation link.
  • the original power consumption is 0.9*I. After switching to the low-dropout regulator LDO power supply, the power consumption becomes 1.8*I, which is doubled.
  • LDO low dropout regulator
  • a clock jitter limiting circuit which uses transistors P1 and N1 and transistors P2 and N2 to form two groups of inverting amplifiers, resistors R1 and R2 respectively give static bias to transistors P1 and N1, and resistors R3 and R4 respectively give static bias to transistors P2 and N2, so that transistors P1, P2, N1, and N2 operate in a saturation region.
  • the power noise of the negative power supply voltage terminal VSS is coupled to the gate terminals of transistors P1 and N1 through capacitor C1, and is amplified by the inverting amplifier and coupled to the gate terminal CTRLP of transistor P3 through capacitor C3.
  • the power noise of the positive power supply voltage terminal VDD is coupled to the gate terminals of transistors P2 and N2 through capacitor C2, and is amplified by the inverting amplifier and coupled to the gate terminal CTRLN of transistor N4 through capacitor C4.
  • Resistors R5, R6 and R7 provide static bias for transistors P3 and N4, so that transistors P3 and N4 may work in the saturation region.
  • the input signal is fed into the data generation link, and is output from the output terminal after passing through transistors P4 and N3.
  • Transistors P4 and N3 are essentially inverters whose current is limited by transistors P3 and N4.
  • power supply noise changes the driving capability of the transistor, causing the delay to change, and then causing output phase jitter.
  • the power supply noise is amplified to the gate terminal CTRLP of transistor P3 and the gate terminal CTRLN of transistor N4 through an inverting amplifier, and then the influence of the power supply noise is offset by transistors P3 and N4.
  • the driving capability of the data generation link will be enhanced and the delay will be reduced.
  • the voltage of the gate terminal CTRLP of the transistor P3 will increase, and the voltage of the gate terminal CTRLN of the transistor N4 will decrease, so the gate-source voltage difference VGS of the transistor P3 will decrease, and the gate-source voltage difference VGS of the transistor N4 will also decrease.
  • the driving capability of the data generation link is enhanced, and the driving of the transistor P3 and the transistor N4 is weakened, thereby offsetting the influence of the power supply noise.
  • the offset gain Gain of the above technology on power supply noise is as follows (only considering the rising edge):
  • t out represents the delay of the inverter composed of transistors P3, P4, N3 and N4; V th represents the flip threshold voltage of the next stage circuit; K represents the ratio of t out to the flip voltage threshold of the next stage.
  • I CH is the charging current output by the inverter pair composed of transistor P3, transistor P4, transistor N3, and transistor N4;
  • C is the output capacitance;
  • G INV is the gain of the two inverting amplifiers composed of transistor P1, transistor N1, transistor P2, and transistor N2;
  • G AC is the AC coupling gain composed of capacitor C1, capacitor C2, capacitor C3, and capacitor C4;
  • gm is the transconductance of transistor P3 and transistor N4.
  • G INV and gm will change dramatically with PVT (pressure, voltage, temperature), which means that the modulation effect of the above technology is very unstable. Due to the high process sensitivity, there will be a large difference between different chips, and it may even happen that the jitter is amplified due to excessive adjustment gain.
  • the embodiment of the present application provides a power supply noise detection circuit for detecting power supply noise, so as to eliminate the phase jitter caused by the power supply noise to the data generation link according to the power supply noise detection structure.
  • the power supply noise detection circuit provided in the embodiment of the present application can be applied not only to the jitter limiting circuit, but also to any circuit that needs to detect power supply noise.
  • the power noise detection circuit includes a first data generation link 20 , a sampling comparison circuit 30 , and a logic processor 40 .
  • the first data generation link 20 is coupled to the clock signal terminal CK, and is used to work at a noise power supply voltage and output a noise signal.
  • the first data generation link 20 is also used to work at a noise reduction power supply voltage and output a noise reduction signal.
  • the first data generation link 20 operates under the noise power supply voltage, and the output signal is a noise signal interfered by the power supply noise in the power supply voltage. Since there is no or almost no power supply noise in the noise reduction power supply voltage, the first data generation link 20 operates under the noise reduction power supply voltage, and the output signal is a noise reduction signal that is not interfered by the power supply noise in the power supply voltage.
  • the noise reduction signal is used as a reference signal, and the noise signal and the noise reduction signal have the same frequency and different phases.
  • the first data generation link 20 is used to work at a noise power supply voltage to output a noise signal, and the first data generation link 20 is also used to work at a noise reduction power supply voltage to output a first noise reduction signal and a second noise reduction signal.
  • the phase of the noise signal is the noise phase p
  • the phase of the first noise reduction signal is the first leading phase p1
  • the phase of the second noise reduction signal is the first lagging phase p2.
  • the first leading phase p1 and the first lagging phase p2 are both M delay units away from the noise phase p, and the delay of each delay unit has a delay time (tdel); M is a positive integer.
  • the sampling and comparison circuit 30 is coupled to the first data generation link 20 and is used to perform sampling and comparison on the phase of the signal output by the first data generation link 20 .
  • the sampling and comparison circuit 30 is used to sample and compare the phase of the noise signal and the phase of the noise reduction signal output by the first data generation link 20. In some embodiments, the sampling and comparison circuit 30 is used to sample and compare the noise phase p of the noise signal and the first leading phase p1 of the first noise reduction signal, and to sample and compare the noise phase p and the first lagging phase p2 of the second noise reduction signal.
  • the logic processor 40 is coupled to the sampling and comparing circuit 30.
  • the logic processor 40 is used to perform logic processing on the sampling and comparing result of the sampling and comparing circuit 30 and output the processing result.
  • the processing result includes a first signal, a second signal, and a third signal.
  • the first signal indicates that the power supply noise in the noise power supply voltage causes the phase of the clock signal at the clock signal end to advance
  • the second signal indicates that the power supply noise in the noise power supply voltage causes the phase of the clock signal at the clock signal end to lag
  • the third signal indicates that the jitter of the phase of the clock signal at the clock signal end caused by the power supply noise in the noise power supply voltage is within an acceptable range.
  • the power supply noise detection circuit further includes a power supply noise elimination branch 50 .
  • the power supply voltage terminal AVDDL and the first data generation link 20 are both coupled to a power supply noise reduction branch 50 .
  • the power supply noise reduction branch 50 is used to remove power supply noise from the noise power supply voltage and input the noise reduction power supply voltage to the first data generation link 20 .
  • the first data generation link 20 operates under the noise power supply voltage, and the generated signal is a noise signal interfered by the power supply noise.
  • the first data generation link 20 operates under the noise reduction power supply voltage, and the generated signal is a noise reduction signal that is not interfered by the power supply noise, and the noise reduction signal is used as a reference signal.
  • the sampling comparison circuit 30 compares the phases of the signals (noise signal and noise reduction signal) generated by the first data generation link 20, and outputs the comparison results after being processed by the logic processor 40, so as to quantify the influence of the power supply noise on the phase of the clock signal, and detect whether the phase fluctuation caused by the power supply noise is phase advance or phase lag.
  • the power supply noise detection circuit provided in the embodiment of the present application does not include structures such as off-chip capacitors and magnetic beads, so the hardware cost of the power supply noise detection circuit is relatively low.
  • the power supply noise detection circuit quantifies the power supply noise by using a mixed method of analog circuits (first data generation link 20) and digital circuits (sampling comparison circuit 30, logic processor 40).
  • the digital process signal only has two types of signals, "0" and "1", and there is no intermediate fluctuation. Therefore, the power supply noise detection circuit has low process sensitivity, is less affected by process interference (PVT), and has stable performance.
  • the power supply denoising branch 50 only needs to supply power to a first data generation link 20, and the power consumption of the first data generation link 20 is less than the power consumption of the data generation link in the source driver circuit in Figure 1C. Therefore, the power consumption and area of the power noise detection circuit are much smaller than the mature technical solution of placing all data generation links in the source driver circuit under the power noise removal branch 50.
  • the power noise detection circuit provided in the embodiment of the present application can quantify the influence of power noise on the phase under the premise of meeting low cost, low power consumption and low process sensitivity.
  • the power supply noise detection circuit includes a first data generation link 20 , a sampling comparison circuit 30 , a logic processor 40 , and a power supply noise removal branch 50 .
  • the first data generation link 20 includes a noise link 21 and a noise reduction link 22 in parallel, and the sampling comparison circuit 30 includes a first sampling comparator 31 and a second sampling comparator 32 .
  • the power supply noise reduction branch 50 is coupled to the power supply voltage terminal AVDDL, and is used to remove noise from the noise power supply voltage of the power supply voltage terminal AVDDL, and output a noise-reduced power supply voltage.
  • the power supply noise reduction branch 50 may include at least one of a low voltage dropout linear regulator, a power generator, or a filter.
  • the noise power supply voltage outputted from the power supply voltage terminal AVDDL passes through the power supply noise removal branch 50, it is equivalent to filtering out the power supply noise in the noise power supply voltage.
  • the noise link 21 is coupled to the clock signal terminal CK and the power supply voltage terminal AVDDL, and is configured to operate under the noise power supply voltage of the power supply voltage terminal AVDDL and output a noise signal.
  • the clock signal terminal CK is used as the clock input of the noise link 21.
  • the noise link 21 directly works under the noise power supply voltage.
  • the power supply noise will affect the noise link 21.
  • the noise link 21 outputs a noise signal affected by the power supply noise.
  • the phase of the noise signal is called the noise phase p.
  • the noise reduction link 22 is coupled to the clock signal terminal CK and the power noise reduction branch 50, and is used to work under the noise reduction power supply voltage output by the power noise reduction branch 50, and output a first noise reduction signal and a second noise reduction signal, and the first noise reduction signal and the second noise reduction signal have different phases.
  • the phase of the noise signal is the noise phase p
  • the phase of the first noise reduction signal is the first leading phase p1
  • the phase of the second noise reduction signal is the first lagging phase p2.
  • the first leading phase p1 and the first lagging phase p2 are both M delay units away from the noise phase p; M is a positive integer.
  • the clock signal terminal CK serves as the clock input of the noise reduction link 22.
  • the noise reduction link 22 directly operates under the noise reduction power supply voltage.
  • the power supply noise has almost no effect on the noise reduction link 22.
  • the noise reduction link 22 outputs the first noise reduction signal and the second noise reduction signal that are not affected by the power supply noise.
  • the first noise reduction signal and the second noise reduction signal can be used as reference clock signals, and the phases of the first noise reduction signal and the second noise reduction signal are used as reference phases.
  • the noise phase p By comparing the first leading phase p1 and the first lagging phase p2 with the noise phase p, it can be determined whether the noise phase p is ahead of the first leading phase p1 or is behind the first lagging phase p2, so as to detect the phase jitter caused by the power supply noise.
  • M 1.
  • the first lagging phase P2 and the first leading phase P1 are both separated from the noise phase by one delay unit, and the first lagging phase P2 and the first leading phase P1 are separated by two delay units.
  • the detection amplitude of the phase jitter can be adjusted, thereby determining the adjustment step of the phase jitter.
  • M the smaller the adjustment step of the phase jitter is, and the lower the tolerance to the phase jitter is. Therefore, the size of M can be adjusted according to different tolerances to phase jitter in different application scenarios.
  • the noise link 21 includes at least one first delay unit 211
  • the noise reduction link 22 includes a plurality of second delay units 221 connected in series, and the number of the second delay units 221 is M more than the number of the first delay units 211.
  • the noise chain 21 includes a plurality of first delay units 211
  • the plurality of first delay units 211 are connected in series.
  • the first stage of the first delay unit 211 is coupled to the clock signal terminal CK and the power supply voltage terminal AVDDL
  • the remaining first delay units 211 are coupled to the power supply voltage terminal AVDDL
  • the output terminal of the last stage of the first delay unit 211 outputs the noise signal.
  • the first-stage second delay unit 221 is coupled to the clock signal terminal CK and the power supply noise reduction branch 50 , and the remaining second delay units 221 are coupled to the power supply noise reduction branch 50 .
  • the first delay unit 211 may be, for example, a buffer
  • the second delay unit 221 may be, for example, a buffer.
  • the output end of the noise link 21 is used as the output end P of the noise phase, and the noise reduction link 22 has a first noise reduction signal.
  • the output terminal P1 and the output terminal P2 of the second noise reduction signal are ahead of the output terminal of the noise link 21 by M second delay units 221, and the output terminal P2 of the second noise reduction signal is behind the output terminal of the noise link 21 by M second delay units 221.
  • the output terminal of the noise reduction link 22 serves as the output terminal P2 of the second noise reduction signal.
  • any first data link 20 capable of generating the first noise reduction signal and the second noise reduction signal is applicable to the embodiment of the present application, and the structure in FIG. 4B is only an illustration.
  • the noise link 21 and the noise reduction link 22 are respectively coupled to the first sampling comparator 31 , for example, the first sampling comparator 31 is coupled to the output terminal P of the noise phase of the noise link 21 and the output terminal P1 of the first noise reduction signal of the noise reduction link 22 .
  • the first sampling comparator 31 is used for sampling and comparing the noise phase p of the noise signal and the first leading phase P1 of the noise reduction signal, and outputting the comparison result.
  • the noise link 21 and the noise reduction link 22 are respectively coupled to the second sampling comparator 32 .
  • the second sampling comparator 32 is coupled to the output terminal P of the noise phase of the noise link 21 and the output terminal P2 of the second noise reduction signal of the noise reduction link 22 .
  • the second sampling comparator 32 is used to sample and compare the noise phase p of the noise signal output by the noise link 21 and the first lag phase P2 of the noise reduction signal output by the noise reduction link 22, and output the comparison result.
  • the first sampling comparator 31 is configured to output the second digital signal when the noise phase p leads the first leading phase P1 , and output the first digital signal when the noise phase p does not lead the first leading phase P1 .
  • the second sampling comparator 32 is used for outputting a first digital signal when the noise phase p lags behind the first lag phase P2 , and outputting a second digital signal when the noise phase p does not lag behind the first lag phase P2 .
  • the first digital signal and the second digital signal are 0 and 1, respectively.
  • the first digital signal is 1 and the second digital signal is 0.
  • sampling and comparison can be performed at the rising edge of the noise phase p, the first lagging phase P2 and the first leading phase P1, or sampling and comparison can be performed at the falling edge of the noise phase p, the first lagging phase P2 and the first leading phase P1, or differential sampling and comparison can be performed on the noise phase p, the first lagging phase P2 and the first leading phase P1.
  • any method of sampling and comparing the noise phase p, the first lagging phase P2 and the first leading phase P1 in the related art can be applied to the embodiments of the present application.
  • the second digital signal is outputted. If the noise signal is greater than the threshold (for example, the threshold is half of the noise power supply voltage), the first digital signal is outputted.
  • the second digital signal is output, and if the noise signal is greater than the threshold, the first digital signal is output.
  • the output terminals of the first sampling comparator 31 and the second sampling comparator 32 are respectively coupled to the logic processor 40 .
  • the logic processor 40 is used for outputting the first signal and the second signal according to the sampling comparison results of the first sampling comparator 31 and the second sampling comparator 32 .
  • the first signal indicates that the power supply noise in the noise power supply voltage causes the phase of the clock signal at the clock signal terminal CK to advance
  • the second signal indicates that the power supply noise in the noise power supply voltage causes the phase of the clock signal at the clock signal terminal CK to lag.
  • the logic processor 40 has a first signal output terminal O1 and a second signal output terminal O2 .
  • the logic processor 40 is used to output the first digital signal as the first signal from the first signal output terminal O1 and output the second digital signal from the second signal output terminal when the first sampling comparator 31 outputs the first digital signal and the second sampling comparator 32 outputs the first digital signal.
  • the first sampling comparator 31 outputs the first digital signal.
  • the second sampling comparator 32 outputs the first digital signal, the first digital signal is output from the first signal output terminal O1 and the second digital signal is output from the second signal output terminal O2 as the first signal.
  • the first sampling comparator 31 When the first sampling comparator 31 outputs the second digital signal and the second sampling comparator 32 outputs the second digital signal,
  • the second digital signal is output from the first signal output terminal O1
  • the first digital signal is output from the second signal output terminal O2 as the second signal.
  • the logic processor 40 outputs a judgment result of whether the power supply noise causes the phase of the clock signal to advance (up), lag (down) or hold (hold) according to the sampling results of the first sampling comparator 31 and the second sampling comparator 32 .
  • the noise link 21 when a large positive ripple appears at the power supply voltage terminal AVDDL, the noise link 21 is affected, and the noise phase P becomes advanced due to the reduced delay caused by the voltage increase.
  • the noise reduction link 22 operates at the noise reduction power supply voltage, so the first leading phase P1 and the first lagging phase P2 are not affected.
  • the first sampling comparator 31 compares the noise phase P with the first leading phase P1. At the rising edge of the first leading phase P1, the noise signal is greater than the threshold, and the first sampling comparator 31 outputs the first digital signal.
  • the second sampling comparator 32 compares the noise phase P with the first lagging phase P2. At the rising edge of the first lagging phase P2, the noise signal is greater than the threshold, and the second sampling comparator 32 outputs the first digital signal. Then, the first sampling comparator 31 outputs the first digital signal, the second sampling comparator 32 outputs the first digital signal, the logic processor 40 outputs the first digital signal from the first signal output terminal O1, and the logic processor 40 outputs the second digital signal from the second signal output terminal O2.
  • a first signal that characterizes that the power supply noise in the noise power supply voltage causes the phase of the clock signal at the clock signal end to advance.
  • the output of the power supply noise detection circuit is that the first signal output terminal O1 outputs the first digital signal, and the second signal output terminal O2 outputs the second digital signal.
  • the noise link 21 when a large negative ripple appears at the power supply voltage terminal AVDDL, the noise link 21 is affected, and the noise phase P becomes delayed due to the increased delay caused by the voltage reduction.
  • the noise reduction link 22 operates at the noise reduction power supply voltage, so the first leading phase P1 and the first lagging phase P2 are not affected.
  • the first sampling comparator 31 compares the noise phase P with the first leading phase P1. At the rising edge of the first leading phase P1, the noise signal is less than the threshold, and the first sampling comparator 31 outputs the second digital signal.
  • the second sampling comparator 32 compares the noise phase P with the first lagging phase P2. At the rising edge of the first lagging phase P2, the noise signal is less than the threshold (half of the noise power supply voltage), and the second sampling comparator 32 outputs the second digital signal. Then, the first sampling comparator 31 outputs the second digital signal, the second sampling comparator 32 outputs the second digital signal, the logic processor 40 outputs the second digital signal from the first signal output terminal O1, and the logic processor 40 outputs the first digital signal from the second signal output terminal O2.
  • a second signal that characterizes the phase lag of the clock signal caused by the power supply noise in the noise power supply voltage.
  • the output of the power supply noise detection circuit is that the first signal output terminal O1 outputs the second digital signal, and the second signal output terminal O2 outputs the first digital signal.
  • the noise reduction link 22 operates under the noise reduction power supply voltage, so the first leading phase P1 and the first lagging phase P2 are not affected.
  • the first sampling comparator 31 compares the noise phase P with the first leading phase P1. At the rising edge of the first leading phase P1, the noise signal is less than the threshold, and the first sampling comparator 31 outputs the second digital signal.
  • the second sampling comparator 32 compares the noise phase P with the first lagging phase P2. At the rising edge of the first lagging phase P2, the noise signal is greater than the threshold, and the second sampling comparator 32 outputs the first digital signal. Then, the first sampling comparator 31 outputs the second digital signal, the second sampling comparator 32 outputs the first digital signal, and the logic processor 40 outputs the second digital signal from the first signal output terminal O1 and the second digital signal from the second signal output terminal O2.
  • the output of the power supply noise detection circuit is that the first signal output terminal O1 outputs the second digital signal, and the second signal output terminal O2 outputs the second digital signal.
  • the noise detection circuit outputs the third signal, and the third signal indicates that the phase jitter of the clock signal at the clock signal terminal CK caused by the power supply noise in the noise power supply voltage is within the tolerance range.
  • the power supply noise detection circuit provided in the embodiment of the present application generates a noise link 21 by operating it at a noise power supply voltage.
  • Noise phase p The noise reduction link 22 operates under the noise reduction power supply voltage, generates a reference phase, and takes the first leading phase P1 of the M delay units lagging behind the noise phase p and the first lagging phase P2 of the M delay units leading the noise phase p as the reference phase.
  • the influence of the power supply noise on the phase is quantified, and the phase fluctuation caused by the power supply noise is detected as a phase advance or a phase lag.
  • the power supply noise detection circuit provided in the embodiment of the present application does not include structures such as off-chip capacitors and magnetic beads, the hardware cost of the power supply noise detection circuit is relatively low.
  • the power supply denoising branch 50 only needs to supply power to the noise reduction link 22, and the power consumption of the noise reduction link 22 is less than the power consumption of the data generation link in the source driving circuit. Therefore, the power consumption and area of the power supply noise detection circuit are much smaller than the mature technical solution of placing all data generation links in the source driving circuit under the power supply denoising branch 50.
  • the power supply noise detection circuit quantifies the power supply noise by a mixed method of analog circuits (noise link 21, power supply denoising branch 50, noise reduction link 22) and digital circuits (first sampling comparator 31, second sampling comparator 32, logic processor 40).
  • the digital process signal has only two signals, "0" and "1", without intermediate fluctuations. Therefore, the process sensitivity of the power supply noise detection circuit is low, the process interference (PVT) is small, and the performance is stable.
  • the power supply noise detection circuit provided in the embodiment of the present application can quantify the influence of power supply noise on phase under the premise of meeting low cost, low power consumption, and low process sensitivity.
  • the power supply noise detection circuit further includes a third sampling comparator 33 and a fourth sampling comparator 34 .
  • the noise link 21, the noise reduction link 22 and the logic processor 40 are respectively coupled to the third sampling comparator 33 and the fourth sampling comparator 34.
  • the third sampling comparator 33 is connected in parallel with the first sampling comparator 31
  • the fourth sampling comparator 34 is connected in parallel with the second sampling comparator 32.
  • the noise reduction link 22 also includes an output terminal P3 of the third noise reduction signal and an output terminal P4 of the fourth noise reduction signal.
  • the output terminal P3 of the third noise reduction signal and the output terminal P4 of the fourth noise reduction signal are both N second delay units 221 apart from the output terminal P of the noise phase, and the output terminal P3 of the third noise reduction signal and the output terminal P4 of the fourth noise reduction signal are 2N second delay units 221 apart.
  • N is a positive integer and N ⁇ M.
  • N can be greater than M or less than M.
  • the second lagging phase p4 obtained at the output end P4 of the fourth noise reduction signal and the second leading phase p3 obtained at the output end P3 of the third noise reduction signal are both N delay units away from the noise phase phase, and the second lagging phase p4 and the second leading phase p3 are 2N delay units apart.
  • the output terminal P of the noise phase of the noise link 21 and the output terminal P4 of the fourth noise reduction signal of the noise reduction link 22 are both coupled to the input terminal of the fourth sampling comparator 34 .
  • the output terminal of the fourth sampling comparator 34 is coupled to the logic processor 40 .
  • the fourth sampling comparator 34 is used to sample and compare the noise phase p of the noise signal output by the noise link 21 and the second lag phase p4 of the noise reduction signal output by the noise reduction link 22, and output the comparison result to the logic processor 40.
  • the output terminal P of the noise phase of the noise link 21 and the output terminal P3 of the third noise reduction signal of the noise reduction link 22 are both coupled to the input terminal of the third sampling comparator 62 .
  • the output terminal of the third sampling comparator 62 is coupled to the logic processor 40 .
  • the third sampling comparator 62 is used to sample and compare the noise phase p of the noise signal output by the noise link 21 and the second leading phase p3 of the noise reduction signal output by the noise reduction link 22, and output the comparison result to the logic processor 40.
  • the third sampling comparator 33 may, for example, have the same structure and principle as the first sampling comparator 31, but the sampling comparison phases of the two are different, and reference may be made to the above description of the first sampling comparator 31.
  • the fourth sampling comparator 34 may, for example, have the same structure and principle as the second sampling comparator 32, but the sampling comparison phases of the two are different, and reference may be made to the above description of the second sampling comparator 32.
  • the logic processor 40 is further configured to output a first signal and a second signal according to sampling and comparison results of the third sampling comparator 33 and the fourth sampling comparator 34 .
  • the logic processor 40 further includes a third signal output terminal O3 and a fourth signal output terminal O4. After the logic processor 40 compares the sampling results of the third sampling comparator 33 and the fourth sampling comparator 34, the comparison results are output from the third signal output terminal O3 and the fourth signal output terminal O4.
  • the comparison process of the sampling results of the third sampling comparator 33 and the fourth sampling comparator 34 by the logic processor 40 may refer to the above processing process of the sampling results of the first sampling comparator 31 and the second sampling comparator 32 by the logic processor 40 .
  • the third signal output terminal O3 outputs the second digital signal
  • the fourth signal output terminal O4 outputs the first digital signal
  • the third signal output terminal O3 outputs 1
  • the fourth signal output terminal O4 outputs 0.
  • the third signal output terminal O3 When the phase lags, the third signal output terminal O3 outputs the first digital signal, and the fourth signal output terminal O4 outputs the second digital signal. For example, the third signal output terminal O3 outputs 0, and the fourth signal output terminal O4 outputs 1.
  • the third signal output terminal O3 When the phase jitter is within the tolerance range, the third signal output terminal O3 outputs the first digital signal, and the fourth signal output terminal O4 outputs the first digital signal. For example, the third signal output terminal O3 outputs 0, and the fourth signal output terminal O4 outputs 0.
  • the logic processor 40 includes a first logic unit and a second logic unit.
  • the work of comparing the sampling results of the first sampling comparator 31 and the second sampling comparator 32 is completed by the first logic processing unit, and the work of comparing the sampling results of the third sampling comparator 33 and the fourth sampling comparator 34 in the logic processor 40 is completed by the second logic processing unit.
  • the first sampling comparator 31 and the second sampling comparator 32 are regarded as a group of sampling comparators, and the third sampling comparator 33 and the fourth sampling comparator 34 are regarded as a group of sampling comparators.
  • the power supply noise detection circuit provided in the embodiment of the present application may also include multiple groups of sampling comparators, each group of sampling comparators is used to collect different leading phases and lagging phases in the noise reduction signal.
  • the first sampling comparator 31 and the second sampling comparator 32 can detect the jitter of the phase jitter that is ahead of or behind the jitter of M delay units
  • the third sampling comparator 33 and the fourth sampling comparator 34 can detect the jitter of the phase jitter that is ahead of or behind the jitter of N delay units, N ⁇ M. It is equivalent to comparing the noise phase p with multiple leading or lagging reference phases, and different jitter amplitudes can be used as detection scales to improve the accuracy of phase jitter detection. For example, N ⁇ M, on the basis of detecting that the jitter amplitude is ahead of or behind M delay units, it is also possible to detect whether the jitter amplitude is ahead of or behind N delay units.
  • the embodiment of the present application further provides a jitter limiting circuit, and the above-mentioned power supply noise detection circuit is applied to the jitter limiting circuit provided in the embodiment of the present application.
  • the jitter limiting circuit includes a power supply noise detection circuit, a first jitter compensation circuit 81 and a second data generation link 90 .
  • the power noise detection circuit, the first jitter compensation circuit 81 and the second data generation link 90 are coupled in series.
  • the first jitter compensation circuit 81 is coupled between the power noise detection circuit and the second data generation link 90 .
  • the second data generation link 90 is, for example, the data generation link in the source driving circuit shown in FIG. 1C .
  • the first jitter compensation circuit 81 is also coupled to the clock data signal terminal C/D, and is used to reversely compensate the phase of the data of the clock data signal terminal C/D according to the output of the power supply noise detection circuit.
  • the first jitter compensation circuit 81 first lags the phase of the data at the clock data signal terminal C/D, and then transmits the data with phase lag jitter to the second data generation link 90.
  • the second data generation link 90 operates under the noise power supply voltage and performs phase advance jitter on the data.
  • the data output by the output terminal OT of the second data generation link 90 is the data after the phase lag jitter and the phase advance jitter are offset, so as to achieve the purpose of eliminating the output jitter caused by the power supply noise.
  • the first jitter compensation circuit 81 first advances the phase of the data at the clock data signal terminal C/D, and then transmits the data with phase advance jitter to the second data generation link 90.
  • the second data generation link 90 operates under the noise power supply voltage and performs phase lag jitter on the data.
  • the data output by the output terminal OT of the second data generation link 90 is the data after the phase lag jitter and the phase advance jitter are offset, so as to achieve the purpose of eliminating the output jitter caused by the power supply noise.
  • the data transmitted by the clock data signal terminal C/D may be a clock signal or a data signal, which is not limited in the embodiment of the present application.
  • the jitter limiting circuit includes a plurality of second data generating chains 90 connected in parallel.
  • multiple second data generation links 90 can be simultaneously transmitted signals.
  • the first jitter compensation circuit 81 includes a third delay unit 811 and a fourth delay unit 812 connected in series, a first capacitor C1 , a first switch SW1 , a second capacitor C2 , and a second switch SW2 .
  • the input end of the third delay unit 811 is coupled to the clock data signal end C/D
  • the output end of the fourth delay unit 812 is coupled to the second data generation link 90
  • the third delay unit 811 and the fourth delay unit 812 are also coupled to the power supply voltage end AVDDL respectively. catch.
  • first node A between the third delay unit 811 and the fourth delay unit 812, a first capacitor C1 and a first switch SW1 are coupled in series between the first node A and the reference ground voltage terminal GND, and a second capacitor C2 and a second switch SW2 are coupled in series between the first node A and the reference ground voltage terminal GND.
  • a control terminal of the first switch SW1 is coupled to the first signal output terminal O1, and the second switch SW2 is used to receive a reverse signal of the second signal output terminal O2.
  • the first switch SW1 is closed, the second switch SW2 is closed, and the load of the third delay unit 811 is the first capacitor C1+the second capacitor C2.
  • the load increases, and the phase will lag and jitter.
  • the first jitter compensation circuit 81 transmits the data with phase lag and jitter to the second data generation link 90.
  • the second data generation link 90 operates under the noise power supply voltage and performs phase advance jitter on the data.
  • the data output by the output terminal OT of the second data generation link 90 is the data after the phase lag jitter and the phase advance jitter are offset, so as to achieve the purpose of eliminating the output jitter caused by the power supply noise.
  • the first jitter compensation circuit 81 transmits the data with phase lag and lead to the second data generation link 90.
  • the second data generation link 90 operates under the noise power supply voltage and performs phase lag jitter on the data.
  • the data output by the output terminal OT of the second data generation link 90 is the data after the phase advance jitter and the phase lag jitter are offset, so as to achieve the purpose of eliminating the output jitter caused by the power supply noise.
  • the first jitter compensation circuit 81 transmits the phase-maintained data to the second data generation link 90.
  • the second data generation link 90 operates under the noise power supply voltage and performs acceptable jitter on the data.
  • the data outputted by the output terminal OT of the second data generation link 90 is still data with acceptable phase jitter.
  • the jitter limiting circuit when the power supply noise detection circuit includes the third sampling comparator 33 and the fourth sampling comparator 34 , the jitter limiting circuit further includes a second jitter compensation circuit 82 .
  • the second jitter compensation circuit 82 is connected in series with the first jitter compensation circuit 81.
  • the second jitter compensation circuit 82 is also coupled to the power supply noise detection circuit, and is used to reversely compensate the data of the clock data signal terminal C/D according to the output of the power supply noise detection circuit of the sampling comparison result of the third sampling comparator 33 and the fourth sampling comparator 34.
  • the second jitter compensation circuit 82 has the same structure and the same working principle as the first jitter compensation circuit 81 .
  • the second jitter compensation circuit 82 is coupled to the third signal output terminal O3 and the fourth signal output terminal O4.
  • the second jitter compensation circuit 82 is controlled by the signals output by the third signal output terminal O3 and the fourth signal output terminal O4 to determine whether to perform further reverse compensation on the phase of the data output by the first jitter compensation circuit 81 in advance.
  • the first jitter compensation circuit 81 and the second jitter compensation circuit 82 both perform reverse compensation, or the first jitter compensation circuit 81 performs reverse compensation and the second jitter compensation circuit 82 remains uncompensated, or both the first jitter compensation circuit 81 and the second jitter compensation circuit 82 remain uncompensated.
  • the jitter limiting circuit provided in the embodiment of the present application is not limited to including two jitter compensation circuits, but may also include more than two jitter compensation circuits, which can be reasonably configured according to needs.
  • the jitter that can be reduced by the jitter limiting circuit is the LSB.
  • the phase detection accuracy of the first jitter compensation circuit 81 is determined by the DC deviation (DC deviation, also called static deviation) of the first lagging phase P2 and the first leading phase P1 output by the noise reduction link 22 relative to the noise phase p output by the noise link 21.
  • the reference phase includes the first leading phase P1, the second leading phase p3, the first lagging phase P2 and the second lagging phase p4.
  • the first leading phase P1 and the first lagging phase P2 lag and lead the noise phase p by 1*tdel
  • the second leading phase p3 and the second lagging phase p4 lag and lead the noise phase p by 2*tdel.
  • the first jitter compensation circuit 81 reversely adjusts the delay of +-1*LSB
  • the second jitter compensation circuit 82 reversely adjusts the delay of +-2*LSB.
  • the jitter limiting circuit When the power supply noise causes the noise phase p to advance by more than 2*tdel, if the jitter limiting circuit only has the first jitter compensation circuit 81, the system can only adjust the phase change of 1*LSB, and the rest cannot be adjusted. If the jitter limiting circuit also includes the second jitter compensation circuit 82, the system can adjust the phase change of 3LSB.
  • the leading phase and the lagging phase are expanded into multiple delay units, and the delay modification signal is also expanded into multiple.
  • multiple jitter compensation circuits are set in the jitter limiting circuit, and multiple delay modification signals control multiple jitter compensation circuits, which can expand the jitter optimization range.
  • the embodiment of the present application also provides a working method of a power supply noise detection circuit, including: the first data generation link 20 operates at a noise power supply voltage and outputs a noise signal; the first data generation link 20 also operates at a noise reduction power supply voltage and outputs a noise reduction signal.
  • the sampling comparison circuit 30 performs sampling comparison on the phase of the noise signal output by the first data generation link 20 and the phase of the noise reduction signal.
  • the logic processor 40 performs logic processing on the sampling comparison result of the sampling comparison circuit 30 and outputs the processing result.

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Abstract

一种电源噪声检测电路及工作方法、抖动限幅电路、电子设备，涉及集成电路技术领域，用于以低成本、低功耗的技术手段来检测电源噪声带来的时钟抖动。电源噪声检测电路例如可以应用于抖动限幅电路中。电源噪声检测电路包括：第一数据产生链路（20），用于工作在噪声电源电压，输出噪声信号；还用于工作在降噪电源电压下，输出降噪信号；降噪信号例如包括第一降噪信号和第二降噪信号；采样比较电路（30），用于对第一数据产生链路（20）输出的噪声信号的相位和降噪信号的相位进行采样比较；逻辑处理器（40），用于对采样比较电路（30）的采样比较结果进行逻辑处理，并输出处理结果，处理结果表征抖动超前或者滞后。

Description

电源噪声检测电路及工作方法、抖动限幅电路、电子设备
本申请要求于2022年10月25日提交国家知识产权局、申请号为202211314315.4、发明名称为“电源噪声检测电路及工作方法、抖动限幅电路、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种电源噪声检测电路及工作方法、抖动限幅电路、电子设备。
背景技术
随着消费类电子设备的不断发展，对低成本、低功耗、中高速的模拟芯片需求越来越多。在芯片的实际使用中，对于芯片中的大多数电路而言，电源噪声施加在电路中会产生时钟抖动。电源电压偏高时，导致时钟抖动边沿超前。电源电压偏低时，导致时钟抖动边沿滞后。
因此，为了不影响电路性能，本领域技术人员需要通过技术手段来检测上述时钟抖动，以尝试消除上述时钟抖动。
发明内容
本申请实施例提供一种电源噪声检测电路及工作方法、抖动限幅电路、电子设备，用于以检测电源噪声带来的时钟抖动。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种电源噪声检测电路，用于检测电源噪声对信号相位的影响。电源噪声检测电路包括第一数据产生链路、采样比较电路以及逻辑处理器。第一数据产生链路与时钟信号端耦接，用于工作在噪声电源电压下，对时钟信号端的时钟信号进行处理，输出噪声信号。第一数据产生链路还用于工作在降噪电源电压下，对时钟信号端的时钟信号进行处理，输出降噪信号。采样比较电路与第一数据产生链路耦接，用于对第一数据产生链路输出的噪声信号的相位和降噪信号的相位进行采样比较。逻辑处理器与采样比较电路耦接，逻辑处理器用于对采样比较电路的采样比较结果进行逻辑处理，并输出处理结果。
本申请实施例提供的电源噪声检测电路，第一数据产生链路工作在噪声电源电压下，产生的信号为受电源噪声干扰的噪声信号。第一数据产生链路工作在降噪电源电压下，产生的信号为未受电源噪声干扰的降噪信号，降噪信号作为参考信号。采样比较电路对第一数据产生链路产生的信号(噪声信号和降噪信号)的相位进行比较，将比较结果经逻辑处理器处理后输出，即可将电源噪声对时钟信号的相位的影响进行量化，检测出电源噪声导致的相位波动为相位超前还是相位滞后。本申请实施例提供的电源噪声检测电路不包括片外电容和磁珠等结构，因此，电源噪声检测电路的硬件成本比较低。而且，电源噪声检测电路是采用模拟电路(第一数据产生链路)和数字电路(采样比较电路、逻辑处理器)混合的方法对电源噪声进行量化，数字工艺的信号只有“0”和“1”两种信号，没有中间波动。因此，电源噪声检测电路的工艺敏感性低，受工艺干扰(PVT)较小，性能稳定。再者，降噪电源电压只需要向一个第一数据产生链路供电，第一数据产生链路的功耗要小于实际数据产生链路的功耗。因此，电源噪声检测电路的功耗和面积要远远小于将源极驱动电路中所有数据产生链路置于电源去噪支路下的成熟技术方案。综上所述，本申请实施例提供的电源噪声检测电路可以实现在满足低成本、低功耗、低工艺敏感性的前提下，将电源噪声对相位影响进行量化
在一种可能的实现方式中，电源噪声检测电路还包括电源去噪支路；电源电压端和第一数据产生链路均耦接于电源去噪支路，电源去噪支路用于去除噪声电源电压中的电源噪声，向第一数据产生链路输入降噪电源电压。采用电源去噪支路生成降噪电源电压，降噪电源电压只需要向一个第一数据产生链路供电，功耗较小。
在一种可能的实现方式中，第一数据产生链路用于工作在降噪电源电压下输出第一降噪信号 和第二降噪信号；噪声信号的相位为噪声相位，第一降噪信号的相位为第一超前相位，第二降噪信号的相位为第一滞后相位；第一超前相位和第一滞后相位均与噪声相位相距M个延迟单元；M为正整数。通过将噪声相位，与超前相位和滞后相位进行对比，判断出抖动是否超前或者滞后，电路结构简单，原理简单，易于实现。
在一种可能的实现方式中，第一数据产生链路包括噪声链路和降噪链路；噪声链路，用于工作在噪声电源电压下，输出噪声信号；降噪链路，用于工作在降噪电源电压下，输出第一降噪信号和第二降噪信号。这是一种结构简单的实现方式。
在一种可能的实现方式中，采样比较电路包括第一采样比较器和第二采样比较器；噪声链路和降噪链路均耦接于第一采样比较器，第一采样比较器用于对噪声信号的噪声相位和第一降噪信号的第一超前相位进行采样比较；噪声链路和降噪链路均耦接于第二采样比较器，第二采样比较器用于对噪声相位和第二降噪信号的第一滞后相位进行采样比较。这是一种结构简单的实现方式。
在一种可能的实现方式中，逻辑处理器具有第一信号输出端和第二信号输出端，第一采样比较器和第二采样比较器均耦接于逻辑处理器，逻辑处理器对第一采样比较器的采样比较结果和第二采样比较器的采样比较结果进行逻辑处理，并从第一信号输出端和第二信号端输出比较结果。这是一种结构简单的实现方式。
在一种可能的实现方式中，电源去噪支路包括低压差线性稳压器、电源产生器或滤波器中的至少一个。这是一种结构简单的实现方式。
在一种可能的实现方式中，噪声链路包括至少一个第一延迟单元，降噪链路包括串联的多个第二延迟单元；第一降噪信号的输出端和第二降噪信号的输出端之间具有2M个第二延迟单元。这是一种结构简单的实现方式。
在一种可能的实现方式中，降噪链路还用于工作在降噪电源电压下，输出第三降噪信号和第四降噪信号；第三降噪信号的相位为第二超前相位，第四降噪信号的相位为第二滞后相位；第二超前相位和第二滞后相位均与噪声相位相距N个延迟单元；N为正整数,N≠M。这样一来，将噪声相位与多个超前或滞后参考相位进行对比，可以以不同的抖动幅度作为检测标尺，提高对相位抖动检测的精准度。例如，N<M，在检测出抖动幅度超前或者滞后M个延迟单元的基础上，还可以检测出抖动幅度是否超前或者滞后于N个延迟单元。
在一种可能的实现方式中，采样比较电路还包括第三采样比较器和第四采样比较器；噪声链路、第三降噪链路以及逻辑处理器均与第三采样比较器和第四采样比较器分别耦接；第三采样比较器用于对噪声相位和第二超前相位进行采样比较；第四采样比较器用于对噪声相位和第二滞后相位进行采样比较。通过在电源噪声检测电路中设置第三采样比较器和第四采样比较器，第一采样比较器和第二采样比较器32检测出相位抖动超前或者滞后于M个延迟单元的抖动，第三采样比较器和第四采样比较器可以检测出相位抖动超前或者滞后于N个延迟单元的抖动，N≠M。相当于将噪声相位与多个超前或滞后参考相位进行对比，可以以不同的抖动幅度作为检测标尺，提高对相位抖动检测的精准度。
在一种可能的实现方式中，逻辑处理器具有第三信号输出端和第四信号输出端；第三采样比较器和第四采样比较器均耦接于逻辑处理器，逻辑处理器对第三采样比较器的采样比较结果和第四采样比较器的采样比较结果进行逻辑处理，并从第三信号输出端和第四信号端输出比较结果。这是一种结构简单的实现方式。
在一种可能的实现方式中，第三降噪信号的输出端和第四降噪信号的输出端之间具有2N个第二延迟单元。这是一种结构简单的实现方式。
本申请实施例的第二方面，提供一种抖动限幅电路，包括电源噪声检测电路、第一抖动补偿电路以及第二数据产生链路；电源噪声检测电路包括第一方面任一项的电源噪声检测电路；第一抖动补偿电路耦接于时钟数据信号端和第二数据产生链路之间；第一抖动补偿电路还与电源噪声检测电路耦接，用于根据电源噪声检测电路的输出反向补偿时钟数据信号端的数据的相位。
本申请实施例第二方面提供的抖动限幅电路，包括第一方面的电源噪声检测电路，其有益效 果与电源噪声检测电路的有益效果相同，此处不再赘述。
在一种可能的实现方式中，第一抖动补偿电路包括串联的第三延迟单元和第四延迟单元、第一电容、第一开关、第二电容以及第二开关；第三延迟单元的输入端与时钟数据信号端耦接，第四延迟单元的输出端与第二数据产生链路耦接；第三延迟单元和第四延迟单元之间具有第一节点；第一电容和第一开关串联耦接于第一节点与参考地电压端之间，第二电容和第二开关串联耦接于第一节点与参考地电压端之间；第一开关的控制端与第一信号输出端耦接，第二开关用于接收第二信号输出端的反向信号。这是一种结构简单的实现方式。
在一种可能的实现方式中，电源噪声检测电路包括第三采样比较器和第四采样比较器；抖动限幅电路还包括第二抖动补偿电路，第二抖动补偿电路与第一抖动补偿电路串联，第二抖动补偿电路还与电源噪声检测电路耦接，用于根据逻辑处理器对第三采样比较器和第四采样比较器的采样比较结果的输出，反向补偿第一抖动补偿电路输出的数据的相位。通过在电源噪声检测电路中设置多组采样比较器，将超前相位和滞后相位拓展为多种延迟单元，延迟修改信号也将拓展为多个。对应的在抖动限幅电路中设置多个抖动补偿电路，多个延迟修改信号控制多个抖动补偿电路，可以扩大抖动优化幅度。
在一种可能的实现方式中，抖动限幅电路包括多条并联的第二数据产生链路。这是一种可能的应用方式。
本申请实施例的第三方面，提供一种电子设备，包括第二方面任一项的抖动限幅电路和电路板，抖动限幅电路与电路板耦接。
本申请实施例提供的电子设备，包括第二方面的抖动限幅电路，其有益效果与抖动限幅电路的有益效果相同，此处不再赘述。
本申请实施例的第四方面，提供一种电源噪声检测电路的工作方法，包括：第一数据产生链路工作在噪声电源电压，输出噪声信号；第一数据产生链路还工作在降噪电源电压下，输出降噪信号；采样比较电路对第一数据产生链路输出的噪声信号的相位和降噪信号的相位进行采样比较；逻辑处理器对采样比较电路的采样比较结果进行逻辑处理，并输出处理结果。
本申请实施例第四方面提供的电源噪声检测电路的工作方法，其有益效果与电源噪声检测电路的有益效果相同，此处不再赘述。
附图说明
图1A为本申请实施例提供的一种电子设备的框架示意图；
图1B为本申请实施例提供的一种电子设备的布局示意图；
图1C为本申请实施例提供的源极驱动电路的框架示意图；
图2A为本申请实施例示意的一种抖动抵消方案示意图；
图2B为本申请实施例示意的另一种抖动抵消方案示意图；
图3A为本申请实施例提供的一种电源噪声检测电路的框架示意图；
图3B为本申请实施例提供的另一种电源噪声检测电路的框架示意图；
图4A为本申请实施例提供的又一种电源噪声检测电路的框架示意图；
图4B为本申请实施例提供的一种噪声链路和降噪链路的结构示意图；
图5A-图5C为本申请实施例提供的一种相位对比示意图；
图6为本申请实施例提供的另一种电源噪声检测电路的框架示意图；
图7为本申请实施例提供的另一种噪声链路和降噪链路的结构示意图；
图8为本申请实施例提供的一种抖动限幅电路的框架示意图；
图9为本申请实施例提供的一种第一抖动补偿电路的结构示意图；
图10为本申请实施例提供的另一种抖动限幅电路的框架示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第二”、“第一”等仅用于描述方便，而不能理解为指示或暗示相对重要性或 者隐含指明所指示的技术特征的数量。由此，限定有“第二”、“第一”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“相耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。术语“接触”可以是直接接触，也可以是通过中间媒介间接的接触。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在开始介绍本申请实施例的细节之前，先对本申请实施例中应用到的技术术语进行定义解释。
电源噪声：一般指电源电压上随时间变化的电压波动。
相位抖动：不同的电压在相同的时钟路径上会产生不同的延迟，最终不同的延迟会导致输出产生不同的相位，即相位抖动。
相位：可以理解为存在一个理想时钟与目标时钟同频，目标时钟上升沿到来时刻与理想时钟上升沿到来时刻之间的差占整个周期的比值再乘以2π称为相位差，如果把理想时钟到来时刻设为0(因为是理想时钟，所以其上升沿到来时刻永远是固定的周期整数倍)，则相位差即相位的值。
抖动：在时钟、数据链路中一般指输出相位随时间的变化。
缓冲器(buffer)：输出等于输入的逻辑电路，主要用于增强推动能力。
磁珠：一种片外器件，性质接近于电感。
低压差稳压器(low droup-out regulator，LDO)：是一种通过负反馈产生一个稳定的输出电压的电路。
链路：指一条组合逻辑通路，一般抖动敏感链路都是由缓冲器组成。
反相器(inverter)，在模拟电路中反相器可以作为一个放大器使用。
栅源电压差(voltage between Gate and Source，VGS)：晶体管的栅极和源极的电压差，对于晶体管而言，栅源电压差决定了其驱动电流。
阈值电压：一般数字逻辑的阈值电压表示输入电压小于这个阈值电压被判断为低，高于这个电压被判断为高。所以阈值电压决定了后级电路感知的输入上升、下降沿到来的时间。对于上升沿，阈值电压越高上升沿就等效为越晚来，对于下降沿则阈值电压越低下降沿就等效为越晚来。
跨导：指晶体管输出电流对输入栅源电压差VGS求导得到的导数。
失配：指晶体管制造过程引入的不匹配问题，一般对于反相器而言，输出沿越缓失配导致的输出相位变化越严重。
采样比较器：其行为大致是输入时钟上升沿到来时，比较输入信号与0的关系，输入大于0则输出高电平，输入小于0则输出低电平。
本申请实施例提供一种的电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、视频传输用电子设备等。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥 控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘(digital video disc，DVD)等。金融终端产品如为自动取款机(automated teller machine，ATM)机、自助办理业务的终端等。视频传输电子设备如为网络视频录像机(network video recorder，NVR)、数字视频录像机(digital video recorder，DVR)、数字硬盘录像机(XVR)、编码器(DVS)、一体机、工控机、网关、行业主机等后端产品。电子设备也可以是机顶盒等具有音频/视频传输需求的电子设备。
以下为了方便说明，以电子设备为平板电脑为例进行举例说明。如图1A所示，电子设备1主要包括盖板11、显示面板12、中框13以及后壳14。后壳14和显示面板12分别位于中框13的两侧，且中框13和显示面板12设置于后壳14内，盖板11设置在显示面板12远离中框13的一侧，显示面板12的显示面朝向盖板11。
上述显示面板12可以是液晶显示屏(liquid crystal display，LCD)，在此情况下，液晶显示屏包括液晶显示面板和背光模组，液晶显示面板设置在盖板11和背光模组之间，背光模组用于为液晶显示面板提供光源。上述显示面板12也可以为有机发光二极管(organic light emitting diode，OLED)显示屏。由于OLED显示屏为自发光显示屏，因而无需设置背光模组。
上述中框13包括承载板131以及绕承载板131一周的边框132。上述电子设备1还可以包括印刷电路板(printed circuit boards，PCB)、电池、摄像头等电子元器件，印刷电路板、电池、摄像头等电子元器件可以设置在承载板131上。
如图1B所示，显示面板12包括有效显示区(active area，AA)A和位于该有效显示区A周边的周边区B。
在一些实施例中，显示面板12的有效显示区A作为电子设备1的显示区，显示面板12的周边区B作为电子设备1的非显示区。
如图1B所示，显示面板12的有效显示区A包括多个亚像素(sub pixel)P。为了方便说明，本申请中上述多个亚像素P是以矩阵形式排列为例进行的说明。此时，沿水平方向排列成一排的亚像素P称为同一行亚像素，沿竖直方向排列成一排的亚像素P称为同一列亚像素。
电子设备1包括位于显示面板12周边区B的栅极驱动电路和源极驱动电路，栅极驱动电路用于为亚像素P提供栅极驱动信号，源极驱动电路用于为亚像素P提供源极驱动信号。
示例的，栅极驱动电路例如可以采用阵列基板行驱动(gate on array，GOA)技术集成在显示面板12中。栅极驱动电路包括多个级联的移位寄存器(shift register，SR)。
栅极驱动电路可以包括一个或者多个，示例的，如图1B所示，电子设备1包括两个栅极驱动电路，两个栅极驱动电路沿水平方向设置在有效显示区A的两侧。
源极驱动电路例如可以集成在驱动芯片(display driver integrated circuit,DDIC)中,示例的，驱动芯片DDIC以裸芯片(die)的形式直接贴合在显示面板12中。
电子设备还包括时序控制器(timing controller，TCON)，在一些实施例中，如图1B所示，设置在柔性电路板(flexible printed circuit，FPC)上。
在一些实施例中，如图1C所示，源极驱动电路包括接收电路和数据输出电路。接收电路可接收从图1B中所示的时序控制器TCON提供的传输信号TD，并且可恢复数据信号DT和时钟信号CK。
数据输出电路可以将接收电路输出的数据信号DT与时钟信号CK转换成数据驱动信号D，并将数据驱动信号D施加至图1B所示的亚像素P中。
数据输出电路中包括数据产生链路，数据产生链路在输出数据驱动信号的过程中容易受到电源噪声的干扰，导致输出的数据驱动信号D产生相位抖动。
为了抑制电源噪声的影响，在一些相关技术中，使用片外电容和磁珠进行虑噪，以抑制电源噪声的影响。
但是，这样会导致硬件成本增大，无法满足低成本的需求。
在另一些相关技术中，如图2A所示，使用低压差稳压器LDO，通过一个更高的输入电压产生一个噪声较小的电源给数据产生链路供电，以抑制电源噪声的影响。
示例的，数据产生链路工作的电源电压为0.9V，使用1.8V的输入电压经低压差稳压器LDO产生一个0.9V的低噪电压后再供给数据产生链路。原来功耗是0.9*I，换成低压差稳压器LDO供电后功耗变为1.8*I，增大了一倍。
因此，使用低压差稳压器LDO降噪供电，会导致系统功耗大大增加，无法满足低功耗的需求。
在又一些相关技术中，如图2B所示，提供一种时钟抖动限幅电路，采用晶体管P1、晶体管N1与晶体管P2、晶体管N2组成两组反相放大器，电阻R1和电阻R2分别给与晶体管P1和晶体管N1静态偏置，电阻R3和电阻R4分别给与晶体管P2和晶体管N2静态偏置，令晶体管P1、晶体管P2、晶体管N1、晶体管N2工作在饱和区。
负电源电压端VSS的电源噪声通过电容C1耦合到晶体管P1和晶体管N1的栅端，被反相放大器放大后通过电容C3耦合到晶体管P3的栅端CTRLP。正电源电压端VDD的电源噪声通过电容C2耦合到晶体管P2和晶体管N2的栅端，被反相放大器放大后通过电容C4耦合到晶体管N4的栅端CTRLN。
电阻R5、电阻R6、电阻R7提供了晶体管P3和晶体管N4的静态偏置，令晶体管P3和晶体管N4可能工作在饱和区。输入信号灌入数据产生链路，经过晶体管P4、晶体管N3后从输出端输出。晶体管P4和晶体管N3本质上是被晶体管P3、晶体管N4限流的反相器。
从电源噪声产生输出抖动的原理上来看，电源噪声是改变了晶体管的驱动能力导致延迟发生变化，继而引起输出相位抖动。上述技术中通过反相放大器将电源噪声放大到晶体管P3的栅端CTRLP和晶体管N4的栅端CTRLN，继而通过晶体管P3、晶体管N4将电源噪声的影响抵消。
例如，当正电源电压端VDD的电源电压增大时，数据产生链路的驱动能力将会增强，延迟将会减小。上述技术中晶体管P3栅端CTRLP的电压会增大，晶体管N4栅端CTRLN法人电压会减小，因此晶体管P3的栅源电压差VGS将会减小，晶体管N4的栅源电压差VGS也会减小。那么，数据产生链路的驱动能力增强，而晶体管P3和晶体管N4的驱动减弱，由此抵消了电源噪声的影响。
当正电源电压端VDD的电源电压减小时，上述技术中晶体管P3栅端CTRLP的电压会减小晶体管N4栅端CTRLN的电压会增大，因此，晶体管P3的栅源电压差VGS将会增大，晶体管N4的栅源电压差VGS也会增大。那么，数据产生链路的驱动能力减小，而晶体管P3和晶体管N4的驱动增强，由此抵消了电源噪声的影响。
上述技术方案虽然可以抵消电源噪声的影响，但是上述技术对电源噪声的抵消增益Gain如下(只考虑上升沿情况)：
其中，tout表示晶体管P3、晶体管P4、晶体管N3、晶体管N4组成的反相器的延迟；Vth表示后一级电路翻转阈值电压；K表示tout与后一级翻转电压阈值的比例。Δtout表示反相器延迟变化量；ΔVDD表示电源电压变化量；ΔK表示tout与阈值电压比例的变化量；ΔVth表示翻转阈值变化量；表示阈值电压随VDD的变化比例。
进一步分析该增益可得：
其中，ICH为晶体管P3、晶体管P4、晶体管N3、晶体管N4组成的反相器对输出的充电电流；C为输出电容；GINV为晶体管P1、晶体管N1、晶体管P2、晶体管N2组成的两个反相放大器的增益；GAC为电容C1、电容C2、电容C3、电容C4组成的AC耦合增益；gm为晶体管P3和晶体管N4的跨导。
公式中GINV、gm都会随着PVT(压强、电压、温度)变化非常剧烈，这意味着上述技术的调制效果很不稳定。由于工艺敏感性比较高，会导致不同芯片之间相差会比较大，甚至可能出现由于调节增益过大导致反而放大抖动的情况。
其次，上述技术需要通过晶体管P3、晶体管N4对输出驱动能力进行调制，将会限制输出的驱动能力， 由此还会引入失配问题。
通过上述描述可知，相关技术中用于抵消电源噪声的方案无法兼顾低成本、低功耗、低工艺敏感性的要求。
基于此，本申请实施例提供一种电源噪声检测电路，用于检测电源噪声，以便于根据电源噪声的检测结构，消除电源噪声对数据产生链路带来的相位抖动。当然，本申请实施例提供的电源噪声检测电路不仅可以应用于抖动限幅电路中，还可以应用于任意需要检测电源噪声的电路中。
如图3A所示，电源噪声检测电路包括第一数据产生链路20、采样比较电路30以及逻辑处理器40。
第一数据产生链路20，与时钟信号端CK耦接，第一数据产生链路20用于工作在噪声电源电压，输出噪声信号。第一数据产生链路20还用于工作在降噪电源电压下，输出降噪信号。
示例的，第一数据产生链路20工作在噪声电源电压下，输出的信号为受到电源电压中的电源噪声干扰的噪声信号。由于降噪电源电压中没有或者几乎没有电源噪声，因此，第一数据产生链路20工作在降噪电源电压下，输出的信号为未受到电源电压中的电源噪声干扰的降噪信号。降噪信号作为参考信号，噪声信号和降噪信号的频率相同，相位不同。
在一些实施例中，第一数据产生链路20用于工作在噪声电源电压下输出噪声信号，第一数据产生链路20还用于工作在降噪电源电压下输出第一降噪信号和第二降噪信号。
噪声信号的相位为噪声相位p，第一降噪信号的相位为第一超前相位p1，第二降噪信号的相位为第一滞后相位p2。第一超前相位p1和第一滞后相位p2均与噪声相位p相距M个延迟单元，每个延迟单元的延具有一个延迟时间(tdel)；M为正整数。
采样比较电路30，与第一数据产生链路20耦接，用于对第一数据产生链路20输出的信号的相位进行采样比较。
采样比较电路30，用于对第一数据产生链路20输出的噪声信号的相位和降噪信号的相位进行采样比较。在一些实施例中，采样比较电路30用于对噪声信号的噪声相位p和第一降噪信号的第一超前相位p1进行采样比较，对噪声相位p和第二降噪信号的第一滞后相位p2进行采样比较。
逻辑处理器40，与采样比较电路30耦接。逻辑处理器40用于对采样比较电路30的采样比较结果进行逻辑处理，并输出处理结果。
示例的，处理结果包括第一信号、第二信号以及第三信号。第一信号表征噪声电源电压中的电源噪声导致时钟信号端的时钟信号的相位超前，第二信号表征噪声电源电压中的电源噪声导致时钟信号端的时钟信号的相位滞后，第三信号表征噪声电源电压中的电源噪声对时钟信号端的时钟信号的相位的抖动在可接受的范围内。
在一些实施例中，如图3B所示，电源噪声检测电路还包括电源去噪支路50。
电源电压端AVDDL和第一数据产生链路20均耦接于电源去噪支路50，电源去噪支路50用于去除噪声电源电压中的电源噪声，向第一数据产生链路20输入降噪电源电压。
本申请实施例提供的电源噪声检测电路，第一数据产生链路20工作在噪声电源电压下，产生的信号为受电源噪声干扰的噪声信号。第一数据产生链路20工作在降噪电源电压下，产生的信号为未受电源噪声干扰的降噪信号，降噪信号作为参考信号。采样比较电路30对第一数据产生链路20产生的信号(噪声信号和降噪信号)的相位进行比较，将比较结果经逻辑处理器40处理后输出，即可将电源噪声对时钟信号的相位的影响进行量化，检测出电源噪声导致的相位波动为相位超前还是相位滞后。
另外，本申请实施例提供的电源噪声检测电路不包括片外电容和磁珠等结构，因此，电源噪声检测电路的硬件成本比较低。而且，电源噪声检测电路是采用模拟电路(第一数据产生链路20)和数字电路(采样比较电路30、逻辑处理器40)混合的方法对电源噪声进行量化，数字工艺的信号只有“0”和“1”两种信号，没有中间波动。因此，电源噪声检测电路的工艺敏感性低，受工艺干扰(PVT)较小，性能稳定。再者，电源去噪支路50只需要向一个第一数据产生链路20供电，第一数据产生链路20的功耗要小于图1C中源极驱动电路中的数据产生链路的功 耗。因此，电源噪声检测电路的功耗和面积要远远小于将源极驱动电路中所有数据产生链路置于电源去噪支路50下的成熟技术方案。综上所述，本申请实施例提供的电源噪声检测电路可以实现在满足低成本、低功耗、低工艺敏感性的前提下，将电源噪声对相位影响进行量化。
下面，对本申请实施例提供的电源检测电路进行详细说明。
如图4A所示，电源噪声检测电路包括第一数据产生链路20、采样比较电路30、逻辑处理器40以及电源去噪支路50。
第一数据产生链路20包括并列的噪声链路21和降噪链路22，采样比较电路30包括第一采样比较器31和第二采样比较器32。
电源去噪支路50与电源电压端AVDDL耦接，用于去除电源电压端AVDDL的噪声电源电压中的噪声，输出降噪电源电压。
示例的，电源去噪支路50可以包括低压差线性稳压器、电源产生器或滤波器中的至少一个。
那么，电源电压端AVDDL输出的噪声电源电压经电源去噪支路50后，相当于滤除掉了噪声电源电压中的电源噪声。
噪声链路21与时钟信号端CK和电源电压端AVDDL耦接，用于工作在电源电压端AVDDL的噪声电源电压下，输出噪声信号。
时钟信号端CK作为噪声链路21的时钟输入，噪声链路21直接工作在噪声电源电压下。电源噪声会对噪声链路21产生影响，噪声链路21输出受电源噪声影响后的噪声信号，噪声信号的相位称为噪声相位p。
降噪链路22与时钟信号端CK和电源去噪支路50耦接，用于工作在电源去噪支路50输出的降噪电源电压下，输出第一降噪信号和第二降噪信号，第一降噪信号和第二降噪信号的相位不同。
在一些实施例中，噪声信号的相位为噪声相位p，第一降噪信号的相位为第一超前相位p1，第二降噪信号的相位为第一滞后相位p2。第一超前相位p1和第一滞后相位p2均与噪声相位p相距M个延迟单元；M为正整数。时钟信号端CK作为降噪链路22的时钟输入，与噪声链路21不同的是，降噪链路22直接工作在降噪电源电压下。电源噪声几乎不会对降噪链路22产生影响，降噪链路22输出未受电源噪声影响的第一降噪信号和第二降噪信号，第一降噪信号和第二降噪信号可以作为参考时钟信号,第一降噪信号和第二降噪信号的相位作为参考相位。
通过将第一超前相位p1和第一滞后相位p2与噪声相位p进行比较，可以判断出噪声相位p是否相对第一超前相位p1超前，或者相对第一滞后相位p2滞后，以检测出电源噪声带来的相位抖动。
示例的，M＝1。第一滞后相位P2和第一超前相位P1均与噪声相位相距1个延迟单元，第一滞后相位P2和第一超前相位P1之间相距2个延迟单元。
通过调整第一滞后相位P2和第一超前相位P1与噪声相位相距的延迟单元M，可以调整相位抖动的检测幅度，从而确定相位抖动的调节步长。M越小，相位抖动的调节步长越小，对相位抖动的容忍度就越低。因此，可以根据不同应用场景下不同的相位抖动容忍度，来调整M的大小。
在一些实施例中，如图4B所示，噪声链路21包括至少一个第一延迟单元211，降噪链路22包括串联的多个第二延迟单元221，第二延迟单元221的数量比第一延迟单元211的数量多M个。图4B中以M＝1为例进行示意。
在噪声链路21包括多个第一延迟单元211的情况下，多个第一延迟单元211串联。第一级第一延迟单元211与时钟信号端CK和电源电压端AVDDL耦接，其余第一延迟单元211与电源电压端AVDDL耦接，最后一级第一延迟单元211的输出端输出噪声信号。
第一级第二延迟单元221与时钟信号端CK和电源去噪支路50耦接，其余第二延迟单元221与电源去噪支路50耦接。
第一延迟单元211例如可以是缓冲器(buffer)，第二延迟单元221例如可以是缓冲器。
示例的，噪声链路21的输出端作为噪声相位的输出端P，降噪链路22具有第一降噪信号的 输出端P1和第二降噪信号的输出端P2。第一降噪信号的输出端P1相比噪声链路21的输出端超前M个第二延迟单元221，第二降噪信号的输出端P2相比噪声链路21的输出端滞后M个第二延迟单元221，第一降噪信号的输出端P1和第二降噪信号的输出端P2之间具有2M个第二延迟单元221。例如，降噪链路22的输出端作为第二降噪信号的输出端P2。
当然，任意能够产生第一降噪信号和第二降噪信号的第一数据链路20均适用于本申请实施例，图4B中的结构仅为一种示意。
下面，对噪声相位p与第一滞后相位P2和第一超前相位P1进行比较的方法进行示意说明。
在一些实施例中，噪声链路21和降噪链路22分别与第一采样比较器31耦接，例如，第一采样比较器31与噪声链路21噪声相位的输出端P和降噪链路22的第一降噪信号的输出端P1耦接。
第一采样比较器31用于对噪声信号的噪声相位p和降噪信号的第一超前相位P1进行采样比较，并输出比较结果。
噪声链路21和降噪链路22分别与第二采样比较器32耦接，例如，第二采样比较器32与噪声链路21的噪声相位的输出端P和降噪链路22的第二降噪信号的输出端P2耦接。
第二采样比较器32用于对噪声链路21输出的噪声信号的噪声相位p和降噪链路22输出的降噪信号的第一滞后相位P2进行采样比较，并输出比较结果。
在一些实施例中，第一采样比较器31用于在噪声相位p超前于第一超前相位P1的情况下，输出第二数字信号，在噪声相位p未超前于第一超前相位P1的情况下，输出第一数字信号。
第二采样比较器32用于在噪声相位p滞后于第一滞后相位P2的情况下，输出第一数字信号，在噪声相位p未滞后于第一滞后相位P2的情况下，输出第二数字信号。
其中，第一数字信号和第二数字信号互为0和1。本申请实施例中以第一数字信号为1，第二数字信号为0为例进行示意。
示例的，可以在噪声相位p、第一滞后相位P2和第一超前相位P1的上升沿处进行采样比较，也可以在噪声相位p、第一滞后相位P2和第一超前相位P1的下降沿处进行采样比较，还可以对噪声相位p、第一滞后相位P2和第一超前相位P1进行差分采样比较。或者相关技术中可以对噪声相位p、第一滞后相位P2和第一超前相位P1进行采样比较的方式，均可应用于本申请实施例中。
下面，以在噪声相位p、第一滞后相位P2和第一超前相位P1的上升沿处进行采样比较为例，对第一采样比较器31和第二采样比较60的实现过程进行说明。
在第一超前相位P1的上升沿时，若噪声信号小于阈值，则输出第二数字信号。若噪声信号大于阈值(示例的，阈值为噪声电源电压的一半)，则输出第一数字信号。
在第一滞后相位P2的上升沿时，若噪声信号小于阈值，则输出第二数字信号。若噪声信号大于阈值，则输出第一数字信号。
第一采样比较器31和第二采样比较器32的输出端分别与逻辑处理器40耦接，逻辑处理器40用于根据第一采样比较器31和第二采样比较器32的采样比较结果，输出第一信号和第二信号。
第一信号表征噪声电源电压中的电源噪声导致时钟信号端CK的时钟信号的相位超前，第二信号表征噪声电源电压中的电源噪声导致时钟信号端CK的时钟信号的相位滞后。
在一些实施例中，逻辑处理器40具有第一信号输出端O1和第二信号输出端O2。
逻辑处理器40用于在第一采样比较器31输出第一数字信号，第二采样比较器32输出第一数字信号的情况下，从第一信号输出端O1输出第一数字信号作为第一信号，并从第二信号输出端输出第二数字信号。
第一采样比较器31输出第一数字信号，在第二采样比较器32输出第一数字信号的情况下，从第一信号输出端O1输出第一数字信号，从第二信号输出端O2输出第二数字信号，作为第一信号。
在第一采样比较器31输出第二数字信号，第二采样比较器32输出第二数字信号的情况下， 从第一信号输出端O1输出第二数字信号，从第二信号输出端O2输出第一数字信号，作为第二信号。
示例的，如图5A-图5C所示，逻辑处理器40根据第一采样比较器31和第二采样比较器32的采样结果，输出电源噪声导致时钟信号相位超前(up)、滞后(down)或者保持(hold)的判断结果。
例如，如图5A所示，当电源电压端AVDDL出现正向大纹波，会影响噪声链路21，噪声相位P则会因为电压升高导致延迟减小而变得超前。但是降噪链路22工作在降噪电源电压下，因此，第一超前相位P1和第一滞后相位P2不受影响。
第一采样比较器31将噪声相位P与第一超前相位P1进行对比。在第一超前相位P1的上升沿时，噪声信号大于阈值，第一采样比较器31输出第一数字信号。第二采样比较器32将噪声相位P与第一滞后相位P2进行对比。在第一滞后相位P2的上升沿时，噪声信号大于阈值，第二采样比较器32输出第一数字信号。那么，第一采样比较器31输出第一数字信号，第二采样比较器32输出第一数字信号，逻辑处理器40从第一信号输出端O1输出第一数字信号，逻辑处理器40从第二信号输出端O2输出第二数字信号。作为表征噪声电源电压中的电源噪声导致时钟信号端的时钟信号的相位超前的第一信号。
那么，在电源噪声导致时钟信号的相位超前时，电源噪声检测电路的输出为第一信号输出端O1输出第一数字信号，第二信号输出端O2输出第二数字信号。例如，相位超前时，O1＝1，O2＝0。
如图5B所示，当电源电压端AVDDL出现负向大波纹，会影响噪声链路21，噪声相位P则会因为电压降低导致延迟增大而变得滞后。但是降噪链路22工作在降噪电源电压下，因此，第一超前相位P1和第一滞后相位P2不受影响。
第一采样比较器31将噪声相位P与第一超前相位P1进行对比。在第一超前相位P1的上升沿时，噪声信号小于阈值，第一采样比较器31输出第二数字信号。第二采样比较器32将噪声相位P与第一滞后相位P2进行对比。在第一滞后相位P2的上升沿时，噪声信号小于阈值(噪声电源电压的一半)，第二采样比较器32输出第二数字信号。那么，第一采样比较器31输出第二数字信号，第二采样比较器32输出第二数字信号，逻辑处理器40从第一信号输出端O1输出第二数字信号，逻辑处理器40从第二信号输出端O2输出第一数字信号。作为表征噪声电源电压中的电源噪声导致时钟信号的相位滞后的第二信号。
那么，在电源噪声导致时钟信号的相位滞后时，电源噪声检测电路的输出为第一信号输出端O1输出第二数字信号，第二信号输出端O2输出第一数字信号。例如，相位超前时，O1＝0，O2＝1。
如图5C所示，当电源电压端AVDDL出现小波纹，会影响噪声链路21，但电源噪声对相位造成的影响在可接受的范围内。降噪链路22工作在降噪电源电压下，因此，第一超前相位P1和第一滞后相位P2不受影响。
第一采样比较器31将噪声相位P与第一超前相位P1进行对比。在第一超前相位P1的上升沿时，噪声信号小于阈值，第一采样比较器31输出第二数字信号。第二采样比较器32将噪声相位P与第一滞后相位P2进行对比。在第一滞后相位P2的上升沿时，噪声信号大于阈值，第二采样比较器32输出第一数字信号。那么，第一采样比较器31输出第二数字信号，第二采样比较器32输出第一数字信号，逻辑处理器40从第一信号输出端O1输出第二数字信号，从第二信号输出端O2输出第二数字信号。
那么，在电源噪声导致时钟信号的相位抖动在可接受范围内时，电源噪声检测电路的输出为第一信号输出端O1输出第二数字信号，第二信号输出端O2输出第二数字信号。例如，相位超前时，O1＝0，O2＝0。
此时，可以认为噪声检测电路输出第三信号，第三信号表征噪声电源电压中的电源噪声导致时钟信号端CK的时钟信号的相位抖动在容忍范围内。
本申请实施例提供的电源噪声检测电路，通过使噪声链路21工作在噪声电源电压下，产生 噪声相位p。降噪链路22工作在降噪电源电压下，产生参考相位，并取滞后于噪声相位pM个延迟单元的第一超前相位P1和超前于噪声相位pM个延迟单元的第一滞后相位P2作为参考相位。通过将噪声相位p与第一超前相位P1及第一滞后相位P2分别作出比较，以M个延迟单元作为抖动大小的衡量单位，将电源噪声对相位的影响进行量化，并检测出电源噪声导致的相位波动为相位超前还是相位滞后。由于本申请实施例提供的电源噪声检测电路不包括片外电容和磁珠等结构，因此，电源噪声检测电路的硬件成本比较低。而且，电源去噪支路50只需要向降噪链路22供电，降噪链路22的功耗要小于源极驱动电路中数据产生链路的功耗。因此，电源噪声检测电路的功耗和面积要远远小于将源极驱动电路中所有数据产生链路置于电源去噪支路50下的成熟技术方案。再者，电源噪声检测电路是采用模拟电路(噪声链路21、电源去噪支路50、降噪链路22)和数字电路(第一采样比较器31、第二采样比较器32、逻辑处理器40)混合的方法对电源噪声进行量化，数字工艺的信号只有“0”和“1”两种信号，没有中间波动。因此，电源噪声检测电路的工艺敏感性低，受工艺干扰(PVT)较小，性能稳定。综上所述，本申请实施例提供的电源噪声检测电路可以实现在满足低成本、低功耗、低工艺敏感性的前提下，将电源噪声对相位影响进行量化。
在一些实施例中，如图6所示，电源噪声检测电路还包括第三采样比较器33和第四采样比较器34。
噪声链路21、降噪链路22以及逻辑处理器40均与第三采样比较器33和第四采样比较器34分别耦接。相当于说，第三采样比较器33与第一采样比较器31并联，第四采样比较器34与第二采样比较器32并联。
如图7所示，降噪链路22还包括第三降噪信号的输出端P3和第四降噪信号的输出端P4，第三降噪信号的输出端P3和第四降噪信号的输出端P4均噪声相位的输出端P相距N个第二延迟单元221，第三降噪信号的输出端P3和第四降噪信号的输出端P4之间相距2N个第二延迟单元221。
其中，N为正整数，且N≠M。N可以大于M，N也可以小于M。例如，M＝1，N＝2。
那么，第四降噪信号的输出端P4采得的第二滞后相位p4和第三降噪信号的输出端P3采得的第二超前相位p3均与噪声相位相p距N个延迟单元，第二滞后相位p4和第二超前相位p3之间相距2N个延迟单元。
噪声链路21的噪声相位的输出端P和降噪链路22的第四降噪信号的输出端P4均耦接于第四采样比较器34的输入端，第四采样比较器34的输出端耦接于逻辑处理器40。
第四采样比较器34用于对噪声链路21输出的噪声信号的噪声相位p和降噪链路22输出的降噪信号的第二滞后相位p4进行采样比较,并将比较结果输出至逻辑处理器40。
噪声链路21的噪声相位的输出端P和降噪链路22的第三降噪信号的输出端P3均耦接于第三采样比较器62的输入端，第三采样比较器62的输出端耦接于逻辑处理器40。
第三采样比较器62用于对噪声链路21输出的噪声信号的噪声相位p和降噪链路22输出的降噪信号的第二超前相位p3进行采样比较,并将比较结果输出至逻辑处理器40。
第三采样比较器33例如可以和第一采样比较器31的结构、原理相同，二者采样对比的相位不同，可参考上述关于第一采样比较器31的相关描述。第四采样比较器34例如可以和第二采样比较器32的结构、原理相同，二者采样对比的相位不同，可参考上述关于第二采样比较器32的相关描述。
逻辑处理器40还用于根据第三采样比较器33和第四采样比较器34的采样比较结果，输出第一信号和第二信号。
示例的，如图6所示，逻辑处理器40还包括第三信号输出端O3和第四信号输出端O4，逻辑处理器40对第三采样比较器33和第四采样比较器34的采样结果进行比较后，将比较结果从第三信号输出端O3和第四信号输出端O4输出。
逻辑处理器40对第三采样比较器33和第四采样比较器34的采样结果的比较过程，可以参考上述关于逻辑处理器40对第一采样比较器31和第二采样比较器32的采样结果的处理过程。
示例的，相位超前时，第三信号输出端O3输出第二数字信号，第四信号输出端O4输出第一数字信号。例如，第三信号输出端O3输出1，第四信号输出端O4输出0。
相位滞后时，第三信号输出端O3输出第一数字信号，第四信号输出端O4输出第二数字信号。例如，第三信号输出端O3输出0，第四信号输出端O4输出1。
相位抖动在容忍范围内时，第三信号输出端O3输出第一数字信号，第四信号输出端O4输出第一数字信号。例如，第三信号输出端O3输出0，第四信号输出端O4输出0。
在一些实施例中，逻辑处理器40包括第一逻辑单元和第二逻辑单元，对第一采样比较器31和第二采样比较器32的采样结果进行比较的工作由第一逻辑处理单元完成，逻辑处理器40中用于对第三采样比较器33和第四采样比较器34的采样结果进行比较的工作由第二逻辑处理单元完成。
将第一采样比较器31和第二采样比较器32看作一组采样比较器，将第三采样比较器33和第四采样比较器34看作一组采样比较器。本申请实施例提供的电源噪声检测电路中还可以包括多组采样比较器，每组采样比较器用于采集降噪信号中不同的超前相位和滞后相位。
通过在电源噪声检测电路中设置第三采样比较器33和第四采样比较器34，第一采样比较器31和第二采样比较器32可以检测出相位抖动超前或者滞后于M个延迟单元的抖动，第三采样比较器33和第四采样比较器34可以检测出相位抖动超前或者滞后于N个延迟单元的抖动，N≠M。相当于将噪声相位p与多个超前或滞后参考相位进行对比，可以以不同的抖动幅度作为检测标尺，提高对相位抖动检测的精准度。例如，N<M，在检测出抖动幅度超前或者滞后M个延迟单元的基础上，还可以检测出抖动幅度是否超前或者滞后于N个延迟单元。
本申请实施例还提供一种抖动限幅电路，将上述电源噪声检测电路应用于本申请实施例提供的抖动限幅电路中。
如图8所示，抖动限幅电路包括电源噪声检测电路、第一抖动补偿电路81以及第二数据产生链路90。
电源噪声检测电路、第一抖动补偿电路81以及第二数据产生链路90串联耦接，第一抖动补偿电路81耦接于电源噪声检测电路和第二数据产生链路90之间。
第二数据产生链路90，例如为图1C所示的源极驱动电路中的数据产生链路。
第一抖动补偿电路81还与时钟数据信号端C/D耦接，用于根据电源噪声检测电路的输出反向补偿时钟数据信号端C/D的数据的相位。
也就是说，在电源噪声检测电路输出第一信号时，第一抖动补偿电路81先滞后时钟数据信号端C/D的数据的相位，然后将相位滞后抖动的数据传输至第二数据产生链路90。此时，第二数据产生链路90工作在噪声电源电压下，对数据进行相位超前抖动。第二数据产生链路90的输出端OT输出的数据为相位滞后抖动和相位超前抖动进行抵消后的数据，以达到消除电源噪声带来的输出抖动的目的。同理，在电源噪声输出第二信号时，第一抖动补偿电路81先超前抖动时钟数据信号端C/D的数据的相位，然后将相位超前抖动的数据传输至第二数据产生链路90。此时，第二数据产生链路90工作在噪声电源电压下，对数据进行相位滞后抖动。第二数据产生链路90的输出端OT输出的数据为相位滞后抖动和相位超前抖动进行抵消后的数据，以达到消除电源噪声带来的输出抖动的目的。
本申请实施例中，时钟数据信号端C/D传输的数据，可以是时钟信号，也可以是数据信号，本申请实施例对此不做限定。
在一些实施例中，如图8所示，抖动限幅电路包括多条并联的第二数据产生链路90。
本申请实施例中，电源噪声检测电路检测出电源噪声带来的相位抖动的大小和方向后，经第一抖动补偿电路81反向补偿后，可同时为多条第二数据产生链路90传输信号。
在一些实施例中，如图9所示，第一抖动补偿电路81包括串联的第三延迟单元811和第四延迟单元812、第一电容C1、第一开关SW1、第二电容C2以及第二开关SW2。
第三延迟单元811的输入端与时钟数据信号端C/D耦接，第四延迟单元812的输出端与第二数据产生链路90耦接，第三延迟单元811和第四延迟单元812还分别与电源电压端AVDDL耦 接。
第三延迟单元811和第四延迟单元812之间具有第一节点A，第一电容C1和第一开关SW1串联耦接于第一节点A与参考地电压端GND之间，第二电容C2和第二开关SW2串联耦接于第一节点A与参考地电压端GND之间。第一开关SW1的控制端与第一信号输出端O1耦接，第二开关SW2用于接收第二信号输出端O2的反向信号。
示例的，在电源噪声检测电路检测电源噪声导致相位超前时，O1＝1，O2＝0。那么，第二信号输出端O2输出信号的反向信号O2B＝1。此时，第一抖动补偿电路81接收到的信号为O1＝1，O2B＝1。
那么，第一开关SW1闭合，第二开关SW2闭合，第三延迟单元811的负载为第一电容C1+第二电容C2，负载增大，相位将滞后抖动。第一抖动补偿电路81将相位滞后抖动的数据传输至第二数据产生链路90。第二数据产生链路90工作在噪声电源电压下，对数据进行相位超前抖动。第二数据产生链路90的输出端OT输出的数据为相位滞后抖动和相位超前抖动进行抵消后的数据，以达到消除电源噪声带来的输出抖动的目的。
在电源噪声检测电路检测电源噪声导致相位滞后时，O1＝0，O2＝1。那么，第二信号输出端O2输出信号的反向信号O2B＝0。此时，第一抖动补偿电路81接收到的信号为O1＝0，O2B＝0。
那么，第一开关SW1断开，第二开关SW2断开，第三延迟单元811的负载为0，负载减小，相位将超前抖动。第一抖动补偿电路81将相位滞后超前的数据传输至第二数据产生链路90。第二数据产生链路90工作在噪声电源电压下，对数据进行相位滞后抖动。第二数据产生链路90的输出端OT输出的数据为相位超前抖动和相位滞后抖动进行抵消后的数据，以达到消除电源噪声带来的输出抖动的目的。
在电源噪声检测电路检测电源噪声导致相位抖动在可接受的范围内时，O1＝0，O2＝0。那么，第二信号输出端O2输出信号的反向信号O2B＝1。此时，第一抖动补偿电路81接收到的信号为O1＝0，O2B＝1。
那么，第一开关SW1断开，第二开关SW2闭合，第三延迟单元811的负载为第二电容C2，负载正常，相位不超前也不滞后。第一抖动补偿电路81将相位保持的数据传输至第二数据产生链路90。第二数据产生链路90工作在噪声电源电压下，对数据进行可接受的抖动。第二数据产生链路90的输出端OT输出的数据仍为相位抖动可接受的数据。
在一些实施例中，如图10所示，电源噪声检测电路包括第三采样比较器33和第四采样比较器34的情况下，抖动限幅电路还包括第二抖动补偿电路82。
第二抖动补偿电路82与第一抖动补偿电路81串联。第二抖动补偿电路82还与电源噪声检测电路耦接，用于根据电源噪声检测电路对第三采样比较器33和第四采样比较器34的采样比较结果的输出，反向补偿时钟数据信号端C/D的数据。
在一些实施例中，第二抖动补偿电路82与第一抖动补偿电路81的结构相同，工作原理也相同。
示例的，第二抖动补偿电路82与第三信号输出端O3和第四信号输出端O4耦接，第二抖动补偿电路82受第三信号输出端O3和第四信号输出端O4输出的信号的控制，决定是否提前对第一抖动补偿电路81输出的数据的相位进行进一步的反向补偿。
根据电源噪声影响程度不同，会出现第一抖动补偿电路81和第二抖动补偿电路82均反向补偿，或者第一抖动补偿电路81反向补偿，第二抖动补偿电路82保持不补偿，或者，第一抖动补偿电路81和第二抖动补偿电路82均保持不补偿等多种组合情况。
当然，本申请实施例提供的抖动限幅电路不限定为包括两个抖动补偿电路，还可以包括两个以上抖动补偿电路，根据需要合理设置即可。
例如第一抖动补偿电路81的调节步长为最低有效位(least significant bit，LSB)，则抖动限幅电路所能减小的抖动就是LSB。第一抖动补偿电路81的鉴相精度由降噪链路22输出的第一滞后相位P2和第一超前相位P1相对于噪声链路21输出的噪声相位p的直流偏差(DC偏差，也称为静态偏差)决定。例如，噪声相位p与第一滞后相位P2和第一超前相位P1的DC偏 差为一个延迟时间tdel，一般地LSB<＝2*tdel。当电源噪声导致的相位抖动大于阈值+/-tdel，第一抖动补偿电路81就会将输出相位反向调制一个LSB减小抖动。如果实际抖动小于+/-(LSB+tdel)，则输出抖动将会被限制在+/-tdel。如果实际抖动大于+/-(LSB+tdel)，则输出抖动将会＝+/-(实际抖动-LSB)，即对实际抖动优化+/-LSB。
当电源噪声检测电路包括第三采样比较器33和第四采样比较器34时，参考相位包括第一超前相位P1、第二超前相位p3、第一滞后相位P2和第二滞后相位p4。例如M＝1，N＝2。那么，第一超前相位P1和第一滞后相位P2相对噪声相位p滞后和超前1*tdel，第二超前相位p3和第二滞后相位p4相对噪声相位p滞后和超前2*tdel。第一抖动补偿电路81反向调节+-1*LSB的延迟，第二抖动补偿电路82反向调节+-2*LSB的延迟。当电源噪声导致噪声相位p超前超过2*tdel时，如果抖动限幅电路只有第一抖动补偿电路81，则系统只能调节1*LSB的相位变化，其余部分无法调节。如果抖动限幅电路还包括第二抖动补偿电路82，则系统可以调节3LSB的相位变化。
因此，通过在电源噪声检测电路中设置多组采样比较器，将超前相位和滞后相位拓展为多种延迟单元，延迟修改信号也将拓展为多个。对应的在抖动限幅电路中设置多个抖动补偿电路，多个延迟修改信号控制多个抖动补偿电路，可以扩大抖动优化幅度。
本申请实施例还提供一种电源噪声检测电路的工作方法，包括第一数据产生链路20工作在噪声电源电压，输出噪声信号；第一数据产生链路20还工作在降噪电源电压下，输出降噪信号。采样比较电路30对第一数据产生链路20输出的噪声信号的相位和降噪信号的相位进行采样比较。逻辑处理器40对采样比较电路30的采样比较结果进行逻辑处理，并输出处理结果。
各器件的具体工作过程，可参考上述对电源噪声检测电路的描述，此处不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种电源噪声检测电路，其特征在于，包括：
    第一数据产生链路，用于工作在噪声电源电压，输出噪声信号；还用于工作在降噪电源电压下，输出降噪信号；
    采样比较电路，用于对所述第一数据产生链路输出的所述噪声信号的相位和所述降噪信号的相位进行采样比较；
    逻辑处理器，用于对所述采样比较电路的采样比较结果进行逻辑处理，并输出处理结果。
  2. 根据权利要求1所述的电源噪声检测电路，其特征在于，还包括电源去噪支路；
    所述电源去噪支路用于去除所述噪声电源电压中的电源噪声，向所述第一数据产生链路输入所述降噪电源电压。
  3. 根据权利要求1或2所述的电源噪声检测电路，其特征在于，所述第一数据产生链路用于工作在所述降噪电源电压下，输出第一降噪信号和第二降噪信号；
    所述噪声信号的相位为噪声相位，所述第一降噪信号的相位为第一超前相位，所述第二降噪信号的相位为第一滞后相位；所述第一超前相位和所述第一滞后相位均与所述噪声相位相距M个延迟单元；M为正整数。
  4. 根据权利要求1-3任一项所述的电源噪声检测电路，其特征在于，所述第一数据产生链路包括噪声链路和降噪链路；
    所述噪声链路，用于工作在所述噪声电源电压下，输出所述噪声信号；
    所述降噪链路，用于工作在所述降噪电源电压下，输出第一降噪信号和第二降噪信号。
  5. 根据权利要求4所述的电源噪声检测电路，其特征在于，所述采样比较电路包括第一采样比较器和第二采样比较器；
    所述第一采样比较器用于对所述噪声信号的噪声相位和所述第一降噪信号的第一超前相位进行采样比较；
    所述第二采样比较器用于对所述噪声相位和所述第二降噪信号的第一滞后相位进行采样比较。
  6. 根据权利要求5所述的电源噪声检测电路，其特征在于，所述逻辑处理器具有第一信号输出端和第二信号输出端，所述逻辑处理器用于对所述第一采样比较器的采样比较结果和所述第二采样比较器的采样比较结果进行逻辑处理，并从所述第一信号输出端和所述第二信号端输出比较结果。
  7. 根据权利要求2-6任一项所述的电源噪声检测电路，其特征在于，所述电源去噪支路包括低压差线性稳压器、电源产生器或滤波器中的至少一个。
  8. 根据权利要求4-6任一项所述的电源噪声检测电路，其特征在于，所述噪声链路包括至少一个第一延迟单元，所述降噪链路包括串联的多个第二延迟单元；
    所述第一降噪信号的输出端和所述第二降噪信号的输出端之间具有2M个所述第二延迟单元。
  9. 根据权利要求4-8任一项所述的电源噪声检测电路，其特征在于，所述降噪链路还用于工作在所述降噪电源电压下，输出第三降噪信号和第四降噪信号；
    所述第三降噪信号的相位为第二超前相位，所述第四降噪信号的相位为第二滞后相位；所述第二超前相位和所述第二滞后相位均与所述噪声相位相距N个延迟单元；N为正整数,N≠M。
  10. 根据权利要求9所述的电源噪声检测电路，其特征在于，所述采样比较电路还包括第三采样比较器和第四采样比较器；
    所述第三采样比较器用于对所述噪声相位和所述第二超前相位进行采样比较；所述第四采样比较器用于对所述噪声相位和所述第二滞后相位进行采样比较。
  11. 根据权利要求10所述的电源噪声检测电路，其特征在于，所述逻辑处理器具有第三信号输出端和第四信号输出端；所述逻辑处理器还用于对所述第三采样比较器的采样比较结果和所述第四采样比较器的采样比较结果进行逻辑处理，并从所述第三信号输出端和所述第四信号端输 出比较结果。
  12. 根据权利要求9-11任一项所述的电源噪声检测电路，其特征在于，所述第三降噪信号的输出端和所述第四降噪信号的输出端之间具有2N个所述第二延迟单元。
  13. 一种抖动限幅电路，其特征在于，包括电源噪声检测电路、第一抖动补偿电路以及第二数据产生链路；所述电源噪声检测电路包括权利要求1-12任一项所述的电源噪声检测电路；
    所述第一抖动补偿电路耦接于所述电源噪声检测电路和所述第二数据产生链路之间；所述第一抖动补偿电路用于根据所述电源噪声检测电路的输出反向补偿时钟数据信号端的数据的相位。
  14. 根据权利要求13所述的抖动限幅电路，其特征在于，所述第一抖动补偿电路包括串联的第三延迟单元和第四延迟单元、第一电容、第一开关、第二电容以及第二开关；
    所述第三延迟单元的输入端与时钟数据信号端耦接，所述第四延迟单元的输出端与所述第二数据产生链路耦接；所述第三延迟单元和所述第四延迟单元之间具有第一节点；
    所述第一电容和所述第一开关串联耦接于所述第一节点与参考地电压端之间，所述第二电容和所述第二开关串联耦接于所述第一节点与所述参考地电压端之间；所述第一开关的控制端与第一信号输出端耦接，所述第二开关用于接收第二信号输出端的反向信号。
  15. 根据权利要求13或14所述的抖动限幅电路，其特征在于，所述电源噪声检测电路包括第三采样比较器和第四采样比较器；
    所述抖动限幅电路还包括第二抖动补偿电路，所述第二抖动补偿电路与所述第一抖动补偿电路串联，所述第二抖动补偿电路还与所述电源噪声检测电路耦接，用于根据逻辑处理器对第三采样比较器和第四采样比较器的采样比较结果的输出，反向补偿所述第一抖动补偿电路输出的数据的相位。
  16. 根据权利要求13-15任一项所述的抖动限幅电路，其特征在于，所述抖动限幅电路包括多条并联的所述第二数据产生链路。
  17. 一种电子设备，其特征在于，包括权利要求13-16任一项所述的抖动限幅电路和电路板，所述抖动限幅电路与所述电路板耦接。
  18. 一种电源噪声检测电路的工作方法，其特征在于，包括：
    第一数据产生链路工作在噪声电源电压，输出噪声信号；第一数据产生链路还工作在降噪电源电压下，输出降噪信号；
    采样比较电路对所述第一数据产生链路输出的所述噪声信号的相位和所述降噪信号的相位进行采样比较；
    逻辑处理器对所述采样比较电路的采样比较结果进行逻辑处理，并输出处理结果。
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