WO2024087694A1 - 鉴相器及其工作方法、时钟与数据恢复电路、电子设备 - Google Patents

鉴相器及其工作方法、时钟与数据恢复电路、电子设备 Download PDF

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Publication number
WO2024087694A1
WO2024087694A1 PCT/CN2023/103186 CN2023103186W WO2024087694A1 WO 2024087694 A1 WO2024087694 A1 WO 2024087694A1 CN 2023103186 W CN2023103186 W CN 2023103186W WO 2024087694 A1 WO2024087694 A1 WO 2024087694A1
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Prior art keywords
data
sampling
integrator
clock
sampling clock
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PCT/CN2023/103186
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English (en)
French (fr)
Inventor
陈焱沁
王晓婷
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华为技术有限公司
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Publication of WO2024087694A1 publication Critical patent/WO2024087694A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular to a phase detector and a working method thereof, a clock and data recovery circuit, and an electronic device.
  • the transceiver circuit In serial data communication transmission, the transceiver circuit is responsible for converting internal parallel data with external serial data.
  • the principle of high-speed clock sampling is used to send the bit data in the parallel data to the transmission medium one by one to achieve parallel to serial conversion.
  • the receiving end since the transmitting end and the receiving end do not have a shared clock signal for data synchronization, the receiving end needs to recover the clock signal from the received serial data stream to achieve synchronous operation, and the clock and data recovery circuit (CDR) is responsible for extracting the recovered clock and recovered data from the serial data.
  • the serial-to-parallel circuit at the subsequent stage then converts the recovered data into parallel data output, and can also determine the characteristic code pattern of the input serial data to achieve byte synchronization.
  • phase detector In the CDR circuit, a phase detector is needed to determine the phase relationship between the recovered clock signal and the data symbol, so as to adjust the clock signal through the feedback loop to obtain the best rising edge. Therefore, the performance of the phase detector has a crucial impact on the accuracy of the CDR circuit.
  • the embodiments of the present application provide a phase detector and a working method thereof, a clock and data recovery circuit, and an electronic device, which are used to solve the problem of how to improve the performance of the phase detector.
  • a phase detector including: a data integrator, coupled to both a data input terminal and a sampling clock terminal, and used to integrate input data of the data input terminal according to a sampling clock of the sampling clock terminal; a data sampling comparator, coupled to the data integrator, and used to sample and compare the output of the data integrator with a set value; a transition edge integrator, coupled to both a data input terminal and a sampling clock terminal, and used to integrate the input data according to the sampling clock of the sampling clock terminal; a transition edge sampling comparator, coupled to the transition edge integrator, and used to sample and compare the output of the transition edge integrator with the set value; a logic processor, coupled to both the data sampling comparator and the transition edge sampling comparator, and used to perform logic processing on a comparison result of the data sampling comparator and a comparison result of the transition edge sampling comparator, and output the processing result.
  • the sampling of the data segment of the data stream input at the data input end is equivalently completed by the data integrator, and the sampling of the transition edge of the data stream is equivalently completed by the transition edge integrator.
  • the sampling period of the sampling clock is equal to one UI
  • the sampling rate of the phase detector is equal to the baud rate, which can effectively reduce the power consumption of the phase detector and improve the performance of the phase detector.
  • a data integrator is provided on the data sampling comparator branch
  • a transition edge integrator is provided on the transition edge sampling comparator branch.
  • the delay and non-ideality introduced by the data integrator and the delay and non-ideality introduced by the transition edge integrator can offset each other, so as to improve the problem of reduced jitter tolerance caused by the introduction of the integrator, improve the jitter tolerance of the phase detector, and further improve the performance of the phase detector.
  • the phase detector further includes a clock delayer; the sampling clock end, the data integrator, and the transition edge integrator are all coupled to the clock delayer, and the clock delayer is used to receive the sampling clock from the sampling clock end and output a delayed sampling clock.
  • the phase detector provided in the embodiment of the present application requires the use of a sampling clock and a delayed sampling clock, but by setting a clock delayer, the clock delayer outputs a delayed sampling clock. It can be achieved that only an external system needs to provide a sampling clock to the sampling clock end.
  • the gain problem caused by the delayed sampling clock output by the clock delayer can be offset by the gain of the data integrator and the transition edge integrator to improve the performance of the phase detector.
  • the data integrator is used to start from the Nth rising edge of the sampling clock to the delayed sampling clock
  • the transition edge integrator is used to integrate the input data of the data input terminal from the Nth rising edge of the delayed sampling clock to the N+1th rising edge of the sampling clock; N is a positive integer.
  • the data integrator is used to integrate the input data of the data input terminal from the N-1th rising edge of the delayed sampling clock to the Nth rising edge of the sampling clock;
  • the transition edge integrator is used to integrate the input data of the data input terminal from the Nth rising edge of the sampling clock to the Nth rising edge of the sampling clock;
  • N is a positive integer.
  • the data integrator and the transition edge integrator have the same structure, which can simplify the circuit structure and make the gains of the two similar.
  • the phase detector further includes a gain controller; the gain controller is coupled to the transition edge integrator and is used to output a bias current to the transition edge integrator.
  • the gain controller can perform gain compensation on the transition edge integrator, so that the gain of the data integrator and the gain of the transition edge integrator are as equal as possible, so as to offset the delay and non-ideality introduced by the data integrator and the delay and non-ideality introduced by the transition edge integrator as much as possible, thereby improving the performance of the phase detector.
  • the gain controller includes an operational amplifier, an inverter, a first transistor, a second transistor, a first switch, a second switch and a capacitor; the input terminal of the operational amplifier is coupled to the reference voltage terminal, the other input terminal of the operational amplifier is coupled to the first node, and the output terminal of the operational amplifier is coupled to the gate of the first transistor; the first electrode of the first transistor is coupled to the first voltage terminal, and the second electrode of the first transistor is coupled to the first node; the gate of the second transistor is coupled to the output terminal of the operational amplifier, the first electrode of the second transistor is coupled to the first voltage terminal, and the second electrode of the second transistor is coupled to the transition edge integrator; the first switch is coupled between the first node and the second node; the control terminal of the first switch is coupled to the sampling clock terminal; the input terminal of the inverter is coupled to the sampling clock terminal, and the output terminal of the inverter is coupled to the control terminal of the second switch; the second switch and the capacitor are coupled in parallel between the second node and
  • the clock delay device includes a buffer, which is a simple implementation.
  • the logic processor has a first output terminal and a second output terminal; the logic processor is used to output a digital signal from the first output terminal, indicating that the phase of the sampling clock leads the phase of the input data; the logic processor is used to output a digital signal from the second output terminal, indicating that the phase of the sampling clock lags the phase of the input data.
  • the value is set to 0. This is an implementation with a simple structure.
  • a clock and data recovery circuit comprising a phase detector and a charge pump, wherein the phase detector is the phase detector of any one of the first aspects, and the phase detector is coupled to the charge pump.
  • the clock and data recovery circuit provided in the second aspect of the embodiment of the present application includes the phase detector of any one of the first aspects, and its beneficial effects are the same as those of the phase detector, which will not be repeated here.
  • an electronic device including a driver chip and a clock and data recovery circuit; the clock and data recovery circuit is arranged in the driver chip; the clock and data recovery circuit is the clock and data recovery circuit of the second aspect.
  • a working method of a phase detector comprising: a data integrator integrates input data of a data input terminal; a data sampling comparator samples and compares an output of the data integrator with a set value; a transition edge integrator integrates the input data; a transition edge sampling comparator samples and compares the output of the transition edge integrator with a set value; a logic processor performs logic processing on a comparison result of the data sampling comparator and a comparison result of the transition edge sampling comparator, and outputs the processing result.
  • the working method of the phase detector provided in the fourth aspect of the embodiment of the present application has the same beneficial effects as the beneficial effects of the phase detector, which will not be repeated here.
  • FIG1A is a schematic diagram of a framework of an electronic device provided in an embodiment of the present application.
  • FIG1B is a schematic diagram of the layout of an electronic device provided in an embodiment of the present application.
  • FIG1C is a schematic diagram of a source driving circuit according to an embodiment of the present application.
  • FIG1D is a schematic diagram of a clock and data recovery circuit according to an embodiment of the present application.
  • FIG2A is a schematic diagram of a phase detector according to an embodiment of the present application.
  • FIG. 2B and 2C are schematic diagrams of the principle of the phase detector shown in FIG. 2A according to an embodiment of the present application;
  • FIG3A is a schematic diagram of a framework of a phase detector provided in an embodiment of the present application.
  • FIG3B is a schematic diagram of an integrator provided in an embodiment of the present application.
  • FIG3C is a schematic diagram of the principle of the phase detector shown in FIG2A provided in an embodiment of the present application;
  • FIG3D is a schematic diagram of another principle of a phase detector according to an embodiment of the present application.
  • FIG4A is a schematic diagram of the structure of a phase detector provided in an embodiment of the present application.
  • FIG4B is a schematic diagram of the structure of another phase detector provided in an embodiment of the present application.
  • FIG5A is a schematic diagram of a phase detector provided in an embodiment of the present application.
  • FIG5B is a schematic diagram of jitter tolerance of a phase detector provided in an embodiment of the present application.
  • FIG5C is a schematic diagram of another principle of a phase detector provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of another phase detector provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the structure of a gain controller provided in an embodiment of the present application.
  • directional terms such as “up”, “down”, “left” and “right” may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • coupled can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • contact can be a direct contact or an indirect contact through an intermediate medium.
  • a and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • Clock and data recovery circuit Recover the corresponding frequency clock based on the input data, and then use this clock to sample the data.
  • Phase detector is a circuit used in clock and data recovery circuit to identify the phase difference between sampling clock and input data.
  • Baud rate For the data within the scope of discussion of the embodiments of this application, the baud rate is the data transmission rate, such as 3Gb/S corresponds to a baud rate of 3Gb/S.
  • Baud rate sampling phase detector refers to a phase detector whose sampling rate is equal to the baud rate of the input data.
  • BANG BANG phase detector (BBPD): The name of the most traditional phase detector circuit, whose sampling rate is twice the baud rate.
  • Sampling comparator Its behavior is roughly to compare the input signal with 0 when the rising edge of the input clock arrives. If the input is greater than 0, the output is a high level, and if the input is less than 0, the output is a low level.
  • UI unit interval: refers to the smallest interval unit of data transmission.
  • the UI of a 3Gb/S data rate is 333.3333pS.
  • Non-ideality includes the integrator's clock injection, clock feedthrough, charge sharing, nonlinearity, setup time, etc. These factors can actually be equivalent to the integrator's delay.
  • Jitter tolerance It is a core indicator for measuring the performance of data recovery circuits. It generally refers to how much jitter the circuit can tolerate in the data. Generally speaking, if the jitter is so large that the sampling clock falls on the transition edge of the data, it is considered that the circuit sampling has been erroneous.
  • Buffer and inverter Both are the most basic digital logic processors. The output and input of the buffer remain in the same direction, while the input and output of the inverter are in opposite directions.
  • Negative feedback refers to the system reducing the sampling error through feedback. In the clock data recovery circuit, it is manifested as the sampling clock phase is close to the ideal position through feedback.
  • the present application provides an electronic device.
  • the electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, an electronic device for video transmission, etc.
  • a consumer electronic product such as a mobile phone
  • mobile phone tablet computer (pad), laptop computer, e-reader, personal computer (PC), personal digital assistant (PDA), desktop display, smart wearable products (e.g., smart watch, smart bracelet), virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, drone, etc.
  • Home electronic products include smart door locks, TV, remote control, refrigerator, rechargeable small household appliances (e.g., soybean milk machine, sweeping robot), etc.
  • Car-mounted electronic products include car navigation system, car high-density digital video disc (DVD), etc.
  • Financial terminal products include automated teller machine (ATM), self-service terminals, etc.
  • Video transmission electronic devices include network video recorders (NVR), digital video recorders (DVR), digital video recorders (XVR), encoders (DVS), all-in-one machines, industrial computers, gateways, industry hosts and other back-end products. Electronic devices can also be electronic devices with audio/video transmission requirements such as set-top boxes.
  • the electronic device is taken as a tablet computer as an example.
  • the electronic device 1 mainly includes a cover plate 11, a display panel 12, a middle frame 13 and a rear shell 14.
  • the rear shell 14 and the display panel 12 are respectively located on both sides of the middle frame 13, and the middle frame 13 and the display panel 12 are arranged in the rear shell 14, the cover plate 11 is arranged on the side of the display panel 12 away from the middle frame 13, and the display surface of the display panel 12 faces the cover plate 11.
  • the display panel 12 may be a liquid crystal display (LCD).
  • the liquid crystal display includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is disposed between the cover plate 11 and the backlight module.
  • the backlight module is used to provide a light source for the liquid crystal display panel.
  • the display panel 12 may also be an organic light emitting diode (OLED) display. Since the OLED display is a self-luminous display, there is no need to set a backlight module.
  • OLED organic light emitting diode
  • the middle frame 13 includes a carrier plate 131 and a frame 132 surrounding the carrier plate 131.
  • the electronic device 1 may also include electronic components such as printed circuit boards (PCB), batteries, and cameras, and the printed circuit boards, batteries, and cameras may be arranged on the carrier plate 131.
  • PCB printed circuit boards
  • the display panel 12 includes an active display area (AA) A and a peripheral area B located around the active display area A.
  • the effective display area A of the display panel 12 serves as the display area of the electronic device 1
  • the peripheral area B of the display panel 12 serves as the non-display area of the electronic device 1 .
  • the effective display area A of the display panel 12 includes a plurality of sub-pixels P.
  • the plurality of sub-pixels P are described in the present application by taking a matrix arrangement as an example.
  • the sub-pixels P arranged in a row along the horizontal direction are called sub-pixels in the same row
  • the sub-pixels P arranged in a row along the vertical direction are called sub-pixels in the same column.
  • the electronic device 1 includes a gate driving circuit and a source driving circuit located in the peripheral area B of the display panel 12.
  • the gate driving circuit is used to provide a gate driving signal for the sub-pixel P
  • the source driving circuit is used to provide a source driving signal for the sub-pixel P.
  • the gate driving circuit can be integrated in the display panel 12 using a gate on array (GOA) technology.
  • the gate driving circuit includes a plurality of cascaded shift registers (SR).
  • the gate driving circuit may include one or more gate driving circuits.
  • the electronic device 1 includes two gate driving circuits, and the two gate driving circuits are arranged on both sides of the effective display area A along the horizontal direction.
  • the source driver circuit may be integrated in a display driver integrated circuit (DDIC), for example.
  • DDIC display driver integrated circuit
  • the driver chip DDIC is directly attached to the display panel 12 in the form of a bare chip (die).
  • the electronic device also includes a timing controller (TCON), which, in some embodiments, as shown in FIG. 1B , is disposed on a flexible printed circuit (FPC).
  • TCON timing controller
  • FPC flexible printed circuit
  • the source driving circuit includes a receiving circuit and a data output circuit.
  • the receiving circuit may receive input data td provided from the timing controller TCON shown in FIG1B , and may restore a data signal dt and a clock signal ck.
  • the data output circuit may convert the data signal dt into a data driving signal d in synchronization with the clock signal ck, and apply the data driving signal d to the sub-pixel P shown in FIG. 1B .
  • the receiving circuit includes a clock and data recovery circuit CDR, which can recover a clock signal ck and a data signal dt according to a transmission signal td.
  • the clock and data recovery circuit CDR includes a data recovery circuit and a clock recovery circuit.
  • the clock recovery circuit can receive input data td and output a clock signal ck.
  • the data recovery circuit can receive input data td and recover the data signal dt synchronously with the clock signal ck to the data signal dt.
  • the clock recovery circuit includes a phase detector 20, a charge pump, a loop filter and a voltage controlled oscillator VCO.
  • the phase detector 20 may detect the phase difference between the data signal dt and the clock signal ck and output a phase difference signal PD.
  • the charge pump may output a bias current control signal in response to the phase difference signal PD from the phase detector 20.
  • the loop filter may output a voltage control signal corresponding to the current control signal.
  • the voltage controlled oscillator VCO may output a clock signal ck having a frequency corresponding to the voltage level of the voltage control signal.
  • CDR Low-power clock and data recovery circuits
  • commonly used phase detectors include BANG BANG phase detectors and baud rate sampling phase detectors.
  • the BANG BANG phase detector includes a data sampling comparator, a transition edge sampling comparator, and a logic controller.
  • the data sampling comparator and the transition edge sampling comparator are both coupled to the logic controller.
  • the system generates sampling clock 1 and sampling clock 2, and sampling clock 1 and sampling clock 2 are used to sample data and transition edges, respectively.
  • the logic controller performs an XOR operation based on the sampling results of sampling clock 1 and sampling clock 2 to obtain the phase relationship between the current sampling clock and the input data (divided into two phase relationships: leading and lagging).
  • sampling clock 1 and sampling clock 2 are separated by half a UI.
  • Sampling clock 1 is used to drive data sampling
  • sampling clock 2 is used to drive transition edge sampling.
  • the rising edges of sampling clock 1 and sampling clock 2 can be used for sampling.
  • Sampling clock 1 ⁇ N> represented by a dotted line represents the ⁇ N>th rising edge of sampling clock 1
  • sampling clock 2 ⁇ N-1> represented by a solid line represents the ⁇ N-1>th rising edge of sampling clock 2.
  • Sampling clock 2 ⁇ N> represented by a dotted line represents the ⁇ N>th rising edge of sampling clock 2.
  • the ideal sampling position of sampling clock 1 should be in the middle of a UI, because at this time the distance between sampling clock 1 and the data transition edges on both sides is the farthest, and it is also the least prone to error.
  • sampling clock 1 when sampling clock 1 lags behind the ideal sampling position, the sampling results of sampling clock 1 ⁇ N> and sampling clock 2 ⁇ N> will be different, and the logic processor will judge the lag accordingly.
  • FIG2C when sampling clock 1 is ahead of the ideal sampling position, the sampling results of sampling clock 1 ⁇ N> and sampling clock 2 ⁇ N-1> will be different, and the logic processor will judge the advance accordingly.
  • sampling clock 1 falls at the ideal position, sampling clock 2 will fall exactly at the data transition edge position, and the sampling result will be random, that is, the logic processor will randomly judge whether it is ahead or behind, and as a result, the system will oscillate back and forth between ahead and behind.
  • the sampling rate of the phase detector is twice the baud rate, resulting in higher power consumption of the phase detector.
  • an embodiment of the present application provides a phase detector 20, as shown in FIG3A, the phase detector 20 includes an integrator, a data sampling comparator, a transition edge sampling comparator, and a logic controller.
  • the integrator is coupled to the data sampling comparator, and the data sampling comparator and the transition edge sampling comparator are both coupled to the logic controller.
  • the system generates a sampling clock, and the sampling clock is used to sample data and transition edges.
  • the sampling clock has a first rising edge CKPRE and a second rising edge CKPOST.
  • the first rising edge CKPRE is the current rising edge of the sampling clock
  • the second rising edge CKPOST is the rising edge of the next cycle of the sampling clock.
  • the integrator starts integrating the input data at the first rising edge CKPRE and stops integrating at the second rising edge CKPOST.
  • the integrator output voltage V O falls on the first rising edge CKPRE and the second rising edge when the input data jumps.
  • I is the integrator bias current and C O is the integrator output capacitance.
  • V is the input data differential amplitude
  • the integrator output is proportional to the input average voltage, and its gain G is:
  • phase detector The specific implementation principle of the phase detector is as follows:
  • the sampling clock directly drives the data transition edge sampler, and its ideal position is in the middle of the data transition edge.
  • the ⁇ N>th and ⁇ N+1>th rising edges of the sampling clock jointly drive the integrator.
  • the integrator starts integrating, and when the ⁇ N+1>th rising edge of the sampling clock arrives, the integrator stops integrating.
  • the output of the integrator will be proportional to the average value of the input data between the ⁇ N>th rising edge of the sampling clock and the ⁇ N+1>th rising edge of the sampling clock. It can also be considered that the integral equivalent sampling position is at the dotted line position in FIG3C .
  • the logic controller performs an XOR operation based on the ⁇ N>th and ⁇ N+1>th rising edges of the sampling clock and the sampling result of the equivalent sampling clock to obtain the phase relationship between the current sampling clock and the input data (divided into two phase relationships: leading and lagging).
  • the sampling period of the sampling clock is equal to one UI, so the sampling rate of the phase detector is equal to the baud rate, which can reduce power consumption.
  • the phase detector 20 includes a data integrator 21 , a data sampling comparator 22 , a transition edge integrator 23 , a transition edge sampling comparator 24 and a logic processor 25 .
  • the data integrator 21 is coupled to both the data input terminal TD and the sampling clock terminal CK, and is used to integrate the input data of the data input terminal TD.
  • the data stream input by the data input terminal TD may be a data signal, and the data stream input by the data input terminal TD may also be a clock signal.
  • the data integrator 21 integrates the data stream inputted from the data input terminal TD under the control of the sampling clock of the sampling clock terminal CK. During the effective integration period of the data integrator 21, the data integrated by the data integrator 21 does not contain the transition edge of the data stream. The output of the data integrator 21 is equivalent to the data at the middle position of the data segment inputted to the data integrator 21 during the effective integration period of the data integrator 21.
  • the data integrator 21 is equivalent to completing the sampling of the data segment in the data stream input by the data input terminal TD.
  • the data sampling comparator 22 is coupled to the data integrator 21 and the sampling clock terminal CK, and is used for sampling and comparing the output of the data integrator 21 with a set value according to the sampling clock of the sampling clock terminal CK.
  • the set value is an intermediate value of the differential data outputted from the data input terminal TD.
  • the set value is 0.
  • the transition edge integrator 23 is coupled to both the data input terminal TD and the sampling clock terminal CK, and is used for integrating the input data of the data input terminal TD.
  • the transition edge integrator 23 integrates the data stream input from the data input terminal TD under the control of the sampling clock of the sampling clock terminal CK. During the effective integration period of the transition edge integrator 23, the data integrated by the transition edge integrator 23 includes the transition edge of the data stream. The output of the transition edge integrator 23 is equivalent to the data at the middle position of the data segment input to the transition edge integrator 23 during the effective integration period of the transition edge integrator 23.
  • the transition edge integrator 23 is equivalent to completing the sampling of the transition edge in the data stream input by the data input terminal TD.
  • the structure of the data integrator 21 is the same as that of the transition edge integrator 23 , and the data integrator 21 and the transition edge integrator 23 are used to integrate data in different time periods of the data stream.
  • the transition edge sampling comparator 24 is coupled to the transition edge integrator 23 and the sampling clock terminal CK, and is used for sampling and comparing the output of the transition edge integrator 23 with a set value according to the sampling clock of the sampling clock terminal CK.
  • the output end of the data sampling comparator 22 and the output end of the transition edge sampling comparator 24 are coupled to the logic processor 25 for performing logic processing on the comparison results of the data sampling comparator 22 and the comparison results of the transition edge sampling comparator 24 and outputting the processing results.
  • the logic processor 25 outputs a first signal and a second signal, wherein the first signal indicates that the phase of the sampling clock at the sampling clock terminal CK leads the phase of the input data at the data input terminal TD, and the second signal indicates that the phase of the sampling clock lags the phase of the input data at the data input terminal TD.
  • the sampling of the data segment of the data stream input at the data input terminal TD is equivalently completed by the data integrator 21, and the sampling of the transition edge of the data stream is equivalently completed by the transition edge integrator 23.
  • the external system only needs to provide a sampling clock to the sampling clock terminal CK.
  • the sampling period of the sampling clock is equal to one UI
  • the sampling rate of the phase detector is equal to the baud rate, which can effectively reduce the power consumption of the phase detector 20 and improve the performance of the phase detector 20.
  • a data integrator 21 is provided on the branch of the data sampling comparator 22, and a transition edge integrator 23 is provided on the branch of the transition edge sampling comparator 24.
  • the gains of the data integrator 21 and the transition edge integrator 23 will introduce delay and non-ideality of the output result
  • the delay and non-ideality introduced by the data integrator 21 and the delay and non-ideality introduced by the transition edge integrator 23 can offset each other, so as to improve the problem of reduced jitter tolerance caused by the introduction of the integrator, improve the jitter tolerance of the phase detector 20, and further improve the performance of the phase detector 20.
  • the phase detector 20 further includes a clock delay 26 .
  • the sampling clock terminal CK, the data integrator 21 and the transition edge integrator 23 are all coupled to the clock delayer 26.
  • the clock delayer 26 is used for receiving the sampling clock of the sampling clock terminal CK and outputting a delayed sampling clock.
  • the data integrator 21 integrates the data stream input from the data input terminal TD under the control of the sampling clock of the sampling clock terminal CK and the delayed sampling clock output from the clock delayer 26.
  • the transition edge integrator 23 integrates the data stream input from the data input terminal TD under the control of the sampling clock of the sampling clock terminal CK and the delayed sampling clock output from the clock delayer 26. Both the data integrator 21 and the transition edge integrator 23 are controlled by the sampling clock and the delayed sampling clock.
  • the clock delay 26 includes a buffer.
  • a clock delayer 26 is provided so that the clock delayer 26 outputs a delayed sampling clock. It can be achieved that only an external system needs to provide a sampling clock to the sampling clock terminal CK.
  • the gain problem caused by the output of the delayed sampling clock by the clock delayer 26 can be offset by the gain of the data integrator 21 and the transition edge integrator 23 to improve the performance of the phase detector 20.
  • phase detector 20 is controlled by a sampling clock and a delayed sampling clock.
  • the data integrator 21 is used to integrate the input data of the data input terminal TD from the Nth rising edge of the sampling clock to the Nth rising edge of the delayed sampling clock, where N is a positive integer.
  • the data sampling comparator 22 samples the equivalent data of the input data at a position between the Nth rising edge of the sampling clock and the Nth rising edge of the delayed sampling clock.
  • the transition edge integrator 23 is used to integrate the input data of the data input terminal TD from the Nth rising edge of the delayed sampling clock to the N+1th rising edge of the sampling clock.
  • the transition sampling integrator 23 samples the equivalent transition edge of the input data at a position between the Nth rising edge of the delayed sampling clock and the N+1th rising edge of the sampling clock.
  • t ⁇ N> is the Nth rising edge time of the sampling clock
  • t ⁇ N+1> is the N+1th rising edge time of the sampling clock
  • t del ⁇ N> is the Nth rising edge time of the delayed sampling clock
  • tdel is the delay time between the delayed sampling clocks.
  • the actual equivalent data sampling position is offset by a delay relative to the theoretical equivalent data sampling position
  • the actual equivalent transition edge sampling position is offset by a delay relative to the theoretical equivalent transition edge sampling position.
  • the transition edge sampling position after the offset will be aligned with the data transition edge, and the equivalent data sampling moment and the equivalent transition edge sampling moment differ by UI/2, and the data sampling position will still fall in the middle of one UI.
  • the actual jitter tolerance is equal to the theoretical jitter tolerance. Therefore, the phase detector 20 provided in the embodiment of the present application will not reduce the jitter tolerance.
  • the sampling of the output of the data integrator 21 by the data sampling comparator 22 is equivalent to the sampling of the input data by the data sampling comparator 22 at the equivalent data sampling position in FIG. 5A .
  • the data sampling comparator 22 compares the sampled data with a set value, for example, the set value is 0. Then, when the sampled data is greater than 0, the data sampling comparator 22 outputs a digital signal 1. When the sampled data is less than 0, the data sampling comparator 22 outputs a digital signal 0.
  • the sampling of the output of the transition edge integrator 23 by the transition edge sampling comparator 24 is equivalent to the sampling of the input data by the transition edge sampling comparator 24 at the equivalent transition edge sampling position in FIG. 5A .
  • the transition edge sampling comparator 24 compares the sampled data with the set value. For example, when the sampled data is greater than 0, the transition edge sampling comparator 24 outputs a digital signal 1. When the sampled data is less than 0, the transition edge sampling comparator 24 outputs a digital signal 0.
  • the signal output by the data sampling comparator 22 to the logic processor 25 is a digital signal 0 or a digital signal 1
  • the signal output by the transition edge sampling comparator 24 to the logic processor 25 is also a digital signal 0 or a digital signal 1.
  • the logic processor 25 is used to perform logic processing on the comparison result of the data sampling comparator 22 and the comparison result of the transition edge sampling comparator 24, and output the processing result.
  • the logic processor 25 has a first output terminal and a second output terminal.
  • the sampling comparison result (e.g., 1) output by the data sampling comparator 22 is different from the sampling result (e.g., 0) output by the transition edge sampling comparator 24 at the Nth rising edge of the delayed sampling clock;
  • the sampling result (e.g., 1) output by the transition edge sampling comparator 24 at the Nth rising edge of the delayed sampling clock is the same as the sampling comparison result (e.g., 1) output by the data sampling comparator 22 at the N+1th rising edge of the sampling clock; and the logic judgment is always such a judgment result.
  • the logic processor 25 outputs a digital signal (e.g., digital signal 1) from the first output terminal, indicating that the phase of the sampling clock is ahead of the phase of the input data.
  • the first output terminal of the logic processor 25 continuously outputs 1
  • the second output terminal of the logic processor 25 continuously outputs 0.
  • the sampling result (e.g., 0) output by the transition edge sampling comparator 24 is different from the sampling comparison result (e.g., 1) output by the data sampling comparator 22 at the N+1th rising edge of the sampling clock.
  • the sampling comparison result (e.g., 0) output by the data sampling comparator 22 is the same as the sampling result (e.g., 0) output by the transition edge sampling comparator 24 at the Nth rising edge of the delayed sampling clock; and the logic judgment is always such a judgment result.
  • the logic processor 25 outputs a digital signal (e.g., digital signal 1) from the second output terminal, indicating that the phase of the sampling clock lags behind the phase of the input data.
  • a digital signal e.g., digital signal 1
  • the first output terminal of the logic processor 25 continuously outputs 0, and the second output terminal of the logic processor 25 continuously outputs 1.
  • sampling comparison result (e.g., 1) output by the data sampling comparator 22 at the Nth rising edge of the sampling clock
  • the sampling result e.g., 0
  • the sampling result (e.g., 0) output by the transition edge sampling comparator 24 at the Nth rising edge of the delayed sampling clock is the same as the sampling comparison result (e.g., 0) output by the data sampling comparator 22 at the N+1th rising edge of the sampling clock, indicating that the comparison result is advanced.
  • the sampling result (e.g., 1) output by the transition edge sampling comparator 24 at the N+1th rising edge of the delayed sampling clock is different from the sampling comparison result (e.g., 0) output by the data sampling comparator 22 at the N+2th rising edge of the sampling clock.
  • the sampling comparison result (e.g., 1) output by the data sampling comparator 22 at the N+1th rising edge of the sampling clock is the same as the sampling result (e.g., 1) output by the transition edge sampling comparator 24 at the N+1th rising edge of the delayed sampling clock, indicating that the comparison result is delayed.
  • this comparison result oscillates back and forth between advance and lag, it indicates that the jitter of the phase of the sampling clock relative to the phase of the input data is within the tolerance range.
  • the output of the logic processor 25 is: the first output terminal outputs 1, the second output terminal outputs 0; the first output terminal outputs 0, the second output terminal outputs 1. The output oscillates back and forth in this way.
  • the logic processor 25 outputs the first signal, indicating that the phase of the sampling clock is ahead of the phase of the input data.
  • the digital signal 0 is continuously output from the first output terminal, and the digital signal 1 is continuously output from the second output terminal, which means that the logic processor 25 outputs the second signal, indicating that the phase of the sampling clock lags behind the phase of the input data.
  • the first output terminal outputs 1, and the second output terminal outputs 0; the first output terminal outputs 0, and the second output terminal outputs 1.
  • This alternating oscillation output indicates that the logic processor 25 outputs the third signal, indicating that the jitter of the sampling clock phase relative to the input data phase is within the tolerance range.
  • the data integrator 21 may also integrate the input data of the data input terminal TD starting from the N ⁇ 1th rising edge of the delayed sampling clock to the Nth rising edge of the sampling clock.
  • the transition edge integrator 23 integrates the input data of the data input terminal TD from the Nth rising edge of the sampling clock to the Nth rising edge of the sampling clock.
  • the phase detector 20 further includes a gain controller 27 ; the gain controller 27 is coupled to the transition edge integrator 23 and is configured to output a bias current to the transition edge integrator 23 .
  • the structure of the data integrator 21 is the same as that of the transition edge integrator 23 .
  • the structure of the data integrator 21 is equal to C O and V of the transition edge integrator 23.
  • the delay time tdel of the data integrator 21 is the delay time of the clock delayer 26, which is controlled by the structure of the clock delayer 26.
  • the delay time tdel of the data integrator 21 is a fixed value.
  • the delay time tdel of the transition edge integrator 23 is a UI, and the UI is limited by the input data of the data input terminal TD. Even if the structure of the phase detector 20 is fixed, the delay time tdel of the transition edge integrator 23 is a variable as the input data is different. This will cause the gain G21 of the data integrator 21 and the gain G23 of the transition edge integrator 23 to be unequal.
  • the gain controller 27 By setting the gain controller 27, the gain controller 27 generates a bias current I1 proportional to the sampling clock frequency FREQ (ie, 1/UI) and provides it to the transition edge integrator 23.
  • the gain G23 of the transition edge integrator 23 is:
  • K is the ratio of the bias current I1 to the sampling clock frequency FREQ.
  • the gain G23 of the transition edge integrator 23 can be made as follows:
  • the gain controller 27 can perform gain compensation on the transition edge integrator 23, so that the gain G21 of the data integrator 21 and the gain G23 of the transition edge integrator 23 are as equal as possible, so as to minimize the The delay and non-ideality introduced by the data integrator 21 and the delay and non-ideality introduced by the transition edge integrator 23 cancel each other out, thereby improving the performance of the phase detector 20 .
  • the gain controller 27 includes an operational amplifier OP, an inverter, a first transistor M1, a second transistor M2, a first switch SW1, a second switch SW2, and a capacitor;
  • An input terminal of the operational amplifier OP is coupled to the reference voltage terminal VREF, another input terminal of the operational amplifier OP is coupled to the first node Z1 , and an output terminal of the operational amplifier OP is coupled to the gate of the first transistor M1 .
  • a first electrode of the first transistor M1 is coupled to the first voltage terminal V1 , and a second electrode of the first transistor M1 is coupled to the first node Z1 .
  • a gate of the second transistor M2 is coupled to the output terminal of the operational amplifier OP, a first electrode of the second transistor M2 is coupled to the first voltage terminal V1 , and a second electrode of the second transistor M2 is coupled to the transition edge integrator 23 .
  • the first switch SW1 is coupled between the first node Z1 and the second node Z2 ; a control terminal of the first switch SW1 is coupled to the sampling clock terminal CK.
  • the input terminal of the inverter is coupled to the sampling clock terminal CK, and the output terminal of the inverter is coupled to the control terminal of the second switch SW2; the second switch SW2 and the capacitor C are coupled in parallel between the second node Z2 and the second voltage terminal V2.
  • the first voltage terminal V1 may be, for example, a power supply voltage terminal
  • the second voltage terminal V2 may be, for example, a reference ground voltage terminal.
  • the structure of the gain controller 27 in the embodiment of the present application is not limited to the structure shown in Figure 7. Any structure that can realize the function of the gain controller 27, or a structure with the same implementation principle as the structure shown in Figure 7, belongs to the protection scope of the embodiment of the present application.
  • the gain controller 27 may include a transistor connected in series or in parallel with the first transistor M1, the gain controller 27 may include a transistor connected in series or in parallel with the second transistor M2, the gain controller 27 may include a switch connected in series or in parallel with the first switch SW1, and the gain controller 27 may include a switch connected in series or in parallel with the second switch SW2.
  • the sampling clock inputted by the sampling clock terminal CK generates an inverted sampling clock through an inverter.
  • the sampling clock is 1, the first switch SW1 is closed and the second switch SW2 is turned off.
  • the first transistor M1 transmits the signal of the first voltage terminal V1 to the capacitor C to charge the capacitor C.
  • the sampling clock is 0, the first switch SW1 is turned off and the second switch SW2 is closed, and the capacitor C is discharged to the second voltage terminal V2.
  • a resistor R can be equivalent to:
  • the operational amplifier OP maintains the first node Z1 at the voltage of the reference voltage terminal VREF through negative feedback, so the bias current I1 flowing through the first transistor M1 is:
  • the gain G23 of the transition edge integrator 23 can be made the same as the gain G21 of the data integrator 21.
  • the gain G23 of the transition edge integrator 23 can be adjusted to make the gain G23 of the transition edge integrator 23 the same as the gain G21 of the data integrator 21, so that the delay and non-ideality introduced by the data integrator 21 and the delay and non-ideality introduced by the transition edge integrator 23 are symmetrical and offset each other, so as to improve the problem of reduced jitter tolerance caused by the introduction of the integrator, improve the jitter tolerance of the phase detector 20, and further enhance the performance of the phase detector 20.

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Abstract

本申请实施例提供一种鉴相器及其工作方法、时钟与数据恢复电路、电子设备，涉及集成电路技术领域，用于解决如何提高鉴相器性能的问题。鉴相器包括数据积分器，与采样时钟端均耦接，用于根据采样时钟端的信号，对输入数据进行积分；数据采样比较器，用于将数据积分器的输出与设定值进行采样比较；跳变沿积分器；与采样时钟端耦接，用于根据采样时钟端的信号，对输入数据进行积分；跳变沿采样比较器；用于将跳变沿积分器的输出与设定值进行采样比较；逻辑处理器，用于对数据采样比较器的比较结果和跳变沿采样比较器的比较结果进行逻辑处理，并输出超前滞后的处理结果。

Description

鉴相器及其工作方法、时钟与数据恢复电路、电子设备
本申请要求于2022年10月25日提交国家知识产权局、申请号为202211314210.9、发明名称为“鉴相器及其工作方法、时钟与数据恢复电路、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种鉴相器及其工作方法、时钟与数据恢复电路、电子设备。
背景技术
在串行数据通信传输中，收发电路负责将内部并行数据与外部串行数据进行转换。在发送端，利用高速时钟采样的原理，将并行数据中的位数据逐个送到传输介质上，实现并行到串行的转换。而在接收端，由于发送端与接收端没有共享的时钟信号进行数据的同步，接收端需要从接收到的串行数据流中恢复出时钟信号以实现同步操作，而时钟与数据恢复电路(clock and data recovery，CDR)就是负责将串行数据中的恢复时钟和恢复数据提取出来。后级的串行转并行电路再将恢复数据转换为并行数据输出，同时还可以判断输入串行数据的特征码型，实现字节同步。
在CDR电路中，需要使用鉴相器来判断所恢复的时钟信号与数据码元之间的相位关系，从而通过反馈环路对时钟信号进行调节以获得最佳上升沿。因此，鉴相器的性能对CDR电路准确性有着至关重要的影响。
发明内容
本申请实施例提供一种鉴相器及其工作方法、时钟与数据恢复电路、电子设备，用于解决如何提高鉴相器性能的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种鉴相器，包括：数据积分器，与数据输入端和采样时钟端均耦接，用于根据采样时钟端的采样时钟，对数据输入端的输入数据进行积分；数据采样比较器，与数据积分器耦接，用于将数据积分器的输出与设定值进行采样比较；跳变沿积分器；与数据输入端和采样时钟端均耦接，用于根据采样时钟端的采样时钟，对输入数据进行积分；跳变沿采样比较器；与跳变沿积分器耦接，用于将跳变沿积分器的输出与设定值进行采样比较；逻辑处理器，与数据采样比较器和跳变沿采样比较器均耦接，用于对数据采样比较器的比较结果和跳变沿采样比较器的比较结果进行逻辑处理，并输出处理结果。
本申请实施例提供的鉴相器中，对数据输入端输入的数据流的数据段的采样由数据积分器等效完成，对数据流的跳变沿的采样由跳变沿积分器等效完成。而完成数据段采样和跳变沿采样只需要外部系统向采样时钟端提供一个采样时钟即可。采样时钟的采样周期等于一个UI，鉴相器的采样率等于波特率，可以有效降低鉴相器的功耗，提升鉴相器的性能。在此基础上，数据采样比较器支路上设置有数据积分器，跳变沿采样比较器支路上设置有跳变沿积分器。虽然数据积分器和跳变沿积分器各自的增益均会引入输出结果的延迟和非理想性，但是数据积分器引入的延迟和非理想性和跳变沿积分器引入的延迟和非理想性可以相互抵消，以改善因积分器的引入所带来的抖动容忍下降的问题，提高鉴相器的抖动容忍，进一步提升鉴相器的性能。
在一种可能的实现方式中，鉴相器还包括时钟延迟器；采样时钟端、数据积分器以及跳变沿积分器均耦接于时钟延迟器，时钟延迟器用于接收采样时钟端的采样时钟，输出延迟采样时钟。本申请实施例提供的鉴相器，在一些实现方案中，虽然需要用到采样时钟和延迟采样时钟，但是通过设置时钟延迟器，由时钟延迟器输出延迟采样时钟。可以实现只需要外部系统向采样时钟端提供一个采样时钟即可。而时钟延迟器输出延迟采样时钟所带来的增益问题，可以由数据积分器和跳变沿积分器的增益来抵消，以提高鉴相器的性能。
在一种可能的实现方式中，数据积分器用于由采样时钟的第N个上升沿起始至延迟采样时钟 的第N个上升沿结束，对数据输入端的输入数据进行积分；跳变沿积分器用于由延迟采样时钟的第N个上升沿起始至采样时钟的第N+1个上升沿结束，对数据输入端的输入数据进行积分；N为正整数。这是一种结构简单的实现方式。
在一种可能的实现方式中，数据积分器用于由延迟采样时钟的第N-1个上升沿起始至采样时钟的第N个上升沿结束，对数据输入端的输入数据进行积分；跳变沿积分器用于由采样时钟的第N个上升沿起始至采样时钟的第N个上升沿结束，对数据输入端的输入数据进行积分；N为正整数。这是一种结构简单的实现方式。
在一种可能的实现方式中，数据积分器和跳变沿积分器结构相同。一方面可使电路结构简单，另一方面可使二者增益相近。
在一种可能的实现方式中，鉴相器还包括增益控制器；增益控制器与跳变沿积分器耦接，用于向跳变沿积分器输出偏置电流。通过在鉴相器中设置增益控制器，增益控制器可以对跳变沿积分器进行增益补偿，以使数据积分器的增益和跳变沿积分器的增益尽量相等，以尽可能的将数据积分器引入的延迟和非理想性和跳变沿积分器引入的延迟和非理想性相互抵消，提高鉴相器的性能。
在一种可能的实现方式中，增益控制器包括运算放大器、反相器、第一晶体管、第二晶体管、第一开关、第二开关以及电容；运算放大器的输入端与基准电压端耦接，运算放大器的另一输入端与第一节点耦接，运算放大器的输出端与第一晶体管的栅极耦接；第一晶体管的第一极与第一电压端耦接，第一晶体管的第二极与第一节点耦接；第二晶体管的栅极与运算放大器的输出端耦接，第二晶体管的第一极与第一电压端耦接，第二晶体管的第二极与跳变沿积分器耦接；第一开关耦接于第一节点与第二节点之间；第一开关的控制端与采样时钟端耦接；反相器的输入端与采样时钟端耦接，反相器的输出端与第二开关的控制端耦接；第二开关和电容并联耦接于第二节点与第二电压端之间。这是一种结构简单的实现方式。
在一种可能的实现方式中，时钟延时器包括缓冲器。这是一种结构简单的实现方式。
在一种可能的实现方式中，逻辑处理器具有第一输出端和第二输出端；逻辑处理器用于从第一输出端输出数字信号，表征采样时钟的相位相对输入数据的相位超前；逻辑处理器用于从第二输出端输出数字信号，表征采样时钟的相位相对输入数据的相位滞后。这是一种结构简单的实现方式。
在一种可能的实现方式中，设定值为0。这是一种结构简单的实现方式。
本申请实施例的第二方面，提供一种时钟与数据恢复电路，包括鉴相器和电荷泵，鉴相器为第一方面任一项的鉴相器，鉴相器与电荷泵耦接。
本申请实施例第二方面提供的时钟与数据恢复电路包括第一方面任一项的鉴相器，其有益效果与鉴相器的有益效果相同，此处不再赘述。
本申请实施例的第三方面，提供一种电子设备，包括驱动芯片和时钟与数据恢复电路；时钟与数据恢复电路设置在驱动芯片内；时钟与数据恢复电路第二方面的时钟与数据恢复电路。
本申请实施例的第四方面，提供一种鉴相器的工作方法，包括：数据积分器对数据输入端的输入数据进行积分；数据采样比较器将数据积分器的输出与设定值进行采样比较；跳变沿积分器对输入数据进行积分；跳变沿采样比较器将跳变沿积分器的输出与设定值进行采样比较；逻辑处理器对数据采样比较器的比较结果和跳变沿采样比较器的比较结果进行逻辑处理，并输出处理结果。
本申请实施例第四方面提供的鉴相器的工作方法，其有益效果与鉴相器的有益效果相同，此处不再赘述。
附图说明
图1A为本申请实施例提供的电子设备的框架示意图；
图1B为本申请实施例提供的电子设备的布局示意图；
图1C为本申请实施例提供的源极驱动电路的框架示意图；
图1D为本申请实施例提供的时钟与数据恢复电路的框架示意图；
图2A为本申请实施例示意的一种鉴相器的框架示意图；
图2B和图2C为本申请实施例示意的一种图2A所示的鉴相器的原理示意图；
图3A为本申请实施例提供的一种鉴相器的框架示意图；
图3B为本申请实施例提供的一种积分器的原理图；
图3C为本申请实施例提供的一种图2A所示的鉴相器的原理示意图；
图3D为本申请实施例示意的另一种鉴相器的原理示意图；
图4A为本申请实施例提供的一种鉴相器的结构示意图；
图4B为本申请实施例提供的另一种鉴相器的结构示意图；
图5A为本申请实施例提供的一种鉴相器的原理示意图；
图5B为本申请实施例提供的一种鉴相器的抖动容忍示意图；
图5C为本申请实施例提供的另一种鉴相器的原理示意图；
图6为本申请实施例提供的又一种鉴相器的结构示意图；
图7为本申请实施例提供的一种增益控制器的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第二”、“第一”等仅用于描述方便，而不能理解为控制或暗示相对重要性或者隐含指明所控制的技术特征的数量。由此，限定有“第二”、“第一”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“相耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。术语“接触”可以是直接接触，也可以是通过中间媒介间接的接触。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在开始介绍本申请实施例的细节之前，先对本申请实施例中应用到的技术术语进行定义解释。
时钟与数据恢复电路(clock and data recovery，CDR)：根据输入数据恢复出对应频率时钟，再用此时钟采样数据。
鉴相器(PHASE DETECTOR简称PD)：是时钟与数据恢复电路中用来鉴定采样时钟和输入数据相位差的电路。
波特率：对于本申请实施例讨论范围内的数据而言，波特率就是数据传输速率，如3Gb/S对应波特率就是3Gb/S。
波特率采样鉴相器：指采样率等于输入数据波特率的鉴相器。
BANG BANG鉴相器(BANG BANG phase detector，BBPD)：最传统的鉴相器电路名称，其采样率为波特率两倍。
采样比较器：其行为大致是输入时钟上升沿到来时，比较输入信号与0的关系，输入大于0则输出高电平，输入小于0则输出低电平。
UI(unit interval)：指数据传输的最小间隔单元，比如3Gb/S的数据率其UI就是333.3333pS。
非理想性：包含了积分器的时钟注入、时钟馈通、电荷分享、非线性、建立时间等，这些因素实际上都可以等效到积分器的延迟上。
抖动容忍(jitter tolerance)：是衡量始终数据恢复电路性能的核心指标，一般指电路能够容忍数据多大的抖动，一般而言抖动大到采样时钟落在数据的跳变沿上就认为电路采样已经出现错误。
缓冲器(buffer)和反相器(inverter)：两者都是最基本的数字逻辑处理器，缓冲器的输出和输入保持同向，反相器的输入和输出是反向。
负反馈：指的是系统通过反馈的手段，减小采样端误差。在时钟数据恢复电路中，表现为通过反馈手段让采样时钟相位与理想位置接近。
本申请实施例提供一种的电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、视频传输用电子设备等。其中，消费性电子产品如为手机
(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载高密度数字视频光盘(digital video disc，DVD)等。金融终端产品如为自动取款机(automated teller machine，ATM)机、自助办理业务的终端等。视频传输电子设备如为网络视频录像机(network video recorder，NVR)、数字视频录像机(digital video recorder，DVR)、数字硬盘录像机(XVR)、编码器(DVS)、一体机、工控机、网关、行业主机等后端产品。电子设备也可以是机顶盒等具有音频/视频传输需求的电子设备。
以下为了方便说明，以电子设备为平板电脑为例进行举例说明。如图1A所示，电子设备1主要包括盖板11、显示面板12、中框13以及后壳14。后壳14和显示面板12分别位于中框13的两侧，且中框13和显示面板12设置于后壳14内，盖板11设置在显示面板12远离中框13的一侧，显示面板12的显示面朝向盖板11。
上述显示面板12可以是液晶显示屏(liquid crystal display，LCD)，在此情况下，液晶显示屏包括液晶显示面板和背光模组，液晶显示面板设置在盖板11和背光模组之间，背光模组用于为液晶显示面板提供光源。上述显示面板12也可以为有机发光二极管(organic light emitting diode，OLED)显示屏。由于OLED显示屏为自发光显示屏，因而无需设置背光模组。
上述中框13包括承载板131以及绕承载板131一周的边框132。上述电子设备1还可以包括印刷电路板(printed circuit boards，PCB)、电池、摄像头等电子元器件，印刷电路板、电池、摄像头等电子元器件可以设置在承载板131上。
如图1B所示，显示面板12包括有效显示区(active area，AA)A和位于该有效显示区A周边的周边区B。
在一些实施例中，显示面板12的有效显示区A作为电子设备1的显示区，显示面板12的周边区B作为电子设备1的非显示区。
如图1B所示，显示面板12的有效显示区A包括多个亚像素(sub pixel)P。为了方便说明，本申请中上述多个亚像素P是以矩阵形式排列为例进行的说明。此时，沿水平方向排列成一排的亚像素P称为同一行亚像素，沿竖直方向排列成一排的亚像素P称为同一列亚像素。
电子设备1包括位于显示面板12周边区B的栅极驱动电路和源极驱动电路，栅极驱动电路用于为亚像素P提供栅极驱动信号，源极驱动电路用于为亚像素P提供源极驱动信号。
示例的，栅极驱动电路例如可以采用阵列基板行驱动(gate on array，GOA)技术集成在显示面板12中。栅极驱动电路包括多个级联的移位寄存器(shift register，SR)。
栅极驱动电路可以包括一个或者多个，示例的，如图1B所示，电子设备1包括两个栅极驱动电路，两个栅极驱动电路沿水平方向设置在有效显示区A的两侧。
源极驱动电路例如可以集成在驱动芯片(display driver integrated circuit,DDIC)中, 示例的，驱动芯片DDIC以裸芯片(die)的形式直接贴合在显示面板12中。
电子设备还包括时序控制器(timing controller，TCON)，在一些实施例中，如图1B所示，设置在柔性电路板(flexible printed circuit，FPC)上。
在一些实施例中，如图1C所示，源极驱动电路包括接收电路和数据输出电路。接收电路可接收从图1B中所示的时序控制器TCON提供的输入数据td，并且可恢复数据信号dt和时钟信号ck。
数据输出电路可以将数据信号dt与时钟信号ck同步地转换成数据驱动信号d，并将数据驱动信号d施加至图1B所示的亚像素P中。
接收电路中包括时钟与数据恢复电路CDR，时钟与数据恢复电路CDR可根据传输信号td恢复时钟信号ck和数据信号dt。
在一些实施例中，如图1D所示，时钟与数据恢复电路CDR包括数据恢复电路和时钟恢复电路。时钟恢复电路可接收输入数据td，并且可输出时钟信号ck。数据恢复电路可接收输入数据td，将数据信号dt与时钟信号ck同步地恢复为数据信号dt。
示例的，时钟恢复电路包括鉴相器20、电荷泵、环路滤波器以及压控振荡器VCO。
鉴相器20可检测数据信号dt与时钟信号ck之间的相位差并输出相位差信号PD。电荷泵可响应于来自鉴相器20的相位差信号PD而输出偏置电流控制信号。环路滤波器可输出与电流控制信号对应的电压控制信号。压控振荡器VCO可输出具有与电压控制信号的电压电平对应的频率的时钟信号ck。
随着模拟技术的发展，高速率电路不断地普及，而芯片功耗也在不断提高，低功耗时钟数据恢复电路CDR成为主流。在低功耗时钟与数据恢复电路CDR中，常采用的鉴相器包括BANG BANG鉴相器和波特率采样鉴相器。
在一些技术中，如图2A所示，BANG BANG鉴相器包括数据采样比较器、跳变沿采样比较器以及逻辑控制器。数据采样比较器、跳变沿采样比较器均耦接于逻辑控制器。系统产生采样时钟1和采样时钟2，采样时钟1和采样时钟2分别用来进行数据和跳变沿的采样。逻辑控制器根据采样时钟1和采样时钟2的采样结果进行异或运算，得到当前采样时钟和输入数据的相位关系(分为超前和滞后两种相位关系)。
其具体实现原理如下：
如图2B所示，采样时钟1和采样时钟2间隔半个UI。采样时钟1用来进行驱动数据采样，采样时钟2用来进行驱动跳变沿采样。示例的，可以使用采样时钟1和采样时钟2的上升沿进行采样。用虚线表示的采样时钟1<N>代表采样时钟1的第<N>个上升沿，用实线表示的采样时钟2<N-1>代表采样时钟2的第<N-1>个上升沿。用点化线表示的采样时钟2<N>代表采样时钟2的第<N>个上升沿。采样时钟1的理想采样位置应当位于一个UI的中间，因为此时采样时钟1与两边数据跳变沿直接的距离最远，也就最不容易出错。
如图2B所示，当采样时钟1滞后于理想采样位置，采样时钟1<N>和采样时钟2<N>的采样结果会不同，据此逻辑处理器将判断滞后。如图2C所示，当采样时钟1超前于理想采样位置，采样时钟1<N>和采样时钟2<N-1>的采样结果将会不同，据此逻辑处理器将判断超前。当采样时钟1落于理想位置，采样时钟2将正好落在数据跳变沿位置，此时采样结果将会随机，也就是逻辑处理器会随机判断超前还是滞后，结果系统将会在超前和滞后之间来回振荡。
上述鉴相器中，采样时钟1和采样时钟2由于只间隔0.5个UI，因此，鉴相器的采样率是波特率的两倍，导致鉴相器的功耗较高。
基于此，本申请实施例提供一种鉴相器20，如图3A所示，鉴相器20包括积分器、数据采样比较器、跳变沿采样比较器以及逻辑控制器。积分器与数据采样比较器耦接，数据采样比较器、跳变沿采样比较器均耦接于逻辑控制器。系统产生一个采样时钟，采样时钟用来进行数据和跳变沿的采样。
但是，如图3B所示，采样时钟具有第一上升沿CKPRE和和第二上升沿CKPOST，第一上升沿CKPRE是采样时钟当前上升沿，第二上升沿CKPOST就是采样时钟下一个周期上升沿。第一上升 沿CKPRE和和第二上升沿CKPOST之间具有延迟时间tdel。
积分器在第一上升沿CKPRE时刻开始对输入数据进行积分，在第二上升沿CKPOST时刻停止积分。积分器输出电压VO在输入数据的跳变沿正好落在第一上升沿CKPRE和和第二上升沿
CKPOST中间时为0，此时输入电压的平均值也为0。当积分器输出电压VO在输入数据的跳变沿与第一上升沿CKPRE和和第二上升沿CKPOST的中间错开Δt，积分器输出为：
其中，I为积分器偏置电流，CO为积分器输出电容。
此时，输入电压的平均值VI为：
其中，V为输入数据差分幅度。
可见积分器输出与输入平均电压呈正比，其增益G为：
鉴相器的具体实现原理如下：
如图3C所示，采样时钟直接驱动数据跳变沿采样器，其理想位置就是在数据跳变沿中间。采样时钟的第<N>和第<N+1>个上升沿共同驱动积分器。当采样时钟第<N>个上升沿到来以后积分器开始积分，采样时钟第<N+1>个上升沿到来以后积分器停止积分。此时积分器的输出将正比于采样时钟第<N>个上升沿和采样时钟第<N+1>个上升沿之间输入数据的平均值，也可以认为积分等效采样位置在图3C中虚线位置处。逻辑控制器根据采样时钟的第<N>和第<N+1>个上升沿以及等效采样时钟的采样结果进行异或运算，得到当前采样时钟和输入数据的相位关系(分为超前和滞后两种相位关系)。
该技术方案中，只存在一个采样时钟，采样时钟的采样周期等于一个UI，所以此时鉴相器的采样率等于波特率，可以降低功耗。
但是，数据采样器前存在积分器，而跳变沿采样比较器前没有积分器。积分器具有增益G，因此，积分器本身会引入一定的延迟和非理想性。所以如图3C所示，实际积分后得到的实际等效采样位置会比理论等效采样位置滞后。此时实际等效采样位置会更加接近下一个数据跳变沿，这将导致抖动容忍下降。需要提及的是，即便将积分器换到跳变沿采样处，如图3D所示，依然会影响抖动容忍，因为根据负反馈原理，最终等效的采样时钟将会对准数据跳变沿，所以最终的数据采样位置还是会偏移一个UI的中间。
基于此，本申请实施例还提供一种鉴相器，如图4A所示，鉴相器20包括数据积分器21、数据采样比较器22、跳变沿积分器23、跳变沿采样比较器24以及逻辑处理器25。
数据积分器21与数据输入端TD和采样时钟端CK均耦接，用于对数据输入端TD的输入数据进行积分。
本申请实施例中，数据输入端TD输入的数据流可以是数据信号，数据输入端TD输入的数据流也可以是时钟信。
数据积分器21在采样时钟端CK的采样时钟的控制下，对数据输入端TD输入的数据流进行积分。在数据积分器21的有效积分时段内，数据积分器21积分的数据不包含数据流的跳变沿。数据积分器21的输出等效于：位于数据积分器21有效积分时段内，输入至数据积分器21的数据段的中间位置处的数据。
这样一来，数据积分器21相当于完成了数据输入端TD输入的数据流中数据段的采样。
数据采样比较器22与数据积分器21和采样时钟端CK均耦接，用于根据采样时钟端CK的采样时钟，对数据积分器21的输出与设定值进行采样比较。
示例的，设定值为数据输入端TD输出的差分数据的中间值。例如，设定值为0。
跳变沿积分器23与数据输入端TD和采样时钟端CK均耦接，用于对数据输入端TD的输入数据进行积分。
跳变沿积分器23在采样时钟端CK的采样时钟的控制下，对数据输入端TD输入的数据流进行积分。在跳变沿积分器23的有效积分时段内，跳变沿积分器23积分的数据包含数据流的跳变沿。跳变沿积分器23的输出等效于：位于跳变沿积分器23有效积分时段内，输入至跳变沿积分器23的数据段的中间位置处的数据。
这样一来，跳变沿积分器23相当于完成了数据输入端TD输入的数据流中跳变沿的采样。
在一些实施例中，数据积分器21的结构与跳变沿积分器23的结构相同，数据积分器21和跳变沿积分器23用于对数据流不同时段的数据进行积分。
跳变沿采样比较器24与跳变沿积分器23和采样时钟端CK均耦接，用于根据采样时钟端CK的采样时钟，对跳变沿积分器23的输出与设定值进行采样比较。
数据采样比较器22的输出端和跳变沿采样比较器24的输出端与逻辑处理器25耦接，用于对数据采样比较器22的比较结果和跳变沿采样比较器24的比较结果进行逻辑处理，并输出处理结果。
示例的，逻辑处理器25输出第一信号和第二信号，第一信号表征采样时钟端CK的采样时钟的相位相对数据输入端TD的输入数据的相位超前，第二信号表征采样时钟的相位相对数据输入端TD的输入数据的相位滞后。
本申请实施例提供的鉴相器20中，对数据输入端TD输入的数据流的数据段的采样由数据积分器21等效完成，对数据流的跳变沿的采样由跳变沿积分器23等效完成。而完成数据段采样和跳变沿采样只需要外部系统向采样时钟端CK提供一个采样时钟即可。采样时钟的采样周期等于一个UI，鉴相器的采样率等于波特率，可以有效降低鉴相器20的功耗，提升鉴相器20的性能。在此基础上，数据采样比较器22支路上设置有数据积分器21，跳变沿采样比较器24支路上设置有跳变沿积分器23。虽然数据积分器21和跳变沿积分器23各自的增益均会引入输出结果的延迟和非理想性，但是数据积分器21引入的延迟和非理想性和跳变沿积分器23引入的延迟和非理想性可以相互抵消，以改善因积分器的引入所带来的抖动容忍下降的问题，提高鉴相器20的抖动容忍，进一步提升鉴相器20的性能。
在一些实施例中，如图4B所示，鉴相器20还包括时钟延迟器26。
采样时钟端CK、数据积分器21以及跳变沿积分器23均耦接于时钟延迟器26，时钟延迟器26用于接收采样时钟端CK的采样时钟，输出延迟采样时钟。
数据积分器21在采样时钟端CK的采样时钟和时钟延迟器26输出的延迟采样时钟的控制下，对数据输入端TD输入的数据流进行积分。跳变沿积分器23在采样时钟端CK的采样时钟和时钟延迟器26输出的延迟采样时钟的控制下，对数据输入端TD输入的数据流进行积分。数据积分器21和跳变沿积分器23均受采样时钟和延迟采样时钟的控制。
示例的，时钟延迟器26包括缓冲器(buffer)。
本申请实施例提供的鉴相器20，在一些实现方案中，虽然需要用到采样时钟和延迟采样时钟，但是通过设置时钟延迟器26，由时钟延迟器26输出延迟采样时钟。可以实现只需要外部系统向采样时钟端CK提供一个采样时钟即可。而时钟延迟器26输出延迟采样时钟所带来的增益问题，可以由数据积分器21和跳变沿积分器23的增益来抵消，以提高鉴相器20的性能。
在一些实施例中，鉴相器20受采样时钟和延迟采样时钟控制。
如图5A所示，数据积分器21用于由采样时钟的第N个上升沿起始至延迟采样时钟的第N个上升沿结束，对数据输入端TD的输入数据进行积分。其中，N为正整数。
这时，数据采样比较器22收到采样时钟的采样指示后，对输入数据的等效数据采样位置位于采样时钟的第N个上升沿与延迟采样时钟的第N个上升沿之间。
跳变沿积分器23用于由延迟采样时钟的第N个上升沿起始至采样时钟的第N+1个上升沿结束，对数据输入端TD的输入数据进行积分。
这时，跳变采样积分器23收到采样时钟的采样指示后，对输入数据的等效跳变沿采样位置位于延迟采样时钟的第N个上升沿与采样时钟的第N+1个上升沿之间。
其具体计算如下：
那么：
延迟采样时钟的采样时刻tdel<N>＝t<N>+tdel。

其中，t<N>为采样时钟的第N个上升沿时刻，t<N+1>为采样时钟的第N+1个上升沿时刻，
tdel<N>为延迟采样时钟的第N个上升沿时刻，tdel为延迟采样时钟之间的延迟时间。
从公式中可以看出，等效数据采样时刻和等效跳变沿采样时刻相差UI/2。由此可以认为其能够起到BANG BANG鉴相器的功能。同时系统只需要提供一个采样时钟，所以也具备波特率采样特性。
如图5B所示，由于数据采样比较器22支路上设置有数据积分器21，跳变沿采样比较器24支路上设置有跳变沿积分器23。因此，受延迟和非理想性的影响，实际等效数据采样位置相对理论等效数据采样位置偏移一个延迟，实际等效跳变沿采样位置相对理论等效跳变沿采样位置偏移一个延迟。根据负反馈原理，偏移后的跳变沿采样位置将对准数据跳变沿，而等效数据采样时刻和等效跳变沿采样时刻相差UI/2，此时数据采样位置将还是落在一个UI的中间。那么，实际抖动容忍和理论抖动容忍相等。因此，本申请实施例提供的鉴相器20也不会降低抖动容忍。
数据采样比较器22对数据积分器21的输出的采样，等效于数据采样比较器22在图5A中的等效数据采样位置对输入数据进行采样。
数据采样比较器22将采样的数据与设定值进行比较，示例的，设定值为0。那么，在采样数据大于0时，数据采样比较器22输出数据信号1。在采样数据小于0时，数据采样比较器22输出数字信号0。
同理，跳变沿采样比较器24对跳变沿积分器23的输出的采样，等效于跳变沿采样比较器24在图5A中的等效跳变沿采样位置对输入数据进行采样。
跳变沿采样比较器24将采样的数据与设定值进行比较，示例的，在采样数据大于0时，跳变沿采样比较器24输出数据信号1。在采样数据小于0时，跳变沿采样比较器24输出数字信号0。
因此，数据采样比较器22向逻辑处理器25输出的信号为数字信号0或者数字信号1，跳变沿采样比较器24向逻辑处理器25输出的信号也为数字信号0或者数字信号1。
逻辑处理器25用于对数据采样比较器22的比较结果和跳变沿采样比较器24的比较结果进行逻辑处理，并输出处理结果。
在一些实施例中，逻辑处理器25具有第一输出端和第二输出端。
当，在采样时钟的第N个上升沿处，数据采样比较器22输出的采样比较结果(例如1)，与，在延迟采样时钟的第N个上升沿处，跳变沿采样比较器24输出的采样结果(例如0)不同；在延迟采样时钟的第N个上升沿处，跳变沿采样比较器24输出的采样结果(例如1)，与，在采样时钟的第N+1个上升沿处，数据采样比较器22输出的采样比较结果(例如1)相同；且逻辑判断一直是这样的判断结果。则逻辑处理器25从第一输出端输出数字信号(例如数字信号1)，表征采样时钟的相位相对输入数据的相位超前。且此时，逻辑处理器25的第一输出端持续输出1，逻辑处理器25的第二输出端持续输出0。
当，在延迟采样时钟的第N个上升沿处，跳变沿采样比较器24输出的采样结果(例如0)，与，在采样时钟的第N+1个上升沿处，数据采样比较器22输出的采样比较结果(例如1)不同。在采样时钟的第N个上升沿处，数据采样比较器22输出的采样比较结果(例如0)，与，在延迟采样时钟的第N个上升沿处，跳变沿采样比较器24输出的采样结果(例如0)相同；且逻辑判断一直是这样的判断结果。则逻辑处理器25从第二输出端输出数字信号(例如数字信号1)，表征采样时钟的相位相对输入数据的相位滞后。且此时，逻辑处理器25的第一输出端持续输出0，逻辑处理器25的第二输出端持续输出1。
当，在采样时钟的第N个上升沿处，数据采样比较器22输出的采样比较结果(例如1)，与，在延迟采样时钟的第N个上升沿处，跳变沿采样比较器24输出的采样结果(例如0)不 同；在延迟采样时钟的第N个上升沿处，跳变沿采样比较器24输出的采样结果(例如0)，与，在采样时钟的第N+1个上升沿处，数据采样比较器22输出的采样比较结果(例如0)相同，表征比较结果超前。而后，在延迟采样时钟的第N+1个上升沿处，跳变沿采样比较器24输出的采样结果(例如1)，与，在采样时钟的第N+2个上升沿处，数据采样比较器22输出的采样比较结果(例如0)不同。在采样时钟的第N+1个上升沿处，数据采样比较器22输出的采样比较结果(例如1)，与，在延迟采样时钟的第N+1个上升沿处，跳变沿采样比较器24输出的采样结果(例如1)又相同，表征比较结果滞后。这种比较结果在超前和滞后之间来回震荡时，则表征采样时钟的相位相对输入数据的相位的抖动在容忍范围内。且此时，逻辑处理器25的输出为：第一输出端输出1，第二输出端输出0；第一输出端输出0，第二输出端输出1。这样来回交替震荡输出。
当然，上述数字信号中“0”和“1”可以互换，依旧属于本申请实施例的保护范围。
那么，从第一输出端持续输出数字信号1，从第二输出端持续输出数字信号0，则表示逻辑处理器25输出第一信号，表征采样时钟的相位相对输入数据的相位超前。
从第一输出端持续输出数字信号0，从第二输出端持续输出数字信号1，则表示逻辑处理器25输出第二信号，表征采样时钟的相位相对输入数据的相位滞后。
第一输出端输出1，第二输出端输出0；第一输出端输出0，第二输出端输出1。这样来回交替震荡输出，则表示逻辑处理器25输出第三信号，表征采样时钟的相位相对输入数据的相位的抖动在容忍范围内。
当然，如图5C所示，数据积分器21也可以由延迟采样时钟的第N-1个上升沿起始至采样时钟的第N个上升沿结束，对数据输入端TD的输入数据进行积分。
跳变沿积分器23由采样时钟的第N个上升沿起始至采样时钟的第N个上升沿结束，对数据输入端TD的输入数据进行积分。
其原理与上述图5A所示的积分方式的原理相同，可参考上述相关描述，此处不再赘述。
在一些实施例中，如图6所示，鉴相器20还包括增益控制器27；增益控制器27与跳变沿积分器23耦接，用于向跳变沿积分器23输出偏置电流。
通过前述介绍可知，数据积分器21的增益G21为：
在一些实施例中，数据积分器21的结构与跳变沿积分器23的结构相同。
那么，数据积分器21的结构与跳变沿积分器23的CO和V相等。但是，数据积分器21的延迟时间tdel为时钟延迟器26的延迟时间，受时钟延迟器26结构控制。在时钟延迟器26的结构固定后，数据积分器21的延迟时间tdel为固定值。跳变沿积分器23的延迟时间tdel为一个UI，而UI受数据输入端TD的输入数据限定。即使鉴相器20的结构固定，随着输入数据的不同，跳变沿积分器23的延迟时间tdel是一个变量。这会导致数据积分器21的增益G21和跳变沿积分器23的增益G23不相等。
通过设置增益控制器27，使增益控制器27产生一个与采样时钟频率FREQ(即1/UI)呈正比的偏置电流I1提供给跳变沿积分器23。例如，增益控制器27输出的偏置电流为：I1＝K*FREQ。
那么，跳变沿积分器23的增益G23为：
其中，K为偏置电流I1和采样时钟频率FREQ的比例。
通过调整增益控制器27的设计参数，使K＝I*tdel，即可使跳变沿积分器23的增益G23为：
因此，通过在鉴相器20中设置增益控制器27，增益控制器27可以对跳变沿积分器23进行增益补偿，以使数据积分器21的增益G21和跳变沿积分器23的增益G23尽量相等，以尽可能的将 数据积分器21引入的延迟和非理想性和跳变沿积分器23引入的延迟和非理想性相互抵消，提高鉴相器20的性能。
在一些实施例中，如图7所示，增益控制器27包括运算放大器OP、反相器(inverter)、第一晶体管M1、第二晶体管M2、第一开关SW1、第二开关SW2以及电容；
运算放大器OP的输入端与基准电压端VREF耦接，运算放大器OP的另一输入端与第一节点Z1耦接，运算放大器OP的输出端与第一晶体管M1的栅极耦接。
第一晶体管M1的第一极与第一电压端V1耦接，第一晶体管M1的第二极与第一节点Z1耦接。
第二晶体管M2的栅极与运算放大器OP的输出端耦接，第二晶体管M2的第一极与第一电压端V1耦接，第二晶体管M2的第二极与跳变沿积分器23耦接。
第一开关SW1耦接于第一节点Z1与第二节点Z2之间；第一开关SW1的控制端与采样时钟端CK耦接。
反相器的输入端与采样时钟端CK耦接，反相器的输出端与第二开关SW2的控制端耦接；第二开关SW2和电容C并联耦接于第二节点Z2与第二电压端V2之间。
第一电压端V1例如可以为电源电压端，第二电压端V2例如可以是参考地电压端。
当然，本申请实施例中增益控制器27的结构并不限定为图7所示的结构，任何能够实现增益控制器27功能的结构，或者与图7所示结构实现原理相同的结构，均属于本申请实施例的保护范围。
示例的，增益控制器27中可以包括与第一晶体管M1串联或者并联的晶体管，增益控制器27中可以包括与第二晶体管M2串联或者并联的晶体管，增益控制器27中可以包括与第一开关SW1串联或者并联的开关，增益控制器27中可以包括与第二开关SW2串联或者并联的开关。
增益控制器27工作过程中，采样时钟端CK输入的采样时钟通过反相器产生反向采样时钟。采样时钟为1时，第一开关SW1闭合，第二开关SW2关断。第一晶体管M1将第一电压端V1的信号传输至电容C，对电容C进行充电。采样时钟为0时，第一开关SW1关断，第二开关SW2闭合，电容C放电到第二电压端V2。此时从第一节点Z1向电容C看，可以等效出一个电阻R：
运算放大器OP通过负反馈将第一节点Z1维持在基准电压端VREF的电压，所以流过第一晶体管M1的偏置电流I1为：
所以，
通过调整电容C的设计参数，使K＝I*tdel，即可使跳变沿积分器23的增益G23与数据积分器21的增益G21相同。
通过设置增益控制器27，可调整跳变沿积分器23的增益G23，使跳变沿积分器23的增益G23与数据积分器21的增益G21相同，使数据积分器21引入的延迟和非理想性和跳变沿积分器23引入的延迟和非理想性相互对称、相互抵消，以改善因积分器的引入所带来的抖动容忍下降的问题，提高鉴相器20的抖动容忍，进一步提升鉴相器20的性能。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种鉴相器，其特征在于，包括：
    数据积分器，与采样时钟端耦接，用于根据所述采样时钟端的信号，对输入数据进行积分；
    数据采样比较器，用于将所述数据积分器的输出与设定值进行采样比较；
    跳变沿积分器；与所述采样时钟端耦接，用于根据所述采样时钟端的信号，对所述输入数据进行积分；
    跳变沿采样比较器；用于将所述跳变沿积分器的输出与所述设定值进行采样比较；
    逻辑处理器，用于对所述数据采样比较器的比较结果和所述跳变沿采样比较器的比较结果进行逻辑处理，并输出处理结果。
  2. 根据权利要求1所述的鉴相器，其特征在于，所述鉴相器还包括时钟延迟器；
    所述采样时钟端、所述数据积分器以及所述跳变沿积分器均耦接于所述时钟延迟器，所述时钟延迟器用于接收所述采样时钟端的采样时钟，输出延迟采样时钟。
  3. 根据权利要求2所述的鉴相器，其特征在于，
    所述数据积分器用于由所述采样时钟的第N个上升沿起始至所述延迟采样时钟的第N个上升沿结束，对所述输入数据进行积分；所述跳变沿积分器用于由所述延迟采样时钟的第N个上升沿起始至所述采样时钟的第N+1个上升沿结束，对所述输入数据进行积分；N为正整数。
  4. 根据权利要求3所述的鉴相器，其特征在于，
    所述数据积分器用于由所述延迟采样时钟的第N-1个上升沿起始至所述采样时钟的第N个上升沿结束，对所述输入数据进行积分；所述跳变沿积分器用于由所述采样时钟的第N个上升沿起始至所述采样时钟的第N个上升沿结束，对所述输入数据进行积分；N为正整数。
  5. 根据权利要求1-4任一项所述的鉴相器，其特征在于，所述数据积分器和所述跳变沿积分器结构相同。
  6. 根据权利要求1-5任一项所述的鉴相器，其特征在于，所述鉴相器还包括增益控制器；所述增益控制器与所述跳变沿积分器耦接，用于向所述跳变沿积分器输出偏置电流。
  7. 根据权利要求6所述的鉴相器，其特征在于，所述增益控制器包括运算放大器、反相器、第一晶体管、第二晶体管、第一开关、第二开关以及电容；
    所述运算放大器的输入端与基准电压端耦接，所述运算放大器的另一输入端与第一节点耦接，所述运算放大器的输出端与所述第一晶体管的栅极耦接；
    所述第一晶体管的第一极与第一电压端耦接，所述第一晶体管的第二极与第一节点耦接；
    所述第二晶体管的栅极与所述运算放大器的输出端耦接，所述第二晶体管的第一极与所述第一电压端耦接，所述第二晶体管的第二极与所述跳变沿积分器耦接；
    所述第一开关耦接于所述第一节点与第二节点之间；所述第一开关的控制端与采样时钟端耦接；
    所述反相器的输入端与所述采样时钟端耦接，所述反相器的输出端与所述第二开关的控制端耦接；所述第二开关和所述电容并联耦接于所述第二节点与第二电压端之间。
  8. 根据权利要求3-7任一项所述的鉴相器，其特征在于，所述时钟延时器包括缓冲器。
  9. 根据权利要求1-8任一项所述的鉴相器，其特征在于，所述逻辑处理器具有第一输出端和第二输出端；
    所述逻辑处理器用于从所述第一输出端输出数字信号，表征所述采样时钟的相位相对所述输入数据的相位超前；
    所述逻辑处理器用于从所述第二输出端输出所述数字信号，表征所述采样时钟的相位相对所述输入数据的相位滞后。
  10. 根据权利要求1-8任一项所述的鉴相器，其特征在于，所述设定值为0。
  11. 一种时钟与数据恢复电路，其特征在于，包括鉴相器和电荷泵，所述鉴相器为权利要求1-10任一项所述的鉴相器，所述鉴相器与所述电荷泵耦接。
  12. 一种电子设备，其特征在于，包括驱动芯片和时钟与数据恢复电路；所述时钟与数据恢 复电路设置在所述驱动芯片内；所述时钟与数据恢复电路为权利要求11所述的时钟与数据恢复电路。
  13. 一种鉴相器的工作方法，其特征在于，包括：
    数据积分器对输入数据进行积分；
    数据采样比较器将所述数据积分器的输出与设定值进行采样比较；
    跳变沿积分器对所述输入数据进行积分；
    跳变沿采样比较器将所述跳变沿积分器的输出与所述设定值进行采样比较；
    逻辑处理器对所述数据采样比较器的比较结果和所述跳变沿采样比较器的比较结果进行逻辑处理，并输出处理结果。
PCT/CN2023/103186 2022-10-25 2023-06-28 鉴相器及其工作方法、时钟与数据恢复电路、电子设备 WO2024087694A1 (zh)

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CN102281060A (zh) * 2011-04-02 2011-12-14 长沙景嘉微电子有限公司 一种应用于时钟数据恢复的鉴相器电路
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CN113992319A (zh) * 2021-10-18 2022-01-28 中国人民解放军国防科技大学 接收机用CDR电路、Duo-Binary PAM4接收机及传输系统

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JP2011234009A (ja) * 2010-04-26 2011-11-17 Renesas Electronics Corp クロックアンドデータリカバリ回路
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