WO2024087220A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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WO2024087220A1
WO2024087220A1 PCT/CN2022/128416 CN2022128416W WO2024087220A1 WO 2024087220 A1 WO2024087220 A1 WO 2024087220A1 CN 2022128416 W CN2022128416 W CN 2022128416W WO 2024087220 A1 WO2024087220 A1 WO 2024087220A1
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Prior art keywords
pixels
sub
column
domain
transistor
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PCT/CN2022/128416
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English (en)
French (fr)
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刘永
王武
廖燕平
王章涛
南明智
何鑫
付兴凯
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京东方科技集团股份有限公司
成都京东方显示科技有限公司
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Priority to PCT/CN2022/128416 priority Critical patent/WO2024087220A1/zh
Publication of WO2024087220A1 publication Critical patent/WO2024087220A1/zh

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  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • Liquid Crystal Display has the advantages of light weight, low power consumption, high image quality, low radiation and easy portability. It has gradually replaced traditional cathode ray tube display (CRT) and is widely used in modern information equipment, such as augmented reality (AR)/virtual reality (VR) display devices, laptops, televisions, mobile phones and digital products.
  • CTR cathode ray tube display
  • AR augmented reality
  • VR virtual reality
  • the display substrate and display device provided by the present disclosure are specifically described as follows:
  • an embodiment of the present disclosure provides a display substrate, comprising:
  • a plurality of pixels arranged in an array wherein the pixels include a plurality of sub-pixels, and the sub-pixels include a first domain and a second domain, wherein the first domain and the second domain have at least two orientations respectively;
  • a plurality of data lines wherein the data lines are electrically connected to the first domain area and the second domain area of the sub-pixels in the same column;
  • a plurality of discharge lines are provided, wherein the discharge lines are electrically connected to the second domain areas of the sub-pixels in the same column, and the discharge lines provide at least two DC signals of different magnitudes for the pixels in two adjacent columns.
  • every at least two adjacent columns of sub-pixels constitute a cycle, and each column of sub-pixels in the same cycle is electrically connected to the discharge lines providing different DC signals, respectively.
  • the plurality of discharge lines provide two different DC signals
  • the plurality of discharge lines provide n different DC signals, where n is the total number of all the sub-pixels in the pixel, and n is greater than or equal to 3;
  • the sub-pixels in all columns of each column of pixels form a cycle, and the sub-pixels in each column within the same cycle are electrically connected to the discharge lines providing different DC signals.
  • the plurality of discharge lines provide 2n different DC signals, where n is the total number of all the sub-pixels in the pixel, and n is greater than or equal to 3;
  • the sub-pixels in all columns of every two adjacent columns of pixels form a cycle, and the sub-pixels in each column within the same cycle are electrically connected to the discharge lines providing different DC signals.
  • the plurality of discharge lines provide two different DC signals
  • the data line provides data signals of two polarities to the sub-pixels in each column of the pixels in the same column.
  • the display substrate provided in the embodiments of the present disclosure further includes at least two terminals, and the same terminal is electrically connected to the discharge line providing the same DC signal.
  • the display substrate provided in the embodiments of the present disclosure further includes at least two filter circuits, each of which is respectively connected between the terminal and the discharge line providing different DC signals.
  • the filtering circuit includes a resistor and a capacitor, wherein the resistor is connected between the terminal and the discharge line, and the capacitor is connected between the discharge line and ground.
  • a gate line is further included, the second domain area includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, the second electrode of the first transistor is electrically connected to the first electrode of the second transistor, the gate of the second transistor is electrically connected to the gate line, and the second electrode of the second transistor is electrically connected to the discharge line;
  • a ratio of a channel width-to-length ratio of the first transistor to a channel width-to-length ratio of the second transistor is different.
  • the channel width-to-length ratios of the first transistors are the same, and the channel width-to-length ratios of the second transistors are different.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • FIG1 is a schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of a multi-domain display light effect of the display substrate shown in FIG1;
  • FIG3 is a schematic structural diagram of the display substrate shown in FIG1 ;
  • FIG4 is an enlarged structural diagram of the Z region in FIG3 ;
  • FIG5 is another schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a multi-domain display light effect of the display substrate shown in FIG5 ;
  • FIG7 is another schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of a multi-domain display light effect of the display substrate shown in FIG7;
  • FIG9 is another schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of a multi-domain display light effect of the display substrate shown in FIG9;
  • FIG11 is another schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG12 is an equivalent circuit diagram of the display substrate shown in FIG3 ;
  • FIG. 13 is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure.
  • Multi-domain display technology has gradually developed.
  • the so-called multi-domain display is to divide a sub-pixel into different areas.
  • the deflection degree of liquid crystal in different areas is different.
  • sub-pixels in related technologies are mostly designed with 8 domains. Specifically, the sub-pixels are divided into two parts, each of which is designed with 4 domains, but the pixel potentials of the two parts are different, and there is a difference in light and dark (the bright pixel part is called a bright pixel, and the dark pixel part is called a dark pixel), so that an 8-domain display effect can be achieved.
  • each sub-pixel has three transistors, one transistor controls the bright pixel, and two transistors control the dark pixel.
  • the transistor that controls the bright pixel is electrically connected to the data line (data), and the two transistors that control the dark pixel are electrically connected to the data line (data) and the discharge line (discharge), respectively.
  • the potential of the dark pixel can be made smaller than the potential of the bright pixel.
  • all sub-pixels are connected to a DC signal with the same potential, resulting in almost no difference in the 8-domain display effects between different sub-pixels. When the color shift effect is not good, the adjustable range is limited.
  • the present disclosure provides a display substrate, as shown in FIG. 1 and FIG. 2, including:
  • the pixels 101 include a plurality of sub-pixels SP, the sub-pixels SP include a first domain area (e.g., bright pixels) and a second domain area (e.g., dark pixels), the first domain area (e.g., bright pixels) and the second domain area (e.g., dark pixels) each have at least two orientations;
  • the first domain area e.g., bright pixels
  • the second domain area e.g., dark pixels
  • a plurality of data lines 102, the data lines 102 are electrically connected to a first domain region (eg, bright pixel) and a second domain region (eg, dark pixel) of sub-pixels SP in the same column;
  • a first domain region eg, bright pixel
  • a second domain region eg, dark pixel
  • a plurality of discharge lines 103 are provided, wherein the discharge lines 103 are electrically connected to the second domain region (e.g., dark pixels) of the sub-pixels SP in the same column, and the discharge lines 103 provide at least two DC signals of different magnitudes for two adjacent columns of pixels 101; optionally, the DC signal of the discharge line 103 in the present disclosure may be greater than 0 and less than or equal to 15V, such as 5V, 8V, 9V, etc.
  • the second domain areas (for example, dark pixels) of the two adjacent columns of pixels 101 can present at least two multi-domain display effects, which is approximately equivalent to increasing the number of domains, thereby better improving color deviation.
  • the total number of orientations of the first domain may be the same as the total number of orientations of the second domain (e.g., dark pixel).
  • the first domain (e.g., bright pixel) and the second domain (e.g., dark pixel) each have four orientations.
  • the total number of orientations of the first domain (e.g., bright pixel) and the total number of orientations of the second domain (e.g., dark pixel) may be different.
  • the first domain (e.g., bright pixel) has two orientations and the second domain (e.g., dark pixel) has four orientations.
  • the total number of orientations of the first domain e.g., bright pixel
  • the total number of orientations of the second domain e.g., dark pixel
  • each adjacent at least two columns of sub-pixels SP constitute a cycle, and each column of sub-pixels SP in the same cycle is electrically connected to the discharge line 103 providing different DC signals, so that the multi-domain display effect of the second domain area (e.g., dark pixel) of each column of sub-pixels SP in the same cycle is different, which can be approximately equivalent to increasing the number of domains, thereby better improving color deviation.
  • the discharge lines 103 respectively connected to the columns of sub-pixels SP corresponding to the same position in each cycle can be gathered together to save the number of terminals providing signals to the discharge lines 103.
  • a plurality of discharge lines 103 provide two different DC signals; each two adjacent columns of sub-pixels SP constitute a cycle, and the two columns of sub-pixels SP in the same cycle are electrically connected to the discharge lines 103 providing different DC signals.
  • the discharge lines 103 corresponding to the two different DC signals are marked as a first discharge line 1031 and a second discharge line 1032, and the two columns of sub-pixels SP in the same cycle are marked as a first column of sub-pixels SP 1 and a second column of sub-pixels SP 2 , wherein the first column of sub-pixels SP 1 is electrically connected to the first discharge line 1031, and the second column of sub-pixels SP 2 is electrically connected to the second discharge line 1032.
  • the discharge lines 103 corresponding to the two different DC signals are marked as a first discharge line 1031 and a second discharge line 1032
  • the two columns of sub-pixels SP in the same cycle are marked as a first column of sub-pixels SP 1 and a second column of sub-pixels SP 2 , wherein the first column of sub-pixels SP 1 is electrically connected to the first discharge line 1031, and the second column of sub-pixels SP 2 is electrically connected to the second discharge line 1032.
  • the second domain area (e.g., dark pixel) in the first column of sub-pixels SP 1 exhibits a multi-domain display effect
  • the second domain area (e.g., dark pixel) in the second sub-pixel column SP 2 exhibits another multi-domain display effect.
  • the present disclosure effectively enriches the multi-domain display effect and is more conducive to improving color shift.
  • a plurality of discharge lines 103 provide n different DC signals, where n is the total number of sub-pixels in a pixel, and n is greater than or equal to 3; the sub-pixels SP in each column of pixels P form a cycle, and each column of sub-pixels SP in the same cycle is electrically connected to the discharge line 103 providing different DC signals.
  • FIG. 5 and FIG. 6 For ease of understanding, FIG. 5 and FIG. 6
  • each column of pixels P has three columns of sub-pixels SP (for example, the column where the red sub-pixel R is located, the column where the green sub-pixel G is located, and the column where the blue sub-pixel B is located), and the plurality of discharge lines 103 provide three DC signals.
  • the discharge lines 103 corresponding to the three DC signals are respectively marked as a first discharge line 1031, a second discharge line 1032, and a third discharge line 1033, and the three columns of sub-pixels SP in the same cycle are respectively marked as a first column of sub-pixels SP 1 , a second column of sub-pixels SP 2 , and a third column of sub-pixels SP 3 , wherein the first column of sub-pixels SP 1 is electrically connected to the first discharge line 1031, the second column of sub-pixels SP 2 is electrically connected to the second discharge line 1032, and the third column of sub-pixels SP 3 is electrically connected to the third discharge line 1033.
  • the second domain area (e.g., dark pixel) in the first column of sub-pixels SP 1 exhibits a first multi-domain display effect
  • the second domain area (e.g., dark pixel) in the second sub-pixel column SP 2 exhibits a second multi-domain display effect
  • the second domain area (e.g., dark pixel) in the third sub-pixel column SP 3 exhibits a third multi-domain display effect.
  • this embodiment further enriches the multi-domain display effect and is more conducive to improving color deviation.
  • this embodiment also realizes separate control of the multi-domain display effects of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B.
  • a plurality of discharge lines 103 provide 2n different DC signals, where n is the total number of sub-pixels SP in the pixel 101, and n is greater than or equal to 3; the sub-pixels SP in each of two adjacent columns of pixels 101 constitute a cycle, and the sub-pixels SP in each column within the same cycle are electrically connected to the discharge lines 103 providing different DC signals.
  • FIG7 illustrates an example in which each column of pixels P has three columns of sub-pixels SP (for example, the columns where the red sub-pixels R are located, the columns where the green sub-pixels G are located, and the columns where the blue sub-pixels B are located), and the plurality of discharge lines 103 provide six DC signals.
  • sub-pixels SP for example, the columns where the red sub-pixels R are located, the columns where the green sub-pixels G are located, and the columns where the blue sub-pixels B are located
  • the plurality of discharge lines 103 provide six DC signals.
  • the discharge lines 103 corresponding to the six DC signals are respectively marked as a first discharge line 1031, a second discharge line 1032, a third discharge line 1033, a fourth discharge line 1034, a fifth discharge line 1035 and a sixth discharge line 1036, and the six columns of sub-pixels SP in the same cycle are respectively marked as a first column of sub-pixels SP 1 , a second column of sub-pixels SP 2 , a third column of sub-pixels SP 3 , a fourth column of sub-pixels SP 4 , a fifth column of sub-pixels SP 5 and a sixth column of sub-pixels SP 6 , wherein the first column of sub-pixels SP 1 is electrically connected to the first discharge line 1031, the second column of sub-pixels SP 2 is electrically connected to the second discharge line 1032, the third column of sub-pixels SP 3 is electrically connected to the third discharge line 1033, the fourth column of sub-pixels SP 4 is electrically connected to the fourth discharge line 10
  • the second domain area (e.g., dark pixel) in the first column of sub-pixels SP1 exhibits the first multi-domain display effect
  • the second domain area (e.g., dark pixel) in the second sub-pixel column SP2 exhibits the second multi-domain display effect
  • the second domain area (e.g., dark pixel) in the third sub-pixel column SP3 exhibits the third multi-domain display effect
  • the second domain area (e.g., dark pixel) in the fourth column of sub-pixels SP4 exhibits the first multi-domain display effect
  • the second domain area (e.g., dark pixel) in the fifth sub-pixel column SP5 exhibits the second multi-domain
  • the second domain area (e.g., dark pixel) in the first column of sub-pixels SP1 and the second sub-pixel column SP2 in the related art Compared with the second domain area (e.g., dark pixel) in the first column of sub-pixels SP1 and the second sub-pixel column SP2 in the related art, the second domain area (e.g., dark pixel) in the first column of sub-pixels SP1 and the second sub-pixel column SP 2 , the second domain area (e.g., dark pixel) in the third sub-pixel column SP 3 , the second domain area (e.g., dark pixel) in the fourth column sub-pixel SP 4 , the second domain area (e.g., dark pixel) in the fifth sub-pixel column SP 5 , and the second domain area (e.g., dark pixel) in the sixth sub-pixel column SP 6 show similar dark-state multi-domain display effects. This embodiment further enriches the multi-domain display effects and is more conducive to improving color shift.
  • the data line 102 provides two polarity data signals for each column of sub-pixels SP in the same column of pixels 101.
  • a column of pixels 101 includes three columns of sub-pixels SP, and the three columns of sub-pixels SP can be loaded with two positive polarity (+) data signals and one negative polarity (-) data signal, or the three columns of sub-pixels SP can be loaded with two negative polarity data signals and one positive polarity data signal.
  • the first column of sub-pixels SP 1 , the second column of sub-pixels SP 2 , the third column of sub-pixels SP 3 , the fourth column of sub-pixels SP 4 , the fifth column of sub-pixels SP 5 and the sixth column of sub-pixels SP 6 in the two columns of pixels 101 may be loaded with positive polarity data signals, negative polarity data signals, positive polarity data signals, negative polarity data signals, positive polarity data signals and negative polarity data signals, respectively, or may be loaded with positive polarity data signals, negative polarity data signals, negative polarity data signals, positive polarity data signals, positive polarity data signals and negative polarity data signals, respectively.
  • the green sub-pixel G and the blue sub-pixel B may be separately controlled, but also the sub-pixels SP loaded with positive polarity data signals and negative polarity data signals may be separately controlled.
  • a plurality of discharge lines 103 provide two different DC signals; each two adjacent columns of pixels 101 constitute a cycle, and the two columns of pixels 101 in the same cycle are electrically connected to the discharge lines 103 providing different DC signals, respectively, and each column of sub-pixels SP in the same column of pixels 101 is electrically connected to the discharge line 103 providing the same DC signal.
  • FIG9 illustrates an example in which each column of pixels 101 has three columns of sub-pixels SP (for example, the column where the red sub-pixel R is located, the column where the green sub-pixel G is located, and the column where the blue sub-pixel B is located).
  • the discharge lines 103 corresponding to the two DC signals are respectively marked as a first discharge line 1031 and a second discharge line 1032
  • the columns of sub-pixels SP in the two columns of pixels 101 within the same cycle are respectively marked as a first column of sub-pixels SP 1 , a second column of sub-pixels SP 2 , a third column of sub-pixels SP 3 , a fourth column of sub-pixels SP 4 , a fifth column of sub-pixels SP 5 and a sixth column of sub-pixels SP 6
  • the first column of sub-pixels SP 1 , the second column of sub-pixels SP 2 and the third column of sub-pixels SP 3 in one column of pixels 101 are all electrically connected to the first discharge line 1031
  • the fourth column of sub-pixels SP 4 , the fifth column of sub-pixels SP 5 and the sixth column of sub-pixels SP 6 in the other column of pixels 101 are all electrically connected to the second discharge line 1032.
  • the second domain area (e.g., dark pixel) in the first column of sub-pixels SP 1 , the second domain area (e.g., dark pixel) in the second sub-pixel column SP 2 , and the second domain area (e.g., dark pixel) in the third sub-pixel column SP 3 exhibit a multi-domain display effect
  • the second domain area (e.g., dark pixel) in the fourth column of sub-pixels SP 4 , the second domain area (e.g., dark pixel) in the fifth sub-pixel column SP 5 , and the second domain area (e.g., dark pixel) in the sixth sub-pixel column SP 6 exhibit another multi-domain display effect, compared with the second domain area (e.g., dark pixel) in the first column of sub-pixels SP 1 , the second domain area (e.g., dark pixel) in the
  • the disclosure uses the number of types of DC signals between 2 and 6 as an example for explanation, and different numbers of DC signals can be selected according to different needs.
  • the DC signal in the disclosure is a DC signal, similar to the common voltage signal. Under normal circumstances, 6 DC signals of different sizes are sufficient for use. In too many cases, control is difficult and the cost increases. Therefore, the disclosure only uses 6 or less DC signals for example. However, in some embodiments, more (for example, more than 7) DC signals of different sizes can also be set, which is not limited here.
  • the columns where the sub-pixels SP or the columns where the pixels 101 are located which are electrically connected to the discharge lines 103 of different DC signals, are alternately arranged, so that the second domain areas (for example, dark pixels) with two different multi-domain display effects are formed in a relatively small range, and the overall multi-domain display effect after the multi-domain display effect formed with the first domain area (for example, bright pixels) is uniform, and there will be no split screen phenomenon.
  • the second domain areas for example, dark pixels
  • the overall multi-domain display effect after the multi-domain display effect formed with the first domain area for example, bright pixels
  • At least two terminals 104 may be further included, and the same terminal 104 is electrically connected to the discharge line 103 providing the same DC signal, so that the same terminal 104 can be used to uniformly load the signal for each discharge line 103 providing the same DC signal, thereby reducing the number of terminals 104.
  • the present disclosure may also include at least two filter circuits 105, each filter circuit 105 is respectively connected between at least two terminals 104 and the discharge line 103 providing different DC signals, so that the DC signal with a fixed potential on the discharge line 103 is ensured to be more stable and reliable through the filter circuit 105, and the interference of the AC signal on the data line 102 on the DC signal on the discharge line 103 is reduced.
  • the filter circuit 105 may include a resistor r and a capacitor c, wherein the resistor r is connected between the terminal 104 and the discharge line 103, and the capacitor c is connected between the discharge line 103 and the ground.
  • filter circuit 105 The structure of such a filter circuit 105 is relatively simple, and the required layout space is small, which is conducive to the narrow frame design of the product.
  • the filter circuit 105 may also have other structures known to those skilled in the art, which are not specifically limited here.
  • a gate line 106 may also be included, the second domain area (for example, a dark pixel) includes a first transistor T1 and a second transistor T2 , the gate of the first transistor T1 is electrically connected to the gate line 106, the first electrode of the first transistor T1 is electrically connected to the data line 102, the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2 , the gate of the second transistor T2 is electrically connected to the gate line 106, and the second electrode of the second transistor T2 is electrically connected to the discharge line 103; in adjacent sub-pixels SP or adjacent pixels 101 in the row direction, the ratio of the channel width-to-length ratio of the first transistor T1 to the channel width-to-length ratio of the second transistor T2 is different.
  • the first transistor T1 and the second transistor T2 connected between the data line 102 and the discharge line 103 can be equivalent to two resistors.
  • the potential of the first domain area (e.g., bright pixel) and the potential of the second domain area (e.g., dark pixel) can be converted by the potential of the data line 102, the potential of the discharge line 103, and the resistance voltage division formula of the first transistor T1 and the second transistor T2 .
  • the ratio of the channel width-to-length ratio of the first transistor T1 and the channel width-to-length ratio of the second transistor T2 (equivalent to the resistance ratio of the two) is 1:1, the data signal of the data line 102 is 10V, and the DC signal of the discharge line 103 is 5V, according to the resistance voltage division formula, the potential of the second domain area (e.g., dark pixel) is 7.5V, and the potential of the first domain area (e.g., bright pixel) is equal to the potential of the data line 102, which is 10V.
  • the second domain area (e.g., dark pixel) of the adjacent pixel 101 or sub-pixel SP when the ratio of the channel width-to-length ratio of the first transistor T1 and the channel width-to-length ratio of the second transistor T2 is different, the second domain area (e.g., dark pixel) of the adjacent pixel 101 or sub-pixel SP can show multi-domain display with different effects, which is beneficial to improve color deviation.
  • the discharge line 103 providing different DC signals
  • the multi-domain display effect of different DC signals can be more fully exerted, and the color deviation can be better improved.
  • the ratio of the channel width-to-length ratio of the first transistor T1 to the channel width-to-length ratio of the second transistor T2 may be in the range of 1 to 5.
  • the first transistor T1 and the second transistor T2 may be oxide (e.g., indium gallium zinc oxide IGZO) transistors, and the channel width-to-length ratio of the first transistor T1 and the channel width-to-length ratio of the second transistor T2 may be 1:4 to 1:1.
  • the channel width of the first transistor T1 and the channel width of the second transistor T2 are 5 ⁇ m
  • the channel length of the first transistor T1 and the channel length of the second transistor T2 are 5 ⁇ m to 20 ⁇ m
  • the channel width-to-length ratio is 5/20 to 5/5 accordingly
  • the channel width of the first transistor T1 and the channel width of the second transistor T2 are 3 ⁇ m
  • the channel length of the first transistor T1 and the channel length of the second transistor T2 are 3 ⁇ m to 12 ⁇ m
  • the channel width-to-length ratio is 3/12 to 3/3 accordingly.
  • the first transistor T1 and the second transistor T2 may also be amorphous silicon (a-Si) transistors, and the channel width-to-length ratio of the first transistor T1 and the channel width-to-length ratio of the second transistor T2 may be 3:5 to 10:3.
  • a-Si amorphous silicon
  • the channel width of the first transistor T1 and the channel length of the second transistor T2 are 5 ⁇ m
  • the channel width of the first transistor T1 and the channel width of the second transistor T2 are 3 ⁇ m to 10 ⁇ m
  • the corresponding channel width-to-length ratio is 3/5 to 10/5
  • the channel width of the first transistor T1 and the channel length of the second transistor T2 are 3 ⁇ m
  • the channel width of the first transistor T1 and the channel width of the second transistor T2 are 3 ⁇ m to 10 ⁇ m
  • the corresponding channel width-to-length ratio is 3/3 to 10/3.
  • the channel width-to-length ratio of the transistor is not limited by the shape of the active layer, so the active layer of the transistor may be an I-shaped shape as shown in FIG. 3 and FIG. 4, or may be a U-shaped shape, an L-shaped shape, etc.
  • the transistor design can be simplified, so that the channel width-to-length ratio of the first transistor T1 is the same, and the channel width-to-length ratio of the second transistor T2 is different; in other words, by adjusting the channel width-to-length ratio of the second transistor T2 in the adjacent sub-pixel SP or the adjacent pixel 101, the ratio of the channel width-to-length ratio of the first transistor T1 and the channel width-to-length ratio of the second transistor T2 in the adjacent sub-pixel SP or the adjacent pixel 101 can be different; without having to simultaneously adjust the channel width-to-length ratio of the first transistor T1 and the channel width-to-length ratio of the second transistor T2 to achieve the purpose of different ratios.
  • the first domain area (for example, a bright pixel) may include a third transistor T3 , a first storage capacitor Cst1 , and a first liquid crystal capacitor Cpx1 formed by a first pixel electrode Px1 and a common electrode Com (which may be located on a counter substrate CF), and the second domain area (for example, a dark pixel) may also include a second storage capacitor Cst2 , and a second liquid crystal capacitor Cpx2 formed by a second pixel electrode Px2 and a common electrode Com; wherein the gate of the third transistor T3 is electrically connected to the gate line 106, the first electrode of the third transistor T3 is electrically connected to the data line 102, the second electrode of the third transistor T3 is electrically connected to the first pixel electrode Px1 and one end of the first storage capacitor Cst1 , and the other end of the
  • the other end of 2 is electrically connected to the common electrode line Vcom.
  • Other elements known to those skilled in the art in the first domain (eg, bright pixel) and the second domain (eg, dark pixel) are not described here and are not intended to limit the present disclosure.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate provided by the embodiment of the present disclosure. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the display device provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned display substrate provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.
  • the display device provided by the embodiment of the present disclosure may further include an opposite substrate 002 located opposite to the display substrate 001, a liquid crystal layer 003 located between the display substrate 001 and the opposite substrate 002, a sealant 004 surrounding the liquid crystal layer 003 between the display substrate 001 and the opposite substrate 002, a first polarizer 005 located on the side of the display substrate 001 away from the liquid crystal layer 003, a second polarizer 006 located on the side of the opposite substrate 002 away from the liquid crystal layer 003, and a backlight module 007 located on the side of the first polarizer 005 away from the display substrate 001.
  • the opposite substrate 002 may include a first base substrate 201, a black matrix 202, a color resist 203, a spacer 204, and a common electrode Com;
  • the display substrate includes transistors (including but not limited to a first transistor T 1 , a second transistor T 2 , and a third transistor T 3 ), a second base substrate 107, a gate insulating layer 108, a passivation layer 109, and the like.
  • the backlight module 007 can be a direct-type backlight module or an edge-type backlight module.
  • the edge-type backlight module may include a light bar, a reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate.
  • the direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film, etc., which are stacked on the light-emitting side of the matrix light source.
  • the reflective sheet includes an opening that is arranged opposite to the position of each lamp bead in the matrix light source.
  • the lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).
  • Submillimeter or even micron-scale micro-LEDs are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting diodes is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare caused by traditional dynamic backlighting between the bright and dark areas of the screen, optimizing the visual experience.
  • OLEDs organic light-emitting diodes
  • the above-mentioned display device may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.
  • the display device includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip.
  • control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like.
  • the control chip may also include a memory, and may also include a power module, and the like, and realize power supply and signal input and output functions through additionally provided wires, lines, and the like.
  • the control chip may also include a hardware circuit and a computer executable code, and the like.
  • the hardware circuit may include a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, and the like.
  • VLSI very large scale integration
  • the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure.
  • the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开提供的显示基板及显示装置，包括阵列排布的多个像素，像素包括多个子像素，子像素包括第一畴区和第二畴区，第一畴区和第二畴区分别具有至少两个取向；多条数据线，数据线与同列子像素的第一畴区、第二畴区电连接；多条放电线，放电线与同列子像素的第二畴区电连接，放电线为相邻两列像素提供至少两种大小不同的直流信号。

Description

显示基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有重量轻、耗电少、画质高、辐射低和携带方便等优点，已逐渐取代传统的阴极射线管显示装置(Cathode Ray Tube display，CRT)，而被广泛应用于现代化信息设备，如增强现实(AR)/虚拟现实(VR)显示设备、笔记本电脑、电视、移动电话和数字产品等。
发明内容
本公开提供的显示基板及显示装置，具体方案如下：
一方面，本公开实施例提供了一种显示基板，包括：
阵列排布的多个像素，所述像素包括多个子像素，所述子像素包括第一畴区和第二畴区，所述第一畴区和所述第二畴区分别具有至少两个取向；
多条数据线，所述数据线与同列所述子像素的所述第一畴区、所述第二畴区电连接；
多条放电线，所述放电线与同列所述子像素的所述第二畴区电连接，所述放电线为相邻两列所述像素提供至少两种大小不同的直流信号。
在一些实施例中，在本公开实施例提供的上述显示基板中，每相邻至少两列所述子像素为一循环周期，同一循环周期内的各列所述子像素分别与提供不同直流信号的所述放电线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多条放电线提供2种不同的直流信号；
每相邻两列所述子像素为一循环周期，同一循环周期内的两列所述子像素分别与提供不同直流信号的所述放电线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多条放电线提供n种不同的直流信号，n为所述像素中全部所述子像素的总数，n大于等于3；
每列所述像素中全部列的所述子像素为一循环周期，同一循环周期内的各列所述子像素分别与提供不同直流信号的所述放电线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多条放电线提供2n种不同的直流信号，n为所述像素中全部所述子像素的总数，n大于等于3；
每相邻两列所述像素中全部列的所述子像素为一循环周期，同一循环周期内的各列所述子像素分别与提供不同直流信号的所述放电线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述多条放电线提供2种不同的直流信号；
每相邻两列所述像素为一循环周期，同一循环周期内的两列所述像素分别与提供不同直流信号的所述放电线电连接，同列所述像素中各列所述子像素与提供相同直流信号的所述放电线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述数据线为同列所述像素中各列所述子像素提供两种极性的数据信号。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括至少两个端子，同一所述端子与提供同一直流信号的所述放电线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括至少两个滤波电路，各所述滤波电路分别连接在所述端子与提供不同直流信号的所述放电线之间。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述滤波电路包括电阻和电容，其中，所述电阻连接在所述端子与所述放电线之间，所述电容连接在所述放电线与地之间。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括栅线，所述第二畴区包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述 栅线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接，所述第二晶体管的栅极与所述栅线电连接，所述第二晶体管的第二极与所述放电线电连接；
在行方向上的相邻所述像素或相邻所述子像素中，所述第一晶体管的沟道宽长比与所述第二晶体管的沟道宽长比的比值不同。
在一些实施例中，在本公开实施例提供的上述显示基板中，在行方向上的相邻所述像素或相邻所述子像素中，所述第一晶体管的沟道宽长比相同，所述第二晶体管的沟道宽长比不同。
另一方面，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示基板。
附图说明
图1为本公开实施例提供的显示基板的一种示意图；
图2为图1所示显示基板的多畴显示光效示意图；
图3为图1所示显示基板的一种结构示意图；
图4为图3中Z区域的放大结构图；
图5为本公开实施例提供的显示基板的又一种示意图；
图6为图5所示显示基板的多畴显示光效示意图；
图7为本公开实施例提供的显示基板的又一种示意图；
图8为图7所示显示基板的多畴显示光效示意图；
图9为本公开实施例提供的显示基板的又一种示意图；
图10为图9所示显示基板的多畴显示光效示意图；
图11为本公开实施例提供的显示基板的又一种示意图；
图12为图3所示显示基板的等效电路图；
图13为本公开实施例提供的显示装置的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本发明内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在下面的描述中，当元件或层被称作“在”另一元件或层“上”或“连接到”另一元件或层时，该元件或层可以直接在所述另一元件或层上、直接连接到所述另一元件或层，或者可以存在中间元件或中间层。当元件或层被称作“设置于”另一元件或层“的一侧”时，该元件或层可以直接在所述另一元件或层的一侧，直接连接到所述另一元件或层，或者可以存在中间元件或中间层。然而，当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”另一元件或层时，不存在中间元件或中间层。术语“和/或”包括一个或更多个相关列出项的任意和全部组合。
随着科学技术的进步，传统的单畴液晶显示屏由于对比度低、视角不对称、不同角度观看显示画面会出现色偏等缺点，已经不能满足人们对液晶显示屏的要求。多畴显示技术逐步发展起来，所谓多畴显示，就是在一个子像素内再分成不同的区域，不同区域的液晶的偏转程度不同，从不同角度观看 液晶显示屏时，都是看到的各个区域的液晶偏转的综合效果，从而降低了因为像素内所有液晶偏转相同带来的不同角度上的对比度差异，进而降低色偏，增大视角。
子像素的畴数越多，色偏效果越好，但增加畴数，往往会降低透过率，因此设计时需综合考虑，在确保透过率时，最大限度提升色偏效果。为提升色偏效果，相关技术中子像素多为8畴设计，具体是将子像素划分为两部分，每个部分为4畴设计，但两部分的像素电位不同，存在明暗差异(明的像素部分称为明像素，暗的像素部分称为暗像素)，从而可实现8畴显示效果。实现8畴显示方案中，明暗像素电位差异的方法有多种，其中一种方案是每个子像素有三个晶体管，一个晶体管控制明像素，两个晶体管控制暗像素，控制明像素的晶体管与数据线(data)电连接，控制暗像素的两个晶体管与数据线(data)和放电线(discharge)分别电连接，通过数据线(data)的电位、放电线(discharge)的电位以及两个晶体管的分压作用，可以使得暗像素的电位小于明像素的电位。然而，全部子像素均接入相同电位的直流信号，致使不同子像素间的8畴显示效果几乎无差异，色偏效果不佳时，可调范围有限。
为了改善相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图1至图2所示，包括：
阵列排布的多个像素101，像素101包括多个子像素SP，子像素SP包括第一畴区(例如明像素)和第二畴区(例如暗像素)，第一畴区(例如明像素)和第二畴区(例如暗像素)分别具有至少两个取向；
多条数据线102，数据线102与同列子像素SP的第一畴区(例如明像素)、第二畴区(例如暗像素)电连接；
多条放电线103，放电线103与同列子像素SP的第二畴区(例如暗像素)电连接，放电线103为相邻两列像素101提供至少两种大小不同的直流信号；可选地，本公开中放电线103的直流信号可以大于0且小于等于15V，例如5V、8V、9V等。
在本公开实施例提供的上述显示基板中，相邻两列像素101接入至少两 种大小不同的直流信号的情况下，可以使得相邻两列像素101的第二畴区(例如暗像素)的呈现出至少两种多畴显示效果，可近似等效为增加了畴(Domain)的数量，从而可以较好的改善色偏。
在一些实施例中，第一畴区(例如明像素)的取向总数可以和第二畴区(例如暗像素)的取向总数相同，例如在图2中第一畴区(例如明像素)和第二畴区(例如暗像素)分别具有四个取向；在另一些实施例中，第一畴区(例如明像素)的取向总数和第二畴区(例如暗像素)的取向总数可以不同，例如第一畴区(例如明像素)具有两个取向，第二畴区(例如暗像素)具有四个取向。当然，第一畴区(例如明像素)的取向总数和第二畴区(例如暗像素)的取向总数并不局限于2个或4个，还可以为其他数量(例如3个)，在此不做限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1至图8所示，每相邻至少两列子像素SP为一循环周期，同一循环周期内的各列子像素SP分别与提供不同直流信号的放电线103电连接，以使得同一循环周期内各列子像素SP的第二畴区(例如暗像素)的多畴显示效果不同，可近似等效为增加了畴(Domain)的数量，从而可以更好的改善色偏。可选地，各循环周期内对应相同位置的子像素SP所在列分别连接的放电线103可汇聚在一起，以节约为放电线103提供信号的端子数量。
在一些实施例中，如图1所示，多条放电线103提供2种不同的直流信号；每相邻两列子像素SP为一循环周期，同一循环周期内的两列子像素SP分别与提供不同直流信号的放电线103电连接。为便于理解，图1中将两种不同直流信号对应的放电线103分别标记为第一放电线1031和第二放电线1032，并将同一循环周期内的两列子像素SP分别标记为第一列子像素SP 1和第二列子像素SP 2，其中，第一列子像素SP 1与第一放电线1031电连接，第二列子像素SP 2与第二放电线1032电连接。在此实施例下，如图2所示，由于第一放电线1031提供的直流信号与第二放电线1032提供的直流信号不同，因此，第一列子像素SP 1中第二畴区(例如暗像素)表现出一种多畴显示效果， 第二子像素列SP 2中第二畴区(例如暗像素)表现出另一种多畴显示效果，相较于相关技术中第一列子像素SP 1中第二畴区(例如暗像素)与第二子像素列SP 2中第二畴区(例如暗像素)表现出相似的暗态多畴显示效果，本公开有效丰富了多畴显示效果，更利于改善色偏。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图5和图6所示，多条放电线103提供n种不同的直流信号，n为像素中子像素的总数，n大于等于3；每列像素P中列的子像素SP为一循环周期，同一循环周期内的各列子像素SP分别与提供不同直流信号的放电线103电连接。为便于理解，图5以每列像素P具有3列子像素SP(例如分别为红色子像素R所在列、绿色子像素G所在列和蓝色子像素B所在列)，多条放电线103提供3种直流信号为例进行了示意。示例性地，图5中将3种直流信号对应的放电线103分别标记为第一放电线1031、第二放电线1032和第三放电线1033，并将同一循环周期内的3列子像素SP分别标记为第一列子像素SP 1、第二列子像素SP 2和第三列子像素SP 3，其中，第一列子像素SP 1与第一放电线1031电连接，第二列子像素SP 2与第二放电线1032电连接，第三列子像素SP 3与第三放电线1033电连接。在此实施例下，如图6所示，由于第一放电线1031提供的直流信号、第二放电线1032提供的直流信号、以及第三放电线1033提供的直流信号均不同，因此，第一列子像素SP 1中第二畴区(例如暗像素)表现出第一种多畴显示效果，第二子像素列SP 2中第二畴区(例如暗像素)表现出第二种多畴显示效果，第三子像素列SP 3中第二畴区(例如暗像素)表现出第三种多畴显示效果，相较于相关技术中第一列子像素SP 1中第二畴区(例如暗像素)、第二子像素列SP 2中第二畴区(例如暗像素)与第三子像素列SP 3中第二畴区(例如暗像素)表现出相似的暗态多畴显示效果，本实施例进一步丰富了多畴显示效果，更利于改善色偏。并且，该实施例还实现了对红色子像素R、绿色子像素G和蓝色子像素B的多畴显示效果的分开控制。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图7和图8所示，多条放电线103提供2n种不同的直流信号，n为像素101中子像素SP 的总数，n大于等于3；每相邻两列像素101中列的子像素SP为一循环周期，同一循环周期内的各列子像素SP分别与提供不同直流信号的放电线103电连接。为便于理解，图7以每列像素P具有3列子像素SP(例如分别为红色子像素R所在列、绿色子像素G所在列和蓝色子像素B所在列)，多条放电线103提供6种直流信号为例进行了示意。示例性地，图7中将6种直流信号对应的放电线103分别标记为第一放电线1031、第二放电线1032、第三放电线1033、第四放电线1034、第五放电线1035和第六放电线1036，并将同一循环周期内的6列子像素SP分别标记为第一列子像素SP 1、第二列子像素SP 2、第三列子像素SP 3、第四列子像素SP 4、第五列子像素SP 5和第六列子像素SP 6，其中，第一列子像素SP 1与第一放电线1031电连接，第二列子像素SP 2与第二放电线1032电连接，第三列子像素SP 3与第三放电线1033电连接，第四列子像素SP 4与第四放电线1034电连接，第五列子像素SP 5与第五放电线1035电连接，第六列子像素SP 6与第六放电线1036电连接。在此实施例下，如图8所示，由于第一放电线1031提供的直流信号、第二放电线1032提供的直流信号、第三放电线1033提供的直流信号、第四放电线1034提供的直流信号、第五放电线1035提供的直流信号、第六放电线1036提供的直流信号均不同，因此，第一列子像素SP 1中第二畴区(例如暗像素)表现出第一种多畴显示效果，第二子像素列SP 2中第二畴区(例如暗像素)表现出第二种多畴显示效果，第三子像素列SP 3中第二畴区(例如暗像素)表现出第三种多畴显示效果，第四列子像素SP 4中第二畴区(例如暗像素)表现出第一种多畴显示效果，第五子像素列SP 5中第二畴区(例如暗像素)表现出第二种多畴显示效果，第六子像素列SP 6中第二畴区(例如暗像素)表现出第三种多畴显示效果，相较于相关技术中第一列子像素SP 1中第二畴区(例如暗像素)、第二子像素列SP 2中第二畴区(例如暗像素)、第三子像素列SP 3中第二畴区(例如暗像素)、第四列子像素SP 4中第二畴区(例如暗像素)、第五子像素列SP 5中第二畴区(例如暗像素)、第六子像素列SP 6中第二畴区(例如暗像素)表现出相似的暗态多畴显示效果，本实施例进一步丰富了多畴显示效果，更利于改善色偏。
在一些实施例中，数据线102为同列像素101中各列子像素SP提供两种极性的数据信号。继续参见图7可见，一列像素101包括3列子像素SP，3列子像素SP可以加载2个正极性(+)数据信号和1个负极性(-)数据信号，或者，3列子像素SP可以加载2个负极性数据信号和1个正极性数据信号。示例性地，在图7所示一个循环周期内，两列像素101中的第一列子像素SP 1、第二列子像素SP 2、第三列子像素SP 3、第四列子像素SP 4、第五列子像素SP 5和第六列子像素SP 6可分别加载正极性数据信号、负极性数据信号、正极性数据信号、负极性数据信号、正极性数据信号和负极性数据信号，或者，还可以分别加载正极性数据信号、负极性数据信号、负极性数据信号、正极性数据信号、正极性数据信号和负极性数据信号。在该实施例中，不但可以对红色子像素R、绿色子像素G和蓝色子像素B的多畴显示效果分开控制，而且实现了对加载正极性数据信号和负极性数据信号的子像素SP的分开控制。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图9和图10所示，多条放电线103提供2种不同的直流信号；每相邻两列像素101为一循环周期，同一循环周期内的两列像素101分别与提供不同直流信号的放电线103电连接，同列像素101中各列子像素SP与提供相同直流信号的放电线103电连接。为便于理解，图9以每列像素101具有3列子像素SP(例如分别为红色子像素R所在列、绿色子像素G所在列和蓝色子像素B所在列)为例进行了示意。示例性地，图9中将2种直流信号对应的放电线103分别标记为第一放电线1031和第二放电线1032，并将同一循环周期内的2列像素101中的各列子像素SP分别标记为第一列子像素SP 1、第二列子像素SP 2、第三列子像素SP 3、第四列子像素SP 4、第五列子像素SP 5和第六列子像素SP 6，其中，其中一列像素101中的第一列子像素SP 1、第二列子像素SP 2、第三列子像素SP 3均与第一放电线1031电连接，另一列像素101中的第四列子像素SP 4、第五列子像素SP 5、第六列子像素SP 6均与第二放电线1032电连接。在此实施例下，如图10所示，由于第一放电线1031提供的直流信号与第二放电线1032提供的直流信号不同，因此，第一列子像素SP 1中第二畴区(例如 暗像素)、第二子像素列SP 2中第二畴区(例如暗像素)、第三子像素列SP 3中第二畴区(例如暗像素)表现出一种多畴显示效果，第四列子像素SP 4中第二畴区(例如暗像素)、第五子像素列SP 5中第二畴区(例如暗像素)、第六子像素列SP 6中第二畴区(例如暗像素)表现出又一种多畴显示效果，相较于相关技术中第一列子像素SP 1中第二畴区(例如暗像素)、第二子像素列SP 2中第二畴区(例如暗像素)、第三子像素列SP 3中第二畴区(例如暗像素)、第四列子像素SP 4中第二畴区(例如暗像素)、第五子像素列SP 5中第二畴区(例如暗像素)、第六子像素列SP 6中第二畴区(例如暗像素)表现出相似的暗态多畴显示效果，本实施例通过对奇偶列像素101的分别控制，有效丰富了多畴显示效果，利于改善色偏。
需要说明的是，本公开中以直流信号的种类在2～6之间为例进行了说明，可根据不同需求选择不同数量的直流信号。并且，本公开中直流信号为直流信号，同公共电压信号类似，正常情况下6种不同大小的直流信号已足够使用，太多情况下，控制困难，且成本增加，因此，本公开仅以6种以下的直流信号为了进行了示例说明。但在一些实施例中，也可以设置更多(例如7种以上)大小不同的直流信号，在此不做限定。另外，在本公开中不同直流信号的放电线103电连接的子像素SP所在列或像素101所在列交替设置，使得在比较小的范围内形成两种不同多畴显示效果的第二畴区(例如暗像素)，在与第一畴区(例如明像素)形成的多畴显示效果综合后的整体多畴显示效果是均匀的，不会出现分屏现象。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图11所示，还可以包括至少两个端子104，同一端子104与提供相同直流信号的放电线103电连接，以通过同一端子104为同种直流信号的各放电线103统一加载信号，便于减小端子104的数量。继续参见图1可见，本公开还可以包括至少两个滤波电路105，各滤波电路105分别连接在至少两个端子104与提供不同直流信号的放电线103之间，以通过滤波电路105确保放电线103上电位固定的直流信号更加稳定可靠，降低数据线102上的交流信号对放电线103上 直流信号的干扰。可选地，如图11所示，滤波电路105可以包括电阻r和电容c，其中，电阻r连接在端子104与放电线103之间，电容c连接在放电线103与地之间，这种滤波电路105的结构比较简单，所需布设空间较小，利于产品的窄边框设计。当然，在一些实施例中，滤波电路105还可以具有本领域技术人员公知的其他结构，在此不做具体限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3、图4和图12所示，还可以包括栅线106，第二畴区(例如暗像素)包括第一晶体管T 1和第二晶体管T 2，第一晶体管T 1的栅极与栅线106电连接，第一晶体管T 1的第一极与数据线102电连接，第一晶体管T 1的第二极与第二晶体管T 2的第一极电连接，第二晶体管T 2的栅极与栅线106电连接，第二晶体管T 2的第二极与放电线103电连接；在行方向上的相邻子像素SP或相邻像素101中，第一晶体管T 1的沟道宽长比与第二晶体管T 2的沟道宽长比的比值不同。连接在数据线102与放电线103之间的第一晶体管T 1和第二晶体管T 2可等效为两个电阻，理想情况下第一畴区(例如明像素)的电位和第二畴区(例如暗像素)的电位可以通过数据线102的电位、放电线103的电位以及第一晶体管T 1和第二晶体管T 2的电阻分压公式进行换算。假如，第一晶体管T 1的沟道宽长比和第二晶体管T 2的沟道宽长比的比值(可等效为二者的电阻比值)为1:1，数据线102的数据信号为10V，放电线103的直流信号为5V，通过电阻分压公式，第二畴区(例如暗像素)的电位就是7.5V，第一畴区(例如明像素)的电位等于数据线102的电位10V，这样第一畴区(例如明像素)和第二畴区(例如暗像素)就会存在2.5V压差，表现出明暗不同的多畴显示效果。在相邻像素101或子像素SP的第二畴区(例如暗像素)中，第一晶体管T 1的沟道宽长比和第二晶体管T 2的沟道宽长比的比值不同的情况下，即可使得相邻像素101或子像素SP的第二畴区(例如暗像素)表现出不同效果的多畴显示，利于改善色偏。在与提供不同直流信号的放电线103结合后，可以更加充分发挥出不同直流信号的多畴显示效果，更好的改善色偏。
在一些实施例中，为了形成较好的多畴显示效果，第一晶体管T 1的沟道 宽长比和第二晶体管T 2的沟道宽长比的比值可以在1～5的范围内。可选地，第一晶体管T 1和第二晶体管T 2可以为氧化物(例如铟镓锌氧化物IGZO)晶体管，第一晶体管T 1的沟道宽长比和第二晶体管T 2的沟道宽长比可以为1:4～1:1。例如，第一晶体管T 1的沟道宽和第二晶体管T 2的沟道宽为5μm，第一晶体管T 1的沟道长和第二晶体管T 2的沟道长为5μm～20μm，相应地沟道宽长比为5/20～5/5；或者，第一晶体管T 1的沟道宽和第二晶体管T 2的沟道宽为3μm，第一晶体管T 1的沟道长和第二晶体管T 2的沟道长为3μm～12μm，相应地沟道宽长比为3/12～3/3。可选地，第一晶体管T 1和第二晶体管T 2还可以为非晶硅(a-Si)晶体管，第一晶体管T 1的沟道宽长比和第二晶体管T 2的沟道宽长比可以为3:5～10:3。例如，第一晶体管T 1的沟道宽和第二晶体管T 2的沟道长为5μm，第一晶体管T 1的沟道宽和第二晶体管T 2的沟道宽为3μm～10μm，相应地沟道宽长比为3/5～10/5；或者，第一晶体管T 1的沟道宽和第二晶体管T 2的沟道长为3μm，第一晶体管T 1的沟道宽和第二晶体管T 2的沟道宽为3μm～10μm，相应地沟道宽长比为3/3～10/3。需要说明的是，晶体管的沟道宽长比并不受有源层的形状限制，因此晶体管的有源层可以是图3和图4所示的I字型，也可以为U型、L型等。
在一些实施例中，在本公开实施例提供的上述显示基板中，在行方向上的相邻子像素SP或相邻像素101中，在保证第一晶体管T 1的沟道宽长比和第二晶体管T 2的沟道宽长比的比值不同的情况下，简化晶体管设计，可以使得第一晶体管T 1的沟道宽长比相同，第二晶体管T 2的沟道宽长比不同；换言之可通过调节相邻子像素SP或相邻像素101中第二晶体管T 2的沟道宽长比，来使得在相邻子像素SP或相邻像素101中第一晶体管T 1的沟道宽长比和第二晶体管T 2的沟道宽长比的比值不同；而不用同时调节第一晶体管T 1的沟道宽长比和第二晶体管T 2的沟道宽长比来达到比值不同的目的。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3、图4和图12所示，第一畴区(例如明像素)可以包括第三晶体管T 3、第一存储电容Cst 1、由第一像素电极Px 1与公共电极Com(可位于对向基板CF上)形成 的第一液晶电容Cpx 1，第二畴区(例如暗像素)还可以包括第二存储电容Cst 2、以及由第二像素电极Px 2与公共电极Com形成的第二液晶电容Cpx 2；其中，第三晶体管T 3的栅极与栅线106电连接，第三晶体管T 3的第一极与数据线102电连接，第三晶体管T 3的第二极与第一像素电极Px 1、第一存储电容Cst 1的一端电连接，第一存储电容Cst 1的另一端与公共电极线Vcom电连接；第二像素电极Px 2、以及第一存储电容Cst 1的一端均连接在第一晶体管T 1的第二极与第二晶体管T 2的第一极的连接位置，第二存储电容Cst 2的另一端与公共电极线Vcom电连接。对于第一畴区(例如明像素)和第二畴区(例如暗像素)内本领域技术人员公知的其他元件，在此不做赘述，也不作为对本公开的限制。
基于同一发明构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示基板，由于该显示装置解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
在一些实施例中，如图13所示，本公开实施例提供的上述显示装置还可以包括与显示基板001相对位置的对向基板002，位于显示基板001和对向基板002之间的液晶层003，在显示基板001和对向基板002之间包围液晶层003的密封胶004，位于显示基板001远离液晶层003一侧的第一偏光片005，位于对向基板002远离液晶层003一侧的第二偏光片006，以及位于第一偏光片005远离显示基板001一侧的背光模组007。可选地，对向基板002可以包括第一衬底基板201、黑矩阵202、色阻203、隔垫物204和公共电极Com；显示基板包括晶体管(包括但不限于第一晶体管T 1、第二晶体管T 2和第三晶体管T 3)、第二衬底基板107、栅绝缘层108、钝化层109等。
在一些实施例中，背光模组007可以为直下式背光模组，也可以为侧入式背光模组。可选地，侧入式背光模组可以包括灯条、层叠设置的反射片、导光板、扩散片、棱镜组等，灯条位于导光板厚度方向的一侧。直下式背光模组可以包括矩阵光源、在矩阵光源出光侧层叠设置的反射片、扩散板和增 亮膜等，反射片包括与矩阵光源中各灯珠的位置正对设置的开孔。灯条中的灯珠、矩阵光源中的灯珠可以为发光二极管(LED)，例如微型发光二极管(Mini LED、Micro LED等)。
亚毫米量级甚至微米量级的微型发光二极管和有机发光二极管(OLED)一样属于自发光器件。其与有机发光二极管一样，有着高亮度、超低延迟、超大可视角度等一系列优势。并且由于无机发光二极管发光是基于性质更加稳定、电阻更低的金属半导体实现发光，因此它相比基于有机物实现发光的有机发光二极管来说，有着功耗更低、更耐高温和低温、使用寿命更长的优势。且在微型发光二极管作为背光源时，能够实现更精密的动态背光效果，在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区域之间造成的眩光现象，优化视觉体验。
在一些实施例中，本公开实施例提供的上述显示装置可以为：投影仪、3D打印机、虚拟现实设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员 可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (13)

  1. 一种显示基板，其中，包括：
    阵列排布的多个像素，所述像素包括多个子像素，所述子像素包括第一畴区和第二畴区，所述第一畴区和所述第二畴区分别具有至少两个取向；
    多条数据线，所述数据线与同列所述子像素的所述第一畴区、所述第二畴区电连接；
    多条放电线，所述放电线与同列所述子像素的所述第二畴区电连接，所述放电线为相邻两列所述像素提供至少两种直流信号。
  2. 如权利要求1所述的显示基板，其中，每相邻至少两列所述子像素为一循环周期，同一循环周期内的各列所述子像素分别与提供不同直流信号的所述放电线电连接。
  3. 如权利要求2所述的显示基板，其中，所述多条放电线提供2种不同的直流信号；
    每相邻两列所述子像素为一循环周期，同一循环周期内的两列所述子像素分别与提供不同直流信号的所述放电线电连接。
  4. 如权利要求2所述的显示基板，其中，所述多条放电线提供n种不同的直流信号，n为所述像素中全部所述子像素的总数，n大于等于3；
    每列所述像素中全部列的所述子像素为一循环周期，同一循环周期内的各列所述子像素分别与提供不同直流信号的所述放电线电连接。
  5. 如权利要求2所述的显示基板，其中，所述多条放电线提供2n种不同的直流信号，n为所述像素中全部所述子像素的总数，n大于等于3；
    每相邻两列所述像素中全部列的所述子像素为一循环周期，同一循环周期内的各列所述子像素分别与提供不同直流信号的所述放电线电连接。
  6. 如权利要求1所述的显示基板，其中，所述多条放电线提供2种不同的直流信号；
    每相邻两列所述像素为一循环周期，同一循环周期内的两列所述像素分 别与提供不同直流信号的所述放电线电连接，同列所述像素中各列所述子像素与提供相同直流信号的所述放电线电连接。
  7. 如权利要求1～6任一项所述的显示基板，其中，所述数据线为同列所述像素中各列所述子像素提供两种极性的数据信号。
  8. 如权利要求1～7任一项所述的显示基板，其中，还包括至少两个端子，同一所述端子与提供同一直流信号的所述放电线电连接。
  9. 如权利要求8所述的显示基板，其中，还包括至少两个滤波电路，各所述滤波电路分别连接在所述至少两个端子与提供不同直流信号的所述放电线之间。
  10. 如权利要求9所述的显示基板，其中，所述滤波电路包括电阻和电容，其中，所述电阻连接在所述端子与所述放电线之间，所述电容连接在所述放电线与地之间。
  11. 如权利要求1～10任一项所述的显示基板，其中，还包括栅线，所述第二畴区包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述栅线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接，所述第二晶体管的栅极与所述栅线电连接，所述第二晶体管的第二极与所述放电线电连接；
    在行方向上的相邻所述像素或相邻所述子像素中，所述第一晶体管的沟道宽长比与所述第二晶体管的沟道宽长比的比值不同。
  12. 如权利要求11所述的显示基板，其中，在行方向上的相邻所述像素或相邻所述子像素中，所述第一晶体管的沟道宽长比相同，所述第二晶体管的沟道宽长比不同。
  13. 一种显示装置，其中，包括如权利要求1～12任一项所述的显示基板。
PCT/CN2022/128416 2022-10-28 2022-10-28 显示基板及显示装置 WO2024087220A1 (zh)

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