WO2024085098A1 - Procédé de fabrication d'éléments gsr - Google Patents

Procédé de fabrication d'éléments gsr Download PDF

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Publication number
WO2024085098A1
WO2024085098A1 PCT/JP2023/037313 JP2023037313W WO2024085098A1 WO 2024085098 A1 WO2024085098 A1 WO 2024085098A1 JP 2023037313 W JP2023037313 W JP 2023037313W WO 2024085098 A1 WO2024085098 A1 WO 2024085098A1
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Prior art keywords
groove
forming
resin film
magnetic wire
asic
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PCT/JP2023/037313
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English (en)
Japanese (ja)
Inventor
工藤一恵
田辺淳一
本蔵義信
本蔵晋平
菊池永喜
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マグネデザイン株式会社
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Priority claimed from JP2022166553A external-priority patent/JP7207676B1/ja
Priority claimed from JP2022166551A external-priority patent/JP7203400B1/ja
Priority claimed from JP2022197538A external-priority patent/JP7329782B1/ja
Application filed by マグネデザイン株式会社 filed Critical マグネデザイン株式会社
Publication of WO2024085098A1 publication Critical patent/WO2024085098A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

Definitions

  • the present invention relates to a method for manufacturing a GSR element through an integration process of a magnetic field detection element and an application specific integrated circuit (hereinafter referred to as ASIC).
  • ASIC application specific integrated circuit
  • High-sensitivity magnetic sensors include Hall sensors, GMR sensors, TMR sensors, high-frequency carrier sensors, FG sensors, MI sensors, GSR sensors, etc.
  • Hall sensors, GMR sensors, TMR sensors, and carrier sensors have been made smaller and thinner by integrating the element with an ASIC, but improving detection sensitivity remains an issue.
  • FG sensors, MI sensors, and GSR sensors have high sensitivity, but the element and ASIC are arranged separately and joined by wire bonding, making it difficult to reduce the thickness and size of the sensors.
  • Patent Document 1 discloses a thin, highly sensitive magnetic sensor in which an insulating resist is applied to the ASIC surface, a groove is formed therein in which a magnetic wire is disposed, and a GSR element consisting of a magnetic wire, a detection coil surrounding the magnetic wire, and electrodes is integrally formed on the ASIC surface.
  • a GSR element consisting of a magnetic wire, a detection coil surrounding the magnetic wire, and electrodes is integrally formed on the ASIC surface.
  • alignment marks are formed on a SiO2 film made on a flat portion, so there are no problems with visibility.
  • Methods for forming alignment marks are also disclosed in Patent Documents 2, 3, and 4, but none of them form alignment marks on photosensitive resin.
  • Another issue is to investigate technology for forming highly visible alignment marks on photosensitive resin.
  • the first problem is how to form the inverted trapezoidal groove.
  • an insulating film such as SiO2
  • a groove is created by RIE
  • the shape of the groove will be rectangular, so we investigated using resist to form the groove only through the photolithography process.
  • epoxy-based negative type resists hereinafter referred to as negative resists
  • the characteristic of negative resists is that the edges after patterning are steep, and even after the curing heat treatment to leave the structure, the groove remains rectangular, with no change in shape. Therefore, we found that it is difficult to form a lower coil along the groove using negative resist.
  • the second problem is the method of forming the alignment marks.
  • it is necessary to reduce the coil pitch to 5 ⁇ m or less and increase the number of turns of the coil, but the finer the coil pitch, the more accurately it is required to align the position of the ASIC board and the positions of the multiple masks. Therefore, the inventors came up with the idea of forming alignment marks and grooves at the same time.
  • alignment marks are formed on SiO2, a substrate protective film, but to form them simultaneously with grooves, they must be formed on a resin coating.
  • the surface of an ASIC substrate may have unevenness of 2 to 3 ⁇ m caused by the integrated circuit. In this case, even if a resin coating of the thickness required for groove formation (approximately 5 to 15 ⁇ m) is applied, the unevenness is transferred to the surface, making it difficult to obtain the flat surface required for alignment mark formation, as on SiO2.
  • the finer the coil pitch the more accurate alignment of the upper and lower coils is required, necessitating an auto-alignment mechanism with advanced alignment functions.
  • the auto-alignment mechanism depends on the contrast of the alignment mark image. As mentioned above, if there are irregularities on the surface of the ASIC board, the signal will be disturbed and the contrast of the mark image will be distorted, as shown in Figure 43. Therefore, if the mark is misrecognized and an attempt is made to form a fine coil with a coil pitch of 5 ⁇ m or less, the connection positions of the two will be misaligned when forming the upper coil after forming the lower coil, resulting in a problem of poor coil connection.
  • the third problem is that the grooves become asymmetrical when a process for forming an inverted trapezoid groove is examined using a positive resist resin film instead of a negative resist.
  • the ASIC substrate already has integrated circuit wiring and the layout of the electrode extraction openings and the like is already determined, so there is a limit to the location where linear grooves 431 for arranging the magnetic wires can be formed, as shown in Fig. 4(a).
  • the electrode extraction portions 421 of the ASIC substrate near the location where the linear grooves for arranging the wires are formed become asymmetrical with respect to the groove.
  • the shape of the upper part of the groove becomes asymmetrical as shown in FIG. 4B.
  • the asymmetrical shape of the upper part of the groove means that the height of the resist forming the groove is different on the left and right sides of the groove.
  • the difference 43H in resist height between the resist 433 on the side close to the electrode extraction opening 432 of the ASIC substrate and the resist 434 on the other side is large, resulting in an asymmetrical groove shape.
  • a common method for flattening the protruding parts of the resist is to use CMP (Chemical-Mechanical Polishing), but because the grooves for placing the magnetic wires are 20 ⁇ m wide or less and 5 to 15 ⁇ m deep, there is a concern that foreign matter may remain in the grooves, making this method difficult to apply.
  • CMP Chemical-Mechanical Polishing
  • the present invention solves these problems by integrating a magnetic field detection element with an application specific integrated circuit (hereinafter referred to as ASIC), 1) First, an inverted trapezoid groove for arranging wires and an alignment mark are simultaneously formed on a resin film on an ASIC substrate. 2) Next, alignment marks with excellent contrast are formed simultaneously with the grooves in order to accommodate the irregularities on the surface of the ASIC substrate and to accommodate further miniaturization. 3) And, the symmetry of the groove shape is improved in correspondence with the electrode extraction opening of the ASIC substrate.
  • the present invention provides a manufacturing method for integrally forming a GSR element having a detection coil formed with a fine coil pitch on an ASIC substrate.
  • a positive resist resin film is applied to the entire surface of the ASIC substrate, and then exposed to light through a mask material and developed, thereby simultaneously forming grooves and recesses for alignment marks. At this time, the groove has a rectangular parallelepiped shape.
  • a curing heat treatment is performed. When the curing heat treatment is performed, the groove changes from a rectangular parallelepiped shape to an inverted trapezoid shape due to the stress generated during the heat treatment. This is the effect of using a positive resist resin coating instead of a SiO2 coating or a negative resist resin coating.
  • the alignment mark recess also becomes inverted trapezoidal, reducing the visibility of the mark.
  • this problem can be solved by protecting the area other than the alignment mark with resist, and using the inverted trapezoid alignment mark itself as a mask to perform RIE processing and dig into the SiO2 on the ASIC surface, thereby making the edges of the digged alignment mark steeper.
  • a negative resist type resin film is applied, exposed to light, and developed to leave the resin film only in the grooves, and a curing heat treatment is performed to form an R shape in the bottom of the groove.
  • a metal film is formed on the entire surface of the ASIC substrate on which the inverted trapezoid groove and the alignment mark recess are formed.
  • the alignment mark recess is covered with the metal film, and this film functions as a reflective film, which further improves the visibility of the alignment mark.
  • This metal film is formed along the inverted trapezoid groove, and by applying a resist thereto and exposing and developing using the alignment mark, the pattern of the lower coil can be formed along the inverted trapezoid groove.
  • the resist is removed and the metal film other than the coil and electrode parts is wetted to form a lower coil with a thickness of 0.2 to 1.0 ⁇ m in the groove.
  • An R part is formed at the bottom of the groove, and the lower coil can be formed without breaking even with fine wiring with a line width of 0.5 to 2 ⁇ m.
  • FIGS. 6A shows the unevenness of the surface of the ASIC substrate 60.
  • FIG. 6B shows that the surface state after applying resist 61 to the areas where the grooves and alignment marks are to be formed and curing is performed has the unevenness of the ASIC substrate surface transferred as is. In this state, as shown in FIG. 3, the alignment mark is obstructed by the uneven mark, making it difficult to align the lower coil and the upper coil.
  • the two-layer resin coating method in Figure 7 involves polishing to remove the irregularities transferred to the first layer of resin 71g, flattening it, and then applying a second layer of resin 72g onto the flat surface and curing it to form grooves 74Gg and alignment marks 74Ag.
  • the first step is to form a first layer by applying a first resin film (negative resist) onto the ASIC substrate with irregularities, then place a flattened first base made of hard resin underneath where the inverted trapezoid groove and alignment mark will be placed, and remove the irregularities that occur in the first resin film.
  • the irregularities on the other parts of the ASIC surface, where the first base is not placed, are left as they will be used as electrode wiring.
  • the second step is to apply a second resin film (positive resist) thicker than the depth of the groove onto the first pedestal to form a second layer, which becomes the second pedestal, and then simultaneously form an inverted trapezoid groove and a recess for an alignment mark in this second pedestal (the second resin film of the second layer), and then deposit a metal film on top of that.
  • a second resin film positive resist
  • the first resin coating layer in the first step is preferably a polyimide-based negative resist because it is preferable to ensure that the top of the base is flat and that the edges of the base have a steep shape.
  • a positive resist can also be used.
  • the second resin coating film, which is the second layer in the second step is applied onto the planarized first pedestal, and it is necessary to use a positive resist in order to form an inverted trapezoidal groove after a curing heat treatment.
  • the alignment mark portion is formed at the same time as the groove portion, so it has an inverted trapezoid shape like the groove portion. Therefore, by using the inverted trapezoid second pedestal itself as a mask and digging into the first pedestal by RIE, the steepness of the alignment mark recess is increased. Furthermore, by using a metal film as a reflective film, it is possible to improve the visibility of the alignment mark. In this way, by adopting a two-layer resin coating, it is possible to remove unevenness that cannot be achieved with a one-layer structure.
  • a first resin film is applied onto the uneven surface of the ASIC substrate to form first pedestals in the groove formation portion and the alignment mark formation portion, but unevenness occurs. Since unevenness remains on the surface of the first pedestal even after the curing heat treatment, it is necessary to flatten the upper surface of the hardened first pedestal by a polishing method such as CMP (Chemical-Mechanical Polishing). This CMP may damage the electrodes of the ASIC, so it is preferable to apply a resist to the entire surface of the ASIC before CMP to protect the ASIC surface other than the pedestal, and then remove the resist with a resist remover after CMP to achieve flattening.
  • CMP Chemical-Mechanical Polishing
  • the groove and alignment mark recess are exposed to light using a mask, developed, and then cured with heat, the groove changes from a rectangular shape to an inverted trapezoid, and the alignment mark recess also changes from a rectangular shape to an inverted trapezoid.
  • This is the effect of using a positive resist resin coating instead of a SiO2 coating. Because the first base has already been flattened, the groove surface and alignment mark portion itself are smooth.
  • the shape of the alignment mark recess also becomes an inverted trapezoid, so in order to make the edges of the alignment mark steeper, the area other than the alignment mark is protected with resist, and the alignment mark area is etched by RIE using the inverted trapezoid second pedestal itself as a mask to engrave the first pedestal.
  • the second pedestal is also a resin coating, the etching selectivity of the RIE is roughly the same. Therefore, the amount of engraving is preferably 0.5 to 1.5 ⁇ m. Below 0.5 ⁇ m, the effect of steepening is small and no improvement in visibility is observed. Above 1.5 ⁇ m, the film loss of the second pedestal is large, affecting visibility.
  • the unevenness on the ASIC board is visible through the first resin and the second resin, making it impossible to ensure the high visibility contrast required for alignment. Therefore, by forming a metal film on the alignment mark to enhance the reflection function, the visibility of the alignment mark can be improved. If the first pedestal is not flattened, the unevenness of the ASIC substrate cannot be eliminated even if a metal film is formed, and sufficient visibility of the alignment mark cannot be ensured. In other words, flattening the pedestal and forming a metal film to enhance the reflection function are essential.
  • a metal film needs to be formed to form the lower coil in the inverted trapezoidal groove, it is desirable to use the same metal film for the alignment mark portion, which enhances the reflective function, and for the lower coil.
  • a negative resist resin film is applied to the groove portion, exposed to light, and developed to leave the resin film only in the groove portion, and an R-shape is formed at the bottom of the groove by a curing heat treatment, thereby preventing breakage of the metal film.
  • the two-layer resin coating method makes it possible to simultaneously form grooves and alignment marks, and to form highly visible alignment marks on the resin coating.
  • the thickness of the first resin film forming the first pedestal of the first layer is preferably three times or more the irregularities (usually about 2 ⁇ m to 3 ⁇ m) of the ASIC surface in order to perform CMP.
  • the film thickness of the second resin in the second layer must be thicker than the minimum groove depth in order to enable groove formation (groove depth of about 5 ⁇ m to 10 ⁇ m).
  • the rectangular parallelepiped groove shape obtained after exposure and development through a mask material becomes asymmetrical at the top of the inverted trapezoid groove formed after curing heat treatment, making it difficult to form a coil, it was thought that this was because, when forming the groove in the positive resist resin film, the electrode extraction portions of the ASIC board are opened at the same time, resulting in a difference in volume of the positive resist resin film on the left and right sides of the groove, and the way they shrink during the curing heat treatment differs.
  • a protective film 62 is formed on the surface of an ASIC substrate 81 .
  • a positive resist resin film 83 is applied to the entire surface of the ASIC substrate 81, and then exposed and developed through a mask material, thereby forming a groove 831, a recess for an alignment mark (not shown), and an opening 832 for extracting electrodes from the ASIC substrate in the resin film 83. If a curing heat treatment is performed in this state, the shape of the groove will be an inverted trapezoid as shown in Figure 8(b), but the upper part of the groove will be asymmetric. Therefore, only the groove portion is subjected to additional exposure once more.
  • the groove 831 becomes an inverted trapezoid as shown in Fig. 8(b), and since additional exposure has been performed, the shape of the upper portion of the groove becomes symmetrical on both sides regardless of the position of the opening in the ASIC substrate.
  • the resist height of the groove resist 833 on the side close to the electrode extraction opening 832 of the ASIC substrate and the resist height of the other groove resist 834 are almost the same, with the difference in resist height on the left and right sides of the groove being 0.2 ⁇ m or less.
  • Figure 9 shows the relationship between the asymmetry of the upper part of the groove (difference in resist height between the left and right sides of the groove: hereafter referred to as left-right difference) when the first exposure dose is 1500 mJ/ cm2 , the groove depth is 8 ⁇ m, and the distance between the groove and the opening for electrode extraction on the ASIC substrate is 50 ⁇ m. Without additional exposure, the difference between the left and right sides was 0.6 ⁇ m. However, with additional exposure, the difference between the left and right sides was minimized at 40 mJ/cm 2 , and with an exposure amount higher than this, the top of the groove on the opposite side became higher.
  • the left-right difference is preferably 0.2 ⁇ m or less, and in this case, the additional exposure amount is in the range of 20 to 60 mJ/ cm2 and the left-right difference is 0.2 ⁇ m or less. In other words, the additional exposure amount is preferably 1 to 4% of the first exposure amount. If it is lower than 1%, the left-right difference at the top of the groove is 0.2 ⁇ m or more, and if it exceeds 4%, the initial left-right difference is reversed, resulting in a left-right difference of 0.2 ⁇ m or more, and the shape of the groove will change.
  • the groove produced by solving the above problems is used to form the coil.
  • a metal film is formed in a groove with an R-shaped bottom, and the entire surface of the substrate is coated with resist, exposed, and developed into a pattern. After plating, the resist is removed and the base film other than the coil pattern is removed to form the lower coil.
  • the magnetic wire is placed in the groove that forms the lower coil with a tension of 30 to 100 kg/mm2, and both ends of the wire are temporarily fixed with adhesive, tape, etc.
  • the magnetic wire is then fixed inside the groove by applying resin, exposing it to light, developing it, and curing it with heat. At this point, both ends of the magnetic wire remain fixed, and by performing the curing heat treatment while maintaining the tension, it is possible to improve the GSR characteristics.
  • the magnetic wire fixed inside the groove is covered with insulating glass, part of the insulating glass covering the magnetic wire is removed to provide wire terminals (both ends of the magnetic wire).
  • hydrofluoric acid treatment is known, but it causes significant damage around the wire terminals and has a significant impact on element formation.
  • glass can be removed by RIE using CF4 gas, and henceforth, glass removal will be performed by RIE.
  • a positive resist resin film is applied to the entire surface of the ASIC board, exposed to light, and developed so that the positive resist resin film remains only in the groove and the magnetic wire, and a curing heat treatment is performed to smooth out the step between the groove and the magnetic wire.
  • negative-type resists are known as resists that are left as structures, but because negative-type resists have sharp edges, the metal film for the upper coil does not adhere well in the next process, raising the risk of breakage. Therefore, we investigated a positive resist resin coating, which is not generally used as a resist that is left as a structure because its shape changes after the curing heat treatment. As a result, the positive resist resin coating can improve the edge shape gently after the curing heat treatment, and can eliminate steps without the risk of disconnection.
  • the upper coil is formed on the magnetic wire and the electrode pattern (including wire terminals and wiring) is formed on the substrate through resist coating, exposure, and development processes. After plating and wet plating, the resist is removed to form the upper coil.
  • the connection part with the lower coil has a gentle shape, and the upper coil can be formed without disconnection, resulting in a detection coil that goes around the magnetic wire.
  • the alignment precision is improved, and the upper coil can be formed without misalignment with the lower coil even with a fine coil pitch.
  • the present invention devisees three new technologies to invent a method for forming elements directly on an ASIC substrate: a method for forming an inverted trapezoidal groove using a positive resist coating, a two-layer resin coating method for forming highly accurate alignment marks on a resin coating, and an additional exposure method for ensuring symmetry in the height of both sides of the groove.
  • the present invention makes it possible to simultaneously form an inverted trapezoidal groove for arranging a magnetic wire with a symmetrical upper shape and a highly visible alignment mark on a photosensitive resin coating without damaging the ASIC substrate, and also improves the symmetry of the groove, making it possible to integrally form a GSR element with a fine coil pitch of 5 ⁇ m or less on the ASIC substrate.
  • FIG. 1 is a diagram showing a groove formed by RIE in a SiO 2 insulating film on an ASIC substrate.
  • FIG. 2 is a diagram showing projections and recesses on the surface of an ASIC board; This figure shows the alignment marks on the surface of an ASIC substrate before the metal film is deposited, and the marks and unevenness signals on the A1-A2 line.
  • 1A is a plan view of an element after an electrode extraction opening and a wire placement groove of an ASIC substrate have been exposed to and developed using a positive resist resin coating
  • FIG. 1B is an A-A' cross-sectional view of the element.
  • 1A shows the shape of a wire placement groove formed in a positive resist resin coating on an ASIC board after exposure and development
  • FIG. 1B shows the groove after a curing heat treatment to form an inverted trapezoid shape.
  • 1A is a cross-sectional view of the uneven state of the ASIC substrate surface
  • FIG. 1B is a cross-sectional view of the state in which the uneven state has been transferred to the resin surface after resin has been applied and cured.
  • This is a cross-sectional view of the grooves and alignment marks after a metal film is formed on an ASIC substrate by the two-layer resin method.
  • 13 shows the shape (a) of a wire placement groove and an opening for electrode extraction of the ASIC substrate after exposure and development of a positive resist resin coating on the ASIC substrate, and a diagram showing the shape (b) of the wire placement groove and the opening for electrode extraction of the ASIC substrate after additional exposure and curing heat treatment of only the wire placement groove portion after exposure and development.
  • 13 is a graph showing the relationship between the amount of additional exposure and the difference between the left and right sides when a positive resist resin film is exposed to light for forming electrode extraction openings and wire placement grooves on an ASIC board, and then developed, and the additional exposure is applied only to the grooves.
  • 1 is a cross-sectional view showing a GSR element fabricated in an inverted trapezoidal groove having an R-shaped bottom on an ASIC substrate.
  • FIG. 1A is a plan view of a groove formation portion and an alignment mark formation portion on an ASIC substrate
  • FIG. 1B is a cross-sectional view taken along line A1-A2.
  • 1 is a cross-sectional view of a GSR element and an alignment mark formed on an ASIC substrate by a two-layer resin coating method.
  • 1A is a plan view showing an inverted trapezoid groove and an alignment mark formed on an ASIC substrate by a two-layer resin coating method
  • FIG. 1B is a cross-sectional view taken along line A1-A2.
  • 1 is a cross-sectional view showing a GSR element produced according to the present invention.
  • FIG. 1 is a diagram showing 2-3 ⁇ m irregularities caused by circuit wiring on the surface of an ASIC substrate.
  • FIG. 13 is a diagram showing a state in which a first pedestal formed in a groove portion and an alignment mark portion is planarized by CMP. 13 is a diagram showing an inverted trapezoidal groove, a recess for an alignment mark, and an opening for extracting electrodes of an ASIC substrate simultaneously formed in the second resin film, and a curing heat treatment is performed after additional exposure only to the groove.
  • 1 is a diagram showing an alignment mark, a mark on the C1-C2 line, and a concave/convex signal after a metal film is formed on an ASIC substrate.
  • FIG. 2 is a plan view of a magnetic field detection element (assembly) and an alignment mark.
  • FIG. 2 is a plan view of a magnetic field detection element.
  • the method for producing a GSR element of the present invention comprises the steps of: A method for manufacturing a GSR element, comprising: a magnetic wire; a detection coil having a coil pitch of 10 ⁇ m or less, which is made up of a lower coil and an upper coil surrounding the magnetic wire; and electrode wiring, the GSR element being directly manufactured on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), (11) A process of applying a positive resist resin film onto the ASIC board, exposing and developing the film to simultaneously form an inverted trapezoid groove for installing the magnetic wire and a plurality of concave portions for alignment marks in the resin film, hardening the film by a curing heat treatment, and after forming the inverted trapezoid groove and the concave portions for alignment marks, applying a negative resist resin film, exposing and developing the film to leave the resin film only in the inverted trapezoid groove portion, and forming an R shape at the bottom of the groove by a curing heat treatment
  • step 14A a step of placing the magnetic wire in the inverted trapezoid groove in which the lower coil is formed while applying tension thereto, temporarily fixing the magnetic wire with resin, and then fixing the magnetic wire by a curing heat treatment; a step of removing insulating glass covering the wire in a wire electrode portion for joining the wire to an electrode wiring by CF 4 -RIE;
  • the present invention is characterized in that it comprises:
  • the GSR element 10 of the present invention is composed of an ASIC substrate 101, a SiO2 protective coating 102 on the ASIC substrate 101, a positive resist 103 coated on the SiO2 protective coating 102, an inverted trapezoidal groove 104 formed in the positive resist 103, a resin coating 100 placed at the bottom of the groove and forming an R-shape at the bottom, a lower coil 105 formed on the surface of the inverted trapezoidal groove 104 and on part of the upper surface of the positive resist 103, a magnetic wire 106 placed on the lower coil, a resin coating 108 that fixes the magnetic wire, a positive resist-based resin coating 109 that eliminates the step between the magnetic wire 106 and the groove 104, and an upper coil 107 formed on the resin coating 109 and connected to the lower coil 105.
  • the magnetic wire 106 is wound around a detection coil consisting of a lower coil 105 and an upper coil 107, and
  • a substrate 110 for forming a GSR element which is an intermediate product of the process of the present invention, will be described with reference to Fig. 11.
  • (a) shows a plan view
  • (b) is a cross-sectional view taken along the line A1-A2 in (a).
  • Fig. 11 shows only one GSR element for explanation.
  • An intermediate product of a GSR element forming substrate 110 is formed, which comprises a groove forming portion 11G consisting of an inverted trapezoid groove 114G for forming a GSR element on an ASIC substrate 111, and an alignment mark portion 11A consisting of an alignment mark recess 114A.
  • the groove forming portion 11G is made up of a positive resist 113G and an inverted trapezoidal groove 114G.
  • the alignment mark portion 11A is made up of a plurality of alignment marks 11a, and its cross section is made up of a positive resist 113A and an alignment mark recess 114A.
  • the metal film in the alignment mark portion functions as a reflective film.
  • the method for producing a GSR element of the present invention comprises the steps of: A method for manufacturing a GSR element, which comprises a detection coil having a coil pitch of 5 ⁇ m or less, which is made up of a magnetic wire, a lower coil and an upper coil surrounding the magnetic wire, and electrode wiring, directly fabricating the GSR element on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), comprising: (21) applying a negative resist-based first resin coating onto the ASIC substrate to form a first base in a groove forming portion and an alignment mark forming portion made of a flat and hard resin; (22) A process of applying a positive resist-based second resin coating thicker than the groove depth onto the first pedestal to form a second pedestal, simultaneously forming a rectangular recess for forming an inverted trapezoid groove (hereinafter referred to as a groove) for arranging the magnetic wire in the groove forming portion of the second pedestal and a recess for forming an alignment mark reces
  • ASIC application specific integrated circuit
  • step 25A placing the magnetic wire on the lower coil in the groove under tension, temporarily fixing the magnetic wire in the groove with resin, and further fixing the magnetic wire in the groove by performing a curing heat treatment while still applying tension; a step of removing insulating glass covering the wire in a wire electrode portion for joining the wire to an electrode wiring by CF 4 -RIE;
  • the present invention is characterized in that it comprises:
  • the grooves and alignment marks can be formed simultaneously in the resin coating, and highly visible alignment marks can be formed on the resin coating, making it possible to integrally form a GSR element consisting of a fine pitch coil on the ASIC substrate.
  • FIG. 12 shows a cross-sectional view of a GSR element manufactured according to the present invention and an alignment mark used in the manufacture.
  • the ASIC substrate 120 has an unevenness 1201 of about 2 to 3 ⁇ m on its surface due to the integrated circuit wiring. Therefore, an alignment mark forming section 123 is required in addition to a normal groove forming section 122.
  • a first seat 1211 is formed on the ASIC 20.
  • an inverted trapezoidal groove 1221 is formed in a second seat 1212 constituting an element.
  • a lower coil 1222 is formed on the surface of the groove 1221, and a magnetic wire 1223 with an insulating glass coating is arranged on the upper part of the lower coil 1222.
  • the magnetic wire is fixed with resin and embedded in the groove 1221.
  • An upper coil 1224 is formed on the magnetic wire 1223 via resin, and is connected to the lower coil 1222 at both ends and wound around the magnetic wire 1223 .
  • Wire electrodes are formed on both ends of the magnetic wire 1223 and both ends of the surrounding coil.
  • a first base 1211 is formed on the ASIC 120.
  • a second base 1212 constituting the alignment mark is formed, which has an alignment mark recess, which is a long, steep, pseudo-inverted trapezoid groove 1231, and a metal film is formed on the surface of the recess.
  • a reflective film made of a metal film is formed on the flat surface.
  • an auto-alignment mechanism enables formation of the lower coil and the upper coil with a coil pitch of 5 ⁇ m or less.
  • the coil pitch is 3 ⁇ m
  • the coil width is 2.0 ⁇ m
  • the coil spacing is 1.0.
  • accuracy of 0.5 ⁇ m or less is required.
  • FIG. 13 is a plan view and a cross-sectional view.
  • 1A is a plan view
  • FIG. 1B is a cross-sectional view taken along line A1-A2 of the plan view of FIG.
  • a groove forming portion 132 and an alignment mark forming portion 133 are formed on an ASIC substrate 130.
  • a second pedestal consisting of an inverted trapezoid groove and a flat surface is formed on a first pedestal 1311 having a flat upper surface.
  • the alignment mark section has an alignment mark recess, which is a long, inverted trapezoidal groove 1331, formed on a first base 1311 with a flat upper surface, and a second base 1312 consisting of a flat surface.
  • the two-layer resin coating method is used to simultaneously form grooves and alignment marks in the resin coating on the ASIC board, and the manufacturing flow for the GSR element consisting of a narrow-pitch coil using highly visible alignment marks is shown in Figure 7 and explained below.
  • the thickness of the first pedestal is 10 ⁇ m in step (1b), and even after the curing heat treatment, it is still about 8 ⁇ m, so there is no problem with CMP.
  • the groove is deformed from a rectangular parallelepiped shape to an inverted trapezoid shape by the stress generated during the curing heat treatment.
  • the upper surface of the second pedestal 72 remains flat.
  • the groove has a depth of 8 ⁇ m.
  • the width of the lower coil is 2.0 ⁇ m, and the thickness is 1.0 ⁇ m.
  • step (2m) to eliminate the step between the groove and the wire, a positive resist resin film is applied, exposed, baked, developed, and cured at 280°C for 1 hour to smooth out the shape of the upper part of the groove. After that, a metal film is formed over the entire ASIC board, and a resist is applied.
  • the upper coil has a width of 2.0 ⁇ m and a thickness of 1.0 ⁇ m.
  • the coil connection portion consisting of the connection portion of the lower coil and the connection portion of the upper coil is formed with a line width of 2.0 ⁇ m and a coil pitch of 3.0 ⁇ m.
  • the method for producing a GSR element of the present invention comprises the steps of: A method for manufacturing a GSR element, comprising: a magnetic wire; a detection coil having a coil pitch of 10 ⁇ m or less, which is made up of a lower coil and an upper coil surrounding the magnetic wire; and electrode wiring, the GSR element being directly manufactured on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), (31) a step of applying a positive resist type resin film (hereinafter referred to as a P-type resin film) onto the ASIC substrate, exposing and developing the film to simultaneously form grooves for disposing the magnetic wires in the P-type resin film and openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate; a step of exposing only the groove portion for arranging the magnetic wire to light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoid groove having
  • ASIC application specific integrated
  • step 31A a step of coating a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for placing the magnetic wires in the P-type resin film, openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate, and alignment marks; and a step of performing additional exposure only on the groove portion for locating the magnetic wire, and then performing a curing heat treatment to harden the P-based resin coating, thereby forming an inverted trapezoidal groove with improved symmetry at the top of the groove.
  • the present invention is characterized in that it comprises:
  • a negative resist-based first resin film (hereinafter referred to as an N-based first resin film) is applied onto the ASIC substrate, exposed to light, and developed. After a curing heat treatment, a planarization treatment is performed to form a flat and hard resin first base in a groove formation portion and an alignment mark formation portion.
  • a step of applying a positive resist-based second resin coating (hereinafter referred to as a P-based second resin coating) having a thickness greater than the depth of the groove on the ASIC substrate to form a second pedestal, and exposing and developing the groove, an opening for electrode extraction of the ASIC substrate (hereinafter referred to as an opening), and the alignment mark on the second pedestal; a step of forming an inverted trapezoidal groove with improved symmetry at the top of the groove by subjecting the second pedestal to additional exposure only in the groove portion and then subjecting the second pedestal to a curing heat treatment;
  • the present invention is characterized in that it comprises:
  • step 31C applying a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for arranging the magnetic wires in the P-type resin film and openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate; a step of exposing only the groove portion for arranging the magnetic wire to additional light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoid groove with improved symmetry at the top of the groove and the opening portion on the ASIC substrate; Further, a process of applying a negative resist type resin film (hereinafter referred to as an N-type resin film) to the ASIC substrate, exposing and developing the N-type resin film so that the N-type resin film remains only in the groove portion of the inverted trapezoidal groove, and forming an R-shape at the bottom of the groove by a
  • step 31A (31D) applying a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for placing the magnetic wires in the P-type resin film, openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate, and alignment marks; a step of exposing only the groove portion for locating the magnetic wire to additional light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoidal groove with improved symmetry at the top of the groove; Further, a process of applying a negative resist type resin film (hereinafter referred to as an N-type resin film) to the ASIC substrate, exposing and developing the N-type resin film so that the N-type resin film remains only in the groove portion of the inverted trapezoidal groove, and forming an R-shape at the bottom of the groove by a curing heat treatment;
  • step 35 after arranging the magnetic wire in the inverted trapezoidal groove, a positive resist resin film is applied to the entire surface of the ASIC substrate, exposed to light, and developed to leave a positive resist resin film (hereinafter referred to as a P-type resin film) only on the groove and the magnetic wire, and a curing heat treatment is performed to smooth out the step between the groove and the magnetic wire; forming a metal film on the entire surface of the ASIC substrate to form the upper coil and the electrode wiring;
  • a method for manufacturing a GSR element comprising the steps of:
  • the amount of exposure when additionally exposing only the groove portion for arranging the magnetic wire is 4% or less of the amount of exposure of the groove portion.
  • the thickness of the N-based first resin coating is at least three times the irregularities on the ASIC substrate.
  • FIG. 14 shows a cross-sectional structure of a magnetic field detection element manufactured according to the present invention.
  • Fig. 14 is a cross-sectional view taken along the line A1-A2 shown in Fig. 13. Also shown is a cross-sectional view of the alignment mark portion 133 shown in Fig. 13.
  • On the ASIC substrate 141 there are irregularities 1411 caused by the integrated circuit, and a protective film 143 is formed on the surface other than the electrode extraction opening 1431.
  • a first seat 1491 is disposed in the groove formation portion, and an inverted trapezoidal groove 142 is formed in the second resin film 1492 without being affected by the irregularities 1411 of the ASIC substrate, and an R-shaped negative resist resin coating 1423 is formed on the bottom of the groove.
  • the magnetic wire 145 is disposed and fixed by the negative resist resin film 1451 .
  • the magnetic wire 145 is covered with insulating glass having a thickness of 1.0 ⁇ m and has a diameter of 12 ⁇ m.
  • a positive resist resin coating 1452 is formed between the groove 142 and the magnetic wire 145 .
  • This positive resist resin coating 1452 also extends over the magnetic wire 145, and the upper coil 146 is formed thereon.
  • the lower coil 144 and the upper coil 146 are connected without any problem because of the positive resist resin coating 1452 and the improved symmetry of the upper part of the groove.
  • the alignment mark portion 149 there are irregularities 1411 on the ASIC substrate 141 caused by the integrated circuit, but the first base 1491 is arranged in the alignment mark portion, and an alignment mark recess 1494 is formed in the second resin film 1492 without being affected by the irregularities 1411 of the ASIC substrate.
  • the alignment mark recess is carved down to the first base, and a reflective film 1493 is further formed on it, improving visibility.
  • the magnetic wire is made of a CoFeSiB-based amorphous alloy, has a diameter of 1 to 15 ⁇ m, and is coated with an insulating film (glass film) having a thickness of 0.5 to 2 ⁇ m.
  • the detection coil is composed of a lower coil, an upper coil and a connection portion, with a coil pitch of 1 to 5 ⁇ m, a coil width of 0.5 to 4.5 ⁇ m, and the thicknesses of the lower and upper coils being 0.1 to 1.0 ⁇ m respectively.
  • the electrode wiring is a general term for external electrodes, electrodes (terminals), and wiring (connection wiring) that connects external electrodes and electrodes (terminals).
  • the external electrodes are input/output electrodes from the GSR element, and in the present invention, are connected to or formed integrally with the electrodes of the ASIC.
  • Electrodes also called terminals
  • the detection coil and the electrode wiring are formed by evaporating or plating a conductive metal such as gold.
  • the ASIC substrate has a predetermined size on which a number of ASICs are formed so that a number of GSR devices can be manufactured. For example, if the size of the ASIC board is 20 mm in length and 20 mm in width, This corresponds to an element substrate consisting of an assembly of elements each consisting of one GSR element and one ASIC, and by dividing the element substrate, it is possible to obtain about 50 to 1500 elements.
  • Steps (31), (31A) to (31D) are steps for forming an inverted trapezoid groove for aligning magnetic wires in the ASIC substrate. 15, unevenness 151 of 2 to 3 ⁇ m due to circuit wiring exists on the surface of the ASIC substrate 150.
  • a protective film 1501 such as SiO2 is formed on the surface of the ASIC substrate 150. Therefore, first, in order to eliminate this step, a first seat is formed in the groove forming portion and the alignment mark recess forming portion.
  • a negative resist-based first resin coating is applied onto the ASIC substrate 150, and exposure and development are performed using a mask material to form a first seat consisting of a groove forming portion for arranging magnetic wires for forming the GSR element and an alignment mark forming portion.
  • a curing heat treatment is performed to harden the first resin film that will become the first base. Even at this point, the unevenness on the ASIC board is transferred and remains on the surface of the first resin film that will become the first base.
  • the temperature for the curing heat treatment is 250 to 350° C. If the temperature is less than 250° C., the curing is insufficient, and there is a concern that the shape may change in a later process, whereas if the temperature exceeds 350° C., there is a concern that problems may occur in the ASIC circuit.
  • the unevenness remaining on the first resin coating of the first base consisting of the groove forming portion and the alignment mark forming portion, where the unevenness has been transferred and hardened is flattened by CMP to form a flat first base 16C consisting of the groove forming portion and the alignment mark forming portion, as shown in FIG. 16.
  • a resist may be applied to the entire surface of the ASIC substrate 160, the resist on the first pedestal may be removed, the surface of the ASIC substrate other than the first pedestal may be protected, CMP may be performed to flatten the first pedestal, and the resist that was protecting the surface of the ASIC substrate other than the first pedestal may be peeled off.
  • the thickness of the first resin coating that forms the first pedestal 16C is preferably at least three times the irregularities 161 on the surface of the ASIC substrate 160 on which the first pedestal is placed. If it is less than three times, the first pedestal itself will become thin before the irregularities of the first pedestal can be flattened by CMP in this process.
  • a positive resist resin film 173 is applied to the entire surface of the ASIC substrate, and exposed and developed through a mask material to form rectangular parallelepiped grooves, concave portions for alignment marks, and openings for electrode extraction of the ASIC substrate in the resin film.
  • the amount of exposure at this time is 1500 mm2.
  • additional exposure is applied only to the grooves.
  • the amount of exposure at this time is 5% or less of the initial exposure amount, that is, 1 to 4%.
  • the shape of the groove 174 becomes an inverted trapezoid, as shown in FIG. 17, and because additional exposure has been performed, the resist height of the resist 177 in the groove closest to the electrode extraction opening 176 of the ASIC board and the resist height of the other resist 178 are symmetrical.
  • the alignment mark recess 17A is formed at the same time as the groove portion 17B, it will have an inverted trapezoid shape like the groove, which may reduce visibility. Therefore, the area other than the alignment mark portion is protected with resist, and the inverted trapezoid alignment mark recess 17A formed in the second resin coating is itself used as a mask to excavate the first pedestal by RIE, thereby increasing the steepness of the alignment mark recess.
  • Step (32) is a step of forming a lower coil in the inverted trapezoidal groove.
  • a negative resist type resin film (hereinafter referred to as an N-type resin film) is applied to the bottom of the groove 174 of the ASIC substrate, exposed to light, and developed so that the N-type resin film remains only in the groove portion, and an R-shape is formed in the bottom of the groove by a curing heat treatment.
  • a metal film is formed on the surface of the ASIC substrate.
  • the film thickness is 0.1 to 1.0 ⁇ m.
  • This metal film also functions as a reflective film 105 in the alignment area, improving the visibility of the alignment marks.
  • the alignment mark formed in this manner and the signal of the mark are shown in Figure 18. There is no noise in the signal portion of the alignment mark, and only the signal of the alignment mark is observed, confirming the improvement in visibility.
  • a resist is applied to the entire surface of the ASIC board, and exposure and development are performed through a mask material to form a coil pattern.
  • the electrode extraction openings of the ASIC board are also opened.
  • the resist is peeled off and the metal film in the non-plated areas is etched.
  • the mask pattern for forming the coil by plating and the mask opening are reversed.
  • Step (33) is a step of arranging and fixing the magnetic wire in the groove.
  • the lower coil is formed along the side of the groove, and the magnetic wire is placed thereon while being subjected to a tension of 30 to 100 kg/mm2.
  • both ends of the magnetic wire are temporarily fixed with adhesive, tape, etc., and then a resin film is applied to the entire surface of the substrate, exposed to light, and developed so that the resin film remains only in the grooves.
  • the magnetic wire is then fixed by a curing heat treatment at a temperature of 250 to 350°C. As a result, the magnetic wire is fixed inside the groove and simultaneously heat-treated while tension is applied thereto, thereby improving the GSR characteristics.
  • Step (34) is a step of partially removing the glass coating covering the magnetic wire in order to contact the magnetic wire with an electrode.
  • resist is applied to the entire surface of the substrate.
  • the resist is opened only at the electrode lead-out portions of the magnetic wires of each element. In other words, everything other than the electrode lead-out portions is protected by resist.
  • CF4-RIE By performing CF4-RIE in this state, it is possible to remove the SiO2 that covers only the electrode lead-out portions of the magnetic wires.
  • the resist is removed, the glass coating is partially removed, and the electrodes can be brought into contact with the magnetic wires. If the magnetic wire is not covered with insulating glass, this step can be omitted.
  • Step (35) is forming the upper coil on the magnetic wire.
  • a positive resist resin film is applied to the entire surface of the ASIC board, exposed to light, and developed so that the positive resist resin film (hereinafter referred to as P-type resin film) remains only in the groove and the magnetic wire portion, and a curing heat treatment is performed to smooth out the stepped portions.
  • a metal film is formed over the entire surface of the substrate. The film thickness is 0.1 to 1.0 ⁇ m.
  • resist is applied to the entire surface of the substrate, and using highly visible alignment marks with an auto-alignment mechanism, exposure and development are performed through a mask material to form a coil pattern.
  • the resist is peeled off and the metal film in the non-plated areas is etched.
  • the mask pattern for forming the coil by plating and the mask opening are reversed. This process prevents breaks in the upper coil and also forms highly visible alignment marks, so there are no problems with aligning it with the lower coil.
  • Step (36) is a step of dividing the element substrate, which is an assembly of elements each including a magnetic wire, a detection coil, and the electrode wiring, into individual pieces.
  • FIG. 19 shows a plan view of an element fabricated on an ASIC substrate according to the present invention.
  • the ASIC board 19 is an assembly of ASIC elements, and for example, a 20 mm square ASIC board is made up of about 300 ASIC elements. Since one magnetic field detection element is formed on one ASIC element, a large number of magnetic field detection elements 19a and alignment marks 19b are arranged on the four corners of the ASIC board 19.
  • the magnetic field detection elements are manufactured on a board-by-board basis, and are finally separated into individual pieces.
  • the magnetic field detection element 20 has an entire surface covered with a second resin coating 201, and has a width (left-right direction) of 1.2 mm, a length (up-down direction) of 1.2 mm, and a thickness of 0.75 mm.
  • An inverted trapezoidal groove 202 and a lower coil 203 are formed on the ASIC board 19, and a magnetic wire 204 is disposed and fixed therein.
  • a detection coil consisting of a lower coil 203 and an upper coil 205 winds around the magnetic wire.
  • the detection coil has a coil pitch of 3.0 ⁇ m, a line width of 1.2 ⁇ m, and a thickness of 1.5 ⁇ m.
  • Two wire terminals 206 are formed on the magnetic wire 204, and wiring 207 and a wire electrode 208 are formed to connect to the wire terminals 206.
  • wiring 203a, 205a and two coil electrodes 209 are formed to connect to the lower coil 203 and the upper coil 205.
  • a first base is placed on the ASIC board using a negative resist resin coating, and then a positive resist resin coating is used on top of that to simultaneously expose and develop the groove for placing the magnetic wire, the recesses for the alignment marks, and the electrode extraction section of the ASIC board.
  • a curing heat treatment is performed to harden the resin coating, forming an inverted trapezoidal groove with symmetrical left and right shapes, making it possible to directly manufacture a GSR element with a fine coil with a narrow pitch on the ASIC board.
  • Step (3a) First, a negative resist-based first resin film is applied to a thickness of 10 ⁇ m on an ASIC board that has unevenness of several ⁇ m caused by the integrated circuit. After exposure and development, a curing heat treatment is performed at 280°C for 1 hour, and a flat and hard first pedestal is placed at the location where the inverted trapezoid groove and alignment mark will be placed. That is, a first pedestal is formed, which is composed of the groove forming portion B and the alignment mark forming portion A. At this time, the thickness of the first pedestal is 9 ⁇ m.
  • Step (3b) In this state, the unevenness of the ASIC substrate is still transferred onto the surface of the first pedestal, so a resist is applied to the entire surface of the ASIC substrate, and a mask material is used to expose and develop the resist, removing only the resist on the first pedestal and protecting the ASIC surface other than the first pedestal. Then, the surface of the first pedestal, which has been hardened by a curing heat treatment, is planarized by CMP (Chemical Mechanical Polishing). Thereafter, the resist protecting the ASIC surface other than the first pedestal is removed with a resist remover to form a flattened first pedestal C. At this time, the film thickness of the first pedestal C is about 6 ⁇ m.
  • Step (3c) Next, a positive resist-based second resin coating is applied to the flattened first base with a thickness of 10 ⁇ m, and the groove, alignment mark recess, and ASIC substrate electrode extraction portion are exposed and developed simultaneously. Since the first base C is flattened, the second base of the groove forming portion B and the alignment mark forming portion A is not affected by the unevenness of the ASIC substrate.
  • the exposure dose at this time is 1500 mJ/ cm2 . Then, only the grooves are exposed again using a mask. This time, the exposure dose is 40 mJ/ cm2 .
  • the grooves change to an inverted trapezoid shape due to the stress generated during the heat treatment, and the shape of the upper part of the groove becomes almost symmetrical.
  • the shape and height of the upper part of the groove near the opening are almost the same as that of the upper part of the other groove, and the asymmetry is greatly improved.
  • Step (3d) Next, a negative resist resin film is applied to the entire ASIC board, exposed to light, and developed to leave the resist only in the grooves. After that, a curing heat treatment is performed at 250°C for 1 hour to form an R shape at the bottom of the groove.
  • Step (3e) On the other hand, since the alignment mark portion also has an inverted trapezoidal shape, in order to make the shape steeper, the area other than the alignment mark portion is protected with resist, and the first pedestal is excavated 1 ⁇ m by O 2 -RIE using the inverted trapezoidal alignment mark recess itself formed in the second resin coating as a mask. The protecting resist is then removed with a resist remover.
  • Step (3f) Next, a Cr/Au laminated film is formed over the entire ASIC substrate, with a thickness of 0.01/0.03 ⁇ m. This film is used as a reflective film in the alignment mark recesses to improve visibility. Then, using the alignment mark recesses, resist is applied to the entire ASIC substrate, exposed, and developed. Through plating and etching processes, a lower coil having a width of 1.2 ⁇ m and a thickness of 0.7 ⁇ m is formed along the surface of the inverted trapezoidal groove.
  • Step (3g) Next, a CoFeB magnetic wire covered with 1 ⁇ m thick insulating glass is placed on top of the lower coil in the groove while applying a tension of 76 kg/ mm2 , and temporarily fixed with adhesive, tape, etc. Then, resin is applied, exposed, developed, and cured at 250°C for 1 hour to fix it in the groove. At this time, the magnetic wire 19 is heat-treated while still under tension, which improves the GSR characteristics.
  • Step (3h) Since the surface of the magnetic wire is covered with a glass (SiO 2 ) film, this portion of the glass film is removed in order to bring the electrodes into contact with the magnetic wire.
  • a resist is applied to the entire surface of the ASIC board, and then exposed and developed to open the resist only in the areas where the electrodes are to come into contact with the magnetic wires. After removing the glass coating with CF4-RIE, the resist is peeled off from the entire board.
  • Step (3i) Next, to eliminate the step between the magnetic wire and the groove, a positive resist is applied to the entire ASIC board, exposed to light, and developed, leaving the resist only in the groove, and then the resist is hardened by a curing heat treatment at 250°C for 1 hour. By heat treating the positive resist, the edge shape becomes smooth, preventing breaks when forming the upper coil.
  • Step (3j) a Cr/Au laminated film is formed to a thickness of 0.01/0.03 ⁇ m to form the lead wires of the upper coil and the conductive portion of the magnetic wire, the openings for electrode extraction and the wiring (wiring) of the ASIC board.
  • resist is applied, exposed, and developed to form the upper coil, the lead wire pattern of the conductive part of the magnetic wire, and the opening for the electrode of the ASIC board on the upper part of the magnetic wire.
  • the alignment mark has a first base and a reflective film, so the signal strength is sufficient and it can be aligned with the lower coil by automatic alignment without any problems.
  • This pattern is plated, wet-plated, and then the resist is removed to form an upper coil with a line width of 1.2 ⁇ m and a thickness of 0.8 ⁇ m on top of the magnetic wire.
  • the connection with the lower coil has a gentle shape, and the upper coil is also formed without any breaks.
  • lead lines for the conductive parts of the magnetic wires, openings for electrode extraction of the ASIC board, and wiring are also formed.
  • the first to third inventions make it possible to integrally form a GSR element with a fine pitch coil on an ASIC substrate.
  • the present invention integrates a GSR element with an ASIC to create an ultra-thin, ultra-compact GSR sensor, which is expected to be used in applications that require ultra-compactness and high performance, such as motion devices in living organisms.
  • the present invention can be applied to small, high-performance GSR sensors for use in automobiles or wearable computers.
  • FIG. 170 ASIC substrate subjected to curing heat treatment after additional exposure.
  • 1701 Protective film on the surface of the ASIC substrate 171: Unevenness on the ASIC substrate 17A: Alignment mark recess forming portion, 17B: groove forming portion, 17C: First base 173 after curing heat treatment and flattening
  • CMP Positive resist type second resin coating
  • 174 inverted trapezoid groove
  • 176 ASIC electrode extraction opening
  • 177 Groove resist on the side closer to the opening for extracting the ASIC electrodes
  • 178 Groove resist on the other side

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Abstract

Lors de la formation d'éléments GSR directement sur un substrat de circuit intégré (ASIC), il est difficile de former des micro-bobines en raison d'a) du procédé de formation de rainures trapézoïdales inversées, b) d'une irrégularité de la surface du substrat ASIC, et c) du placement d'ouvertures dans le substrat ASIC. [Solution] a) un film de résine de réserve positive est appliqué sur un substrat ASIC, et est simultanément exposé et développé avec des rainures pour l'installation de fils magnétiques et une pluralité d'évidements de marquage d'alignement pour former des rainures trapézoïdales inversées ; b) les bases primaires sont aplaties par un procédé de résine à deux couches pour éliminer l'irrégularité, et c) une exposition partielle des rainures uniquement, pour l'installation de fils magnétiques, est ajoutée pour former des rainures trapézoïdales inversées et des rainures bilatéralement symétriques. Des éléments GSR comportant un pas de micro-bobine inférieur ou égal à 3 µm peuvent ainsi être fabriqués directement sur des substrats ASIC.
PCT/JP2023/037313 2022-10-17 2023-10-16 Procédé de fabrication d'éléments gsr WO2024085098A1 (fr)

Applications Claiming Priority (6)

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JP2022-166551 2022-10-17
JP2022-166553 2022-10-17
JP2022166553A JP7207676B1 (ja) 2022-10-17 2022-10-17 Ｇｓｒ素子の製造方法
JP2022166551A JP7203400B1 (ja) 2022-10-17 2022-10-17 Ｇｓｒ素子の製造方法
JP2022-197538 2022-12-09
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5246787A (en) * 1975-10-11 1977-04-13 Hitachi Ltd Coil for integrated circuit and process for production of same
JP2004258038A (ja) * 2003-02-25 2004-09-16 Samsung Electronics Co Ltd 磁界検出素子およびその製造方法
WO2010097932A1 (fr) * 2009-02-27 2010-09-02 愛知製鋼株式会社 Élément capteur à magnéto-impédance et son procédé de fabrication
WO2015025606A1 (fr) * 2013-08-20 2015-02-26 マグネデザイン株式会社 Élément de capteur à magnéto-impédance à bobine électromagnétique et capteur à magnéto-impédance à bobine électromagnétique
JP2016003866A (ja) * 2014-06-13 2016-01-12 マグネデザイン株式会社 Ｚ軸用ｇｍｉ素子および超薄型３次元ｇｍｉセンサ
JP2018148189A (ja) * 2017-03-01 2018-09-20 ナノコイル株式会社 ナノコイル型ｇｓｒセンサ素子の製造方法
WO2018225454A1 (fr) * 2017-06-05 2018-12-13 朝日インテック株式会社 Élément de capteur gsr
JP2019191016A (ja) * 2018-04-25 2019-10-31 マグネデザイン株式会社 超薄型高感度磁気センサ
JP2019203763A (ja) * 2018-05-22 2019-11-28 マグネデザイン株式会社 磁性ワイヤ整列装置および磁性ワイヤ整列方法
JP2022037949A (ja) * 2020-08-26 2022-03-10 マグネデザイン株式会社 Ｇｓｒセンサ素子の製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5246787A (en) * 1975-10-11 1977-04-13 Hitachi Ltd Coil for integrated circuit and process for production of same
JP2004258038A (ja) * 2003-02-25 2004-09-16 Samsung Electronics Co Ltd 磁界検出素子およびその製造方法
WO2010097932A1 (fr) * 2009-02-27 2010-09-02 愛知製鋼株式会社 Élément capteur à magnéto-impédance et son procédé de fabrication
WO2015025606A1 (fr) * 2013-08-20 2015-02-26 マグネデザイン株式会社 Élément de capteur à magnéto-impédance à bobine électromagnétique et capteur à magnéto-impédance à bobine électromagnétique
JP2016003866A (ja) * 2014-06-13 2016-01-12 マグネデザイン株式会社 Ｚ軸用ｇｍｉ素子および超薄型３次元ｇｍｉセンサ
JP2018148189A (ja) * 2017-03-01 2018-09-20 ナノコイル株式会社 ナノコイル型ｇｓｒセンサ素子の製造方法
WO2018225454A1 (fr) * 2017-06-05 2018-12-13 朝日インテック株式会社 Élément de capteur gsr
JP2019191016A (ja) * 2018-04-25 2019-10-31 マグネデザイン株式会社 超薄型高感度磁気センサ
JP2019203763A (ja) * 2018-05-22 2019-11-28 マグネデザイン株式会社 磁性ワイヤ整列装置および磁性ワイヤ整列方法
JP2022037949A (ja) * 2020-08-26 2022-03-10 マグネデザイン株式会社 Ｇｓｒセンサ素子の製造方法

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