WO2024080574A1 - Dispositif d'étalonnage d'impédance - Google Patents

Dispositif d'étalonnage d'impédance Download PDF

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Publication number
WO2024080574A1
WO2024080574A1 PCT/KR2023/013557 KR2023013557W WO2024080574A1 WO 2024080574 A1 WO2024080574 A1 WO 2024080574A1 KR 2023013557 W KR2023013557 W KR 2023013557W WO 2024080574 A1 WO2024080574 A1 WO 2024080574A1
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WIPO (PCT)
Prior art keywords
pull
resistance value
resistor circuit
voltage
circuit
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PCT/KR2023/013557
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English (en)
Korean (ko)
Inventor
성창경
이만형
Original Assignee
주식회사 퀄리타스반도체
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Priority claimed from KR1020220172740A external-priority patent/KR102663032B1/ko
Application filed by 주식회사 퀄리타스반도체 filed Critical 주식회사 퀄리타스반도체
Publication of WO2024080574A1 publication Critical patent/WO2024080574A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/12—Compensating for variations in line impedance

Definitions

  • the technical idea of the present disclosure relates to electronic devices, and specifically to a device and method for measuring and calibrating impedance for impedance matching between a transceiver and a transmission line.
  • transmission lines channels
  • transmitters and receivers of various impedances
  • PVT process voltage temperature
  • the impedances of each component included in the interconnect device may deviate from the normal values set at design, and impedance mismatching may affect signal integrity in high-speed communication, resulting in This may cause communication errors.
  • the present disclosure was made in response to the above-described background technology, and its purpose is to provide an apparatus and method for measuring and calibrating the output impedance of a transmitter to achieve impedance matching with a transmission line.
  • the purpose of the present disclosure is to provide a device that can effectively calibrate the output impedance of a driver included in a transmitter according to a preset size or condition.
  • An impedance calibration device for realizing the above-described problem includes a target driver module including a pull-up resistor circuit and a pull-down resistor circuit, a pull-up resistance value of the pull-up resistor circuit, and a pull-down resistance value of the pull-down resistor circuit.
  • a resistance measurement module for measuring each resistance value, and a control module for generating a pull-up code for adjusting the pull-up resistance value and a pull-down code for adjusting the pull-down resistance value to calibrate the pull-up resistance value and the pull-down resistance value.
  • the control module is characterized in that it updates the pull-down code based on the pull-down resistance value and a preset target pull-down resistance value, and updates the pull-up code based on the pull-up resistance value and the preset target pull-up resistance value.
  • the resistance measurement module may include a voltage controlled oscillator whose output frequency varies based on the input voltage.
  • the target driver module may connect one end of the pull-up resistor circuit to the first node based on a first activation signal, and connect one end of the pull-down resistor circuit to the first node based on a second activation signal. You can. A supply voltage may be applied to the other end of the pull-up resistor circuit.
  • control module receives a first reference frequency generated by the voltage-controlled oscillator based on a first reference voltage, and inputs a reference current and a voltage generated based on the pull-down resistor circuit to the voltage-controlled oscillator.
  • the first pull-down frequency generated from may be received, and a pull-down resistance value of the pull-down resistor circuit may be generated based on the first reference frequency and the first pull-down frequency.
  • control module may update the pull-down code so that the difference between the first reference frequency and the first pull-down frequency is less than or equal to a first range.
  • control module receives a second reference frequency generated by the voltage control oscillator as an input a second reference voltage generated at a first rate based on the supply voltage, and based on the voltage of the first node
  • the first pull-up frequency generated by the voltage controlled oscillator may be received, and a pull-up resistance value of the pull-up resistor circuit may be generated based on the second reference frequency and the first pull-up frequency.
  • the pull-up resistor circuit may include a plurality of transistors connected in parallel, and may selectively connect one or more of the plurality of transistors to a signal transmission path based on the pull-up code.
  • the pull-down resistor circuit may include a plurality of transistors connected in parallel, and one or more of the plurality of transistors may be selectively connected to a signal transmission path based on the pull-down code.
  • the resistance measurement module includes a counter that measures the output frequency, the counter generating a first reference count based on the first reference frequency, and generating a first reference count based on the first pulldown frequency. Counts can be created.
  • An impedance calibration device includes a target driver module including a pull-up resistor circuit capable of adjusting the resistance value based on a pull-up code and a pull-down resistor circuit capable of adjusting the resistance value based on the pull-down code, and measuring the resistance value.
  • a resistance measurement module and the target driver including a reference signal circuit for generating a reference signal for It includes a control module that controls the module or the resistance measurement module and calibrates the measured resistance value.
  • the reference signal circuit may include one or more voltage sources, a current source, and a plurality of switches for selectively connecting the voltage source or current source to the target driver module.
  • the target driver module may include a first transistor connecting one end of the pull-up resistor circuit to the first node based on a first activation signal, and a first transistor connecting one end of the pull-down resistor circuit to the first node based on a second activation signal. It includes a second transistor connected to the node. A supply voltage may be applied to the other end of the pull-up resistor circuit.
  • the target driver module may include an output load circuit coupled to the first node.
  • the pull-up resistor circuit may selectively connect one or more of the plurality of transistors to the signal transmission path based on a pull-up code.
  • the pull-down resistor circuit may selectively connect one or more of the plurality of transistors to the signal transmission path based on a pull-down code.
  • the resistance measurement module may include a voltage-controlled oscillator whose output frequency varies based on the input voltage and a counter that measures the output frequency.
  • the reference signal circuit may include a first voltage source for generating a reference signal when measuring the resistance value of the pull-up resistor circuit, a second voltage source for generating a reference signal when measuring the resistance value of the pull-down resistor circuit, and a pull-down resistor circuit. It may include a current source for measuring the resistance value.
  • the reference signal circuit may include a second node connected to the target driver module, a third node connected to the resistance measurement module, a first switch connecting the first voltage source to the third node, and the second node. It may include a second switch connecting the voltage source to the third node, a fourth switch connecting the current source to the second node, and a third switch connecting the second node and the third node.
  • control module turns on the second switch, receives a first reference frequency generated by the voltage controlled oscillator based on the second reference voltage source, turns off the second switch, and Turn on the fourth switch, the third switch, and the second transistor, receive a first pull-down frequency generated by the voltage-controlled oscillator based on the reference current source and the pull-down resistor circuit, and The pull-down resistance value of the pull-down resistor circuit may be generated based on the first pull-down frequency.
  • control module may update the pull-down code so that the difference between the first reference frequency and the first pull-down frequency is less than or equal to a first range.
  • the control module turns on the first switch, receives a second reference frequency generated by the voltage controlled oscillator based on the first reference voltage source, and includes the third switch, the first transistor, and Turn on the second transistor, receive a first pull-up frequency generated by the voltage-controlled oscillator based on the voltage of the first node, and apply the pull-up resistor based on the second reference frequency and the first pull-up frequency.
  • the pull-up resistance value of the circuit can be generated.
  • the voltage level of the first reference voltage source may be half of the voltage level of the supply voltage.
  • control module may update the pull-up code so that the pull-up resistance value becomes a preset pull-up resistance value.
  • the output impedance of the transmitter is outside the impedance value range set during design due to changes in PVT, etc., the output impedance can be corrected to a desired impedance value.
  • the pull-down impedance or pull-up impedance included in the transmitter can be calibrated without being affected by changes in supply voltage.
  • FIG. 1 is a diagram showing a system according to an embodiment of the present disclosure.
  • Figure 2 is a block diagram of an impedance calibration device according to an embodiment of the present disclosure.
  • FIG. 3 is a diagram illustrating an impedance calibration device according to an embodiment of the present disclosure.
  • Figure 4 is a flowchart explaining an impedance calibration method according to an embodiment of the present disclosure.
  • Figure 5 is a diagram showing the driver structure of a transmitter according to an embodiment of the present disclosure.
  • FIG. 6 is a diagram illustrating a sub-driver module according to an embodiment of the present disclosure.
  • FIG. 7 is a diagram illustrating a target driver module according to an embodiment of the present disclosure.
  • FIG. 8 is a circuit diagram illustrating a pull-up resistor circuit and a pull-down resistor circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a diagram illustrating a change in resistance value according to a code change in a pull-up resistor circuit or a pull-down resistor circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a diagram illustrating a reference signal circuit included in an impedance calibration device according to an embodiment of the present disclosure.
  • FIG. 11 is a diagram illustrating a measurement circuit included in an impedance calibration device according to an embodiment of the present disclosure.
  • the term “or” is intended to mean an inclusive “or” and not an exclusive “or.” That is, unless otherwise specified in the present disclosure or the meaning is not clear from the context, “X uses A or B” should be understood to mean one of natural implicit substitutions. For example, unless otherwise specified in the present disclosure or the meaning is not clear from the context, “X uses A or B” means that It can be interpreted as one of the cases where all B is used.
  • N is a natural number
  • N is a natural number
  • components performing different functional roles may be distinguished as first components or second components.
  • components that are substantially the same within the technical spirit of the present disclosure but must be distinguished for convenience of explanation may also be distinguished as first components or second components.
  • impedance used in the present disclosure may be a value that prevents the flow of current when a voltage is applied in a circuit. Impedance in an alternating current circuit is an extension of the concept of resistance, and unlike resistance, which only has a magnitude value, it can have magnitude and phase values. In a direct current circuit, impedance and resistance are the same, which may be the case where the phase angle of impedance is 0. In the present disclosure, impedance calibration describes a process of measuring and calibrating based on resistance, but is not limited thereto.
  • FIG. 1 is a diagram showing a system according to an embodiment of the present disclosure.
  • system 10 may include a transmitter 11 and a receiver 13 that communicate with each other over a channel 12 .
  • the system 10 may include a data transmission/reception circuit, a SERDES (Serializer/Deserializer) circuit, a high-speed data transmission system, etc.
  • SERDES Serializer/Deserializer
  • Transmitter 11 may transmit data or signals to receiver 13 through channel 12.
  • the transmitter 11 may include a driver 200 and an impedance calibration device 100 for calibrating the output impedance of the driver 200.
  • the driver 200 may have a Series Source Termination (SST) structure, and may have a structure in which one or more sub-driver modules (or unit driver segments) 210 are connected in parallel.
  • the output impedance of the driver 200 may have a structure in which the output impedances of each sub-driver module 210 are connected in parallel.
  • the present invention exemplarily describes a method of measuring and calibrating output impedance in an SST driver structure, but is not limited thereto and can be applied to various types of driver structures such as CML (Current Mode Logic Driver).
  • the impedance calibration device 100 may include components for calibrating the output impedance of the driver 200. Specifically, the impedance calibration device 100 measures the output impedance of a target driver module (or unit driver replica) replicating the sub-driver module 210 in order to indirectly measure the output impedance of the driver 200. can do.
  • the target driver module may include the same components related to output impedance included in the sub-driver module 210, and may further include components for measuring and calibrating the output impedance.
  • the impedance calibration device 100 may measure the output impedance of the target driver module, perform calibration with a preset output impedance value, and generate code for setting the output impedance.
  • the impedance calibration device 100 may transmit the generated code to the driver 200 to calibrate the output impedance of the sub-driver modules 210 included in the driver 200 to a preset output impedance value.
  • the code for calibration is generated based on the pull-up resistor circuit or pull-down resistor circuit of the target driver module, and can be applied to the target driver module or sub-driver module 210.
  • the calibration device 100 can control the output impedance of the driver 200 within a desired range using the generated code.
  • the channel 12 may be a path or transmission line that physically or electrically connects the transmitter 11 and the receiver 13.
  • the channel 12 may be implemented using a trace of a printed circuit board (PCB) or a coaxial cable.
  • PCB printed circuit board
  • the receiver 13 may receive a signal transmitted from the transmitter 11 through the channel 12.
  • the receiver 13 may further include an amplifier or equalizer to restore the transmission signal or compensate for channel loss.
  • the output impedance of the driver 200 included in the transmitter 11 and the impedance of the channel 12 are outside the normal range set at design due to changes in PVT, etc., the calibration device 100 ), the output impedance of the driver 200 can be adjusted to effectively maintain the impedance matching state.
  • Figure 2 is a block diagram of an impedance calibration device according to an embodiment of the present disclosure.
  • the impedance calibration device 100 may include a target driver module 110, a resistance measurement module 120, and a control module 130.
  • the target driver module 110 may be a replica module of any one of the sub-driver modules included in the driver (e.g., 200 in FIG. 1) of the transmitter (e.g., 11 in FIG. 1).
  • the target driver module 110 may include a pull-up resistor circuit 112 and a pull-down resistor circuit 114.
  • the target driver module 110 may have some differences in configuration from the sub-driver module of the transmitter (for example, 210 in FIG. 1) in order to measure and calibrate the resistance of the pull-up resistor circuit 112 and the pull-down resistor circuit 114. there is.
  • the sub-driver module generates an output signal based on an input signal, but the target driver module 110 generates a pull-up activation signal (e.g., a first activation signal) or a pull-down activation signal (e.g., instead of an input signal). , the second activation signal), the connection state of the pull-up resistor circuit 112 or the pull-down resistor circuit 114 can be controlled.
  • Target driver module 110 may include an output load circuit 116.
  • Output load circuit 116 may include a passive resistive element.
  • the resistance measurement module 120 applies a reference signal (R_SIG) to the target driver module 110, and in response measures the output signal (V_R) of the target driver module 110 to measure the pull-up resistance circuit 112 and the pull-down resistor circuit 112.
  • the resistance value of the resistance circuit 114 can be measured.
  • the reference signal (R_SIG) is generated from various voltage sources or current sources applied to the target driver module 110 in consideration of the supply voltage, the target resistance value (impedance value) of the pull-up resistor circuit 112 and the pull-down resistor circuit 114, etc. May contain signals.
  • a target resistance value including a preset target pulldown resistance value or a preset target pullup resistance value may be a value set for matching between the output impedance of a driver included in the transmitter and the impedance of the channel.
  • the resistance measurement module 120 may include a reference signal circuit 122 and a measurement circuit 124.
  • the reference signal circuit 122 may sequentially apply preset reference signals (R_SIG) to the pull-up resistor circuit 112 and the pull-down resistor circuit 114 of the target driver module 110.
  • the measurement circuit 124 measures the output signal (V_R) of the target driver module 110 to calculate the output impedance of the target driver module 110 or calculates the resistance values of the pull-up resistor circuit 112 and the pull-down resistor circuit 114. It can be calculated.
  • the control module 130 may transmit a pull-up activation signal or a pull-down activation signal to the target driver module 110 to control whether the pull-up resistor circuit 112 or the pull-down resistor circuit 114 is connected to the output load circuit 116. there is.
  • the control module 130 may generate a pull-up code for adjusting the resistance value of the pull-up resistor circuit 112 and may generate a pull-down code for adjusting the resistance value of the pull-down resistor circuit 114.
  • the control module 130 can control the resistance value of the pull-up resistor circuit 112 by transmitting the pull-up code to the pull-up resistor circuit 112, and transmits the pull-down code to the pull-down resistor circuit 114 to adjust the resistance value of the pull-up resistor circuit 114.
  • the resistance value can be adjusted.
  • the pull-up control signal (CTL_PU) transmitted from the control module 130 to the pull-up resistor circuit 112 may include a pull-up activation signal and a pull-up code.
  • the pull-down control signal (CTL_PD) transmitted from the control module 130 to the pull-down resistor circuit 114 may include a pull-down activation signal and a pull-down code.
  • the control module 130 transmits the switch control signal (CTL_SW) to the reference signal circuit 122 to control a plurality of switching elements included in the reference signal circuit 122, and controls the reference signal preset in the target driver module 110.
  • CTL_SW switch control signal
  • the control module 130 may receive a signal output from the measurement circuit 124 and calculate the resistance values of the pull-up resistor circuit 112 and the pull-down resistor circuit 114 that are measurement targets.
  • the control module 130 may receive a frequency corresponding to the voltage level of the output node of the target driver module 110 and calculate the resistance value of the measurement target based on the frequency.
  • control module 130 may be at least one processor included in a semiconductor package. At least one processor may execute a series of instructions or process signals based on the supply voltage. Each component included in the impedance calibration device 100 will be described in detail in FIGS. 5 to 10.
  • FIG. 3 is a diagram illustrating an impedance calibration device according to an embodiment of the present disclosure.
  • the impedance calibration device 1000 may include a target driver module 300, a reference signal circuit 400, a measurement circuit 500, and a control module 600.
  • the target driver module 300 may include a pull-up resistor circuit 310, a pull-up activating transistor (MP31), a pull-down resistor circuit 320, a pull-down activating transistor (MN31), and an output load circuit 330.
  • MP31 pull-up activating transistor
  • MN31 pull-down activating transistor
  • One end of the pull-up resistor circuit 310 may be connected to the supply voltage (VDD) and the other end may be connected to the third node (N33).
  • One end of the pull-down resistor circuit 320 may be connected to the ground node (GND) and the other end may be connected to the fourth node (N34).
  • One end of the pull-up activation transistor MP31 may be connected to the third node N33 and the other end may be connected to the first node N31.
  • One end of the pull-down activation transistor MN31 may be connected to the fourth node N34 and the other end may be connected to the first node N31.
  • the output load circuit 330 may be connected between the first node N31 and the second node N32, which is an output node.
  • the pull-up control signal (CTL_PU) transmitted from the control module 600 to the pull-up resistor circuit 310 may include a pull-up activation signal (CODE_PU) and a pull-up code.
  • the pull-down control signal (CTL_PD) transmitted from the control module 600 to the pull-down resistor circuit 320 may include a pull-down activation signal and a pull-down code (CODE_PD).
  • the control module 600 transmits a pull-up activation signal (EN_PU) or a pull-down activation signal (EN_PD) to the target driver module 300 to connect the pull-up resistor circuit 310 or the pull-down resistor circuit 320 to the first node (N31). You can control whether or not to connect.
  • the control module 600 may generate a pull-up code (CODE_PU) to adjust the resistance value of the pull-up resistor circuit 310, and generate a pull-down code (CODE_PD) to adjust the resistance value of the pull-down resistor circuit 320. can do.
  • the control module 600 can control the resistance value of the pull-up resistor circuit 310 by transmitting the pull-up code (CODE_PU) to the pull-up resistor circuit 310 and transmitting the pull-down code (CODE_PD) to the pull-down resistor circuit 320.
  • the resistance value of the pull-down resistor circuit 320 can be adjusted.
  • the control module 600 transmits a pull-up code (CODE_PU) to the pull-up resistor circuit 310 to selectively connect one or more of the plurality of PMOS transistors connected in parallel between the supply voltage (VDD) and the third node (N33). You can.
  • the control module 600 may invert the signal level of the pull-up code (CODE_PU) and transmit it to the pull-up resistor circuit 310.
  • the control module 600 may connect the pull-up resistor circuit 310 to the first node N31 by applying the pull-up activation signal (EN_PU) to the pull-up activation transistor (MP31).
  • the control module 600 transmits a pull-down code (CODE_PD) to the pull-down resistor circuit 320 to selectively connect one or more of the plurality of NMOS transistors connected in parallel between the ground node (GND) and the fourth node (N34). You can.
  • the control module 600 may connect the pull-down resistor circuit 320 to the first node N31 by applying the pull-down activation signal EN_PD to the pull-down activation transistor MN31.
  • the reference signal circuit 400 includes a first voltage source 410, a second voltage source 420, a current source 430, a first switch (SW1), a second switch (SW2), a third switch (SW3), and a fourth switch. (SW4) may be included.
  • the first voltage source 410 may be a voltage generated based on a supply voltage (VDD, or driving voltage) applied to the transmitter or the impedance calibration device 1000.
  • VDD supply voltage
  • the voltage level of the first voltage source 410 may be half the voltage level of the supply voltage VDD.
  • the size ratio of the supply voltage and the first voltage source 410 is set variously. It can be.
  • the second voltage source 420 may provide a reference voltage having a preset voltage level.
  • the voltage level of the second voltage source 420 may be a voltage level corresponding to the size of the preset resistance value of the pull-down resistor circuit 320 for impedance matching.
  • the voltage level of the second voltage source 420 is measured by the pull-up resistor circuit 310, the pull-down resistor circuit 320, and the output load circuit 330 included in the target driver module to measure the magnitude of the resistance value of the pull-down resistor circuit 320. ) can be set considering such factors.
  • the current source 430 may provide a reference current having a preset size.
  • the reference signal circuit 400 applies the reference current generated by the current source 430 to the pull-down resistor circuit 320, and the voltage of the output node N32 is increased by the resistance component of the pull-down resistor circuit 320. You can control its creation.
  • the control module 600 transmits the switch control signal (CTL_SW) to the reference signal circuit 400 to operate the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4). You can control it.
  • the control module 600 may control the first voltage source 410 and the third node N43 to be connected using the first switch SW1.
  • the control module 600 may control the second voltage source 420 and the third node N43 to be connected using the second switch SW2.
  • the control module 600 can control the current source 430 and the second node N42 to be connected using the fourth switch SW4.
  • the control module 600 may control the second node N42 and the third node N43 to be connected using the third switch SW3.
  • the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) may be composed of transistors.
  • Measurement circuit 500 may include a voltage controlled oscillator 510 and a counter 520.
  • the measurement circuit 500 may generate an output frequency corresponding to the resistance value of the pull-up resistor circuit 310 or the pull-down resistor circuit 320 that is the measurement target based on the target voltage (V_R) output from the target driver module 300. there is.
  • the voltage control oscillator 510 may generate an oscillation signal based on the target voltage (V_R), and the counter 520 may count the oscillation signal during a reference period and provide a counting signal (CNT) to the control module 600. You can.
  • Figure 4 is a flowchart explaining an impedance calibration method according to an embodiment of the present disclosure.
  • the impedance calibration device 1000 may set a measurement standard for the pull-down resistor circuit 320 included in the target driver module 300 (S110).
  • the impedance calibration device 1000 uses a first reference count (or first reference) that serves as a standard for measuring the resistance value of the pull-down resistor circuit 320 based on the second voltage source 420 (or first reference voltage).
  • the second switch (SW2) can be turned on to generate a frequency).
  • the voltage controlled oscillator 510 may generate an oscillating signal based on the second voltage source 420, and the counter 520 may generate a first reference count from the oscillating signal.
  • the voltage level of the second voltage source 420 may be a voltage level corresponding to the target resistance value of the pull-down resistor circuit 320.
  • the impedance calibration device 1000 can measure the resistance value of the pull-down resistance circuit 320 (S120). For example, in order to measure the resistance value of the pull-down resistance circuit 320, the impedance calibration device 1000 applies a high-level pull-down activation signal (EN_PD) to turn on the pull-down activation transistor (MN31), and turns on the pull-down resistance circuit ( 320) can be connected to the first node (N31). The impedance calibration device 1000 may turn on the third switch SW3 and the fourth switch SW4 to measure the voltage level generated by applying the current source 430 to the pull-down resistor circuit 320.
  • EN_PD high-level pull-down activation signal
  • the voltage controlled oscillator 510 generates an oscillation signal based on the voltage level of the second node N32 of the target driver module 300, and the counter 520 calculates the first pulldown count (or first pulldown frequency) from the oscillation signal. can be created.
  • the impedance calibration device 1000 may determine the resistance value of the pull-down resistor circuit 320 based on the first pull-down count.
  • the impedance calibration device 1000 may calibrate the pull-down resistance value based on the measured resistance value of the pull-down resistance circuit 320 (S130). For example, in order to adjust the resistance value of the pull-down resistance circuit 320, the impedance calibration device 1000 updates the pull-down code (CODE_PD) so that the difference between the first reference count and the first pull-down count is less than or equal to the first range. can do.
  • CODE_PD pull-down code
  • the impedance calibration device 1000 may repeat steps S110 to S130 until it finds the pull-down code (CODE_PD) in which the difference between the first reference count and the first pull-down count is the smallest.
  • the impedance calibration device 1000 selects the pull-down code (CODE_PD) with the low resistance value of the pull-down resistor circuit 320 among the pull-down codes (CODE_PD) that minimize the difference between the first reference count and the first pull-down count, or A pull-down code (CODE_PD) with a high resistance value of the resistance circuit 320 can be selected.
  • the impedance calibration device 1000 interpolates two values measured in adjacent pull-down codes (CODE_PD) at a specific ratio among the count (CNT) values measured while changing the pull-down code (CODE_PD) to determine the first A pull-down code (CODE_PD) that matches the target resistance value can be selected by comparing it to the reference count.
  • CODE_PD adjacent pull-down codes
  • the impedance calibration device 1000 may set a measurement standard for the resistance value of the pull-up resistor circuit 310 included in the target driver module 300 (S140). For example, the impedance calibration device 1000 uses a second reference count (or 2 reference frequency), the first switch (SW1) can be turned on.
  • the voltage controlled oscillator 510 may generate an oscillating signal based on the first voltage source 410, and the counter 520 may generate a second reference count from the oscillating signal.
  • the voltage level of the first voltage source 410 may be half of the supply voltage.
  • the impedance calibration device 1000 can measure the resistance value of the pull-up resistor circuit 310 (S150). For example, in order to measure the resistance value of the pull-up resistance circuit 310, the impedance calibration device 1000 applies a low-level pull-up activation signal (EN_PU) to turn on the pull-up activation transistor (MP31) and activates the pull-up resistance circuit ( 310) can be connected to the first node (N31). In order to measure the resistance value of the pull-up resistor circuit 310, the impedance calibration device 1000 applies a high-level pull-down activation signal (EN_PD) to turn on the pull-down activation transistor (MN31) and turns on the pull-down resistance circuit 320. 1 Can be connected to node (N31).
  • EN_PU low-level pull-up activation signal
  • MN31 pull-down activation transistor
  • MN31 pull-down activation transistor
  • the impedance calibration device 1000 uses a third switch ( SW3) can be turned on.
  • the voltage controlled oscillator 510 generates an oscillation signal based on the voltage level of the first node N31 of the target driver module 300, and the counter 520 calculates the first pull-up count (or first pull-up frequency) from the oscillation signal. can be created.
  • the impedance calibration device 1000 may determine the resistance value of the pull-up resistor circuit 320 based on the first pull-up count.
  • the voltage level of the first node N31 is determined based on the supply voltage applied to the pull-up resistor circuit 310 and the size ratio of the resistance values of the pull-down resistor circuit 320 and the pull-up resistor circuit 310, in step S130
  • the resistance value of the pull-up resistor circuit 310 can be estimated by considering the determined resistance value of the pull-down resistor circuit 320.
  • the voltage level of the first node N31 may be half the voltage level of the supply voltage.
  • the impedance calibration device 1000 may calibrate the pull-up resistance based on the measured resistance value of the pull-up resistance circuit 310 (S160). For example, in order to adjust the resistance value of the pull-up resistor circuit 310, the impedance calibration device 1000 updates the pull-up code (CODE_PU) so that the difference between the second reference count and the first pull-up count is less than or equal to the first range. can do.
  • CODE_PU pull-up code
  • the impedance calibration device 1000 transfers the pull-up code (CODE_PU) and pull-down code (CODE_PD) determined in steps S110 to S160 to each of the driver 200 or sub-driver modules described in FIGS. 5 and 6 to determine the driver 200's Output impedance can be adjusted.
  • the impedance calibration device 1000 performs an impedance calibration method to correct the output impedance to a desired impedance value even when the output impedance of the transmitter or the driver included in the transmitter is outside the impedance value range set at design due to changes in PVT, etc. and the pull-down impedance or pull-up impedance included in the transmitter can be calibrated without being affected by changes in supply voltage.
  • Figure 5 is a diagram showing the driver structure of a transmitter according to an embodiment of the present disclosure.
  • the driver 200 may be a voltage-mode driver including a plurality of sub-driver modules.
  • the driver 200 may include sub-driver modules between differential inputs (DIN_P, DIN_N) and differential outputs (DOUT_P, DOUT_N).
  • the first sub-driver modules 210_1, 210_2, x, and 210_n may be connected in parallel between the first input (DIN_P) and the first output (DOUT_P).
  • the second sub-driver modules 220_1, 220_2, 220_n may be connected in parallel between the second input (DIN_N) and the second output (DOUT_N).
  • the output impedance is the first output impedance of each of the first sub-driver modules (210_1, 210_2, 210_n) connected in parallel, and the output impedance of each of the second sub-driver modules (220_1, 220_2, 220_n). may include a second output impedance connected in parallel.
  • the structure of the sub-driver module is explained in FIG. 6.
  • FIG. 6 is a diagram illustrating a sub-driver module according to an embodiment of the present disclosure.
  • the sub-driver module 210 may generate an output signal (DOUT) based on the input signal (DIN).
  • the sub-driver module 210 may include a pull-up resistor circuit 212, a pull-down resistor circuit 214, an inverter 216, and an output load circuit 218.
  • Output load circuit 218 may be a passive resistor.
  • the sub-driver module 210 may connect either the pull-up resistor circuit 212 or the pull-down resistor circuit 214 to the output load circuit 218 according to the input signal DIN.
  • the pull-up resistor circuit 212 may include a plurality of PMOS transistors connected in parallel.
  • the pull-up resistor circuit 212 may selectively connect one or more of the plurality of PMOS transistors to a path where the output signal DOUT is generated or a signal transmission path according to the pull-up code CODE_PU.
  • the pull-up code (CODE_PU) may be input to the pull-up resistor circuit 212 in an inverted signal level.
  • the pull-down resistor circuit 214 may include a plurality of NMOS transistors connected in parallel.
  • the pull-down resistor circuit 214 may selectively connect one or more of the plurality of NMOS transistors to a path where the output signal (DOUT) is generated or a signal transmission path according to the pull-down code (CODE_PD).
  • FIG. 7 is a diagram illustrating a target driver module according to an embodiment of the present disclosure.
  • the target driver module 300 may include a pull-up resistor circuit 310, a pull-up activating transistor (MP31), a pull-down resistor circuit 320, a pull-down activating transistor (MN31), and an output load circuit 330. You can.
  • One end of the pull-up resistor circuit 310 may be connected to the supply voltage (VDD) and the other end may be connected to the third node (N33).
  • One end of the pull-down resistor circuit 320 may be connected to the ground node (GND) and the other end may be connected to the fourth node (N34).
  • One end of the pull-up activation transistor MP31 may be connected to the third node N33 and the other end may be connected to the first node N31.
  • One end of the pull-down activation transistor MN31 may be connected to the fourth node N34 and the other end may be connected to the first node N31.
  • the output load circuit 330 may be connected between the first node N31 and the second node N32, which is an output node.
  • the pull-up resistor circuit 310 may include a plurality of PMOS transistors connected in parallel.
  • the pull-up resistor circuit 310 may selectively connect one or more of the plurality of PMOS transistors between the supply voltage VDD and the third node N33 according to the pull-up code CODE_PU.
  • the pull-up code (CODE_PU) may be input to the pull-up resistor circuit 310 in an inverted signal level.
  • the pull-up activation transistor MP31 may connect the pull-up resistor circuit 310 to the first node N31 based on the pull-up activation signal EN_PU.
  • the pull-down resistor circuit 320 may include a plurality of NMOS transistors connected in parallel.
  • the pull-down resistor circuit 320 may selectively connect one or more of the plurality of NMOS transistors between the ground node (GND) and the fourth node (N34) according to the pull-down code (CODE_PD).
  • the pull-down activation transistor MN31 may connect the pull-down resistor circuit 320 to the first node N31 based on the pull-down activation signal EN_PD.
  • the impedance calibration device can measure and calibrate the impedance (zi) of the target driver module 300.
  • the impedance (zi) of the target driver module 300 may include the resistance value of the pull-up resistor circuit 310 or the resistance value of the pull-down resistor circuit 320.
  • FIG. 8 is a circuit diagram illustrating a pull-up resistor circuit and a pull-down resistor circuit according to an embodiment of the present disclosure
  • FIG. 9 is a circuit diagram illustrating a resistance value according to a code change in a pull-up resistor circuit or a pull-down resistor circuit according to an embodiment of the present disclosure. This is a drawing explaining the change.
  • a target driver module or sub-driver module may include a pull-up resistor circuit 312 and a pull-down resistor circuit 322.
  • the pull-up resistor circuit 212 illustrated in FIG. 6 or the pull-up resistor circuit 310 illustrated in FIG. 7 may be implemented in the same form as the pull-up resistor circuit 312 illustrated in FIG. 8 .
  • the pull-down resistor circuit 214 illustrated in FIG. 6 or the pull-down resistor circuit 320 illustrated in FIG. 7 may be implemented in the same form as the pull-down resistor circuit 322 illustrated in FIG. 8 .
  • the pull-up resistor circuit 312 may include a plurality of PMOS transistor-resistor sets connected between the supply voltage (VDD) and the connection node (N_PU).
  • the first PMOS transistor (MP_1) and the first resistor (RPU_1) may be connected in series between the supply voltage (VDD) and the connection node (N_PU)
  • the second PMOS transistor (MP_2) and the second resistor ( RPU_2) may be connected in series between the supply voltage (VDD) and the connection node (N_PU)
  • the Nth PMOS transistor (MP_N) and the Nth resistor (RPU_N) may be connected in series between the supply voltage (VDD) and the connection node (N_PU).
  • the resistance values of the first resistor (RPU_1) to the Nth resistor (RPU_N) may be the same.
  • the first PMOS transistor (MP_1) to the Nth PMOS transistor (MP_N) may be driven by an N-bit pull-up code (CODE_PU).
  • CODE_PU N-bit pull-up code
  • the first to Nth resistors RPU_1 to RPU_N may be resistance components corresponding to each of the first to Nth PMOS transistors MP_1 to Nth PMOS transistors MP_N or may be separate resistance elements.
  • the pull-up resistor circuit 312 may be implemented as a binary type driver.
  • the binary type driver may represent a driver configured so that each width of a plurality of PMOS transistors is sequentially increased by two times.
  • the width of the first PMOS transistor MP_1 may be twice the width of the second PMOS transistor MP_2, and the width of the second PMOS transistor MP_2 may be twice the width of the third PMOS transistor.
  • the pull-up resistor circuit 312 can provide various resistance values.
  • a change in the resistance value of the pull-up resistor circuit 312 according to a change in the pull-up code (CODE_PU) may be in the form shown in the graph of FIG. 9.
  • the X-axis may be a pull-up code (CODE_PU) or a pull-down code (CODE_PD)
  • the Y-axis may be a resistance value (R).
  • the gate of the first PMOS transistor (MP_1) may be driven by the most significant bit value of the N-bit pull-up code (CODE_PU), and the gate of the second PMOS transistor (MP_2) may be driven by the N-bit pull-up code (CODE_PU). It can be driven by the next most significant bit value of the code (CODE_PU), and the gate of the Nth PMOS transistor (MP_N) can be driven by the lowest bit value of the N-bit pull-up code (CODE_PU), and can be used in various other forms.
  • the pull-up code (CODE_PU) is not limited to this, and a plurality of PMOS transistor-resistors included in the pull-up resistor circuit 312 can be controlled in various forms.
  • connection node N_PU may represent an electrical node to which a circuit element external to the pull-up resistor circuit 312 is connected.
  • connection node (N_PU) of the pull-up resistor circuit 312 may be the third node (N33) of the pull-up resistor circuit 310, as described in FIG. 5, and may be connected to the pull-up activation transistor MP31. there is.
  • the pull-down resistor circuit 322 may include a plurality of NMOS transistor-resistor sets connected between the ground node (GND) and the connection node (N_PD).
  • the first NMOS transistor (MN_1) and the first resistor (RPD_1) may be connected in series between the ground node (GND) and the connection node (N_PD)
  • the second NMOS transistor (MN_2) and the second resistor ( RPD_2) may be connected in series between the ground node (GND) and the connection node (N_PD)
  • the M NMOS transistor (MN_M) and the M resistor (RPD_M) may be connected in series between the ground node (GND) and the connection node (N_PD).
  • the resistance values of the first resistor (RPD_1) to the Mth resistor (RPD_M) may be the same.
  • the first NMOS transistor (MN_1) to the M-th NMOS transistor (MN_M) may be driven by an M-bit pull-down code (CODE_PD).
  • the first to N-th resistors (RPD_1) to RPD_N may be resistance components corresponding to each of the first to N-th NMOS transistors (MN_1) to N-th NMOS transistors (MN_N) or may be separate resistance elements.
  • the pull-down resistor circuit 322 may be implemented as a binary type driver.
  • the binary type driver may represent a driver configured such that the width of each of a plurality of NMOS transistors is sequentially increased by two times.
  • the width of the first NMOS transistor (MN_1) may be twice the width of the second NMOS transistor (MN_2)
  • the width of the second NMOS transistor (MN_2) may be twice the width of the third NMOS transistor.
  • the pull-down resistor circuit 322 can provide various resistance values. For example, a change in the resistance value of the pull-down resistor circuit 322 according to a change in the pull-down code (CODE_PD) may be in the form shown in the graph of FIG. 7.
  • a plurality of NMOS transistors included in the pull-down resistor circuit 322 may be driven by the pull-down code CODE _PD in the same manner as described for the pull-up resistor circuit 312.
  • connection node N_PD may represent an electrical node to which a circuit element external to the pull-down resistor circuit 322 is connected.
  • connection node (N_PD) of the pull-down resistor circuit 322 may be the fourth node (N34) of the pull-down resistor circuit 322, as described in FIG. 5, and may be connected to the pull-down activation transistor (MN31). there is.
  • FIG. 10 is a diagram illustrating a reference signal circuit included in an impedance calibration device according to an embodiment of the present disclosure.
  • the reference signal circuit 400 includes a first voltage source 410, a second voltage source 420, a current source 430, a first switch (SW1), a second switch (SW2), and a third switch ( SW3) and a fourth switch (SW4).
  • the first voltage source 410 may be a voltage generated based on a supply voltage or driving voltage applied to the transmitter or impedance calibration device.
  • the voltage level of the first voltage source 410 may be half the voltage level of the supply voltage.
  • the size ratio of the supply voltage and the first voltage source 410 may be set in various ways.
  • the first voltage source 410 may generate a second reference voltage.
  • the second voltage source 420 may provide a reference voltage having a preset voltage level.
  • the voltage level of the second voltage source 420 may be a voltage level corresponding to the target resistance value of the pull-down resistor circuit.
  • the voltage level of the second voltage source 420 may be set in consideration of the pull-up resistor circuit, pull-down resistor circuit, output load circuit, etc. included in the target driver module to measure the size of the target resistance value of the pull-down resistor circuit.
  • the second voltage source 420 may generate a first reference voltage.
  • the current source 430 may provide a reference current having a preset size.
  • the reference signal circuit 400 applies the reference current generated by the current source 430 to the pull-down resistor circuit and controls the output node voltage of the target driver module to be generated by the resistance component of the pull-down resistor circuit. .
  • the reference signal circuit 400 can control the first voltage source 410 and the third node N43 to be connected using the first switch SW1.
  • the reference signal circuit 400 can control the second voltage source 420 and the third node N43 to be connected using the second switch SW2.
  • the reference signal circuit 400 can control the current source 430 and the second node N42 to be connected using the fourth switch SW4.
  • the reference signal circuit 400 can control the second node N42 and the third node N43 to be connected using the third switch SW3.
  • the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) may be composed of transistors.
  • FIG. 11 is a diagram illustrating a measurement circuit included in an impedance calibration device according to an embodiment of the present disclosure.
  • the measurement circuit 500 may include a voltage controlled oscillator 510 and a counter 520.
  • the measurement circuit 500 may generate an output frequency corresponding to the resistance value of the pull-up resistor circuit or pull-down resistor circuit that is the measurement target based on the voltage (V_R) output from the target driver module.
  • the voltage controlled oscillator 510 may generate an oscillation signal based on the target voltage V_R, and the counter 520 may count the oscillation signal during a reference period and provide a counting signal CNT.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)
  • Networks Using Active Elements (AREA)

Abstract

Un dispositif d'étalonnage d'impédance selon un mode de réalisation de la présente divulgation comprend : un module d'attaque cible comprenant un circuit de résistance d'excursion haute et un circuit de résistance d'excursion basse ; un module de mesure de résistance servant à mesurer aussi bien une valeur de résistance d'excursion haute du circuit de résistance d'excursion haute qu'une valeur de résistance d'excursion basse du circuit de résistance d'excursion basse ; et un module de commande qui, afin d'étalonner la valeur de résistance d'excursion haute et la valeur de résistance d'excursion basse, génère un code d'excursion haute pour ajuster la valeur de résistance d'excursion haute et un code d'excursion basse pour ajuster la valeur de résistance d'excursion basse. Le module de commande met à jour le code d'excursion basse sur la base de la valeur de résistance d'excursion basse et d'une valeur de résistance d'excursion basse cible prédéterminée, et met à jour le code d'excursion haute sur la base de la valeur de résistance d'excursion haute et d'une valeur de résistance d'excursion haute cible prédéterminée.
PCT/KR2023/013557 2022-10-12 2023-09-11 Dispositif d'étalonnage d'impédance WO2024080574A1 (fr)

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KR20220130472 2022-10-12
KR10-2022-0130472 2022-10-12
KR1020220172740A KR102663032B1 (ko) 2022-10-12 2022-12-12 임피던스 캘리브레이션 장치
KR10-2022-0172740 2022-12-12

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040055879A (ko) * 2002-12-23 2004-06-30 주식회사 하이닉스반도체 온 다이 터미네이션 회로
JP2009246725A (ja) * 2008-03-31 2009-10-22 Renesas Technology Corp インピーダンスの調整が可能な出力バッファを備えた半導体装置
KR101024244B1 (ko) * 2009-11-30 2011-03-29 주식회사 하이닉스반도체 임피던스 조절 장치
KR20110129030A (ko) * 2010-05-25 2011-12-01 주식회사 하이닉스반도체 임피던스 코드 생성회로 및 이를 포함하는 반도체 장치, 터미네이션 임피던스 값 설정방법
KR20220013072A (ko) * 2020-07-24 2022-02-04 에스케이하이닉스 주식회사 캘리브레이션 회로 및 이를 포함하는 송신기
WO2022141800A1 (fr) * 2020-12-30 2022-07-07 深圳市紫光同创电子有限公司 Circuit d'étalonnage d'impédance et procédé

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040055879A (ko) * 2002-12-23 2004-06-30 주식회사 하이닉스반도체 온 다이 터미네이션 회로
JP2009246725A (ja) * 2008-03-31 2009-10-22 Renesas Technology Corp インピーダンスの調整が可能な出力バッファを備えた半導体装置
KR101024244B1 (ko) * 2009-11-30 2011-03-29 주식회사 하이닉스반도체 임피던스 조절 장치
KR20110129030A (ko) * 2010-05-25 2011-12-01 주식회사 하이닉스반도체 임피던스 코드 생성회로 및 이를 포함하는 반도체 장치, 터미네이션 임피던스 값 설정방법
KR20220013072A (ko) * 2020-07-24 2022-02-04 에스케이하이닉스 주식회사 캘리브레이션 회로 및 이를 포함하는 송신기
WO2022141800A1 (fr) * 2020-12-30 2022-07-07 深圳市紫光同创电子有限公司 Circuit d'étalonnage d'impédance et procédé

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