WO2015170845A1 - Émetteur de signalisation différentielle à basse tension - Google Patents

Émetteur de signalisation différentielle à basse tension Download PDF

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Publication number
WO2015170845A1
WO2015170845A1 PCT/KR2015/004147 KR2015004147W WO2015170845A1 WO 2015170845 A1 WO2015170845 A1 WO 2015170845A1 KR 2015004147 W KR2015004147 W KR 2015004147W WO 2015170845 A1 WO2015170845 A1 WO 2015170845A1
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Prior art keywords
voltage
pull
driving
switching element
terminal
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PCT/KR2015/004147
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English (en)
Korean (ko)
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김태우
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(주) 픽셀플러스
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Priority to CN201580026933.0A priority Critical patent/CN106416077B/zh
Publication of WO2015170845A1 publication Critical patent/WO2015170845A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Definitions

  • the present invention relates to low voltage differential signal transmitters and, more particularly, to low voltage differential signal transmitters having an output resistance characteristic insensitive to process variations.
  • a video display device receives a video signal (Audio / Video signal) from airwaves, cables, and other external devices (VCR, DVD, etc.), processes the video signal to output the video signal, and processes the video signal to the video signal processing main body. It is composed of a display panel (Display pannel) for displaying the displayed image on the screen. In this case, the display panel and the image signal processing main body may be formed in one piece, or may be separately separated from each other.
  • the display panel and the video signal processing body generally transmit video signals using a Low Voltage Differential Signal (LVDS) interface.
  • the LVDS interface is a transmission method for sending digital information to a flat panel display at high speed through copper wire.
  • low voltage (LV) that is, low voltage means that the LVDS uses a voltage lower than the standard voltage.
  • the LVDS interface is in the spotlight as a solution for such high-speed data transmission.
  • LVDS interfaces are widely used in laptop computers because fewer wires can be used between the motherboard and the panel.
  • this technology is being used between the image scaler and the panel of a large number of self-contained flat panel displays.
  • LVDS interface method is more noise-resistant than conventional single-ended signal method, easier signal termination than pECL (pseudo-emitter coupled logic) signal, and high speed transmission and reception of Gbps or more. This is a possible serial communication method.
  • the LVDS interface uses a low voltage, an electromagnetic interference (EMI) is reduced and power consumption is reduced. Due to these advantages, the LVDS interface is applied to various fields such as data transfer between boards as well as data transfer between boards.
  • EMI electromagnetic interference
  • the present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to enable a low voltage differential signal transmitter to have an output resistance characteristic insensitive to process changes.
  • a low voltage differential signal transmitter includes a plurality of pre-drivers, and drives a positive input signal and a negative input signal to drive a plurality of drive signals having a pull-up voltage level and a plurality of drive signals having a pull-down voltage level.
  • An input driver for outputting a;
  • a voltage generator for regulating a power supply voltage to generate a first driving voltage;
  • a plurality of switching elements selectively turned on by the plurality of driving signals, wherein the first driving voltage is selectively supplied to the differential output stage, and the turn-on resistances of the plurality of switching elements are controlled by the pull-up voltage level and the pull-down voltage level.
  • a main drive to be adjusted.
  • the present invention prevents the reflection of a signal that may occur while the transmission speed of the signal increases at high speed by matching the characteristic with the characteristic impedance of the transmission line so as not to be affected by the variation of the semiconductor manufacturing process, and transmits a signal without distortion. Provide the effect of doing so.
  • FIG. 1 is a conceptual diagram of a low voltage differential signal transmitter according to an embodiment of the present invention.
  • FIG. 2 is a detailed circuit diagram of the transmitter of FIG.
  • FIG. 3 is a detailed block diagram of the pull-up control unit of FIG.
  • FIG. 4 is a detailed block diagram of the pull-down control unit of FIG.
  • FIG. 5 is another embodiment of the transmitter of FIG.
  • FIG. 6 is a detailed configuration diagram of the pull-up control unit of FIG. 5.
  • FIG. 6 is a detailed configuration diagram of the pull-up control unit of FIG. 5.
  • FIG. 7 is a detailed configuration diagram illustrating the pull-down control unit of FIG. 5.
  • FIG. 7 is a detailed configuration diagram illustrating the pull-down control unit of FIG. 5.
  • FIG. 8 is an operation timing diagram relating to the transmitter of FIG.
  • FIG. 1 is a conceptual diagram of a low voltage differential signal transmitter according to an embodiment of the present invention.
  • the low voltage differential signal transmitter is a circuit capable of high speed operation, low current consumption, and low electromagnetic interference (EMI).
  • the low voltage differential signal transmitter has a high speed such as an image sensor, a liquid crystal display driver chip (LDI: LCD driver IC), and communication. It is used in the field requiring data transmission.
  • LDM liquid crystal display driver chip
  • the low voltage differential signal transmitter includes a transmitter 100, a transmission line 200, a receiver 300, and termination resistors 400 and 500.
  • the transmitter 100 receives data through an input terminal.
  • Data input to the transmitter 100 is transmitted to the receiver 300 in a differential manner through the transmission line 200.
  • the potential difference between the two transmission paths is generated based on the data input through the transmitter 100, thereby generating a differential signal.
  • the receiver 300 converts the differential signal received through the transmission line 200 to a CMOS level and outputs it through an output terminal.
  • Each transmission line 200 has the same electrical characteristics, and forms a balanced transmission path so that one signal can be transmitted through two transmission paths.
  • a termination resistor 400 is connected to an input terminal of the receiver 300.
  • a termination resistor 500 for impedance matching may be additionally connected to the output terminal side of the transmitter 100.
  • FIG. 2 is a detailed circuit diagram of the transmitter 100 of FIG. 1.
  • the transmitter 100 includes an input driver 110, a voltage generator 120, a main driver 130, and differential output terminals DN and DP.
  • the input driver 110 includes a plurality of pre-drivers D1 to D4.
  • the pre-drivers D1 and D3 are drivers for driving the pull-up end of the main driver 130, and the pre-drivers D2 and D4 are drivers for driving the pull-down end of the main driver 130.
  • the pre-driver D1 pre-drives the positive input signal INP to the pull-up voltage Vrup to generate the driving voltage VP1.
  • the pre-driver D2 pre-drives the positive input signal INP to the pull-down voltage Vrdn to generate the driving voltage VP2.
  • the pre-driver D3 pre-drives the negative input signal INN to the pull-up voltage Vrup to generate the driving voltage VN1.
  • the pre-driver D4 pre-drives the negative input signal INN to the pull-down voltage Vrdn to generate the driving voltage VN2.
  • the pre-drivers D1 and D3 are driven by the pull-up voltage Vrup, and the pre-drivers D2 and D4 are driven by the pull-down voltage Vrdn.
  • the voltage generator 120 generates the driving voltage Vreg of the main driver 130 by regulating the power supply voltage VDD.
  • the voltage generator 120 supplies the generated driving voltage Vreg to the switching elements M1 and M2 of the main driver 130.
  • the main driver 130 includes a plurality of switching elements M1 to M4.
  • the switching elements M1 to M4 may be formed of field effect transistors (FETs).
  • the switching elements M1 and M3 are connected in series between the application terminal of the driving voltage Vreg and the ground GND voltage terminal.
  • the driving voltage VP1 is applied to the switching element M1 through the gate terminal
  • the driving voltage VN2 is applied to the switching element M3 through the gate terminal.
  • the switching elements M2 and M4 are connected in series between the application terminal of the driving voltage Vreg and the ground GND voltage terminal.
  • the driving voltage VN1 is applied to the switching element M2 through the gate terminal
  • the driving voltage VP2 is applied to the switching element M4 through the gate terminal.
  • the number of pre-drivers D1 to D4 corresponds to the number of switching elements M1 to M4 provided in the main driver 130. That is, the pre-drivers D1 to D4 individually drive control the switching elements M1 to M4. When the number of switching elements M1 to M4 is changed, the number of switching elements M1 to M4 may be changed to correspond to the number of pre-drivers D1 to D4.
  • the common connection node of the switching elements M1 and M3 is connected to the differential output terminal DP, and the common connection node of the switching elements M2 and M4 is connected to the differential output terminal DN.
  • the differential output terminals DN and DP are connected to the transmission line 200.
  • the turn-on resistance of the switching elements M1 to M4 becomes the output resistance of the transmitter 100.
  • the turn-on resistance of the switching elements M1 to M4 is determined by the pullup voltage Vrup and the pulldown voltage Vrdn.
  • the transmitter 100 having such a configuration individually adjusts output voltages VP1, VP2, VN1 and VN2 of the pre-drivers D1 to D4 for driving the switching elements M1 to M4 provided in the main driver 130. Accordingly, the turn-on resistance of the switching elements M1 to M4 of the main driver 130 can be kept constant.
  • the switching elements M1 and M4 are turned on. Then, the driving voltage Vreg output from the voltage generator 120 is output to the differential output terminal DP through the switching element M1.
  • the output signal of the differential output terminal DP is input to the differential output terminal DN through the termination resistor 400 through the transmission line 200 and output to the ground voltage GND terminal through the switching element M4.
  • the driving voltages VN1 and VN2 have polarities opposite to those of the driving voltages VP1 and VP2.
  • the driving voltages VP1 and VP2 are high, the driving voltages VN1 and VN2 are turned low, and the switching elements M2 and M3 are turned off.
  • the switching elements M2 and M3 are turned on. Accordingly, the driving voltage Vreg is output to the differential output terminal DN through the switching element M2.
  • the output signal of the differential output terminal DN is input to the differential output terminal DP via the termination resistor 400 through the transmission line 200 and output to the ground voltage GND terminal through the switching element M3.
  • the current flowing from the driving voltage Vreg to the ground voltage GND becomes (Vreg-GND) / ((M2 turn-on resistance) + (termination resistor) + (M3 turn-on resistance)).
  • this current is called Iref
  • the voltage across the differential output DN becomes Vreg-Iref * (M2 turn-on resistance) and the voltage across the differential output DP is GND + Iref * (M3 turn-on resistance).
  • the driving voltages VN1 and VN2 are high, the driving voltages VP1 and VP2 are turned low so that the switching elements M1 and M4 are turned off.
  • FIG. 3 is a detailed block diagram of the pull-up control unit 111 of FIG. 2.
  • the pull-up control unit 111 generates the pull-up voltage Vrup supplied to the pre-drivers D1 and D3.
  • the pull-up control unit 111 includes a high voltage generator 112, a voltage generator 113, an amplifier 114, a constant current source 115, a switching element M5, and a pull-up voltage generator PU.
  • the high voltage generator 112 generates a high voltage Vhigh corresponding to the power supply voltage VDD and supplies it to the amplifier 114.
  • the voltage generator 113 generates the driving voltage Vreg2 by regulating the power supply voltage VDD and supplies it to the switching element M5.
  • the driving voltage Vreg2 may have the same voltage level as the driving voltage Vreg.
  • the amplifier 114 outputs the pull-up driving signal VPU by comparing and amplifying the high voltage Vhigh and the feedback voltage Vfeedh in response to the power supply voltage VDD. That is, the amplifier 114 receives the high voltage Vhigh through the positive input terminal and the feedback voltage Vfeedh through the negative input terminal.
  • the constant current source 115 is connected between the switching element M5 and the ground GND voltage terminal, so that the constant current Iref corresponding to the feedback voltage Vfeedh flows.
  • the pull-up voltage generation unit PU regulates the pull-up driving signal VPU in response to the power supply voltage VDD to generate a pull-up voltage Vrup and supplies it to the pre-drivers D1 and D3.
  • the switching element M5 is connected between the driving voltage Vreg2 applying terminal and the constant current source 115 to receive the pull-up driving signal VPU through the gate terminal.
  • the switching element M5 is a replica having the same size and the same layout as the switching elements M1 and M2 of FIG. 2. Here, it is assumed that the switching elements M1 and M2 have the same size and the same layout.
  • the gain (DC gain) of the amplifier 114 is sufficiently large (for example, 60 dB or more)
  • the level of the pull-up drive signal VPU is adjusted so that the feedback voltage Vfeedh is equal to the value of the high voltage Vhigh.
  • the turn on resistance of the switching element M5 becomes (Vreg2-Vhigh) / Iref.
  • the pull-up voltage generator PU generates the pull-up voltage Vrup by regulating the adjusted pull-up driving signal VPU.
  • the pull-up voltage generator PU supplies the generated pull-up voltage Vrup to power of the pre-drivers D1 and D3.
  • the pre-drivers D1 and D3 receiving the pull-up voltage Vrup as the power supply voltage control the driving of the switching elements M1 and M2 according to the driving voltages VP1 and VN1.
  • the high state voltages of the driving voltages VP1 and VN1 become the pull-up voltage Vrup level.
  • the turn-on resistance value when the pull-up voltage Vrup is applied to the switching elements M1 and M2 of the main driver 130 is the same as the turn-on resistance value of the switching element M5, resulting in (Vreg2-Vhigh) / Iref.
  • the driving voltage Vreg2 preferably has a voltage level higher than the high voltage Vhigh.
  • the switching element M1 by the high voltage Vhigh and the constant current source 115 generated based on the switching element M5, the amplifier 114, and the band gap voltage corresponding to the process change of the switching elements M1 and M2. Since the level of the pullup voltage Vrup is adjusted so that the output resistance of M2 is constant, the turn-on resistance values of the switching elements M1 and M2 are not affected by the process change.
  • FIG. 4 is a detailed configuration diagram illustrating the pull-down control unit 116 of FIG. 2.
  • the pulldown control unit 116 generates a pulldown voltage Vrdn supplied to the pre drivers D2 and D4.
  • the pull-down controller 116 includes a low voltage generator 117, an amplifier 118, a constant current source 119, a switching element M6, and a pull-down voltage generator PD.
  • the low voltage generator 117 generates the low voltage Vlow in response to the power supply voltage VDD and supplies it to the amplifier 118.
  • the amplifier 118 compares and amplifies the low voltage Vlow and the feedback voltage Vfeedl in response to the power supply voltage VDD, and outputs a pull-down driving signal VPD. That is, the amplifier 118 receives the low voltage Vlow through the negative input terminal and the feedback voltage Vfeedl through the positive input terminal.
  • the constant current source 119 is connected between the supply voltage VDD applying stage and the switching element M6 so that the constant current Iref corresponding to the feedback voltage Vfeedl flows.
  • the pull-down voltage generator PD generates a pull-down voltage Vrdn by regulating the pull-down driving signal VPD in response to the power supply voltage VDD and supplies it to the pre-drivers D2 and D4.
  • the switching element M6 is connected between the constant current source 119 and the ground GND voltage terminal, and the pull-down driving signal VPD is applied through the gate terminal.
  • the switching element M6 is a replica having the same size and the same layout as the switching elements M3 and M4 of FIG. 2. Here, it is assumed that the switching elements M3 and M4 have the same size and the same layout.
  • the gain (DC gain) of the amplifier 118 is sufficiently large (for example, 60 dB or more), the level of the pull-down drive signal VPD is adjusted so that the feedback voltage Vfeedl is equal to the value of the low voltage Vlow. At this time, the turn on resistance of the switching element M6 becomes Vlow / Iref.
  • the pull-down voltage generator PD generates the pull-down voltage Vrdn by regulating the adjusted pull-down driving signal VPD.
  • the pull-down voltage generator PD supplies the generated pull-down voltage Vrdn to power of the pre-drivers D2 and D4.
  • the pre-drivers D2 and D4 which receive the pull-down voltage Vrdn as the power supply voltage, control the driving of the switching elements M3 and M4 according to the driving voltages VP2 and VN2. In other words, the high state voltages of the driving voltages VP2 and VN2 become the pull-down voltage Vrdn level.
  • the turn-on resistance value when the pull-down voltage Vrdn is applied to the switching elements M3 and M4 of the main driver 130 is the same as the turn-on resistance value of the switching element M6, resulting in Vlow / Iref.
  • 5 is another embodiment of the transmitter 100 of FIG.
  • the transmitter 100_1 includes an input driver 110_1, a voltage generator 120_1, a main driver 130_1, and differential output terminals DN and DP. 5 has the same structure as the embodiment of FIG. However, it is different from FIG. 2 in that the main driver 130_1 includes resistors R1 to R4 for preventing electrostatic discharge (ESD).
  • ESD electrostatic discharge
  • a resistor R1 is connected between the switching element M1 and the differential output terminal DP.
  • a resistor R2 is connected between the switching element M2 and the differential output terminal DN.
  • a resistor R3 is connected between the switching element M3 and the differential output terminal DP.
  • a resistor R4 is connected between the switching element M4 and the differential output terminal DN. That is, the resistors R2 and R4 are connected between the differential output terminal DN and the switching elements M2 and M4, and the resistors R1 and R3 are connected between the differential output terminal DP and the switching elements M1 and M3.
  • the differential output terminals DP and DN are interfaces that connect the inside and the outside of the semiconductor chip, which may cause electrostatic discharge (ESD) problems in the differential output terminals DP and DN.
  • ESD electrostatic discharge
  • the resistors R1 to R4 are connected to the differential output terminals DP and DN connected to the transmission line 200.
  • the sum of the turn-on resistances of the switching elements M1 to M4 and the resistances of the resistors R1 to R4 becomes the output resistance of the transmitter 100_1.
  • the turn-on resistance of the switching elements M1 to M4 is determined by the pullup voltage Vrup and the pulldown voltage Vrdn.
  • the voltage across the differential output terminals DP, DN and the constant current sources 115 and 119 is the resistance value of the resistors R1 to R4 for the ESD of the main driver 130_1 to the transistor turn on resistances of the switching elements M1 to M4.
  • FIG. 6 is a detailed block diagram of the pull-up control unit 111_1 of FIG. 5.
  • FIG. 6 has the same structure as that in FIG. 3, but differs from FIG. 3 in that a resistor R5 is further provided between the switching element M5 and the constant current source 115.
  • the gain (DC gain) of the amplifier 114 is sufficiently large (for example, 60 dB or more)
  • the level of the pull-up drive signal VPU is adjusted so that the feedback voltage Vfeedh is equal to the value of the high voltage Vhigh.
  • the sum of the turn on resistance of the switching element M5 and the resistance R5 becomes (Vreg2-Vhigh) / Iref.
  • the pull-up voltage generator PU generates the pull-up voltage Vrup by regulating the adjusted pull-up driving signal VPU.
  • the pull-up voltage generator PU supplies the generated pull-up voltage Vrup to power of the pre-drivers D1 and D3.
  • the pre-drivers D1 and D3 receiving the pull-up voltage Vrup as the power supply voltage control the driving of the switching elements M1 and M2 according to the driving voltages VP1 and VN1.
  • the high state voltages of the driving voltages VP1 and VN1 become the pull-up voltage Vrup level.
  • the driving voltage Vreg2 preferably has a voltage level higher than the high voltage Vhigh.
  • the high voltage Vhigh and the constant current source generated based on the switching element M5, the resistor R5, the amplifier 114, and the bandgap voltage are copied in response to the process change of the switching elements M1, M2 and the resistors R1, R2.
  • the level of the pull-up voltage Vrup is adjusted so that the turn-on resistances of the switching elements M1 and M2 and the sum of the resistors R1 and R2 are constant, so the sum of the turn-on resistances of the switching elements M1 and M2 and the resistors R1 and R2 is processed. It is not affected by change.
  • FIG. 7 is a detailed configuration diagram illustrating the pull-down control unit 116_1 of FIG. 5.
  • FIG. 7 has the same structure as that of FIG. 4, it is different from FIG. 4 to further include a resistor R6 between the switching element M6 and the constant current source 119.
  • the gain (DC gain) of the amplifier 118 is sufficiently large (for example, 60 dB or more), the level of the pull-down drive signal VPD is adjusted so that the feedback voltage Vfeedl is equal to the value of the low voltage Vlow. At this time, the sum of the turn on resistance of the switching element M6 and the resistor R6 becomes Vlow / Iref.
  • the pull-down voltage generator PD generates the pull-down voltage Vrdn by regulating the adjusted pull-down driving signal VPD.
  • the pull-down voltage generator PD supplies the generated pull-down voltage Vrdn to power of the pre-drivers D2 and D4.
  • the pre-drivers D2 and D4 which receive the pull-down voltage Vrdn as the power supply voltage, control the driving of the switching elements M3 and M4 according to the driving voltages VP2 and VN2. In other words, the high state voltages of the driving voltages VP2 and VN2 become the pull-down voltage Vrdn level.
  • the pull-down voltage Vrdn When the pull-down voltage Vrdn is applied to the switching elements M3 and M4 of the main driver 130, the sum of the turn-on resistance and the resistors R3 and R4 is equal to the sum of the turn-on resistance and the resistance R6 of the switching element M6, and thus Vlow / It becomes Iref.
  • the low voltage Vlow and the constant current source generated based on the switching element M6, the resistor R6, the amplifier 118, and the bandgap voltage are copied in response to the process change of the switching elements M3, M4 and the resistors R3, R4.
  • the level of the pull-down voltage Vrdn is adjusted so that the turn-on resistance of the switching elements M3 and M4 and the sum of the resistors R3 and R4 are constant by 119, the sum of the turn-on resistance of the switching elements M3 and M4 and the resistors R3 and R4 is processed. It is not affected by change.
  • 8 is an operation timing diagram for the transmitter 100 according to the embodiment of the present invention.
  • the positive input signal INP and the negative input signal INN swing between the power supply voltage VDD and the ground voltage GND level.
  • the positive input signal INP and the negative input signal INN have opposite phases.
  • the driving voltages VP1 and VN1 swing between the level of the pullup voltage Vrup and the ground voltage GND.
  • the driving voltages VP2 and VN2 swing between the pull-down voltage Vrdn and the ground voltage GND.
  • the driving voltages VP1 and VP2 have phases opposite to those of the driving voltages VN1 and VN2.
  • the differential output stages DN and DP which are outputs of the transmitter 100, swing between the levels of the high voltage Vhigh and the low voltage Vlow.
  • the high voltage Vhigh is Vreg-Iref * (M1 turn on resistance) or Vreg-Iref * (M2 trun on resistance).
  • the low voltage Vlow becomes GND + Iref * (M4 turn-on resistor) or GND + Iref * (M3 turn-on resistor).
  • GND is 0V
  • the low voltage Vlow is either Iref * (M4 turn on resistance) or Iref * (M3 turn on resistance).
  • the MIPI Mobile Industry Processor Interface
  • LCD driver ICs LCD driver ICs
  • image sensors for mobile phones
  • the termination resistor 300 uses 100 ohms.
  • the current Iref should be 2 mA and the turn-on resistance of each transistor M1-M4 should be 50 ohm, and the characteristic impedance matching of the transmission line 200 is also satisfied. Done. At this time, the output resistance of the transmitter 100 is 50 ohm.
  • the sum of the turn-on resistance of each transistor M1 to M4 and the resistance R for ESD should be 50 ohm.
  • the turn-on resistance of the transistors M1 to M4 or the resistance R for ESD are highly dependent on the variation in the semiconductor manufacturing process, and thus the output resistance of the transmitter 100 when a variation occurs in the semiconductor manufacturing process. Will affect directly.
  • the output resistance specifications are as low as 40 ohms and as high as 62.5 ohms.
  • the characteristic impedance matching of the transmission line 200 may not be properly performed, thereby causing reflection in the signal transmission, causing distortion in the signal transmitted at a higher speed.
  • the switching elements M1 to M4 and the resistors R1 to R4 for the ESD are generated based on the copies M5, M6, resistors R5, R6 and the bandgap voltage.
  • the level of the pull-up voltage Vrup and the pull-down voltage Vrdn is controlled by the high voltage Vhigh, the low voltage Vlow and the constant current sources 115 and 119 and the amplifiers 114 and 118, so that the turn-on resistance values of the switching elements M1 to M4, or R to R4 The sum will not be affected by process changes.

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Abstract

La présente invention porte sur un émetteur de signalisation différentielle à basse tension, plus particulièrement sur la technologie qui permet à l'émetteur de signalisation différentielle à basse tension de présenter des caractéristiques de résistance de sortie qui sont insensibles aux variations de processus. La présente invention comprend : une unité d'attaque d'entrée comprenant une pluralité de dispositifs d'attaque préalable pour délivrer en sortie une pluralité de signaux d'attaque comportant un niveau de tension d'excursion haute par attaque de signaux d'entrée positifs (INP) et de signaux d'entrée négatifs (INN), et une pluralité de signaux d'attaque comportant un niveau de tension d'excursion basse ; un générateur de tension pour réguler une tension d'alimentation et générer une première tension d'attaque ; et une unité d'attaque principale comprenant une pluralité de dispositifs de commutation qui sont sélectivement débloqués par la pluralité de signaux d'attaque pour fournir sélectivement la première tension d'attaque à une borne de sortie différentielle, la résistance à l'état passant de la pluralité de dispositifs de commutation étant commandée par le niveau de tension d'excursion haute et le niveau de tension d'excursion basse.
PCT/KR2015/004147 2014-05-08 2015-04-27 Émetteur de signalisation différentielle à basse tension WO2015170845A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114268080A (zh) * 2021-12-17 2022-04-01 中国电子科技集团公司第五十八研究所 一种防总线漏电的m-lvds驱动电路
US20230032010A1 (en) * 2021-07-30 2023-02-02 Renesas Electronics America Inc. Apparatus for multi-driver architecture with high voltage protection and impedance control

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