WO2024080089A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2024080089A1
WO2024080089A1 PCT/JP2023/034106 JP2023034106W WO2024080089A1 WO 2024080089 A1 WO2024080089 A1 WO 2024080089A1 JP 2023034106 W JP2023034106 W JP 2023034106W WO 2024080089 A1 WO2024080089 A1 WO 2024080089A1
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Prior art keywords
semiconductor device
conductive member
chip
terminal lead
mounting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/034106
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English (en)
French (fr)
Japanese (ja)
Inventor
諒介 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
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Filing date
Publication date
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Priority to CN202380071318.6A priority Critical patent/CN120019481A/zh
Priority to DE112023003772.8T priority patent/DE112023003772T5/de
Priority to JP2024551354A priority patent/JPWO2024080089A1/ja
Publication of WO2024080089A1 publication Critical patent/WO2024080089A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/041—Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/435—Shapes or dispositions of insulating layers on leadframes, e.g. bridging members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/886—Die-attach connectors and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/763—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/766—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • Patent Document 1 semiconductor devices in which semiconductor elements such as diodes or transistors are covered with a resin package are known (for example, Patent Document 1).
  • the semiconductor device described in Patent Document 1 includes first to third lead frames, a power semiconductor chip, a first inner lead, a second inner lead, and a molded resin.
  • the power semiconductor chip includes a first power semiconductor chip bonded to the first lead frame, and a second power semiconductor chip bonded to the second lead frame.
  • the first and second power semiconductor chips each function as a switching element.
  • the first inner lead connects the first power semiconductor chip to the second lead frame.
  • the second inner lead connects the second power semiconductor chip to the third lead frame.
  • the two inner leads are each arranged separately.
  • An object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that are improved over conventional methods.
  • an object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that improves production efficiency.
  • the semiconductor device provided by the first aspect of the present disclosure includes a semiconductor circuit section, a first conductive member that is conductive to the semiconductor circuit section, a second conductive member that is conductive to the semiconductor circuit section, an insulating member that contacts the first conductive member and the second conductive member, and a sealing resin that covers the semiconductor circuit section, the first conductive member, the second conductive member, and a portion of the insulating member.
  • the first conductive member and the second conductive member are fixed by the insulating member.
  • the method for manufacturing a semiconductor device includes the steps of preparing a lead frame including a first conductive member and a second conductive member, fixing the first conductive member and the second conductive member with an insulating member in the lead frame state, joining the first conductive member and the second conductive member to a semiconductor circuit section while the first conductive member and the second conductive member are fixed with the insulating member, and forming a sealing resin that covers the first conductive member, the second conductive member, and the semiconductor circuit section.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a plan view showing the semiconductor device according to the first embodiment.
  • FIG. 3 is a plan view of FIG. 2 in which the sealing resin is shown by imaginary lines.
  • FIG. 4 is a partially enlarged view of a part of FIG.
  • FIG. 5 is a bottom view showing the semiconductor device according to the first embodiment.
  • FIG. 6 is a front view showing the semiconductor device according to the first embodiment.
  • FIG. 7 is a right side view showing the semiconductor device according to the first embodiment.
  • FIG. 8 is a partially enlarged view of a part of FIG. 7, in which the sealing resin is indicated by imaginary lines.
  • FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. FIG.
  • FIG. 10 is a partially enlarged view of a part of FIG.
  • FIG. 11 is a partially enlarged view of a part of FIG.
  • FIG. 12 is a partially enlarged view of a part of FIG.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG.
  • FIG. 14 is a partially enlarged view of a part of FIG.
  • FIG. 15 is a cross-sectional view taken along line XV-XV in FIG.
  • FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG.
  • FIG. 17 is a diagram illustrating an example of a circuit configuration of the semiconductor device according to the first embodiment.
  • FIG. 18 is a plan view showing a process of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 18 is a plan view showing a process of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 19 is a plan view showing a process of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 20 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 21 is a plan view showing a semiconductor device according to a first modification of the first embodiment, in which a sealing resin is indicated by imaginary lines.
  • FIG. 22 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a first modification of the first embodiment.
  • FIG. 23 is a plan view showing a semiconductor device according to a second modification of the first embodiment, in which a sealing resin is indicated by imaginary lines.
  • FIG. 24 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a second modification of the first embodiment.
  • FIG. 20 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 21 is a plan view showing a semiconductor device according to a first modification of
  • FIG. 25 is a plan view showing a semiconductor device according to a third modification of the first embodiment, in which a sealing resin is indicated by imaginary lines.
  • FIG. 26 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a third modification of the first embodiment.
  • FIG. 27 is a plan view showing the semiconductor device according to the second embodiment, in which the sealing resin is indicated by imaginary lines.
  • FIG. 28 is a partially enlarged view of a part of FIG.
  • FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG.
  • FIG. 30 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to the second embodiment.
  • FIG. 31 is a plan view showing a semiconductor device according to a first modification of the second embodiment, in which a sealing resin is indicated by imaginary lines.
  • FIG. 32 is a plan view showing a semiconductor device according to a second modification of the second embodiment, in which a sealing resin is indicated by imaginary lines.
  • FIG. 33 is a plan view showing a semiconductor device according to a third modification of the second embodiment, in which a sealing resin is indicated by imaginary lines.
  • FIG. 34 is a cross-sectional view showing a semiconductor device according to a modified example, and corresponds to the cross section of FIG.
  • FIG. 35 is a cross-sectional view showing a semiconductor device according to a modified example, and corresponds to the cross section of FIG. FIG.
  • FIG. 36 is an enlarged plan view of a main part of a semiconductor device according to a modified example.
  • FIG. 37 is a cross-sectional view showing the semiconductor device of FIG. 36, and corresponds to the cross section of FIG.
  • FIG. 38 is an enlarged plan view of a main part of a semiconductor device according to a modified example.
  • FIG. 39 is a cross-sectional view showing a semiconductor device according to a modified example, and corresponds to the cross section of FIG.
  • FIG. 40 is an enlarged plan view of a main part of a semiconductor device according to a modified example.
  • FIG. 41 is a front view showing the semiconductor device of FIG. 40, in which the sealing resin is indicated by imaginary lines.
  • an object A is formed on an object B
  • an object A is formed on (an object B)
  • an object A is formed directly on an object B
  • an object A is formed on an object B with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A is disposed on an object B” and “an object A is disposed on (an object B)” include “an object A is disposed directly on an object B” and “an object A is disposed on (an object B) with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A is located on (an object B) includes “an object A is in contact with an object B and is located on (an object B)” and “an object A is located on (an object B) with another object interposed between the object A and the object B".
  • an object A overlaps an object B includes “an object A overlaps the entire object B” and “an object A overlaps a part of an object B” unless otherwise specified.
  • an object A (its material) contains a certain material C includes “an object A (its material) is made of a certain material C” and "an object A (its material) is mainly composed of a certain material C.”
  • FIGS. 1 to 17 show a semiconductor device A10 according to a first embodiment.
  • the semiconductor device A10 includes a first mounting portion 10A, a second mounting portion 10B, a plurality of terminal leads 13, a semiconductor circuit portion 20, two conductive members 31, 32, a plurality of conductive members 41A, 41B, 42A, 42B, a sealing resin 50, and an insulating member 60.
  • the plurality of terminal leads 13 include a first terminal lead 14, a second terminal lead 15, a third terminal lead 16, a fourth terminal lead 171, a sixth terminal lead 172, a fifth terminal lead 181, and a seventh terminal lead 182.
  • the semiconductor circuit portion 20 includes a first chip 21 and a second chip 22.
  • the thickness direction of the semiconductor device A10 is referred to as the "thickness direction z".
  • one side of the thickness direction z may be referred to as the upper side, and the other side as the lower side.
  • the terms “upper”, “lower”, “upper”, “lower”, “top surface” and “bottom surface” indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.
  • “planar view” refers to the view in the thickness direction z.
  • the direction perpendicular to the thickness direction z is referred to as the "first direction x”.
  • the direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y”.
  • the semiconductor device A10 converts the DC power supply voltage applied to the first terminal lead 14 and the second terminal lead 15 of the multiple terminal leads 13 into an AC voltage using the semiconductor circuit section 20 (first chip 21 and second chip 22).
  • the converted AC voltage is input to a power supply target such as a motor from the third terminal lead 16 of the multiple terminal leads 13.
  • the semiconductor device A10 is used in a power conversion circuit such as an inverter.
  • the first mounting portion 10A and the second mounting portion 10B are positioned apart from each other in the first direction x.
  • the first mounting portion 10A, together with the second mounting portion 10B and the multiple terminal leads 13, are composed of the same lead frame.
  • the lead frame is copper (Cu) or a copper alloy. Therefore, the composition of each of the first mounting portion 10A, the second mounting portion 10B and the multiple terminal leads 13 includes copper.
  • Each of the first mounting portion 10A and the second mounting portion 10B is, for example, approximately rectangular in a plan view.
  • the first mounting portion 10A and the second mounting portion 10B each have a main surface 101 and a back surface 102. Unless otherwise specified, the main surface 101 and the back surface 102 described below are common to the first mounting portion 10A and the second mounting portion 10B.
  • the main surface 101 faces one side (upward) in the thickness direction z.
  • the main surface 101 is covered with sealing resin 50.
  • the first chip 21 is mounted on the main surface 101 of the first mounting portion 10A.
  • the back surface 102 of the first mounting portion 10A faces the side opposite to the side where the first chip 21 is located in the thickness direction z.
  • the second chip 22 is mounted on the main surface 101 of the second mounting portion 10B.
  • the back surface 102 of the second mounting portion 10B faces the side opposite to the side where the second chip 22 is located in the thickness direction z.
  • the back surface 102 is exposed from the sealing resin 50.
  • the back surface 102 is plated with, for example, tin (Sn).
  • the sealing resin 50 covers the semiconductor circuit section 20 (the first chip 21 and the second chip 22), the two conductive members 31, 32, and at least a portion of each of the first mounting section 10A and the second mounting section 10B. Furthermore, the sealing resin 50 covers a portion of each of the multiple terminal leads 13 and the multiple conductive members 41A, 41B, 42A, and 42B.
  • the sealing resin 50 has electrical insulation properties.
  • the sealing resin 50 includes, for example, a black epoxy resin. As shown in Fig. 2, the dimension L1 of the sealing resin 50 in the first direction x is longer than the dimension L2 of the sealing resin 50 in the second direction y.
  • the sealing resin 50 has a resin main surface 51, a resin back surface 52, a pair of first side surfaces 53, a second side surface 54, a third side surface 55, multiple recesses 56, a groove portion 57, and multiple recesses 581, 582.
  • the resin main surface 51 faces the same side as the main surfaces 101 of the first mounting portion 10A and the second mounting portion 10B in the thickness direction z.
  • the resin back surface 52 faces the opposite side to the resin main surface 51 in the thickness direction z.
  • the back surfaces 102 of the first mounting portion 10A and the second mounting portion 10B are exposed from the resin back surface 52.
  • the pair of first side surfaces 53 are positioned apart from each other in the first direction x.
  • the pair of first side surfaces 53 face the first direction x and extend in the second direction y.
  • the pair of first side surfaces 53 are connected to the resin main surface 51 and the resin back surface 52.
  • the second side 54 and the third side 55 are located apart from each other in the second direction y.
  • the second side 54 and the third side 55 face opposite each other in the second direction y and extend in the first direction x.
  • the second side 54 and the third side 55 are connected to the resin main surface 51 and the resin back surface 52.
  • a plurality of terminal leads 13 are exposed from the third side 55.
  • the multiple recesses 56 recess from the third side surface 55 in the second direction y and extend from the resin main surface 51 to the resin back surface 52 in the thickness direction z.
  • the multiple recesses 56 are individually located between the seventh terminal lead 182 and the third terminal lead 16, between the third terminal lead 16 and the first terminal lead 14, between the first terminal lead 14 and the second terminal lead 15, and between the second terminal lead 15 and the fifth terminal lead 181.
  • the groove portion 57 is recessed from the resin back surface 52 in the thickness direction z and extends along the second direction y. Both sides of the groove portion 57 in the second direction y are connected to the second side surface 54 and the third side surface 55. When viewed in the thickness direction z, the groove portion 57 separates the back surface 102 of the first mounting portion 10A from the back surface 102 of the second mounting portion 10B.
  • each of the multiple recesses 581, 582 is recessed from the resin main surface 51 in the thickness direction z.
  • the planar shape of each of the multiple recesses 581, 582 is not particularly limited, but is circular in the illustrated example.
  • Each of the multiple recesses 581 overlaps the first mounting portion 10A in a planar view.
  • the multiple recesses 581 are individually located near the four corners of the first mounting portion 10A in a planar view.
  • Each of the multiple recesses 582 overlaps the second mounting portion 10B in a planar view.
  • the multiple recesses 582 are individually located near the four corners of the second mounting portion 10B in a planar view.
  • the multiple recesses 581 are formed by pins for fixing the first mounting portion 10A during the manufacture of the semiconductor device A10.
  • the pins are pressed against the first mounting portion 10A at a stage before the sealing resin 50 is formed, and fix the first mounting portion 10A. In this state, the formation of the sealing resin 50 begins. Then, the pin is pulled out before the formation of the sealing resin 50 is completed. As a result, the sealing resin 50 is formed in at least a part of the area where the pin was located, so that the main surface 101 of the first mounting portion 10A is covered with the sealing resin 50.
  • the multiple recesses 581 are marks formed by the molding process of the sealing resin 50.
  • the multiple recesses 582 are also formed by pins for fixing the second mounting portion 10B during the manufacture of the semiconductor device A10. The multiple recesses 582 are marks formed by the molding process of the sealing resin 50.
  • the first mounting portion 10A and the second mounting portion 10B have a first end face 111, a second end face 112, a third end face 113, and a fourth end face 114.
  • the first end face 111, the second end face 112, the third end face 113, and the fourth end face 114 are covered with the sealing resin 50.
  • the first end face 111 faces in the first direction x and extends in the second direction y.
  • the first end face 111 is located closest to a pair of first side faces 53 of the sealing resin 50.
  • the second end face 112 faces in the second direction y and extends in the first direction x.
  • the second end face 112 is located closest to the second side face 54 of the sealing resin 50.
  • the third end face 113 faces the opposite side to the second end face 112 in the second direction y, and extends in the first direction x.
  • the third end surface 113 is located closest to the third side surface 55 of the sealing resin 50.
  • the fourth end surface 114 faces the opposite side to the first end surface 111 in the first direction x and extends in the second direction y.
  • a groove portion 57 is located between the fourth end surface 114 of the first mounting portion 10A and the fourth end surface 114 of the second mounting portion 10B.
  • the distance P2 between the third end face 113 and the third side face 55 is longer than the distance P1 between the second end face 112 and the second side face 54.
  • the second mounting portion 10B has a first seating surface 103 and a first upright surface 104.
  • the first seating surface 103 faces the same side as the main surface 101 in the thickness direction z, and is located between the main surface 101 and the back surface 102 in the thickness direction z.
  • the first seating surface 103 is connected to the fourth end surface 114.
  • the first upright surface 104 faces a direction perpendicular to the thickness direction z, and is connected to the first seating surface 103 and the main surface 101.
  • the first seating surface 103 and the first upright surface 104 form a step on the second mounting portion 10B.
  • Each of the first chip 21 and the second chip 22 is, for example, a transistor.
  • the transistor is, for example, any one of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a bipolar transistor, and an IGBT (Insulated Gate Bipolar Transistor).
  • the first chip 21 and the second chip 22 are each an RC-IGBT with a built-in reverse conducting diode, as shown in FIG. 17. Note that the first chip 21 and the second chip 22 may be an IGBT without a built-in reverse conducting diode.
  • Each of the first chip 21 and the second chip 22 includes a compound semiconductor substrate.
  • the composition of the compound semiconductor substrate includes silicon (Si) or silicon carbide (SiC).
  • the first chip 21 is mounted on the first mounting portion 10A as shown in Figures 3, 4, 9 and 10.
  • the center of gravity of the first chip 21 overlaps with the center of the first mounting portion 10A.
  • the center of the first mounting portion 10A is the center when the first mounting portion 10A is divided into Nx (Nx is a positive odd number) in the first direction x, and is the region that corresponds to the center when the first mounting portion 10A is divided into Ny (Ny is a positive odd number) in the second direction y.
  • Nx and Ny are not limited in any way, but are, for example, 3 or 5.
  • the first chip 21 has a first main surface 21a and a first back surface 21b.
  • the first main surface 21a and the first back surface 21b are spaced apart from each other in the thickness direction z.
  • the first main surface 21a faces in the same direction as the main surface 101 of the first mounting portion 10A.
  • the first back surface 21b faces the opposite side to the first main surface 21a in the thickness direction z and faces the main surface 101 of the first mounting portion 10A.
  • the first chip 21 has a first main surface electrode 211, multiple main surface electrodes 212, 214, and a first back surface electrode 213.
  • the first principal surface electrode 211 is disposed on the first principal surface 21a. A current corresponding to the power converted by the first chip 21 flows through the first principal surface electrode 211.
  • the first principal surface electrode 211 is, for example, an emitter electrode, and in an example where the first chip 21 is a MOSFET, the first principal surface electrode 211 is, for example, a source electrode.
  • the first principal surface electrode 211 includes a plurality of metal plating layers.
  • the first principal surface electrode 211 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer.
  • the first principal surface electrode 211 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.
  • the principal surface electrode 212 is disposed on the first principal surface 21a.
  • a first drive signal (gate voltage) for driving the first chip 21 is applied to the principal surface electrode 212.
  • the principal surface electrode 212 is, for example, a gate electrode in either the case where the first chip 21 is an IGBT or a MOSFET. In a plan view, the area of the principal surface electrode 212 is smaller than the area of the first principal surface electrode 211.
  • the pair of principal surface electrodes 214 are arranged on the first principal surface 21a. Each of the pair of principal surface electrodes 214 has the same potential as the first principal surface electrode 211. In an example where the first chip 21 is an IGBT, each of the pair of principal surface electrodes 214 is, for example, an emitter sense electrode, and in an example where the first chip 21 is a MOSFET, each of the pair of principal surface electrodes 214 is, for example, a source sense electrode. In a plan view, the pair of principal surface electrodes 214 are arranged on both sides of the principal surface electrode 212 in the second direction y. Note that the first chip 21 may have only one of the pair of principal surface electrodes 214, or may have neither of the pair of principal surface electrodes 214.
  • the first back surface electrode 213 is disposed on the first back surface 21b.
  • the first back surface electrode 213 is provided facing the main surface 101 of the first mounting portion 10A.
  • a current corresponding to the power before being converted by the first chip 21 flows through the first back surface electrode 213.
  • the first back surface electrode 213 is, for example, a collector electrode, and in an example where the first chip 21 is a MOSFET, the first back surface electrode 213 is, for example, a drain electrode.
  • the second chip 22 is mounted on the main surface 101 of the second mounting portion 10B as shown in Figures 3, 4, 9 and 11.
  • the center of gravity of the second chip 22 overlaps with the center of the second mounting portion 10B.
  • the center of the second mounting portion 10B is the center when the second mounting portion 10B is divided into Lx (Lx is a positive odd number) in the first direction x, and is the region that corresponds to the center when the second mounting portion 10B is divided into Ly (Ly is a positive odd number) in the second direction y.
  • Lx and Ly are not limited in any way, but are, for example, 3 or 5.
  • the second chip 22 has a second main surface 22a and a second back surface 22b.
  • the second main surface 22a and the second back surface 22b are spaced apart from each other in the thickness direction z.
  • the second main surface 22a faces in the same direction as the main surface 101 of the second mounting portion 10B.
  • the second back surface 22b faces the opposite side to the second main surface 22a in the thickness direction z and faces the main surface 101 of the second mounting portion 10B.
  • the second chip 22 has a second principal surface electrode 221, a plurality of principal surface electrodes 222, 224, and a second back surface electrode 223.
  • the second principal surface electrode 221 is disposed on the second principal surface 22a. A current corresponding to the power converted by the second chip 22 flows through the second principal surface electrode 221.
  • the second principal surface electrode 221 is, for example, an emitter electrode, and in an example where the second chip 22 is a MOSFET, the second principal surface electrode 221 is, for example, a source electrode.
  • the second principal surface electrode 221 includes multiple metal plating layers, similar to the first principal surface electrode 211.
  • the second principal surface electrode 221 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer.
  • the second principal surface electrode 221 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.
  • the principal surface electrode 222 is disposed on the second principal surface 22a.
  • a second drive signal (gate voltage) for driving the second chip 22 is applied to the principal surface electrode 222.
  • the principal surface electrode 222 is, for example, a gate electrode.
  • the area of the principal surface electrode 222 is smaller than the area of the second principal surface electrode 221.
  • the pair of principal surface electrodes 224 are arranged on the second principal surface 22a. Each of the pair of principal surface electrodes 224 has the same potential as the second principal surface electrode 221. In an example where the second chip 22 is an IGBT, each of the pair of principal surface electrodes 224 is, for example, an emitter sense electrode, and in an example where the second chip 22 is a MOSFET, each of the pair of principal surface electrodes 224 is, for example, a source sense electrode. In a plan view, the pair of principal surface electrodes 224 are arranged on both sides of the principal surface electrode 222 in the second direction y. Note that the second chip 22 may have only one of the pair of principal surface electrodes 224, or may have neither of the pair of principal surface electrodes 224.
  • the second back surface electrode 223 is disposed on the second back surface 22b.
  • the second back surface electrode 223 is provided facing the main surface 101 of the second mounting portion 10B.
  • a current corresponding to the power before being converted by the second chip 22 flows through the second back surface electrode 223.
  • the second back surface electrode 223 is, for example, a collector electrode, and in an example where the second chip 22 is a MOSFET, the second back surface electrode 223 is, for example, a drain electrode.
  • the semiconductor device A10 further includes two die bonding layers 231, 232.
  • Each of the two die bonding layers 231, 232 is conductive.
  • Each of the die bonding layers 231, 232 is, for example, solder.
  • each of the die bonding layers 231, 232 may be a sintered metal.
  • the die bonding layer 231 is interposed between the main surface 101 of the first mounting portion 10A and the first back electrode 213 of the first chip 21.
  • the die bonding layer 231 joins the main surface 101 of the first mounting portion 10A and the first back electrode 213 of the first chip 21. This allows the first back electrode 213 of the first chip 21 to be conductive to the first mounting portion 10A.
  • the die bonding layer 232 is interposed between the main surface 101 of the second mounting portion 10B and the second back electrode 223 of the second chip 22.
  • the die bonding layer 232 joins the main surface 101 of the second mounting portion 10B and the second back electrode 223 of the second chip 22. This allows the second back electrode 223 of the second chip 22 to be conductive to the second mounting portion 10B.
  • the multiple terminal leads 13 are located on the side opposite to the side where the second end face 112 faces the first mounting portion 10A and the second mounting portion 10B in the second direction y. At least one of the multiple terminal leads 13 is electrically connected to either the first chip 21 or the second chip 22.
  • the multiple terminal leads 13 are arranged along the first direction x.
  • the multiple terminal leads 13 include a first terminal lead 14, a second terminal lead 15, a third terminal lead 16, a fourth terminal lead 171, a fifth terminal lead 181, a sixth terminal lead 172, and a seventh terminal lead 182.
  • the first terminal lead 14 is located away from the first mounting portion 10A and the second mounting portion 10B in the second direction y, and is located between the second terminal lead 15 and the third terminal lead 16 in the first direction x.
  • the first terminal lead 14 extends along the second direction y.
  • the first terminal lead 14 is electrically connected to the second main surface electrode 221 of the second chip 22.
  • the first terminal lead 14 includes a covering portion 14A and an exposed portion 14B.
  • the covering portion 14A is covered with the sealing resin 50.
  • the exposed portion 14B is connected to the covering portion 14A and is exposed from the third side surface 55 of the sealing resin 50.
  • the exposed portion 14B extends away from the first mounting portion 10A and the second mounting portion 10B in the second direction y.
  • the surface of the exposed portion 14B is, for example, tin-plated.
  • the covering portion 14A of the first terminal lead 14 has a second seating surface 14C and a second upright surface 14D.
  • the second seating surface 14C faces the same side in the thickness direction z as the main surfaces 101 of the first mounting portion 10A and the second mounting portion 10B, and is located lower in the thickness direction z than the upper surface of the covering portion 14A (the surface facing upward in the thickness direction z).
  • the second upright surface 14D faces in a direction perpendicular to the thickness direction z, and is connected to the second seating surface 14C and the upper surface of the covering portion 14A.
  • the second seating surface 14C and the second upright surface 14D form a step in the covering portion 14A of the first terminal lead 14.
  • the second terminal lead 15 includes a portion extending along the second direction y and is connected to the first mounting portion 10A. Therefore, the second terminal lead 15 is electrically connected to the first back electrode 213 of the first chip 21 via the first mounting portion 10A.
  • the second terminal lead 15 is a P terminal (positive electrode) to which the DC power supply voltage to be converted is applied.
  • the second terminal lead 15 includes a covering portion 15A and an exposed portion 15B. As shown in FIG. 4, the covering portion 15A is connected to the third end surface 113 of the first mounting portion 10A and is covered with the sealing resin 50. When viewed in the first direction x, the covering portion 15A is bent. As shown in FIGS.
  • the exposed portion 15B is connected to the covering portion 15A and is exposed from the third side surface 55 of the sealing resin 50.
  • the exposed portion 15B extends away from the first mounting portion 10A in the second direction y.
  • the surface of exposed portion 15B is, for example, tin-plated.
  • the third terminal lead 16 includes a portion extending along the second direction y and is connected to the second mounting portion 10B. Therefore, the third terminal lead 16 is electrically connected to the second back electrode 223 of the second chip 22 via the second mounting portion 10B.
  • the AC power converted by the first chip 21 and the second chip 22 is output from the third terminal lead 16.
  • the third terminal lead 16 includes a covering portion 16A and an exposed portion 16B. As shown in FIG. 4, the covering portion 16A is connected to the third end surface 113 of the second mounting portion 10B and is covered with the sealing resin 50. When viewed in the first direction x, the covering portion 16A is bent in the same manner as the covering portion 15A of the second terminal lead 15. As shown in FIGS.
  • the exposed portion 16B is connected to the covering portion 16A and is exposed from the third side surface 55 of the sealing resin 50.
  • the exposed portion 16B extends away from the second mounting portion 10B in the second direction y.
  • the surface of the exposed portion 16B is plated with, for example, tin.
  • the fourth terminal lead 171 is located away from the first mounting portion 10A in the second direction y and is located on one side in the first direction x.
  • the sixth terminal lead 172 is located away from the second mounting portion 10B in the second direction y and is located on the other side in the first direction x.
  • the fourth terminal lead 171 is electrically connected to the principal surface electrode 212 (gate electrode) of the first chip 21.
  • a drive signal (gate voltage) for driving the first chip 21 is applied to the fourth terminal lead 171.
  • the sixth terminal lead 172 is electrically connected to the principal surface electrode 222 (gate electrode) of the second chip 22.
  • a drive signal (gate voltage) for driving the second chip 22 is applied to the sixth terminal lead 172.
  • the fourth terminal lead 171 includes a covering portion 171A and an exposed portion 171B.
  • the covering portion 171A is covered with the sealing resin 50.
  • the exposed portion 171B is connected to the covering portion 171A and is exposed from the third side surface 55 of the sealing resin 50.
  • the exposed portion 171B extends in the second direction y away from the first mounting portion 10A.
  • the surface of the exposed portion 171B is, for example, tin-plated.
  • the sixth terminal lead 172 includes a covering portion 172A and an exposed portion 172B.
  • the covering portion 172A is covered with the sealing resin 50.
  • the exposed portion 172B is connected to the covering portion 172A and is exposed from the sealing resin 50.
  • the exposed portion 172B extends in the second direction y away from the second mounting portion 10B.
  • the surface of the exposed portion 172B is, for example, tin-plated.
  • the fifth terminal lead 181 is located away from the first mounting portion 10A in the second direction y, and is located between the second terminal lead 15 and the fourth terminal lead 171 in the first direction x.
  • the seventh terminal lead 182 is located away from the second mounting portion 10B in the second direction y, and is located between the third terminal lead 16 and the sixth terminal lead 172 in the first direction x.
  • the fifth terminal lead 181 is electrically connected to the principal surface electrode 214 (emitter sense electrode) of the first chip 21.
  • a voltage corresponding to the current flowing through the principal surface electrode 214 (first principal surface electrode 211) of the first chip 21 is applied to the fifth terminal lead 181.
  • the seventh terminal lead 182 is electrically connected to the second principal surface electrode 221 (emitter sense electrode) of the second chip 22.
  • a voltage corresponding to the current flowing through the principal surface electrode 224 (second principal surface electrode 221) of the second chip 22 is applied to the seventh terminal lead 182.
  • the fifth terminal lead 181 includes a covering portion 181A and an exposed portion 181B.
  • the covering portion 181A is covered with the sealing resin 50.
  • the exposed portion 181B is connected to the covering portion 181A and is exposed from the third side surface 55 of the sealing resin 50.
  • the exposed portion 181B extends in the second direction y away from the first mounting portion 10A.
  • the surface of the exposed portion 181B is, for example, tin-plated.
  • the seventh terminal lead 182 includes a covering portion 182A and an exposed portion 182B.
  • the covering portion 182A is covered with the sealing resin 50.
  • the exposed portion 182B is connected to the covering portion 182A and is exposed from the third side surface 55 of the sealing resin 50.
  • the exposed portion 182B extends in the second direction y away from the second mounting portion 10B.
  • the surface of the exposed portion 182B is, for example, tin-plated.
  • the heights h of the exposed portions 14B of the first terminal lead 14, 15B of the second terminal lead 15, and 16B of the third terminal lead 16 are all the same (or approximately the same). Furthermore, the thicknesses of these are all the same (or approximately the same). Therefore, when viewed in the first direction x, at least a portion of the first terminal lead 14 (exposed portion 14B) overlaps with each of the second terminal lead 15 and the third terminal lead 16 (see FIG. 7).
  • the conductive member 31 is electrically connected to the semiconductor circuit section 20 (first chip 21).
  • the conductive member 31 is an example of a "first conductive member" as described in the claims. As shown in FIG. 3, the conductive member 31 is joined to the first main surface electrode 211 of the first chip 21 and the second mounting section 10B. As a result, the first main surface electrode 211 is electrically connected to the second mounting section 10B and the second back surface electrode 223 of the second chip 22.
  • the conductive member 31 contains copper.
  • the conductive member 31 is a metal clip.
  • the conductive member 31 has a first body section 311, a plurality of first joints 312, a second joint 313, a plurality of first connecting sections 314, and a second connecting section 315.
  • the first body portion 311 forms a main portion of the conductive member 31.
  • the first body portion 311 extends in the first direction x.
  • the first body portion 311 extends linearly between the first chip 21 and the second chip 22 in a plan view.
  • the first body portion 311 straddles between the first mounting portion 10A and the second mounting portion 10B.
  • the first body portion 311 is located above the multiple first joint portions 312 and the second joint portions 313 in the thickness direction z.
  • the first body portion 311 includes two partition portions 311a, 311b.
  • partition 311a is connected to a plurality of first connecting portions 314 and partition 311b.
  • Partition 311b is connected to partition 311a and second connecting portion 315.
  • the width of partition 311b (dimension in the second direction y) is smaller than the width of partition 311a (dimension in the second direction y).
  • first main body portion 311 has an L-shape in a plan view.
  • the first joints 312 are each joined to the first principal surface electrode 211 of the first chip 21. As shown in FIG. 3, 4 and 15, the first joints 312 are spaced apart from one another in the second direction y. The first joints 312 are arranged parallel to one another (or approximately parallel) in a plan view. Each of the first joints 312 is connected to the first body 311 (partition 311a) via a corresponding one of the first connecting portions 314. The first connecting portions 314 are connected to the first body 311 and the first joints 312. As shown in FIG. 9, each of the first connecting portions 314 is bent in the thickness direction z.
  • the second joint 313 is joined to the first seating surface 103 of the second mounting portion 10B.
  • the second joint 313 extends in the second direction y. At least a portion of the second joint 313 is contained in an area defined by the first seating surface 103 and the first upright surface 104 of the second mounting portion 10B.
  • the second joint 313 is connected to the first main body portion 311 (partition portion 311b) via the second connecting portion 315. As shown in Figure 9, the second connecting portion 315 is bent in the thickness direction z.
  • the second joint 313 is located on the opposite side to the first joint 312 with the first main body portion 311 in between.
  • the semiconductor device A10 further includes a first bonding layer 33.
  • the first bonding layer 33 is interposed between the first main surface electrode 211 of the first chip 21 and each of the first bonding portions 312.
  • the first bonding layer 33 bonds the first main surface electrode 211 to each of the first bonding portions 312.
  • the first bonding layer 33 is conductive.
  • the first bonding layer 33 is, for example, solder.
  • the first bonding layer 33 may be a sintered metal.
  • each of the multiple first bonding portions 312 is 0.1 mm or more and is not more than twice the maximum thickness Tmax (see FIG. 10) of the first bonding layer 33.
  • the maximum thickness Tmax of the first bonding layer 33 is greater than the thickness of the first chip 21.
  • the semiconductor device A10 further includes a second bonding layer 34.
  • the second bonding layer 34 is interposed between the first seating surface 103 of the second mounting portion 10B and the second bonding portion 313.
  • the second bonding layer 34 bonds the second mounting portion 10B and the second bonding portion 313.
  • the second bonding layer 34 is conductive.
  • the second bonding layer 34 is, for example, solder.
  • the second bonding layer 34 may be a sintered metal.
  • the conductive member 32 is electrically connected to the semiconductor circuit section 20 (second chip 22).
  • the conductive member 32 is an example of a "second conductive member" as described in the claims. As shown in FIG. 3, the conductive member 32 is joined to the second main surface electrode 221 of the second chip 22 and the covering portion 14A of the first terminal lead 14. As a result, the second main surface electrode 221 is electrically connected to the first terminal lead 14.
  • the conductive member 32 contains copper.
  • the conductive member 32 is a metal clip.
  • the conductive member 32 has a second body section 321, a third joint section 322, a plurality of fourth joint sections 323, a third connection section 324, and a plurality of fourth connection sections 325.
  • the second body portion 321 forms a main portion of the conductive member 32.
  • the second body portion 321 is bent into a hook shape.
  • the second body portion 321 overlaps the main surface 101 of the second mounting portion 10B.
  • the second body portion 321 is located above the third joint portion 322 and the multiple fourth joint portions 323 in the thickness direction z.
  • the second body portion 321 includes multiple partition portions 321a, 321b, and 321c.
  • partition 321a is connected to third connecting portion 324 and partition 321b.
  • Partition 321a extends from third connecting portion 324 in the second direction y in a plan view.
  • Partition 321b is connected to two partitions 321a and 321c.
  • Partition 321b extends in the first direction x in a plan view.
  • Partition 321c is connected to partition 321b and a plurality of fourth connecting portions 325.
  • Partition 321c is strip-shaped with the second direction y as the longitudinal direction in a plan view.
  • the third joint 322 is joined to the second seating surface 14C of the first terminal lead 14.
  • the third joint 322 extends in the first direction x. At least a portion of the third joint 322 is contained in an area defined by the second seating surface 14C and the second upright surface 14D of the first terminal lead 14.
  • the third joint 322 is connected to the second body portion 321 (partition portion 321a) via the third connecting portion 324. As shown in Figure 13, the third connecting portion 324 is bent in the thickness direction z.
  • the third joint 322 is located on the opposite side to the fourth joint 323 with the second body portion 321 in between.
  • the multiple fourth joints 323 are each joined to the second principal surface electrode 221 of the second chip 22. As shown in FIG. 3, 4 and 16, the multiple fourth joints 323 are positioned apart from one another in the second direction y. The multiple fourth joints 323 are arranged parallel to one another (or approximately parallel) in a plan view. Each of the multiple fourth joints 323 is connected to the second body 321 (partition portion 321c) via a corresponding one of the multiple fourth connecting portions 325. The multiple fourth connecting portions 325 are connected to the second body 321 and the multiple fourth joints 323. As shown in FIG. 9, each fourth connecting portion 325 is bent in the thickness direction z.
  • the semiconductor device A10 further includes a third bonding layer 35.
  • the third bonding layer 35 is interposed between the second seating surface 14C of the first terminal lead 14 and the third bonding portion 322.
  • the third bonding layer 35 bonds the covering portion 14A of the first terminal lead 14 to the third bonding portion 322.
  • the third bonding layer 35 is conductive.
  • the third bonding layer 35 is, for example, solder.
  • the third bonding layer 35 may be a sintered metal.
  • the semiconductor device A10 further includes a fourth bonding layer 36.
  • the fourth bonding layer 36 is interposed between the second main surface electrode 221 of the second chip 22 and the multiple fourth bonding portions 323.
  • the fourth bonding layer 36 bonds the second main surface electrode 221 of the second chip 22 to the multiple fourth bonding portions 323.
  • the fourth bonding layer 36 is conductive.
  • the fourth bonding layer 36 is, for example, solder.
  • the fourth bonding layer 36 may be a sintered metal.
  • each of the multiple fourth bonding portions 323 is 0.1 mm or more and is not more than twice the maximum thickness Tmax (see FIG. 11) of the fourth bonding layer 36.
  • the maximum thickness Tmax of the fourth bonding layer 36 is greater than the thickness of the second chip 22.
  • Each of the multiple conductive members 41A, 41B, 42A, and 42B is, for example, a bonding wire.
  • the composition of each of the multiple conductive members 41A, 41B, 42A, and 42B includes gold.
  • the composition of each of the multiple conductive members 41A, 41B, 42A, and 42B may include copper or aluminum (Al).
  • the conductive member 41A is joined to the principal surface electrode 212 of the first chip 21 and the covering portion 171A of the fourth terminal lead 171. This allows the fourth terminal lead 171 to be electrically connected to the principal surface electrode 212 of the first chip 21.
  • the conductive member 41B is joined to the principal surface electrode 222 of the second chip 22 and the covering portion 172A of the sixth terminal lead 172. This allows the sixth terminal lead 172 to be electrically connected to the principal surface electrode 222 of the second chip 22.
  • the conductive member 42A is joined to one of the pair of principal surface electrodes 214 of the first chip 21 and the covering portion 181A of the fifth terminal lead 181. This allows the fifth terminal lead 181 to be electrically connected to the principal surface electrode 214 of the first chip 21.
  • the conductive member 42B is joined to one of the pair of principal surface electrodes 224 of the second chip 22 and the covering portion 182A of the seventh terminal lead 182. This allows the seventh terminal lead 182 to be electrically connected to the principal surface electrode 224 of the second chip 22.
  • the insulating member 60 contacts the two conductive members 31, 32.
  • the two conductive members 31, 32 are fixed to each other by the insulating member 60.
  • the insulating member 60 is covered with the sealing resin 50.
  • the insulating member 60 contains, for example, the same resin material as the sealing resin 50. Note that the insulating member 60 is not limited in any way as long as it contains an insulating material.
  • the shape of the insulating member 60 in a planar view is not limited in any way, but is rectangular in the illustrated example.
  • the insulating member 60 is formed, for example, in a part where the two conductive members 31, 32 are close to each other in a planar view.
  • a part of the conductive member 31 and a part of the conductive member 32 are sandwiched by the insulating member 60 in the thickness direction z.
  • the insulating member 60 is formed, for example, across the first main body portion 311 of the conductive member 31 and the second main body portion 321 of the conductive member 32 in a planar view. In this embodiment, as shown in Figures 3 and 9, the insulating member 60 is not in contact with any of the first connecting portion 314, the second connecting portion 315, the third connecting portion 324, and the fourth connecting portion 325. Note that the range in which the insulating member 60 is formed is not limited to the size and shape shown in the figures, as long as it spans the two conductive members 31 and 32.
  • the semiconductor device A10 configured as described above, the first main surface electrode 211 of the first chip 21 and the second back surface electrode 223 of the second chip 22 are electrically connected. Therefore, the semiconductor device A10 forms a half-bridge circuit using two transistors (the first chip 21 and the second chip 22).
  • Figures 18 and 19 are plan views showing one step in the method for manufacturing the semiconductor device A10.
  • Figure 20 is a cross-sectional view showing one step in the method for manufacturing the semiconductor device A10, and corresponds to the cross section of Figure 9.
  • the lead frame 30 includes a frame portion 301, a number of hanging portions 302, and two conductive members 31, 32.
  • the two conductive members 31, 32 are each supported by the frame portion 301 via some of the number of hanging portions 302.
  • an insulating member 60 is formed on the lead frame 30.
  • the insulating member 60 is formed so as to straddle the two conductive members 31, 32.
  • the two conductive members 31, 32 are fixed by the insulating member 60 in the lead frame 30 state.
  • the insulating member 60 contains, for example, epoxy resin, and in this example, the insulating member 60 is formed by, for example, molding.
  • the two conductive members 31, 32 are cut off from the frame portion 301. For example, they are cut along the cutting line CL shown in FIG. 19. This results in the formation of two conductive members 31, 32 fixed by the insulating member 60.
  • the two conductive members 31, 32 are joined to the semiconductor circuit section 20 (the first chip 21 and the second chip 22) while being fixed with the insulating member 60.
  • a lead frame including the first mounting section 10A, the second mounting section 10B and a plurality of terminal leads 13 is prepared, and the first chip 21 and the second chip 22 are joined to the first mounting section 10A and the second mounting section 10B, respectively.
  • the plurality of terminal leads 13 are connected to each other.
  • a number of conductive members 41A, 41B, 42A, and 42B are formed, and then a sealing resin 50 is formed to cover the two conductive members 31 and 32 and the insulating member 60. After that, the multiple terminal leads 13 that are connected to each other are each cut off. Through the above steps, the semiconductor device A10 is manufactured.
  • the functions and effects of the semiconductor device A10 and its manufacturing method according to the first embodiment are as follows.
  • the semiconductor device A10 includes an insulating member 60 that contacts the two conductive members 31, 32.
  • the two conductive members 31, 32 are fixed by the insulating member 60.
  • the two conductive members 31, 32 can be fixed by the insulating member 60 and then joined to the semiconductor circuit section 20 (the first chip 21 and the second chip 22). Therefore, since the two conductive members 31, 32 can be arranged together, the semiconductor device A10 can improve production efficiency.
  • the two conductive members 31, 32 are fixed and arranged with the insulating member 60, so that deviation in their relative positional relationship is suppressed.
  • the semiconductor device A10 can suppress the two conductive members 31, 32 from contacting each other.
  • the distance between the two conductive members 31, 32 can be reduced.
  • the mutual inductance generated by the current flowing through the conductive member 31 and the current flowing through the conductive member 32 can be increased, so that the semiconductor device A10 can reduce the parasitic inductance.
  • each of the two conductive members 31, 32 can be enlarged, so that the wiring resistance and self-inductance in the two conductive members 31, 32 can be reduced.
  • the semiconductor device A10 can reduce the parasitic inductance.
  • the first joint 312 of the conductive member 31 is joined to the first main surface electrode 211 by a first bonding layer 33.
  • the second joint 313 of the conductive member 31 is joined to the second mounting portion 10B by a second bonding layer 34.
  • the third joint 322 of the conductive member 32 is joined to the first terminal lead 14 by a third bonding layer 35.
  • the fourth joint 323 of the conductive member 32 is joined to the second main surface electrode 221 by a fourth bonding layer 36.
  • the first bonding layer 33, the second bonding layer 34, the third bonding layer 35 and the fourth bonding layer 36 are each, for example, solder.
  • the insulating member 60 is formed in the area where the two conductive members 31, 32 are adjacent to each other.
  • an insulator can be disposed in the area where the two conductive members 31, 32 are adjacent to each other, so that the dielectric strength voltage between the two conductive members 31, 32 can be ensured.
  • the insulating member 60 contains the same resin material as the sealing resin 50. With this configuration, the dielectric strength voltage between the two conductive members 31, 32 can be made equivalent to that when the sealing resin 50 is disposed between the two conductive members 31, 32. In addition, since the difference in the linear expansion coefficient between the insulating member 60 and the sealing resin 50 can be suppressed, the thermal stress caused by the difference in the linear expansion coefficients can be suppressed.
  • the insulating member 60 is disposed at approximately the center of the two conductive members 31, 32 in plan view.
  • the two conductive members 31, 32 are transported while fixed by the insulating member 60.
  • the semiconductor device A10 can prevent the two conductive members 31, 32 from being tilted.
  • the two conductive members 31, 32 are not brought into contact with the transport member, so deformation of the two conductive members 31, 32 can also be prevented.
  • the semiconductor circuit section 20 includes a first chip 21 and a second chip 22.
  • the first chip 21 and the second chip 22 are covered with a sealing resin 50.
  • the semiconductor device A10 has two chips (the first chip 21 and the second chip 22) packaged together with a single sealing resin 50. Therefore, the semiconductor device A10 can reduce the mounting area on the circuit board on which the semiconductor device A10 is mounted.
  • FIGS. 21 and 22 show a semiconductor device A11 according to a first modified example of the first embodiment.
  • the semiconductor device A11 differs from the semiconductor device A10 in the following respect. That is, the first chip 21 of the semiconductor device A11 is a diode, not a transistor.
  • the first chip 21 of the semiconductor device A11 has a first main surface electrode 211 and a first back surface electrode 213. As shown in FIG. 21, the first chip 21 of the semiconductor device A11 does not have main surface electrodes 212, 214. As shown in FIG. 22, the first chip 21 of the semiconductor device A11 is a diode, and the first main surface electrode 211 is, for example, an anode electrode, and the first back surface electrode 213 is, for example, a cathode electrode.
  • the semiconductor device A11 does not include either of the two conductive members 41A, 42A.
  • the fourth terminal lead 171 and the fifth terminal lead 181 are not electrically connected to either the first chip 21 or the second chip 22. Therefore, in the semiconductor device A11, the fourth terminal lead 171 and the fifth terminal lead 181 are non-connect terminals.
  • the semiconductor device A11 includes the conductive member 42B, but in a configuration different from this example, the semiconductor device A11 may not include the conductive member 42B.
  • the semiconductor device A11 As shown in FIG. 22, in the semiconductor device A11, the first main surface electrode 211 (anode electrode) of the first chip 21 and the second back surface electrode 223 (collector electrode) of the second chip 22 are electrically connected.
  • the semiconductor device A11 with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15, the high voltage side is a diode and the low voltage side is a transistor.
  • the semiconductor device A11 is used, for example, as a boost chopper circuit.
  • FIGS. 23 and 24 show a semiconductor device A12 according to a second modified example of the first embodiment.
  • the semiconductor device A12 differs from the semiconductor device A10 in the following respect. That is, the second chip 22 of the semiconductor device A12 is a diode, not a transistor.
  • the second chip 22 of the semiconductor device A12 has a second main surface electrode 221 and a second back surface electrode 223. As shown in FIG. 23, the second chip 22 of the semiconductor device A12 does not have main surface electrodes 222, 224. As shown in FIG. 24, the second chip 22 of the semiconductor device A12 is a diode, and the second main surface electrode 221 is, for example, an anode electrode, and the second back surface electrode 223 is, for example, a cathode electrode.
  • the semiconductor device A12 does not include either of the two conductive members 41B, 42B.
  • the sixth terminal lead 172 and the seventh terminal lead 182 are not electrically connected to either the first chip 21 or the second chip 22. Therefore, in the semiconductor device A12, the sixth terminal lead 172 and the seventh terminal lead 182 are non-connect terminals.
  • the semiconductor device A12 includes a conductive member 42A, but in a configuration different from this example, the semiconductor device A12 may not include the conductive member 42A.
  • the semiconductor device A12 As shown in FIG. 24, in the semiconductor device A12, the first main surface electrode 211 (emitter electrode) of the first chip 21 and the second back surface electrode 223 (cathode electrode) of the second chip 22 are electrically connected.
  • the high voltage side is a transistor and the low voltage side is a diode.
  • the semiconductor device A12 is used, for example, as a step-down chopper circuit.
  • FIGS. 25 and 26 show a semiconductor device A13 according to a third modified example of the first embodiment.
  • the semiconductor device A13 differs from the semiconductor device A10 in the following respect. That is, each of the first chip 21 and the second chip 22 of the semiconductor device A13 is a diode rather than a transistor.
  • the first chip 21 of the semiconductor device A13 has a first main surface electrode 211 and a first back surface electrode 213. As shown in FIG. 25, the first chip 21 of the semiconductor device A13 does not have main surface electrodes 212, 214. As shown in FIG. 26, the first chip 21 of the semiconductor device A13 is a diode, the first main surface electrode 211 is an anode electrode, and the first back surface electrode 213 is a cathode electrode.
  • the second chip 22 of the semiconductor device A13 has a second main surface electrode 221 and a second back surface electrode 223. As shown in FIG. 25, the second chip 22 of the semiconductor device A13 does not have main surface electrodes 222, 224. As shown in FIG. 26, the second chip 22 of the semiconductor device A13 is a diode, the second main surface electrode 221 is an anode electrode, and the second back surface electrode 223 is a cathode electrode.
  • the semiconductor device A13 does not include any of the multiple conductive members 41A, 42A, 41B, 42B.
  • the fourth terminal lead 171, the fifth terminal lead 181, the sixth terminal lead 172, and the seventh terminal lead 182 are not conductive to either the first chip 21 or the second chip 22. Therefore, in the semiconductor device A13, the fourth terminal lead 171, the fifth terminal lead 181, the sixth terminal lead 172, and the seventh terminal lead 182 are each a non-connect terminal.
  • the semiconductor device A13 As shown in FIG. 26, in the semiconductor device A13, the first main surface electrode 211 (anode electrode) of the first chip 21 and the second back surface electrode 223 (cathode electrode) of the second chip 22 are electrically connected. In the semiconductor device A13, both the high voltage side and the low voltage side are diodes with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15.
  • the semiconductor device A13 is a diode bridge circuit.
  • the two conductive members 31, 32 are fixed by an insulating member 60, similar to the semiconductor device A10. Therefore, in the semiconductor devices A11 to A13, the two conductive members 31, 32 can be arranged together, similar to the semiconductor device A10, and production efficiency can be improved.
  • each of the semiconductor devices A11 to A13 has the same configuration as the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10. For example, each of the semiconductor devices A11 to A13 can prevent the two conductive members 31, 32 from contacting each other.
  • each of the semiconductor devices A11 to A13 can increase the mutual inductance caused by the current flowing through the conductive member 31 and the current flowing through the conductive member 32, and therefore can reduce parasitic inductance.
  • the semiconductor device of the present disclosure can configure four types of power conversion circuits (bridge circuits using transistors, step-up chopper circuits, step-down chopper circuits, and bridge circuits using diodes) by combining the first chip 21 and the second chip 22.
  • the configurations of the terminal leads 13 and the sealing resin 50 are common to the semiconductor devices A10 to A13. Therefore, the semiconductor device of the present disclosure can configure any of the four types of power conversion circuits while keeping the appearance of the package the same.
  • the semiconductor device of the present disclosure can utilize the configurations of the terminal leads 13 and the sealing resin 50 as they are, even if the first chip 21 and the second chip 22 are different in terms of whether they are transistors or diodes.
  • the semiconductor device of the present disclosure can standardize the package structure regardless of which of the four types of power conversion circuits is used, which is preferable in terms of improving productivity.
  • the semiconductor device of the present disclosure is arranged such that the center of gravity of the first chip 21 overlaps with the center of the first mounting portion 10A in a planar view. This configuration is preferable for sharing the conductive member 31.
  • the semiconductor device of the present disclosure is arranged such that the center of gravity of the second chip 22 overlaps with the center of the second mounting portion 10B in a planar view. This configuration is preferable for sharing the conductive member 32.
  • FIGS. 27 to 30 show a semiconductor device A20 according to the second embodiment.
  • the semiconductor device A20 differs from the semiconductor device A10 in the following respects.
  • each of the multiple conductive members 41A, 42A, 41B, and 42B is a conductive plate-like member rather than a bonding wire.
  • a first insulating member 61, a second insulating member 62, and a third insulating member 63 are provided.
  • the first chip 21 and the second chip 22 are each a MOSFET as shown in FIG. 30, but may be an IGBT (or an RC-IGBT) as in the semiconductor device A10.
  • each of the plurality of conductive members 41A, 42A, 41B, and 42B includes copper or a copper alloy. Unlike this example, the composition of each of the plurality of conductive members 41A, 42A, 41B, and 42B may include other metal materials.
  • the conductive member 41A is joined to the main surface electrode 212 (first chip 21) and the covering portion 171A (fourth terminal lead 171) by a conductive bonding material.
  • the conductive member 42A is joined to the main surface electrode 214 (first chip 21) and the covering portion 181A (fifth terminal lead 181) by a conductive bonding material.
  • the conductive member 41B is joined to the main surface electrode 222 (second chip 22) and the covering portion 172A (sixth terminal lead 172) by a conductive bonding material.
  • the conductive member 42B is joined to the main surface electrode 224 (second chip 22) and the covering portion 182A (seventh terminal lead 182) by a conductive bonding material.
  • the first insulating member 61, the second insulating member 62, and the third insulating member 63 each contain, for example, the same resin material as the sealing resin 50. Unlike this example, the composition of each of the first insulating member 61, the second insulating member 62, and the third insulating member 63 may be another insulating material.
  • the first insulating member 61 like the insulating member 60 of the semiconductor device A10, is formed across and secures the two conductive members 31 and 32.
  • the second insulating member 62 contacts the two conductive members 41A, 42A and fixes them together. A portion of the conductive member 41A and a portion of the conductive member 42A are covered by the second insulating member 62 in the thickness direction z.
  • the shape of the second insulating member 62 in a plan view is not limited in any way, but is rectangular in the illustrated example.
  • the third insulating member 63 contacts the two conductive members 41B, 42B and fixes them in place. A portion of the conductive member 41B and a portion of the conductive member 42B are covered by the third insulating member 63 in the thickness direction z.
  • the planar shape of the third insulating member 63 is not limited in any way, but is rectangular in the illustrated example.
  • the first joint 312 of the conductive member 31 includes two strip portions 312a, as shown in Figures 27 and 28. As shown in Figures 27 and 28, the two strip portions 312a are positioned apart from each other in the second direction y. The longitudinal direction of each of the two strip portions 312a is the first direction x. The two strip portions 312a are arranged parallel to each other (or approximately parallel) in a plan view. Unlike this example, the first joint 312 does not have to be separated into two strip portions 312a.
  • the fourth joint 323 of the conductive member 32 includes two strip portions 323a, as shown in Figures 27 and 28. As shown in Figures 27 and 28, the two strip portions 323a are positioned apart from each other in the second direction y. The longitudinal direction of each of the two strip portions 323a is the first direction x. The two strip portions 323a are arranged parallel to each other (or approximately parallel) in a planar view. Unlike this example, the fourth joint 323 does not have to be separated into two strip portions 323a.
  • the two conductive members 41A, 42A are fixed with a second insulating member 62 and then bonded to the first chip 21 (principal surface electrodes 212 and 214) and the covering portion 171A and the covering portion 181A.
  • the two conductive members 41A, 42A are formed from the same lead frame and are fixed with the second insulating member 62 when in the lead frame state.
  • the two conductive members 41B, 42B are fixed with a third insulating member 63 and then bonded to the second chip 22 (principal surface electrodes 222 and 224) and the covering portion 172A and the covering portion 182A.
  • the two conductive members 41B, 42B are formed from the same lead frame and are fixed with the third insulating member 63 when in the lead frame state.
  • the semiconductor device A20 the two conductive members 31, 32 are fixed by the first insulating member 61. Therefore, the semiconductor device A20 can arrange the two first conductive members 31, 32 together, so that the semiconductor device A20 can improve production efficiency. Also, like the semiconductor device A10, the semiconductor device A20 can suppress deviation in the relative positional relationship between the two conductive members 31, 32, so that they can be prevented from contacting each other. Also, like the semiconductor device A10, the semiconductor device A20 can increase the mutual inductance generated by the current flowing through the conductive member 31 and the current flowing through the conductive member 32, so that the semiconductor device A20 can reduce parasitic inductance. In addition, the semiconductor device A20 has a common configuration with the semiconductor device A10, so that it has the same effects as the semiconductor device A10.
  • the two conductive members 41A, 42A are fixed with the second insulating member 62.
  • the two conductive members 41A, 42A can be fixed with the second insulating member 62 and then joined to the semiconductor circuit section 20. Therefore, since the two conductive members 41A, 42A can be arranged together, the semiconductor device A20 can improve production efficiency.
  • the semiconductor device A20 can suppress the two conductive members 41A, 42A from coming into contact with each other.
  • the two conductive members 41B, 42B are fixed with the third insulating member 63.
  • the two conductive members 41B, 42B can be fixed with the third insulating member 63 and then joined to the semiconductor circuit section 20. Therefore, since the two conductive members 41B, 42B can be arranged together, the semiconductor device A20 can improve production efficiency.
  • the two conductive members 41B, 42B are arranged after being fixed with the third insulating member 63, deviation in their relative positional relationship is suppressed. As a result, the semiconductor device A20 can suppress the two conductive members 41B, 42B from coming into contact with each other.
  • the semiconductor device A20 was provided with the first insulating member 61, the second insulating member 62, and the third insulating member 63.
  • the semiconductor device A20 may be configured to include one or two of the first insulating member 61, the second insulating member 62, and the third insulating member 63.
  • the semiconductor device A20 may be configured to include only the second insulating member 62.
  • the conductive member 41A is an example of a "first conductive member" as defined in the claims
  • the conductive member 42A is an example of a "second conductive member" as defined in the claims.
  • FIG. 31 shows a semiconductor device A21 according to a first modified example of the second embodiment.
  • the semiconductor device A21 like the semiconductor device A11, the first chip 21 is a diode rather than a transistor.
  • the semiconductor device A21 compared to the semiconductor device A20, the semiconductor device A21 does not include either of the two conductive members 41A, 42A, and does not include the second insulating member 62.
  • FIG. 32 shows a semiconductor device A22 according to a second modified example of the second embodiment.
  • the semiconductor device A22 like the semiconductor device A12, the second chip 22 is a diode rather than a transistor.
  • the semiconductor device A22 does not include either of the two conductive members 41B, 42B, and does not include the third insulating member 63.
  • FIG 33 shows a semiconductor device A23 according to a third modified example of the second embodiment.
  • each of the first chip 21 and the second chip 22 is a diode rather than a transistor.
  • the semiconductor device A23 does not include any of the multiple conductive members 41A, 42A, 41B, 42B, and does not include any of the second insulating member 62 and the third insulating member 63.
  • the two conductive members 31, 32 are fixed by the first insulating member 61, similar to the semiconductor device A20. Therefore, in the semiconductor devices A21 to A23, the two conductive members 31, 32 can be arranged together, similar to the semiconductor device A20, and production efficiency can be improved.
  • each of the semiconductor devices A21 to A23 has the same effect as the semiconductor device A20 due to the configuration common to the semiconductor device A20. For example, each of the semiconductor devices A21 to A23 can prevent the two conductive members 31, 32 from contacting each other.
  • each of the semiconductor devices A21 to A23 can increase the mutual inductance caused by the current flowing through the conductive member 31 and the current flowing through the conductive member 32, and therefore can reduce parasitic inductance.
  • the insulating member 60 may not sandwich the conductive member 31 and the conductive member 32 in the thickness direction z.
  • FIG. 34 shows a configuration example in the semiconductor device A10 in which the insulating member 60 is not formed below the conductive member 31 and the conductive member 32 in the thickness direction z.
  • FIG. 35 shows a configuration example in the semiconductor device A10 in which the insulating member 60 is not formed above the conductive member 31 and the conductive member 32 in the thickness direction z.
  • the two conductive members 31 and 32 can be fixed by the insulating member 60 (first insulating member 61) and arranged together.
  • the two conductive members 31 and 32 can be fixed more firmly if the insulating member 60 (first insulating member 61) is configured to sandwich the conductive member 31 and the conductive member 32 in the thickness direction z.
  • such a modification can be applied not only to the insulating member 60 (first insulating member 61), but also to each of the second insulating member 62 and the third insulating member 63.
  • the insulating member 60 (first insulating member 61) may be in contact with any of the first connecting portion 314, the second connecting portion 315, the third connecting portion 324, and the fourth connecting portion 325.
  • FIG. 36 and FIG. 37 show a configuration example in which the insulating member 60 is in contact with the second connecting portion 315 in the semiconductor device A10.
  • the two conductive members 31, 32 can be fixed with the insulating member 60 (first insulating member 61) and arranged together.
  • the formation range of the insulating member 60 is larger, so that the two conductive members 31, 32 can be fixed more firmly by the insulating member 60.
  • a through hole may be formed in the conductive member 31 in a portion covered by the insulating member 60.
  • a through hole may be formed in the conductive member 32 in a portion covered by the insulating member 60.
  • FIG. 38 shows a configuration example in which a through hole 319 is formed in the conductive member 31 and a through hole 329 is formed in the conductive member 32 in the semiconductor device A10.
  • the through hole 319 is formed in a portion of the first body portion 311 of the conductive member 31 that is covered by the insulating member 60.
  • the through hole 319 penetrates the first body portion 311 in the thickness direction z.
  • the through hole 329 is formed in a portion of the second body portion 321 of the conductive member 32 that is covered by the insulating member 60.
  • the through hole 329 penetrates the second body portion 321 in the thickness direction z.
  • Each of the through holes 319, 329 is filled with the insulating member 60.
  • the two conductive members 31, 32 can be fixed by the insulating member 60 and arranged together.
  • this modified example has the following effects. First, when the insulating member 60 is formed (molded), the resin material flows from the upper side in the thickness direction z of the conductive member 31 to the lower side in the thickness direction z through each of the through holes 319, 329, so that the occurrence of voids in the insulating member 60 can be suppressed. Second, the insulating member 60 formed in the through holes 319, 329 can suppress the insulating member 60 from peeling off from the conductive members 31 and 32.
  • unevenness may be formed on a part of the surface of the conductive member 31 that contacts the insulating member 60.
  • unevenness may be formed on a part of the surface of the conductive member 32 that contacts the insulating member 60.
  • FIG. 39 shows a configuration example in which the upper surface (surface facing upward in the thickness direction z) of the first main body portion 311 of the conductive member 31 and the upper surface (surface facing upward in the thickness direction z) of the second main body portion 321 of the conductive member 32 are rough surfaces (having fine unevenness) in the semiconductor device A10.
  • the two conductive members 31 and 32 can be fixed by the insulating member 60 and arranged together. Furthermore, in this modified example, the anchor effect due to the unevenness of the two conductive members 31 and 32 can prevent the insulating member 60 from peeling off from the conductive members 31 and 32.
  • the upper surfaces of the first body portion 311 and the second body portion 321 are rough, but the lower surfaces may also be rough, or only the areas in contact with the insulating member 60 may be rough.
  • the insulating member 60 may be, for example, an insulating adhesive sheet, instead of a molded resin material.
  • FIGS. 40 and 41 show a configuration example in which the insulating member 60 in the semiconductor device A20 is an insulating adhesive sheet.
  • the upper surfaces of the conductive member 31, the conductive member 32, the conductive member 41A, the conductive member 42A, the conductive member 41B, and the conductive member 42B are arranged at the same (or approximately the same) height in the thickness direction z.
  • the insulating member 60 is in contact with and adheres to a part of the upper surfaces of the two conductive members 31 and 32 and the multiple conductive members 41A, 42A, 41B, and 42B. Even in such a modified example, the two conductive members 31 and 32 can be fixed by the insulating member 60 and arranged together. Furthermore, in this modified example, the insulating member 60 can also collectively arrange the multiple conductive members 41A, 42A, 41B, and 42B.
  • the semiconductor circuit unit 20 may include a plurality of first chips 21.
  • the plurality of first chips 21 may all be transistors or diodes, or may include a transistor and a diode (for example, connected in anti-parallel to a transistor).
  • the semiconductor circuit unit 20 may include a plurality of second chips 22.
  • the plurality of second chips 22 may all be transistors or diodes, or may include a transistor and a diode (for example, connected in anti-parallel to a transistor).
  • the package structure of the semiconductor device disclosed herein is not limited to those exemplified in the above first to third embodiments (including their variations).
  • the semiconductor device disclosed herein can also be applied to other TO (Transistor Outline) packages.
  • the semiconductor devices A10 to A13 and A20 to A23 according to the first and second embodiments are an extension of a package structure called TO-247, but may also be extensions of other package structures called TO-220, TO-252, TO263, etc.
  • the semiconductor device disclosed herein makes it possible to package multiple semiconductor elements (first chip 21 and second chip 22) in a single sealing resin 50 while maintaining an appearance similar to that of a conventional TO package.
  • the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-mentioned embodiment.
  • the specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the method for manufacturing the semiconductor device according to the present disclosure can be freely designed in various ways.
  • the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure include the following embodiments. Appendix 1.
  • a semiconductor circuit unit A first conductive member that is electrically connected to the semiconductor circuit portion; A second conductive member that is electrically connected to the semiconductor circuit portion; an insulating member in contact with the first conductive member and the second conductive member; a sealing resin that covers the semiconductor circuit portion, the first conductive member, the second conductive member, and a part of the insulating member; Equipped with The first conductive member and the second conductive member are fixed by the insulating member.
  • the semiconductor circuit unit includes a first chip and a second chip, the first conductive member is joined to the first chip, 2. The semiconductor device according to claim 1, wherein the second conductive member is joined to the second chip.
  • Appendix 3. the first chip and the second chip are electrically connected in series; 3.
  • the semiconductor device wherein the semiconductor circuit portion forms a half-bridge circuit.
  • Appendix 4. a first mounting portion for mounting the first chip; a second mounting portion for mounting the second chip; and a first terminal lead spaced apart from the first mounting portion and the second mounting portion.
  • the first chip has a first main surface facing one side in a thickness direction of the sealing resin, a first back surface facing the other side in the thickness direction, a first main surface electrode formed on the first main surface, and a first back surface electrode formed on the first back surface;
  • the first back surface electrode faces the first mounting portion and is electrically connected to the first mounting portion;
  • the second chip has a second main surface facing the one side in the thickness direction, a second back surface facing the other side in the thickness direction, a second main surface electrode formed on the second main surface, and a second back surface electrode formed on the second back surface, 5.
  • the second back surface electrode faces the second mounting portion and is electrically connected to the second mounting portion.
  • the first conductive member electrically connects the first principal surface electrode and the second mounting portion;
  • Appendix 7. The semiconductor device according to claim 6, wherein the first mounting portion is located on one side of the second mounting portion in a first direction perpendicular to the thickness direction.
  • Appendix 8. a second terminal lead extending from the first mounting portion in a second direction perpendicular to the thickness direction and the first direction; a third terminal lead extending in the second direction from the second mounting portion; Further equipped with 8.
  • the semiconductor device wherein the first terminal lead is located between the second terminal lead and the third terminal lead in the first direction.
  • Appendix 10. A fourth terminal lead; A fifth terminal lead; a third conductive member electrically connecting the first chip and the fourth terminal lead; a fourth conductive member electrically connecting the first chip and the fifth terminal lead; Further equipped with 10.
  • the semiconductor device according to claim 9, wherein the fourth terminal lead and the fifth terminal lead are located on one side of the first direction relative to the second terminal lead and are adjacent to each other in the first direction.
  • Appendix 11 The insulating member is a first insulating member, and a second insulating member is further provided, the third conductive member and the fourth conductive member are each a plate-shaped member, 11.
  • Appendix 12. A sixth terminal lead; A seventh terminal lead; a fifth conductive member electrically connecting the second chip and the sixth terminal lead; a sixth conductive member electrically connecting the second chip and the seventh terminal lead; Further equipped with 12.
  • Appendix 13 Further comprising a third insulating member; each of the fifth conductive member and the sixth conductive member is a plate-shaped member; 13.
  • Appendix 14 the first chip is either a transistor or a diode; 14. The semiconductor device according to claim 2, wherein the second chip is either a transistor or a diode. Appendix 15. 15. The semiconductor device according to claim 1, wherein the insulating member is formed in a portion where the first conductive member and the second conductive member are adjacent to each other when viewed in a thickness direction of the sealing resin. Appendix 16. 16. The semiconductor device according to claim 1, wherein the insulating member contains the same resin material as the sealing resin. Appendix 17. 17. 17. The semiconductor device according to claim 1, wherein a portion of the first conductive member and a portion of the second conductive member are sandwiched between the insulating member in a thickness direction. Appendix 18.
  • a lead frame including a first conductive member and a second conductive member; a step of fixing the first conductive member and the second conductive member with an insulating member in the lead frame state; a step of joining the first conductive member and the second conductive member to a semiconductor circuit portion while the first conductive member and the second conductive member are fixed by the insulating member; and forming a sealing resin that covers the first conductive member, the second conductive member, and the semiconductor circuit portion.

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
PCT/JP2023/034106 2022-10-12 2023-09-20 半導体装置および半導体装置の製造方法 Ceased WO2024080089A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017169134A1 (ja) * 2016-03-30 2017-10-05 三菱電機株式会社 パワーモジュール及びその製造方法並びにパワーエレクトロニクス機器及びその製造方法
WO2018142863A1 (ja) * 2017-02-06 2018-08-09 富士電機株式会社 半導体モジュール、電気自動車、及びパワーコントロールユニット
WO2020079798A1 (ja) * 2018-10-18 2020-04-23 株式会社日産アーク 半導体装置及びその製造方法
WO2022025041A1 (ja) * 2020-07-28 2022-02-03 ローム株式会社 半導体装置
WO2022113617A1 (ja) * 2020-11-27 2022-06-02 ローム株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017169134A1 (ja) * 2016-03-30 2017-10-05 三菱電機株式会社 パワーモジュール及びその製造方法並びにパワーエレクトロニクス機器及びその製造方法
WO2018142863A1 (ja) * 2017-02-06 2018-08-09 富士電機株式会社 半導体モジュール、電気自動車、及びパワーコントロールユニット
WO2020079798A1 (ja) * 2018-10-18 2020-04-23 株式会社日産アーク 半導体装置及びその製造方法
WO2022025041A1 (ja) * 2020-07-28 2022-02-03 ローム株式会社 半導体装置
WO2022113617A1 (ja) * 2020-11-27 2022-06-02 ローム株式会社 半導体装置

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