WO2024077954A1 - 像素电路及其驱动方法 - Google Patents

像素电路及其驱动方法 Download PDF

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Publication number
WO2024077954A1
WO2024077954A1 PCT/CN2023/095034 CN2023095034W WO2024077954A1 WO 2024077954 A1 WO2024077954 A1 WO 2024077954A1 CN 2023095034 W CN2023095034 W CN 2023095034W WO 2024077954 A1 WO2024077954 A1 WO 2024077954A1
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WIPO (PCT)
Prior art keywords
module
light
phase
initialization
driving
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PCT/CN2023/095034
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English (en)
French (fr)
Inventor
盖翠丽
郭恩卿
潘康观
郭双
李俊峰
邢汝博
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2024077954A1 publication Critical patent/WO2024077954A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a pixel circuit and a driving method thereof.
  • the refresh frequencies in different working modes are different.
  • the display device displays static pictures and displays dynamic pictures of games
  • the refresh frequencies are different.
  • the display device needs to switch the refresh frequencies.
  • the present application provides a pixel circuit and a driving method thereof, so as to improve the display quality when the refresh frequency is switched.
  • an embodiment of the present application provides a pixel circuit, including: a data writing module, a driving module, a compensation module, a light emitting control module and a light emitting module;
  • the data writing module is configured to write a data voltage to the control terminal of the driving module during the data writing phase of the writing frame;
  • the compensation module is configured to compensate the threshold voltage of the driving module during the data writing phase of the writing frame
  • the light-emitting control module is configured to be turned on during the light-emitting phase of the writing frame and the holding frame, and the driving module is configured to drive the light-emitting module to emit light during the light-emitting phase;
  • the pixel circuit further includes a reset module, the reset module is electrically connected to the first end or the second end of the driving module, and the reset module is configured to reset the potential of the first end and the second end of the driving module to a fixed potential during the reset phase. Reset voltage;
  • the reset phase is between the data write phase and the light emission phase; in the hold frame, the reset phase is before the light emission phase.
  • an embodiment of the present application further provides a method for driving a pixel circuit, including:
  • the data writing module writes the data voltage to the control end of the driving module in the data writing phase
  • the compensation module compensates the threshold voltage of the driving module in the data writing phase of the writing frame
  • the reset module resets the potential of the first end and the second end of the driving module to a fixed reset voltage in the reset phase
  • the light-emitting control module is turned on in the light-emitting phase
  • the driving module drives the light-emitting module to emit light in the light-emitting phase
  • the reset module resets the potentials of the first terminal and the second terminal of the driving module to a fixed reset voltage in the reset phase
  • the light-emitting control module is turned on in the light-emitting phase
  • the driving module drives the light-emitting module to emit light in the light-emitting phase
  • the reset phase is between the data write phase and the light emission phase; in the hold frame, the reset phase is before the light emission phase.
  • the pixel circuit and driving method of the embodiment of the present application are provided with a pixel circuit including a reset module, the reset module being electrically connected to the first end or the second end of the driving module, the reset module resetting the potential of the first end and the second end of the driving module between the data writing stage and the light emitting stage of the writing frame, and resetting the potential of the first end and the second end of the driving module before the light emitting stage of the holding frame, thereby making the potential of the first end of the driving module the same before the light emitting stage of the writing frame and the holding frame, and the potential of the second end of the driving module the same before the light emitting stage of the writing frame and the holding frame, thereby making the bias state of the driving module the same before the light emitting stage of the writing frame and the holding frame, thereby facilitating the improvement of the transient characteristics of the driving module, so that the brightness of the light emitting module will not change suddenly when the refresh frequency is switched, and the brightness of the light emitting module will not change suddenly when the writing frame and the
  • FIG1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application.
  • FIG5 is a driving timing diagram of a writing frame of a pixel circuit provided by an embodiment of the present application.
  • FIG6 is a driving timing diagram of a pixel circuit for maintaining a frame provided by an embodiment of the present application.
  • FIG7 is a driving timing diagram of a writing frame of another pixel circuit provided in an embodiment of the present application.
  • FIG8 is a driving timing diagram of another pixel circuit for maintaining a frame provided by an embodiment of the present application.
  • FIG9 is a schematic diagram of another pixel circuit structure provided in an embodiment of the present application.
  • FIG10 is a driving timing sequence of a writing frame of another pixel circuit provided in an embodiment of the present application.
  • FIG11 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application.
  • FIG12 is a driving timing diagram of a writing frame of another pixel circuit provided in an embodiment of the present application.
  • FIG13 is a driving timing diagram of a writing frame of another pixel circuit provided in an embodiment of the present application.
  • FIG14 is a driving timing diagram of a pixel circuit for maintaining a frame provided by an embodiment of the present application.
  • FIG15 is a driving timing diagram of a writing frame of another pixel circuit provided in an embodiment of the present application.
  • FIG16 is a driving timing diagram of another pixel circuit for maintaining a frame provided by an embodiment of the present application.
  • FIG17 is a driving timing diagram of a writing frame of another pixel circuit provided in an embodiment of the present application.
  • FIG18 is a driving timing diagram of a writing frame of another pixel circuit provided in an embodiment of the present application.
  • FIG19 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application.
  • FIG20 is a driving timing diagram of a writing frame of another pixel circuit provided in an embodiment of the present application.
  • FIG21 is a flow chart of a driving method of a pixel circuit provided in an embodiment of the present application.
  • 22 is a flow chart of a driving method of a pixel circuit in a writing frame provided by an embodiment of the present application.
  • FIG. 23 is a flow chart of a driving method for a pixel circuit while maintaining a frame provided in an embodiment of the present application.
  • the skip frame is implemented, for example, when the refresh frequency is 60Hz, all 60 data frames are write frames, and data is written in each write frame; when the refresh frequency is 1Hz, on the basis of 60Hz, one data frame is used as a write frame, and the other data frames are used as hold frames, and data is only written in the write frame, and not in the hold frame.
  • FIG1 is a schematic diagram of the structure of a pixel circuit provided by the embodiment of the present application.
  • the pixel circuit includes: a data writing module 110, a driving module 120, a compensation module 130, a light-emitting control module 140 and a light-emitting module 150;
  • the data writing module 110 is configured to write a data voltage to the control end of the driving module 120 during the data writing phase of the writing frame;
  • the compensation module 130 is configured to compensate the threshold voltage of the driving module 120 during the data writing phase of the writing frame;
  • the light-emitting control module 140 is configured to be turned on during the light-emitting phase of the writing frame and the holding frame, and the driving module 120 is configured to drive the light-emitting module 150 to emit light during the light-emitting phase;
  • the pixel circuit also includes a reset module 160, the reset module 160 is electrically connected to the first end or the second end of the driving module 120, and the reset module 160 is configured to reset the potential
  • the pixel circuit can operate at different refresh frequencies. At a high refresh frequency, each data frame is a write frame; at a low refresh frequency, at least one data frame can be used as a write frame, and the other data frames can be used as hold frames.
  • the first end of the data writing module 110 is connected to the data line Data, and the second end of the data writing module 110 is connected to the first end of the driving module 120; the first end of the compensation module 130 is connected to the second end of the driving module 120, and the second end of the compensation module 130 is connected to the control end G1 of the driving module 120.
  • the light control module 140, the driving module 120 and the light emitting module 150 are connected in series between the first power line VDD and the second power line VSS.
  • the reset module 160 is electrically connected to the first end or the second end of the driving module 120, so as to achieve the reset of the potential of the first end and the second end of the driving module 120 in the reset stage.
  • the reset voltage VEH can be set according to the actual screen adjustment effect. For example, during the actual screen adjustment, the size of the reset voltage VEH can be adjusted, and the reset voltage corresponding to the optimal actual screen adjustment effect is set to the final fixed reset voltage of the display panel after leaving the factory, that is, the reset voltage VEH in the pixel circuit of this embodiment.
  • FIG 1 schematically shows the situation that the reset module 160 is electrically connected to the second end of the driving module 120.
  • the working process of the pixel circuit in writing a frame is as follows:
  • the data writing module 110 and the compensation module 130 are turned on, and the light emitting control module 140 and the reset module 160 are turned off.
  • the data writing module 110 writes the data voltage to the control terminal G1 of the driving module 120, and the compensation module 130 compensates for the threshold voltage of the driving module 120, wherein the driving module 120 includes a driving transistor DT, and the threshold voltage of the driving module 120 is the threshold voltage of the driving transistor DT.
  • the reset module 160 In the reset stage, the reset module 160 is turned on, and the reset module 160 writes the reset voltage VEH to the second end of the driving module 120, and writes the reset voltage VEH to the first end of the driving module 120 through the driving module 120.
  • the data writing module 110, the compensation module 130, and the light control module 140 are turned off.
  • the reset module 160 is connected to the first end of the driving module 120, and in the reset stage, the reset module 160 is turned on, and the reset voltage VEH is written to the first end of the driving module 120, and is written to the second end of the driving module 120 through the driving module 120.
  • the light-emitting control module 140 is turned on, and the driving module 120 generates a driving current according to the voltage of its control terminal G1 and the first terminal to drive the light-emitting module 150 to emit light.
  • the data writing module 110, the compensation module 130 and the reset module 160 are turned off.
  • the reset module 160 In the reset phase, the reset module 160 is turned on, and the reset module 160 writes the reset voltage VEH to the second end of the driving module 120, and writes the reset voltage VEH to the first end of the driving module 120 through the driving module 120.
  • the data writing module 110, the compensation module 130 and the light control module 140 are turned off.
  • the light-emitting control module 140 is turned on, and the driving module 120 generates a driving current according to the voltage of its own control terminal G1 and the first terminal to drive the light-emitting module 150 to emit light.
  • the module 130 and the reset module 160 are turned off.
  • the pixel circuit of the present embodiment includes a reset module by setting the pixel circuit, the reset module is electrically connected to the first end or the second end of the driving module, the reset module resets the potential of the first end and the second end of the driving module between the data writing stage and the light-emitting stage of the writing frame, and resets the potential of the first end and the second end of the driving module before the light-emitting stage of the holding frame, thereby making the potential of the first end of the driving module before the light-emitting stage of the writing frame and the holding frame the same, and the potential of the second end of the driving module before the light-emitting stage of the writing frame and the holding frame is also the same, thereby making the bias state of the driving module before the light-emitting stage of the writing frame and the holding frame the same, thereby facilitating the improvement of the transient characteristics of the driving module, so that the brightness of the light-emitting module will not change suddenly when the refresh frequency is switched, and the brightness of the light-emitting module will not change suddenly
  • the first end of the reset module 160 is connected to the reset voltage VEH
  • the second end of the reset module 160 is electrically connected to the second end of the driving module 120
  • the reset module 160 is configured to write the reset voltage VEH to the first end and the second end of the driving module 120 during the reset phase under the control of the signal connected to its own control end.
  • a valid control signal is input to the control end of the reset module 160, so that the reset module 160 is turned on, and the reset voltage VEH is written to the second end of the driving module 120 through the reset module 160.
  • the magnitude of the reset voltage VEH can be set.
  • the driving transistor DT is a P-type transistor, and the reset voltage VEH is greater than the data voltage, so that the driving transistor DT can be turned on in the reset phase, ensuring that the reset voltage VEH can be written from the second end of the driving module 120 to the first end of the driving module 120.
  • the driving transistor DT is an N-type transistor, and the reset voltage VEH is less than the data voltage, so that the driving transistor DT can be turned on in the reset phase, ensuring that the reset voltage VEH can be written from the second end of the driving module 120 to the first end of the driving module 120.
  • the light-emitting control module 140 includes a first light-emitting control unit 141 and a second light-emitting control unit 142, the first light-emitting control unit 141 is connected in series between the first power line VDD and the first end of the driving module 120; the second light-emitting control unit 142 is connected in series between the second end of the driving module 120 and the first end of the light-emitting module 150, and the second end of the light-emitting module 150 is electrically connected to the second power line VSS.
  • the reset module 160 is a newly added module on the basis of the data writing module 110, the driving module 120, the compensation module 130, the light-emitting control module 140 and the light-emitting module 150 included in the pixel circuit; in other optional embodiments of the present application, the reset module 160 can be formed by using parts of the data writing module 110, the driving module 120, the compensation module 130, the light-emitting control module 140 and the light-emitting module 150 included in the pixel circuit.
  • FIG2 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application.
  • the light control module 140 includes a first light control unit 141 and a second light control unit 142.
  • the first light control unit 141 is connected in series between the first power line VDD and the first end of the driving module 120;
  • the second light control unit 142 is connected in series between the second end of the driving module 120 and the first end of the light emitting module 150, and the second end of the light emitting module 150 is electrically connected to the second power line VSS.
  • a first end of the data writing module 110 is electrically connected to the data line Data, and a second end of the data writing module 110 is electrically connected to a first end of the driving module 120;
  • the data line Data is configured to transmit a data voltage during a data writing phase of a writing frame, and to transmit a first power supply voltage during a reset phase of a holding frame;
  • the reset module 160 includes a first light-emitting control unit 141 and a data writing module 110; wherein the first light-emitting control unit 141 is configured to write the first power supply voltage to the first end and the second end of the driving module 120 during the reset phase of the writing frame; the data writing module 110 is configured to write the first power supply voltage to the first end and the second end of the driving module 120 during the reset phase of the holding frame, that is, during the reset phase of the holding frame, the voltage input to the input end of the data writing module 110 is the first power supply voltage.
  • the data writing phase and the light emitting phase are respectively the same as the operation of the pixel circuit shown in FIG1 in the writing frame.
  • the first light-emitting control unit 141 In the reset phase of the writing frame of the pixel circuit shown in FIG2 , the first light-emitting control unit 141 is turned on, the first light-emitting control unit 141 writes the first power supply voltage to the first end of the driving module 120, and writes the first power supply voltage to the second end of the driving module 120 through the driving module 120.
  • the data writing module 110, the compensation module 130 and the second light-emitting control unit 142 are turned off.
  • the data writing module 110 In the reset phase, the data writing module 110 is turned on, the data writing module 110 writes the first power supply voltage to the first end of the driving module 120, and writes the first power supply voltage to the second end of the driving module 120 through the driving module 120.
  • the compensation module 130, the first light emitting control unit 141, and the second light emitting control unit 142 are turned off.
  • the working process in the light-emitting stage is the same as the working process of the pixel circuit shown in FIG. 1 in the light-emitting stage of the holding frame, and will not be described in detail here.
  • the voltage connected to the input end of the data writing module 110 is not fixed.
  • the voltage input to the input end of the data writing module 110 is the data voltage.
  • the voltage input to the input end of the data writing module 110 is the first power supply voltage.
  • the reset module 160 is formed by the original structure in the pixel circuit, and there is no need to add additional circuit modules on the basis of the data writing module 110, the driving module 120, the compensation module 130, the light control module 140 and the light emitting module 150 in the pixel circuit. Therefore, on the basis of improving the display quality, the number of devices included in the pixel circuit is reduced, which is conducive to improving the pixel density.
  • the pixel circuit further includes an initialization module
  • Figure 3 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application
  • Figure 4 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application
  • Figure 3 is a pixel circuit structure in which an initialization module 170 is added on the basis of the pixel circuit shown in Figure 1
  • Figure 4 is a pixel circuit structure in which an initialization module 170 is added to the pixel circuit shown in Figure 2, referring to Figures 3 and 4,
  • the initialization module 170 is configured to write an initialization voltage to the first end of the light-emitting module 150 and the control end of the driving module 120 in the first initialization phase of writing a frame
  • the second light-emitting control unit 142 and the compensation module 130 are configured to The first initialization phase of the write frame is turned on to write the initialization voltage written to the first end of the light-emitting module 150 to the control
  • the initialization module 170 is further configured to write the initialization voltage to the first end of the light emitting module 150 in the first initialization phase of the holding frame; in the holding frame, the first initialization phase is before the reset phase.
  • the pixel circuit shown in FIG3 and FIG4 includes a first initialization stage in the working process of writing a frame and holding a frame.
  • the initialization module 170 is turned on, and then the initialization voltage is written into the first end of the light-emitting module 150 to initialize the light-emitting module 150; at the same time, the second light-emitting control unit 142 and the compensation module 130 are turned on, and the initialization voltage is written into the control end of the driving module 120 through the initialization module 170, the second light-emitting control unit 142 and the compensation module 130 to initialize the control end of the driving module 120.
  • the initialization module 170 is turned on, and the initialization voltage is written into the first end of the light-emitting module 150, thereby ensuring that the light-emitting module 150 will not emit light when black insertion is performed in the holding frame, which is beneficial to improving the display quality.
  • the first light-emitting control unit 141 and the second light-emitting control unit 142 can also be turned on during the first initialization stage of the frame, so that during the first initialization stage of the frame, a large current exists between the first power line and the initialization line Vref, which is beneficial to improving the afterimage and improving the display quality.
  • the control end of the initialization module 170 is connected to the first scan line S1, the first end of the initialization module 170 is connected to the initialization line Vref, and the second end of the initialization module 170 is connected to the first end of the light emitting module 150;
  • the control end of the data writing module 110 is connected to the second scan line S2, the first end of the data writing module 110 is connected to the data line Data, and the second end of the data writing module 110 is connected to the first end of the driving module 120.
  • the first end of the data writing module 110 serves as the input end of the data writing module 110 in the above embodiment.
  • the control end of the first light-emitting control unit 141 is connected to the first light-emitting control signal line EM1, the first end of the first light-emitting control unit 141 is connected to the first power line VDD, the second end of the first light-emitting control unit 141 is connected to the first end of the driving module 120; the control end of the second light-emitting control unit 142 is connected to the first end of the driving module 120; The second light emitting control signal line EM2, the first end of the second light emitting control unit 142 is connected to the second end of the driving module 120, the second end of the second light emitting control unit 142 is connected to the first end of the light emitting module 150; the second end of the light emitting module 150 is connected to the second power line VSS.
  • the compensation module 130 is connected between the second end of the driving module 120 and the control end of the driving module 120, the control end of the compensation module 130 is connected to the compensation control signal line Sn, the first end of the compensation module 130 is connected to the second end of the driving module 120, and the second end of the compensation module 130 is connected to the control end of the driving module 120.
  • the compensation module 130 is connected between the second end of the driving module 120 and the control end of the driving module 120, the control end of the compensation module 130 is connected to the first light-emitting control signal line EM1, the first end of the compensation module 130 is connected to the second end of the driving module 120, and the second end of the compensation module 130 is connected to the control end of the driving module 120.
  • Figure 3 may correspond to a structure in which each module in Figure 1 is refined into a circuit device
  • Figure 4 may correspond to a structure in which each module in Figure 2 is refined into a circuit device.
  • the driving module 120 includes a driving transistor DT
  • the data writing module 110 includes a first transistor T1
  • the compensation module 130 includes a second transistor T2
  • the first light-emitting control unit 141 includes a third transistor T3
  • the second light-emitting control unit 142 includes a fourth transistor T4
  • the initialization module 170 includes a sixth transistor T6
  • the light-emitting module 150 includes a light-emitting device D1, which may be an organic light-emitting device D1 or an inorganic light-emitting device D1.
  • control end of the reset module 160 is connected to the third scan line S3 , and the reset module 160 includes a fifth transistor T5 .
  • the second transistor T2 is an N-type transistor, and the other transistors are P-type transistors.
  • the channel type of the transistor included in the first light-emitting control unit is opposite to that of the transistor included in the compensation module.
  • the second transistor T2 is an oxide transistor, and the leakage current of the oxide transistor is small, so that the potential of the control end of the driving module 120 in the light-emitting stage can be better maintained, which is more conducive to improving display uniformity and display quality.
  • FIG5 is a driving timing diagram of a writing frame of a pixel circuit provided by an embodiment of the present application, and the driving timing diagram can be used to drive the pixel circuit shown in FIG3.
  • the pixel circuit works The operation process includes a first initialization phase t1, a data writing phase t2, a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the signals on the second scan line S2 and the third scan line S3 are at a high level
  • the compensation control signal on the compensation control signal line Sn is at a high level. Therefore, the sixth transistor T6 is turned on in response to the low-level first scan signal
  • the fourth transistor T4 is turned on in response to the low-level second light control signal
  • the second transistor T2 is turned on in response to the high-level compensation control signal.
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the second scanning signal on the second scanning line S2 is at a low level, and other control signals in the pixel circuit are at a high level.
  • the first transistor T1 is turned on in response to the low-level second scanning signal, and the second transistor T2 is turned on in response to the high-level compensation control signal.
  • the data voltage is written to the gate of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2, and the threshold voltage of the driving transistor DT is compensated at the same time.
  • the third scanning signal is at a low level
  • the compensation control signal is at a low level
  • other control signals in the pixel circuit are all at a high level.
  • the fifth transistor T5 is turned on in response to the low-level third scanning signal, and the reset voltage VEH is written to the drain of the driving transistor DT through the fifth transistor T5, and is written to the source of the driving transistor DT through the driving transistor DT.
  • the first light emitting control signal and the second light emitting control signal are at a low level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the driving transistor DT drives the light emitting device D1 to emit light.
  • FIG. 6 is a driving timing diagram of a holding frame of a pixel circuit provided in an embodiment of the present application.
  • the driving timing diagram can be used to drive the pixel circuit shown in FIG. 3 .
  • the operation process of the pixel circuit includes the first initialization
  • the present invention comprises a first stage t1, a second stage t3 and a second stage t4.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the signals on the second scan line S2 and the third scan line S3 are at a high level
  • the compensation control signal on the compensation control signal line Sn is at a low level.
  • the sixth transistor T6 is turned on in response to the low-level first scan signal, the fourth transistor T4 is turned on in response to the low-level second light control signal, and the initialization voltage on the initialization line Vref is written to the anode of the light emitting device D1 through the sixth transistor T6, thereby initializing the anode of the light emitting device D1.
  • the first light-emitting control signal on the first light-emitting control line is always at a low level, then in the first initialization stage t1, the third transistor T3 is turned on, and since the fourth transistor T4 is also turned on in the first initialization stage t1, there is a large current between the first power line VDD and the initialization line Vref, which is beneficial to improve the afterimage.
  • the third scanning signal is at a low level
  • the compensation control signal is at a low level
  • other control signals in the pixel circuit are all at a high level.
  • the fifth transistor T5 is turned on in response to the low-level third scanning signal, and the reset voltage VEH is written to the drain of the driving transistor DT through the fifth transistor T5, and is written to the source of the driving transistor DT through the driving transistor DT.
  • the first light emitting control signal and the second light emitting control signal are at a low level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the driving transistor DT drives the light emitting device D1 to emit light.
  • the first scan line S1 , the second scan line S2 , and the third scan line S3 are connected to the same scan driving circuit, which is beneficial to realizing a narrow frame of the display panel.
  • the reset module includes a first transistor T1 and a third transistor T3 .
  • Fig. 7 is a driving timing diagram of a write frame of another pixel circuit provided in an embodiment of the present application, and the driving timing diagram can be used to drive the pixel circuit shown in Fig. 4 .
  • the working process of the pixel circuit includes a first initialization phase t1 , a data writing phase t2 , a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the signal on the second scan line S2 is at a high level.
  • the sixth transistor T6 is turned on in response to the low-level first scan signal
  • the fourth transistor T4 is turned on in response to the low-level second light control signal
  • the second transistor T2 is turned on in response to the high-level first light control signal
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the second scanning signal on the second scanning line S2 is at a low level, and other control signals in the pixel circuit are at a high level.
  • the first transistor T1 is turned on in response to the low-level second scanning signal
  • the second transistor T2 is turned on in response to the high-level first light-emitting control signal.
  • the first light emitting control signal is at a low level
  • the third transistor T3 is turned on in response to the low level first light emitting control signal
  • the first power supply voltage is written to the source of the driving transistor DT through the third transistor T3 and to the drain of the driving transistor DT through the driving transistor DT.
  • the first light emitting control signal and the second light emitting control signal are at a low level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the driving transistor DT drives the light emitting device D1 to emit light.
  • FIG8 is a driving timing diagram of a holding frame of another pixel circuit provided in an embodiment of the present application.
  • the driving timing diagram can be used to drive the pixel circuit shown in FIG4 .
  • the working process of the pixel circuit includes a first initialization phase t1 , a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a low level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the signal on the second scan line S2 is at a high level. Therefore,
  • the sixth transistor T6 is turned on in response to the low-level first scanning signal
  • the fourth transistor T4 is turned on in response to the low-level second light-emitting control signal
  • the third transistor T3 is turned on in response to the low-level first light-emitting control signal.
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, thereby initializing the anode of the light-emitting device D1.
  • the first light-emitting control signal is at a low level
  • the third transistor T3 is turned on in response to the low-level first light-emitting control signal, and the first power supply voltage is written to the source of the driving transistor DT through the third transistor T3; at the same time, the second scanning signal is at a low level, and the voltage input by the data line Data is also the first power supply voltage, so the first power supply voltage is also written to the source of the driving transistor DT through the first transistor T1, and the first power supply voltage is written to the drain of the driving transistor DT through the driving transistor DT. That is, the first light-emitting control unit 141 (the third transistor T3) is also configured to write the first power supply voltage to the first terminal and the second terminal of the driving module 120 in the reset phase of the writing frame.
  • the first light emitting control signal and the second light emitting control signal are at a low level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the driving transistor DT drives the light emitting device D1 to emit light.
  • the first scan line S1 and the second scan line S2 are connected to the same scan driving circuit, which is beneficial to realizing a narrow frame of the display panel.
  • FIG9 is a schematic diagram of another pixel circuit structure provided by an embodiment of the present application, and FIG9 can correspond to each module in FIG1 and be refined into another structure of a circuit device.
  • the difference between FIG9 and FIG3 is that the control end of the initialization module 170 is connected to the first light-emitting control line EM1, the control end of the data writing module 110 is connected to the first scan line S1, and the control end of the reset module 160 is connected to the second scan line S2.
  • the control end of the first light-emitting control unit 141 is connected to the first light-emitting control line EM1, and the control end of the second light-emitting control unit 142 is connected to the second light-emitting control line EM2;
  • the compensation module 130 is connected between the second end of the driving module 120 and the control end of the driving module 120, and the control end of the compensation module 130 is connected to the compensation control signal line Sn;
  • the control end of the initialization module 170 is connected to the first light-emitting control line EM1.
  • the transistor included in the initialization module 170 and the transistor included in the first light emitting control unit 141 The channel types of the transistors are opposite.
  • the transistors included in the initialization module 170 are oxide transistors.
  • the second transistor T2 and the sixth transistor T6 are N-type transistors, and the other transistors are P-type transistors.
  • Fig. 10 is a driving timing of a write frame of another pixel circuit provided by an embodiment of the present application, and the driving timing can be used to drive the pixel circuit shown in Fig. 9.
  • the working process of the pixel circuit includes a first initialization phase t1, a data writing phase t2, a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a high level
  • the second scan signal on the second scan line S2 is at a high level
  • the compensation control signal on the compensation control signal line Sn is at a high level.
  • the sixth transistor T6 is turned on in response to the high-level first light control signal
  • the fourth transistor T4 is turned on in response to the low-level second light control signal
  • the second transistor T2 is turned on in response to the high-level compensation control signal
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the second scanning signal on the first scanning line S1 is at a low level, and other control signals in the pixel circuit are at a high level.
  • the first transistor T1 is turned on in response to the low-level first scanning signal, and the second transistor T2 is turned on in response to the high-level compensation control signal.
  • the data voltage is written to the gate of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2, and the threshold voltage of the driving transistor DT is compensated at the same time.
  • the second scanning signal is at a low level
  • the compensation control signal is at a low level
  • other control signals in the pixel circuit are all at a high level.
  • the fifth transistor T5 is turned on in response to the low-level second scanning signal, and the reset voltage VEH is written to the drain of the driving transistor DT through the fifth transistor T5, and is written to the source of the driving transistor DT through the driving transistor DT.
  • the first light-emitting control signal and the second light-emitting control signal are at a low level, and the third crystal
  • the body transistor T3 and the fourth transistor T4 are turned on, and the driving transistor DT drives the light emitting device D1 to emit light.
  • the driving timing of the pixel circuit shown in FIG9 in the holding frame is different from the driving timing of the writing frame shown in FIG10 only in that, in the holding frame, the compensation control signal is always at a low level, and other control signals are the same as those in the writing frame.
  • the working process of the pixel circuit shown in FIG9 in the holding frame includes a first initialization stage, a reset stage, and a light-emitting stage which are performed successively.
  • the first light control signal in the first initialization stage, is at a high level, and the initialization voltage on the initialization line is written to the anode of the light-emitting device through the sixth transistor to initialize the anode of the light-emitting device.
  • the first light control signal on the first light control line in the holding frame, is always at a low level.
  • the third transistor is turned on, and there is a large current between the first power line and the initialization line, which is conducive to improving the afterimage.
  • the reset phase and the light-emitting phase of the hold frame have the same working processes as the reset phase and the light-emitting phase of the write frame, and will not be described in detail here.
  • the first scan line S1 and the second scan line S2 are connected to the same scan driving circuit, which is beneficial to the realization of a narrow frame of the display panel.
  • FIG11 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application.
  • FIG11 may correspond to another structure in which each module in FIG3 is refined into a circuit device.
  • the control end of the compensation module 130 is connected to the compensation control signal line Sn.
  • the difference between FIG11 and the pixel circuit shown in FIG3 is that the control end of the first light-emitting control unit 141 and the control end of the second light-emitting control unit 142 are electrically connected to the same light-emitting control line EM.
  • Fig. 12 is a driving timing diagram of a write frame of another pixel circuit provided by an embodiment of the present application, and the driving timing can be used to drive the pixel circuit shown in Fig. 11.
  • the working process of the pixel circuit includes a first initialization phase t1, a data writing phase t2, a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the light control signal on the light control signal line EM is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the second scan line S2 and the third scan line S3 are at a low level.
  • the signal is high level
  • the compensation control signal on the compensation control signal line Sn is high level.
  • the sixth transistor T6 is turned on in response to the low level first scanning signal
  • the fourth transistor T4 is turned on in response to the low level light-emitting control signal
  • the second transistor T2 is turned on in response to the high level compensation control signal
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the third transistor T3 is turned on in response to the low level light-emitting control signal, and there is a large current between the first power line VDD and the initialization line Vref, which is conducive to improving the residual image.
  • the second scanning signal on the second scanning line S2 is at a low level, and other control signals in the pixel circuit are at a high level.
  • the first transistor T1 is turned on in response to the low-level second scanning signal, and the second transistor T2 is turned on in response to the high-level compensation control signal.
  • the data voltage is written to the gate of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2, and the threshold voltage of the driving transistor DT is compensated at the same time.
  • the third scanning signal is at a low level
  • the compensation control signal is at a low level
  • other control signals in the pixel circuit are all at a high level.
  • the fifth transistor T5 is turned on in response to the low-level third scanning signal, and the reset voltage VEH is written to the drain of the driving transistor DT through the fifth transistor T5, and is written to the source of the driving transistor DT through the driving transistor DT.
  • the light emitting control signal is at a low level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the driving transistor DT drives the light emitting device D1 to emit light.
  • the driving timing of the pixel circuit shown in FIG11 in the holding frame is different from the driving timing of the writing frame shown in FIG12 only in that, in the holding frame, the compensation control signal is always at a low level, and other control signals are the same as those in the writing frame.
  • the working process of the pixel circuit shown in FIG11 in the holding frame includes a first initialization stage, a reset stage, and a light-emitting stage which are performed successively.
  • the first scanning signal is at a low level, and the initialization voltage on the initialization line is written to the anode of the light-emitting device through the sixth transistor to initialize the anode of the light-emitting device. The same, no longer repeated here.
  • the writing frame is set to also include a second initialization stage t11
  • the initialization module 170 is also set to write the initialization voltage to the first end of the light-emitting module 150 and the control end of the driving module 120 in the second initialization stage t11 of the writing frame
  • the second light-emitting control unit 142 and the compensation module 130 are also set to be turned on in the second initialization stage t11 of the writing frame to write the initialization voltage written to the first end of the light-emitting module 150 to the control end of the driving module through the second light-emitting control unit 142 and the compensation module 130; wherein the second initialization stage t11 is performed before the first initialization stage t1.
  • the initialization voltage is written to the first end of the light-emitting module 150, and the initialization voltage is written to the control end of the driving module 120 through the initialization module 170, the second light-emitting control unit 142 and the compensation module 130.
  • the writing of the initialization voltage to the control end of the driving module 120 includes two stages, the second initialization stage t11 and the first initialization stage t1.
  • the time for writing the initialization voltage to the control end of the driving module 120 is extended, which is beneficial for fully writing the initialization voltage to the control end of the driving module 120 before the data writing stage t2 of the writing frame, thereby reducing the difference when writing data in the data writing stage t2, improving the display uniformity of the display device, and reducing the afterimage phenomenon.
  • the write frame also includes a pre-charge stage t21
  • the data write module 110 is also configured to write a pre-charge voltage to the control end of the drive module 120 during the pre-charge stage t21 of the write frame; wherein, in the write frame, the pre-charge stage t21 is between the second initialization stage t11 and the first initialization stage t1, and the data write stage t2 is after the first initialization stage t1.
  • a pre-charge voltage is written to the control end of the driving module 120 in the pre-charge stage t21 between the second initialization stage t11 and the first initialization stage t1
  • a pre-charge voltage is written to the control end of the driving module 120. Since a data line Data in the display panel is connected to a column of pixel circuits, the data voltage difference between two rows that are close to each other in a column of pixel circuits is small during display. Therefore, the pre-charge voltage is set to the data voltage corresponding to the upper n rows of pixel circuits in the same column of the pixel circuits.
  • n ⁇ 2 (wherein the second initialization stage of the pixel circuits in this row corresponds to the data writing stage of the pixel circuits in the previous row, so the pre-charge voltage cannot be the data voltage corresponding to the upper 1 row of pixel circuits in the same column of the pixel circuits), so that in the pre-charge stage t21, the difference in pre-charge voltages written to the control end of the driving module 120 of each row of pixel circuits in the same column of pixel circuits is small, and thus in the first initialization stage t1, the control ends of the driving modules 120 of the pixel circuits in the same column all have similar voltages to start initialization and write the initialization voltage, and then after the first initialization stage t1, the voltage difference of the control end of the driving module 120 is also small, and thus the difference in data written in the data writing stage t2 is also small, thereby improving display uniformity.
  • the data voltages corresponding to the pixel circuits in the same column are the same. Therefore, no matter what display screen the previous frame is, after the pre-charging stage t21, the control end of the driving module 120 is the same voltage. Then, during the first initialization stage t1, the control end of the driving module 120 of each pixel circuit in a column of pixel circuits is initialized from the same voltage to the initialization voltage, thereby further reducing the difference in data written during the data writing stage t2 and improving display uniformity.
  • the initialization module 170 is further configured to be turned on in the second initialization phase t11 of the holding frame, wherein in the holding frame, the second initialization phase t11 is before the first initialization phase t1.
  • the light emitting device D1 By setting the initialization module 170 to be turned on in the second initialization phase t11 of the holding frame, the light emitting device D1 will not be lit when black insertion is performed in the holding frame, thereby ensuring display quality.
  • FIG13 is a driving timing diagram of a write frame of another pixel circuit provided in an embodiment of the present application, and the driving timing can also be used to drive the pixel circuit shown in FIG3.
  • the working process of the pixel circuit includes a second initialization phase t11, a pre-charge phase t21, a first initialization phase t1, a data write phase t2, and a light emitting phase t4, which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the signals on the second scan line S2 and the third scan line S3 are at a high level
  • the compensation control signal on the compensation control signal line Sn is at a high level.
  • the sixth transistor T6 is turned on in response to the low-level first scan signal, the fourth transistor T4 is turned on in response to the low-level second light control signal, and the second transistor T2 is turned on in response to the high-level compensation control signal, and the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the second scan signal on the second scan line S2 is at a low level, other control signals in the pixel circuit are at a high level, the first transistor T1 is turned on in response to the low-level second scan signal, and the second transistor T2 is turned on in response to the high-level compensation control signal, and the pre-charge voltage is written to the gate of the driving transistor DT through the first transistor T1, the driving transistor DT, and the second transistor T2.
  • the pre-charge voltage is the data voltage corresponding to the upper n rows of pixel circuits in the same column of the pixel circuit, n ⁇ 2, so that the difference in the data written in the subsequent data writing stage t2 will also be smaller, thereby improving the display uniformity and reducing the afterimage phenomenon.
  • the working state of each transistor in the pixel circuit is the same as the working state of each transistor corresponding to the first initialization stage t1 of the driving timing shown in FIG5, except that when driving with the driving timing shown in FIG5, in the first initialization stage t1, the gate of the driving transistor DT needs to be written as the initialization voltage by the voltage of the previous frame, and when driving with the driving timing shown in FIG13, the gate of the driving transistor DT is written as the initialization voltage by the pre-charge voltage, so that in the first initialization stage t1, the driving transistor DT
  • the gates of the transistors can be initialized to similar or identical voltages, so that the difference in data written in the subsequent data writing phase t2 will be smaller, thereby improving display uniformity.
  • the working states of each transistor in the pixel circuit are respectively the same as the working states of each transistor in the data writing stage t2, the reset stage t3 and the light emitting stage t4 corresponding to the driving timing shown in FIG5 , and are not repeated here.
  • FIG. 14 is a driving timing diagram of a holding frame of a pixel circuit provided in an embodiment of the present application.
  • the driving timing diagram can be used to drive the pixel circuit shown in FIG. 3 .
  • the operation process of the pixel circuit includes a second initialization phase t11 , a first initialization phase t1 , a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the signals on the second scan line S2 and the third scan line S3 are at a high level
  • the compensation control signal on the compensation control signal line Sn is at a low level.
  • the sixth transistor T6 is turned on in response to the low-level first scan signal, the fourth transistor T4 is turned on in response to the low-level second light control signal, and the initialization voltage on the initialization line Vref is written to the anode of the light emitting device D1 through the sixth transistor T6, thereby initializing the anode of the light emitting device D1.
  • the working process in the first initialization stage t1 is the same as the working process in the second initialization stage t11 , and will not be described in detail here.
  • the waveforms of the first light-emitting control signal and the second light-emitting control signal are the same, when Figures 13 and 14 are used to drive the pixel circuit shown in Figure 3, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 can be connected to the same light-emitting driving circuit, which is conducive to the realization of a narrow frame.
  • the first light control signal on the first light control line is always at a low level. Then, in the second initialization stage t11 and the first initialization stage t1, the third transistor T3 is turned on, and a large current exists between the first power line VDD and the initialization line Vref, which is beneficial to improve the afterimage.
  • the third scanning signal is at a low level
  • the compensation control signal is at a low level
  • other control signals in the pixel circuit are all at a high level.
  • the fifth transistor T5 is turned on in response to the low-level third scanning signal, and the reset voltage VEH is written to the drain of the driving transistor DT through the fifth transistor T5, and is written to the source of the driving transistor DT through the driving transistor DT.
  • the first light emitting control signal and the second light emitting control signal are at a low level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the driving transistor DT drives the light emitting device D1 to emit light.
  • the second scan line S2 may not include a low-level pulse signal, that is, the signals on the second scan line S2 in the holding frame are all high-level.
  • FIG15 is a driving timing diagram of a write frame of another pixel circuit provided in an embodiment of the present application, and the driving timing can also be used to drive the pixel circuit shown in FIG4.
  • the working process of the pixel circuit includes a second initialization phase t11, a pre-charge phase t21, a first initialization phase t1, a data write phase t2, a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the second scan signal on the second scan line S2 is at a high level.
  • the sixth transistor T6 is turned on in response to the low-level first scan signal
  • the fourth transistor T4 is turned on in response to the low-level second light control signal
  • the second transistor T2 is turned on in response to the high-level first light control signal
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the second scan signal on the second scan line S2 is at a low level, and other control signals in the pixel circuit are at a high level.
  • the first transistor T1 is turned on in response to the low-level second scan signal, and the second transistor T2 is turned on in response to the high-level first light-emitting control signal.
  • the pre-charge voltage is written to the gate of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2.
  • the working states of each transistor in the pixel circuit are respectively the same as the working states of each transistor in the first initialization stage t1, the data writing stage t2, the reset stage t3, and the light-emitting stage t4 corresponding to the driving timing shown in FIG. 7, and are not repeated here.
  • the pre-charge voltage is the data voltage corresponding to the upper n rows of pixel circuits in the same column of the pixel circuits, n ⁇ 2, so that in the first initialization stage t1, the gate of the driving transistor DT is written from the pre-charge voltage to the initialization voltage, so that in the first initialization stage t1, the gate of the driving transistor DT can be initialized to a similar or identical voltage, and the difference in data written in the subsequent data writing stage t2 will also be smaller, thereby improving display uniformity and reducing the afterimage phenomenon.
  • FIG. 16 is a driving timing diagram of a holding frame of another pixel circuit provided in an embodiment of the present application.
  • the driving timing diagram can be used to drive the pixel circuit shown in FIG. 4 .
  • the working process of the pixel circuit includes a second initialization phase t11 , a first initialization phase t1 , a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a low level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the second scan signal on the second scan line S2 is at a high level. Therefore, the sixth transistor T6 is turned on in response to the low-level first scan signal, the fourth transistor T4 is turned on in response to the low-level second light control signal, and the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the third transistor T3 is turned on in response to the low-level first light control signal, and a large current exists between the first power line VDD and the initialization line Vref, which is conducive to improving the residual image.
  • the working process in the first initialization stage t1 is the same as the working process in the second initialization stage t11 , and will not be described in detail here.
  • the states of the transistors in the pixel circuit are respectively the same as the working processes of the reset stage t3 and the light emitting stage t4 in the driving timing of FIG8, and will not be repeated here.
  • FIG17 is a driving timing diagram of a write frame of another pixel circuit provided in an embodiment of the present application, and the driving timing can also be used to drive the pixel circuit shown in FIG9.
  • the working process of the pixel circuit includes a second initialization phase t11, a pre-charge phase t21, a first initialization phase t1, a data write phase t2, a reset phase t3 and a light emitting phase t4 which are performed successively.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a high level
  • the second scan signal on the second scan line S2 is at a high level
  • the compensation control signal on the compensation control signal line Sn is at a high level.
  • the sixth transistor T6 is turned on in response to the high-level first light control signal
  • the fourth transistor T4 is turned on in response to the low-level second light control signal
  • the second transistor T2 is turned on in response to the high-level compensation control signal
  • the initialization voltage on the initialization line Vref is written to the anode of the light emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the first scan signal on the first scan line S1 is at a low level, and other control signals in the pixel circuit are at a high level.
  • the first transistor T1 is turned on in response to the low-level first scan signal, and the second transistor T2 is turned on in response to the high-level compensation control signal.
  • the pre-charge voltage is written to the gate of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2.
  • the working states of each transistor in the pixel circuit are respectively the same as the working states of each transistor in the first initialization stage t1, the data writing stage t2, the reset stage t3, and the light-emitting stage t4 corresponding to the driving timing shown in FIG. 10, and are not repeated here.
  • the pixel circuit of this embodiment can improve display uniformity and reduce the afterimage phenomenon based on the same reasons as the driving timings of FIG. 13 and FIG. 15 , which will not be described in detail here.
  • the driving timing of the pixel circuit shown in FIG9 in the hold frame is different from the driving timing of the write frame shown in FIG17 in that in the hold frame, the compensation control signal is always at a low level, and the other control signals are at the same level as in the write frame.
  • the working process of the pixel circuit shown in FIG9 in the holding frame includes a second initialization phase, a first initialization phase, a reset phase and a light emitting phase which are performed successively.
  • the first light control signal on the first light control signal line is at a high level
  • the second light control signal on the second light control signal line is at a low level
  • the first scan signal on the first scan line is at a high level
  • the second scan signal on the second scan line is at a high level
  • the compensation control signal on the compensation control signal line is at a low level. Therefore, the sixth transistor is turned on in response to the high-level first light control signal, the fourth transistor is turned on in response to the low-level second light control signal, and the initialization voltage on the initialization line is written to the anode of the light-emitting device through the sixth transistor, thereby initializing the anode of the light-emitting device.
  • Fig. 18 is a driving timing diagram of a write frame of another pixel circuit provided in an embodiment of the present application, and the driving timing can be used to drive the pixel circuit shown in Fig. 11.
  • the working process of the pixel circuit includes a second initialization phase t11, a pre-charge phase t21, a first initialization phase t1, a data write phase t2, a reset phase t3 and a light emitting phase t4 which are successively performed.
  • the light-emitting control signal on the light-emitting control signal line is at a low level
  • the first scanning signal on the first scanning line S1 is at a low level
  • the signals on the second scanning line S2 and the third scanning line S3 are at a high level
  • the compensation control signal on the compensation control signal line Sn is at a high level.
  • the sixth transistor T6 is turned on in response to the low-level first scanning signal
  • the fourth transistor T4 is turned on in response to the low-level light-emitting control signal
  • the second transistor T2 is turned on in response to the high-level compensation control signal
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the third transistor T3 is turned on in response to the low-level light-emitting control signal, and a large current exists between the first power line VDD and the initialization line Vref, which is conducive to improving the residual image.
  • the second scan signal on the second scan line S2 is at a low level, and other control signals
  • the signals are both high level
  • the first transistor T1 is turned on in response to the low level second scanning signal
  • the second transistor T2 is turned on in response to the high level compensation control signal
  • the pre-charge voltage is written to the gate of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2.
  • the working states of each transistor in the pixel circuit are respectively the same as the working states of each transistor in the first initialization stage t1, the data writing stage t2, the reset stage t3, and the light-emitting stage t4 corresponding to the driving timing shown in FIG. 12, and are not repeated here.
  • the pixel circuit of this embodiment can improve display uniformity and reduce the afterimage phenomenon based on the same reasons as the driving timings of Figures 13, 15 and 17, which will not be repeated here.
  • the driving timing of the pixel circuit shown in FIG11 in the holding frame is different from the driving timing of the writing frame shown in FIG18 only in that, in the holding frame, the compensation control signal is always at a low level, and other control signals are the same as those in the writing frame.
  • the working process of the pixel circuit shown in FIG11 in the holding frame includes a second initialization stage, a first initialization stage, a reset stage, and a light-emitting stage, which are performed successively.
  • the light control signal on the light control signal line is at a low level
  • the first scanning signal on the first scanning line is at a low level
  • the signals on the second scanning line and the third scanning line are at a high level
  • the compensation control signal on the compensation control signal line is at a low level. Therefore, the sixth transistor is turned on in response to the low-level first scanning signal, the fourth transistor is turned on in response to the low-level light control signal, and the initialization voltage on the initialization line is written to the anode of the light-emitting device through the sixth transistor, thereby initializing the anode of the light-emitting device.
  • the third transistor is turned on in response to the low-level light control signal, and a large current exists between the first power line and the initialization line, which is conducive to improving the residual image.
  • the working processes in the first initialization phase, the reset phase and the light-emitting phase of the frame holding period are respectively the same as the first initialization phase, the reset phase and the light-emitting phase of the write frame drive timing shown in FIG. 18 , and will not be repeated here.
  • FIG19 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application.
  • FIG19 may correspond to another structure of circuit devices in which each module in FIG1 is refined.
  • the compensation module 130 (the second transistor T2) is connected to the first light-emitting control signal line EM1, and the other structures and connection relationships in the pixel circuit are the same as those in FIG. 3 , which will not be described in detail here.
  • the only difference between FIG. 19 and FIG. 11 is that in FIG.
  • the first light-emitting control unit 141 is connected to the first light-emitting control line
  • the second light-emitting control unit 142 is connected to the second light-emitting control line
  • the other structures and connection relationships are the same as those in FIG. 11 .
  • FIG20 is a driving timing diagram of a write frame of another pixel circuit provided in an embodiment of the present application, and the driving timing can be used to drive the pixel circuit shown in FIG19.
  • the working process of the pixel circuit includes a second initialization phase t11, a pre-charge phase t21, a first initialization phase t1, a data write phase t2, a reset phase t3 and a light emitting phase t4 which are successively performed.
  • the first light control signal on the first light control signal line EM1 is at a high level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the signals on the second scan line S2 and the third scan line S3 are at a high level.
  • the sixth transistor T6 is turned on in response to the low-level first scan signal
  • the fourth transistor T4 is turned on in response to the low-level second light control signal
  • the second transistor T2 is turned on in response to the high-level first light control signal
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the initialization voltage is also written to the gate of the driving transistor DT through the sixth transistor T6, the fourth transistor T4 and the second transistor T2, so as to initialize the gate of the driving transistor DT.
  • the second scan signal on the second scan line S2 is at a low level, and other control signals are all at high levels.
  • the first transistor T1 is turned on in response to the low-level second scan signal, and the second transistor T2 is turned on in response to the high-level first light-emitting control signal.
  • the pre-charge voltage is written to the gate of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2.
  • the working state of each transistor in the pixel circuit is the same as that in the second initialization stage t11, which will not be described in detail here.
  • the second scanning signal on the second scanning line S2 is at a low level, and other control signals in the pixel circuit are at a high level.
  • the first transistor T1 is turned on in response to the low-level second scanning signal, and the second transistor T2 is turned on in response to the high-level first light-emitting control signal.
  • the data voltage is passed through the first transistor T1 , the driving transistor DT and the second transistor T2 write to the gate of the driving transistor DT, and at the same time realize compensation for the threshold voltage of the driving transistor DT.
  • the third scanning signal is at a low level
  • the first light-emitting control signal is at a low level
  • other control signals in the pixel circuit are all at a high level.
  • the fifth transistor T5 is turned on in response to the low-level third scanning signal, and the reset voltage VEH is written to the drain of the driving transistor DT through the fifth transistor T5, and is written to the source of the driving transistor DT through the driving transistor DT.
  • the first light emitting control signal and the second light emitting control signal are at a low level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the driving transistor DT drives the light emitting device D1 to emit light.
  • the pixel circuit of this embodiment can improve display uniformity and reduce the afterimage phenomenon based on the same reasons as the driving timings of Figures 13, 15, 17 and 18, which will not be repeated here.
  • the driving timing of the pixel circuit shown in FIG19 in the holding frame is different from the driving timing of the writing frame shown in FIG20 only in that, in the holding frame, the first light-emitting control signal is always at a low level, and other control signals are the same as those in the writing frame.
  • the working process of the pixel circuit shown in FIG9 in the holding frame includes a second initialization stage t11, a first initialization stage t1, a reset stage t3, and a light-emitting stage t4, which are successively performed.
  • the first light control signal on the first light control signal line EM1 is at a low level
  • the second light control signal on the second light control signal line EM2 is at a low level
  • the first scan signal on the first scan line S1 is at a low level
  • the signals on the second scan line S2 and the third scan line S3 are at a high level. Therefore, the sixth transistor T6 is turned on in response to the low-level first scan signal, the fourth transistor T4 is turned on in response to the low-level second light control signal
  • the initialization voltage on the initialization line Vref is written to the anode of the light-emitting device D1 through the sixth transistor T6, so as to initialize the anode of the light-emitting device D1.
  • the third transistor T3 is turned on in response to the low-level first light control signal, and a large current exists between the first power line VDD and the initialization line Vref, which is conducive to improving the residual image.
  • the working processes in the first initialization stage t1, the reset stage t3 and the light-emitting stage t4 of the frame holding period are respectively the same as the first initialization stage t1, the reset stage t3 and the light-emitting stage t4 of the write frame drive timing shown in Figure 20, and will not be repeated here.
  • each control signal (including the control terminal of the data writing module)
  • the signal inputted by the control end of the compensation module, the signal inputted by the control end of the initialization module, the signal inputted by the control end of the reset module, the signal inputted by the control end of the first light-emitting control unit, and the signal inputted by the control end of the second light-emitting control unit) can be provided by different gate drive circuits.
  • the duration of the reset phase can be adjusted, that is, the effective pulse width of the signal inputted by the control end of the reset module is adjustable.
  • the duration of the reset phase of the holding frame is greater than the duration of the reset phase of the writing frame.
  • the gate of the driving transistor is initialized in the first initialization phase and the second initialization phase of the writing frame, and the gate of the driving transistor is not initialized in the first initialization phase and the second initialization phase of the holding frame.
  • the writing frame includes a data writing phase, and the driving transistor is turned on in the data writing phase; while the holding frame does not include a data writing phase. Therefore, there are differences in the characteristics of the driving transistor in the writing frame and the holding frame.
  • the duration of the holding frame reset phase to be greater than the duration of the writing frame reset phase, the difference in the characteristics of the driving transistor in the writing frame and the holding frame can be reduced, which is conducive to improving the display quality.
  • the pixel circuit further includes a first storage module 180, a first end of the first storage module 180 is connected to the first power line VDD, and a second end of the first storage module 180 is connected to the control end of the driving module 120.
  • the first storage module 180 is configured to store and maintain the potential of the control end of the driving module 120.
  • the pixel circuit also includes a second storage module 190, a first end of the second storage module 190 is connected to the first power line VDD, and a second end of the second storage module 190 is connected to the first end of the driving module 120.
  • the write frame also includes a subthreshold compensation stage t5, and the compensation module 130 is also configured to be turned on during the subthreshold compensation stage t5, wherein the subthreshold compensation stage t5 is between the data writing stage t2 and the reset stage t3 of the write frame.
  • the first storage module 180 includes a first capacitor
  • the second storage module 190 includes a second capacitor
  • the compensation control signal is at a high level, and other control signals are also at a high level.
  • the second transistor T2 included in the compensation module 130 responds to the high level.
  • the compensation control signal is turned on, and the current generated by the driving transistor DT continues to charge the gate of the driving transistor DT through the second transistor T2.
  • the first light-emitting control signal is at a high level, and other control signals are also at a high level.
  • the second transistor T2 included in the compensation module 130 is turned on in response to the high-level first light-emitting control signal, and the current generated by the driving transistor DT continues to charge the gate of the driving transistor DT through the second transistor T2.
  • the compensation control signal is at a high level, and other control signals are also at a high level.
  • the second transistor T2 included in the compensation module 130 is turned on in response to the high-level compensation control signal, and the current of the driving transistor DT continues to charge the gate of the driving transistor DT through the second transistor T2.
  • the compensation control signal is at a high level, and other control signals are also at a high level.
  • the second transistor T2 included in the compensation module 130 is turned on in response to the high-level compensation control signal, and the current of the driving transistor DT continues to charge the gate of the driving transistor DT through the second transistor T2.
  • the first light-emitting control signal is at a high level, and other control signals are also at a high level.
  • the second transistor T2 included in the compensation module 130 is turned on in response to the high-level first light-emitting control signal, and the current of the driving transistor DT continues to charge the gate of the driving transistor DT through the second transistor T2.
  • Subthreshold swing also known as S factor
  • S factor is numerically equal to the gate voltage increment required to change the driving current between the source and drain of the driving transistor DT by one order of magnitude.
  • the size of the subthreshold swing affects the size of the driving current generated by the driving transistor DT.
  • the driving currents generated by the driving transistor DT are different.
  • the larger the subthreshold swing the larger the driving current generated by the driving transistor DT under the set gray scale.
  • the set gray scale can correspond to the gray scale range when the driving current generated by the driving transistor DT is less than the set current threshold.
  • the pixel circuit of this embodiment by setting the pixel circuit to also include a second The storage module 190, the second storage module 190 maintains the potential of the first end of the driving module 120 (the first electrode of the driving transistor DT) in the subthreshold swing compensation stage. Since the subthreshold swing compensation stage is after the data writing stage t2, and the data writing module 110 is electrically connected to the first electrode of the driving transistor DT, the second storage module 190 maintains the data voltage of the first electrode of the driving transistor DT in the subthreshold swing compensation stage.
  • the compensation module 130 is turned on in the subthreshold swing compensation stage, so that the current generated by the driving transistor DT continues to charge the gate of the driving transistor DT.
  • the gate potential change of the driving transistor DT is recorded as ⁇ V. Since the gate potential of the driving transistor DT is Vdata+Vth after the data writing stage t2 is completed, the gate potential of the driving transistor DT is Vdata+Vth+ ⁇ V after the subthreshold swing compensation stage. Because the subthreshold swing of the driving transistor DT is larger under the set gray scale, the current of the driving transistor DT itself is larger, and the gate potential change ⁇ V of the driving transistor DT in the subthreshold swing compensation stage is larger. According to the driving current calculation formula of the driving transistor DT:
  • ⁇ represents carrier mobility
  • Cox represents gate oxide capacitance (capacitance per unit area of gate oxide)
  • W/L represents the width-to-length ratio of the driving transistor DT
  • Vgs represents the voltage difference between the gate and the first electrode of the driving transistor DT
  • Vth represents the threshold voltage of the driving transistor DT
  • Vdata represents the data voltage
  • Vdd represents the first power supply voltage input to the first power supply voltage input terminal.
  • the driving transistor DT as a P-type transistor as an example, the data voltage and the first power supply voltage on the first power line VDD are both positive voltages, and the data voltage is less than the first power supply voltage, so Vdata-Vdd ⁇ 0. Since the data voltage is a positive voltage, the gate voltage of the driving transistor DT gradually increases in the subthreshold swing stage, that is, ⁇ V>0. According to the above driving current calculation formula, when the data voltage remains unchanged, the greater the gate potential change ⁇ V, the smaller the absolute value of
  • the driving transistor DT current generated by the driving transistor DT with a larger subthreshold swing is reduced more, Therefore, under the same data voltage when setting the gray scale, the driving currents of the driving transistors DT with different subthreshold swings tend to be consistent, reducing the display unevenness caused by the different subthreshold swings of the driving transistors DT in the display panel under the set gray scale.
  • the driving transistor DT is an N-type transistor, the working principle is similar to that of the P-type driving transistor DT, which will not be described in detail here.
  • FIG. 21 is a flow chart of a driving method for a pixel circuit provided in the embodiment of the present application. Referring to FIG. 21 , the driving method for the pixel circuit includes:
  • Step 210 in the write frame, the data write module writes the data voltage to the control end of the driving module in the data write phase, and the compensation module compensates for the threshold voltage of the driving module in the data write phase of the write frame; the reset module resets the potential of the first end and the second end of the driving module to a fixed reset voltage in the reset phase, the light-emitting control module is turned on in the light-emitting phase, and the driving module drives the light-emitting module to emit light in the light-emitting phase.
  • the resetting phase is between the data writing phase and the light emitting phase.
  • a valid signal is input to the control end of the data writing module through a control signal line connected to the control end of the data writing module, so that the data writing module is turned on during the data writing phase of the writing frame, and the data writing module writes the data voltage to the control end of the driving module;
  • a valid signal is input to the control end of the compensation module through a control signal line connected to the control end of the compensation module, so that the compensation module is turned on during the data writing phase of the writing frame, and the compensation module compensates for the threshold voltage of the driving module during the data writing phase of the writing frame.
  • a valid signal is input to the control end of the reset module through a control signal line connected to the control end of the reset module, so that the reset module is turned on during the reset phase of the write frame, so that the reset module resets the potential of the first end and the second end of the driving module to a fixed reset voltage during the reset phase.
  • a valid signal is input to the control end of the light-emitting control module through a control signal line connected to the control end of the light-emitting control module, so that the light-emitting control module is turned on during the light-emitting phase of the writing frame, and the driving module drives the light-emitting module to emit light during the light-emitting phase.
  • Step 220 in the holding frame, the reset module resets the potentials of the first and second ends of the driving module to a fixed reset voltage in the reset phase, the light-emitting control module is turned on in the light-emitting phase, and the driving module drives the light-emitting module to emit light in the light-emitting phase.
  • the reset phase is before the light-emitting phase.
  • a valid signal is input to the control end of the reset module through a control signal line connected to the control end of the reset module, so that the reset module is turned on during the reset phase of the holding frame, so that the reset module resets the potential of the first end and the second end of the driving module to a fixed reset voltage during the reset phase.
  • a valid signal is input to the control end of the light-emitting control module through a control signal line connected to the control end of the light-emitting control module, so that the light-emitting control module is turned on during the light-emitting stage of the holding frame, and the driving module drives the light-emitting module to emit light during the light-emitting stage.
  • the driving method is used to drive the pixel circuit of any of the above embodiments of the present application and will not be described in detail here.
  • the light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit, and the pixel circuit also includes an initialization module;
  • Figure 22 is a flowchart of a driving method for a pixel circuit in a writing frame provided in an embodiment of the present application.
  • the driving method of the pixel circuit in the writing frame includes:
  • Step 310 In the second initialization stage, the initialization module is turned on to write the initialization voltage into the first terminal of the light emitting module and the control terminal of the driving module.
  • the second light emitting control unit and the compensation module are turned on in the second initialization phase, and the initialization voltage is written to the control end of the driving module through the initialization module, the second light emitting control unit and the compensation module.
  • a valid signal is input to the control end of the initialization module through the control signal line connected to the control end of the initialization module, so that the initialization module is turned on and the initialization voltage is written to the first end of the light-emitting module.
  • a valid signal is input to the control end of the second light-emitting control unit through the control signal line connected to the control end of the second light-emitting control unit, so that the second light-emitting control unit is turned on;
  • a valid signal is input to the control end of the compensation module through the control signal line connected to the control end of the compensation module, so that the compensation module is turned on, so that the initialization voltage passes through the initialization module, the second light-emitting control unit and the compensation module. Write to the control end of the driver module.
  • Step 320 In the pre-charging stage, the data writing module writes the pre-charging voltage to the control terminal of the driving module.
  • the pre-charging voltage is the data voltage corresponding to the upper n rows of pixel circuits in the same column of the pixel circuits, where n ⁇ 2.
  • a valid signal is input to the control end of the data write module through the control signal line connected to the control end of the data write module, so that the data write module is turned on.
  • a valid signal is input to the control end of the compensation module through the control signal line connected to the control end of the compensation module, so that the compensation module is turned on.
  • the pre-charge voltage is written to the control end of the driving module through the data write module, the driving module and the compensation module.
  • Step 330 In the first initialization stage, the initialization module is turned on to write the initialization voltage into the first terminal of the light emitting module and the control terminal of the driving module.
  • the second light emitting control unit and the compensation module are turned on in the first initialization phase, and the initialization voltage is written to the control end of the driving module through the initialization module, the second light emitting control unit and the compensation module.
  • a valid signal is input to the control end of the initialization module through the control signal line connected to the control end of the initialization module, so that the initialization module is turned on and the initialization voltage is written to the first end of the light-emitting module.
  • a valid signal is input to the control end of the second light-emitting control unit through the control signal line connected to the control end of the second light-emitting control unit, so that the second light-emitting control unit is turned on;
  • a valid signal is input to the control end of the compensation module through the control signal line connected to the control end of the compensation module, so that the compensation module is turned on, so that the initialization voltage is written to the control end of the driving module through the initialization module, the second light-emitting control unit and the compensation module.
  • Step 340 In the data writing phase, the data writing module writes the data voltage to the control terminal of the driving module, and the compensation module compensates for the threshold voltage of the driving module.
  • a valid signal is input to the control end of the data writing module through a control signal line connected to the control end of the data writing module, so that the data writing module is turned on during the data writing stage of the writing frame, and the data writing module writes the data voltage to the control end of the driving module;
  • a valid signal is input to the control end of the compensation module through a control signal line connected to the control end of the compensation module, so that the compensation module is turned on during the data writing stage of the writing frame, and the compensation module compensates for the threshold voltage of the driving module during the data writing stage of the writing frame.
  • Step 350 In the reset phase, the reset module resets the potentials of the first terminal and the second terminal of the driving module to a fixed reset voltage.
  • a valid signal is input to the control end of the reset module through a control signal line connected to the control end of the reset module, so that the reset module is turned on during the reset phase, and the reset module resets the potentials of the first end and the second end of the driving module to a fixed reset voltage during the reset phase.
  • Step 360 In the light-emitting stage, the light-emitting control module is turned on, and the driving module drives the light-emitting module to emit light.
  • a valid signal is input to the control end of the light-emitting control module through a control signal line connected to the control end of the light-emitting control module, so that the light-emitting control module is turned on in the light-emitting stage, and the driving module drives the light-emitting module to emit light in the light-emitting stage.
  • the second initialization phase is before the first initialization phase
  • the pre-charge phase is between the first initialization phase and the second initialization phase
  • the data write phase is after the first initialization phase
  • FIG. 23 is a flow chart of a driving method of a pixel circuit in a holding frame provided by an embodiment of the present application.
  • the driving method of the pixel circuit in a holding frame includes:
  • Step 410 In the second initialization stage, the initialization module writes the initialization voltage into the first end of the light emitting module.
  • a valid signal is input to the control end of the initialization module through a control signal line connected to the control end of the initialization module, so that the initialization module is turned on and the initialization voltage is written into the first end of the light emitting module.
  • Step 420 In the first initialization stage, the initialization module writes the initialization voltage into the first end of the light emitting module.
  • a valid signal is input to the control end of the initialization module through a control signal line connected to the control end of the initialization module, so that the initialization module is turned on and the initialization voltage is written into the first end of the light emitting module.
  • Step 430 In the reset phase, the reset module resets the potentials of the first terminal and the second terminal of the driving module to a fixed reset voltage.
  • a valid signal is input to the control end of the reset module through a control signal line connected to the control end of the reset module, so that the reset module is turned on during the reset phase, and the reset module resets the potentials of the first end and the second end of the driving module to a fixed reset voltage during the reset phase.
  • Step 440 In the light-emitting stage, the light-emitting control module is turned on, and the driving module drives the light-emitting module to emit light.
  • a valid signal is input to the control end of the light-emitting control module through a control signal line connected to the control end of the light-emitting control module, so that the light-emitting control module is turned on in the light-emitting stage, and the driving module drives the light-emitting module to emit light in the light-emitting stage.

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Abstract

一种像素电路及其驱动方法，通过设置像素电路包括重置模块（160），重置模块（160）与驱动模块（120）的第一端或第二端电连接，重置模块（160）在写入帧的数据写入阶段和发光阶段之间对驱动模块（120）的第一端和第二端的电位进行重置，并在保持帧的发光阶段之前对驱动模块（120）的第一端和第二端的电位进行重置。

Description

像素电路及其驱动方法
本申请要求在2022年10月12日提交中国专利局、申请号为202211245823.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种像素电路及其驱动方法。
背景技术
随着显示技术的发展，用户对显示质量的要求也越来越高。
显示装置在工作时，会有不同的工作模式，不同工作模式下的刷新频率不同。例如显示装置在显示静态图片和显示游戏的动态画面时，刷新频率是不同的，在不同的工作模式下，显示装置需要进行刷新频率的切换。
然而，在刷新频率切换时，显示装置的画面显示质量较差。
发明内容
本申请提供一种像素电路及其驱动方法，以实现提高刷新频率切换时的显示质量。
第一方面，本申请实施例提供了一种像素电路，包括：数据写入模块、驱动模块、补偿模块、发光控制模块和发光模块；
数据写入模块设置为在写入帧的数据写入阶段向驱动模块的控制端写入数据电压；
补偿模块设置为在写入帧的数据写入阶段对驱动模块的阈值电压进行补偿；
发光控制模块设置为在写入帧和保持帧的发光阶段导通，驱动模块设置为在发光阶段驱动发光模块发光；
像素电路还包括重置模块，重置模块与驱动模块的第一端或第二端电连接，重置模块设置为在重置阶段将驱动模块的第一端和第二端的电位重置为固定的 重置电压；
在写入帧，重置阶段介于数据写入阶段和发光阶段之间；在保持帧，重置阶段在发光阶段之前。
第二方面，本申请实施例还提供了一种像素电路的驱动方法，包括：
在写入帧，数据写入模块在数据写入阶段向驱动模块的控制端写入数据电压，补偿模块在写入帧的数据写入阶段对驱动模块的阈值电压进行补偿；重置模块在重置阶段将驱动模块的第一端和第二端的电位重置为固定的重置电压，发光控制模块在发光阶段导通，驱动模块在发光阶段驱动发光模块发光；
在保持帧，重置模块在重置阶段将驱动模块的第一端和第二端的电位重置为固定的重置电压，发光控制模块在发光阶段导通，驱动模块在发光阶段驱动发光模块发光；
在写入帧，重置阶段介于数据写入阶段和发光阶段之间；在保持帧，重置阶段在发光阶段之前。
本申请实施例的像素电路及其驱动方法，通过设置像素电路包括重置模块，重置模块与驱动模块的第一端或第二端电连接，重置模块在写入帧的数据写入阶段和发光阶段之间对驱动模块的第一端和第二端的电位进行重置，并在保持帧的发光阶段之前对驱动模块的第一端和第二端的电位进行重置，进而使得写入帧和保持帧的发光阶段前驱动模块的第一端的电位相同，写入帧和保持帧的发光阶段前驱动模块的第二端的电位也相同，进而使得写入帧和保持帧的发光阶段前驱动模块的偏置状态相同，进而有利于改善驱动模块的瞬态特性，使得进行刷新频率切换时发光模块的亮度不会发生突变，以及低频显示的写入帧和保持帧，发光模块的亮度不会发生突变，进而有利于提高显示质量。
附图说明
图1是本申请实施例提供的一种像素电路的结构示意图；
图2是本申请实施例提供的另一种像素电路的结构示意图；
图3是本申请实施例提供的另一种像素电路的结构示意图；
图4是本申请实施例提供的另一种像素电路的结构示意图；
图5是本申请实施例提供的一种像素电路的写入帧的驱动时序图；
图6是本申请实施例提供的一种像素电路的保持帧的驱动时序图；
图7是本申请实施例提供的另一种像素电路的写入帧的驱动时序图；
图8是本申请实施例提供的另一种像素电路的保持帧的驱动时序图；
图9是本申请实施例提供的另一种像素电路结构示意图；
图10是本申请实施例提供的另一种像素电路的写入帧的驱动时序；
图11是本申请实施例提供的另一种像素电路的结构示意图；
图12是本申请实施例提供的另一种像素电路的写入帧的驱动时序图；
图13是本申请实施例提供的另一种像素电路的写入帧的驱动时序图；
图14是本申请实施例提供的一种像素电路的保持帧的驱动时序图；
图15是本申请实施例提供的另一种像素电路的写入帧的驱动时序图；
图16是本申请实施例提供的另一种像素电路的保持帧的驱动时序图；
图17是本申请实施例提供的另一种像素电路的写入帧的驱动时序图；
图18是本申请实施例提供的另一种像素电路的写入帧的驱动时序图；
图19是本申请实施例提供的另一种像素电路的结构示意图；
图20是本申请实施例提供的另一种像素电路的写入帧的驱动时序图；
图21是本申请实施例提供的一种像素电路的驱动方法的流程图；
图22是本申请实施例提供的一种像素电路的在写入帧的驱动方法的流程图；
图23是本申请实施例提供的一种像素电路的在保持帧的驱动方法的流程图。
具体实施方式
下面结合附图和实施例对本申请作详细说明。
刷新频率切换时，显示装置的画面显示质量较差。经研究发现，出现上述问题的原因在于，显示装置在进行显示时，低刷新频率是在高刷新频率的基础 上跳帧实现，例如刷新频率为60Hz时，60个数据帧均为写入帧，在每个写入帧均进行数据的写入；在刷新频率为1Hz时，在60Hz的基础上，将一个数据帧作为写入帧，其他数据帧作为保持帧，只有在写入帧进行数据的写入，在保持帧不进行数据的写入。因像素电路中，数据写入时需要通过驱动晶体管，因此写入帧和保持帧驱动晶体管的动作不同，因此驱动晶体管的特性有差异，造成在刷新频率切换以及低频显示时，显示装置的显示质量较差。
本申请实施例提供了一种像素电路，图1是本申请实施例提供的一种像素电路的结构示意图，参考图1，该像素电路包括：数据写入模块110、驱动模块120、补偿模块130、发光控制模块140和发光模块150；数据写入模块110设置为在写入帧的数据写入阶段向驱动模块120的控制端写入数据电压；补偿模块130设置为在写入帧的数据写入阶段对驱动模块120的阈值电压进行补偿；发光控制模块140设置为在写入帧和保持帧的发光阶段导通，驱动模块120设置为在发光阶段驱动发光模块150发光；像素电路还包括重置模块160，重置模块160与驱动模块120的第一端或第二端电连接，重置模块160设置为在重置阶段对驱动模块120的第一端和第二端的电位重置为固定的重置电压VEH；其中，在写入帧，重置阶段介于数据写入阶段和发光阶段之间；在保持帧，重置阶段在发光阶段之前。
像素电路可以工作在不同的刷新频率下。其中，在高刷新频率下，每个数据帧均为写入帧；在低刷新频率下，可以将至少一个数据帧作为写入帧，其他数据帧作为保持帧。
参考图1，数据写入模块110的第一端连接数据线Data，数据写入模块110的第二端连接驱动模块120的第一端；补偿模块130的第一端连接驱动模块120的第二端，补偿模块130的第二端连接驱动模块120的控制端G1。发光控制模块140、驱动模块120和发光模块150串联在第一电源线VDD和第二电源线VSS之间。重置模块160与驱动模块120的第一端或第二端电连接，进而实现在重置阶段对驱动模块120第一端和第二端的电位进行重置。
其中，重置电压VEH可以根据实际调屏效果进行设定，示例性的，在实际调屏时，可以调节重置电压VEH的大小，将实际调屏效果最优时对应的重置电压设定为显示面板出厂后最终固定的重置电压，也即本实施例像素电路中的重置电压VEH。
其中，图1中示意性示出了重置模块160与驱动模块120的第二端电连接的情况。以图1所示像素电路为例，该像素电路在写入帧的工作过程如下：
在数据写入阶段，数据写入模块110和补偿模块130导通，发光控制模块140和重置模块160关断。数据写入模块110将数据电压写到驱动模块120的控制端G1，补偿模块130对驱动模块120的阈值电压进行补偿，其中，驱动模块120包括驱动晶体管DT，驱动模块120的阈值电压为驱动晶体管DT的阈值电压。
在重置阶段，重置模块160导通，重置模块160将重置电压VEH写入到驱动模块120的第二端，并通过驱动模块120将重置电压VEH写入到驱动模块120的第一端。数据写入模块110、补偿模块130以及发光控制模块140关断。在本申请其他可选实施例中，重置模块160与驱动模块120的第一端连接，在重置阶段，重置模块160导通，将重置电压VEH写入到驱动模块120的第一端，并通过驱动模块120写入到驱动模块120的第二端。
在发光阶段，发光控制模块140导通，驱动模块120根据自身控制端G1和第一端的电压产生驱动电流，驱动发光模块150发光。数据写入模块110、补偿模块130以及重置模块160关断。
该像素电路在保持帧的工作过程如下：
在重置阶段，重置模块160导通，重置模块160将重置电压VEH写入到驱动模块120的第二端，并通过驱动模块120将重置电压VEH写入到驱动模块120的第一端。数据写入模块110、补偿模块130以及发光控制模块140关断。
在发光阶段，发光控制模块140导通，驱动模块120根据自身控制端G1和第一端的电压产生驱动电流，驱动发光模块150发光。数据写入模块110、补偿 模块130以及重置模块160关断。
本实施例的像素电路，通过设置像素电路包括重置模块，重置模块与驱动模块的第一端或第二端电连接，重置模块在写入帧的数据写入阶段和发光阶段之间对驱动模块的第一端和第二端的电位进行重置，并在保持帧的发光阶段之前对驱动模块的第一端和第二端的电位进行重置，进而使得写入帧和保持帧的发光阶段前驱动模块的第一端的电位相同，写入帧和保持帧的发光阶段前驱动模块的第二端的电位也相同，进而使得写入帧和保持帧的发光阶段前驱动模块的偏置状态相同，进而有利于改善驱动模块的瞬态特性，使得进行刷新频率切换时发光模块的亮度不会发生突变，以及低频显示的写入帧和保持帧，发光模块的亮度不会发生突变，进而有利于改善切频和低频闪烁的问题，提高显示质量。
继续参考图1，可选的，重置模块160的第一端接入重置电压VEH，重置模块160的第二端与驱动模块120的第二端电连接，重置模块160设置为在自身控制端接入信号的控制下，在重置阶段将重置电压VEH写入驱动模块120的第一端和第二端。
在重置阶段，重置模块160的控制端输入有效控制信号，使得重置模块160导通，重置电压VEH通过重置模块160写入到驱动模块120的第二端。为保证驱动模块120在重置阶段可以导通，使得重置电压VEH可以从驱动模块120的第二端写到驱动模块120的第一端，可以对重置电压VEH的大小进行设定。
在一个可选实施例中，驱动晶体管DT为P型晶体管，重置电压VEH大于数据电压，进而使得驱动晶体管DT在重置阶段能够导通，保证重置电压VEH可以从驱动模块120的第二端写到驱动模块120的第一端。
在另一个可选实施例中，驱动晶体管DT为N型晶体管，重置电压VEH小于数据电压，进而使得驱动晶体管DT在重置阶段能够导通，保证重置电压VEH可以从驱动模块120的第二端写到驱动模块120的第一端。
继续参考图1，可选的，发光控制模块140包括第一发光控制单元141和第二发光控制单元142，第一发光控制单元141串联在第一电源线VDD与驱动模块120的第一端之间；第二发光控制单元142的串联在驱动模块120的第二端与发光模块150的第一端之间，发光模块150的第二端与第二电源线VSS电连接。
图1所示像素电路中，重置模块160是在像素电路包括的数据写入模块110、驱动模块120、补偿模块130、发光控制模块140和发光模块150基础上新增加的模块；在本申请其他可选实施例中，重置模块160可以是利用像素电路所包括的数据写入模块110、驱动模块120、补偿模块130、发光控制模块140和发光模块150中的部分来形成。
图2是本申请实施例提供的另一种像素电路的结构示意图，参考图2，可选的，发光控制模块140包括第一发光控制单元141和第二发光控制单元142，第一发光控制单元141串联在第一电源线VDD与驱动模块120的第一端之间；第二发光控制单元142的串联在驱动模块120的第二端与发光模块150的第一端之间，发光模块150的第二端与第二电源线VSS电连接；
数据写入模块110的第一端与数据线Data电连接，数据写入模块110的第二端与驱动模块120的第一端电连接；数据线Data设置为在写入帧的数据写入阶段传输数据电压，以及在保持帧的重置阶段传输第一电源电压；
重置模块160包括第一发光控制单元141和数据写入模块110；其中，第一发光控制单元141设置为在写入帧的重置阶段，将第一电源电压写入到驱动模块120的第一端和第二端；数据写入模块110设置为在保持帧的重置阶段，将第一电源电压写入到驱动模块120的第一端和第二端，即在保持帧的重置阶段，数据写入模块110输入端输入的电压为第一电源电压。
图2所示像素电路在写入帧的工作过程中，数据写入阶段与发光阶段分别与图1所示像素电路在写入帧的数据写入阶段和发光阶段的工作过程相同。
图2所示像素电路在写入帧的重置阶段，第一发光控制单元141导通，第一发光控制单元141将第一电源电压写入到驱动模块120的第一端，并通过驱动模块120将第一电源电压写入到驱动模块120的第二端。数据写入模块110、补偿模块130以及第二发光控制单元142关断。
该像素电路在保持帧的工作过程如下：
在重置阶段，数据写入模块110导通，数据写入模块110将第一电源电压写入到驱动模块120的第一端，并通过驱动模块120将第一电源电压写入到驱动模块120的第二端。补偿模块130、第一发光控制单元141、第二发光控制单元142关断。
在发光阶段的工作过程与图1所示像素电路在保持帧的发光阶段工作过程相同，在此不再赘述。
本实施例中，数据写入模块110输入端所接入的电压不是固定不变的，在写入帧，数据写入模块110输入端输入的电压为数据电压，在保持帧，数据写入模块110输入端输入的电压为第一电源电压。
本实施例中，重置模块160采用像素电路中的原有结构形成，不需在像素电路中数据写入模块110、驱动模块120、补偿模块130、发光控制模块140和发光模块150的基础上额外增加电路模块，进而在提高显示质量的基础上，使得像素电路所包括的器件数量较少，有利于提高像素密度。
可选的，在图1-2所示像素电路的基础上，可选的，像素电路还包括初始化模块，图3是本申请实施例提供的另一种像素电路的结构示意图，图4是本申请实施例提供的另一种像素电路的结构示意图，图3是在图1所示像素电路的基础上增加初始化模块170的像素电路结构，图4是在图2所示像素电路上增加初始化模块170的像素电路结构，参考图3和图4，可选的，初始化模块170设置为在写入帧的第一初始化阶段，将初始化电压写入到发光模块150的第一端和驱动模块120的控制端，第二发光控制单元142和补偿模块130设置为在 写入帧的第一初始化阶段导通，以将写入到发光模块150第一端的初始化电压通过第二发光控制单元142和补偿模块130写入到驱动模块的控制端；其中，在写入帧，第一初始化阶段在数据写入阶段之前。
可选的，初始化模块170还设置为在保持帧的第一初始化阶段，将初始化电压写入到发光模块150的第一端；在保持帧，第一初始化阶段在重置阶段之前。
图3和图4所示像素电路在写入帧和保持帧的工作过程均包括第一初始化阶段。在写入帧的第一初始化阶段，初始化模块170导通，进而将初始化电压写入到发光模块150的第一端，实现对发光模块150的初始化；同时，第二发光控制单元142和补偿模块130导通，初始化电压通过初始化模块170、第二发光控制单元142和补偿模块130写入到驱动模块120的控制端，实现对驱动模块120的控制端的初始化。在保持帧的第一初始化阶段，初始化模块170导通，将初始化电压写入到发光模块150的第一端，进而保证在保持帧进行插黑时，发光模块150不会发光，进而有利于提高显示质量。
对于图4所示像素电路，第一发光控制单元141和第二发光控制单元142在保持帧的第一初始化阶段也可导通，进而使得在保持帧的第一初始化阶段，第一电源线与初始化线Vref之间存在大电流，有利于改善残影，提升显示质量。
继续参考图3和图4，可选的，初始化模块170的控制端连接第一扫描线S1，初始化模块170的第一端连接初始化线Vref，初始化模块170的第二端连接发光模块150的第一端；数据写入模块110的控制端连接第二扫描线S2，数据写入模块110的第一端连接数据线Data，数据写入模块110的第二端连接驱动模块120的第一端。其中，数据写入模块110的第一端作为上述实施例中数据写入模块110的输入端。
可选的，第一发光控制单元141的控制端连接第一发光控制信号线EM1，第一发光控制单元141的第一端连接第一电源线VDD，第一发光控制单元141的第二端连接驱动模块120的第一端；第二发光控制单元142的控制端连接第 二发光控制信号线EM2，第二发光控制单元142的第一端连接驱动模块120的第二端，第二发光控制单元142的第二端连接发光模块150的第一端；发光模块150的第二端连接第二电源线VSS。
参考图3，补偿模块130连接在驱动模块120的第二端与驱动模块120的控制端之间，补偿模块130的控制端连接补偿控制信号线Sn，补偿模块130的第一端连接驱动模块120的第二端，补偿模块130的第二端连接驱动模块120的控制端。
参考图4，补偿模块130连接在驱动模块120的第二端与驱动模块120的控制端之间，补偿模块130的控制端连接第一发光控制信号线EM1，补偿模块130的第一端连接驱动模块120的第二端，补偿模块130的第二端连接驱动模块120的控制端。
图3可以对应将图1中各模块细化为电路器件的一种结构，图4可以对应将图2中各模块细化为电路器件的一种结构，可选的，驱动模块120包括驱动晶体管DT，数据写入模块110包括第一晶体管T1，补偿模块130包括第二晶体管T2，第一发光控制单元141包括第三晶体管T3，第二发光控制单元142包括第四晶体管T4，初始化模块170包括第六晶体管T6，发光模块150包括发光器件D1，该发光器件D1可以是有机发光器件D1，也可以是无机发光器件D1。
继续参考图3，可选的，重置模块160的控制端连接第三扫描线S3，重置模块160包括第五晶体管T5。
可选的，第二晶体管T2为N型晶体管，其他晶体管为P型晶体管。可选的，第一发光控制单元所包括的晶体管与补偿模块所包括的晶体管的沟道类型相反。可选的，第二晶体管T2为氧化物晶体管，氧化物晶体管的漏电流较小，进而使得发光阶段驱动模块120的控制端的电位可以得到更好地保持，更加有利于提高显示均一性，提高显示质量。
图5是本申请实施例提供的一种像素电路的写入帧的驱动时序图，该驱动时序可用于驱动图3所示像素电路。参考图3和图5，在写入帧，像素电路的工 作过程包括先后进行的第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4。
在第一初始化阶段t1，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2、第三扫描线S3上的信号为高电平，补偿控制信号线Sn上的补偿控制信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，第二晶体管T2响应高电平的补偿控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。
在数据写入阶段t2，第二扫描线S2上的第二扫描信号为低电平，像素电路中其他控制信号为高电平，第一晶体管T1响应低电平的第二扫描信号导通，第二晶体管T2响应高电平的补偿控制信号导通，数据电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2写入到驱动晶体管DT的栅极，同时实现对驱动晶体管DT的阈值电压的补偿。
在重置阶段t3，第三扫描信号为低电平，补偿控制信号为低电平，像素电路中其他控制信号均为高电平，第五晶体管T5响应低电平的第三扫描信号导通，重置电压VEH通过第五晶体管T5写入到驱动晶体管DT的漏极，并通过驱动晶体管DT写到驱动晶体管DT的源极。
在发光阶段t4，第一发光控制信号和第二发光控制信号为低电平，第三晶体管T3和第四晶体管T4导通，驱动晶体管DT驱动发光器件D1发光。
图6是本申请实施例提供的一种像素电路的保持帧的驱动时序图，该驱动时序可用于驱动图3所示像素电路。
参考图3和图6，在保持帧，像素电路的工作过程包括先后进行的第一初始 化阶段t1、重置阶段t3和发光阶段t4。
在第一初始化阶段t1，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2、第三扫描线S3上的信号为高电平，补偿控制信号线Sn上的补偿控制信号为低电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。
在本申请另一可选实施例中，在保持帧，第一发光控制线上的第一发光控制信号始终为低电平，则在第一初始化阶段t1，第三晶体管T3导通，由于第一初始化阶段t1，第四晶体管T4也导通，因此第一电源线VDD与初始化线Vref之间存在大电流，进而有利于改善残影。
在重置阶段t3，第三扫描信号为低电平，补偿控制信号为低电平，像素电路中其他控制信号均为高电平，第五晶体管T5响应低电平的第三扫描信号导通，重置电压VEH通过第五晶体管T5写入到驱动晶体管DT的漏极，并通过驱动晶体管DT写到驱动晶体管DT的源极。
在发光阶段t4，第一发光控制信号和第二发光控制信号为低电平，第三晶体管T3和第四晶体管T4导通，驱动晶体管DT驱动发光器件D1发光。
可选的，图3中，第一扫描线S1、第二扫描线S2和第三扫描线S3连接相同的扫描驱动电路，进而有利于显示面板窄边框的实现。
参考图4，可选的，重置模块包括第一晶体管T1和第三晶体管T3。图7是本申请实施例提供的另一种像素电路的写入帧的驱动时序图，该驱动时序可用于驱动图4所示像素电路。
参考图4和图7，在写入帧，像素电路的工作过程包括先后进行的第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4。
在第一初始化阶段t1，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2上的信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，第二晶体管T2响应高电平的第一发光控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。
在数据写入阶段t2，第二扫描线S2上的第二扫描信号为低电平，像素电路中其他控制信号为高电平，第一晶体管T1响应低电平的第二扫描信号导通，第二晶体管T2响应高电平的第一发光控制信号导通，在写入帧数据线Data输入数据电压，数据电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2向驱动晶体管DT的栅极写入，同时实现对驱动晶体管DT的阈值电压的补偿。
在重置阶段t3，第一发光控制信号为低电平，第三晶体管T3响应低电平的第一发光控制信号导通，第一电源电压通过第三晶体管T3写入到驱动晶体管DT的源极，并通过驱动晶体管DT写到驱动晶体管DT的漏极。
在发光阶段t4，第一发光控制信号和第二发光控制信号为低电平，第三晶体管T3和第四晶体管T4导通，驱动晶体管DT驱动发光器件D1发光。
图8是本申请实施例提供的另一种像素电路的保持帧的驱动时序图，该驱动时序可用于驱动图4所示像素电路。
参考图4和图8，在保持帧，像素电路的工作过程包括先后进行的第一初始化阶段t1、重置阶段t3和发光阶段t4。
在第一初始化阶段t1，第一发光控制信号线EM1上的第一发光控制信号为低电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2上的信号为高电平。因此， 第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，第三晶体管T3响应低电平的第一发光控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，第一电源线VDD与初始化线Vref之间存在大电流，有利于改善残影，提升显示质量。
在重置阶段t3，第一发光控制信号为低电平，第三晶体管T3响应低电平的第一发光控制信号导通，第一电源电压通过第三晶体管T3写入到驱动晶体管DT的源极；同时第二扫描信号为低电平，数据线Data输入的电压也为第一电源电压，因此第一电源电压还通过第一晶体管T1写入到驱动晶体管DT源极，第一电源电压通过驱动晶体管DT写到驱动晶体管DT的漏极。也即，第一发光控制单元141(第三晶体管T3)还设置为在写入帧的重置阶段，将第一电源电压写入到驱动模块120的第一端和第二端。
在发光阶段t4，第一发光控制信号和第二发光控制信号为低电平，第三晶体管T3和第四晶体管T4导通，驱动晶体管DT驱动发光器件D1发光。
可选的，图4中，第一扫描线S1和第二扫描线S2连接相同的扫描驱动电路，进而有利于显示面板窄边框的实现。
图9是本申请实施例提供的另一种像素电路结构示意图，图9可以对应图1中各模块细化为电路器件的另一种结构。参考图9，图9与图3的区别在于，初始化模块170的控制端连接第一发光控制线EM1，数据写入模块110的控制端连接第一扫描线S1，重置模块160的控制端连接第二扫描线S2。参考图9，可选的，第一发光控制单元141的控制端连接第一发光控制线EM1，第二发光控制单元142的控制端连接第二发光控制线EM2；补偿模块130连接在驱动模块120的第二端与驱动模块120的控制端之间，补偿模块130的控制端连接补偿控制信号线Sn；初始化模块170的控制端连接第一发光控制线EM1。
可选的，初始化模块170所包括的晶体管与第一发光控制单元141所包括 的晶体管的沟道类型相反。可选的，初始化模块170所包括的晶体管为氧化物晶体管。参考图9，其中，第二晶体管T2和第六晶体管T6为N型晶体管，其他晶体管均为P型晶体管。
图10是本申请实施例提供的另一种像素电路的写入帧的驱动时序，该驱动时序可用于驱动图9所示像素电路。参考图9和图10，在写入帧，像素电路的工作过程包括先后进行的第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4。
在第一初始化阶段t1，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为高电平，第二扫描线S2上的第二扫描信号为高电平，补偿控制信号线Sn上的补偿控制信号为高电平。因此，第六晶体管T6响应高电平的第一发光控制信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，第二晶体管T2响应高电平的补偿控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。
在数据写入阶段t2，第一扫描线S1上的第二扫描信号为低电平，像素电路中其他控制信号为高电平，第一晶体管T1响应低电平的第一扫描信号导通，第二晶体管T2响应高电平的补偿控制信号导通，数据电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2向驱动晶体管DT的栅极写入，同时实现对驱动晶体管DT的阈值电压的补偿。
在重置阶段t3，第二扫描信号为低电平，补偿控制信号为低电平，像素电路中其他控制信号均为高电平，第五晶体管T5响应低电平的第二扫描信号导通，重置电压VEH通过第五晶体管T5写入到驱动晶体管DT的漏极，并通过驱动晶体管DT写到驱动晶体管DT的源极。
在发光阶段t4，第一发光控制信号和第二发光控制信号为低电平，第三晶 体管T3和第四晶体管T4导通，驱动晶体管DT驱动发光器件D1发光。
图9所示像素电路在保持帧的驱动时序与图10所示写入帧的驱动时序区别仅在于，在保持帧，补偿控制信号一直为低电平，其他控制信号与写入帧的相同。图9所示像素电路在保持帧的工作过程包括先后进行的第一初始化阶段、重置阶段和发光阶段。
其中，在第一初始化阶段，第一发光控制信号为高电平，初始化线上的初始化电压通过第六晶体管写入到发光器件的阳极，实现对发光器件阳极的初始化。在本申请另一可选实施例中，在保持帧，第一发光控制线上的第一发光控制信号始终为低电平。则在第一初始化阶段，第三晶体管导通，第一电源线与初始化线之间存在大电流，进而有利于改善残影。
保持帧的重置阶段、发光阶段分别与写入帧的重置阶段、发光阶段的工作过程相同，在此不再赘述。
可选的，图9中，第一扫描线S1和第二扫描线S2连接相同的扫描驱动电路，进而有利于显示面板窄边框的实现。
图11是本申请实施例提供的另一种像素电路的结构示意图，图11可以对应将图3中各模块细化为电路器件的另一种结构。参考图11，与图3所示像素电路相同，补偿模块130的控制端与补偿控制信号线Sn连接。图11与图3所示像素电路的区别在于，第一发光控制单元141的控制端和第二发光控制单元142的控制端与同一发光控制线EM电连接。
图12是本申请实施例提供的另一种像素电路的写入帧的驱动时序图，该驱动时序可用于驱动图11所示像素电路。参考图11和图12，在写入帧，像素电路的工作过程包括先后进行的第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4。
在第一初始化阶段t1，发光控制信号线EM上的发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2、第三扫描线S3上 的信号为高电平，补偿控制信号线Sn上的补偿控制信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的发光控制信号导通，第二晶体管T2响应高电平的补偿控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。同时，第三晶体管T3响应低电平的发光控制信号导通，第一电源线VDD与初始化线Vref之间存在大电流，有利于改善残影。
在数据写入阶段t2，第二扫描线S2上的第二扫描信号为低电平，像素电路中其他控制信号为高电平，第一晶体管T1响应低电平的第二扫描信号导通，第二晶体管T2响应高电平的补偿控制信号导通，数据电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2向驱动晶体管DT的栅极写入，同时实现对驱动晶体管DT的阈值电压的补偿。
在重置阶段t3，第三扫描信号为低电平，补偿控制信号为低电平，像素电路中其他控制信号均为高电平，第五晶体管T5响应低电平的第三扫描信号导通，重置电压VEH通过第五晶体管T5写入到驱动晶体管DT的漏极，并通过驱动晶体管DT写到驱动晶体管DT的源极。
在发光阶段t4，发光控制信号为低电平，第三晶体管T3和第四晶体管T4导通，驱动晶体管DT驱动发光器件D1发光。
图11所示像素电路在保持帧的驱动时序与图12所示写入帧的驱动时序区别仅在于，在保持帧，补偿控制信号一直为低电平，其他控制信号与写入帧的相同。图11所示像素电路在保持帧的工作过程包括先后进行的第一初始化阶段、重置阶段和发光阶段。
其中，在第一初始化阶段，第一扫描信号为低电平，初始化线上的初始化电压通过第六晶体管写入到发光器件的阳极，实现对发光器件阳极的初始化。保持帧的重置阶段、发光阶段分别与写入帧的重置阶段、发光阶段的工作过程 相同，在此不再赘述。
通过上述对图3、图4、图9和图11所示像素电路在写入帧和保持帧的工作过程的分析可知，通过设置像素电路包括重置模块160，使得在写入帧和保持帧的发光阶段前，驱动晶体管DT的源极电压相同，驱动晶体管DT的漏极电压也相同，则驱动晶体管DT在写入帧和保持帧的偏置状态相同，进而确保在写入帧和保持帧发光器件D1的发光亮度一致，进而提高显示质量。
经研究还发现，像素电路工作在高刷新频率下时，对驱动模块的控制端的初始化时间较短，导致在对上一帧灰阶差异较大的不同像素电路进行初始化时，驱动模块的控制端被初始化的电压不同，则在当前帧显示时，向像素电路写入数据会存在差异，使得显示装置显示不均，同时会出现残影现象。
基于上述原因，在上述技术方案的基础上，可选的，设置写入帧还包括第二初始化阶段t11，初始化模块170还设置为在写入帧的第二初始化阶段t11，将初始化电压写入到发光模块150的第一端和驱动模块120的控制端，第二发光控制单元142和补偿模块130还设置为在写入帧的第二初始化阶段t11导通，以将写入到发光模块150第一端的初始化电压通过第二发光控制单元142和补偿模块130写入到驱动模块的控制端；其中第二初始化阶段t11在第一初始化阶段t1之前进行。
通过设置写入帧还包括第二初始化阶段t11，在第二初始化阶段t11，初始化电压写入到发光模块150的第一端，并且，初始化电压通过初始化模块170、第二发光控制单元142和补偿模块130写入到驱动模块120的控制端，对驱动模块120的控制端写入初始化电压包括第二初始化阶段t11和第一初始化阶段t1两个阶段，因此对驱动模块120的控制端写入初始化电压的时间被延长，有利于在写入帧的数据写入阶段t2之前，将驱动模块120的控制端充分写入初始化电压，进而使得在数据写入阶段t2写入数据时差异减小，提高显示装置的显示均一性，减轻残影现象。
在上述技术方案的基础上，可选的，写入帧还包括预充阶段t21，数据写入模块110还设置为在写入帧的预充阶段t21，向驱动模块120的控制端写入预充电压；其中，在写入帧，预充阶段t21介于第二初始化阶段t11和第一初始化阶段t1之间，数据写入阶段t2在第一初始化阶段t1后。
通过在第二初始化阶段t11和第一初始化阶段t1之间的预充阶段t21，向驱动模块120的控制端写入预充电压，因显示面板中一条数据线Data连接一列像素电路，一列像素电路中距离较近的两行在显示时数据电压差异较小，因此设置预充电压为像素电路同列中的上n行像素电路对应的数据电压，但是为保证像素电路正常工作，n≥2(其中本行像素电路的第二初始化阶段对应上一行像素电路的数据写入阶段，因此预充电压不能为像素电路同列中的上1行像素电路对应的数据电压)，使得在预充阶段t21，同一列像素电路中各行像素电路的驱动模块120的控制端被写入的预充电压差异较小，进而使得在第一初始化阶段t1，同一列像素电路的驱动模块120的控制端均有相近的电压开始进行初始化，写入初始化电压，进而在第一初始化阶段t1后，驱动模块120的控制端的电压差异也较小，进而使得数据写入阶段t2写入数据的差异也会较小，进而提高显示均一性。尤其对于当前帧为全屏同灰阶的显示画面，同一列像素电路对应的数据电压相同，因此无论上一帧为何种显示画面，在预充阶段t21后，驱动模块120的控制端都为相同电压，则第一初始化阶段t1时一列像素电路中各像素电路的驱动模块120的控制端均由相同电压初始化为初始化电压，进而进一步减小数据写入阶段t2写入数据的差异，提高显示均一性。
在上述技术方案的基础上，可选的，初始化模块170还设置为在保持帧的第二初始化阶段t11导通，其中，在保持帧，第二初始化阶段t11在第一初始化阶段t1之前。
通过设置初始化模块170在保持帧的第二初始化阶段t11导通，使得在保持帧进行插黑时，发光器件D1不会被点亮，保证显示质量。
图13是本申请实施例提供的另一种像素电路的写入帧的驱动时序图，该驱动时序同样可用于驱动图3所示像素电路。参考图3和图13，在写入帧，像素电路的工作过程包括先后进行的第二初始化阶段t11、预充阶段t21、第一初始化阶段t1、数据写入阶段t2和发光阶段t4。
在第二初始化阶段t11，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2、第三扫描线S3上的信号为高电平，补偿控制信号线Sn上的补偿控制信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，第二晶体管T2响应高电平的补偿控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。
在预充阶段t21，第二扫描线S2上的第二扫描信号为低电平，像素电路中其他控制信号为高电平，第一晶体管T1响应低电平的第二扫描信号导通，第二晶体管T2响应高电平的补偿控制信号导通，预充电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2写入到驱动晶体管DT的栅极。其中，与上所述的，预充电压为像素电路同列中的上n行像素电路对应的数据电压，n≥2，进而使得后续数据写入阶段t2写入数据的差异也会较小，进而提高显示均一性，减轻残影现象。
在第一初始化阶段t1，像素电路中各晶体管的工作状态与图5所示驱动时序第一初始化阶段t1对应的各晶体管的工作状态相同，区别在于，以图5所示驱动时序进行驱动时，在第一初始化阶段t1，驱动晶体管DT的栅极需要由上一帧的电压写为初始化电压，以图13所示驱动时序进行驱动时，驱动晶体管DT的栅极由预充电压写为初始化电压，使得在第一初始化阶段t1，驱动晶体管DT 的栅极可以被初始化为相近或相同电压，而使得后续数据写入阶段t2写入数据的差异也会较小，进而提高显示均一性。
在数据写入阶段t2、重置阶段t3和发光阶段t4，像素电路中各晶体管的工作状态分别与图5所示驱动时序对应的数据写入阶段t2、重置阶段t3和发光阶段t4各晶体管的工作状态相同，在此不再赘述。
图14是本申请实施例提供的一种像素电路的保持帧的驱动时序图，该驱动时序可用于驱动图3所示像素电路。
参考图3和图14，在保持帧，像素电路的工作过程包括先后进行的第二初始化阶段t11、第一初始化阶段t1、重置阶段t3和发光阶段t4。
在第二初始化阶段t11，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2、第三扫描线S3上的信号为高电平，补偿控制信号线Sn上的补偿控制信号为低电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。
在第一初始化阶段t1的工作过程与第二初始化阶段t11的工作过程相同，在此不再赘述。
参考图13和图14，因第一发光控制信号和第二发光控制信号的波形相同，因此采用图13和图14对图3所示像素电路进行驱动时，第一发光控制信号线EM1和第二发光控制信号线EM2可以连接相同的发光驱动电路，有利于窄边框的实现。
在本申请另一可选实施例中，在保持帧，第一发光控制线上的第一发光控制信号始终为低电平。则在第二初始化阶段t11和第一初始化阶段t1，第三晶体管T3导通，第一电源线VDD与初始化线Vref之间存在大电流，进而有利于改善残影。
在重置阶段t3，第三扫描信号为低电平，补偿控制信号为低电平，像素电路中其他控制信号均为高电平，第五晶体管T5响应低电平的第三扫描信号导通，重置电压VEH通过第五晶体管T5写入到驱动晶体管DT的漏极，并通过驱动晶体管DT写到驱动晶体管DT的源极。
在发光阶段t4，第一发光控制信号和第二发光控制信号为低电平，第三晶体管T3和第四晶体管T4导通，驱动晶体管DT驱动发光器件D1发光。
在本申请另一可选实施例中，在保持帧，第二扫描线S2上的可以不包括低电平脉冲信号，即在保持帧第二扫描线S2上的信号均为高电平。
图15是本申请实施例提供的另一种像素电路的写入帧的驱动时序图，该驱动时序同样可用于驱动图4所示像素电路。参考图4和图15，在写入帧，像素电路的工作过程包括先后进行的第二初始化阶段t11、预充阶段t21、第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4。
在第二初始化阶段t11，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2上的第二扫描信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，第二晶体管T2响应高电平的第一发光控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。
在预充阶段t21，第二扫描线S2上的第二扫描信号为低电平，像素电路中其他控制信号为高电平，第一晶体管T1响应低电平的第二扫描信号导通，第二晶体管T2响应高电平的第一发光控制信号导通，预充电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2写入到驱动晶体管DT的栅极。
在第一初始化阶段t1、数据写入阶段t2、重置阶段t3、发光阶段t4，在像素电路中各晶体管的工作状态分别与图7所示驱动时序对应的第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4各晶体管的工作状态相同，在此不再赘述。
本实施例中，预充电压为像素电路同列中的上n行像素电路对应的数据电压，n≥2，使得在第一初始化阶段t1驱动晶体管DT的栅极由预充电压写为初始化电压，使得在第一初始化阶段t1，驱动晶体管DT的栅极可以被初始化为相近或相同电压，而使得后续数据写入阶段t2写入数据的差异也会较小，进而提高显示均一性，减轻残影现象。
图16是本申请实施例提供的另一种像素电路的保持帧的驱动时序图，该驱动时序可用于驱动图4所示像素电路。
参考图4和图16，在保持帧，像素电路的工作过程包括先后进行的第二初始化阶段t11、第一初始化阶段t1、重置阶段t3和发光阶段t4。
在第二初始化阶段t11，第一发光控制信号线EM1上的第一发光控制信号为低电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2上的第二扫描信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时第三晶体管T3响应低电平的第一发光控制信号导通，第一电源线VDD和初始化线Vref之间存在大电流，有利于改善残影。
在第一初始化阶段t1的工作过程与第二初始化阶段t11的工作过程相同，在此不再赘述。
在重置阶段t3和发光阶段t4，像素电路中各晶体管的状态分别与图8驱动时序中重置阶段t3、发光阶段t4的工作过程相同，在此不再赘述。
图17是本申请实施例提供的另一种像素电路的写入帧的驱动时序图，该驱动时序同样可用于驱动图9所示像素电路。参考图9和图17，在写入帧，像素电路的工作过程包括先后进行的第二初始化阶段t11、预充阶段t21、第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4。
在第二初始化阶段t11，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为高电平，第二扫描线S2上的第二扫描信号为高电平，补偿控制信号线Sn上的补偿控制信号为高电平。因此，第六晶体管T6响应高电平的第一发光控制信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，第二晶体管T2响应高电平的补偿控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。
在预充阶段t21，第一扫描线S1上的第一扫描信号为低电平，像素电路中其他控制信号为高电平，第一晶体管T1响应低电平的第一扫描信号导通，第二晶体管T2响应高电平的补偿控制信号导通，预充电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2写入到驱动晶体管DT的栅极。
在第一初始化阶段t1、数据写入阶段t2、重置阶段t3、发光阶段t4，在像素电路中各晶体管的工作状态分别与图10所示驱动时序对应的第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4各晶体管的工作状态相同，在此不再赘述。
本实施例的像素电路，基于与图13和图15驱动时序同样的原因，可以提高显示均一性，减轻残影现象。在此不再赘述。
图9所示像素电路在保持帧的驱动时序与图17所示写入帧的驱动时序区别仅在于，在保持帧，补偿控制信号一直为低电平，其他控制信号与写入帧的相 同。图9所示像素电路在保持帧的工作过程包括先后进行的第二初始化阶段、第一初始化阶段、重置阶段和发光阶段。
在第二初始化阶段，第一发光控制信号线上的第一发光控制信号为高电平，第二发光控制信号线上的第二发光控制信号为低电平，第一扫描线上的第一扫描信号为高电平，第二扫描线上的第二扫描信号为高电平，补偿控制信号线上的补偿控制信号为低电平。因此，第六晶体管响应高电平的第一发光控制信号导通，第四晶体管响应低电平的第二发光控制信号导通，初始化线上的初始化电压通过第六晶体管写入到发光器件的阳极，实现对发光器件阳极的初始化。
在第一初始化阶段、保持帧的重置阶段、发光阶段分别与图17所示写入帧驱动时序的重置阶段、发光阶段的工作过程相同，在此不再赘述。
图18是本申请实施例提供的另一种像素电路的写入帧的驱动时序图，该驱动时序可用于驱动图11所示像素电路。参考图11和图18，在写入帧，像素电路的工作过程包括先后进行的第二初始化阶段t11、预充阶段t21、第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4。
在第二初始化阶段t11，发光控制信号线上的发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2、第三扫描线S3上的信号为高电平，补偿控制信号线Sn上的补偿控制信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的发光控制信号导通，第二晶体管T2响应高电平的补偿控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。同时，第三晶体管T3响应低电平的发光控制信号导通，第一电源线VDD与初始化线Vref之间存在大电流，有利于改善残影。
在预充阶段t21，第二扫描线S2上的第二扫描信号为低电平，其他控制信 号均为高电平，第一晶体管T1响应低电平的第二扫描信号导通，第二晶体管T2响应高电平的补偿控制信号导通，预充电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2写入到驱动晶体管DT的栅极。
在第一初始化阶段t1、数据写入阶段t2、重置阶段t3、发光阶段t4，在像素电路中各晶体管的工作状态分别与图12所示驱动时序对应的第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4各晶体管的工作状态相同，在此不再赘述。
本实施例的像素电路，基于与图13、图15和图17驱动时序同样的原因，可以提高显示均一性，减轻残影现象，在此不再赘述。
图11所示像素电路在保持帧的驱动时序与图18所示写入帧的驱动时序区别仅在于，在保持帧，补偿控制信号一直为低电平，其他控制信号与写入帧的相同。图11所示像素电路在保持帧的工作过程包括先后进行的第二初始化阶段、第一初始化阶段、重置阶段和发光阶段。
在第二初始化阶段，发光控制信号线上的发光控制信号为低电平，第一扫描线上的第一扫描信号为低电平，第二扫描线、第三扫描线上的信号为高电平，补偿控制信号线上的补偿控制信号为低电平。因此，第六晶体管响应低电平的第一扫描信号导通，第四晶体管响应低电平的发光控制信号导通，初始化线上的初始化电压通过第六晶体管写入到发光器件的阳极，实现对发光器件阳极的初始化。同时，第三晶体管响应低电平的发光控制信号导通，第一电源线与初始化线之间存在大电流，有利于改善残影。
在第一初始化阶段、保持帧的重置阶段、发光阶段分别与图18所示写入帧驱动时序的第一初始化阶段、重置阶段、发光阶段的工作过程相同，在此不再赘述。
图19是本申请实施例提供的另一种像素电路的结构示意图，图19可以对应将图1中各模块细化为电路器件的另一种结构。其中，图19与图3的区别仅 在于，图19中，补偿模块130(第二晶体管T2)连接第一发光控制信号线EM1，像素电路中其他结构和连接关系与图3相同，在此不再赘述。图19与图11的区别仅在于，图19中，第一发光控制单元141连接第一发光控制线，第二发光控制单元142连接第二发光控制线，其他结构及连接关系与图11相同。
图20是本申请实施例提供的另一种像素电路的写入帧的驱动时序图，该驱动时序可用于驱动图19所示像素电路。参考图19和图20，在写入帧，像素电路的工作过程包括先后进行的第二初始化阶段t11、预充阶段t21、第一初始化阶段t1、数据写入阶段t2、重置阶段t3和发光阶段t4。
在第二初始化阶段t11，第一发光控制信号线EM1上的第一发光控制信号为高电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2、第三扫描线S3上的信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，第二晶体管T2响应高电平的第一发光控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，初始化电压还通过第六晶体管T6、第四晶体管T4和第二晶体管T2写入到驱动晶体管DT的栅极，实现对驱动晶体管DT栅极的初始化。
在预充阶段t21，第二扫描线S2上的第二扫描信号为低电平，其他控制信号均为高电平，第一晶体管T1响应低电平的第二扫描信号导通，第二晶体管T2响应高电平的第一发光控制信号导通，预充电压通过第一晶体管T1、驱动晶体管DT和第二晶体管T2写入到驱动晶体管DT的栅极。
在第一初始化阶段t1，像素电路中各晶体管的工作状态与第二初始化阶段t11过程相同，在此不再赘述，
在数据写入阶段t2，第二扫描线S2上的第二扫描信号为低电平，像素电路中其他控制信号为高电平，第一晶体管T1响应低电平的第二扫描信号导通，第二晶体管T2响应高电平的第一发光控制信号导通，数据电压通过第一晶体管 T1、驱动晶体管DT和第二晶体管T2向驱动晶体管DT的栅极写入，同时实现对驱动晶体管DT的阈值电压的补偿。
在重置阶段t3，第三扫描信号为低电平，第一发光控制信号为低电平，像素电路中其他控制信号均为高电平，第五晶体管T5响应低电平的第三扫描信号导通，重置电压VEH通过第五晶体管T5写入到驱动晶体管DT的漏极，并通过驱动晶体管DT写到驱动晶体管DT的源极。
在发光阶段t4，第一发光控制信号和第二发光控制信号为低电平，第三晶体管T3和第四晶体管T4导通，驱动晶体管DT驱动发光器件D1发光。
本实施例的像素电路，基于与图13、图15、图17和图18驱动时序同样的原因，可以提高显示均一性，减轻残影现象，在此不再赘述。
图19所示像素电路在保持帧的驱动时序与图20所示写入帧的驱动时序区别仅在于，在保持帧，第一发光控制信号一直为低电平，其他控制信号与写入帧的相同。图9所示像素电路在保持帧的工作过程包括先后进行的第二初始化阶段t11、第一初始化阶段t1、重置阶段t3和发光阶段t4。
在第二初始化阶段t11，第一发光控制信号线EM1上的第一发光控制信号为低电平，第二发光控制信号线EM2上的第二发光控制信号为低电平，第一扫描线S1上的第一扫描信号为低电平，第二扫描线S2、第三扫描线S3上的信号为高电平。因此，第六晶体管T6响应低电平的第一扫描信号导通，第四晶体管T4响应低电平的第二发光控制信号导通，初始化线Vref上的初始化电压通过第六晶体管T6写入到发光器件D1的阳极，实现对发光器件D1阳极的初始化。同时，第三晶体管T3响应低电平的第一发光控制信号导通，第一电源线VDD与初始化线Vref之间存在大电流，有利于改善残影。
在第一初始化阶段t1、保持帧的重置阶段t3、发光阶段t4分别与图20所示写入帧驱动时序的第一初始化阶段t1、重置阶段t3、发光阶段t4的工作过程相同，在此不再赘述。
在本申请的一可选实施例中，各控制信号(包括数据写入模块的控制端接 入的信号、补偿模块的控制端接入的信号、初始化模块的控制端接入的信号、重置模块的控制端接入的信号、第一发光控制单元的控制端接入的信号和第二发光控制单元的控制端接入的信号)可以由不同的栅极驱动电路提供。在写入帧和保持帧，重置阶段的时长均可调，也即重置模块的控制端接入的信号的有效脉宽可调。可选的，保持帧重置阶段的时长大于写入帧重置阶段的时长。因在写入帧的第一初始化阶段、第二初始化阶段，对驱动晶体管的栅极进行初始化，而在保持帧的第一初始化阶段、第二初始化阶段，不对驱动晶体管的栅极进行初始化。并且写入帧包括数据写入阶段，在数据写入阶段驱动晶体管导通；而保持帧不包括数据写入阶段。因此驱动晶体管特性在写入帧和保持帧存在差异，本实施例中，通过设置保持帧重置阶段的时长大于写入帧重置阶段的时长，可以减小写入帧和保持帧驱动晶体管特性差异，进而有利于显示质量的提升。
在上述各技术方案的基础上，参考图3、图4、图9、图11和图19，可选的，像素电路还包括第一存储模块180，第一存储模块180的第一端连接第一电源线VDD，第一存储模块180的第二端连接驱动模块120的控制端。其中第一存储模块180设置为对驱动模块120的控制端的电位进行存储保持。
继续参考图3、图4、图9、图11和图19，可选的，像素电路还包括第二存储模块190，第二存储模块190的第一端连接第一电源线VDD，第二存储模块190的第二端连接驱动模块120的第一端。
继续参考图5、图7、图10、图13、图15、图17、图18和图20，写入帧还包括亚阈值补偿阶段t5，补偿模块130还设置为在亚阈值补偿阶段t5导通，其中，亚阈值补偿阶段t5介于写入帧的数据写入阶段t2与重置阶段t3之间。
可选的，第一存储模块180包括第一电容，第二存储模块190包括第二电容。
参考图3、图5和图13，在亚阈值补偿阶段t5，补偿控制信号为高电平，其他控制信号也均为高电平，补偿模块130包括的第二晶体管T2响应高电平的 补偿控制信号导通，驱动晶体管DT产生的电流通过第二晶体管T2继续向驱动晶体管DT的栅极充电。
参考图4、图7和图15，在亚阈值补偿阶段t5，第一发光控制信号为高电平，其他控制信号也均为高电平，补偿模块130包括的第二晶体管T2响应高电平的第一发光控制信号导通，驱动晶体管DT产生的电流通过第二晶体管T2继续向驱动晶体管DT的栅极充电。
参考图9、图10和图17，在亚阈值补偿阶段t5，补偿控制信号为高电平，其他控制信号也均为高电平，补偿模块130包括的第二晶体管T2响应高电平的补偿控制信号导通，驱动晶体管DT的电流通过第二晶体管T2继续向驱动晶体管DT的栅极充电。
参考图11、图12和图18，在亚阈值补偿阶段t5，补偿控制信号为高电平，其他控制信号也均为高电平，补偿模块130包括的第二晶体管T2响应高电平的补偿控制信号导通，驱动晶体管DT的电流通过第二晶体管T2继续向驱动晶体管DT的栅极充电。
参考图19和图20，在亚阈值补偿阶段t5，第一发光控制信号为高电平，其他控制信号也均为高电平，补偿模块130包括的第二晶体管T2响应高电平的第一发光控制信号导通，驱动晶体管DT的电流通过第二晶体管T2继续向驱动晶体管DT的栅极充电。
亚阈值摆幅，又称为S因子，亚阈值摆幅在数值上等于为使驱动晶体管DT的源漏极之间的驱动电流变化一个数量级时所需要的栅极电压增量。其中，亚阈值摆幅的大小影响驱动晶体管DT产生的驱动电流大小，对于亚阈值摆幅不同的两个驱动晶体管DT，栅源电压差相同时，驱动晶体管DT产生的驱动电流大小不同，其中栅源电压差相同时，亚阈值摆幅越大的，在设定灰阶下驱动晶体管DT产生的驱动电流越大，其中，设定灰阶可以对应驱动晶体管DT产生的驱动电流小于设定电流阈值时的灰阶范围。因此亚阈值摆幅不一致同样会影响到显示面板的显示均匀性。本实施例的像素电路，通过设置像素电路还包括第二 存储模块190，该第二存储模块190在亚阈值摆幅补偿阶段，对驱动模块120的第一端(驱动晶体管DT的第一极)电位进行保持，因亚阈值摆幅补偿阶段在数据写入阶段t2之后，且数据写入模块110与驱动晶体管DT的第一极电连接，因此在亚阈值摆幅补偿阶段，第二存储模块190保持驱动晶体管DT第一极的数据电压。补偿模块130在亚阈值摆幅补偿阶段导通，使得驱动晶体管DT产生的电流继续为驱动晶体管DT的栅极充电，在亚阈值摆幅补偿阶段，驱动晶体管DT的栅极电位变化量记为ΔV。因在数据写入阶段t2完成之后，驱动晶体管DT的栅极电位为Vdata+Vth，则亚阈值摆幅补偿阶段后，驱动晶体管DT的栅极电位为Vdata+Vth+ΔV。因设定灰阶下，驱动晶体管DT的亚阈值摆幅越大，驱动晶体管DT自身的电流越大，在亚阈值摆幅补偿阶段驱动晶体管DT的栅极电位变化量ΔV越大。根据驱动晶体管DT的驱动电流计算公式：
其中，μ表示载流子迁移率，Cox为栅氧化层电容(栅极氧化物单位面积上电容)，W/L为驱动晶体管DT的宽长比，Vgs表示驱动晶体管DT的栅极与第一极的电压差，Vth表示驱动晶体管DT的阈值电压，Vdata表示数据电压，Vdd表示第一电源电压输入端输入的第一电源电压。
以驱动晶体管DT为P型晶体管为例，数据电压和第一电源线VDD上的第一电源电压电压均为正电压，数据电压小于第一电源电压，因此Vdata-Vdd<0。而因数据电压为正电压，因此在亚阈值摆幅阶段，驱动晶体管DT的栅极电压逐渐升高，即ΔV>0，根据上述驱动电流计算公式，数据电压不变时，栅极电位变化量ΔV越大，|Vdata-Vdd+ΔV|的绝对值越小，则驱动电流会越小。因此通过在亚阈值摆幅补偿阶段对亚阈值摆幅的补偿，使得在设定灰阶时，相同数据电压下，亚阈值摆幅越大的驱动晶体管DT产生的驱动晶体管DT电流被减小地越多， 进而使得在设定灰阶时的相同数据电压下，不同亚阈值摆幅的驱动晶体管DT的驱动电流趋于一致，减轻设定灰阶下显示面板中因驱动晶体管DT亚阈值摆幅不同带来的显示不均。对于驱动晶体管DT为N型晶体管时，工作原理与上述P型驱动晶体管DT的原理类似，在此不再赘述。
本申请实施例还提供了一种像素电路的驱动方法，图21是本申请实施例提供的一种像素电路的驱动方法的流程图，参考图21，该像素电路的驱动方法包括：
步骤210、在写入帧，数据写入模块在数据写入阶段向驱动模块的控制端写入数据电压，补偿模块在写入帧的数据写入阶段对驱动模块的阈值电压进行补偿；重置模块在重置阶段将驱动模块的第一端和第二端的电位重置为固定的重置电压，发光控制模块在发光阶段导通，驱动模块在发光阶段驱动发光模块发光。
其中，在写入帧，重置阶段介于数据写入阶段和发光阶段之间。
示例性的，在写入帧的数据写入阶段，通过与数据写入模块的控制端连接的控制信号线向数据写入模块的控制端输入有效信号，使得数据写入模块在写入帧的数据写入阶段导通，使得数据写入模块向驱动模块的控制端写入数据电压；在写入帧的数据写入阶段，通过与补偿模块的控制端连接的控制信号线向补偿模块的控制端输入有效信号，使得补偿模块在写入帧的数据写入阶段导通，补偿模块在写入帧的数据写入阶段对驱动模块的阈值电压进行补偿。
在写入帧的重置阶段，通过与重置模块的控制端连接的控制信号线向重置模块的控制端输入有效信号，使得重置模块在写入帧的重置阶段导通，使得重置模块在重置阶段将驱动模块的第一端和第二端的电位重置为固定的重置电压。
在写入帧的发光阶段，通过与发光控制模块的控制端连接的控制信号线向发光控制模块的控制端输入有效信号，使得发光控制模块在写入帧的发光阶段导通，驱动模块在发光阶段驱动发光模块发光。
步骤220、在保持帧，重置模块在重置阶段将驱动模块的第一端和第二端的电位重置为固定的重置电压，发光控制模块在发光阶段导通，驱动模块在发光阶段驱动发光模块发光。
其中，在保持帧，重置阶段在发光阶段之前。
在保持帧的重置阶段，通过与重置模块的控制端连接的控制信号线向重置模块的控制端输入有效信号，使得重置模块在保持帧的重置阶段导通，使得重置模块在重置阶段将驱动模块的第一端和第二端的电位重置为固定的重置电压。
在保持帧的发光阶段，通过与发光控制模块的控制端连接的控制信号线向发光控制模块的控制端输入有效信号，使得发光控制模块在保持帧的发光阶段导通，驱动模块在发光阶段驱动发光模块发光。
该驱动方法用于驱动本申请上述任意实施例的像素电路，在此不再赘述。
在上述技术方案的基础上，可选的，发光控制模块包括第一发光控制单元和第二发光控制单元，像素电路还包括初始化模块；图22是本申请实施例提供的一种像素电路的在写入帧的驱动方法的流程图。
参考图22，像素电路的在写入帧的驱动方法包括：
步骤310、在第二初始化阶段，初始化模块导通，将初始化电压写入到发光模块的第一端和驱动模块的控制端。
第二发光控制单元和补偿模块在第二初始化阶段导通，初始化电压通过初始化模块、第二发光控制单元和补偿模块写入到驱动模块的控制端。
在第二初始化阶段，通过与初始化模块控制端所连接的控制信号线向初始化模块的控制端输入有效信号，使得初始化模块导通，将初始化电压写入到发光模块的第一端。通过与第二发光控制单元的控制端连接的控制信号线向第二发光控制单元的控制端输入有效信号，使得第二发光控制单元导通；通过与补偿模块的控制端连接的控制信号线向补偿模块的控制端输入有效信号，使得补偿模块导通，使得初始化电压通过初始化模块、第二发光控制单元和补偿模块 写入到驱动模块的控制端。
步骤320、在预充阶段，数据写入模块向驱动模块的控制端写入预充电压。可选的，预充电压为像素电路同列中的上n行像素电路对应的数据电压，n≥2。
在预充阶段，通过数据写入模块的控制端连接的控制信号线向数据写入模块的控制端输入有效信号，使得数据写入模块导通，同时通过补偿模块的控制端连接的控制信号线向补偿模块的控制端输入有效信号，使得补偿模块导通，预充电压通过数据写入模块、驱动模块和补偿模块写入到驱动模块的控制端。
步骤330、在第一初始化阶段，初始化模块导通，将初始化电压写入到发光模块的第一端和驱动模块的控制端。
第二发光控制单元和补偿模块在第一初始化阶段导通，初始化电压通过初始化模块、第二发光控制单元和补偿模块写入到驱动模块的控制端。
在第一初始化阶段，通过与初始化模块控制端所连接的控制信号线向初始化模块的控制端输入有效信号，使得初始化模块导通，将初始化电压写入到发光模块的第一端。通过与第二发光控制单元的控制端连接的控制信号线向第二发光控制单元的控制端输入有效信号，使得第二发光控制单元导通；通过与补偿模块的控制端连接的控制信号线向补偿模块的控制端输入有效信号，使得补偿模块导通，使得初始化电压通过初始化模块、第二发光控制单元和补偿模块写入到驱动模块的控制端。
步骤340、在数据写入阶段，数据写入模块向驱动模块的控制端写入数据电压，补偿模块在对驱动模块的阈值电压进行补偿。
在数据写入阶段，通过与数据写入模块的控制端连接的控制信号线向数据写入模块的控制端输入有效信号，使得数据写入模块在写入帧的数据写入阶段导通，使得数据写入模块向驱动模块的控制端写入数据电压；在数据写入阶段，通过与补偿模块的控制端连接的控制信号线向补偿模块的控制端输入有效信号，使得补偿模块在写入帧的数据写入阶段导通，补偿模块在写入帧的数据写入阶段对驱动模块的阈值电压进行补偿。
步骤350、在重置阶段，重置模块将驱动模块的第一端和第二端的电位重置为固定的重置电压。
在重置阶段，通过与重置模块的控制端连接的控制信号线向重置模块的控制端输入有效信号，使得重置模块在重置阶段导通，使得重置模块在重置阶段将驱动模块的第一端和第二端的电位重置为固定的重置电压。
步骤360、在发光阶段，发光控制模块导通，驱动模块驱动发光模块发光。
在发光阶段，通过与发光控制模块的控制端连接的控制信号线向发光控制模块的控制端输入有效信号，使得发光控制模块在发光阶段导通，驱动模块在发光阶段驱动发光模块发光。
其中，在写入帧，第二初始化阶段在第一初始化阶段之前，预充阶段介于第一初始化阶段和第二初始化阶段之间，数据写入阶段在第一初始化阶段后。
图23是本申请实施例提供的一种像素电路的在保持帧的驱动方法的流程图，参考图23，像素电路的在保持帧的驱动方法包括：
步骤410、在第二初始化阶段，初始化模块将初始化电压写入到发光模块的第一端。
在第二初始化阶段，通过与初始化模块控制端所连接的控制信号线向初始化模块的控制端输入有效信号，使得初始化模块导通，将初始化电压写入到发光模块的第一端。
步骤420、在第一初始化阶段，初始化模块将初始化电压写入到发光模块的第一端。
在第一初始化阶段，通过与初始化模块控制端所连接的控制信号线向初始化模块的控制端输入有效信号，使得初始化模块导通，将初始化电压写入到发光模块的第一端。
步骤430、在重置阶段，重置模块将驱动模块的第一端和第二端的电位重置为固定的重置电压。
在重置阶段，通过与重置模块的控制端连接的控制信号线向重置模块的控制端输入有效信号，使得重置模块在重置阶段导通，使得重置模块在重置阶段将驱动模块的第一端和第二端的电位重置为固定的重置电压。
步骤440、在发光阶段，发光控制模块导通，驱动模块驱动发光模块发光。
在发光阶段，通过与发光控制模块的控制端连接的控制信号线向发光控制模块的控制端输入有效信号，使得发光控制模块在发光阶段导通，驱动模块在发光阶段驱动发光模块发光。

Claims (19)

  1. 一种像素电路，包括：数据写入模块、驱动模块、补偿模块、发光控制模块和发光模块；
    所述数据写入模块设置为在写入帧的数据写入阶段向驱动模块的控制端写入数据电压；
    所述补偿模块设置为在所述写入帧的数据写入阶段对所述驱动模块的阈值电压进行补偿；
    所述发光控制模块设置为在写入帧和保持帧的发光阶段导通，所述驱动模块设置为在所述发光阶段驱动所述发光模块发光；
    所述像素电路还包括重置模块，所述重置模块与所述驱动模块的第一端或第二端电连接，所述重置模块设置为在重置阶段将所述驱动模块的第一端和第二端的电位重置为固定的重置电压；
    在所述写入帧，所述重置阶段介于所述数据写入阶段和所述发光阶段之间；在所述保持帧，所述重置阶段在所述发光阶段之前。
  2. 根据权利要求1所述的像素电路，其中，所述发光控制模块包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元串联在第一电源线与所述驱动模块的第一端之间；所述第二发光控制单元串联在所述驱动模块的第二端与所述发光模块的第一端之间，所述发光模块的第二端与第二电源线电连接；
    所述数据写入模块的第一端与数据线电连接，所述数据写入模块的第二端与所述驱动模块的第一端电连接。
  3. 根据权利要求2所述的像素电路，其中，所述重置模块包括所述第一发光控制单元和所述数据写入模块；所述数据线设置为在所述写入帧的数据写入阶段传输所述数据电压，以及在所述保持帧的重置阶段传输第一电源电压；
    所述第一发光控制单元设置为在所述写入帧的重置阶段，将所述第一电源电压写入到所述驱动模块的第一端和第二端；
    所述数据写入模块设置为在所述保持帧的重置阶段，将所述第一电源电压 写入到所述驱动模块的第一端和第二端；
    或者，所述重置模块的第一端接入所述重置电压，所述重置模块的第二端与所述驱动模块的第二端电连接，所述重置模块设置为在自身控制端接入信号的控制下，在所述重置阶段将所述重置电压写入所述驱动模块的第一端和第二端。
  4. 根据权利要求3所述的像素电路，其中，所述驱动模块包括驱动晶体管，所述驱动晶体管为P型晶体管，所述重置电压大于所述数据电压。
  5. 根据权利要求3所述的像素电路，其中，还包括初始化模块，
    所述初始化模块设置为在所述写入帧的第一初始化阶段，将初始化电压写入到所述发光模块的第一端和所述驱动模块的控制端；在所述写入帧，所述第一初始化阶段在所述数据写入阶段之前；
    所述初始化模块还设置为在所述保持帧的第一初始化阶段，将所述初始化电压写入到所述发光模块的第一端；在所述保持帧，所述第一初始化阶段在所述重置阶段之前。
  6. 根据权利要求5所述的像素电路，其中，所述初始化模块还设置为在写入帧的第二初始化阶段，将初始化电压写入到所述发光模块的第一端和所述驱动模块的控制端；所述第二初始化阶段在所述第一初始化阶段之前进行。
  7. 根据权利要求6所述的像素电路，其中，所述写入帧还包括预充阶段，所述数据写入模块还设置为在写入帧的预充阶段，向所述驱动模块的控制端写入预充电压；所述预充电压为所述像素电路同列中的上n行像素电路对应的数据电压，n≥2；在写入帧，所述预充阶段介于所述第二初始化阶段和所述第一初始化阶段之间，所述数据写入阶段在所述第一初始化阶段之后。
  8. 根据权利要求6所述的像素电路，其中，所述初始化模块还设置为在所述保持帧的第二初始化阶段导通，在保持帧，所述第二初始化阶段在所述第一初始化阶段之前。
  9. 根据权利要求5所述的像素电路，其中，所述初始化模块的控制端连接 第一扫描线，所述数据写入模块的控制端连接第二扫描线，所述第一扫描线、所述第二扫描线连接相同的扫描驱动电路。
  10. 根据权利要求9所述的像素电路，其中，所述重置模块的控制端连接第三扫描线，所述第一扫描线、所述第二扫描线和所述第三扫描线连接相同的扫描驱动电路。
  11. 根据权利要求2-10任一项所述的像素电路，其中，还包括第一存储模块，所述第一存储模块的第一端连接所述第一电源线，所述第一存储模块的第二端连接所述驱动模块的控制端；
    所述像素电路还包括第二存储模块，所述第二存储模块的第一端连接所述第一电源线，所述第二存储模块的第二端连接所述驱动模块的第一端；
    所述写入帧还包括亚阈值补偿阶段，所述补偿模块还设置为所述亚阈值补偿阶段导通，所述亚阈值补偿阶段介于所述写入帧的所述数据写入阶段与所述重置阶段之间。
  12. 根据权利要求2-10任一项所述的像素电路，其中，所述第一发光控制单元的控制端连接第一发光控制线，所述第二发光控制单元的控制端连接第二发光控制线；
    所述补偿模块连接在所述驱动模块的第二端与所述驱动模块的控制端之间，所述补偿模块的控制端连接所述第一发光控制线；所述第一发光控制单元所包括的晶体管与所述补偿模块所包括的晶体管的沟道类型相反；
    或者，所述重置模块的第一端接入所述重置电压，所述重置模块的第二端与所述驱动模块的第二端电连接；所述补偿模块连接在所述驱动模块的第二端与所述驱动模块的控制端之间，所述补偿模块的控制端连接补偿控制信号线。
  13. 根据权利要求3所述的像素电路，其中，所述重置模块的第一端接入所述重置电压，所述重置模块的第二端与所述驱动模块的第二端电连接；所述第一发光控制单元的控制端和所述第二发光控制单元的控制端与同一发光控制线电连接，所述补偿模块的控制端与补偿控制信号线电连接。
  14. 根据权利要求3所述的像素电路，其中，所述重置模块的第一端接入所述重置电压，所述重置模块的第二端与所述驱动模块的第二端电连接；所述像素电路还包括初始化模块；所述第一发光控制单元的控制端连接第一发光控制线，所述第二发光控制单元的控制端连接第二发光控制线；
    所述补偿模块连接在所述驱动模块的第二端与所述驱动模块的控制端之间，所述补偿模块的控制端连接补偿控制信号线；
    所述初始化模块的控制端连接所述第一发光控制线，所述第一发光控制单元所包括的晶体管与所述初始化模块所包括的晶体管的沟道类型相反；
    所述数据写入模块的控制端连接第一扫描线，所述重置模块的控制端连接第二扫描线。
  15. 根据权利要求14所述的像素电路，其中，所述第一扫描线和所述第二扫描线连接相同的扫描驱动电路。
  16. 一种像素电路的驱动方法，包括：
    在写入帧，数据写入模块在数据写入阶段向驱动模块的控制端写入数据电压，补偿模块在所述写入帧的数据写入阶段对所述驱动模块的阈值电压进行补偿；重置模块在重置阶段将所述驱动模块的第一端和第二端的电位重置为固定的重置电压，发光控制模块在发光阶段导通，驱动模块在所述发光阶段驱动所述发光模块发光；
    在保持帧，重置模块在重置阶段将所述驱动模块的第一端和第二端的电位重置为固定的重置电压，发光控制模块在发光阶段导通，驱动模块在所述发光阶段驱动所述发光模块发光；
    在所述写入帧，所述重置阶段介于所述数据写入阶段和所述发光阶段之间；在所述保持帧，所述重置阶段在所述发光阶段之前。
  17. 根据权利要求16所述的像素电路的驱动方法，其中，所述发光控制模块包括第一发光控制单元和第二发光控制单元，所述像素电路还包括初始化模块；所述驱动方法还包括：
    在所述写入帧，初始化模块在第一初始化阶段和第二初始化阶段，将初始化电压写入到所述发光模块的第一端和所述驱动模块的控制端。
  18. 根据权利要求17所述的像素电路的驱动方法，其中，所述写入帧还包括预充阶段，所述驱动方法还包括：
    所述数据写入模块在写入帧的预充阶段，向所述驱动模块的控制端写入预充电压；
    在写入帧，所述第二初始化阶段在所述第一初始化阶段之前，所述预充阶段介于所述第一初始化阶段和所述第二初始化阶段之间，所述数据写入阶段在所述第一初始化阶段后。
  19. 根据权利要求17所述的像素电路的驱动方法，其中，还包括：
    在所述保持帧，所述初始化模块在第一初始化阶段和第二初始化阶段，将初始化电压写入到所述发光模块的第一端。
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