WO2024066278A1 - 沟槽电容器封装结构及其制备方法、半导体结构 - Google Patents

沟槽电容器封装结构及其制备方法、半导体结构 Download PDF

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Publication number
WO2024066278A1
WO2024066278A1 PCT/CN2023/086127 CN2023086127W WO2024066278A1 WO 2024066278 A1 WO2024066278 A1 WO 2024066278A1 CN 2023086127 W CN2023086127 W CN 2023086127W WO 2024066278 A1 WO2024066278 A1 WO 2024066278A1
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Prior art keywords
layer
electrode
substrate
exposed
target
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PCT/CN2023/086127
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English (en)
French (fr)
Inventor
高远皓
王春阳
陈军
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长鑫存储技术有限公司
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Publication of WO2024066278A1 publication Critical patent/WO2024066278A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a trench capacitor packaging structure and a preparation method thereof, and a semiconductor structure.
  • trench capacitors such as deep trench capacitors (DTC)
  • DTC dynamic random access memory
  • DRAM dynamic random access memory
  • Some embodiments of the present disclosure provide a trench capacitor packaging structure, including: a substrate, a trench capacitor, and a transition structure.
  • the substrate has a trench.
  • the trench capacitor is located on one side of the substrate and fills the trench.
  • the trench capacitor includes: a plurality of stacked electrode layers and a dielectric layer located between any two adjacent electrode layers. Any layer structure from the substrate to the top dielectric layer constitutes a target layer.
  • the top surfaces of the electrode layer and the dielectric layer located on the side of the target layer away from the substrate are located in the same plane as the top surface of the target layer.
  • the top surface of the electrode layer located on the side of the target layer away from the substrate constitutes an exposed electrode.
  • the transition structure is arranged on the side of the trench capacitor away from the substrate, and is at least correspondingly connected to the exposed electrode.
  • the target layer is the substrate.
  • the top surface of each electrode layer is located in the same plane as the top surface of the substrate and constitutes an exposed electrode.
  • the transfer structure is connected to the exposed electrodes of each electrode layer respectively.
  • the trench capacitor packaging structure further includes: a functional layer.
  • the functional layer is located between the substrate and the trench capacitor and covers the substrate surface and the inner wall surface of the trench.
  • the target layer is the functional layer.
  • the top surface of each electrode layer is located in the same plane as the top surface of the functional layer and constitutes an exposed electrode.
  • the transfer structure is connected to the exposed electrodes of each electrode layer respectively.
  • the target layer is any dielectric layer.
  • the edge portion of the electrode layer located on the side of the target layer close to the substrate is arranged in a stepped structure with the target layer in at least one direction.
  • the transfer structure is also connected to the edge portion of the electrode layer in the stepped structure.
  • the thickness of the electrode layer located on a side of the target layer facing away from the substrate is greater than the thickness of the electrode layer located on a side of the target layer close to the substrate.
  • the target layer is any electrode layer other than the top electrode layer.
  • the edge portion of the electrode layer located on the side of the target layer close to the substrate is arranged in a stepped structure with the target layer in at least one direction.
  • the transfer structure is also connected to the edge portion of the electrode layer in the stepped structure.
  • the thickness of the target layer is greater than the thickness of the other electrode layers.
  • the trench capacitor packaging structure further includes: a first dielectric layer and a second dielectric layer.
  • the first dielectric layer at least covers the trench capacitor and has a plurality of first redistribution holes.
  • the second dielectric layer covers the first dielectric layer and has a plurality of second redistribution holes.
  • the second redistribution holes are correspondingly connected to the first redistribution holes.
  • the transfer structure is disposed in the first redistribution holes and the second redistribution holes and is correspondingly connected to each electrode layer.
  • the transfer structure includes: at least two contact structures; wherein each contact structure is respectively connected to at least one electrode layer.
  • some embodiments of the present disclosure provide a method for preparing a trench capacitor packaging structure, comprising the following steps.
  • a substrate is provided, the substrate having a groove.
  • An initial capacitor is formed on one side of the substrate and in the groove.
  • the initial capacitor includes: a plurality of stacked electrode layers and a dielectric layer between any two adjacent electrode layers.
  • the initial capacitor is polished to expose the target layer and form at least one exposed electrode; wherein the target layer is selected from any layer structure from the substrate to the top dielectric layer, and the exposed electrode is formed based on at least one electrode layer on the side of the target layer facing away from the substrate.
  • a switching structure is formed, and the switching structure is at least correspondingly connected to the exposed electrode.
  • the target layer is a substrate.
  • the forming of the initial capacitor on one side of the substrate and in the groove includes: forming alternately stacked electrode material layers and dielectric material layers on the surface of the substrate.
  • the polishing of the initial capacitor until the target layer is exposed and at least one exposed electrode is formed includes: polishing the initial capacitor until the substrate is exposed, so that the retained portions of each electrode material layer respectively form an electrode layer, and the retained portions of each dielectric material layer respectively form a dielectric layer; wherein the polished surface of each electrode layer is exposed to form a plurality of exposed electrodes.
  • the preparation method before forming the initial capacitor on one side of the substrate and in the groove, further includes: forming a functional layer on the surface of the substrate and the inner wall of the groove. Forming the initial capacitor on one side of the substrate and in the groove also includes: forming alternately stacked electrode material layers and dielectric material layers on the surface of the functional layer facing away from the substrate.
  • the target layer is a functional layer.
  • the polishing of the initial capacitor until the target layer is exposed and at least one exposed electrode is formed includes: polishing the initial capacitor until the functional layer is exposed, so that the retained portions of each electrode material layer respectively form an electrode layer, and the retained portions of each dielectric material layer respectively form a dielectric layer; wherein the polished surface of each electrode layer is exposed to form a plurality of exposed electrodes.
  • the preparation method further includes: forming a first dielectric layer covering each exposed electrode and the target layer.
  • the forming of the transfer structure includes the following steps.
  • the first dielectric layer is patterned to form a plurality of first redistribution holes; and a plurality of exposed electrodes are respectively exposed in the corresponding first redistribution holes.
  • a sacrificial layer filling the first redistribution holes is formed.
  • a second dielectric layer is formed to cover the sacrificial layer and the first dielectric layer.
  • the second dielectric layer is patterned to form a plurality of second redistribution holes; the sacrificial layer is exposed in the second redistribution holes.
  • the sacrificial layer is removed to connect the second redistribution holes to the first redistribution holes.
  • a transfer structure is formed in the second redistribution holes and the first redistribution holes; the transfer structure is respectively connected to the exposed electrodes exposed in each of the first redistribution holes.
  • the forming of the initial capacitor on one side of the substrate and in the trench includes the following steps.
  • Electrode material layers and dielectric material layers are alternately stacked on one side of the substrate.
  • Each electrode material layer and each dielectric material layer is patterned to form a multi-layer initial electrode layer and a multi-layer initial dielectric layer that at least fills the groove.
  • the target layer is any dielectric layer, and the edge portion of the electrode layer on the side of the target layer close to the substrate is arranged in a stepped structure with the target layer in at least one direction; or, the target layer is any electrode layer other than the top electrode layer, and when the target layer is not the first electrode layer, the edge portion of the electrode layer on the side of the target layer close to the substrate is arranged in a stepped structure with the target layer in at least one direction.
  • the target layer is any dielectric layer.
  • the electrode layer on the side of the target layer facing away from the substrate is formed to have a thickness greater than the electrode layer on the side of the target layer close to the substrate.
  • the target layer is any dielectric layer.
  • Each initial electrode layer located on the side of the target layer away from the substrate and the initial electrode layer located on the side of the target layer close to the substrate and adjacent to the target layer are patterned using the same mask.
  • the target layer is any electrode layer other than the top electrode layer.
  • the target layer is formed with a thickness greater than that of other electrode layers.
  • the preparation method further includes: forming a first dielectric layer covering at least the stepped structure, the target layer and the exposed electrode.
  • the forming of the transfer structure includes the following steps.
  • the first dielectric layer is patterned to form a plurality of first redistribution holes.
  • the bare electrodes and the edge portions of each electrode layer in the stepped structure are respectively exposed in the corresponding first redistribution holes.
  • a sacrificial layer filling the first redistribution holes is formed.
  • a second dielectric layer is formed to cover the sacrificial layer and the first dielectric layer.
  • the second dielectric layer is patterned to form a plurality of second redistribution holes, and the sacrificial layer is exposed in the second redistribution holes.
  • the sacrificial layer is removed to connect the second redistribution holes to the first redistribution holes.
  • a transfer structure is formed in the second redistribution hole and the first redistribution hole, and the transfer structure is correspondingly connected to the exposed electrode and the edge portion of each electrode layer in the stepped structure.
  • the target layer is any dielectric layer.
  • a portion of the target layer is also exposed in the first redistribution hole corresponding to the target exposed electrode.
  • the target exposed electrode is located on a side of the target layer away from the substrate and adjacent to the target layer.
  • some embodiments of the present disclosure provide a semiconductor structure, including: a trench capacitor packaging structure as described in any of the above embodiments.
  • FIG1 is a schematic structural diagram of a trench capacitor packaging structure provided in one embodiment
  • FIG2 is a schematic structural diagram of another trench capacitor packaging structure provided in an embodiment
  • FIG3 is a schematic structural diagram of another trench capacitor packaging structure provided in an embodiment
  • FIG4 is an enlarged schematic diagram of a trench capacitor provided in one embodiment
  • FIG5 is a schematic structural diagram of another trench capacitor packaging structure provided in an embodiment
  • FIG6 is an enlarged schematic diagram of another trench capacitor provided in one embodiment
  • FIG7 is a schematic flow diagram of a method for preparing a trench capacitor packaging structure provided in an embodiment
  • FIG8 is a schematic flow diagram of another method for preparing a trench capacitor packaging structure provided in an embodiment
  • FIG9 is a schematic diagram of a structure obtained after forming an initial capacitor provided in one embodiment
  • FIG10 is a schematic structural diagram of a structure obtained after forming a bare electrode provided in an embodiment
  • FIG11 is a schematic flow chart of a method for preparing a transfer structure provided in an embodiment
  • FIG12 is a schematic structural diagram of a structure obtained after forming a first dielectric layer provided in an embodiment
  • FIG13 is a schematic structural diagram of a structure obtained after forming a first photoresist layer provided in an embodiment
  • FIG14 is a schematic structural diagram of a structure obtained after forming first redistribution holes provided in one embodiment
  • FIG15 is a schematic structural diagram of a structure obtained after forming a sacrificial layer provided in one embodiment
  • FIG16 is a schematic structural diagram of a structure obtained after forming a second dielectric layer provided in an embodiment
  • FIG17 is a schematic structural diagram of a structure obtained after forming a second photoresist layer provided in one embodiment
  • FIG18 is a schematic structural diagram of a structure obtained after forming second redistribution holes provided in one embodiment
  • FIG19 is a schematic diagram of a structure obtained after removing a sacrificial layer provided in an embodiment
  • FIG20 is a schematic structural diagram of a structure obtained after forming a transfer structure material layer provided in an embodiment
  • FIG21 is a schematic structural diagram of a structure obtained after forming a transfer structure provided in an embodiment
  • FIG22 is a schematic flow chart of another method for preparing an initial capacitor provided in an embodiment
  • FIG23 is a schematic flow chart of another method for preparing a transfer structure provided in an embodiment
  • FIG24 is a schematic diagram of a structure obtained after alternately stacking dielectric material layers and electrode material layers provided in one embodiment
  • FIG25 is a schematic structural diagram of a structure obtained after forming a third photoresist layer provided in an embodiment
  • FIG26 is a schematic diagram of a structure obtained after forming an initial electrode layer and an initial dielectric layer provided in one embodiment
  • FIG27 is a schematic structural diagram of a structure obtained after forming a first covering material layer provided in an embodiment
  • FIG28 is a schematic structural diagram of a structure obtained after forming a first initial covering layer provided in an embodiment
  • FIG29 is a schematic structural diagram of a structure obtained after forming a fourth photoresist layer provided in an embodiment
  • FIG30 is a schematic structural diagram of a structure obtained after forming a first covering layer provided in an embodiment
  • FIG31 is a schematic structural diagram of a structure obtained after forming a second covering layer provided in one embodiment
  • FIG32 is a schematic diagram of a structure obtained after forming a bare electrode provided in one embodiment
  • FIG33 is a schematic structural diagram of a structure obtained after forming a second sub-dielectric layer provided in an embodiment
  • FIG34 is a schematic structural diagram of a structure obtained after forming a fifth photoresist layer provided in one embodiment
  • FIG35 is a schematic diagram of another structure obtained after forming first redistribution holes provided in an embodiment
  • FIG36 is a schematic diagram of another structure obtained after forming a sacrificial layer provided in an embodiment
  • FIG37 is a schematic structural diagram of another structure obtained after forming a second dielectric layer provided in an embodiment
  • FIG38 is a schematic structural diagram of a structure obtained after forming a sixth photoresist layer provided in an embodiment
  • FIG39 is a schematic structural diagram of another structure obtained after forming second redistribution holes provided in one embodiment.
  • FIG40 is a schematic structural diagram of another structure obtained after forming a transfer structure material layer provided in an embodiment
  • FIG. 41 is a schematic diagram of another structure obtained after forming a transfer structure provided in an embodiment.
  • first, second, etc. can be used to describe various elements, components, regions, layers, doping types and/or parts, these elements, components, regions, layers, doping types and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
  • spatially relative terms such as “under,” “beneath,” “below,” “under,” “above,” “above,” and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as “under other elements” or “under it” or “under it” will be oriented as being “above” the other elements or features. Thus, the exemplary terms “under” and “under” may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances are anticipated.
  • embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques.
  • the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.
  • Trench capacitors especially deep trench capacitors (DTC) have a high capacitance per unit and can be widely used in various memory devices or semiconductor integrated circuits (ICs).
  • Trench capacitors usually include multiple electrode layers arranged in the trench, and a dielectric layer located between adjacent electrode layers. In this way, each electrode layer located in different layers in the trench capacitor needs to be transferred and packaged, so that the transfer packaging of the trench capacitor often relies on multiple mask processes. For example, it is necessary to cut the corresponding electrode layers separately through different masks so that each electrode layer is exposed separately, and then transfer and package each electrode layer. Therefore, the transfer packaging of the trench capacitor requires a large number of masks, resulting in high production costs and low production efficiency.
  • the embodiments of the present disclosure provide a trench capacitor packaging structure and a preparation method thereof, and a semiconductor structure, which can reduce the number of masks during trench capacitor transfer packaging, thereby reducing production costs and improving production efficiency.
  • some embodiments of the present disclosure provide a trench capacitor packaging structure, including: a substrate 10, a trench capacitor C, and a transfer structure 30.
  • the substrate 10 has a trench G.
  • the trench capacitor C is located on one side of the substrate 10 and fills the trench G.
  • the trench capacitor C includes: a stacked multilayer electrode layer 21 and a dielectric layer 22 located between any two adjacent electrode layers 21; wherein any layer structure from the substrate 10 to the top dielectric layer 22 constitutes a target layer M; the top surfaces of the electrode layer 21 and the dielectric layer 22 located on the side of the target layer M away from the substrate 10 are located in the same plane as the top surface of the target layer M; the top surface of the electrode layer 21 located on the side of the target layer M away from the substrate 10 constitutes an exposed electrode E.
  • the transfer structure 30 is disposed on the side of the trench capacitor C away from the substrate 10, and is at least correspondingly connected to the exposed electrode E.
  • any layer structure from the substrate 10 to the top dielectric layer 22 includes: the substrate 10, any dielectric layer 22, any electrode layer 21 other than the top electrode layer 21, or any thin film structure arranged on the surface of the substrate 10, such as a functional layer.
  • the top dielectric layer 22 refers to the dielectric layer 22 stacked on the outermost layer in the direction away from the substrate 10, and the dielectric layer 22 is also located at the center of the groove G.
  • the top electrode layer 21 refers to the electrode layer 21 stacked on the outermost layer in the direction away from the substrate 10, and the electrode layer 21 is also located at the center of the groove G.
  • the top dielectric layer 22 is located on the side of the top electrode layer 21 close to the substrate 10 (including the inner wall surface of the groove G).
  • top surface refers to the surface of each corresponding layer structure parallel to the upper surface of the substrate 10.
  • the top surface of the electrode layer 21 and the dielectric layer 22 located on the side of the target layer M away from the substrate 10 are located in the same plane as the top surface of the target layer M, which means that the top surface of the electrode layer 21 and the dielectric layer 22 located on the side of the target layer M away from the substrate 10 can be obtained by polishing to the top surface of the target layer M; that is, the "top surface” can be the polished surface of the corresponding layer structure.
  • the electrode layer 21 includes a polysilicon layer, a metal layer or a metal compound layer.
  • the material of the metal layer or the metal compound layer includes titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), copper (Cu) or aluminum (Al).
  • dielectric layer 22 comprises a high-K dielectric layer.
  • the material of dielectric layer 22 includes, but is not limited to, aluminum oxide ( Al2O3 ), hafnium oxide ( HfO2 ), hafnium oxynitride (HfON), zirconium oxide ( ZrO2 ) , tantalum oxide ( Ta2O5 ), titanium oxide ( TiO2 ), or strontium titanium oxide ( SrTiO3 ).
  • the number and thickness of the electrode layers 21 and the dielectric layers 22 can be set according to actual needs.
  • the thickness of each electrode layer 21 is the same or different, and the thickness of each dielectric layer 22 is the same or different.
  • any layer structure from the substrate 10 to the top dielectric layer 22 can be selected as the target layer M, and then the top surface of the electrode layer 21 located on the side of the target layer M away from the substrate 10 is directly formed into an exposed electrode E through a polishing process.
  • the top surfaces of the electrode layer 21 and the dielectric layer 2 located on the side of the target layer M away from the substrate 10 are located in the same plane as the top surface of the target layer M, and the top surface of the electrode layer 21 located on the side of the target layer M away from the substrate 10 constitutes the exposed electrode E, which can ensure that the electrode layer 21 located on the side of the target layer M away from the substrate 10 does not need to be patterned using a mask, and can also have an exposed electrode E.
  • This facilitates the subsequent direct formation of a transfer structure 30 on the surface of the aforementioned exposed electrode E, so that the transfer structure 30 is at least connected to the exposed electrode E.
  • the total number of masks during the transfer packaging of the trench capacitor can be reduced, which is conducive to reducing production costs and improving production efficiency.
  • the trench capacitor packaging structure further includes: a first dielectric layer 41 and a second dielectric layer 42.
  • the first dielectric layer 41 at least covers the trench capacitor C and has a plurality of first redistribution holes H1.
  • the second dielectric layer 42 covers the first dielectric layer 41 and has a plurality of second redistribution holes H2.
  • the second redistribution holes H2 are correspondingly connected to the first redistribution holes H1, and the transfer structure 30 is disposed in the first redistribution holes H1 and the second redistribution holes H2, and is respectively connected to each electrode layer 21.
  • the materials of the first dielectric layer 41 and the second dielectric layer 42 can be the same, for example, including oxides, such as silicon dioxide. In this way, it is not only convenient for preparation, but also convenient to etch the first dielectric layer 41 and the second dielectric layer 42 using the same process to form a desired pattern (i.e., the corresponding redistribution holes). Of course, it is also allowed that the materials of the first dielectric layer 41 and the second dielectric layer 42 are different.
  • the material of the first dielectric layer 41 and the second dielectric layer 42 is different from the material of the dielectric layer 22 .
  • the transfer structure 30 includes: at least two contact structures; wherein each contact structure is respectively connected to at least one electrode layer 21 correspondingly.
  • the contact structure matches the number of the second redistribution holes H2 , and the same contact structure can be used to connect the exposed electrode layer 21 portions (including the exposed electrodes E) in one or more first redistribution holes H1 .
  • the electrode layer 21 has three layers.
  • the transfer structure 30 includes: a first contact structure 31 correspondingly connected to the first electrode layer 21 and the top electrode layer 21 , and a second contact structure 32 correspondingly connected to the second electrode layer 21 .
  • the transfer structure 30 is formed of a conductive material, such as metal, including titanium (Ti), tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al).
  • a conductive material such as metal, including titanium (Ti), tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al).
  • the target layer M is the substrate 10 .
  • the top surface of each electrode layer 21 is located in the same plane as the top surface of the substrate 10 , and constitutes an exposed electrode E.
  • the transfer structure 30 is connected to the exposed electrode E of each electrode layer 21 respectively.
  • the top surface of the substrate 10 is the upper surface thereof.
  • the substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination thereof.
  • the substrate 10 can be a single-layer structure or a multi-layer structure.
  • the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III/V semiconductor substrates or II/VI semiconductor substrates.
  • the substrate 1 can be a layered substrate including Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator.
  • the exposed electrode E formed by the polished surface in each electrode layer 21 is exposed in the corresponding first redistribution hole H1.
  • the exposed electrode E of the electrode layer 21 other than the top electrode layer 21 can be a ring electrode.
  • the first redistribution holes H1 corresponding to the other two adjacent electrode layers 21 other than the top electrode layer 21 can be arranged in a staggered manner, for example, they can be respectively located on both sides of the axis direction of the exposed electrode E of the top electrode layer 21.
  • the space on the side of the trench capacitor C away from the substrate 10 can be reasonably utilized to facilitate the photolithography forming of the first redistribution hole H1 and reduce the difficulty of the photolithography of the first redistribution hole H1.
  • the substrate 10 is a silicon substrate or a silicon-based substrate.
  • the inner wall surface of the trench G on the substrate 10 may be provided with a functional layer (not shown in FIG. 1 ), and the trench capacitor C is also covered with the functional layer.
  • the trench capacitor packaging structure further includes: a functional layer 11.
  • the functional layer 11 is located between the substrate 10 and the trench capacitor C, and covers the surface of the substrate 10 and the inner wall of the trench G.
  • the functional layer 11 includes a passivation layer, a barrier layer, a seed layer or a layer structure having other functions.
  • the target layer M is the functional layer 11 .
  • the top surface of each electrode layer 21 is located in the same plane as the top surface of the functional layer 11 and constitutes an exposed electrode E.
  • the transfer structure 30 is connected to the exposed electrode E of each electrode layer 21 respectively.
  • the exposed electrode E formed by the polished surface in each electrode layer 21 is exposed in the corresponding first redistribution hole H1.
  • the exposed electrode E of the other electrode layers 21 outside the top electrode layer 21 can be a ring electrode.
  • the first redistribution holes H1 corresponding to the other two adjacent electrode layers 21 outside the top electrode layer 21 can be arranged in a staggered manner, for example, they can be respectively located on both sides of the axis direction of the exposed electrode E of the top electrode layer 21.
  • the space on the side of the trench capacitor C away from the substrate 10 can be reasonably utilized to facilitate the photolithography forming of the first redistribution hole H1 and reduce the difficulty of the photolithography of the first redistribution hole H1.
  • the target layer M is any dielectric layer 22.
  • the edge portion of the electrode layer 21 located on the side of the target layer M close to the substrate 10 is arranged in at least one direction with the target layer M to form a step structure S.
  • the transfer structure 30 is also connected to the edge portion of the electrode layer 21 in the step structure S.
  • the electrode layer 21 and the dielectric layer 22 located on the side of the target layer M close to the substrate 10 can be patterned by a photomask to form a step structure S.
  • the step structure S can include at least one step.
  • the step structure S includes a plurality of steps; the number of the steps is less than or equal to the number of electrode layers 21 located on the side of the target layer M close to the substrate 10.
  • the edge portion of each electrode layer 21 located on the side of the target layer M close to the substrate 10 may form a step; or at least one step may be formed by the edge portions of at least two adjacent electrode layers 21 located on the side of the target layer M close to the substrate 10.
  • the first dielectric layer 41 may be a single-layer structure or a multi-layer structure.
  • the first dielectric layer 41 is a multi-layer structure, for example, including a first sub-dielectric layer 41A and a second sub-dielectric layer 41B, wherein the first sub-dielectric layer 41A covers the stepped structure S outside the target layer M, and the second sub-dielectric layer 41B covers the first sub-dielectric layer 41A, the target layer M and each exposed electrode E.
  • the first sub-dielectric layer 41A may be a multi-layer structure related to the number of layers of the electrode layer 21 in the stepped structure S.
  • the number of layers of the electrode layer 21 in the stepped structure S is two
  • the first sub-dielectric layer 41A includes: a first covering layer 411 and a second covering layer 412; wherein the first covering layer 411 has an opening for accommodating the first electrode layer 21 and covers the substrate 10 or the functional layer 11; and the second covering layer 412 has an opening for accommodating the second electrode layer 21 and covers the edge portion of the first electrode layer 21.
  • each covering layer in the first sub-dielectric layer 41A may be formed after the corresponding electrode layer 21 is patterned, that is, it may be formed accordingly according to the patterning requirements of each electrode layer 21.
  • the target layer M is any dielectric layer 22, and the thickness of the electrode layer 21 located on the side of the target layer M away from the substrate 10 is greater than the thickness of the electrode layer 21 located on the side of the target layer M close to the substrate 10.
  • the area of the exposed electrode E formed after polishing can be increased, thereby increasing the landing area of the transfer structure 30, facilitating the subsequent via connection between the transfer structure 30 and the exposed electrode E, and reducing the risk of poor contact.
  • the number of electrode layers 21 is three, and the target layer M is the top dielectric layer 22.
  • the electrode layer 21 located on the side of the target layer M close to the substrate 10 includes a first electrode layer 21 and a second electrode layer 21, wherein the thickness of the first electrode layer 21 is T1, the thickness of the second electrode layer 21 is T2, and T1 and T2 may be equal or different.
  • the electrode layer 21 located on the side of the target layer M away from the substrate 10 is the top electrode layer 21, and the thickness of the top electrode layer 21 is T3, T3>T1 and T3>T2.
  • the target layer M may also be any electrode layer 21 other than the top electrode layer 21 .
  • the edge portion of the electrode layer 21 located on the side of the target layer M close to the substrate 10 is arranged in at least one direction with the target layer M to form a step structure S.
  • the transition structure 30 is also connected to the edge portion of the electrode layer 21 in the step structure S accordingly.
  • the electrode layer 21 and the dielectric layer 22 located on the side of the target layer M close to the substrate 10 can be patterned by a photomask to form a step structure S.
  • the step structure S may include at least one step.
  • the step structure S includes a plurality of steps; the number of the steps is less than or equal to the number of electrode layers 21 located on the side of the target layer M close to the substrate 10.
  • the edge portion of each electrode layer 21 located on the side of the target layer M close to the substrate 10 may form a step; or at least one step may be formed by the edge portions of at least two adjacent electrode layers 21 located on the side of the target layer M close to the substrate 10.
  • the first dielectric layer 41A may be a single-layer structure or a multi-layer structure.
  • the first dielectric layer 41 is a multi-layer structure, for example, including a first sub-dielectric layer 41A and a second sub-dielectric layer 41B, wherein the first sub-dielectric layer 41A covers the stepped structure S outside the target layer M, and the second sub-dielectric layer 41B covers the first sub-dielectric layer 41A, the target layer M and each exposed electrode E.
  • the first sub-dielectric layer 41A may be a one-layer or multi-layer structure, and may be formed accordingly according to the graphic requirements of each electrode layer 21.
  • the number of layers of the electrode layer 21 in the stepped structure S is two layers, wherein the first sub-dielectric layer 41A is a one-layer structure, has an opening for accommodating the second electrode layer 21, and covers the edge portion of the first electrode layer 21 and the substrate 10 or the functional layer 11; the second electrode layer 21 is the target layer M.
  • the target layer M is any electrode layer 21 other than the top electrode layer 21, and the thickness of the target layer M is greater than the thickness of other electrode layers 21. In this way, in the process of polishing to the target layer M to form the exposed electrode E, over-polishing of the electrode layer 21 as the target layer M can be avoided to ensure the electrical performance of the electrode layer 21, thereby ensuring the reliability of the trench capacitor C.
  • some embodiments of the present disclosure further provide a method for preparing a trench capacitor packaging structure, which is used to prepare the trench capacitor packaging structure in some of the above embodiments, and includes the following steps.
  • the initial capacitor includes a plurality of stacked electrode layers and a plurality of electrodes disposed between any two adjacent electrodes.
  • the dielectric layer between the electrode layers.
  • the initial capacitor is polished using a chemical mechanical polishing process.
  • the transfer structure is formed using a dual damascene process.
  • any layer structure from the substrate to the top dielectric layer can be selected as the target layer by selecting the target layer, and then the top surface of the electrode layer on the side of the target layer facing away from the substrate is directly formed into an exposed electrode through a polishing process.
  • the top surface of the electrode layer and the dielectric layer on the side of the target layer facing away from the substrate are located in the same plane as the top surface of the target layer, and the top surface of the electrode layer on the side of the target layer facing away from the substrate constitutes an exposed electrode, which can ensure that the electrode layer on the side of the target layer facing away from the substrate does not need to be patterned using a mask, and can also have an exposed electrode.
  • the number of dielectric layers and electrode layers in the initial capacitor can be set according to the needs.
  • the structure of the initial capacitor can also be implemented differently, and the target layer can match the structure of the initial capacitor selected from the substrate, any dielectric layer, any electrode layer other than the top electrode layer, or any thin film structure arranged on the surface of the substrate, such as a functional layer.
  • the functional layer includes a passivation layer, a barrier layer, a seed layer, or a layer structure with other functions.
  • the functional layer covers the substrate surface and the inner wall of the groove, and the material and thickness of the functional layer can be set according to actual needs.
  • the target layer is a substrate.
  • Step S200 forms an initial capacitor on one side of the substrate and in the trench, including: forming alternately stacked electrode material layers and dielectric material layers on the surface of the substrate.
  • Step S300 polishes the initial capacitor until the target layer is exposed and at least one exposed electrode is formed, including: polishing the initial capacitor until the substrate is exposed, so that the retained portions of each electrode material layer respectively form an electrode layer, and the retained portions of each dielectric material layer respectively form a dielectric layer; wherein the polished surface of each electrode layer is exposed to form a plurality of exposed electrodes.
  • the target layer is a functional layer. Referring to FIG8 , before forming an initial capacitor on one side of the substrate and in the trench in step S200 , the manufacturing method further includes S150 .
  • step S200 forms an initial capacitor on one side of the substrate and in the trench, and further includes: forming alternately stacked electrode material layers and dielectric material layers on the surface of the functional layer facing away from the substrate.
  • Step S300 polishes the initial capacitor until the target layer is exposed and at least one exposed electrode is formed, including: polishing the initial capacitor until the functional layer is exposed, so that the retained portions of each electrode material layer respectively form an electrode layer, and the retained portions of each dielectric material layer respectively form a dielectric layer; wherein the polished surface of each electrode layer is exposed to form a plurality of exposed electrodes.
  • the preparation methods of the initial capacitor and each exposed electrode are similar.
  • the following is a detailed description taking the target layer as a functional layer as an example.
  • step S200 alternately stacked electrode material layers 2100 and dielectric material layers 2200 are formed on the surface of the functional layer 11 facing away from the substrate 10.
  • the preparation of the initial capacitor 2 is considered completed.
  • the electrode material layer 2100 and the dielectric material layer 2200 are formed by deposition processes.
  • the deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the number of layers and thickness of the electrode material layer 2100 and the dielectric material layer 2200 can be set according to actual needs.
  • the thickness of each electrode material layer 2100 is the same, and the thickness of each dielectric material layer 2200 is the same.
  • the material of the electrode material layer 2100 includes polysilicon, metal or metal compound, such as titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), copper (Cu) or aluminum (Al).
  • metal or metal compound such as titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), copper (Cu) or aluminum (Al).
  • the material of the dielectric material layer 2200 includes a high-K dielectric material , including but not limited to aluminum oxide ( Al2O3 ), hafnium oxide ( HfO2 ), hafnium oxynitride (HfON), zirconium oxide ( ZrO2 ), tantalum oxide ( Ta2O5 ), titanium oxide ( TiO2 ), or strontium titanium oxide ( SrTiO3 ).
  • Al2O3 aluminum oxide
  • HfO2 hafnium oxide
  • HfON hafnium oxynitride
  • ZrO2 zirconium oxide
  • Ta2O5 tantalum oxide
  • TiO2 titanium oxide
  • strontium titanium oxide strontium titanium oxide
  • step S300 the initial capacitor 2 is polished until the functional layer 11 is exposed, so that the retained portions of each electrode material layer 2100 respectively form an electrode layer 21, and the retained portions of each dielectric material layer 2200 respectively form a dielectric layer 22; wherein the polished surface of each electrode layer 21 is exposed to form a plurality of exposed electrodes E.
  • the polished surface of each electrode layer 21 is directly exposed to form an exposed electrode E.
  • the functional layer 11 is used as the target layer M, and the process of using multiple masks to pattern each electrode material layer 2100 can be omitted, thereby effectively reducing the number of masks used in the preparation process of the trench capacitor packaging structure, so as to minimize the production cost and improve the production efficiency.
  • the preparation method further includes S350 .
  • the step S400 of forming a transfer structure includes the following steps.
  • a substrate or a functional layer is selected as a target layer, and after a plurality of exposed electrodes are formed by polishing an initial capacitor, a transfer structure can be formed in the second redistribution hole and the first redistribution hole by forming a first redistribution hole and a second redistribution hole, and corresponding connections between the transfer structure and each exposed electrode are achieved.
  • the preparation method in the embodiment of the present disclosure is easy to implement, which is conducive to effectively improving production efficiency and reducing production costs.
  • step S350 referring to FIG. 12 , a first dielectric layer 41 is formed to cover each exposed electrode E and the functional layer 11 (ie, the target layer M).
  • step S410 referring to FIG. 13 and FIG. 14 , the first dielectric layer 41 is patterned to form a plurality of first redistribution holes H1 ; and a plurality of exposed electrodes E are respectively exposed in the corresponding first redistribution holes H1 .
  • a patterned first photoresist layer PR1 is formed on the surface of the first dielectric layer 41 .
  • the first dielectric layer 41 is etched based on the patterned first photoresist layer PR1, such as dry etching, to form a plurality of first redistribution holes H1 to ensure that each exposed electrode E can be exposed to the corresponding first redistribution hole H1.
  • the exposed electrode E formed by the polished surface in any electrode layer 21 is exposed in the corresponding first redistribution hole H1.
  • the exposed electrode E of the other electrode layers 21 outside the top electrode layer can be a ring electrode.
  • the first redistribution holes H1 corresponding to the other two adjacent electrode layers 21 outside the top electrode layer are staggered, for example, they can be located on both sides of the axis direction of the exposed electrode of the top electrode layer. In this way, the space on the side of the trench capacitor away from the substrate can be reasonably utilized to facilitate the photolithography forming of the first redistribution hole H1 and reduce the difficulty of the photolithography of the first redistribution hole H1.
  • step S420 referring to FIG. 15 , a sacrificial layer 50 filling the first redistribution holes H1 is formed.
  • the material of the sacrificial layer 50 includes but is not limited to spin-on carbon (SOC).
  • SOC spin-on carbon
  • the sacrificial layer 50 is formed by a spin coating process, which facilitates the filling of the sacrificial layer 50 in the first redistribution hole H1 and ensures that the upper surface of the sacrificial layer 50 is flush with the upper surface of the first dielectric layer 41.
  • step S430 referring to FIG. 16 , a second dielectric layer 42 is formed to cover the sacrificial layer 50 and the first dielectric layer 41 .
  • the first dielectric layer 41 and the second dielectric layer 42 are made of the same material, such as oxide, such as silicon dioxide, which is not only convenient for preparation, but also convenient for etching the first dielectric layer 41 and the second dielectric layer 42 using the same process to form a desired pattern.
  • step S440 referring to FIGS. 17 and 18 , the second dielectric layer 42 is patterned to form a plurality of second redistribution holes H2 ; the sacrificial layer 50 is exposed in the second redistribution holes H2 .
  • a patterned second photoresist layer PR2 is formed on the surface of the second dielectric layer 42 .
  • the second dielectric layer 42 is etched based on the patterned second photoresist layer PR2, such as dry etching, to form a plurality of second redistribution holes H2 to ensure that the sacrificial layer 50 is exposed.
  • step S450 referring to FIG. 19 , the sacrificial layer 50 is removed so that the second redistribution holes H2 are connected to the first redistribution holes H1 .
  • step S460 referring to FIG. 20 and FIG. 21 , the transfer structures 30 are formed in the second redistribution holes H2 and the first redistribution holes H1 ; the transfer structures 5 are connected to the exposed electrodes E exposed in each of the first redistribution holes H respectively.
  • a transfer structure material layer 300 is deposited.
  • the transfer structure material layer 300 fills the first redistribution hole H1 and the second redistribution hole H2, and covers the upper surface of the second dielectric layer 42.
  • the transfer structure 30 includes: a first contact structure 31 correspondingly connected to the exposed electrodes E of the first electrode layer 21 and the top electrode layer 21 , and a second contact structure 32 correspondingly connected to the second electrode layer 21 .
  • an initial capacitor is formed on one side of the substrate and in the trench in step S200 , including the following steps.
  • each electrode material layer and each dielectric material layer to form a multi-layer initial electrode layer and a multi-layer initial dielectric layer that at least fill the grooves.
  • each initial electrode layer and the corresponding initial dielectric layer to form a multi-layer electrode layer and a multi-layer dielectric layer; wherein, the target layer is any dielectric layer, and the edge portion of the electrode layer located on the side of the target layer close to the substrate is arranged in a stepped structure with the target layer in at least one direction; or, the target layer is any electrode layer other than the top electrode layer, and when the target layer is not the first electrode layer, the edge portion of the electrode layer located on the side of the target layer close to the substrate is arranged in a stepped structure with the target layer in at least one direction.
  • the edge portion of the electrode layer located on the side of the target layer close to the substrate is arranged in a stepped structure with the target layer in at least one direction, which means that the edge portion of the electrode layer located on the side of the target layer close to the substrate is staggered with the target layer in at least one direction, and is respectively exposed and forms different steps, so as to facilitate the subsequent transfer connection.
  • the stepped structure includes at least one step, and the number of steps is less than or equal to the number of electrode layers on the side of the target layer close to the substrate.
  • each electrode layer located on the side of the target layer close to the substrate can form a step; or, at least one step can be formed by the edge portions of at least two adjacent electrode layers on the side of the target layer close to the substrate.
  • the electrode layer located on the side of the target layer away from the substrate does not need to be patterned by a mask, and only the electrode layer on the side of the target layer close to the substrate can be patterned.
  • the initial capacitor fills the groove, the initial capacitor starts with the first electrode layer and ends with the top electrode layer; and there is a dielectric layer between adjacent electrode layers to achieve insulation isolation of adjacent electrode layers.
  • the dielectric layer corresponding to each electrode layer refers to: the dielectric layer that is close to and directly contacts the substrate side of the electrode layer. Unless otherwise specified, the electrode layer and the corresponding dielectric layer can be processed synchronously.
  • the target layer is any dielectric layer.
  • the target layer can be simultaneously exposed and at least one exposed electrode can be formed, which means that the exposed electrode can be ensured to have a dielectric layer next to it.
  • the electrode layer formed on the side of the target layer away from the substrate is formed thicker than the electrode layer formed on the side of the target layer close to the substrate.
  • the area of the exposed electrode formed after polishing can be increased, thereby increasing the landing area of the transfer structure, facilitating the subsequent via connection between the transfer structure and the exposed electrode, and reducing the risk of poor contact.
  • each initial electrode layer located on the side of the target layer away from the substrate and the initial electrode layer located on the side of the target layer close to the substrate and adjacent to the target layer can be patterned using the same mask, thereby further reducing the total number of masks when patterning the initial electrode layers to form electrode layers.
  • the target layer is any electrode layer other than the top electrode layer.
  • the target layer is formed with a thickness greater than the thickness of other electrode layers. In this way, over-polishing of the electrode layer as the target layer can be avoided to ensure the electrical performance of the electrode layer, thereby ensuring the reliability of the trench capacitor.
  • the target layer is selected from any layer structure in the initial capacitor.
  • the preparation method further includes S350 ′.
  • step S400 forms a switching structure, including the following steps.
  • a transfer structure can be formed in the second redistribution hole and the first redistribution hole by forming the first redistribution hole, and the corresponding connection between the transfer structure and the exposed electrode and the edge portion of each electrode layer in the stepped structure is achieved.
  • the preparation process of the transfer structure in the embodiment of the present disclosure is easy to implement, which is conducive to improving production efficiency.
  • the first dielectric layer can be a single-layer structure or a multi-layer structure.
  • the first dielectric layer is a multi-layer structure, for example, including a first sub-dielectric layer and a second sub-dielectric layer, wherein the first sub-dielectric layer covers the stepped structure outside the target layer, and the second sub-dielectric layer covers the first sub-dielectric layer, the target layer and each exposed electrode.
  • the first sub-dielectric layer may be a multi-layer structure related to the number of electrode layers in the stepped structure. For example, if the number of electrode layers in the stepped structure is two, the first sub-dielectric layer includes: a first covering layer and a second covering layer; wherein the first covering layer has an opening for accommodating the first electrode layer and covers the substrate or the functional layer; and the second covering layer has an opening for accommodating the second electrode layer and covers the edge portion of the first electrode layer.
  • each covering layer in the first sub-dielectric layer may be formed after the corresponding electrode layer is patterned, that is, it may be formed accordingly according to the patterning requirements of each electrode layer.
  • step S350' may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps (such as S300) or at least a part of the sub-steps or stages of other steps (such as S300).
  • steps S350' and S300 There is no strict order restriction for the execution of steps S350' and S300.
  • the target layer is selected from any layer structure in the initial capacitor.
  • the target layer is described in detail below as an example of the top dielectric layer.
  • the exposed electrodes and other electrode layers in the stepped structure that need to be separately patterned can be formed by referring to the corresponding preparation process, which will not be described in detail in the embodiments of the present disclosure.
  • step S210 referring to FIG. 24 , electrode material layers 2100 and dielectric material layers 2200 are alternately stacked on one side of the substrate 10 .
  • Electrode material layers 2100 and dielectric material layers 2200 are alternately stacked on the surface of the functional layer 11 facing away from the substrate 10 .
  • the electrode material layer 2100 and the dielectric material layer 2200 are formed by deposition processes.
  • the deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the number of layers and thickness of the electrode material layer 2100 and the dielectric material layer 2200 can be set according to actual needs.
  • the thickness of each electrode material layer 2100 is the same, and the thickness of each dielectric material layer 2200 is the same.
  • the material of the electrode material layer 2100 includes polysilicon, metal or metal compound, such as titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), copper (Cu) or aluminum (Al).
  • metal or metal compound such as titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), copper (Cu) or aluminum (Al).
  • the material of the dielectric material layer 2200 includes a high-K dielectric material.
  • the high-K dielectric material includes but is not limited to aluminum oxide (Al 2 O 3 ), Hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), or strontium titanium oxide (SrTiO 3 ), or the like.
  • each electrode material layer 2100 and each dielectric material layer 2200 are patterned to form a multi-layer initial electrode layer 210 and a multi-layer initial dielectric layer 220 that at least fills the trench G.
  • the functional layer 11 covers the substrate 10, which can protect the surface of the substrate 10 and effectively isolate the substrate 10 and the first initial electrode layer 210.
  • a patterned third photoresist layer PR3 can be formed on the surface of the top electrode material layer 2100 first, and then each electrode material layer 2100 and the corresponding dielectric material layer 2200 are etched based on the patterned third photoresist layer PR3, such as dry etching.
  • a multi-layer initial electrode layer 210 and a multi-layer initial dielectric layer 220 are obtained as shown in FIG26 .
  • step S230 please refer to Figures 27 to 32, and graph each initial electrode layer 210 and the corresponding initial dielectric layer 220 to form a multi-layer electrode layer 21 and a multi-layer dielectric layer 22; wherein, the target layer M is any dielectric layer 22, and the edge portion of the electrode layer 21 located on the side of the target layer M close to the substrate 10 is arranged in a step structure S with the target layer M in at least one direction; or, the target layer M is any electrode layer 21 other than the top electrode layer 21, and when the target layer M is not the first electrode layer 21, the edge portion of the electrode layer 21 located on the side of the target layer M close to the substrate 10 is arranged in a step structure S with the target layer M in at least one direction.
  • the target layer M is the top dielectric layer 22 .
  • step S350 ′ referring to FIGS. 27 to 33 , a first dielectric layer 41 at least covering the step structure S, the target layer M and the exposed electrode E is formed.
  • the first dielectric layer 41 includes a first sub-dielectric layer 41A and a second sub-dielectric layer 41B.
  • the first sub-dielectric layer 41 includes a first cover layer 411 and a second cover layer 412.
  • the first cover layer 411 may be formed after the first electrode layer 21 is formed
  • the second cover layer 412 may be formed after the second electrode layer 21 is formed.
  • the first sub-dielectric layer 41A may also include a plurality of corresponding cover layers.
  • a first covering material layer 4110 is deposited to cover the functional layer 11, the sidewalls of each initial electrode layer 210 and initial dielectric layer 220, and the top initial electrode layer 210.
  • the deposition thickness of the first covering material layer 4110 is greater than the sum of the thicknesses of each initial electrode layer 210 and each initial dielectric layer 220 above the substrate 10.
  • the first covering material layer 4110 is polished to form a first initial covering layer 411B having a flat surface.
  • a patterned fourth photoresist layer PR4 is formed on the surface of the first initial covering layer 411B.
  • the first initial cover layer 411B and each initial electrode layer 210 and each initial dielectric layer 220 are etched based on the patterned fourth photoresist layer PR4 to form the first cover layer 411A and the first electrode layer 21, and the edge portion of the first electrode layer 21 is exposed to form the first step B1.
  • the edge portion of the second electrode layer 21 can simultaneously form the second step B2.
  • the first step B1 and the second step B2 can form a step structure S.
  • the target layer M is any dielectric layer 22, and each initial electrode layer 210 located on the side of the target layer M facing away from the substrate 10 can be patterned by the same mask as the initial electrode layer 210 located on the side of the target layer M close to the substrate 10 and adjacent to the target layer M.
  • the target layer M can be selected from the top dielectric layer 22.
  • the top initial electrode layer 210 and the second top initial electrode layer 210 can be patterned by the same mask.
  • the top initial electrode layer 210 is located on the side of the target layer M (i.e., the top dielectric layer 22) facing away from the substrate 10, and the second top initial electrode layer 210 is located on the side of the target layer M (i.e., the top dielectric layer) close to the substrate 10, and the top initial electrode layer 210 and the second top initial electrode layer 210 are two adjacent initial electrode layers 210. Furthermore, the top initial dielectric layer 220 is located between the top initial electrode layer 210 and the second top initial electrode layer 210. When the top initial electrode layer 210 and the second top initial electrode layer 210 are patterned by the same mask, the top initial dielectric layer 220 can be patterned synchronously to form the top dielectric layer 22.
  • the second top initial dielectric layer 220 can also be patterned synchronously with the aforementioned top initial electrode layer 210, the top initial dielectric layer 220 and the second top initial electrode layer 210 to form the second top dielectric layer 220, and expose the edge portion of the initial electrode layer 210 on one side close to the substrate 10.
  • the stepped structure S can be formed by a single mask process.
  • the top electrode layer 21 can directly form the exposed electrode E by a polishing process without the need for mask patterning.
  • the second covering layer 412A is deposited.
  • the second covering layer 412A can be formed before the top electrode layer 21 is polished to form the exposed electrode E.
  • the second covering layer 412A covers the first covering layer 411A and the upper surface of the first step B1 and the side wall of the second step B2 in the aforementioned step structure S.
  • the second covering layer 412A and the first covering layer 411A together constitute the first initial sub-dielectric layer.
  • the materials of the second covering layer 412A and the first covering layer 411A can be the same or different.
  • the target layer M is the top dielectric layer
  • the initial capacitor is polished in step S300 until the target layer is exposed and at least one exposed electrode is formed, and it also includes: polishing the first initial sub-dielectric layer and the top electrode layer 21 to expose the top dielectric layer (ie, the target layer M), and making the retained portion of the top electrode layer 21 form the exposed electrode E, and making the retained portion of the first initial sub-dielectric layer form the first sub-dielectric layer 41A.
  • the first sub-dielectric layer 41A includes a polished first capping layer 411 and a polished second capping layer 412 .
  • a second sub-dielectric layer 42A is formed to cover the exposed electrode E, the target layer M and the first sub-dielectric layer 41A.
  • the first sub-dielectric layer 41A and the second sub-dielectric layer 42A together constitute the first dielectric layer 41 .
  • step S410' referring to FIG. 34 and FIG. 35, the first dielectric layer 41 is patterned to form a plurality of first redistribution holes H1; the electrodes are exposed. The edge portions of the electrode layers 21 in the stepped structure E and S are respectively exposed to the corresponding first redistribution holes H1.
  • a patterned fifth photoresist layer PR5 is formed on the surface of the first dielectric layer 41 .
  • the first dielectric layer 41 and the top dielectric layer are etched based on the patterned fifth photoresist layer PR5, such as dry etching, to form a plurality of first redistribution holes H1, so as to ensure that the edge portions of the exposed electrode E and each electrode layer 21 in the stepped structure S can be exposed to the corresponding first redistribution holes H1.
  • the target layer M is the electrode layer 21, it is not necessary to etch the target layer M to form the first redistribution holes H1.
  • the target layer M is any dielectric layer 22 ; a portion of the target layer M is also exposed in the first redistribution hole H1 corresponding to the target exposed electrode E; and the target exposed electrode E is located on the side of the target layer M away from the substrate 10 and is adjacent to the target layer M.
  • a portion of the top dielectric layer (ie, the target layer M) is also exposed in the first redistribution hole H1 corresponding to the exposed electrode E.
  • the first redistribution hole H1 corresponding to the exposed electrode E can have a larger process size, for example, a portion of the top dielectric layer can be exposed, thereby reducing the etching accuracy of the first redistribution hole H1, so as to further reduce the production cost and improve the production efficiency.
  • step S420 ′ referring to FIG36 , a sacrificial layer 50 is formed to fill the first redistribution holes H1 .
  • the upper surface of the sacrificial layer 50 is flush with the upper surface of the first dielectric layer 41 .
  • step S430 ′ referring to FIG. 37 , a second dielectric layer 42 is formed to cover the sacrificial layer 50 and the first dielectric layer 41 .
  • the second dielectric layer 42 is patterned to form a plurality of second redistribution holes H2; the sacrificial layer 50 is exposed in the second redistribution holes H2. The sacrificial layer 50 is removed to connect the second redistribution holes H2 to the first redistribution holes H1.
  • a patterned sixth photoresist layer PR6 is formed on the surface of the second dielectric layer 42 .
  • step S460' referring to FIG. 40 and FIG. 41, a transfer structure 30 is formed in the second redistribution hole H2 and the first redistribution hole H1; the transfer structure 30 is connected to the exposed electrode E and the edge portions of each electrode layer 21 in the stepped structure S respectively.
  • a transfer structure material layer 300 is deposited.
  • the transfer structure material layer 300 fills the first redistribution hole H1 and the second redistribution hole H2, and covers the upper surface of the second dielectric layer 42.
  • the structure obtained after the transfer structure material layer 300 is polished until the second dielectric layer 42 is exposed, so that the portion of the transfer structure material layer 300 retained in the second redistribution hole H2 and the first redistribution hole H1 forms a transfer structure 30, which can ensure that the transfer structure 30 has a high surface quality, so as to facilitate the subsequent bonding connection of the trench capacitor packaging structure with other devices.
  • the transition structure 30 includes: a first contact structure 31 correspondingly connected to the first electrode layer 21 and the top electrode layer (ie, the exposed electrode E), and a second contact structure 32 correspondingly connected to the second electrode layer.
  • the materials of the first dielectric layer 41 and the second dielectric layer 42 are the same.
  • the materials of the first dielectric layer 41 and the second dielectric layer 42 are different from the materials of the dielectric layer 22 (i.e., the dielectric material layer 2200).
  • the materials of the first dielectric layer 41 and the second dielectric layer 42 include oxides, such as silicon dioxide. In this way, it is not only convenient to prepare, but also convenient to etch the first dielectric layer 41 and the second dielectric layer 42 using the same process to form a desired pattern.
  • the material of the sacrificial layer 50 includes but is not limited to spin-on carbon (SOC).
  • SOC spin-on carbon
  • the sacrificial layer 50 is formed by a spin coating process, which facilitates the filling of the sacrificial layer 50 in the first redistribution hole H1 and ensures that the upper surface of the sacrificial layer 50 is flush with the upper surface of the first dielectric layer 41.
  • some embodiments of the present disclosure provide a semiconductor structure, including: a trench capacitor packaging structure as described in any of the above embodiments.
  • the semiconductor structure may be a memory device.
  • the semiconductor structure may be a passive device, such as an adapter.

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Abstract

本公开涉及一种沟槽电容器封装结构及其制备方法、半导体结构。沟槽电容器封装结构包括：具有沟槽的衬底、位于衬底一侧且填充沟槽的沟槽电容器及转接结构。沟槽电容器包括：层叠设置的多层电极层及位于任相邻两层电极层之间的介电层。衬底至顶层介电层中的任一层结构构成目标层。位于目标层背离衬底一侧的电极层及介电层的顶表面与目标层的顶表面位于同一平面。位于目标层背离衬底一侧的电极层的顶表面构成裸露电极。转接结构设置于沟槽电容器背离衬底的一侧，并至少与裸露电极对应连接。

Description

沟槽电容器封装结构及其制备方法、半导体结构
相关申请的交叉引用
本公开要求于2022年09月29日提交中国专利局、申请号为202211200558.5、发明名称为“沟槽电容器封装结构及其制备方法、半导体结构”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体制造技术领域，特别是涉及一种沟槽电容器封装结构及其制备方法、半导体结构。
背景技术
随着半导体超大规模集成电路的发展，现有的技术工艺已经接近物理极限。在对电子产品进一步小型化、多功能化的目的驱动下，在动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)中采用沟槽电容器，例如深沟槽电容器(Deep Trench Capacitor，简称DTC)，可以使DRAM具有较大的电容存储量，并表现出较高的器件性能。
发明内容
本公开一些实施例提供了一种沟槽电容器封装结构，包括：衬底、沟槽电容器以及转接结构。衬底具有沟槽。沟槽电容器位于衬底一侧且填充沟槽。沟槽电容器包括：层叠设置的多层电极层及位于任相邻两层电极层之间的介电层。衬底至顶层介电层中的任一层结构构成目标层。位于目标层背离衬底一侧的电极层及介电层的顶表面与目标层的顶表面位于同一平面。位于目标层背离衬底一侧的电极层的顶表面构成裸露电极。转接结构设置于沟槽电容器背离衬底的一侧，并至少与裸露电极对应连接。
在一些实施例中，目标层为所述衬底。各层电极层的顶表面均与衬底的顶表面位于同一平面，且构成裸露电极。转接结构与各层电极层的裸露电极分别对应连接。
在一些实施例中，沟槽电容器封装结构还包括：功能层。功能层位于衬底和沟槽电容器之间，并覆盖衬底表面及沟槽内壁面。目标层为功能层。各层电极层的顶表面均与功能层的顶表面位于同一平面，且构成裸露电极。转接结构与各层电极层的裸露电极分别对应连接。
在一些实施例中，目标层为任一层介电层。位于目标层靠近衬底一侧的电极层的边缘部分与目标层在至少一个方向上排布成阶梯结构。转接结构还与阶梯结构中电极层的边缘部分对应连接。
在一些实施例中，位于目标层背离衬底一侧的电极层的厚度大于位于目标层靠近衬底一侧的电极层的厚度。
在一些实施例中，目标层为顶层电极层之外任一层电极层。在目标层非第一层电极层的情况下，位于目标层靠近衬底的一侧的电极层的边缘部分与目标层在至少一个方向上排布成阶梯结构。转接结构还与阶梯结构中电极层的边缘部分对应连接。
在一些实施例中，目标层的厚度大于其他电极层的厚度。
在一些实施例中，沟槽电容器封装结构，还包括：第一介质层和第二介质层。第一介质层至少覆盖沟槽电容器，具有多个第一重分布孔。第二介质层覆盖第一介质层，具有多个第二重分布孔。第二重分布孔与第一重分布孔对应连通。转接结构设置于第一重分布孔及第二重分布孔内，并与各电极层分别对应连接。
在一些实施例中，转接结构包括：至少两个接触结构；其中，各接触结构分别与至少一层电极层对应连接。
另一方面，本公开一些实施例提供了一种沟槽电容器封装结构的制备方法，包括如下步骤。
提供衬底，衬底具有沟槽。
于衬底一侧及沟槽内形成初始电容器。初始电容器包括：层叠设置的多层电极层及位于任相邻两层电极层之间的介电层。
抛光初始电容器至暴露出目标层并形成至少一个裸露电极；其中，目标层选自衬底至顶层介电层中的任一层结构，裸露电极基于目标层背离衬底的一侧的至少一层电极层形成。
形成转接结构，转接结构至少与裸露电极对应连接。
在一些实施例中，目标层为衬底。所述于衬底一侧及沟槽内形成初始电容器，包括：于衬底表面形成交替层叠的电极材料层和介电材料层。所述抛光初始电容器至暴露出目标层并形成至少一个裸露电极，包括：抛光初始电容器至暴露出衬底，以使各电极材料层的保留部分分别形成电极层，各介电材料层的保留部分分别形成介电层；其中，各层电极层的抛光表面裸露以形成多个裸露电极。
在一些实施例中，所述于衬底一侧及沟槽内形成初始电容器之前，所述制备方法还包括：于衬底表面及沟槽内壁面形成功能层。所述于衬底一侧及沟槽内形成初始电容器，还包括：于功能层背离衬底的表面形成交替层叠的电极材料层和介电材料层。
目标层为功能层。所述抛光初始电容器至暴露出目标层并形成至少一个裸露电极，包括：抛光初始电容器至暴露出功能层，以使各电极材料层的保留部分分别形成电极层，各介电材料层的保留部分分别形成介电层；其中，各层电极层的抛光表面裸露以形成多个裸露电极。
在一些实施例中，所述抛光初始电容器至暴露出目标层并形成至少一个裸露电极之后，所述制备方法还包括：形成覆盖各裸露电极和目标层的第一介质层。
所述形成转接结构，包括如下步骤。
图形化第一介质层，形成多个第一重分布孔；多个裸露电极分别暴露于对应的第一重分布孔内。
形成填充第一重分布孔的牺牲层。
形成覆盖牺牲层及第一介质层的第二介质层。
图形化第二介质层，形成多个第二重分布孔；牺牲层暴露于第二重分布孔内。
去除牺牲层，使第二重分布孔与第一重分布孔对应连通。
于第二重分布孔和第一重分布孔内形成转接结构；转接结构与暴露于各第一重分布孔内的裸露电极分别对应连接。
在一些实施例中，所述于衬底一侧及沟槽内形成初始电容器，包括如下步骤。
于衬底一侧形成交替层叠的电极材料层和介电材料层。
图形化各电极材料层及各介电材料层，形成至少填充沟槽的多层初始电极层和多层初始介电层。
图形化各初始电极层及对应的初始介电层，形成多层电极层和多层介电层；其中，目标层为任一层介电层，位于目标层靠近衬底一侧的电极层的边缘部分与目标层在至少一个方向上排布成阶梯结构；或者，目标层为顶层电极层之外任一层电极层，在目标层非第一层电极层的情况下，目标层靠近衬底一侧的电极层的边缘部分与目标层在至少一个方向上排布成阶梯结构。
在一些实施例中，目标层为任一层介电层。位于目标层背离衬底一侧的电极层的形成厚度大于位于目标层靠近衬底一侧的电极层的形成厚度。
在一些实施例中，目标层为任一层介电层。位于目标层背离衬底一侧的各层初始电极层与位于目标层靠近衬底一侧且与目标层相邻的初始电极层通过同一光罩图形化。
在一些实施例中，目标层为顶层电极层之外任一层电极层。目标层的形成厚度大于其他电极层的形成厚度。
在一些实施例中，所述抛光初始电容器至暴露出目标层并形成至少一个裸露电极之后，所述制备方法还包括：形成至少覆盖阶梯结构、目标层和裸露电极的第一介质层。
所述形成转接结构，包括如下步骤。
图形化所述第一介质层，形成多个第一重分布孔。裸露电极及阶梯结构中各层电极层的边缘部分分别暴露于对应的第一重分布孔内。
形成填充第一重分布孔的牺牲层。
形成覆盖牺牲层及第一介质层的第二介质层。
图形化第二介质层，形成多个第二重分布孔。牺牲层暴露于第二重分布孔内。
去除牺牲层，使第二重分布孔与第一重分布孔对应连通。
于第二重分布孔和第一重分布孔内形成转接结构。转接结构与裸露电极、阶梯结构中各层电极层的边缘部分分别对应连接。
在一些实施例中，目标层为任一层介电层。目标裸露电极对应的第一重分布孔内还暴露出部分目标层。目标裸露电极位于目标层背离衬底一侧并与目标层相邻。
又一方面，本公开一些实施例提供了一种半导体结构，包括：如上任一实施例所述的沟槽电容器封装结构。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的一种沟槽电容器封装结构的结构示意图；
图2为一实施例中提供的另一种沟槽电容器封装结构的结构示意图；
图3为一实施例中提供的又一种沟槽电容器封装结构的结构示意图；
图4为一实施例中提供的一种沟槽电容器的放大示意图；
图5为一实施例中提供的又一种沟槽电容器封装结构的结构示意图；
图6为一实施例中提供的另一种沟槽电容器的放大示意图；
图7为一实施例中提供的一种沟槽电容器封装结构的制备方法的流程示意图；
图8为一实施例中提供的另一种沟槽电容器封装结构的制备方法的流程示意图；
图9为一实施例中提供的一种形成初始电容器后所得结构的结构示意图；
图10为一实施例中提供的一种形成裸露电极后所得结构的结构示意图；
图11为一实施例中提供的一种转接结构制备方法的流程示意图；
图12为一实施例中提供的一种形成第一介质层后所得结构的结构示意图；
图13为一实施例中提供的一种形成第一光刻胶层后所得结构的结构示意图；
图14为一实施例中提供的一种形成第一重分布孔后所得结构的结构示意图；
图15为一实施例中提供的一种形成牺牲层后所得结构的结构示意图；
图16为一实施例中提供的一种形成第二介质层后所得结构的结构示意图；
图17为一实施例中提供的一种形成第二光刻胶层后所得结构的结构示意图；
图18为一实施例中提供的一种形成第二重分布孔后所得结构的结构示意图；
图19为一实施例中提供的一种去除牺牲层后所得结构的结构示意图；
图20为一实施例中提供的一种形成转接结构材料层后所得结构的结构示意图；
图21为一实施例中提供的一种形成转接结构后所得结构的结构示意图；
图22为一实施例中提供的另一种初始电容器制备方法的流程示意图；
图23为一实施例中提供的另一种转接结构制备方法的流程示意图；
图24为一实施例中提供的一种形成交替层叠的介电材料层和电极材料层后所得结构的结构示意图；
图25为一实施例中提供的一种形成第三光刻胶层后所得结构的结构示意图；
图26为一实施例中提供的一种形成初始电极层和初始介电层后所得结构的结构示意图；
图27为一实施例中提供的一种形成第一覆盖材料层后所得结构的结构示意图；
图28为一实施例中提供的一种形成第一初始覆盖层后所得结构的结构示意图；
图29为一实施例中提供的一种形成第四光刻胶层后所得结构的结构示意图；
图30为一实施例中提供的一种形成第一覆盖层后所得结构的结构示意图；
图31为一实施例中提供的一种形成第二覆盖层后所得结构的结构示意图；
图32为一实施例中提供的一种形成裸露电极后所得结构的结构示意图；
图33为一实施例中提供的一种形成第二子介质层后所得结构的结构示意图；
图34为一实施例中提供的一种形成第五光刻胶层后所得结构的结构示意图；
图35为一实施例中提供的另一种形成第一重分布孔后所得结构的结构示意图；
图36为一实施例中提供的另一种形成牺牲层后所得结构的结构示意图；
图37为一实施例中提供的另一种形成第二介质层后所得结构的结构示意图；
图38为一实施例中提供的一种形成第六光刻胶层后所得结构的结构示意图；
图39为一实施例中提供的另一种形成第二重分布孔后所得结构的结构示意图；
图40为一实施例中提供的另一种形成转接结构材料层后所得结构的结构示意图；
图41为一实施例中提供的另一种形成转接结构后所得结构的结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。
应当明白，尽管可使用术语第一、第二等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
沟槽电容器，尤其是深沟槽电容器(Deep Trench Capacitor，简称DTC)，具有较高的每单位电容量，可以广泛应用于各种存储器件或半导体集成电路(IC)中。沟槽电容器通常包括设置于沟槽内的多个电极层，以及位于相邻电极层之间的介电层。这样沟槽电容器内位于不同层的各电极层均需要转接封装，使得沟槽电容器的转接封装往往依赖于多次光罩(Mask)工艺。例如，需要通过不同的光罩分别切割对应的电极层，使得各电极层分别裸露，然后再对各电极层进行转接封装。因此，沟槽电容器的转接封装需要较多数量的光罩，导致生产成本较高，而生产效率较低。
基于此，本公开实施例提供了一种沟槽电容器封装结构及其制备方法、半导体结构，可以减少沟槽电容器转接封装时的光罩数量，以降低生产成本，并提高生产效率。
请参阅图1，本公开一些实施例提供了一种沟槽电容器封装结构，包括：衬底10、沟槽电容器C以及转接结构30。衬底10具有沟槽G。沟槽电容器C位于衬底10一侧且填充沟槽G。沟槽电容器C包括：层叠设置的多层电极层21及位于任相邻两层电极层21之间的介电层22；其中，衬底10至顶层介电层22中的任一层结构构成目标层M；位于目标层M背离衬底10一侧的电极层21及介电层22的顶表面与目标层M的顶表面位于同一平面；位于目标层M背离衬底10一侧的电极层21的顶表面构成裸露电极E。转接结构30设置于沟槽电容器C背离衬底10的一侧，并至少与裸露电极E对应连接。
可以理解，衬底10至顶层介电层22中的任一层结构包括：衬底10、任一层介电层22、顶层电极层21之外其他任一层电极层21或者设置于衬底10表面上的任一薄膜结构，例如功能层等。顶层介电层22是指沿远离衬底10的方向层叠于最外层的介电层22，且该介电层22还位于沟槽G的最中心。顶层电极层21是指沿远离衬底10的方向层叠于最外层的电极层21，且该电极层21还位于沟槽G的最中心。顶层介电层22位于顶层电极层21靠近衬底10(包括沟槽G的内壁面)的一侧。
并且，本公开实施例中提及的术语“顶表面”是指各对应层结构平行于衬底10上表面的表面。本公开实施例中，位于目标层M背离衬底10一侧的电极层21及介电层22的顶表面与目标层M的顶表面位于同一平面，表示：位于目标层M背离衬底10一侧的电极层21及介电层22的顶表面可以通过抛光至目标层M顶表面的方式获得；也即，“顶表面”可以为对应层结构的抛光表面。
示例地，电极层21包括多晶硅层、金属层或金属化合物层。金属层或金属化合物层的材料例如包括钛(Ti)、氮化钛(TiN)、钨(W)、钴(Co)、铜(Cu)或铝(Al)等。
示例地，介电层22包括高K介电层。介电层22的材料包括但不限于氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、氧化锆(ZrO2)、氧化钽(Ta2O5)、氧化钛(TiO2)或锶钛氧化物(SrTiO3)等。
此外，电极层21和介电层22的层数及厚度均可以根据实际需求选择设置。可选地，各电极层21的厚度相同或不同，各介电层22的厚度相同或不同。
本公开实施例中，可以通过选定目标层M的方式，于衬底10至顶层介电层22中选择任一层结构作为目标层M，然后通过抛光工艺使位于目标层M背离衬底10一侧的电极层21的顶表面直接形成裸露电极E。如此，位于目标层M背离衬底10一侧的电极层21及介电层2的顶表面与目标层M的顶表面位于同一平面，位于目标层M背离衬底10一侧的电极层21的顶表面构成裸露电极E，可以确保位于目标层M背离衬底10一侧的电极层21无需利用光罩图形化，也可以具有裸露电极E。从而方便后续于前述裸露电极E表面直接形成转接结构30，以使转接结构30至少与该裸露电极E对应连接。进而可以减少沟槽电容器转接封装时的光罩总数量，有利于降低生产成本，并提高生产效率。
在一些实施例中，请继续参阅图1，沟槽电容器封装结构还包括：第一介质层41和第二介质层42。第一介质层41至少覆盖沟槽电容器C，具有多个第一重分布孔H1。第二介质层42覆盖第一介质层41，具有多个第二重分布孔H2。第二重分布孔H2与第一重分布孔H1对应连通，转接结构30设置于第一重分布孔H1及第二重分布孔H2内，并与各电极层21分别对应连接。
示例地，第一介质层41和第二介质层42的材料可以相同，例如包括氧化物，例如为二氧化硅。如此，不仅方便于制备，还便于采用相同工艺对第一介质层41和第二介质层42进行刻蚀，以形成所需图案(即对应的重分布孔)。当然，第一介质层41和第二介质层42的材料不同，也均是允许的。
示例地，第一介质层41和第二介质层42的材料与介电层22的材料不同。
在一些实施例中，转接结构30包括：至少两个接触结构；其中，各接触结构分别与至少一层电极层21对应连接。
此处，可以理解，接触结构匹配第二重分布孔H2的数量设置。并且，同一个接触结构可以用于连接一个或多个第一重分布孔H1内裸露的电极层21部分(包括裸露电极E)。
示例地，如图1中所示，电极层21的层数为三层。转接结构30包括：与第一层电极层21和顶层电极层21二者对应连接的第一接触结构31，以及与第二层电极层21对应连接的第二接触结构32。
示例地，转接结构30采用导电材料形成，例如金属，包括钛(Ti)、钨(W)、钴(Co)、铜(Cu)或铝(Al)等。
在一些实施例中，请继续参阅图1，目标层M为衬底10。各层电极层21的顶表面均与衬底10的顶表面位于同一平面，且构成裸露电极E。转接结构30与各层电极层21的裸露电极E分别对应连接。
此处，衬底10的顶表面即为其上表面。
可选地，衬底10可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。衬底10可以为单层结构，也可以为多层结构。例如，衬底10可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底1可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。
此外，本公开实施例中，各电极层21中由抛光表面形成的裸露电极E暴露于对应的第一重分布孔H1内。并且，顶层电极层21之外其他层电极层21的裸露电极E可以为环形电极。如此，顶层电极层21之外其他相邻两层电极层21对应的第一重分布孔H1可以错位排布，例如可以分别位于顶层电极层21裸露电极E轴线方向的两侧。从而可以合理利用沟槽电容器C背离衬底10的一侧的空间，以容易实现第一重分布孔H1的光刻成型，并降低第一重分布孔H1的光刻难度。
在一些实施例中，衬底10为硅衬底或硅基衬底。衬底10上沟槽G的内壁面可以设置有功能层(图1中未示出)，沟槽电容器C还覆盖功能层。
在一些实施例中，请参阅图2，沟槽电容器封装结构，还包括：功能层11。功能层11位于衬底10和沟槽电容器C之间，并覆盖衬底10表面及沟槽G内壁面。
可选地，功能层11包括钝化层、阻挡层、种子层或具有其他功能的层结构。
在一些实施例中，请继续参阅图2，目标层M为功能层11。各层电极层21的顶表面均与功能层11的顶表面位于同一平面，且构成裸露电极E。转接结构30与各层电极层21的裸露电极E分别对应连接。
此处，各电极层21中由抛光表面形成的裸露电极E暴露于对应的第一重分布孔H1内。并且，可选地，顶层电极层21之外其他层电极层21的裸露电极E可以为环形电极。如此，顶层电极层21之外其他相邻两层电极层21对应的第一重分布孔H1可以错位排布，例如可以分别位于顶层电极层21裸露电极E轴线方向的两侧。从而可以合理利用沟槽电容器C背离衬底10的一侧的空间，以容易实现第一重分布孔H1的光刻成型，并降低第一重分布孔H1的光刻难度。
在一些实施例中，请参阅图3，目标层M为任一层介电层22。位于目标层M靠近衬底10一侧的电极层21的边缘部分与目标层M在至少一个方向上排布成阶梯结构S。转接结构30还与阶梯结构S中电极层21的边缘部分对应连接。
可以理解，位于目标层M靠近衬底10一侧的电极层21及介电层22可以通过光罩进行图形化，以形成阶梯结构S。阶梯结构S可以包括至少一个台阶。
示例地，阶梯结构S包括多个台阶；所述台阶的数量小于或等于位于目标层M靠近衬底10一侧的电极层21的层数。例如，位于目标层M靠近衬底10一侧的每层电极层21的边缘部分均可以形成一个台阶；或者，至少一个台阶可以由目标层M靠近衬底10一侧的至少两层相邻电极层21的边缘部分共同构成。
此外，第一介质层41可以为单层结构，也可以为多层结构。本公开实施例中，第一介质层41为多层结构，例如包括第一子介质层41A和第二子介质层41B，其中，第一子介质层41A覆盖目标层M之外的阶梯结构S，第二子介质层41B覆盖第一子介质层41A、目标层M及各裸露电极E。
在一些示例中，与阶梯结构S中电极层21的层数相关，第一子介质层41A可以为多层结构。例如图3中所示，阶梯结构S中电极层21的层数为两层，第一子介质层41A包括：第一覆盖层411和第二覆盖层412；其中，第一覆盖层411具有容置第一层电极层21的开口且覆盖衬底10或功能层11；第二覆盖层412具有容置第二层电极层21的开口且覆盖第一层电极层21的边缘部分。如此，第一子介质层41A中的各覆盖层可以分别形成于对应电极层21图形化之后，即可以根据各电极层21的图形化需求对应形成。
在一些实施例中，请参阅图4，目标层M为任一层介电层22，位于目标层M背离衬底10一侧的电极层21的厚度大于位于目标层M靠近衬底10一侧的电极层21的厚度。如此，可以增大抛光后形成的裸露电极E的面积，从而增大转接结构30的着陆面积，利于实现后续转接结构30与裸露电极E的过孔连接，并降低其接触不良的风险。
示例地，如图4中所示，电极层21的层数为三层，目标层M为顶层介电层22。位于目标层M靠近衬底10一侧的电极层21包括第一层电极层21和第二层电极层21，其中，第一层电极层21的厚度为T1，第二层电极层21的厚度为T2，T1与T2相等或不等，均可。位于目标层M背离衬底10一侧的电极层21为顶层电极层21，顶层电极层21的厚度为T3，T3＞T1且T3＞T2。
在一些实施例中，请参阅图5，目标层M还可以为顶层电极层21之外任一层电极层21。
在目标层M非第一层电极层21的情况下，位于目标层M靠近衬底10一侧的电极层21的边缘部分与目标层M在至少一个方向上排布成阶梯结构S。转接结构30还与阶梯结构S中电极层21的边缘部分对应连接。
可以理解，位于目标层M靠近衬底10一侧的电极层21及介电层22可以通过光罩进行图形化，以形成阶梯结构S。阶梯结构S可以包括至少一个台阶。
示例地，阶梯结构S包括多个台阶；所述台阶的数量小于或等于位于目标层M靠近衬底10一侧的电极层21的层数。例如，位于目标层M靠近衬底10一侧的每层电极层21的边缘部分均可以形成一个台阶；或者，至少一个台阶可以由目标层M靠近衬底10一侧的至少两层相邻电极层21的边缘部分共同构成。
此外，第一介质层41A可以为单层结构，也可以为多层结构。本公开实施例中，第一介质层41为多层结构，例如包括第一子介质层41A和第二子介质层41B，其中，第一子介质层41A覆盖目标层M之外的阶梯结构S，第二子介质层41B覆盖第一子介质层41A、目标层M及各裸露电极E。
在一些示例中，与阶梯结构S中电极层21的层数相关，第一子介质层41A可以为一层或多层结构，可以根据各电极层21的图形化需求对应形成。例如图5中所示，阶梯结构S中电极层21的层数为两层，其中，第一子介质层41A为一层结构，具有容置第二层电极层21的开口，且覆盖第一层电极层21的边缘部分以及衬底10或功能层11；第二层电极层21为目标层M。
在一些实施例中，请参阅图6，目标层M为顶层电极层21之外的任一层电极层21，目标层M的厚度大于其他电极层21的厚度。如此，可以在抛光至目标层M以形成裸露电极E的过程中，避免作为目标层M的电极层21出现过度抛光，以确保该电极层21的电学性能，从而确保沟槽电容器C的使用可靠性。
请参阅图7，本公开一些实施例还提供了一种沟槽电容器封装结构的制备方法，用于制备上述一些实施例中的沟槽电容器封装结构。包括如下步骤。
S100，提供衬底，衬底具有沟槽。
S200，于衬底一侧及沟槽内形成初始电容器。初始电容器包括层叠设置的多层电极层及位于任相邻两 层电极层之间的介电层。
S300，抛光初始电容器至暴露出目标层并形成至少一个裸露电极；其中，目标层选自衬底至顶层介电层中的任一层结构，裸露电极基于目标层背离衬底的一侧的至少一层电极层形成。
示例地，初始电容器采用化学机械研磨工艺抛光。
S400，形成转接结构，转接结构至少与裸露电极对应连接。
示例地，转接结构采用双大马士革工艺形成。
本公开实施例中，在沟槽内及衬底表面制备初始电容器后，可以通过选定目标层的方式，于衬底至顶层介电层中选择任一层结构作为目标层，然后通过抛光工艺使位于目标层背离衬底一侧的电极层的顶表面直接形成裸露电极。如此，位于目标层背离衬底一侧的电极层及介电层的顶表面与目标层的顶表面位于同一平面，位于目标层背离衬底一侧的电极层的顶表面构成裸露电极，可以确保位于目标层背离衬底一侧的电极层无需利用光罩图形化，也可以具有裸露电极。从而方便后续于前述裸露电极表面直接形成转接结构，以使转接结构至少与该裸露电极对应连接。进而可以减少沟槽电容器转接封装时的光罩总数量，有利于降低生产成本，并提高生产效率。
可以理解，初始电容器中介电层和电极层的数量可以根据需求选择设置。并且，初始电容器的结构也可以有不同的实施，目标层可以匹配初始电容器的结构选自衬底、任一层介电层、顶层电极层之外的任一层电极层或者设置于衬底表面上的任一薄膜结构，例如功能层等。示例地，功能层包括钝化层、阻挡层、种子层或具有其他功能的层结构。本公开实施例中，功能层覆盖衬底表面及沟槽内壁面，功能层的材料及厚度等可以根据实际需求选择设置。
在一些实施例中，目标层为衬底。步骤S200于衬底一侧及沟槽内形成初始电容器，包括：于衬底表面形成交替层叠的电极材料层和介电材料层。
步骤S300抛光初始电容器至暴露出目标层并形成至少一个裸露电极，包括：抛光初始电容器至暴露出衬底，以使各电极材料层的保留部分分别形成电极层，各介电材料层的保留部分分别形成介电层；其中，各层电极层的抛光表面裸露以形成多个裸露电极。
在一些实施例中，目标层为功能层。请参阅图8，步骤S200于衬底一侧及沟槽内形成初始电容器之前，所述制备方法还包括S150。
S150，于衬底表面及沟槽内壁面形成功能层。
相应地，步骤S200于衬底一侧及沟槽内形成初始电容器，还包括：于功能层背离衬底的表面形成交替层叠的电极材料层和介电材料层。
步骤S300抛光初始电容器至暴露出目标层并形成至少一个裸露电极，包括：抛光初始电容器至暴露出功能层，以使各电极材料层的保留部分分别形成电极层，各介电材料层的保留部分分别形成介电层；其中，各层电极层的抛光表面裸露以形成多个裸露电极。
由上，目标层为衬底或功能层时，初始电容器及各裸露电极的制备方法相似。为了更清楚说明上述一些实施例中的制备方法，以下以目标层为功能层为例进行了详述。
请参阅图9，在步骤S200中，于功能层11背离衬底10的表面形成交替层叠的电极材料层2100和介电材料层2200。本公开实施例中，在沉积形成各电极材料层2100和各介电材料层2200之后，即可视为完成了初始电容器2的制备。
示例地，电极材料层2100和介电材料层2200分别采用沉积工艺形成。沉积工艺包括但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或原子层沉积(Atomic Layer Deposition，简称ALD)。并且，电极材料层2100和介电材料层2200的层数及厚度均可以根据实际需求选择设置。可选地，各电极材料层2100的厚度相同，各介电材料层2200的厚度相同。
示例地，电极材料层2100的材料包括多晶硅、金属或金属化合物。金属或金属化合物例如包括钛(Ti)、氮化钛(TiN)、钨(W)、钴(Co)、铜(Cu)或铝(Al)等。
示例地，介电材料层2200的材料包括高K介电材料。高K介电材料包括但不限于氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、氧化锆(ZrO2)、氧化钽(Ta2O5)、氧化钛(TiO2)或锶钛氧化物(SrTiO3)等。
为了方便描述，以下一些实施例中以电极材料层2100的层数为三层且介电材料层2200的层数为两层进行了示例，而更多层电极材料层2100和介电材料层2200的处理工艺可参照其对应执行。
请结合图9和图10理解，在步骤S300中，抛光初始电容器2至暴露出功能层11，以使各电极材料层2100的保留部分分别形成电极层21，各介电材料层2200的保留部分分别形成介电层22；其中，各层电极层21的抛光表面裸露以形成多个裸露电极E。
此处，如图10中所示，在抛光至暴露功能层11之后，各电极层21的抛光表面直接裸露以形成裸露电极E。本公开实施例中，以功能层11为目标层M，可以省去利用多个光罩分别图形化各电极材料层2100的过程，从而有效减小沟槽电容器封装结构制备过程中光罩的使用数量，以最大程度的降低生产成本并提高生产效率。
基于此，请参阅图11，在一些实施例中，步骤S300中抛光初始电容器至暴露出目标层并形成至少一个裸露电极之后，所述制备方法还包括S350。
S350，形成覆盖各裸露电极和目标层的第一介质层。
相应地，请继续参阅图11，步骤S400中形成转接结构，包括如下步骤。
S410，图形化第一介质层，形成多个第一重分布孔；多个裸露电极分别暴露于对应的第一重分布孔内。
S420，形成填充第一重分布孔的牺牲层。
S430，形成覆盖牺牲层及第一介质层的第二介质层。
S440，图形化第二介质层，形成多个第二重分布孔；牺牲层暴露于第二重分布孔内。
S450，去除牺牲层，使第二重分布孔与第一重分布孔对应连通。
S460，于第二重分布孔和第一重分布孔内形成转接结构；转接结构与暴露于各第一重分布孔内的裸露电极分别对应连接。
本公开实施例中，选用衬底或功能层为目标层，并在通过抛光初始电容器的方式形成多个裸露电极之后，可以通过形成第一重分布孔及第二重分布孔的方式，于第二重分布孔和第一重分布孔内形成转接结构，并实现转接结构与各裸露电极的对应连接。本公开实施例中的制备方法易于实施，利于有效提升生产效率并降低生产成本。
在步骤S350中，请参阅图12，形成覆盖各裸露电极E和功能层11(即目标层M)的第一介质层41。
在步骤S410中，请参阅图13和图14，图形化第一介质层41，形成多个第一重分布孔H1；多个裸露电极E分别暴露于对应的第一重分布孔H1内。
示例地，如图13中所示，于第一介质层41表面形成图形化的第一光刻胶层PR1。
请结合图13和图14理解，基于图形化的第一光刻胶层PR1对第一介质层41进行刻蚀，例如干法刻蚀，可以形成多个第一重分布孔H1，以确保各裸露电极E均能暴露于对应的第一重分布孔H1内。
此处，可以理解，任一电极层21中由抛光表面形成的裸露电极E暴露于对应的第一重分布孔H1内。并且，顶层电极层之外其他层电极层21的裸露电极E可以为环形电极。如此，顶层电极层之外其他相邻两层电极层21对应的第一重分布孔H1错位排布，例如可以分别位于顶层电极层裸露电极轴线方向的两侧。从而可以合理利用沟槽电容器背离所述衬底的一侧的空间，以容易实现第一重分布孔H1的光刻成型，并降低第一重分布孔H1的光刻难度。
在步骤S420中，请参阅图15，形成填充第一重分布孔H1的牺牲层50。
示例地，牺牲层50的材料包括但不限于旋涂碳(Spin On Carbon，简称SOC)。牺牲层50采用旋涂工艺形成，利于实现牺牲层50在第一重分布孔H1内的填充，并确保牺牲层50的上表面与第一介质层41的上表面平齐。
在步骤S430中，请参阅图16，形成覆盖牺牲层50及第一介质层41的第二介质层42。
示例地，第一介质层41的第二介质层42的材料相同，例如包括氧化物，例如为二氧化硅。如此，不仅方便于制备，还便于采用相同工艺对第一介质层41的第二介质层42进行刻蚀，以形成所需图案。
在步骤S440中，请参阅图17和图18，图形化第二介质层42，形成多个第二重分布孔H2；牺牲层50暴露于第二重分布孔H2内。
示例地，如图17中所示，于第二介质层42表面形成图形化的第二光刻胶层PR2。
请结合图17和图18理解，基于图形化的第二光刻胶层PR2对第二介质层42进行刻蚀，例如干法刻蚀，可以形成多个第二重分布孔H2，以确保暴露出牺牲层50。
在步骤S450中，请参阅图19，去除牺牲层50，使第二重分布孔H2与第一重分布孔H1对应连通。
在步骤S460中，请参阅图20和图21，于第二重分布孔H2和第一重分布孔H1内形成转接结构30；转接结构5与暴露于各第一重分布孔H内的裸露电极E分别对应连接。
示例地，如图20中所示，沉积形成转接结构材料层300。转接结构材料层300填充第一重分布孔H1和第二重分布孔H2，并覆盖第二介质层42的上表面。如图21中所示，抛光形成转接结构材料层300后的所得结构至暴露出第二介质层42，以使转接结构材料层500保留于第二重分布孔H2和第一重分布孔H1内的部分形成转接结构30，可以确保转接结构30具有较高的表面质量，以利于实现沟槽电容器封装结构后续与其他器件的键合连接。
示例地，如图21中所示，电极层21的层数为三层。转接结构30包括：与第一层电极层21和顶层电极层21二者裸露电极E对应连接的第一接触结构31，以及与第二层电极层21对应连接的第二接触结构32。
在一些实施例中，请参阅图22，步骤S200中于衬底一侧及沟槽内形成初始电容器，包括如下步骤。
S210，于衬底一侧形成交替层叠的电极材料层和介电材料层。
S220，图形化各电极材料层及各介电材料层，形成至少填充沟槽的多层初始电极层和多层初始介电层。
S230，图形化各初始电极层及对应的初始介电层，形成多层电极层和多层介电层；其中，目标层为任一层介电层，位于目标层靠近衬底一侧的电极层的边缘部分与目标层在至少一个方向上排布成阶梯结构；或者，目标层为顶层电极层之外任一层电极层，在目标层非第一层电极层的情况下，目标层靠近衬底一侧的电极层的边缘部分与目标层在至少一个方向上排布成阶梯结构。
此处，位于目标层靠近衬底一侧的电极层的边缘部分与目标层在至少一个方向上排布成阶梯结构，是指：位于目标层靠近衬底一侧的电极层的边缘部分与目标层在至少一个方向上错落，并分别裸露并形成不同的台阶，以便于后续实现转接连接。可选地，阶梯结构包括至少一个台阶，台阶的数量小于或等于目标层靠近衬底一侧的电极层的层数。例如，位于目标层靠近衬底一侧的每层电极层的边缘部分均可以形成一个台阶；或者，至少一个台阶可以由目标层靠近衬底一侧至少两层相邻电极层的边缘部分共同构成。如此，位于目标层背离衬底一侧的电极层无需通过光罩图形化，可以仅针对目标层靠近衬底一侧的电极层进行图形化。
可以理解，初始电容器填充沟槽，初始电容器以第一层电极层开始，顶层电极层结束；并且，相邻电极层之间均具有介电层，以实现相邻电极层的绝缘隔离。如此，每层电极层对应的介电层是指：该电极层靠近衬底一侧并直接接触的介电层。如无特别说明，电极层和对应的介电层可以同步图形化处理。
在一些实施例中，目标层为任一层介电层。如此，通过抛光初始电容器的方式，可以同步暴露出目标层并形成至少一个裸露电极，也即可以确保裸露电极的旁侧具有介电层。如此，在后续形成转接结构的过程中，利于使得转接结构具有较大的工艺尺寸，从而降低转接结构的制备难度，以进一步降低生产成本并提高生产效率。
可选地，位于目标层背离衬底一侧的电极层的形成厚度大于位于目标层靠近衬底一侧的电极层的形成厚度。如此，可以增大抛光后形成的裸露电极的面积，从而增大转接结构的着陆面积，利于实现后续转接结构与裸露电极的过孔连接，并降低其接触不良的风险。
可选地，位于目标层背离衬底一侧的各层初始电极层与位于目标层靠近衬底一侧且与目标层相邻的初始电极层可以通过同一光罩图形化。从而有利于进一步减少图形化初始电极层以形成电极层时的光罩总数量。
在一些实施例中，目标层为顶层电极层之外任一层电极层。目标层的形成厚度大于其他电极层的形成厚度。如此，可以避免作为目标层的电极层出现过度抛光，以确保该电极层的电学性能，从而确保沟槽电容器的使用可靠性。
在上述一些实施例中，目标层选自初始电容器中的任一层结构。请参阅图23，步骤S300抛光初始电容器至暴露出目标层并形成至少一个裸露电极之后，所述制备方法还包括S350'。
S350'，形成至少覆盖阶梯结构、目标层和裸露电极的第一介质层。
基于此，步骤S400形成转接结构，包括如下步骤。
S410'，图形化第一介质层，形成多个第一重分布孔；裸露电极及阶梯结构中各层电极层的边缘部分分别暴露于对应的第一重分布孔内。
S420'，形成填充第一重分布孔的牺牲层。
S430'，形成覆盖牺牲层及第一介质层的第二介质层。
S440'，图形化第二介质层，形成多个第二重分布孔；牺牲层暴露于第二重分布孔内。
S450'，去除牺牲层，使第二重分布孔与第一重分布孔对应连通。
S460'，于第二重分布孔和第一重分布孔内形成转接结构；转接结构与裸露电极、阶梯结构中各层电极层的边缘部分分别对应连接。
本公开实施例中，在通过抛光初始电容器的方式形成裸露电极之后，可以通过形成第一重分布孔及第二重分布孔的方式，于第二重分布孔和第一重分布孔内形成转接结构，并实现转接结构与裸露电极以及阶梯结构中各层电极层边缘部分的对应连接。本公开实施例中转接结构的制备工艺易于实施，利于提升生产效率。
可以理解，上述第一介质层可以为单层结构，也可以为多层结构。本公开实施例中，第一介质层为多层结构，例如包括第一子介质层和第二子介质层，其中，第一子介质层覆盖目标层之外的阶梯结构，第二子介质层覆盖第一子介质层、目标层及各裸露电极。
在一些示例中，与阶梯结构中电极层的层数相关，第一子介质层可以为多层结构。例如阶梯结构中电极层的层数为两层，第一子介质层包括：第一覆盖层和第二覆盖层；其中，第一覆盖层具有容置第一层电极层的开口且覆盖衬底或功能层；第二覆盖层具有容置第二层电极层的开口且覆盖第一层电极层的边缘部分。如此，第一子介质层中的各覆盖层可以分别形成于对应电极层图形化之后，即可以根据各电极层的图形化需求对应形成。
由上，步骤S350'的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤(例如S300)或者其它步骤(例如S300)的子步骤或者阶段的至少一部分轮流或者交替地执行。步骤S350'和S300的执行并没有严格的顺序限制。
在上述一些实施例中，目标层选自初始电容器中的任一层结构。为了更清楚说明上述一些实施例中的制备方法，以下以目标层为顶层介电层为例进行了详述。在以其他介电层或电极层为目标层的一些实施方式中，裸露电极及阶梯结构中其他需要单独图形化的电极层可以参照相应的制备工艺形成，本公开实施例中不再展开详述。
在步骤S210中，请参阅图24，于衬底10一侧形成交替层叠的电极材料层2100和介电材料层2200。
可选地，衬底10表面形成有功能层11。电极材料层2100和介电材料层2200交替层叠于功能层11背离衬底10的表面。
示例地，电极材料层2100和介电材料层2200分别采用沉积工艺形成。沉积工艺包括但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或原子层沉积(Atomic Layer Deposition，简称ALD)。并且，电极材料层2100和介电材料层2200的层数及厚度均可以根据实际需求选择设置。可选地，各电极材料层2100的厚度相同，各介电材料层2200的厚度相同。
示例地，电极材料层2100的材料包括多晶硅、金属或金属化合物。金属或金属化合物例如包括钛(Ti)、氮化钛(TiN)、钨(W)、钴(Co)、铜(Cu)或铝(Al)等。
示例地，介电材料层2200的材料包括高K介电材料。高K介电材料包括但不限于氧化铝(Al2O3)、 氧化铪(HfO2)、氮氧化铪(HfON)、氧化锆(ZrO2)、氧化钽(Ta2O5)、氧化钛(TiO2)或锶钛氧化物(SrTiO3)等。
为了方便描述，以下一些实施例中以电极材料层层数为三层且介电材料层层数为两层进行了示例，而更多层电极材料层和介电材料层的处理工艺可参照其对应执行。
在步骤S220中，请参阅图25和图26，图形化各电极材料层2100及各介电材料层2200，形成至少填充沟槽G的多层初始电极层210和多层初始介电层220。
可选地，功能层11覆盖衬底10，可以对衬底10表面进行保护，并有效隔离衬底10及第一层初始电极层210。并且，如图25中所示，可以先于顶层电极材料层2100表面形成图形化的第三光刻胶层PR3，然后基于图形化的第三光刻胶层PR3对各电极材料层2100和对应的介电材料层2200进行刻蚀，例如干法刻蚀。从而获得多层初始电极层210和多层初始介电层220如图26中所示。
在步骤S230中，请参阅图27～图32，图形化各初始电极层210及对应的初始介电层220，以形成多层电极层21和多层介电层22；其中，目标层M为任一层介电层22，位于目标层M靠近衬底10一侧的电极层21的边缘部分与目标层M在至少一个方向上排布成阶梯结构S；或者，目标层M为顶层电极层21之外任一层电极层21，在目标层M非第一层电极层21的情况下，目标层M靠近衬底10一侧的电极层21的边缘部分与目标层M在至少一个方向上排布成阶梯结构。
本公开实施例中，示例地，目标层M为顶层介电层22。
在步骤S350'，请参阅图27～图33，形成至少覆盖阶梯结构S、目标层M和裸露电极E的第一介质层41。
示例地，如图33中所示，第一介质层41包括第一子介质层41A和第二子介质层41B。第一子介质层41包括第一覆盖层411和第二覆盖层412。第一覆盖层411可以形成于第一层电极层21形成之后，第二覆盖层412可以形成于第二层电极层21形成之后。此处，可以理解，在初始电极层210为更多层的示例中，第一子介质层41A还可以对应包括更多的覆盖层。
示例地，请参阅图26和图27，在步骤S220形成多层初始电极层210和多层初始介电层220之后，沉积第一覆盖材料层4110，以覆盖功能层11、各初始电极层210和初始介电层220的侧壁、以及顶层初始电极层210。第一覆盖材料层4110的沉积厚度大于衬底10上方各初始电极层210和各初始介电层220的厚度之和。
请参阅图28，抛光第一覆盖材料层4110，以形成表面平整的第一初始覆盖层411B。
请参阅图29，于第一初始覆盖层411B表面形成图形化的第四光刻胶层PR4。
在电极层21为三层且目标层M为顶层介电层22的示例中，请结合图29和图30理解，基于图形化的第四光刻胶层PR4对第一初始覆盖层411B及各初始电极层210和各初始介电层220进行刻蚀，以形成第一覆盖层411A和第一层电极层21，并使第一层电极层21的边缘部分裸露，形成第一台阶B1。并且，如图30中所示，第二层电极层21的边缘部分可以同步构成第二台阶B2。从而，第一台阶B1和第二台阶B2可以构成阶梯结构S。
需要补充的是，在一些实施例中，目标层M为任一层介电层22，位于目标层M背离衬底10一侧的各层初始电极层210可以与位于目标层M靠近衬底10一侧且相邻的初始电极层210通过同一光罩图形化。例如，目标层M可以选自顶层介电层22。在初始电极层210为三层或更多层的示例中，顶层初始电极层210和次顶层初始电极层210可以通过同一光罩图形化。其中，顶层初始电极层210位于目标层M(即顶层介电层22)背离衬底10的一侧，次顶层初始电极层210位于目标层M(即顶层介电层)靠近衬底10的一侧，顶层初始电极层210和次顶层初始电极层210为相邻设置的两层初始电极层210。并且，顶层初始介电层220位于顶层初始电极层210和次顶层初始电极层210之间，顶层初始电极层210和次顶层初始电极层210通过同一光罩图形化时，顶层初始介电层220可以同步图形化以形成顶层介电层22。进一步地，次顶层初始介电层220也可以与前述顶层初始电极层210、顶层初始介电层220和次顶层初始电极层210同步图形化，以形成次顶层介电层220，并暴露出其靠近衬底10的一侧初始电极层210的边缘部分。如此，在初始电极层210为三层的示例中，阶梯结构S可以通过一次光罩工艺形成。此外，选择顶层介电层22为目标层M，顶层电极层21可以通过抛光工艺直接形成裸露电极E，而无需利用光罩图形化。
在电极层21为三层且目标层为顶层介电层的示例中，请参阅图31，沉积形成第二覆盖层412A。第二覆盖层412A可以在顶层电极层21采用抛光工艺形成裸露电极E之前进行。如此，第二覆盖层412A覆盖第一覆盖层411A以及前述阶梯结构S中第一台阶B1的上表面及第二台阶B2的侧壁。第二覆盖层412A和第一覆盖层411A共同构成第一初始子介质层。第二覆盖层412A和第一覆盖层411A的材料相同或不同，均可。
由上，完成了初始电容器2的制备。
基于此，在形成第一初始子介质层之后，请参阅图32，目标层M为顶层介电层，步骤S300中抛光初始电容器至暴露出目标层并形成至少一个裸露电极，还包括：抛光第一初始子介质层和顶层电极层21，以暴露出顶层介电层(即目标层M)，并使顶层电极层21的保留部分形成裸露电极E，使第一初始子介质层的保留部分形成第一子介质层41A。
示例地，如图32中所示，第一子介质层41A包括抛光后的第一覆盖层411和抛光后的第二覆盖层412。
请参阅图33，形成覆盖裸露电极E、目标层M和第一子介质层41A的第二子介质层42A。第一子介质层41A和第二子介质层42A共同构成第一介质层41。
在步骤S410'中，请参阅图34和图35，图形化第一介质层41，形成多个第一重分布孔H1；裸露电极 E及阶梯结构S中各层电极层21的边缘部分分别暴露于对应的第一重分布孔H1内。
示例地，如图34中所示，于第一介质层41表面形成图形化的第五光刻胶层PR5。
请结合图34和图35理解，基于图形化的第五光刻胶层PR5对第一介质层41及顶层介电层(即目标层M)进行刻蚀，例如干法刻蚀，可以形成多个第一重分布孔H1，以确保裸露电极E及阶梯结构S中各层电极层21的边缘部分均能暴露于对应的第一重分布孔H1内。可以理解，在目标层M为电极层21的示例中，无需对目标层M刻蚀以形成第一重分布孔H1。
在一些实施例中，目标层M为任一层介电层22；目标裸露电极E对应的第一重分布孔H1内还暴露出部分目标层M；目标裸露电极E位于目标层M背离衬底10一侧并与目标层M相邻。
此处，可选地，如图35中所示，裸露电极E对应的第一重分布孔H1内还暴露出部分顶层介电层(即目标层M)。
可以理解，在抛光顶层电极层形成裸露电极E后，裸露电极E上表面与目标层M上表面平齐，裸露电极E与次顶层电极层21之间可以通过目标层M有效隔离。如此，裸露电极E对应的第一重分布孔H1可以具有较大的工艺尺寸，例如可以暴露出部分顶层介电层，从而可以降低第一重分布孔H1的刻蚀精度，以进一步降低生产成本并提高生产效率。
在步骤S420'中，请参阅图36，形成填充第一重分布孔H1的牺牲层50。此处，牺牲层50的上表面与第一介质层41的上表面平齐。
在步骤S430'中，请参阅图37，形成覆盖牺牲层50及第一介质层41的第二介质层42。
在步骤S440'和S450'中，请参阅图38和39，图形化第二介质层42，形成多个第二重分布孔H2；牺牲层50暴露于第二重分布孔H2内。去除牺牲层50，使第二重分布孔H2与第一重分布孔H1对应连通。
示例地，如图38中所示，于第二介质层42表面形成图形化的第六光刻胶层PR6。
请结合图38和图39理解，基于图形化的第六光刻胶层PR6对第二介质层42进行刻蚀，例如干法刻蚀，可以形成多个第二重分布孔H2，以确保牺牲层50暴露于对应的第二重分布孔H2内。
在步骤S460'中，请参阅图40和图41，于第二重分布孔H2和第一重分布孔H1内形成转接结构30；转接结构30与裸露电极E、阶梯结构S中各层电极层21的边缘部分分别对应连接。
示例地，如图40中所示，沉积形成转接结构材料层300。转接结构材料层300填充第一重分布孔H1和第二重分布孔H2，并覆盖第二介质层42的上表面。如图41中所示，抛光形成转接结构材料层300后的所得结构至暴露出第二介质层42，以使转接结构材料层300保留于第二重分布孔H2和第一重分布孔H1内的部分形成转接结构30，可以确保转接结构30具有较高的表面质量，以利于实现沟槽电容器封装结构后续与其他器件的键合连接。
示例地，如图41中所示，电极层21的层数为三层。转接结构30包括：与第一层电极层21和顶层电极层(即裸露电极E)对应连接的第一接触结构31，以及与第二层电极层对应连接的第二接触结构32。
需要说明的是，在一些实施例中，第一介质层41和第二介质层42的材料相同。第一介质层41和第二介质层42的材料与介电层22(即介电材料层2200)的材料不同。示例地，第一介质层41和第二介质层42的材料包括氧化物，例如为二氧化硅。如此，不仅方便于制备，还便于采用相同工艺对第一介质层41和第二介质层42进行刻蚀，以形成所需图案。
在一些实施例中，牺牲层50的材料包括但不限于旋涂碳(Spin On Carbon，简称SOC)。牺牲层50采用旋涂工艺形成，利于实现牺牲层50在第一重分布孔H1内的填充，并确保牺牲层50的上表面与第一介质层41的上表面平齐。
又一方面，本公开一些实施例提供了一种半导体结构，包括：如上任一实施例所述的沟槽电容器封装结构。
示例地，半导体结构可以为存储器件。或者，半导体结构可以为无源器件，例如转接板。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种沟槽电容器封装结构，其特征在于，包括：
    衬底(10)，具有沟槽(G)；
    沟槽电容器(C)，位于所述衬底(10)一侧且填充所述沟槽(G)；所述沟槽电容器(C)包括：层叠设置的多层电极层(21)及位于任相邻两层所述电极层(21)之间的介电层(22)；其中，所述衬底(10)至顶层所述介电层(22)中的任一层结构构成目标层(M)；位于所述目标层(M)背离所述衬底(10)一侧的所述电极层(21)及所述介电层(22)的顶表面与所述目标层(M)的顶表面位于同一平面；位于所述目标层(M)背离所述衬底(10)一侧的所述电极层(21)的所述顶表面构成裸露电极(E)；
    以及，转接结构(30)，设置于所述沟槽电容器(C)背离所述衬底(10)的一侧，并至少与所述裸露电极(E)对应连接。
  2. 根据权利要求1所述的沟槽电容器封装结构，其特征在于，所述目标层(M)为所述衬底(10)；各层所述电极层(21)的顶表面均与所述衬底(10)的顶表面位于同一平面，且构成所述裸露电极(E)；所述转接结构(30)与各层所述电极层(21)的所述裸露电极(E)分别对应连接。
  3. 根据权利要求1所述的沟槽电容器封装结构，其特征在于，还包括：
    功能层(11)，位于所述衬底(10)和所述沟槽电容器(C)之间，并覆盖所述衬底(10)表面及所述沟槽(G)内壁面；
    其中，所述目标层(M)为所述功能层(11)；各层所述电极层(21)的顶表面均与所述功能层(11)的顶表面位于同一平面，且构成所述裸露电极(E)；所述转接结构(30)与各层所述电极层(21)的所述裸露电极(E)分别对应连接。
  4. 根据权利要求1所述的沟槽电容器封装结构，其特征在于，所述目标层(M)为任一层所述介电层(22)；
    位于所述目标层(M)靠近所述衬底(10)一侧的所述电极层(21)的边缘部分与所述目标层(M)在至少一个方向上排布成阶梯结构(S)；所述转接结构(30)还与所述阶梯结构(S)中所述电极层(21)的边缘部分对应连接。
  5. 根据权利要求4所述的沟槽电容器封装结构，其特征在于，位于所述目标层(M)背离所述衬底(10)一侧的所述电极层(21)的厚度大于位于所述目标层(M)靠近所述衬底(10)一侧的所述电极层(21)的厚度。
  6. 根据权利要求1所述的沟槽电容器封装结构，其特征在于，
    所述目标层(M)为顶层所述电极层(21)之外任一层所述电极层(21)；
    在所述目标层(M)非第一层所述电极层(21)的情况下，位于所述目标层(M)靠近所述衬底(10)一侧的所述电极层(21)的边缘部分与所述目标层(M)在至少一个方向上排布成阶梯结构(S)；所述转接结构(30)还与所述阶梯结构(S)中所述电极层(21)的边缘部分对应连接。
  7. 根据权利要求6所述的沟槽电容器封装结构，其特征在于，所述目标层(M)的厚度大于其他所述电极层(21)的厚度。
  8. 根据权利要求1～7中任一项所述的沟槽电容器封装结构，其特征在于，还包括：
    第一介质层(41)，至少覆盖所述沟槽电容器(C)，具有多个第一重分布孔(H1)；
    第二介质层(42)，覆盖所述第一介质层(41)，具有多个第二重分布孔(H2)；
    其中，所述第二重分布孔(H2)与所述第一重分布孔(H1)对应连通，所述转接结构(30)设置于所述第一重分布孔(H1)及所述第二重分布孔(H2)内，并与各所述电极层(21)分别对应连接。
  9. 根据权利要求1～8中任一项所述的沟槽电容器封装结构，其特征在于，所述转接结构(30)包括：至少两个接触结构(31和32)；其中，各所述接触结构(31或32)分别与至少一层所述电极层(21)对应连接。
  10. 一种沟槽电容器封装结构的制备方法，其特征在于，包括：
    提供衬底(10)，所述衬底(10)具有沟槽(G)；
    于所述衬底(10)一侧及所述沟槽(G)内形成初始电容器(2)；所述初始电容器(2)包括：层叠设置的多层电极层(21)及位于任相邻两层所述电极层(21)之间的介电层(22)；
    抛光所述初始电容器(2)至暴露出目标层(M)并形成至少一个裸露电极(E)；其中，所述目标层(M)选自所述衬底(10)至顶层所述介电层(22)中的任一层结构，所述裸露电极(E)基于所述目标层(M)背离所述衬底(10)的一侧的至少一层所述电极层(21)形成；
    形成转接结构(30)，所述转接结构(30)至少与所述裸露电极(E)对应连接。
  11. 根据权利要求10所述的沟槽电容器封装结构的制备方法，其特征在于，所述目标层(M)为所述衬底(10)；
    所述于所述衬底(10)一侧及所述沟槽(G)内形成初始电容器(2)，包括：于所述衬底(10)表面形成交替层叠的电极材料层(2100)和介电材料层(2200)；
    所述抛光所述初始电容器(2)至暴露出目标层(M)并形成至少一个裸露电极(E)，包括：抛光所述初始电容器(2)至暴露出所述衬底(10)，以使各所述电极材料层(2100)的保留部分分别形成电极层(21)，各所述介电材料层(2200)的保留部分分别形成介电层(22)；其中，各层所述电极层(21)的抛光表面裸露以形成多个所述裸露电极(E)。
  12. 根据权利要求10所述的沟槽电容器封装结构的制备方法，其特征在于，
    所述于所述衬底(10)一侧及所述沟槽(G)内形成初始电容器(2)之前，所述制备方法还包括：于所述衬底(10)表面及所述沟槽(G)内壁面形成功能层(11)；
    所述于所述衬底(10)一侧及所述沟槽(G)内形成初始电容器(2)，还包括：于所述功能层(11)背离所述衬底(10)的表面形成交替层叠的电极材料层(2100)和介电材料层(2200)；
    其中，所述目标层(M)为所述功能层(11)；
    所述抛光所述初始电容器(2)至暴露出目标层(M)并形成至少一个裸露电极(E)，包括：抛光所述初始电容器(2)至暴露出所述功能层(11)，以使各所述电极材料层(2100)的保留部分分别形成电极层(21)，各所述介电材料层(2200)的保留部分分别形成介电层(22)；其中，各层所述电极层(21)的抛光表面裸露以形成多个所述裸露电极(E)。
  13. 根据权利要求11或12中任一项所述的沟槽电容器封装结构的制备方法，其特征在于，所述抛光所述初始电容器(2)至暴露出目标层(M)并形成至少一个裸露电极(E)之后，所述制备方法还包括：形成覆盖各所述裸露电极(E)和所述目标层(M)的第一介质层(41)；
    所述形成转接结构(30)，包括：
    图形化所述第一介质层(41)，形成多个第一重分布孔(H1)；多个所述裸露电极(E)分别暴露于对应的所述第一重分布孔(H1)内；
    形成填充所述第一重分布孔(H1)的牺牲层(50)；
    形成覆盖所述牺牲层(50)及所述第一介质层(41)的第二介质层(42)；
    图形化所述第二介质层(42)，形成多个第二重分布孔(H2)；所述牺牲层(50)暴露于所述第二重分布孔(H2)内；
    去除所述牺牲层(50)，使所述第二重分布孔(H2)与所述第一重分布孔(H1)对应连通；
    于所述第二重分布孔(H2)和所述第一重分布孔(H1)内形成所述转接结构(30)；所述转接结构(30)与暴露于各所述第一重分布孔(H1)内的所述裸露电极(E)分别对应连接。
  14. 根据权利要求10所述的沟槽电容器封装结构的制备方法，其特征在于，所述于所述衬底(10)一侧及所述沟槽内形成初始电容器，包括：
    于所述衬底(10)一侧形成交替层叠的电极材料层(2100)和介电材料层(2200)；
    图形化各所述电极材料层(2100)及各所述介电材料层(2200)，形成至少填充所述沟槽(G)的多层初始电极层(210)和多层初始介电层(220)；
    图形化各所述初始电极层(210)及对应的所述初始介电层(220)，形成多层所述电极层(21)和多层所述介电层(22)；其中，所述目标层(M)为任一层所述介电层(22)，位于所述目标层(M)靠近所述衬底(10)一侧的所述电极层(21)的边缘部分与所述目标层(M)在至少一个方向上排布成阶梯结构(S)；或者，所述目标层(M)为顶层所述电极层(21)之外任一层所述电极层(21)，在所述目标层(M)非第一层所述电极层(21)的情况下，所述目标层(M)靠近所述衬底(10)一侧的所述电极层(21)的边缘部分与所述目标层(M)在至少一个方向上排布成阶梯结构(S)。
  15. 根据权利要求14所述的沟槽电容器封装结构的制备方法，其特征在于，所述目标层(M)为任一层所述介电层(22)；位于所述目标层(M)背离所述衬底(10)一侧的所述电极层(21)的形成厚度大于位于所述目标层(M)靠近所述衬底(10)一侧的所述电极层(21)的形成厚度。
  16. 根据权利要求14或15所述的沟槽电容器封装结构的制备方法，其特征在于，所述目标层(M)为任一层所述介电层(22)；位于所述目标层(M)背离所述衬底(10)一侧的各层所述初始电极层(210)与位于所述目标层(M)靠近所述衬底(10)一侧且与所述目标层(M)相邻的所述初始电极层(210)通过同一光罩图形化。
  17. 根据权利要求14所述的沟槽电容器封装结构的制备方法，其特征在于，所述目标层(M)为顶层所述电极层(21)之外任一层所述电极层(21)；所述目标层(M)的形成厚度大于其他所述电极层(21)的形成厚度。
  18. 根据权利要求14～17中任一项所述的沟槽电容器封装结构的制备方法，其特征在于，所述抛光所述初始电容器(2)至暴露出目标层(M)并形成至少一个裸露电极(E)之后，所述制备方法还包括：形成至少覆盖所述阶梯结构(S)、所述目标层(M)和所述裸露电极(E)的第一介质层(41)；
    所述形成转接结构(30)，包括：
    图形化所述第一介质层(41)，形成多个第一重分布孔(H1)；所述裸露电极(E)及所述阶梯结构(S)中各层所述电极层(21)的边缘部分分别暴露于对应的所述第一重分布孔(H1)内；
    形成填充所述第一重分布孔(H1)的牺牲层(50)；
    形成覆盖所述牺牲层(50)及所述第一介质层(41)的第二介质层(42)；
    图形化所述第二介质层(42)，形成多个第二重分布孔(H2)；所述牺牲层(50)暴露于所述第二重分布孔(H2)内；
    去除所述牺牲层(50)，使所述第二重分布孔(H2)与所述第一重分布孔(H1)对应连通；
    于所述第二重分布孔(H2)和所述第一重分布孔(H1)内形成所述转接结构(30)；所述转接结构(30)与所述裸露电极(E)、所述阶梯结构(S)中各层所述电极层(21)的边缘部分分别对应连接。
  19. 根据权利要求18所述的沟槽电容器封装结构的制备方法，其特征在于，所述目标层(M)为任一层所述介电层(22)；目标所述裸露电极(E)对应的所述第一重分布孔(H1)内还暴露出部分所述 目标层(M)；目标所述裸露电极(E)位于所述目标层(M)背离所述衬底(10)一侧并与所述目标层(M)相邻。
  20. 一种半导体结构，其特征在于，包括：如权利要求1～9中任一项所述的沟槽电容器封装结构。
PCT/CN2023/086127 2022-09-29 2023-04-04 沟槽电容器封装结构及其制备方法、半导体结构 WO2024066278A1 (zh)

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