WO2024065989A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2024065989A1
WO2024065989A1 PCT/CN2022/133246 CN2022133246W WO2024065989A1 WO 2024065989 A1 WO2024065989 A1 WO 2024065989A1 CN 2022133246 W CN2022133246 W CN 2022133246W WO 2024065989 A1 WO2024065989 A1 WO 2024065989A1
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Prior art keywords
layer
bit line
sub
landing pad
initial
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English (en)
French (fr)
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陆勇
宋小杰
陈晓鹏
韩凯
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections

Definitions

  • the present disclosure relates to the semiconductor field, and in particular to a semiconductor structure and a method for manufacturing the same.
  • DRAM Dynamic Random Access Memory
  • Each storage cell usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.
  • the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can at least improve the reliability of the semiconductor structure.
  • an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate; a bit line structure, wherein the bit line structure is located on the substrate and is arranged at intervals; a capacitor contact structure, located between adjacent bit line structures, wherein the capacitor contact structure comprises: a contact plug, a landing pad, and a barrier layer located between the landing pad and the contact plug, wherein the top surface of the contact plug is lower than the top surface of the bit line structure; wherein the top of the contact plug comprises a transition layer, and the barrier layer is also located between the transition layer and the bit line structure.
  • the barrier layer includes: a first sub-barrier layer, the first sub-barrier layer covers a side wall of the transition layer facing the bit line structure; and a second sub-barrier layer, the second sub-barrier layer covers a top surface of the transition layer.
  • the thickness of the first sub-blocking layer is 0.2-2 nm.
  • the first sub-blocking layer and the second sub-blocking layer are made of the same material, including titanium nitride or tantalum nitride.
  • the material of the contact plug includes silicon, and the material of the transition layer includes cobalt silicide, nickel silicide or titanium silicide.
  • the material of the landing pad includes: tungsten, aluminum or copper.
  • the bit line structure includes a bit line body and a sidewall isolation layer, the sidewall isolation layer is located on the side wall of the bit line body facing the capacitor contact structure, the barrier layer is also located between the landing pad and the sidewall isolation layer, and the sidewall isolation layer is a multi-layer composite structure.
  • the sidewall isolation layer includes, in sequence from the bit line body toward the capacitor contact structure: a first insulating layer, an air gap layer, and a second insulating layer.
  • the first sub-barrier layer and the second sub-barrier layer are further located on a sidewall of the landing pad facing the bit line structure.
  • the landing pad also covers a portion of a top surface of one of the two bit line structures adjacent to the capacitor contact structure.
  • the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a bit line structure, wherein the bit line structure is located on the substrate, and a plurality of the bit line structures are arranged at intervals; forming a capacitor contact structure, wherein the capacitor contact structure comprises: a contact plug, a landing pad, and a barrier layer located between the landing pad and the contact plug, wherein a top surface of the contact plug is lower than a top surface of the bit line structure, wherein a top portion of the contact plug comprises a transition layer, and the barrier layer is also located between the transition layer and the bit line structure.
  • the method of forming the barrier layer includes: forming a first sub-barrier layer, the first sub-barrier layer covers the side wall of the transition layer facing the bit line structure; forming a second sub-barrier layer, the second sub-barrier layer covers the top surface of the transition layer.
  • the method of forming the first sub-blocking layer includes: forming a first initial blocking layer, the first initial blocking layer covering the side walls of the bit line structure and the top surface of the bit line structure; etching the first initial blocking layer, the remaining first initial blocking layer covering the side walls of the bit line structure, and the remaining first initial blocking layer serving as the first sub-blocking layer.
  • the method for forming the transition layer includes: forming a metal conductive layer, the metal conductive layer being located on the top surface of the contact plug; using an annealing process to react the metal conductive layer with the contact plug to form a transition layer; and removing the metal conductive layer.
  • the method of forming the landing pad includes: forming an initial landing pad, the initial landing pad covering the top surface of the bit line structure, and the initial landing pad also covering the side wall of the barrier layer; etching the initial landing pad so that the remaining initial landing pad covers a portion of the top surface of one of the two bit line structures adjacent to the capacitor contact structure, and the remaining initial landing pad serves as the landing pad.
  • the method for forming the bit line structure includes: forming a bit line body, wherein the bit line body is located on the substrate and arranged at intervals; forming an initial side wall isolation layer, wherein the initial side wall isolation layer is located on the side wall of the bit line body facing the capacitor contact structure; etching a portion of the initial side wall isolation layer to expose the top surface of the substrate, and the remaining initial side wall isolation layer serves as a side wall isolation layer, and the side wall isolation layer and the bit line body constitute the bit line structure.
  • the method for forming the initial sidewall isolation layer includes: forming a first insulating layer, the first insulating layer is located on the side wall of the bit line body facing the capacitor contact structure; forming a dielectric layer, the dielectric layer is located on the side wall of the first insulating layer facing the capacitor contact structure; forming a second insulating layer, the second insulating layer is located on the side wall of the dielectric layer facing the capacitor contact structure.
  • FIG1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIGS. 2 to 8 are schematic structural diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • the present disclosure implements a semiconductor structure, wherein a capacitor contact structure is disposed between adjacent bit line structures, and the capacitor contact structure includes: a contact plug, a landing pad, and a barrier layer between the landing pad and the contact plug, and the barrier layer is also located between a transition layer and the bit line structure.
  • the barrier layer is used to protect the transition layer, thereby preventing subsequent process steps from affecting the transition layer, thereby improving the reliability of the semiconductor structure.
  • Figure 1 is a semiconductor structure provided by an embodiment of the present disclosure, including: a substrate 100; a bit line structure 110, the bit line structure 110 is located on the substrate 100 and is arranged at intervals; a capacitor contact structure 120, located between adjacent bit line structures 110, the capacitor contact structure 120 includes: a contact plug 121, a landing pad 122 and a barrier layer 123 located between the landing pad 122 and the contact plug 121, the top surface of the contact plug 121 is lower than the top surface of the bit line structure 110; wherein the top of the contact plug 121 includes a transition layer 124, and the barrier layer 123 is also located between the transition layer 124 and the bit line structure 110.
  • the embodiment of the present disclosure reads data information in a storage unit by setting a bit line structure 110 located on a substrate 100, or writes data information into a storage unit for storage through the bit line structure 110, and can lead out a signal of the capacitor by setting a capacitor contact structure 120, or facilitates storing a signal in the capacitor, and is electrically connected to the substrate 100 through a contact plug 121.
  • the electrical signal of the contact plug 121 can be led out by setting a landing pad 122, and an abnormality caused by a large difference between the landing pad 122 and the contact plug 121 can be avoided by setting a transition layer 124.
  • the transition layer 124 can be protected by setting a barrier layer 123 located between the transition layer 124 and the bit line structure 110, thereby preventing the transition layer 124 from being affected by other process steps, thereby improving the reliability of the semiconductor structure.
  • the substrate 100 is a semiconductor material, and the semiconductor material includes but is not limited to any one of a silicon substrate, a germanium substrate, a germanium silicon substrate, or a silicon carbide substrate.
  • the substrate 100 may also be an ion-doped substrate, and the doped ions are N-type ions or P-type ions, and the N-type ions may specifically be phosphorus ions, arsenic ions, or antimony ions, and the P-type ions may specifically be boron ions, indium ions, or boron fluoride ions.
  • the bit line structure 110 includes a bit line body 111 and a sidewall isolation layer 112.
  • the sidewall isolation layer 112 is located on the side wall of the bit line body 111 facing the capacitor contact structure 120.
  • the barrier layer 123 is also located between the landing pad 122 and the sidewall isolation layer 112.
  • the sidewall isolation layer 112 is a multi-layer composite structure.
  • the bit line body 111 is the part of the bit line structure 110 used to read the data information in the storage unit, or write the data information into the storage unit for storage through the bit line structure 110
  • the sidewall isolation layer 112 is the part that isolates the bit line structure 110 from other structures that do not need to be electrically connected.
  • the reliability of the semiconductor structure can be improved by the sidewall isolation layer 112.
  • the barrier layer 123 between the landing pad 122 and the sidewall isolation layer 112 the landing pad 122 can be prevented from being contaminated by the side wall directly opposite to the sidewall isolation layer 112 in the process step of forming the sidewall isolation layer 112 or in the process step after the sidewall isolation layer 112 is formed, thereby improving the reliability of the semiconductor structure.
  • the bit line body 111 may include a bit line conductive layer 130 and a bit line protective layer 140.
  • the bit line protective layer 140 may be located on the top surface of the bit line conductive layer 130.
  • the bit line conductive layer 130 is the portion of the bit line body 111 used for conduction, and the bit line protective layer 140 is the portion used to protect the bit line body 111.
  • the bit line conductive layer 130 may be used to read data information in a storage unit, or the bit line conductive layer 130 may be used to write data information into a storage unit for storage.
  • the bit line protective layer 140 may protect the bit line conductive layer 130 from being affected in subsequent process steps, and the bit line protective layer 140 may be used to isolate the bit line conductive layer 130 from the outside world. Therefore, when the bit line structure 110 is subjected to external stress, a portion of the stress may be absorbed by the bit line protective layer 140, thereby reducing the stress on the bit line conductive layer 130.
  • the bit line conductive layer 130 may be a stack of multiple film layers, or may be a single film layer.
  • the material of the bit line conductive layer 130 may include metal materials such as tungsten, cobalt or nickel, and may also include some commonly used metal semiconductor compound materials, such as cobalt silicide, nickel silicide or titanium silicide.
  • bit line protection layer 140 may also be a stack of multiple film layers, or may also be a single film layer.
  • the material of the bit line protection layer 140 may include insulating materials such as silicon nitride or silicon oxide.
  • the sidewall spacer 112 includes: a first insulating layer 150, an air gap layer 160, and a second insulating layer 170 in sequence from the bitline body 111 toward the capacitor contact structure 120. It can be understood that since both the bitline structure 110 and the capacitor contact structure 120 are conductive structures, a parasitic capacitor is formed between the bitline structure 110 and the capacitor contact structure 120. The parasitic capacitor between the bitline structure 110 and the capacitor contact structure 120 can be reduced by setting the structure of the sidewall spacer 112 to include the first insulating layer 150, the air gap layer 160, and the second insulating layer 170 in sequence. The larger the volume of the air gap and the more complete the morphology, the lower the parasitic capacitor between the bitline structure 110 and the capacitor contact structure 120.
  • the material of the first insulating layer 150 may be the same as that of the second insulating layer 170 , for example, both may be silicon nitride materials.
  • the thickness distribution of the second insulating layer 170 in the direction perpendicular to the surface of the substrate 100 is that the thickness of the second insulating layer 170 located in the upper portion is thinner than the thickness of the second insulating layer 170 located in the lower portion.
  • this thinner portion of the second insulating layer 170 is also the portion through which contaminants can easily penetrate in subsequent process steps. Therefore, by forming a first sub-blocking layer 180 to cover the thinner side wall of the second insulating layer 170, contaminants can be prevented from penetrating through the second insulating layer 170 to contaminate the capacitor contact structure 120, thereby improving the reliability of the semiconductor structure.
  • the material of the contact plug 121 may include silicon, and the material of the transition layer 124 may include: cobalt silicide, nickel silicide or titanium silicide, etc.
  • the interface state between the contact plug 121 and the substrate 100 can be reduced, thereby improving the reliability of the semiconductor structure.
  • the material of the transition layer 124 to be a metal semiconductor compound By controlling the material of the transition layer 124 to be a metal semiconductor compound, the contact resistance between the transition layer 124 and the contact plug 121 can be reduced, thereby improving the performance of the semiconductor structure.
  • the material of the landing pad 122 includes: tungsten, aluminum or copper. It can be understood that tungsten, aluminum or copper have better conductivity. By setting the material of the landing pad 122 to aluminum or copper, the conductivity of the landing pad 122 can be improved, and the conduction time of the electrical signal can be reduced, thereby improving the response speed of the semiconductor structure.
  • the landing pad 122 may be made of other metallic materials. In still other embodiments, the landing pad 122 may be made of other conductive materials.
  • the landing pad 122 also covers a portion of the top surface of one of the two bit line structures 110 adjacent to the capacitor contact structure 120. Taking the figure as an example, in the figure, the landing pad 122 is located on a portion of the top surface of the bit line structure 110 on the right side of the capacitor contact structure 120.
  • the 4F2 arrangement of the contact plug 121 can be changed to a 6F2 arrangement, thereby increasing the arrangement density of the semiconductor structure and improving the integration of the semiconductor structure.
  • the F in the above-mentioned 4F2 arrangement and 6F2 arrangement represents the minimum pattern size that can be obtained under given process conditions.
  • the blocking layer 123 includes: a first sub-blocking layer 180, the first sub-blocking layer 180 covers the side wall of the transition layer 124 facing the bit line structure 110; a second sub-blocking layer 190, the second sub-blocking layer 190 covers the top surface of the transition layer 124, the first sub-blocking layer 180 is used to protect the side wall of the transition layer 124 facing the bit line structure 110, so that in the process step of forming the sidewall isolation layer 112 or in the process step after forming the sidewall isolation layer 112, the landing pad 122 can be prevented from being contaminated by the side wall directly opposite to the sidewall isolation layer 112, thereby improving the reliability of the semiconductor structure; the second sub-blocking layer 190 can be used to isolate the transition layer 124 from the landing pad 122, which can prevent the metal ions of the metal material of the landing pad 122 from entering the transition layer 124, and can ensure the electrical performance and reliability of the device structure.
  • the first sub-blocking layer 180 also covers the side walls of the sidewall isolation layer 112 that is higher than the transition layer 124. By covering the side walls of the sidewall isolation layer 112 that is higher than the transition layer 124, contamination impurities can be prevented from entering the capacitor contact structure 120 through the second insulating layer 170, and the capacitor contact structure 120 can be prevented from being contaminated, thereby improving the reliability of the semiconductor structure.
  • the thickness of the first sub-blocking layer 180 is 0.2 to 2 nm. By setting the thickness of the first sub-blocking layer 180 to 0.2 to 2 nm, the space required for the first sub-blocking layer 180 can be reduced while ensuring that the first sub-blocking layer 180 has a good protective effect. When the thickness of the first sub-blocking layer 180 is less than 0.2 nm, the ability of the first sub-blocking layer 180 to protect the transition layer 124 is not strong. When the thickness of the first sub-blocking layer 180 is greater than 2 nm, the thickness of the first sub-blocking layer 180 is too thick, which will occupy the space for the subsequent formation of the transition layer 124, and may affect the performance of the transition layer 124.
  • the thickness of the first sub-blocking layer 180 may be other thicknesses, which may be adjusted according to the specific size of the actual semiconductor structure.
  • the second insulating layer 170 is divided into two parts, the first part is the part in contact with the contact plug 121, and the second part is the part located on the top surface of the first part. It can be understood that the thickness of the second part is less than the thickness of the first part, and the sum of the thickness of the second part and the thickness of the first sub-blocking layer 180 can be equal to the thickness of the first part. By setting the sum of the thickness of the second part and the thickness of the first sub-blocking layer 180 equal to the thickness of the first part, the space occupied by the first sub-blocking layer 180 can be reduced. In other words, the reliability of the semiconductor structure is improved by forming the first sub-blocking layer 180 without changing the morphology of the original semiconductor structure.
  • the equal thickness mentioned above may refer to completely equal thickness, or it may refer to that the difference in thickness between the sum of the thickness of the second part and the thickness of the first sub-blocking layer 180 and the thickness of the first part is within a preset range. Within this range, it can also be regarded that the sum of the thickness of the second part and the thickness of the first sub-blocking layer 180 is equal to the thickness of the first part.
  • the first sub-barrier layer 180 and the second sub-barrier layer 190 are made of the same material, including titanium nitride or tantalum nitride.
  • the interface state between the first sub-barrier layer 180 and the second sub-barrier layer 190 can be improved, thereby improving the tightness of the connection between the first sub-barrier layer 180 and the second sub-barrier layer 190, thereby improving the reliability of the semiconductor structure.
  • the materials of the first sub-blocking layer 180 and the second sub-blocking layer 190 may also be different.
  • the material of the first sub-blocking layer 180 is titanium nitride
  • the material of the second sub-blocking layer 190 is tantalum nitride, tungsten nitride, etc.
  • the materials of the first sub-blocking layer 180 and the second sub-blocking layer 190 may also be other materials.
  • the material of the first sub-blocking layer 180 only needs to meet the purpose of the first sub-blocking layer 180 for protecting the transition layer 124
  • the material of the second sub-blocking layer 190 needs to have certain conductive properties and can prevent the metal ions of the landing pad 122 from diffusing into the contact plug 121 .
  • the first sub-blocking layer 180 and the second sub-blocking layer 190 are also located on the side wall of the landing pad 122 facing the bit line structure 110; in other words, the first sub-blocking layer 180 not only covers the side wall of the transition layer 124 facing the bit line structure 110, but also covers a portion of the side wall of the landing pad 122 facing the bit line structure 110, and the second sub-blocking layer 190 also covers the side wall of the first sub-blocking layer 180.
  • the first sub-blocking layer 180 covers a portion of the side wall of the landing pad 122 toward the bit line structure 110, and the second sub-blocking layer 190 can also cover the side wall of the first sub-blocking layer 180, so that etching increases the distance between the landing pad 122 and the air gap layer 160, thereby improving the reliability of the semiconductor structure.
  • the embodiment of the present disclosure reads data information in a storage unit by setting a bit line structure 110 located on a substrate 100, or writes data information into a storage unit for storage through the bit line structure 110, and can lead out a signal of the capacitor by setting a capacitor contact structure 120 so as to store the signal in the capacitor, and can be electrically connected to the substrate 100 through a contact plug 121, and can lead out an electrical signal of the contact plug 121 by setting a landing pad 122, and can avoid anomalies caused by a large difference between the landing pad 122 and the contact plug 121 by setting a transition layer 124, and can protect the transition layer 124 by setting a barrier layer 123 located between the transition layer 124 and the bit line structure 110, thereby preventing the transition layer 124 from being affected by other process steps, thereby improving the reliability of the semiconductor structure.
  • Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.
  • the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the same or corresponding parts of the aforementioned embodiments can refer to the corresponding description of the aforementioned embodiments and will not be repeated below.
  • Figures 2 to 8 and Figure 1 are structural schematic diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure includes: providing a substrate 100; forming a bit line structure 110, wherein the bit line structure 110 is located on the substrate 100, and a plurality of bit line structures 110 are arranged at intervals; forming a capacitor contact structure 120, wherein the capacitor contact structure 120 includes: a contact plug 121, a landing pad 122, and a barrier layer 123 located between the landing pad 122 and the contact plug 121, wherein the top surface of the contact plug 121 is lower than the top surface of the bit line structure 110, wherein the top of the contact plug 121 includes a transition layer 124, and the barrier layer 123 is also located between the transition layer 124 and the bit line structure 110.
  • the embodiment of the present disclosure forms a bit line structure 110, through which data information can be written into a storage unit formed in a subsequent process step, or through which data information stored in a storage unit can be read.
  • the capacitor contact structure 120 can be formed to connect a capacitor structure formed subsequently and a substrate 100.
  • the barrier layer 123 is formed between the landing pad 122 and the contact plug 121, so that material particles in the contact plug 121 can be prevented from diffusing into the landing pad 122, thereby preventing the material of the landing pad 122 from being contaminated.
  • the barrier layer 123 is formed between the transition layer 124 and the bit line structure 110, so that subsequent process steps can prevent the transition layer 124 from being contaminated, thereby protecting the transition layer 124 and improving the reliability of the semiconductor structure.
  • a method for forming a bit line structure 110 includes: forming a bit line body 111, the bit line body 111 being located on a substrate 100 and arranged at intervals; forming an initial sidewall isolation layer 113, the initial sidewall isolation layer 113 being located on a side wall of the bit line body 111 facing a capacitor contact structure 120; etching a portion of the initial sidewall isolation layer 113 to expose a top surface of the substrate 100, and the remaining initial sidewall isolation layer 113 serving as a sidewall isolation layer 112, the sidewall isolation layer 112 and the bit line body 111 constituting the bit line structure 110.
  • bit line body 111 By forming the bit line body 111, data information in the storage unit can be read, or data information can be written into the storage unit through the bit line structure 110.
  • initial sidewall isolation layer 113 By forming the initial sidewall isolation layer 113, a process basis is provided for the subsequent formation of the sidewall isolation layer 112. By etching the initial sidewall isolation layer 113 to form a sidewall isolation layer 112 that exposes the top surface of the substrate 100, a sidewall isolation layer 112 with an air gap can be formed, thereby improving the performance of the sidewall isolation layer 112 and reducing the parasitic capacitance between the bit line structure 110 and the capacitor contact structure 120.
  • the method of forming the initial sidewall isolation layer 113 may include: forming a first insulating layer 150, the first insulating layer 150 is located on the sidewall of the bit line body 111 facing the capacitor contact structure 120; forming a dielectric layer 161, the dielectric layer 161 is located on the sidewall of the first insulating layer 150 facing the capacitor contact structure 120; forming a second insulating layer 170, the second insulating layer 170 is located on the sidewall of the dielectric layer 161 facing the capacitor contact structure 120.
  • the formed dielectric layer 161 can provide a process basis for the subsequent formation of the sidewall isolation layer with an air gap, and the air gap can be formed by directly etching the dielectric layer 161, thereby reducing the process difficulty of the semiconductor structure formation method.
  • the material of the first insulating layer 150 may be silicon nitride
  • the material of the dielectric layer 161 may be silicon oxide
  • the material of the second insulating layer 162 may be silicon nitride
  • the structure of the initial sidewall isolation layer 113 is a NON (nitride-oxide-nitride) structure.
  • NON nitride-oxide-nitride
  • the insulating performance of the initial sidewall isolation layer 113 can be improved, and the material of silicon nitride is relatively hard.
  • the morphology of the initial sidewall isolation layer 113 can be improved.
  • the method of forming the initial sidewall isolation layer 113 may be to form a first insulating layer 150, a dielectric layer 161 and a second insulating layer 170 respectively by sequential deposition; in other embodiments, the method of forming the initial sidewall isolation layer 113 may also be to form an initial insulating layer, the initial insulating layer occupies the space of the first insulating layer 150, the dielectric layer 161 and the second insulating layer 170 to be formed, the first insulating layer 150 and the second insulating layer 170 are formed by etching the initial insulating layer, and then the dielectric layer 161 is formed between the first insulating layer 150 and the second insulating layer 170 by deposition.
  • the thicknesses of the first insulating layer 150, the dielectric layer 161, and the second insulating layer 170 may be equal.
  • the thicknesses of the first insulating layer 150, the dielectric layer 161, and the second insulating layer 170 may not be equal.
  • the thickness of the dielectric layer 161 may be controlled to be greater than the thicknesses of the first insulating layer 150 and the second insulating layer 170. It is understandable that the greater the thickness of the dielectric layer 161, the greater the thickness of the subsequently formed air gap layer, the better the insulation performance of the subsequently formed sidewall isolation layer 112, and the stronger the ability to reduce the parasitic capacitance between the bit line structure 110 and the capacitor contact structure 120.
  • the thicknesses of the first insulating layer 150, the dielectric layer 161, and the second insulating layer 170 may also be increased or decreased in sequence.
  • the thickness of the first insulating layer 150 , the dielectric layer 161 and the second insulating layer 170 mentioned above refers to the size of the first insulating layer 150 , the dielectric layer 161 and the second insulating layer 170 in the direction from the midline structure 110 toward the capacitor contact structure as shown in the figure.
  • a contact plug 121 having a top surface lower than the top surface of the bit line body 111 is formed. It can be understood that by etching back the contact plug 121 of the semiconductor structure shown in FIG2 , a portion of the second insulating layer 170 is also etched simultaneously during the etching back process. However, this portion of the etched second insulating layer 170 may cause contaminated impurities to enter the capacitor contact structure 120 through the second insulating layer 170, causing the capacitor contact structure 120 to be contaminated.
  • the method for forming the barrier layer 123 may include: forming a first sub-barrier layer 180, the first sub-barrier layer 180 covers the side wall of the transition layer 124 facing the bit line structure 110; forming a second sub-barrier layer 190, the second sub-barrier layer 190 covers the top surface of the transition layer 124.
  • the first sub-barrier layer 180 By forming the first sub-barrier layer 180, the side wall of the transition layer 124 facing the bit line structure 110 can be protected, so that in the process step of forming the sidewall isolation layer 112 or in the process step after forming the sidewall isolation layer 112, the landing pad 122 can be prevented from being contaminated by the side wall directly facing the sidewall isolation layer 112, thereby improving the reliability of the semiconductor structure.
  • the transition layer 124 can be isolated from the landing pad 122, and the metal ions of the metal material of the landing pad 122 can be prevented from entering the transition layer 124, so as to ensure the electrical performance and reliability of the device structure.
  • the method for forming the first sub-blocking layer 180 includes: forming a first initial blocking layer 181, the first initial blocking layer 181 covering the side walls of the bit line structure 110 and the top surface of the bit line structure 110; etching the first initial blocking layer 181, the remaining first initial blocking layer 181 covering the side walls of the bit line structure 110, and the remaining first initial blocking layer 181 is the first sub-blocking layer 180.
  • a first initial sub-barrier layer 181 is formed to cover the top surface of the bit line body 111 , the top surface and sidewalls of the initial sidewall spacer 113 , and the top surface of the contact plug 121 .
  • the method of forming the first initial sub-blocking layer 181 may be through chemical vapor deposition to form the first initial sub-blocking layer 181 on the top surface of the bit line body 111, the top surface and sidewall of the initial sidewall isolation layer 113, and the top surface of the contact plug 121.
  • the first initial sub-barrier layer 181 is etched to expose top surfaces of the bit line body 111 , the initial sidewall spacers 113 , and the contact plugs 121 , and the remaining first initial sub-barrier layer 181 serves as the first sub-barrier layer 180 .
  • a transition layer 124 is formed.
  • the method for forming the transition layer 124 may include: forming a metal conductive layer (not shown in the figure), the metal conductive layer being located on the top surface of the contact plug 121; using an annealing process to react the metal conductive layer with the contact plug 121 to form the transition layer 124; removing the metal conductive layer, in other words, heating so that ions of the metal conductive layer and the contact plug 121 diffuse into each other to form the transition layer 124, which can reduce the contact resistance between the transition layer 124 and the contact plug 121, thereby improving the electrical performance of the semiconductor structure.
  • the process dimension of the annealing process may be 400° C. to 1000° C. It is understood that when the process temperature of the thermal annealing process is less than 400° C., the metal conductive layer and the contact plug 121 react poorly and at a slow reaction rate, and when the process temperature of the thermal annealing process is greater than 1000° C., the formed transition layer 124 is unstable, causing part of the transition layer 124 to be reduced to a semiconductor material, which may affect the reliability of the formed capacitor contact structure.
  • a second sub-blocking layer 190 is formed, and the second sub-blocking layer 190 covers the top surface of the bit line body 111, the top surface of the initial sidewall isolation layer 113, and the top surface of the first sub-blocking layer 180.
  • the second sub-blocking layer also covers the sidewall of the first sub-blocking layer 180 and the top surface of the transition layer 124.
  • a portion of the second sub-blocking layer 190 is etched, and the remaining second sub-blocking layer 190 covers the side walls of the first sub-blocking layer 180, the top surface of the transition layer 124, the top surface of one of the initial sidewall isolation layers 113 adjacent to the capacitor contact structure 120, and the top surface of the bit line body 111 in contact with the initial sidewall isolation layer 113.
  • the method for forming the landing pad 122 includes: forming an initial landing pad 200, the initial landing pad 200 covering the top surface of the bit line structure 110, and the initial landing pad 200 also covering the side wall of the barrier layer 123; etching the initial landing pad 200 so that the remaining initial landing pad 200 covers a portion of the top surface of one of the two bit line structures 110 adjacent to the capacitor contact structure 120, and the remaining initial landing pad 200 serves as the landing pad 122.
  • the initial landing pad 200 is formed by depositing the entire surface of the semiconductor structure shown in FIG.
  • the initial landing pad 200 can fill the space surrounded by the transition layer 124 and the first sub-barrier layer 180, so that the reliability of the subsequently formed landing pad 122 can be improved, and the initial landing pad 200 is formed by etching the initial landing pad 200 to form the landing pads 122 arranged at intervals, so as to avoid electrical connection between adjacent landing pads 122, so as to improve the reliability of the semiconductor structure.
  • the dielectric layer 161 is etched to form an air gap layer 160 .
  • the air gap layer 160 can improve the insulation performance of the sidewall isolation layer 112 and reduce the parasitic capacitance between the bit line structure 110 and the capacitor contact structure 120 .
  • the embodiment of the present disclosure forms a bit line structure 110, through which data information can be written into a storage unit formed in a subsequent process step, or through which data information stored in a storage unit can be read.
  • the capacitor contact structure 120 can be formed to connect a capacitor structure formed subsequently and a substrate 100.
  • the barrier layer 123 is formed between the landing pad 122 and the contact plug 121, so that material particles in the contact plug 121 can be prevented from diffusing into the landing pad 122, thereby preventing the material of the landing pad 122 from being contaminated.
  • the barrier layer 123 is formed between the transition layer 124 and the bit line structure 110, so that subsequent process steps can prevent the transition layer 124 from being contaminated, thereby protecting the transition layer 124 and improving the reliability of the semiconductor structure.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及其制作方法，其中，半导体结构包括：衬底；位线结构，位线结构位于衬底上且间隔排布；电容接触结构，位于相邻位线结构之间，电容接触结构包括：接触插塞，着陆垫以及位于着陆垫与接触插塞之间的阻挡层，接触插塞的顶面低于位线结构的顶面；其中，接触插塞顶部包含过渡层，阻挡层还位于过渡层和位线结构之间。可以提高半导体结构的可靠性。

Description

半导体结构及其制作方法
交叉引用
本公开要求于2022年09月26日递交的名称为“半导体结构及其制作方法”、申请号为202211176956.8的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管；晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或通过位线将数据信息写入到电容器中进行存储。
目前，在形成动态随机存储器的过程中，部分工艺步骤会影响形成的电容接触结构的可靠性。
发明内容
本公开实施例提供一种半导体结构及其制作方法，至少可以提高半导体结构的可靠性。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：衬底；位线结构，所述位线结构位于所述衬底上且间隔排布；电容接触结构，位于相邻所述位线结构之间，所述电容接触结构包括：接触插塞，着陆垫以及位于所述着陆垫与所述接触插塞之间的阻挡层，所述接触插塞的顶面低于所述位线结构的顶面；其中，所述接触插塞顶部包含过渡层，所述阻挡层还位于所述过渡层和所述位线结构之间。
在一些实施例中，所述阻挡层包括：第一子阻挡层，所述第一子阻挡层覆盖所述过渡层朝向所述位线结构的侧壁；第二子阻挡层，所述第二子阻挡层覆盖所述过渡层的顶面。
在一些实施例中，所述第一子阻挡层的厚度为0.2～2nm。
在一些实施例中，所述第一子阻挡层与所述第二子阻挡层的材料相同，包括：氮化钛或氮化钽。
在一些实施例中，所述接触插塞的材料包括硅，所述过渡层的材料包括：硅化钴、硅 化镍或硅化钛。
在一些实施例中，所述着陆垫的材料包括：钨、铝或铜。
在一些实施例中，所述位线结构包括位线主体及侧壁隔离层，所述侧壁隔离层位于所述位线主体朝向所述电容接触结构的侧壁，所述阻挡层还位于所述着陆垫与所述侧壁隔离层之间，所述侧壁隔离层为多层复合结构。
在一些实施例中，所述侧壁隔离层由所述位线主体朝向所述电容接触结构依次包括：第一绝缘层、空气间隙层及第二绝缘层。
在一些实施例中，所述第一子阻挡层和所述第二子阻挡层还位于所述着陆垫朝向所述位线结构的侧壁。
在一些实施例中，所述着陆垫还覆盖与所述电容接触结构相邻的两个所述位线结构中的一者的部分顶面。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制作方法，包括：提供衬底；形成位线结构，所述位线结构位于所述衬底上，且多个所述位线结构间隔排布；形成电容接触结构，所述电容接触结构包括：接触插塞，着陆垫以及位于所述着陆垫与所述接触插塞之间的阻挡层，所述接触插塞的顶面低于所述位线结构的顶面，其中，所述接触插塞顶部包含过渡层，所述阻挡层还位于所述过渡层和所述位线结构之间。
在一些实施例中，形成所述阻挡层的方法包括：形成第一子阻挡层，所述第一子阻挡层覆盖所述过渡层朝向所述位线结构的侧壁；形成第二子阻挡层，所述第二子阻挡层覆盖所述过渡层的顶面。
在一些实施例中，形成所述第一子阻挡层的方法包括：形成第一初始阻挡层，所述第一初始阻挡层覆盖所述位线结构的侧壁及所述位线结构的顶面；刻蚀所述第一初始阻挡层，剩余所述第一初始阻挡层覆盖所述位线结构的侧壁，剩余所述第一初始阻挡层作为所述第一子阻挡层。
在一些实施例中，形成所述过渡层的方法包括：形成金属导电层，所述金属导电层位于所述接触插塞的顶面；采用退火工艺使所述金属导电层与所述接触插塞反应形成过渡层；去除所述金属导电层。
在一些实施例中，形成所述着陆垫的方法包括：形成初始着陆垫，所述初始着陆垫覆盖所述位线结构的顶面，所述初始着陆垫还覆盖所述阻挡层的侧壁；刻蚀所述初始着陆垫，以使剩余所述初始着陆垫覆盖与所述电容接触结构相邻的两个所述位线结构中的一者的部分顶面，剩余所述初始着陆垫作为所述着陆垫。
在一些实施例中，形成所述位线结构的方法包括：形成位线主体，所述位线主体位于所述衬底上且间隔排布；形成初始侧壁隔离层，所述初始侧壁隔离层位于所述位线主体朝向所述电容接触结构的侧壁；刻蚀部分所述初始侧壁隔离层，以暴露所述衬底的顶面，剩余所述初始侧壁隔离层作为侧壁隔离层，所述侧壁隔离层与所述位线主体构成所述位线结构。
在一些实施例中，形成所述初始侧壁隔离层的方法包括：形成第一绝缘层，所述第一绝缘层位于所述位线主体朝向所述电容接触结构的侧壁；形成介质层，所述介质层位于所述第一绝缘层朝向所述电容接触结构的侧壁；形成第二绝缘层，所述第二绝缘层位于所述介质层朝向所述电容接触结构的侧壁。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的一种半导体结构的结构示意图；
图2至图8为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
本公开实施提供一种半导体结构，通过设置电容接触结构位于相邻的位线结构之间，且电容接触结构包括：接触插塞，着陆垫以及位于着陆垫与接触插塞之间的阻挡层，且阻挡层还位于过渡层和位线结构之间，通过阻挡层将过渡层进行保护，从而可以避免后续的工艺步骤对过渡层造成影响，从而可以提高半导体结构的可靠性。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
参考图1，图1为本公开实施例提供的一种半导体结构，包括：衬底100；位线结构110，位线结构110位于衬底100上且间隔排布；电容接触结构120，位于相邻位线结构110之间，电容接触结构120包括：接触插塞121，着陆垫122以及位于着陆垫122与接触插塞121之间的阻挡层123，接触插塞121的顶面低于位线结构110的顶面；其中，接触插塞121顶部包含过渡层124，阻挡层123还位于过渡层124和位线结构110之间。
本公开实施例通过设置位于衬底100上的位线结构110读取存储单元中的数据信息，或者通过位线结构110将数据信息写入到存储单元内进行存储，通过设置电容接触结构120可以将电容的信号引出，或者便于向电容中存储信号，通过接触插塞121与衬底100进行电连接，通过设置着陆垫122可以将接触插塞121的电信号引出，通过设置过渡层124可以避免出现因为着陆垫122与接触插塞121之间差异过大导致的异常，通过设置位于过渡层124和位线结构110之间的阻挡层123可以将过渡层124保护起来，从而可以避免过渡层124受到其他工艺步骤的影响，从而可以提高半导体结构的可靠性。
在一些实施例中，在一些实施例中，衬底100为半导体材料，半导体材料包括但不限于硅衬底、锗衬底、锗硅衬底或碳化硅衬底的任一种。衬底100还可以是离子掺杂衬底，掺杂离子为N型离子或者P型离子，N型离子具体可以为磷离子、砷离子或者锑离子，P型离子具体可以为硼离子、铟离子或者氟化硼离子。
在一些实施例中，位线结构110包括位线主体111及侧壁隔离层112，侧壁隔离层112位于位线主体111朝向电容接触结构120的侧壁，阻挡层123还位于着陆垫122与侧壁隔离层112之间，侧壁隔离层112为多层复合结构。
可以理解的是，位线主体111也就是位线结构110中用于读取存储单元中的数据信息，或者通过位线结构110将数据信息写入到存储单元内进行存储的部分，侧壁隔离层112也就是将位线结构110与其他不需要进行电连接的结构进行隔离的部分，通过侧壁隔离层112可以提高半导体结构的可靠性，通过设置阻挡层123位于着陆垫122与侧壁隔离层112之间可以在形成侧壁隔离层112的工艺步骤中或者形成侧壁隔离层112之后的工艺步骤中，避免着陆垫122通过与侧壁隔离层112正对的侧壁导致着陆垫122被污染，从而可以提高半导体结构的可靠性。
在一些实施例中，位线主体111可以包括位线导电层130及位线保护层140，位线保护层140可以位于位线导电层130的顶面，位线导电层130也就是位线主体111中用于导电的部分，位线保护层140也就是用于保护位线主体111的部分，通过位线导电层130可以用于读取存储单元中的数据信息，或者通过位线导电层130将数据信息写入到存储单元内进行存储，通过位线保护层140可以在后续的工艺步骤中保护位线导电层130不受影响，且可以通过位线保护层140将位线导电层130与外界进行隔离，从而当位线结构110受到外界应力作用时可以通过位线保护层140吸收一部分的应力作用从而可以减少位线导电层130上受到的应力作用。
在一些实施例中，位线导电层130可以为多层膜层结构的堆叠，或者也可以为单层膜层。
在一些实施例中，位线导电层130的材料可以包括钨、钴或者镍等金属材料，也可以 包括一些常用的金属半导体化合物材料，例如硅化钴、硅化镍或硅化钛等等。
在一些实施例中，位线保护层140也可以是多层膜层结构的堆叠，或者也可以是单层膜层。
在一些实施例中，位线保护层140的材料可以包括氮化硅或者氧化硅等绝缘材料。
在一些实施例中，侧壁隔离层112由位线主体111朝向电容接触结构120依次包括：第一绝缘层150、空气间隙层160及第二绝缘层170。可以理解的是，由于位线结构110与电容接触结构120都为导电结构，因此在位线结构110与电容接触结构120之间会形成有寄生电容，通过设置侧壁隔离层112的结构依次包括第一绝缘层150、空气间隙层160及第二绝缘层170可以减少位线结构110与电容接触结构120之间的寄生电容，且空气间隙的体积越大、形貌越完整，就越能降低位线结构110与电容接触结构120之间的寄生电容。
在一些实施例中，第一绝缘层150的材料可以与第二绝缘层170的材料相同，例如都可以是氮化硅材料。
在一些实施例中，如图1所示，在垂直于衬底100表面的方向上第二绝缘层170的厚度分布为位于上面部分的第二绝缘层170的厚度比位于下面部分的第二绝缘层170的厚度薄，然而这部分较薄的第二绝缘层170也就是后续工艺步骤中污染杂质容易渗透的部分，因此通过形成第一子阻挡层180覆盖第二绝缘层170这部分较薄的侧壁可以避免污染杂质透过第二绝缘层170污染电容接触结构120，从而可以提高半导体结构的可靠性。
在一些实施例中，接触插塞121的材料可以包括硅，过渡层124的材料可以包括：硅化钴、硅化镍或硅化钛等，通过控制接触插塞121的材料为硅可以减少接触插塞121与衬底100之间的界面态，从而可以提高半导体结构可靠性，通过控制过渡层124的材料为金属半导体化合物可以减少过渡层124与接触插塞121之间的接触电阻，可以提高半导体结构的性能。
在一些实施例中，着陆垫122的材料包括：钨、铝或铜，可以理解的是，钨、铝或铜的导电性能较好，通过设置着陆垫122的材料为铝或铜可以提高着陆垫122的导电性能，且还可以降低电信号的传导时间，提高半导体结构的响应速度。
在另一些实施例中，着陆垫122还可以是其他金属材料，在又一些实施例中，着陆垫122也可以是其他可以导电的材料。
在一些实施例中，着陆垫122还覆盖与电容接触结构120相邻的两个位线结构110中的一者的部分顶面。以图示为例，图示中，着陆垫122位于电容接触结构120右侧的位线结构110的部分顶面，通过设置着陆垫122覆盖与电容接触结构120相邻的两个位线结构110中的一者的部分顶面可以将接触插塞121的4F2排布改为6F2排布，从而可以增加半导体结 构的排布密度，提高半导体结构的集成度。
需要说明的是上述的4F2排布及6F2排布中的F表示在给定工艺条件下可获得的最小图案尺寸。
在一些实施例中，阻挡层123包括：第一子阻挡层180，第一子阻挡层180覆盖过渡层124朝向位线结构110的侧壁；第二子阻挡层190，第二子阻挡层190覆盖过渡层124的顶面，第一子阻挡层180用于将过渡层124朝向位线结构110的侧壁保护起来，从而可以在形成侧壁隔离层112的工艺步骤中或者形成侧壁隔离层112之后的工艺步骤中，避免着陆垫122通过与侧壁隔离层112正对的侧壁导致着陆垫122被污染，从而可以提高半导体结构的可靠性；第二子阻挡层190可以用于将过渡层124与着陆垫122进行隔离，可以避免着陆垫122的金属材料的金属离子进入过渡层124中，可以保证器件结构的电学性能和可靠性。
在一些实施例中，第一子阻挡层180还覆盖高于过渡层124的侧壁隔离层112的侧壁，通过覆盖高于过渡层124的侧壁隔离层112的侧壁可以避免污染杂质通过第二绝缘层170进入电容接触结构120，可以避免电容接触结构120被污染，从而可以提高半导体结构的可靠性。
在一些实施例中，第一子阻挡层180的厚度为0.2～2nm，通过设置第一子阻挡层180的厚度为0.2～2nm可以在保证第一子阻挡层180具有较好的保护效果的同时减少第一子阻挡层180所需占用的空间，当第一子阻挡层180的厚度小于0.2nm时，第一子阻挡层180保护过渡层124的能力并不强，当第一子阻挡层180的厚度大于2nm时，第一子阻挡层180的厚度太厚，会占用后续形成过渡层124的空间，可能影响过渡层124的性能。
在另一些实施例中，第一子阻挡层180的厚度还可以是其他厚度，可以根据实际半导体结构的具体尺寸进行调整。
在一些实施例中，将第二绝缘层170分为两个部分，第一部分是与接触插塞121接触的部分，第二部分是位于第一部分顶面的部分，可以理解的是，第二部分的厚度小于第一部分的厚度，第二部分的厚度与第一子阻挡层180的厚度之和可以等于第一部分的厚度，通过设置第二部分的厚度与第一子阻挡层180的厚度之和等于第一部分的厚度，可以减少第一子阻挡层180所占用的空间，也就是说，不改变原有半导体结构的形貌的基础上通过形成有第一子阻挡层180提高半导体结构的可靠性。
需要说明的是，上述中的厚度相等可以指厚度完全相等，也可以指第二部分的厚度与第一子阻挡层180的厚度之和与第一部分的厚度之间的厚度差异在一个预设范围内，在这个范围内的也可以视为第二部分的厚度与第一子阻挡层180的厚度之和等于第一部分的厚度。
在一些实施例中，第一子阻挡层180与第二子阻挡层190的材料相同，包括：氮化钛 或氮化钽。通过设置第一子阻挡层180与第二子阻挡层190的材料相同可以改善第一子阻挡层180与第二子阻挡层190之间连接的界面态，从而可以提高第一子阻挡层180和第二子阻挡层190之间连接的紧密型，从而可以提高半导体结构的可靠性。
在另一些实施例中，第一子阻挡层180和第二子阻挡层190的材料也可以不同，例如，第一子阻挡层180的材料为氮化钛，第二子阻挡层190的材料为氮化钽、氮化钨等。
在另一些实施例中，第一子阻挡层180和第二子阻挡层190的材料还可以是其他材料，第一子阻挡层180的材料仅需要满足第一子阻挡层180用于保护过渡层124的目的即可，第二子阻挡层190的材料需满足具有一定的导电性能，且可以避免着陆垫122的金属离子扩散至接触插塞121中即可。
在一些实施例中，第一子阻挡层180和第二子阻挡层190还位于着陆垫122朝向位线结构110的侧壁；换句话说，第一子阻挡层180不仅覆盖过渡层124朝向位线结构110的侧壁，还覆盖部分着陆垫122朝向位线结构110的侧壁，第二子阻挡层190还覆盖第一子阻挡层180的侧壁，通过设置第一子阻挡层180覆盖着陆垫122朝向位线结构110的侧壁可以降低后续工艺步骤对位线结构110的影响，从而可以提高半导体结构的可靠性。
在一些实施例中，第一子阻挡层180覆盖部分着陆垫122朝向位线结构110的侧壁，第二子阻挡层190还可以覆盖第一子阻挡层180的侧壁，从而刻蚀增加着陆垫122与空气间隙层160之间的间距，从而可以提高半导体结构的可靠性。
本公开实施例通过设置位于衬底100上的位线结构110读取存储单元中的数据信息，或者通过位线结构110将数据信息写入到存储单元内进行存储，通过设置电容接触结构120可以将电容的信号引出，以便向电容中存储信号，通过接触插塞121与衬底100进行电连接，通过设置着陆垫122可以将接触插塞121的电信号引出，通过设置过渡层124可以避免出现因为着陆垫122与接触插塞121之间差异过大导致的异常，通过设置位于过渡层124和位线结构110之间的阻挡层123可以将过渡层124保护起来，从而可以避免过渡层124受到其他工艺步骤的影响，从而可以提高半导体结构的可靠性。
本公开另一实施例还提供一种半导体结构的制作方法，可以用于形成上述半导体结构，以下将结合附图对本公开另一实施例提供的半导体结构的制作方法进行说明，需要说明的是前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图2至图8及图1，其中图2至图8及图1为本公开实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
本公开实施例提供的半导体结构的制作方法包括：提供衬底100；形成位线结构110，位线结构110位于衬底100上，且多个位线结构110间隔排布；形成电容接触结构120，电 容接触结构120包括：接触插塞121，着陆垫122以及位于着陆垫122与接触插塞121之间的阻挡层123，接触插塞121的顶面低于位线结构110的顶面，其中，接触插塞121顶部包含过渡层124，阻挡层123还位于过渡层124和位线结构110之间。
本公开实施例通过形成位线结构110可以通过位线结构110向后续工艺步骤中形成的存储单元中写入数据信息，或者通过位线结构110读取存储单元中存储的数据信息，通过形成电容接触结构120可以用于连接后续形成的电容结构及衬底100，通过形成位于着陆垫122与接触插塞121之间的阻挡层123可以避免接触插塞121中的材料粒子扩散至着陆垫122中，避免着陆垫122的材料被污染，通过形成位于过渡层124和位线结构110之间的阻挡层123可以避免后续的工艺步骤对过渡层124造成污染，从而可以将过渡层124进行保护，可以提高半导体结构的可靠性。
在一些实施例中，形成位线结构110的方法包括：形成位线主体111，位线主体111位于衬底100上且间隔排布；形成初始侧壁隔离层113，初始侧壁隔离层113位于位线主体111朝向电容接触结构120的侧壁；刻蚀部分初始侧壁隔离层113，以暴露衬底100的顶面，剩余初始侧壁隔离层113作为侧壁隔离层112，侧壁隔离层112与位线主体111构成位线结构110。通过形成位线主体111可以用于读取存储单元中的数据信息，或者通过位线结构110将数据信息写入到存储单元内进行存储的部分，通过形成初始侧壁隔离层113为后续形成侧壁隔离层112提供工艺基础，通过刻蚀初始侧壁隔离层113以形成暴露衬底100顶面的侧壁隔离层112从而可以形成具有空气间隙的侧壁隔离层112，从而可以提高侧壁隔离层112的性能，可以减少位线结构110与电容接触结构120之间的寄生电容。
参考图2，在一些实施例中，形成初始侧壁隔离层113的方法可以包括：形成第一绝缘层150，第一绝缘层150位于位线主体111朝向电容接触结构120的侧壁；形成介质层161，介质层161位于第一绝缘层150朝向电容接触结构120的侧壁；形成第二绝缘层170，第二绝缘层170位于介质层161朝向电容接触结构120的侧壁。通过形成的介质层161可以为后续形成的具有空气间隙的侧壁隔离层提供工艺基础，后续可以通过直接刻蚀介质层161的方式形成空气间隙，从而可以降低半导体结构形成方法的工艺难度。
在一些实施例中，第一绝缘层150的材料可以是氮化硅，介质层161的材料可以是氧化硅，第二绝缘层162的材料可以是氮化硅，也就是初始侧壁隔离层113的结构为NON(氮化物-氧化物-氮化物)结构，通过形成NON结构可以提高初始侧壁隔离层113的绝缘性能，且氮化硅的材料材质较硬，通过形成NON结构可以改善初始侧壁隔离层113的形貌。
在一些实施例中，形成初始侧壁隔离层113的方法可以是，通过依次沉积的方式，以分别形成第一绝缘层150、介质层161及第二绝缘层170；在另一些实施例中，形成初始侧壁隔离层113的方法还可以是形成初始绝缘层，初始绝缘层占用需要形成的第一绝缘层150、 介质层161及第二绝缘层170的空间，通过刻蚀初始绝缘层的方式形成第一绝缘层150及第二绝缘层170，再通过沉积的方式在第一绝缘层150及第二绝缘层170之间形成介质层161。
在一些实施例中，形成的第一绝缘层150、介质层161及第二绝缘层170的厚度可以是相等，通过控制第一绝缘层150、介质层161及第二绝缘层170的厚度相等，可以在通过沉积的方式形成第一绝缘层150、介质层161及第二绝缘层170的过程中，不需要调整沉积的数量及喷涂相应材料的速率，从而可以简化半导体结构的工艺步骤；在另一些实施例中，第一绝缘层150、介质层161及第二绝缘层170的厚度也可以不相等，例如可以控制形成的介质层161的厚度大于第一绝缘层150及第二绝缘层170的厚度，可以理解的是，介质层161的厚度越大，后续形成的空气间隙层的厚度也就越大，后续形成的侧壁隔离层112的绝缘性能也就越好，降低位线结构110与电容接触结构120之间的寄生电容的能力也就越强；第一绝缘层150、介质层161及第二绝缘层170的厚度还可以是依次增加或者依次减小等。
需要说明的是，上述提到的第一绝缘层150、介质层161及第二绝缘层170的厚度是指沿图示中位线结构110朝向电容接触结构的方向上第一绝缘层150、介质层161及第二绝缘层170的尺寸。
参考图3，形成顶面低于位线主体111顶面的接触插塞121，可以理解的是，通过回刻蚀图2所示的半导体结构的接触插塞121，在回刻蚀的过程中部分第二绝缘层170还被同时刻蚀，然而这部分被刻蚀的第二绝缘层170可能导致污染杂质通过第二绝缘层170进入电容接触结构120内，导致电容接触结构120被污染。
参考图4至图8，形成阻挡层123的方法可以包括：形成第一子阻挡层180，第一子阻挡层180覆盖过渡层124朝向位线结构110的侧壁；形成第二子阻挡层190，第二子阻挡层190覆盖过渡层124的顶面，通过形成第一子阻挡层180可以将过渡层124朝向位线结构110的侧壁保护起来，从而可以在形成侧壁隔离层112的工艺步骤中或者形成侧壁隔离层112之后的工艺步骤中，避免着陆垫122通过与侧壁隔离层112正对的侧壁导致着陆垫122被污染，从而可以提高半导体结构的可靠性，通过形成第二子阻挡层190可以将过渡层124与着陆垫122进行隔离，可以避免着陆垫122的金属材料的金属离子进入过渡层124中，可以保证器件结构的电学性能和可靠性。
具体的参考图4及图5，形成第一子阻挡层180的方法包括：形成第一初始阻挡层181，第一初始阻挡层181覆盖位线结构110的侧壁及位线结构110的顶面；刻蚀第一初始阻挡层181，剩余第一初始阻挡层181覆盖位线结构110的侧壁，剩余第一初始阻挡层181为第一子阻挡层180。
具体的，参考图4，形成第一初始子阻挡层181，第一初始子阻挡层181覆盖位线主体111的顶面、初始侧壁隔离层113的顶面及侧壁以及接触插塞121的顶面。
在一些实施例中，形成第一初始子阻挡层181的方法可以是通过化学气相沉积，以在位线主体111的顶面、初始侧壁隔离层113的顶面及侧壁以及接触插塞121的顶面形成第一初始子阻挡层181。
参考图5，刻蚀第一初始子阻挡层181以暴露位线主体111顶面、初始侧壁隔离层113的顶面及接触插塞121的顶面，剩余第一初始子阻挡层181作为第一子阻挡层180。
参考图6，形成过渡层124，在一些实施例中，形成过渡层124的方法可以包括：形成金属导电层(图中未示出)，金属导电层位于接触插塞121的顶面；采用退火工艺使金属导电层与接触插塞121反应形成过渡层124；去除金属导电层，换句话说，也就是加热使得金属导电层和接触插塞121的离子相互扩散以形成过渡层124，可以减小过渡层124与接触插塞121之间的接触电阻，从而可以提高半导体结构的电学性能。
在一些实施例中，退火工艺的工艺维度可以为400℃～1000℃。可以理解的是，当热退火工艺的工艺温度小于400℃时，金属导电层与接触插塞121反应的效果不佳，且反应速率较慢，当热退火工艺的工艺温度大于1000℃时，形成的过渡层124不稳定，导致部分过渡层124还原成半导体材料，可能会影响形成的电容接触结构的可靠性。
参考图7，形成第二子阻挡层190，第二子阻挡层190覆盖位线主体111的顶面、初始侧壁隔离层113的顶面及第一子阻挡层180的顶面，第二子阻挡层还覆盖第一子阻挡层180的侧壁及过渡层124的顶面，
参考图8，刻蚀部分第二子阻挡层190，剩余第二子阻挡层190覆盖第一子阻挡层180的侧壁、过渡层124的顶面、与电容接触结构120相邻的初始侧壁隔离层113中的一者的顶面以及与该初始侧壁隔离层113接触连接的位线主体111的顶面。
继续参考图7及图8，形成着陆垫122的方法包括：形成初始着陆垫200，初始着陆垫200覆盖位线结构110的顶面，初始着陆垫200还覆盖阻挡层123的侧壁；刻蚀初始着陆垫200，以使剩余初始着陆垫200覆盖与电容接触结构120相邻的两个位线结构110中的一者的部分顶面，剩余初始着陆垫200作为着陆垫122。通过在图6所示的半导体结构的表面整面沉积的方式形成初始着陆垫200，从而可以确保初始着陆垫200可以填充满过渡层124以及第一子阻挡层180围成的空间，从而可以提高后续形成的着陆垫122的可靠性，通过刻蚀初始着陆垫200的方式以形成间隔排布的着陆垫122，避免相邻的着陆垫122之间电连接，从而可以提高半导体结构的可靠性。
参考图1，形成着陆垫122之后，刻蚀介质层161以形成空气间隙层160，通过形成空气间隙层160可以提高侧壁隔离层112的绝缘性能，且可以减少位线结构110与电容接触结构120之间的寄生电容。
本公开实施例通过形成位线结构110可以通过位线结构110向后续工艺步骤中形成的存储单元中写入数据信息，或者通过位线结构110读取存储单元中存储的数据信息，通过形成电容接触结构120可以用于连接后续形成的电容结构及衬底100，通过形成位于着陆垫122与接触插塞121之间的阻挡层123可以避免接触插塞121中的材料粒子扩散至着陆垫122中，避免着陆垫122的材料被污染，通过形成位于过渡层124和位线结构110之间的阻挡层123可以避免后续的工艺步骤对过渡层124造成污染，从而可以将过渡层124进行保护，可以提高半导体结构的可靠性。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (17)

  1. 一种半导体结构，包括：
    衬底；
    位线结构，所述位线结构位于所述衬底上且间隔排布；
    电容接触结构，位于相邻所述位线结构之间，所述电容接触结构包括：接触插塞，着陆垫以及位于所述着陆垫与所述接触插塞之间的阻挡层，所述接触插塞的顶面低于所述位线结构的顶面；
    其中，所述接触插塞顶部包含过渡层，所述阻挡层还位于所述过渡层和所述位线结构之间。
  2. 根据权利要求1所述的半导体结构，其中，所述阻挡层包括：
    第一子阻挡层，所述第一子阻挡层覆盖所述过渡层朝向所述位线结构的侧壁；
    第二子阻挡层，所述第二子阻挡层覆盖所述过渡层的顶面。
  3. 根据权利要求2所述的半导体结构，其中，所述第一子阻挡层的厚度为0.2～2nm。
  4. 根据权利要求2所述的半导体结构，其中，所述第一子阻挡层与所述第二子阻挡层的材料相同，包括：氮化钛或氮化钽。
  5. 根据权利要求1所述的半导体结构，其中，所述接触插塞的材料包括硅，所述过渡层的材料包括：硅化钴、硅化镍或硅化钛。
  6. 根据权利要求1所述的半导体结构，其中，所述着陆垫的材料包括：钨、铝或铜。
  7. 根据权利要求2所述的半导体结构，其中，所述位线结构包括位线主体及侧壁隔离层，所述侧壁隔离层位于所述位线主体朝向所述电容接触结构的侧壁，所述阻挡层还位于所述着陆垫与所述侧壁隔离层之间，所述侧壁隔离层为多层复合结构。
  8. 根据权利要求7所述的半导体结构，其中，所述侧壁隔离层由所述位线主体朝向所述电容接触结构依次包括：第一绝缘层、空气间隙层及第二绝缘层。
  9. 根据权利要求7所述的半导体结构，其中，所述第一子阻挡层和所述第二子阻挡层还位于所述着陆垫朝向所述位线结构的侧壁。
  10. 根据权利要求1所述的半导体结构，其中，所述着陆垫还覆盖与所述电容接触结构相邻的两个所述位线结构中的一者的部分顶面。
  11. 一种半导体结构的制作方法，包括：
    提供衬底；
    形成位线结构，所述位线结构位于所述衬底上，且多个所述位线结构间隔排布；
    形成电容接触结构，所述电容接触结构包括：接触插塞，着陆垫以及位于所述着陆垫与所述接触插塞之间的阻挡层，所述接触插塞的顶面低于所述位线结构的顶面，其中，所述接触插塞顶部包含过渡层，所述阻挡层还位于所述过渡层和所述位线结构之间。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，形成所述阻挡层的方法包括：
    形成第一子阻挡层，所述第一子阻挡层覆盖所述过渡层朝向所述位线结构的侧壁；
    形成第二子阻挡层，所述第二子阻挡层覆盖所述过渡层的顶面。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，形成所述第一子阻挡层的方法包括：
    形成第一初始阻挡层，所述第一初始阻挡层覆盖所述位线结构的侧壁及所述位线结构的顶面；
    刻蚀所述第一初始阻挡层，剩余所述第一初始阻挡层覆盖所述位线结构的侧壁，剩余所述第一初始阻挡层作为所述第一子阻挡层。
  14. 根据权利要求11所述的半导体结构的制作方法，其中，形成所述过渡层的方法包括：
    形成金属导电层，所述金属导电层位于所述接触插塞的顶面；
    采用退火工艺使所述金属导电层与所述接触插塞反应形成过渡层；
    去除所述金属导电层。
  15. 根据权利要求11所述的半导体结构的制作方法，其中，形成所述着陆垫的方法包括：
    形成初始着陆垫，所述初始着陆垫覆盖所述位线结构的顶面，所述初始着陆垫还覆盖所述阻挡层的侧壁；
    刻蚀所述初始着陆垫，以使剩余所述初始着陆垫覆盖与所述电容接触结构相邻的两个所述位线结构中的一者的部分顶面，剩余所述初始着陆垫作为所述着陆垫。
  16. 根据权利要求11所述的半导体结构的制作方法，其中，形成所述位线结构的方法包括：
    形成位线主体，所述位线主体位于所述衬底上且间隔排布；
    形成初始侧壁隔离层，所述初始侧壁隔离层位于所述位线主体朝向所述电容接触结构的侧壁；
    刻蚀部分所述初始侧壁隔离层，以暴露所述衬底的顶面，剩余所述初始侧壁隔离层作为 侧壁隔离层，所述侧壁隔离层与所述位线主体构成所述位线结构。
  17. 根据权利要求16所述的半导体结构的制作方法，其中，形成所述初始侧壁隔离层的方法包括：
    形成第一绝缘层，所述第一绝缘层位于所述位线主体朝向所述电容接触结构的侧壁；
    形成介质层，所述介质层位于所述第一绝缘层朝向所述电容接触结构的侧壁；
    形成第二绝缘层，所述第二绝缘层位于所述介质层朝向所述电容接触结构的侧壁。
PCT/CN2022/133246 2022-09-26 2022-11-21 半导体结构及其制作方法 Ceased WO2024065989A1 (zh)

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