WO2024065388A1 - 像素电路及其驱动方法、显示基板和显示装置 - Google Patents

像素电路及其驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2024065388A1
WO2024065388A1 PCT/CN2022/122558 CN2022122558W WO2024065388A1 WO 2024065388 A1 WO2024065388 A1 WO 2024065388A1 CN 2022122558 W CN2022122558 W CN 2022122558W WO 2024065388 A1 WO2024065388 A1 WO 2024065388A1
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Prior art keywords
transistor
signal line
electrode
node
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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PCT/CN2022/122558
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English (en)
French (fr)
Inventor
赵攀
青海刚
于子阳
蒋志亮
王苗
胡明
张跳梅
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Filing date
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to GB2410822.7A priority Critical patent/GB2629322A/en
Priority to CN202280003387.9A priority patent/CN119032391A/zh
Priority to DE112022007829.4T priority patent/DE112022007829T5/de
Priority to PCT/CN2022/122558 priority patent/WO2024065388A1/zh
Priority to US18/691,051 priority patent/US12579935B2/en
Publication of WO2024065388A1 publication Critical patent/WO2024065388A1/zh
Anticipated expiration legal-status Critical
Priority to US19/424,170 priority patent/US20260112319A1/en
Ceased legal-status Critical Current

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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • H—ELECTRICITY
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Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a pixel circuit configured to drive a light-emitting device to emit light, comprising: a node control subcircuit, a storage subcircuit, a driving subcircuit and a light-emitting control subcircuit;
  • a node control subcircuit electrically connected to the first node, the second node, the third node, the fourth node, the first scan signal line, the second scan signal line, the first initial signal line, the second initial signal line, the reset signal line, the data signal line and the first power line, respectively, and configured to provide the signal of the first initial signal line or the third node to the first node, provide the signal of the second initial signal line to the fourth node, and provide the signal of the data signal line to the second node under the control of the reset signal line, the first scan signal line and the second scan signal line;
  • the storage subcircuit is electrically connected to the second node and the first power line respectively, and is configured to charge the second node when the first scanning signal line is a valid level signal.
  • a driving subcircuit electrically connected to the first node, the second node and the third node respectively, and configured to provide a driving current to the third node under the control of the first node and the second node;
  • a light emitting control subcircuit electrically connected to the light emitting signal line, the first power line, the second node, the third node and the fourth node, respectively, and configured to provide a signal of the first power line to the second node and provide a signal of the third node to the fourth node under the control of the light emitting signal line;
  • a first electrode of the light emitting device is connected to the fourth node, and a second electrode of the light emitting device is connected to the second power line.
  • a time period during which the signal of the reset signal line is an effective level signal includes a first time period and a second time period, and the first time period occurs before the second time period; a time period during which the signal of the first scan signal line is an effective level signal includes a third time period and a fourth time period, and the third time period occurs before the fourth time period; a time period during which the signal of the second scan signal line is an effective level signal includes a fifth time period and a sixth time period, and the fifth time period occurs before the sixth time period, the second time period and the third time period at least partially overlap, and the fourth time period and the fifth time period at least partially overlap;
  • the signal of the light-emitting signal line is an invalid level signal.
  • the signals of the reset signal line, the first scanning signal line and the second scanning signal line are invalid level signals.
  • the node control subcircuit includes: a reset subcircuit, a write subcircuit, and a compensation subcircuit;
  • the reset subcircuit is electrically connected to the reset signal line, the first initial signal line, the second initial signal line, the first node and the fourth node respectively, and is configured to provide a signal of the first initial signal line to the first node and a signal of the second initial signal line to the fourth node under the control of the reset signal line;
  • the writing subcircuit is electrically connected to the first scanning signal line, the data signal line and the second node respectively, and is configured to provide a signal of the data signal line to the second node under the control of the first scanning signal line;
  • the compensation subcircuit is electrically connected to the second scan signal line, the first node and the third node respectively, and is configured to provide a signal of the third node to the first node under the control of the second scan signal line;
  • the energy storage subcircuit is electrically connected to the first node and the first power line, respectively, and is configured to store a voltage difference of a signal between the first node and the first power line.
  • the reset subcircuit is further connected to the first scan signal line and is configured to provide a signal of the first initial signal line to the first node and provide a signal of the second initial signal line to the fourth node under the control of the reset signal line and the first scan signal line.
  • the reset subcircuit includes a first transistor and a seventh transistor
  • the write subcircuit includes a fourth transistor
  • the compensation subcircuit includes: a second transistor
  • the energy storage subcircuit includes: a first capacitor
  • the control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node;
  • a control electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node;
  • the control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node;
  • One end of the first capacitor is electrically connected to the first power line, and the other end of the first capacitor is electrically connected to the first node.
  • the reset subcircuit includes a first transistor, a seventh transistor, and an eighth transistor
  • the write subcircuit includes a fourth transistor
  • the compensation subcircuit includes: a second transistor
  • the energy storage subcircuit includes: a first capacitor
  • the control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first electrode of the eighth transistor;
  • the control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node;
  • a control electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node;
  • the control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node;
  • a control electrode of the eighth transistor is electrically connected to the first scan signal line, and a second electrode of the eighth transistor is electrically connected to the first node;
  • One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the first power line.
  • the storage subcircuit includes: a second capacitor
  • One end of the second capacitor is electrically connected to the first power line, and the other end of the second capacitor is electrically connected to the second node.
  • the node control subcircuit includes: a first transistor, a second transistor, a fourth transistor, a seventh transistor and a first capacitor
  • the storage subcircuit includes: a second capacitor
  • the driving subcircuit includes a third transistor
  • the light emitting control subcircuit includes: a fifth transistor and a sixth transistor
  • the control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the second scanning signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node;
  • the control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;
  • a control electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node;
  • the control electrode of the fifth transistor is electrically connected to the light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node;
  • the control electrode of the sixth transistor is electrically connected to the light emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node;
  • the control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node;
  • One end of the first capacitor is electrically connected to the first power line, and the other end of the first capacitor is electrically connected to the first node;
  • One end of the second capacitor is electrically connected to the first power line, and the other end of the second capacitor is electrically connected to the second node.
  • the node control subcircuit includes: a first transistor, a second transistor, a fourth transistor, a seventh transistor, an eighth transistor and a first capacitor;
  • the storage subcircuit includes: a second capacitor;
  • the driving subcircuit includes a third transistor, and the light emitting control subcircuit includes: a fifth transistor and a sixth transistor;
  • the control electrode of the first transistor is electrically connected to the reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first electrode of the eighth transistor;
  • the control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node;
  • the control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;
  • a control electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node;
  • the control electrode of the fifth transistor is electrically connected to the light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the second node;
  • the control electrode of the sixth transistor is electrically connected to the light emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node;
  • the control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fourth node;
  • the control electrode of the eighth transistor is electrically connected to the first scan signal line, and the second electrode of the eighth transistor is electrically connected to the first node;
  • One end of the first capacitor is electrically connected to the first power line, and the other end of the first capacitor is electrically connected to the first node;
  • One end of the second capacitor is electrically connected to the first power line, and the other end of the second capacitor is electrically connected to the second node.
  • the present disclosure also provides a display substrate, comprising: a substrate and a driving circuit layer and a light-emitting structure layer sequentially arranged on the substrate, the driving circuit layer comprising the above-mentioned pixel circuit, multiple first initial signal lines, multiple second initial signal lines, multiple first scanning signal lines, multiple second scanning signal lines, multiple reset signal lines, multiple first power lines and multiple data signal lines, and the light-emitting structure layer comprising: a light-emitting device.
  • the driving circuit layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer sequentially stacked on the substrate
  • the pixel circuit includes: a plurality of transistors, a first capacitor and a second capacitor, the first capacitor and the second capacitor include: a first plate and a second plate;
  • the semiconductor layer at least includes: an active layer of a plurality of transistors and a first plate of a second capacitor;
  • the first conductive layer at least includes: a reset signal line, a light emitting signal line, control electrodes of a plurality of transistors, and a first electrode plate of a first capacitor;
  • the second conductive layer at least includes: a second initial signal line, a second electrode plate of the first capacitor and a second electrode plate of the second capacitor;
  • the third conductive layer at least includes: a first scanning signal line and a second scanning signal line;
  • the fourth conductive layer at least includes: a first initial signal line, a first power line and a data signal line.
  • the pixel circuit includes first to seventh transistors, and an active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region;
  • the length of the first area of the active layer of the third transistor along the first direction is greater than the length of the second area of the active layer of the third transistor along the first direction, and the first area of the active layer of the third transistor is reused as the first plate of the second capacitor.
  • the second plate of the first capacitor is connected to the second plate of the second capacitor, and the second plate of the second capacitor of the pixel circuit in the Nth column in the same row is connected to the second plate of the first capacitor of the pixel circuit in the N+1th column;
  • the length of the second plate of the first capacitor along the second direction is smaller than the length of the second plate of the second capacitor along the second direction, and the first direction intersects with the second direction.
  • the second electrode plate of the second capacitor includes: a capacitor body extending along the second direction and a first connecting block and a second connecting block extending along the first direction; the first connecting block and the second connecting block are respectively connected to the capacitor body, and the first connecting block and the second connecting block are arranged in parallel and are located on a side of the capacitor body away from the second electrode plate of the first capacitor;
  • the orthographic projection of the capacitor body on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the second capacitor on the substrate, the orthographic projection of the first connecting block on the substrate partially overlaps with the orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor on the substrate, and the orthographic projection of the second connecting block on the substrate partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate;
  • the second plate of the first capacitor is connected to the capacitor body, and the second connection block of the Nth column pixel circuit in the same row is connected to the second plate of the first capacitor of the N+1th column pixel circuit.
  • the length of the first power line along the first direction is greater than the length of the data signal line along the first direction and greater than the length of the first initial signal line along the first direction, and the length of the first initial signal line along the first direction is greater than the length of the data signal line along the first direction.
  • the driving circuit layer includes: a blocking layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer
  • the pixel circuit includes: a plurality of transistors, a first capacitor and a second capacitor, the first capacitor includes: a first plate and a second plate, the second capacitor includes: a first plate, a second plate and a third plate;
  • the shielding layer comprises at least: a first plate of a second capacitor, the shielding layer being configured to transmit a high voltage power signal;
  • the semiconductor layer at least includes: an active layer of a plurality of transistors, a second plate of a second capacitor, a first initial signal line and a second initial signal line;
  • the first conductive layer at least includes: a light-emitting signal line, control electrodes of a plurality of transistors and a first electrode plate of a first capacitor;
  • the second conductive layer at least includes: a second plate of the first capacitor and a third plate of the second capacitor;
  • the third conductive layer at least includes: two reset signal lines, a first scan signal line and a second scan signal line;
  • the fourth conductive layer may include: a first power line and a data signal line.
  • the plurality of transistors include: a first transistor to an eighth transistor, the shielding layer further includes: a first shielding structure, a second shielding structure, a first shielding connection structure, a second shielding connection structure, a third shielding connection structure, and a fourth shielding connection structure, and the first plate of the second capacitor is reused as the second shielding structure;
  • the first shielding connection structure and the second shielding structure are respectively located on two opposite sides of the first shielding structure and connected to the first shielding structure, and the second shielding connection structure is located on a side of the second shielding structure away from the first shielding structure and connected to the second shielding structure.
  • the third shielding connection structure and the fourth shielding connection structure are respectively located on the other two opposite sides of the first shielding structure, and the third shielding connection structure is connected to the second shielding structure, and the fourth shielding connection structure is connected to the first shielding structure;
  • the orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the channel region of the active layer of the third transistor on the substrate
  • the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the second plate of the second capacitor on the substrate
  • the orthographic projection of the third shielding connection structure on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate
  • the orthographic projection of the fourth shielding connection structure on the substrate at least partially overlaps with the orthographic projection of the active layer of the seventh transistor on the substrate.
  • the second shielding structure of the Nth column sub-pixel located in the same row is located on the side of the first shielding structure of the Nth column sub-pixel close to the first shielding structure of the N+1th column sub-pixel
  • the first shielding connection structure of the Nth column sub-pixel located in the same row is located on the side of the first shielding structure of the Nth column sub-pixel close to the first shielding structure of the N-1th column sub-pixel, and is connected to the fourth shielding connection structure of the N-1th column sub-pixel.
  • the second shielding connection structure of the Nth column sub-pixel located in the same row is connected to the first shielding connection structure of the N+1th column sub-pixel;
  • the third shielding connection structure of the Mth row sub-pixel located in the same column is located on the side of the first shielding structure 11 of the Mth row sub-pixel close to the first shielding structure of the M-1th row sub-pixel, and is connected to the fourth shielding connection structure of the M-1th row sub-pixel.
  • the fourth shielding connection structure of the Mth row sub-pixel located in the same column is located on the side of the first shielding structure of the Mth row sub-pixel close to the first shielding structure of the M+1th row sub-pixel, and is connected to the fifth shielding connection structure of the M+1th row sub-pixel.
  • the second plate of the first capacitor and the third plate of the second capacitor are connected to each other;
  • the third electrode plate of the second capacitor of the sub-pixel in the Nth column is located near the second electrode plate of the first capacitor of the sub-pixel in the Nth column, close to the second electrode plate of the first capacitor of the sub-pixel in the N+1th column, and connected to the second electrode plate of the first capacitor of the sub-pixel in the N+1th column;
  • the length of the second plate of the first capacitor along the second direction is smaller than the length of the third plate of the second capacitor along the second direction.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate.
  • it further includes: a gate driving circuit, the gate driving circuit including: K+2 cascaded shift registers, K being the total number of rows of pixel circuits;
  • the first-stage shift register is connected to the reset signal line connected to the first row of pixel circuits
  • the second-stage shift register is respectively connected to the first scanning signal line connected to the first row of pixel circuits and the reset signal line connected to the second row of pixel circuits
  • the i-th-stage shift register is respectively connected to the second scanning signal line connected to the i-2-th row of pixel circuits
  • the K+1-th-stage shift register is respectively connected to the second scanning signal line connected to the K-1-th row of pixel circuits and the first scanning signal line connected to the K-th row of pixel circuits
  • the present disclosure further provides a method for driving a pixel circuit, which is configured to drive the above-mentioned pixel circuit, and the method includes:
  • the node control subcircuit provides the signal of the first initial signal line or the third node to the first node, provides the signal of the second initial signal line to the fourth node, and provides the signal of the data signal line to the second node under the control of the reset signal line, the first scan signal line and the second scan signal line;
  • the storage sub-circuit charges the second node when the first scanning signal line is a valid level signal
  • a driving current is provided to the third node
  • the light emitting control subcircuit Under the control of the light emitting signal line, the light emitting control subcircuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node.
  • FIG1 is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of the structure of a node control subcircuit
  • FIG3 is a schematic diagram of the structure of another node control subcircuit
  • FIG4 is an equivalent circuit diagram of a pixel circuit
  • FIG5 is an equivalent circuit diagram of another pixel circuit
  • FIG6 is a working timing diagram of the pixel circuit provided in FIG4 and FIG5 ;
  • FIG7 is a first structural schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG8 is a second structural schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of the display substrate provided in FIG7 after a semiconductor layer pattern is formed
  • FIG10 is a schematic diagram of a first conductive layer pattern of a display substrate provided in FIG7 ;
  • FIG11 is a schematic diagram of the display substrate provided in FIG7 after a first conductive layer pattern is formed
  • FIG12 is a schematic diagram of a second conductive layer pattern of the display substrate provided in FIG7 ;
  • FIG13 is a schematic diagram of the display substrate provided in FIG7 after a second conductive layer pattern is formed
  • FIG14 is a schematic diagram of the display substrate provided in FIG7 after a third insulating layer is formed;
  • FIG15 is a schematic diagram of a third conductive layer pattern of a display substrate provided in FIG7 ;
  • FIG16 is a schematic diagram of the display substrate provided in FIG7 after a third conductive layer pattern is formed
  • FIG17 is a schematic diagram of the display substrate provided in FIG7 after a fourth insulating layer pattern is formed;
  • FIG18 is a schematic diagram of a fourth conductive layer pattern of the display substrate provided in FIG7 ;
  • FIG19 is a schematic diagram of the display substrate provided in FIG7 after a fourth conductive layer pattern is formed
  • FIG20 is a schematic diagram of the display substrate provided in FIG8 after a shielding layer pattern is formed
  • FIG21 is a schematic diagram of a semiconductor layer pattern of a display substrate provided in FIG8 ;
  • FIG22 is a schematic diagram of the display substrate provided in FIG8 after a semiconductor layer pattern is formed
  • FIG23 is a schematic diagram of a first conductive layer pattern of the display substrate provided in FIG8 ;
  • FIG24 is a schematic diagram of the display substrate provided in FIG8 after a first conductive layer pattern is formed
  • FIG25 is a schematic diagram of a second conductive layer pattern of the display substrate provided in FIG8 ;
  • FIG26 is a schematic diagram of the display substrate provided in FIG8 after a second conductive layer pattern is formed
  • FIG27 is a schematic diagram of the display substrate provided in FIG8 after a fourth insulating layer pattern is formed
  • FIG28 is a schematic diagram of a third conductive layer pattern of the display substrate provided in FIG8 ;
  • FIG29 is a schematic diagram of the display substrate provided in FIG8 after a third conductive layer pattern is formed
  • FIG30 is a schematic diagram of the display substrate provided in FIG8 after a fifth insulating layer pattern is formed
  • FIG31 is a schematic diagram of a fourth conductive layer pattern of the display substrate provided in FIG8 ;
  • FIG32 is a schematic diagram of the display substrate provided in FIG8 after a fourth conductive layer pattern is formed
  • FIG. 33 is a connection diagram of a gate drive circuit.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the situation where the components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • Fig. 1 is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present disclosure.
  • the pixel circuit provided in an embodiment of the present disclosure is configured to drive a light-emitting device to emit light, and includes: a node control subcircuit, a storage subcircuit, a driving subcircuit and a light-emitting control subcircuit.
  • the node control subcircuit is electrically connected to the first node N1, the second node N2, the third node N3, the fourth node N4, the first scan signal line Gate1, the second scan signal line Gate2, the first initial signal line INIT1, the second initial signal line INIT2, the reset signal line Reset, the data signal line Data and the first power line VDD, respectively, and is configured to provide the signal of the first initial signal line INIT1 or the third node N3 to the first node N1, provide the signal of the second initial signal line INIT2 to the fourth node N4, and provide the signal of the data signal line D to the second node N2 under the control of the reset signal line Reset, the first scan signal line Gate1 and the second scan signal line Gate2.
  • a storage sub-circuit which is electrically connected to the second node N2 and the first power line VDD, respectively, and is configured to charge the second node N2 when the first scan signal line Gate1 is a valid level signal;
  • a driving sub-circuit which is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving current to the third node N3 under the control of the first node N1 and the second node N2;
  • a light-emitting control sub-circuit which is electrically connected to the light-emitting signal line EM, the first power line VDD, the second node N2, the third node N3 and the fourth node N4, respectively, and is configured to provide a signal of the first power line VDD to the second node N2 and a signal of the third node N3 to the fourth node N4 under the control of the light-emitting signal line EM;
  • a first electrode of the light-emitting device is
  • the first power line VDD continuously provides a high voltage power signal
  • the second power line VSS continuously provides a low voltage power signal
  • the initial signals of the first initial signal line INIT1 and the second initial signal line INIT2 may be the same, or may be different.
  • the first initial signal line INIT1 and the second initial signal line INIT2 may use the same signal line, or may use different signal lines, and the present disclosure does not make any limitation on this.
  • the light emitting device is electrically connected to the fourth node N4 and the second power line VSS, respectively.
  • the light emitting device may be an organic light emitting diode (OLED), including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).
  • OLED organic light emitting diode
  • the anode of the organic light emitting diode is electrically connected to the fourth node N4, and the cathode of the organic light emitting diode is electrically connected to the second power line VSS.
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the electron transport layers of all sub-pixels may be a common layer connected together
  • the hole blocking layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • An embodiment of the present disclosure provides a pixel circuit.
  • the present disclosure sets a storage sub-circuit so that when the first scanning signal line Gate1 is a valid level signal, the second node N2 is charged, and the circuit can be discharged after the signal of the first scanning signal line Gate1 is a valid level signal.
  • the charging time of the first node N1 is extended while ensuring a high refresh rate of the display product, thereby improving the display effect of the display product.
  • the time period during which the signal of the reset signal line Reset is an effective level signal includes a first time period and a second time period, and the first time period occurs before the second time period;
  • the time period during which the signal of the first scan signal line Gate1 is an effective level signal includes a third time period and a fourth time period, and the third time period occurs before the fourth time period;
  • the time period during which the signal of the second scan signal line Gate2 is an effective level signal includes a fifth time period and a sixth time period, and the fifth time period occurs before the sixth time period, the second time period and the third time period at least partially overlap, and the fourth time period and the fifth time period at least partially overlap.
  • the second time period and the third time period may be the same time period, and the fourth time period and the fifth time period may be the same time period.
  • the signal of the light emitting signal line EM when the signals of the reset signal line Reset, the first scanning signal line Gate1, and the second scanning signal line Gate2 are valid level signals, the signal of the light emitting signal line EM is an invalid level signal; when the signal of the light emitting signal line EM is a valid level signal, the signals of the reset signal line Reset, the first scanning signal line Gate1, and the second scanning signal line Gate2 are invalid level signals.
  • Fig. 2 is a schematic diagram of the structure of a node control subcircuit.
  • the node control subcircuit may include: a reset subcircuit, a write subcircuit, a compensation subcircuit and an energy storage subcircuit.
  • the reset subcircuit is electrically connected to the reset signal line Reset, the first initial signal line INIT1, the second initial signal line INIT2, the first node N1 and the fourth node N4, respectively, and is configured to provide the signal of the first initial signal line INIT1 to the first node N1 and the signal of the second initial signal line INIT2 to the fourth node N4 under the control of the reset signal line Reset;
  • the write subcircuit is electrically connected to the first scan signal line Gate1, the data signal line Data and the second node N2, respectively, and is configured to provide the signal of the data signal line Data to the second node N2 under the control of the first scan signal line Gate1;
  • the compensation subcircuit is electrically connected to the second scan signal line Gate2, the first power line VDD, the first node N1 and the third node N3, respectively, and is configured to provide the signal of the third node N3 to the first node N1 under the control of the second scan signal line Gate2;
  • the energy storage subcircuit is electrically connected to the
  • Fig. 3 is a schematic diagram of the structure of another node control subcircuit.
  • the reset subcircuit is also connected to the first scan signal line Gate1, and is configured to provide the signal of the first initial signal line INIT1 to the first node N1 and provide the signal of the second initial signal line INIT2 to the fourth node N4 under the control of the reset signal line Reset and the first scan signal line Gate1.
  • Fig. 4 is an equivalent circuit diagram of a pixel circuit.
  • the reset subcircuit may include a first transistor T1 and a seventh transistor T7
  • the write subcircuit may include a fourth transistor T4
  • the compensation subcircuit may include: a second transistor T2
  • the energy storage subcircuit may include: a first capacitor C1.
  • the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3;
  • the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2;
  • the control electrode of the seventh transistor T7 is electrically connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected
  • Fig. 5 is an equivalent circuit diagram of another pixel circuit.
  • the reset subcircuit may include a first transistor T1, a seventh transistor T7, and an eighth transistor T8, the write subcircuit includes a fourth transistor T4, the compensation subcircuit may include: a second transistor T2, and the energy storage subcircuit may include: a first capacitor C1.
  • the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the eighth transistor T8;
  • the control electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3;
  • the control electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2;
  • the control electrode of the seventh transistor T7 is electrically connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is
  • the storage sub-circuit may include: a second capacitor C2 , wherein one end of the second capacitor C2 is electrically connected to the first power line VDD, and the other end of the second capacitor C2 is electrically connected to the second node N2 .
  • the node control subcircuit may include: a first transistor T1, a second transistor T2, a fourth transistor T4, a seventh transistor T7 and a first capacitor C1
  • the storage subcircuit may include: a second capacitor C2
  • the driving subcircuit may include a third transistor T3
  • the light emitting control subcircuit may include: a fifth transistor T5 and a sixth transistor T6.
  • the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3;
  • the control electrode of the third transistor T3 is electrically connected to the first node, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3;
  • the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second no
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, realize low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the node control subcircuit may include: a first transistor T1, a second transistor T2, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8 and a first capacitor C1;
  • the storage subcircuit may include: a second capacitor C2;
  • the driving subcircuit may include a third transistor T3, and the light emitting control subcircuit may include: a fifth transistor T5 and a sixth transistor T6.
  • the control electrode of the first transistor T1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the eighth transistor T8;
  • the control electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3;
  • the control electrode of the third transistor T3 is electrically connected to the first node, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N4.
  • the third node N3 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the light emitting signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4
  • the control electrode of the seventh transistor T7 is electrically connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode
  • the first transistor T1 to the eighth transistor T8 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.
  • the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the eighth transistor T8 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, realize low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between its control electrode and the first electrode.
  • the fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors.
  • the signal of the light emitting signal line EM is an effective level signal
  • the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.
  • FIG. 4 An exemplary structure of the node control subcircuit, storage subcircuit, drive subcircuit and light control subcircuit is shown in Figures 4 and 5. It is easy for those skilled in the art to understand that the implementation of the node control subcircuit, storage subcircuit, drive subcircuit and light control subcircuit is not limited thereto.
  • FIG. 6 is a working timing diagram of the pixel circuit provided by FIG. 4 and FIG. 5 .
  • FIG. 6 is illustrated by taking an example that all transistors in the pixel circuit are P-type transistors.
  • the data signal line Data may output a data voltage in the second stage S2 and/or the third stage S3.
  • FIG. 6 is explained by taking the example that the data signal line Data outputs a data voltage in the second stage S2 and the third stage S3.
  • the display substrate where the pixel circuit is located includes: at least one gate driving circuit, the at least one gate driving circuit is electrically connected to at least one of the first scanning signal line, the second scanning signal line, the light emitting signal line and the reset signal line, and the gate driving circuit includes: a plurality of shift registers, when there is a cascade relationship between the plurality of shift registers, the data signal line Data can output the data voltage only in the third stage S3 or the second stage S2.
  • the data signal line Data outputs the data voltage in the third stage S3 or the second stage S2 to avoid crosstalk between signals, and can improve the display effect of the display substrate where the pixel circuit is located.
  • the working process of the pixel circuit of FIG4 may include:
  • the first stage S1 is called the initialization stage.
  • the signal of the reset signal line Reset is a low-level signal, and the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the light-emitting signal line EM are high-level signals.
  • the reset signal line Reset is a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, the signal of the first initial signal line INIT1 is written into the first node N1 through the turned-on first transistor T1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor T7, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the light-emitting signal line EM are high-level signals, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and in this stage, the light-emitting device L does not emit light.
  • the second stage S2 is called the charging stage, the signals of the reset signal line Reset and the first scanning signal line Gate1 are low level signals, the signals of the second scanning signal line Gate2 and the luminous signal line EM are high level signals, and the data signal line Data outputs a data voltage.
  • the reset signal line Reset is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are continuously turned on, the signal of the first initial signal line INIT1 is written into the first node N1 through the turned-on first transistor T1, the first node N1 is continuously initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed
  • the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor T7
  • the fourth node N4 is continuously initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed
  • the signal of the first scanning signal line Gate1 is a low-level signal
  • the fourth transistor T4 is turned on
  • the signal of the data signal line Data is written into the second node N2 through the turned-on fourth transistor T4 to charge the second capacitor C2, the signals of the second scanning signal line Gate2 and the light-emitting signal line EM are high-level signals
  • the second transistor T2 the fifth
  • the third stage S3 is called the data writing stage.
  • the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, the signals of the reset signal line Reset and the light-emitting signal line EM are high-level signals, and the data signal line Data outputs a data voltage.
  • the first node N1 is a low-level signal, and the third transistor T3 is turned on.
  • the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, the second transistor T2 and the fourth transistor T4 are turned on, and the data voltage output by the data signal line Data charges the first node N1.
  • the data voltage output by the data signal line Data is written to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2.
  • the signals of the reset signal line Reset and the light-emitting signal line EM are high-level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. In this stage, the voltage of the first node N1 is less than Vd-
  • the fourth stage S4 is called the discharge stage.
  • the signal of the second scan signal line Gate2 is a low-level signal, and the signals of the first scan signal line Gate1, the reset signal line Reset and the light-emitting signal line EM are high-level signals.
  • the third transistor T3 is continuously turned on.
  • the signal of the second scan signal line Gate2 is a low-level signal
  • the fourth transistor T4 is continuously turned on
  • the second capacitor C2 continues to charge the first node N1
  • the signal of the second node N2 is provided to the first node N1 through the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage of the first node N1 is Vd-
  • the signals of the first scan signal line Gate1, the reset signal line Reset and the light-emitting signal line EM are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.
  • the fifth stage S5 is called the light-emitting stage.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the reset signal line are high-level signals.
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the reset signal line are high-level signals
  • the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned off.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the second node N2, the third transistor T3, the third node N3, the turned-on sixth transistor T6 and the fourth node N4, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the present disclosure can continue to charge the first node N1 in the fourth stage S4 after the third stage, ie, the data writing stage, by setting the second capacitor C2, thereby extending the charging time of the first node N1 and effectively solving the technical problem of insufficient charging of the pixel circuit.
  • the operation process of the pixel circuit of FIG. 5 may include:
  • the first stage S1 is called the initialization stage.
  • the signal of the reset signal line Reset is a low-level signal, and the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the light-emitting signal line EM are high-level signals.
  • the reset signal line Reset is a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor T7, and the fourth node N4 is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the light-emitting signal line EM are high-level signals, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light-emitting device L does not emit light.
  • the second stage S2 is called the charging stage, the signals of the reset signal line Reset and the first scanning signal line Gate1 are low level signals, the signals of the second scanning signal line Gate2 and the luminous signal line EM are high level signals, and the data signal line Data outputs a data voltage.
  • the reset signal line Reset is a low-level signal
  • the first transistor T1 and the seventh transistor T7 are continuously turned on
  • the signal of the first scanning signal line Gate1 is a low-level signal
  • the eighth transistor T8 is turned on
  • the signal of the first initial signal line INIT1 is written into the first node N1 through the turned-on first transistor T1 and the turned-on eighth transistor T8, and the first node N1 is continuously initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor T7, and the fourth node N4 is continuously initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the signal of the first scanning signal line Gate1 is a low-level signal
  • the fourth transistor T4 is turned on
  • the signal of the data signal line Data is written into the second node N2 through the turned-on fourth transistor T4 to charge the second capacitor C2.
  • the signals of the second scanning signal line Gate2 and the light-emitting signal line EM are high-level signals.
  • the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the light-emitting device L does not emit light.
  • the third stage S3 is called the data writing stage.
  • the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, the signals of the reset signal line Reset and the light-emitting signal line EM are high-level signals, and the data signal line Data outputs a data voltage.
  • the first node N1 is a low-level signal, and the third transistor T3 is turned on.
  • the signals of the first scanning signal line Gate1 and the second scanning signal line Gate2 are low-level signals, the second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on, and the data voltage output by the data signal line Data charges the first node N1.
  • the data voltage output by the data signal line Data is written to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2.
  • the signals of the reset signal line Reset and the light-emitting signal line EM are high-level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. In this stage, the voltage of the first node N1 is less than Vd-
  • the fourth stage S4 is called the discharge stage.
  • the signal of the second scan signal line Gate2 is a low-level signal, and the signals of the first scan signal line Gate1, the reset signal line Reset and the light-emitting signal line EM are high-level signals.
  • the third transistor T3 is continuously turned on.
  • the signal of the second scan signal line Gate2 is a low-level signal
  • the fourth transistor T4 is continuously turned on
  • the second capacitor C2 continues to charge the first node N1
  • the signal of the second node N2 is provided to the first node N1 through the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage of the first node N1 is Vd-
  • the signals of the first scan signal line Gate1, the reset signal line Reset and the light-emitting signal line EM are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this stage, the light-emitting device L does not emit light.
  • the fifth stage S5 is called the light-emitting stage.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the reset signal line are high-level signals.
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2 and the reset signal line are high-level signals
  • the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned off.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the second node N2, the third transistor T3, the third node N3, the turned-on sixth transistor T6 and the fourth node N4, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the present disclosure can continue to charge the first node N1 in the fourth stage S4 after the third stage, i.e., the data writing stage, by setting the second capacitor C2, thereby extending the charging time of the first node N1, effectively solving the technical problem of insufficient charging of the pixel circuit, and improving the display effect of the display product.
  • FIG. 7 is a schematic diagram of the structure of the display substrate provided by the embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of the structure of the display substrate provided by the embodiment of the present disclosure. As shown in FIG. 7 and FIG.
  • the display substrate may include: a substrate, and a driving circuit layer and a light-emitting structure layer sequentially arranged on the substrate, the driving circuit layer includes a pixel circuit, a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, a plurality of first scanning signal lines Gate1, a plurality of second scanning signal lines Gate2, a plurality of reset signal lines Reset, a plurality of first power lines VDD and a plurality of data signal lines Data, and the light-emitting structure layer includes: a light-emitting device.
  • FIG. 7 is explained by taking the display substrate including the pixel circuit provided by FIG. 4 as an example
  • FIG. 8 is explained by taking the display substrate including the pixel circuit provided by FIG. 5 as an example.
  • the pixel circuit is the pixel circuit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be repeated here.
  • the display substrate may further include an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the display substrate may include other film layers, such as a touch control structure layer, etc., which are not limited in the present disclosure.
  • the display substrate may include: a plurality of sub-pixels, at least one sub-pixel may include: a pixel circuit and a light-emitting device, the pixel circuit being configured to output a corresponding current to the connected light-emitting device so that the light-emitting device emits light of corresponding brightness.
  • the plurality of sub-pixels may include a plurality of pixel rows and a plurality of pixel columns.
  • a plurality of sub-pixels arranged in sequence along the horizontal direction may be referred to as pixel rows
  • a plurality of sub-pixels arranged in sequence along the vertical direction may be referred to as pixel columns
  • the plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.
  • a plurality of sub-pixels constitute one pixel unit, and the pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, or a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel.
  • the first sub-pixel when the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel may be a red sub-pixel (R) emitting red light, the second sub-pixel may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light.
  • the shapes of the three sub-pixels may be triangles, rectangles, rhombuses, pentagons, or hexagons, etc., which are not limited in the present disclosure.
  • the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in sequence in an aligned manner, and in the direction of the pixel column, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in sequence in a staggered manner to form a sub-pixel layout.
  • the first sub-pixel in an odd row may be located between the adjacent second and third sub-pixels in an even row, or the first sub-pixel in an even row may be located between the adjacent second and third sub-pixels in an odd row.
  • the second subpixel in an odd-numbered row may be located between the adjacent first and third subpixels in an even-numbered row, or the second subpixel in an even-numbered row may be located between the adjacent first and third subpixels in an odd-numbered row.
  • the third subpixel in an odd-numbered row may be located between the adjacent first and second subpixels in an even-numbered row, or the third subpixel in an even-numbered row may be located between the adjacent first and second subpixels in an odd-numbered row.
  • the first sub-pixel when the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, the third sub-pixel and the fourth sub-pixel may be green sub-pixels (G) that emit green light, and the shapes of the three sub-pixels may be triangles, rectangles, rhombuses, pentagons, or hexagons, etc., which are not limited in the present disclosure.
  • R red sub-pixel
  • B blue sub-pixel
  • G green sub-pixels
  • the shapes of the three sub-pixels may be triangles, rectangles, rhombuses, pentagons, or hexagons, etc., which are not limited in the present disclosure.
  • the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, which are not limited in the present disclosure.
  • the four sub-pixels may be arranged in a square manner to form a GGRB pixel arrangement.
  • the four sub-pixels may be arranged in a diamond manner to form an RGGB pixel arrangement.
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the display substrate may be a low temperature polycrystalline silicon (Low Temperature Poly-Silicon, referred to as LTPS) display substrate or a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, referred to as LTPO) display substrate.
  • LTPS Low Temperature Poly-Silicon
  • LTPO low temperature polycrystalline oxide
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the light-emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on the substrate;
  • the anode layer includes: an anode
  • the organic structure layer includes: an organic light-emitting layer
  • the cathode layer includes: a cathode.
  • the driving circuit layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer sequentially stacked on the substrate
  • the pixel circuit includes: a plurality of transistors, a first capacitor and a second capacitor, the first capacitor and the second capacitor include: a first plate and a second plate;
  • the semiconductor layer at least includes: an active layer of a plurality of transistors and a first plate of a second capacitor;
  • the first conductive layer at least includes: a reset signal line, a light emitting signal line, control electrodes of a plurality of transistors, and a first electrode plate of a first capacitor;
  • the second conductive layer at least includes: a second initial signal line, a second electrode plate of the first capacitor and a second electrode plate of the second capacitor;
  • the third conductive layer at least includes: a first scanning signal line and a second scanning signal line;
  • the fourth conductive layer at least includes: a first initial signal line, a first power line and a data signal line.
  • the pixel circuit includes first to seventh transistors, and an active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region;
  • the length of the first area of the active layer of the third transistor along the first direction is greater than the length of the second area of the active layer of the third transistor along the first direction, and the first area of the active layer of the third transistor is reused as the first plate of the second capacitor.
  • the second plate of the first capacitor is connected to the second plate of the second capacitor, and the second plate of the second capacitor of the pixel circuit in the Nth column in the same row is connected to the second plate of the first capacitor of the pixel circuit in the N+1th column;
  • the length of the second plate of the first capacitor along the second direction is smaller than the length of the second plate of the second capacitor along the second direction, and the first direction intersects the second direction.
  • the second electrode plate of the second capacitor includes: a capacitor body extending along the second direction and a first connecting block and a second connecting block extending along the first direction; the first connecting block and the second connecting block are respectively connected to the capacitor body, and the first connecting block and the second connecting block are arranged in parallel and are located on a side of the capacitor body away from the second electrode plate of the first capacitor;
  • the orthographic projection of the capacitor body on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the second capacitor on the substrate, the orthographic projection of the first connecting block on the substrate partially overlaps with the orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor on the substrate, and the orthographic projection of the second connecting block on the substrate partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate;
  • the second plate of the first capacitor is connected to the capacitor body, and the second connection block of the Nth column pixel circuit in the same row is connected to the second plate of the first capacitor of the N+1th column pixel circuit.
  • the length of the first power line along the first direction is greater than the length of the data signal line along the first direction and greater than the length of the first initial signal line along the first direction, and the length of the first initial signal line along the first direction is greater than the length of the data signal line along the first direction.
  • the driving circuit layer includes: a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer
  • the pixel circuit includes: a plurality of transistors, a first capacitor and a second capacitor, the first capacitor includes: a first plate and a second plate, the second capacitor includes: a first plate, a second plate and a third plate;
  • the shielding layer comprises at least: a first plate of a second capacitor, the shielding layer being configured to transmit a high voltage power signal;
  • the semiconductor layer at least includes: an active layer of a plurality of transistors, a second electrode plate of a second capacitor, a first initial signal line and a second initial signal line;
  • the first conductive layer at least includes: a light-emitting signal line, control electrodes of a plurality of transistors and a first electrode plate of a first capacitor;
  • the second conductive layer at least includes: a second plate of the first capacitor and a third plate of the second capacitor;
  • the third conductive layer at least includes: two reset signal lines, a first scan signal line and a second scan signal line;
  • the fourth conductive layer at least includes: a first power line and a data signal line.
  • the plurality of transistors include: a first transistor to an eighth transistor, the shielding layer further includes: a first shielding structure, a second shielding structure, a first shielding connection structure, a second shielding connection structure, a third shielding connection structure, and a fourth shielding connection structure, and the first plate of the second capacitor is reused as the second shielding structure;
  • the first shielding connection structure and the second shielding structure are respectively located on two opposite sides of the first shielding structure and are connected to the first shielding structure;
  • the second shielding connection structure is located on a side of the second shielding structure away from the first shielding structure and is connected to the second shielding structure;
  • the third shielding connection structure and the fourth shielding connection structure are respectively located on the other two opposite sides of the first shielding structure, and the third shielding connection structure is connected to the second shielding structure, and the fourth shielding connection structure is connected to the first shielding structure;
  • the orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the channel region of the active layer of the third transistor on the substrate
  • the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the second plate of the second capacitor on the substrate
  • the orthographic projection of the third shielding connection structure on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate
  • the orthographic projection of the fourth shielding connection structure on the substrate at least partially overlaps with the orthographic projection of the active layer of the seventh transistor on the substrate.
  • the second blocking structure of the sub-pixel in the Nth column located in the same row is located on a side of the first blocking structure of the sub-pixel in the Nth column close to the first blocking structure of the sub-pixel in the N+1th column
  • the first blocking connection structure of the sub-pixel in the Nth column located in the same row is located on a side of the first blocking structure of the sub-pixel in the Nth column close to the first blocking structure of the sub-pixel in the N-1th column, and is connected to the fourth blocking connection structure of the sub-pixel in the N-1th column
  • the second blocking connection structure of the sub-pixel in the Nth column located in the same row is connected to the first blocking connection structure of the sub-pixel in the N+1th column
  • the third blocking connection structure of the sub-pixel in the Mth row located in the same column is located on a side of the first blocking structure 11 of the sub-pixel in the Mth row close to the first blocking structure of the sub-pixel in the M-1th row, and is connected to the fourth blocking connection structure of
  • the second plate of the first capacitor and the third plate of the second capacitor are connected to each other;
  • the third electrode plate of the second capacitor of the sub-pixel in the Nth column is located near the second electrode plate of the first capacitor of the sub-pixel in the Nth column, close to the second electrode plate of the first capacitor of the sub-pixel in the N+1th column, and connected to the second electrode plate of the first capacitor of the sub-pixel in the N+1th column;
  • the length of the second plate of the first capacitor along the second direction is smaller than the length of the third plate of the second capacitor along the second direction.
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the manufacturing process of the display substrate provided in FIG7 using a pixel circuit with one row and two columns may include:
  • forming a semiconductor layer pattern may include: sequentially depositing semiconductor thin films on a substrate, patterning the semiconductor thin films by a patterning process, and forming a semiconductor layer pattern, as shown in FIG9 , which is a schematic diagram of the display substrate provided in FIG7 after a semiconductor layer pattern is formed.
  • the semiconductor layer pattern of each sub-pixel may include at least an active layer T11 of a first transistor to an active layer T71 of a seventh transistor.
  • the active layer T11 of the first transistor to the active layer T61 of the sixth transistor are an integral structure connected to each other.
  • the active layer T21 of the second transistor and the active layer T61 of the sixth transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel
  • the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel
  • the active layer T21 of the second transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in the present subpixel.
  • the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor, and the active layer T71 of the seventh transistor may be located on the same layer of the active layer T31 of the third transistor in the present subpixel, and the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor may be located on the other side of the active layer T31 of the third transistor in the present subpixel.
  • the active layer T11 of the first transistor may have an “n” shape
  • the active layer T21 of the second transistor may have an “L” shape
  • the active layer T31 of the third transistor may have an “ ⁇ ” shape
  • the active layer T41 of the fourth transistor the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor
  • the active layer T71 of the seventh transistor may have an “I” shape.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region T11_2 of the active layer T11 of the first transistor may serve as the first region T21_1 of the active layer T21 of the second transistor
  • the first region T31_1 of the active layer T31 of the third transistor may serve as the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor
  • the second region T31_2 of the active layer T31 of the third transistor may serve as the second region T21_2 of the active layer T21 of the second transistor and the first region T61_1 of the active layer T61 of the sixth transistor
  • the second region T61_2 of the active layer T61 of the sixth transistor can serve as the second region T71_2 of the active layer T71 of the seventh transistor
  • the first region T11_1 of the active layer T11 of the sixth transistor can serve as the second region T71_2 of
  • the shape of the first region T31_1 of the active layer T31 of the third transistor may be a strip structure extending along the second direction Y, and the length along the first direction X may be greater than the length of the first region T41_1 of the active layer T41 of the fourth transistor and the first region T51_1 of the active layer T51 of the fifth transistor along the first direction.
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, and forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the first insulating layer, as shown in FIGS. 10 and 11, wherein FIG. 10 is a schematic diagram of the first conductive layer pattern of the display substrate provided in FIG. 7, and FIG. 11 is a schematic diagram of the display substrate provided in FIG. 7 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each sub-pixel may include at least a reset signal line Reset, a light emitting signal line EM, control electrodes T12 to T72 of the first transistor, and a first plate C11 of the first capacitor.
  • the shape of the first electrode plate C11 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered, and the orthographic projection of the first electrode plate C11 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate.
  • the first electrode plate C11 of the first capacitor can also serve as the control electrode T32 of the third transistor T3.
  • the reset signal line Reset may be in the shape of a line extending along the first direction X, and the reset signal line Reset may be located on the side of the first plate C11 of the first capacitor away from the light emitting signal line EM.
  • the area where the reset signal line Reset overlaps with the active layer of the first transistor T1 serves as the control electrode T12 of the first transistor, and the area where the reset signal line Reset overlaps with the active layer of the seventh transistor serves as the control electrode T72 of the seventh transistor.
  • the active layer T11 of the first transistor may be in the shape of an "n"
  • the reset signal line Reset overlaps with the active layer of the first transistor, that is, there are two control electrodes T12 of the first transistor, and the first transistor has a dual-gate structure.
  • the shape of the light emitting signal line EM can be a line shape extending along the first direction X, and the area where the light emitting signal line EM overlaps with the active layer of the fifth transistor T5 serves as the control electrode T52 of the fifth transistor T5, and the area where the light emitting signal line EM overlaps with the active layer of the sixth transistor T6 serves as the control electrode T62 of the sixth transistor T6.
  • control electrode T22 of the second transistor T2 and the control electrode T42 of the fourth transistor T4 can be located on a side of the first plate C11 of the first capacitor close to the reset signal line Reset, and the control electrode T42 of the fourth transistor of the present sub-pixel is located on a side of the control electrode T22 of the second transistor T2 of the present sub-pixel close to the control electrode T22 of the second transistor T2 of the adjacent column sub-pixel.
  • the control electrode T22 of the second transistor may include a first electrode connection portion T22A and a second electrode connection portion T22B, and the first electrode connection portion T22A is located on a side of the second electrode connection portion T22B away from the control electrode T42 of the fourth transistor, the first electrode connection portion T22A is in the shape of a line extending along the first direction X, the second electrode connection portion T22B is in the shape of a line extending along the second direction Y, and the orthographic projections of the first electrode connection portion T22A and the second electrode connection portion T22B on the substrate partially overlap with the orthographic projections of the active layer of the second transistor on the substrate, therefore, there are two regions where the control electrode T22 of the second transistor overlaps with the active layer T21 of the second transistor, that is, there are two control electrodes T22 of the second transistor, and the second transistor has a dual-gate structure.
  • the shape of the control electrode T42 of the fourth transistor may be a line shape extending along the first direction X.
  • the reset signal line Reset and the light-emitting signal line EM can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the semiconductor layer can be conductorized by using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer forms the channel area of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the active layer of the first transistor to the seventh transistor are both conductorized, and the first area of the active layer of the third transistor after conductorization (also the second area of the active layer of the fourth transistor and the second area of the active layer of the fifth transistor) can be used as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor, the second electrode T54 of the fifth transistor, and the first electrode C21 of the second capacitor at the same time, and the second area T31_2 of the active layer T31 of the third transistor after conductorization (also the second area T21_2 of the active layer T21 of the second transistor and the first area
  • forming the second conductive layer pattern may include: depositing a second insulating layer film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer.
  • Figure 12 is a schematic diagram of the second conductive layer pattern of the display substrate provided in Figure 7
  • Figure 13 is a schematic diagram of the display substrate provided in Figure 7 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each sub-pixel may include at least a second initial signal line INIT2 , a second plate C12 of the first capacitor, and a second plate C22 of the second capacitor.
  • the second plate C12 of the first capacitor and the second plate C22 of the second capacitor are an integral structure connected to each other.
  • the second plate C12 of the first capacitor may be in a rectangular shape, and the corners of the rectangle may be chamfered, and the orthographic projection of the second plate C12 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the first capacitor on the substrate.
  • An opening V0 is provided on the second plate C12 of the first capacitor, and the shape of the opening V0 may be rectangular, and may be located in the middle of the second plate C12 of the first capacitor, so that the second plate C12 of the first capacitor forms a ring structure.
  • the opening exposes the second insulating layer covering the first plate of the first capacitor, and the orthographic projection of the first plate of the first capacitor on the substrate includes the orthographic projection of the opening V0 on the substrate.
  • the second electrode plate C22 of the second capacitor may include: a capacitor main body C22_1, a first connection block C22_2, and a second connection block C22_3 connected to each other.
  • the capacitor main body C22_1 may be in the shape of a line extending along the second direction Y
  • the first connection block C22_2 and the second connection block C22_3 may be in the shape of a line extending along the first direction X.
  • the first connection block C22_2 and the second connection block C22_3 may be located on a side of the capacitor main body C22_1 away from the second electrode plate C12 of the first capacitor, and the first connection block C22_2 and the second connection block C22_3 are arranged along the second direction Y, that is, the second electrode plate C22 of the second capacitor may be a combing structure, the capacitor main body C22_1 may be used as a comb back, and the first connection block C22_2 and the second connection block C22_3 may be used as comb teeth, respectively.
  • an orthographic projection of the capacitor body portion C22_1 on the substrate at least partially overlaps an orthographic projection of the first electrode plate of the second capacitor on the substrate.
  • the orthographic projection of the first connection block C22_2 on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor on the substrate.
  • the orthographic projection of the first connection block on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor on the substrate, so that the active layer of the second transistor located between the control electrodes of the second transistor can be shielded by the first connection block, which can effectively prevent leakage, thereby improving the reliability of the display substrate.
  • the orthographic projection of the second connection block C22_3 on the substrate at least partially overlaps with the orthographic projection of the second region of the active layer of the third transistor (also the second region of the active layer of the second transistor and the first region of the active layer of the sixth transistor) on the substrate.
  • a virtual straight line extending along the first direction X does not pass through the second plate C12 of the first capacitor and the first connection block C22_2 at the same time, and a virtual straight line extending along the first direction passes through the second plate C12 of the first capacitor and the first connection block C22_2.
  • the second plate C12 of the first capacitor in the present subpixel is connected to the capacitor body of the second plate C22 of the second capacitor.
  • the second connection block of the present subpixel is connected to the second plate C12 of the first capacitor of the adjacent subpixel.
  • the length of the second plate C12 of the first capacitor along the second direction Y is less than the length of the second plate C22 of the second capacitor along the second direction Y.
  • the length of the first connection block C22_2 along the second direction Y may be the same as or different from the length of the second connection block C22_3 along the second direction Y, and the present disclosure does not make any limitation thereto.
  • the second initial signal line INIT2 may be in a line shape extending in the first direction X, and the second initial signal line INIT2 may be located on a side of the reset signal line away from the first plate of the first capacitor.
  • the orthographic projection of the second initial signal line INIT2 on the substrate may partially overlap with the orthographic projections of the active layer of the seventh transistor and the active layer of the first transistor on the substrate.
  • the second plate C12 of the first capacitor of the sub-pixels arranged along the first direction X is connected to the second plate C22 of the second capacitor of the adjacent sub-pixel, so that the signals flowing through the second plate C12 of the first capacitor and the second plate C22 of the second capacitor of the sub-pixels arranged along the first direction X are the same, thereby improving the display uniformity of the display substrate.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG. 14 , which is a schematic diagram of the display substrate provided in FIG. 7 after the third insulating layer is formed.
  • the multiple via holes of the third insulating layer of each sub-pixel may include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10 and an eleventh via hole V11.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the active layer of the first transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first region of the active layer of the first transistor through the via hole.
  • the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the first transistor (also the first area of the active layer of the second transistor) on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second area of the active layer of the first transistor (also the first area of the active layer of the second transistor), and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor) to the first area of the active layer of the first transistor (also the first area of the active layer of the second transistor) through the via.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active layer of the fourth transistor through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the first area of the active layer of the fifth transistor, and the fourth via hole V4 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of the active layer of the fifth transistor through the via hole.
  • the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the sixth transistor (also the second area of the active layer of the seventh transistor) on the substrate, the first insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the second area of the active layer of the sixth transistor (also the second area of the active layer of the seventh transistor), and the fifth via V5 is configured to connect the second electrode of the subsequently formed sixth transistor T1 (also the second electrode of the seventh transistor) to the second area of the active layer of the sixth transistor (also the second area of the active layer of the seventh transistor) through the via.
  • the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the seventh transistor on the substrate, the first insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the first area of the active layer of the seventh transistor, and the sixth via V6 is configured to connect the first electrode of the subsequently formed seventh transistor to the first area of the active layer of the seventh transistor through the via.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second electrode connecting portion of the control electrode of the second transistor on the substrate, the second insulating layer in the seventh via hole V7 is etched away to expose the surface of the control electrode of the second transistor, and the seventh via hole V7 is configured to connect a subsequently formed second scanning signal line to the control electrode of the second transistor through the via hole.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the opening on the substrate, the second insulating layer in the eighth via V8 is etched away to expose the surface of the first plate of the first capacitor (also the control electrode of the third transistor), and the eighth via V8 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the first plate of the first capacitor (also the control electrode of the third transistor) through the via.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the control electrode of the fourth transistor on the substrate, the second insulating layer in the ninth via hole V9 is etched away to expose the surface of the control electrode of the fourth transistor, and the ninth via hole V9 is configured to connect a subsequently formed first scanning signal line to the control electrode of the fourth transistor through the via hole.
  • the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second initial signal line INIT2 on the substrate, the tenth via V10 exposes the surface of the second initial signal line INIT2, and the tenth via V10 is configured to connect the first electrode of the subsequently formed seventh transistor to the second initial signal line INIT2 through the via.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second electrode plate of the first capacitor (also the second electrode plate of the second capacitor) on the substrate, and the eleventh via hole V11 exposes the surface of the second electrode plate of the first capacitor (also the second electrode plate of the second capacitor), and the eleventh via hole V11 is configured to connect the first electrode of the fifth transistor formed subsequently to the second electrode plate of the first capacitor (also the second electrode plate of the second capacitor) through the via hole.
  • a virtual straight line extending in the second direction may pass through the second via hole V2 and the eighth via hole V8 .
  • a virtual straight line extending in the second direction may pass through the fourth via hole V4 and the ninth via hole V9 .
  • a virtual straight line extending in the second direction passes through the fifth via hole V5 and the seventh via hole V7 .
  • a virtual straight line extending in the second direction passes through the sixth via hole V6 and the tenth via hole V10 .
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in FIGS. 15 and 16 , where FIG. 15 is a schematic diagram of a third conductive layer pattern of a display substrate provided in FIG. 7 , and FIG. 16 is a schematic diagram of a display substrate provided in FIG. 7 after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern of each sub-pixel may include at least a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 of a second transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a second electrode T64 of a sixth transistor, a first electrode T73 and a second electrode T74 of a seventh transistor, and a first scan signal line Gate1 and a second scan signal line Gate2.
  • the second electrode T14 of the first transistor can simultaneously serve as the first electrode T23 of the second transistor
  • the second electrode T64 of the sixth transistor can simultaneously serve as the second electrode T74 of the seventh transistor
  • the first electrode T13 of the first transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, and the first electrode T73 of the seventh transistor can be set separately.
  • the first electrode T13 of the first transistor, the first electrode T43 of the fourth transistor, and the first electrode T73 of the seventh transistor may be located on a side of the first scan signal line Gate1 away from the second scan signal line Gate2, and the first electrode T43 of the fourth transistor and the first electrode T73 of the seventh transistor are respectively located on both sides of the first electrode T13 of the first transistor.
  • the second electrode T14 of the first transistor (also the first electrode T23 of the second transistor), the first electrode T53 of the fifth transistor, and the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) may be located on a side of the second scan signal line Gate2 away from the first scan signal line Gate1.
  • the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) and the first electrode T53 of the fifth transistor are respectively located on both sides of the second electrode T14 of the first transistor (also the first electrode T23 of the second transistor).
  • the shape of the first electrode T13 of the first transistor may be a block structure, and the first electrode T13 of the first transistor.
  • the orthographic projection of the first electrode T13 of the first transistor on the substrate may overlap with the orthographic projection of the first via hole and the reset signal line RESET on the substrate.
  • the first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through the first via hole.
  • the shape of the second pole T14 of the first transistor may be a linear shape extending along the second direction Y.
  • the orthographic projection of the second pole T14 of the first transistor (also the first pole T23 of the second transistor) on the substrate may overlap with the orthographic projection of the second via, the eighth via, the first plate of the first capacitor, and the second plate of the first capacitor on the substrate.
  • the second pole T14 of the first transistor (also the first pole T23 of the second transistor) is connected to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) through the second via, and is connected to the first plate of the first capacitor through the eighth via.
  • the shape of the first electrode T43 of the fourth transistor may be a linear shape extending along the second direction Y.
  • the orthographic projection of the first electrode T43 of the fourth transistor on the substrate at least partially overlaps with the orthographic projection of the third via hole and the reset signal line Reset on the substrate.
  • the first electrode of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the third via hole.
  • the shape of the first electrode T53 of the fifth transistor may be a linear shape extending along the second direction Y.
  • the orthographic projection of the first electrode T53 of the fifth transistor on the substrate may at least partially overlap with the orthographic projection of the fourth via hole, the eleventh via hole, the light emitting signal line EM, and the second electrode plate of the first capacitor (also the second electrode plate of the second capacitor) on the substrate.
  • the first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the fourth via hole, and overlaps with the orthographic projection of the second electrode plate of the first capacitor (also the second electrode plate of the second capacitor) on the substrate through the eleventh via hole.
  • the second electrode T64 of the sixth transistor may be a block structure.
  • the orthographic projection of the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) on the substrate may overlap at least partially with the orthographic projection of the fifth via hole and the light emitting signal line EM on the substrate.
  • the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) is connected to the second region of the active layer of the sixth transistor (also the second region of the active layer of the seventh transistor) through the fifth via hole V5.
  • the first electrode T73 of the seventh transistor may be in a linear shape extending along the second direction Y.
  • the orthographic projection of the first electrode T73 of the seventh transistor on the substrate at least partially overlaps with the orthographic projections of the sixth via hole, the tenth via hole, the reset signal line Reset, and the second initial signal line INIT2 on the substrate.
  • the first electrode of the seventh transistor is connected to the first region of the active layer of the seventh transistor through the sixth via hole V6, and is connected to the second initial signal line INIT2 through the tenth via hole.
  • the shape of the first scan signal line Gate1 may be a line shape extending along the first direction X, and the first scan signal line Gate1 may be located on a side of the second scan signal line Gate2 close to the first electrode T13 of the first transistor.
  • the orthographic projection of the first scan signal line Gate1 on the substrate may at least partially overlap with the orthographic projection of the ninth via hole and the control electrode of the fourth transistor on the substrate.
  • the first scan signal line Gate1 is connected to the control electrode of the fourth transistor through the ninth via hole.
  • the shape of the second scan signal line Gate2 may be a line shape extending along the first direction X, and the second scan signal line Gate2 may be located on a side of the first scan signal line Gate1 close to the first electrode T53 of the fifth transistor.
  • the orthographic projection of the second scan signal line Gate2 on the substrate may at least partially overlap with the orthographic projection of the seventh via hole, the second electrode connection portion of the control electrode of the second transistor, and the capacitor body portion of the second electrode plate of the second capacitor on the substrate.
  • the second scan signal line Gate2 is connected to the control electrode of the second transistor through the seventh via hole.
  • the first scanning signal line Gate1 and the second scanning signal line Gate2 can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG. 17 , which is a schematic diagram of the display substrate provided in FIG. 7 after the fourth insulating layer pattern is formed.
  • the plurality of via holes of the fourth insulating layer of each sub-pixel may include at least a twelfth via hole V12 , a thirteenth via hole V13 , a fourteenth via hole V14 , and a fifteenth via hole V15 .
  • the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first electrode of the first transistor on the substrate, the twelfth via V12 exposes the surface of the first electrode of the first transistor, and the twelfth via V12 is configured to connect a subsequently formed first initial signal line to the first electrode of the first transistor through the via.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the thirteenth via hole V13 exposes the surface of the first electrode of the fourth transistor, and the thirteenth via hole V13 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via hole.
  • the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the fourteenth via V14 exposes the surface of the first electrode of the fifth transistor, and the fourteenth via V14 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor through the via.
  • the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the fifteenth via hole V15 exposes the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the fifteenth via hole V15 is configured to connect a subsequently formed connecting electrode to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the via hole.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern, as shown in FIGS. 18 and 19.
  • FIG. 18 is a schematic diagram of a fourth conductive layer pattern of the display substrate provided in FIG. 7, and
  • FIG. 19 is a schematic diagram of a display substrate provided in FIG. 7 after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern of each sub-pixel may include at least a first initial signal line INIT1 , a connection electrode VL, a first power line VDD, and a data signal line Data.
  • connection electrode VL may be located at a side of the first initial signal line INIT1 away from the first power line VDD located between the first initial signal line INIT1 and the data signal line Data.
  • the shape of the connection electrode VL may be a strip shape.
  • the orthographic projection of the connection electrode VL on the substrate overlaps the orthographic projection of the fifteenth via hole on the substrate.
  • the connection electrode VL is connected to the second region of the sixth active layer (also the second region of the seventh active layer) as the second pole of the sixth transistor T6 (also the second pole of the seventh transistor T7) through the fifteenth via hole.
  • the connection electrode VL is configured to be connected to an anode formed subsequently.
  • the shape of the first initial signal line INIT1 may be a line shape in which the main part extends along the second direction Y.
  • the orthographic projection of the first initial signal line INIT1 on the substrate overlaps at least partially with the orthographic projection of the second via, the eighth via, the twelfth via, and the second electrode of the first transistor (also the first electrode of the second transistor) on the substrate.
  • the first initial signal line INIT1 is connected to the first electrode of the first transistor through the twelfth via.
  • the orthographic projection of the first initial signal line on the substrate overlaps at least partially with the orthographic projection of the eighth via on the substrate, which can prevent other signals from interfering with the first node and effectively improve the stability of the first node.
  • the orthographic projection of the first initial signal line on the substrate overlaps partially with the orthographic projection of the twelfth via on the substrate, so that the active layer of the first transistor located between the control electrodes of the first transistor is shielded by the first initial signal line, which can effectively prevent leakage, thereby improving the reliability of the display substrate.
  • the first initial signal line is located in the fourth conductive layer, and the main body extends along the second direction. Since the signal of the first initial signal line is fed into the display area through the chip located in the binding area, the first initial signal line of the main body extending along the second direction is the shortest path in design.
  • the first initial signal line can be fed directly from below, which can be more conducive to accelerating the initialization of the first node.
  • the main body of the first power line VDD may be in the shape of a line extending along the second direction Y, and the orthographic projection of the first power line VDD on the substrate overlaps with the orthographic projection of the capacitor main body of the ninth via hole, the fourteenth via hole, the control electrode of the fourth transistor, the second electrode plate of the first capacitor, and the second electrode plate of the second capacitor on the substrate.
  • the first power line VDD is connected to the first electrode of the fifth transistor through the fourteenth via hole, so that the power signal is written into the first electrode of the fifth transistor, and the first electrode of the fifth transistor is connected to the second electrode plate of the first capacitor and the second electrode plate of the second capacitor, so that the first electrode of the fifth transistor, the second electrode plate of the first capacitor, and the second electrode plate of the second capacitor have the same potential.
  • the orthographic projection of the first power line VDD on the substrate is located between the orthographic projection of the eighth via on the substrate and the orthographic projection of the data signal line Data on the substrate, so that the first power line VDD shields the first node and the data signal line Data, effectively preventing the influence of the jump of the data signal line Data on the first node, thereby preventing the occurrence of signal crosstalk and improving the reliability of the display substrate.
  • the shape of the data signal line Data may be a line shape whose main body portion extends along the second direction Y, and the orthographic projection of the data signal line Data on the substrate at least partially overlaps with the thirteenth via hole, the capacitor main body portion of the second plate of the second capacitor, and the orthographic projection of the control electrode of the fourth transistor on the substrate.
  • the data signal line Data is connected to the first electrode of the fourth transistor through the thirteenth via hole.
  • the data signal line Data is located in the fourth conductive layer, which can reduce the parasitic capacitance between the data signal line Data and the conductive film layer thereunder, thereby reducing the load on the data signal line Data, which is beneficial to saving charging time and power consumption.
  • the first initial signal line INIT1, the data signal line Data, and the first power line VDD may be designed with equal widths, or may be designed with unequal widths, may be straight lines, or may be broken lines, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the width of the first power line VDD may be greater than the width of the data signal line Data, and greater than the width of the first initial signal line INIT1, and the width of the first initial signal line INIT1 may be greater than the width of the data signal line Data.
  • Forming a planar layer pattern may include coating a planar film on the substrate on which the aforementioned pattern is formed, and patterning the planar film using a patterning process to form a planar layer covering the fourth conductive layer pattern.
  • the drive circuit layer of the display substrate provided in FIG. 7 is prepared on the substrate.
  • the drive circuit layer may include a plurality of pixel circuits, and the drive circuit layer also includes: a first scanning signal line, a second scanning signal line, a light emitting signal line, a first initial signal line, a second initial signal line, a data signal line and a first power line connection.
  • the drive circuit layer may be disposed on the substrate, and the substrate may include a first flexible layer, a barrier layer, a substrate conductive layer and a second flexible layer stacked.
  • the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer and a flat layer arranged in sequence on the substrate.
  • the semiconductor layer may include at least an active layer of the first transistor to the seventh transistor and a first plate of the second capacitor
  • the first conductive layer may include at least a reset signal line, a light emitting signal line, a control electrode of the first transistor to the seventh transistor and a first plate of the first capacitor
  • the second conductive layer may include at least a second plate of the first capacitor, a second plate of the second capacitor and a second initial signal line
  • the third conductive layer may include at least a first scanning signal line and a second scanning signal line
  • the fourth conductive layer may include at least: a first initial signal line, a data signal line, a first power line and a connecting electrode.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer may be referred to as a buffer layer
  • the second insulating layer and the third insulating layer may be referred to as a gate insulating (GI) layer
  • the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer
  • the fifth insulating layer may be referred to as a passivation (PVX) layer.
  • the planar layer may be made of an organic material, such as a resin, etc.
  • the manufacturing process of the display substrate provided in FIG8 using a pixel circuit with one row and two columns may include:
  • forming a shielding layer pattern may include: sequentially depositing a shielding conductive film on the substrate, and patterning the shielding conductive film through a patterning process to form a shielding layer pattern, as shown in FIG. 20 , which is a schematic diagram of the display substrate provided in FIG. 8 after forming a shielding layer pattern.
  • the shielding layer pattern of each sub-pixel may include at least a first shielding structure 11, a second shielding structure 12, a first shielding connection structure 13, a second shielding connection structure 14, a third shielding connection structure 15, a fourth shielding connection structure 16, and a first plate C21 of a second capacitor.
  • the second shielding structure 12 is also the first plate C21 of the second capacitor.
  • the shielding layer is configured to transmit a high voltage power signal.
  • the first shielding connection structure 13 and the second shielding structure 12 are respectively located on two opposite sides of the first shielding structure 11, and are connected to the first shielding structure 11.
  • the second shielding connection structure 14 is located on a side of the second shielding structure 12 (also the first plate C21 of the second capacitor) away from the first shielding structure 11, and is connected to the second shielding structure 12 (also the first plate C21 of the second capacitor).
  • the third shielding connection structure 15 and the fourth shielding connection structure 16 are respectively located on the other two opposite sides of the first shielding structure 11, and the third shielding connection structure 15 is connected to the second shielding structure 12 (also the first plate C21 of the second capacitor), and the fourth shielding connection structure 16 is connected to the first shielding structure 11.
  • the second shielding structure 12 (also the first plate C21 of the second capacitor) of the Nth column sub-pixel in the same row is located on the side of the first shielding structure 11 of the sub-pixel close to the first shielding structure 11 of the N+1th column sub-pixel
  • the first shielding connection structure 13 of the Nth column sub-pixel in the same row is located on the side of the first shielding structure 11 of the sub-pixel close to the first shielding structure 11 of the N-1th column sub-pixel, and is connected to the fourth shielding connection structure 14 of the N-1th column sub-pixel.
  • the second shielding connection structure 14 of the Nth column sub-pixel in the same row is connected to the first shielding connection structure 13 of the N+1th column sub-pixel.
  • the third shielding connection structure 15 of the Mth row of sub-pixels located in the same column is located on a side of the first shielding structure 11 of the sub-pixel close to the first shielding structure 11 of the M-1th row of sub-pixels, and is connected to the fourth shielding connection structure 16 of the M-1th row of sub-pixels.
  • the fourth shielding connection structure 16 of the Mth row of sub-pixels located in the same column is located on a side of the first shielding structure 11 of the sub-pixel close to the first shielding structure 11 of the M+1th row of sub-pixels, and is connected to the fifth shielding connection structure 15 of the M+1th row of sub-pixels.
  • a virtual straight line extending along the second direction Y passes through the third shielding connection structure 15 and the fourth shielding connection structure 16 .
  • the shape of the first shielding structure 11 may be a rectangle, and the corners of the rectangle may be chamfered.
  • the shape of the second shielding structure 12 may be a line extending along the second direction Y.
  • the shape of the first shielding connection structure 13 and the shape of the second shielding connection structure 14 may be a line extending along the first direction X.
  • the shape of the main body of the third shielding connection structure 15 may be a broken line extending along the second direction Y.
  • the shape of the fourth shielding connection structure 16 may be a line extending along the second direction Y.
  • the length of the first shielding structure 11 along the first direction X is greater than the length of the second shielding structure 12 along the first direction X, and the length of the first shielding structure 11 along the second direction Y is less than the length of the second shielding structure 12 along the second direction Y.
  • the shapes of the shielding layers in the plurality of sub-pixels may be the same.
  • the shielding layers of all sub-pixels are connected as a whole and are in a mesh shape, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding layer pattern, and a semiconductor layer pattern located on the first insulating layer, as shown in FIGS. 21 and 22 , where FIG. 21 is a schematic diagram of a semiconductor layer pattern of the display substrate provided in FIG. 8 , and FIG. 22 is a schematic diagram of the display substrate provided in FIG. 8 after a semiconductor layer pattern is formed.
  • the semiconductor layer pattern of each sub-pixel may include at least an active layer T11 of a first transistor to an active layer T81 of an eighth transistor.
  • the active layer T11 of the first transistor to the active layer T81 of the eighth transistor are an integral structure connected to each other.
  • the active layer T21 of the second transistor and the active layer T61 of the sixth transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel
  • the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel
  • the active layer T21 of the second transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in the present subpixel.
  • the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor, and the active layer T81 of the eighth transistor may be located on the same side of the active layer T31 of the third transistor in the present subpixel, and the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor may be located on the other side of the active layer T31 of the third transistor in the present subpixel.
  • the active layer T11 of the first transistor may be shaped like a “T”
  • the active layer T21 of the second transistor may be shaped like a horizontally flipped “7”
  • the active layer T31 of the third transistor may be shaped like an “ ⁇ ”
  • the active layer T41 of the fourth transistor the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T81 of the eighth transistor may be shaped like an “I”
  • the active layer T71 of the seventh transistor may be shaped like a “ ⁇ ”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region T11_2 of the active layer T11 of the first transistor may serve as the first region T81_1 of the active layer T81 of the eighth transistor
  • the second region T81_2 of the active layer T81 of the eighth transistor may serve as the first region T21_1 of the active layer T21 of the second transistor
  • the first region T31_1 of the active layer T31 of the third transistor may serve as the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor
  • the second region T31_2 of the active layer T31 of the third transistor may serve as the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor.
  • the second region T61_2 of the active layer T61 of the sixth transistor can serve as the second region T71_2 of the active layer T71 of the seventh transistor, the first region T11_1 of the active layer T11 of the first transistor, the first region T41_1 of the active layer T41 of the fourth transistor, the first region T51_1 of the active layer T51_1 of the fifth transistor, and the first region T71_1 of the active layer T71 of the seventh transistor can be set separately.
  • the first region T11_1 of the active layer T11 of the first transistor includes a first connection portion T11_1A extending in a first direction X and a second connection portion T11_1B extending in a second direction Y.
  • the first regions T11_1 of the active layers T11 of the first transistors of adjacent sub-pixels in the same row are connected to each other.
  • the first connection portions T11_1A of the first regions T11_1 of the active layers T11 of the first transistors of adjacent sub-pixels in the same row are connected to each other.
  • the first region T71_1 of the active layer T71 of the seventh transistor includes a third connection portion T71_1A extending in the first direction X and a fourth connection portion T71_1B extending in the second direction Y.
  • the first regions T71_1 of the active layers T71 of the seventh transistors of adjacent sub-pixels in the same row are connected to each other.
  • the third connection portions T71_1A of the first regions T71_1 of the active layers T71 of the seventh transistors of adjacent sub-pixels in the same row are connected to each other.
  • the orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the channel region of the active layer T31 of the third transistor on the substrate
  • the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the first region T31_1 of the active layer T31 of the third transistor (the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor) on the substrate.
  • the orthographic projection of the third shielding connection structure on the substrate at least partially overlaps with the orthographic projection of the first region T11_1 of the active layer T11 of the first transistor on the substrate.
  • the orthographic projection of the fourth shielding connection structure on the substrate at least partially overlaps with the orthographic projection of the first region T71_1 of the active layer T71 of the seventh transistor on the substrate.
  • the orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the channel region of the active layer T31 of the third transistor on the substrate, which can improve the performance of the third transistor, namely the driving transistor, and thus improve the reliability of the display substrate.
  • forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern located on the second insulating layer, as shown in FIGS. 23 and 24, wherein FIG. 23 is a schematic diagram of the first conductive layer pattern of the display substrate provided in FIG. 8, and FIG. 24 is a schematic diagram of the display substrate provided in FIG. 8 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each sub-pixel may include at least: a light emitting signal line EM, control electrodes T12 to T82 of the first transistor, and a first plate C11 of the first capacitor.
  • the shape of the first electrode plate C11 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered, and the orthographic projection of the first electrode plate C11 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate.
  • the first electrode plate C11 of the first capacitor can also serve as the control electrode T32 of the third transistor T3.
  • the shape of the light emitting signal line EM can be a line shape extending along the first direction X, and the area where the light emitting signal line EM overlaps with the active layer of the fifth transistor T5 serves as the control electrode T52 of the fifth transistor T5, and the area where the light emitting signal line EM overlaps with the active layer of the sixth transistor T6 serves as the control electrode T62 of the sixth transistor T6.
  • the control electrode T12 of the first transistor T1, the control electrode T22 of the second transistor T2, the control electrode T42 of the fourth transistor T4, and the control electrode T82 of the eighth transistor T8 may be located on a side of the first plate C11 of the first capacitor away from the light emitting signal line EM
  • the control electrode T42 of the fourth transistor T4 and the control electrode T82 of the eighth transistor T8 are located on a side of the control electrode T22 of the second transistor T2 away from the first plate C11 of the first capacitor
  • the control electrode T12 of the first transistor T1 is located on a side of the control electrode T42 of the fourth transistor T4 and the control electrode T82 of the eighth transistor T8 away from the first plate C11 of the first capacitor.
  • the control electrode of the seventh transistor T72 is located on a side of the light emitting signal line EM away from the first plate C11 of the first capacitor.
  • the shapes of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor may be line shapes extending along the first direction X. As shown in FIGS. 23 and 24 , as shown in FIGS. 23 and 24 , the shapes of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor may be line shapes extending along the first direction X. As shown in FIGS. 23 and 24 , as shown in FIGS. 23 and 24 , the shapes of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor may be line shapes extending along the first direction X. As shown in FIGS.
  • control electrode T42 of the fourth transistor can also serve as the control electrode T82 of the eighth transistor.
  • the shape of the control electrode T42 of the fourth transistor (also the control electrode T82 of the eighth transistor) can be a line shape extending along the first direction X.
  • the control electrode T22 of the second transistor may include a first electrode connection portion T22A extending along a first direction X and a second electrode connection portion T22B extending along a second direction Y, and the orthographic projections of the first electrode connection portion T22A and the second electrode connection portion T22B on the substrate partially overlap with the orthographic projections of the active layer of the second transistor on the substrate, and therefore, there are two regions where the control electrode T22 of the second transistor overlaps with the active layer T21 of the second transistor, that is, there are two control electrodes T22 of the second transistor, and the second transistor has a dual-gate structure.
  • the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer, and the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the eighth transistor T8, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the active layer of the first transistor to the active layer of the eighth transistor are both conductorized.
  • the first region T11_1 of the conductive active layer T11 of the first transistor can be used as the first electrode T13 of the first transistor and the first initial signal line INIT1 at the same time.
  • the second region T11_2 of the conductive active layer T11 of the first transistor (also the first region T81_1 of the active layer T81 of the eighth transistor) can be used as the second electrode T14 of the first transistor and the first electrode T83 of the eighth transistor at the same time.
  • the first region T31_1 of the conductive active layer T31 of the third transistor (also the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor) can be used as the first electrode T33 of the third transistor, the second electrode T44 of the fourth transistor, The second electrode T54 of the fifth transistor and the second electrode plate C22 of the second capacitor, the second area T31_2 of the active layer T31 of the third transistor after conductorization (also the second area T21_2 of the active layer T21 of the second transistor and the first area T61_1 of the active layer T61 of the sixth transistor) also serve as the second electrode T24 of the second transistor, the second electrode T34 of the third transistor and the first electrode T63 of the sixth transistor at the same time, and the first area T71_1 of the active layer T71 of the seventh transistor after conductorization can serve as the first electrode T73 of the seventh transistor and the second initial signal line INIT2 at the same time.
  • the first initial signal line INIT1, the second initial signal line INIT2 and the light-emitting signal line EM can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • forming the second conductive layer pattern may include: depositing a third insulating layer film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the third insulating layer.
  • Figure 25 is a schematic diagram of the second conductive layer pattern of the display substrate provided in Figure 8
  • Figure 26 is a schematic diagram of the display substrate provided in Figure 8 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each sub-pixel includes at least: a second plate C12 of the first capacitor, a third plate C23 of the second capacitor, and a shielding electrode 21 .
  • the second plate C12 of the first capacitor and the third plate C23 of the second capacitor are connected to each other, and the shielding electrode 21 is provided separately.
  • the third electrode plate C23 of the second capacitor of the sub-pixel in the Nth column is located near the second electrode plate C12 of the first capacitor of the sub-pixel in the Nth column and close to the second electrode plate C12 of the first capacitor of the sub-pixel in the Nth column, and is connected to the second electrode plate C12 of the first capacitor of the sub-pixel in the Nth column.
  • connection between the third electrode plate C23 of the second capacitor of the sub-pixel in the Nth column and the second electrode plate C12 of the first capacitor of the sub-pixel in the Nth column can make the second electrode plate C12 of the first capacitor and the third electrode plate C23 of the second capacitor of adjacent sub-pixels arranged along the first direction X flow through the same signal, which can improve the uniformity of display of the display substrate.
  • the second capacitor includes: a first plate located at the shielding layer, a second plate located at the semiconductor layer, and a third plate located at the second conductive layer, wherein both the first plate and the third plate transmit a high voltage power signal.
  • the present disclosure can make the second capacitor store more charge by setting the second capacitor to include: a first plate located at the shielding layer, a second plate located at the semiconductor layer, and a third plate located at the second conductive layer, thereby improving the charging performance of the second capacitor, prolonging the charging time of the first node in the pixel circuit, improving the performance of the display substrate, and facilitating the realization of a high refresh rate.
  • the second electrode plate C12 of the first capacitor may include: a capacitor main body C12A and a connecting portion C12B connected to each other.
  • the connecting portion C12B and the third electrode plate C23 of the second capacitor are respectively located on two opposite sides of the capacitor main body C12A and are respectively connected to the capacitor main body C12A.
  • the connecting portion C12B of the N+1th column sub-pixel is connected to the third electrode plate C23 of the second capacitor of the Nth column sub-pixel.
  • the shape of the capacitor body C12A may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the capacitor body C12A on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate.
  • An opening V0 is provided on the capacitor body C12A, and the shape of the opening V0 may be rectangular, and may be located in the middle of the capacitor body C12A, so that the capacitor body C12A forms a ring structure.
  • the opening V0 exposes the third insulating layer covering the first electrode plate of the first capacitor, and the orthographic projection of the first electrode plate of the first capacitor on the substrate includes the orthographic projection of the opening V0 on the substrate.
  • the shape of the connection portion C12B may be a line shape extending in the first direction X. As shown in FIGS. 25 and 26 , as shown in FIGS. 25 and 26 , the shape of the connection portion C12B may be a line shape extending in the first direction X. As shown in FIGS. 25 and 26 , the shape of the connection portion C12B may be a line shape extending in the first direction X. As shown in FIGS. 25 and 26 , the shape of the connection portion C12B may be a line shape extending in the first direction X.
  • the shape of the third plate C23 of the second capacitor may be a zigzag shape extending along the second direction X.
  • the orthographic projection of the third plate C23 of the second capacitor on the substrate at least partially overlaps the orthographic projection of the second plate of the second capacitor on the substrate.
  • the length of the second plate C12 of the first capacitor along the second direction Y is smaller than the length of the third plate C23 of the second capacitor along the second direction Y.
  • the shielding electrode 21 of the sub-pixel in the M+1th row is located on a side where the second plate C12 of the first capacitor of the sub-pixel in the M+1th row is close to the second plate C12 of the first capacitor of the sub-pixel in the Mth row.
  • the shielding electrode 21 of the sub-pixel in the N+1th column is electrically connected to the third plate C23 of the second capacitor of the sub-pixel in the Nth column.
  • the shielding electrode 21 may be in a block shape.
  • the orthographic projection of the shielding electrode 21 on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor on the substrate.
  • the orthographic projection of the shielding electrode 21 on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor located between the control electrodes of the second transistor on the substrate, so that the active layer of the second transistor located between the control electrodes of the second transistor is shielded by the shielding electrode, which can effectively prevent leakage, thereby improving the reliability of the display substrate.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are disposed on the fourth insulating layer, as shown in FIG. 27 , which is a schematic diagram of the display substrate provided in FIG. 8 after the fourth insulating layer pattern is formed.
  • the multiple via holes of the fourth insulating layer of each sub-pixel may include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8 and a ninth via hole V9.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first area of the active layer T21 of the second transistor (also the second area of the active layer of the eighth transistor) on the substrate, the second insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first area of the active layer of the second transistor (also the second area of the active layer of the eighth transistor), and the first via hole V1 is configured to connect the first electrode of the subsequently formed second transistor (also the second electrode of the eighth transistor) to the first area of the active layer of the second transistor (also the second area of the active layer of the eighth transistor) through the via hole.
  • the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor on the substrate, the second insulating layer and the third insulating layer in the second via V2 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the second via V2 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active layer of the fourth transistor through the via.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth transistor on the substrate, the second insulating layer and the third insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the active layer of the fifth transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of the active layer of the fifth transistor through the via hole.
  • the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the sixth transistor (also the second area of the active layer of the seventh transistor) on the substrate, the second insulating layer and the third insulating layer in the fourth via V4 are etched away to expose the surface of the second area of the active layer of the sixth transistor (also the second area of the active layer of the seventh transistor), and the fifth via V5 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second area of the active layer of the sixth transistor (also the second area of the active layer of the seventh transistor) through the via.
  • the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor on the substrate, the third insulating layer in the fifth via V5 is etched away to expose the surface of the control electrode of the first transistor, and the fifth via V5 is configured to connect one of the reset signal lines formed subsequently to the control electrode of the first transistor through the via.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the control electrode of the second transistor on the substrate, the third insulating layer in the sixth via hole V6 is etched away to expose the surface of the control electrode of the second transistor, and the sixth via hole V6 is configured to connect a subsequently formed first scanning signal line to the control electrode of the second transistor through the via hole.
  • the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the opening on the substrate, the third insulating layer in the seventh via V7 is etched away to expose the surface of the first electrode plate of the first capacitor (also the control electrode of the third transistor), and the seventh via V7 is configured to connect the first electrode of the subsequently formed second transistor (also the second electrode of the eighth transistor) to the first electrode plate of the first capacitor (also the control electrode of the third transistor) through the via.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the control electrode of the fourth transistor (also the control electrode of the eighth transistor) on the substrate, the third insulating layer in the eighth via V8 is etched away to expose the surface of the control electrode of the fourth transistor (also the control electrode of the eighth transistor), and the eighth via V8 is configured to connect a subsequently formed second scanning signal line to the control electrode of the fourth transistor (also the control electrode of the eighth transistor) through the via.
  • the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the control electrode of the seventh transistor on the substrate, the third insulating layer in the ninth via V9 is etched away to expose the surface of the control electrode of the seventh transistor, and the ninth via V9 is configured to connect another reset signal line formed subsequently to the control electrode of the seventh transistor through the via.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 28 and 29 , where FIG. 28 is a schematic diagram of a third conductive layer pattern of the display substrate provided in FIG. 8 , and FIG. 29 is a schematic diagram of a display substrate provided in FIG. 8 after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern of each sub-pixel may include at least two reset signal lines Reset, a first scan signal line Gate1 and a second scan signal line Gate2, a first electrode T23 of a second transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a second electrode T64 of a sixth transistor, a second electrode T74 of a seventh transistor, and a second electrode T84 of an eighth transistor.
  • the first electrode T23 of the second transistor may also serve as the second electrode T84 of the eighth transistor
  • the second electrode T64 of the sixth transistor may also serve as the second electrode T74 of the seventh transistor
  • the first electrode T43 of the fourth transistor and the first electrode T53 of the fifth transistor may be provided separately.
  • the first electrode T43 of the fourth transistor may be located between one of the reset signal lines Reset and the first scan signal line Gate1.
  • the first electrode T23 of the second transistor (also the second electrode T84 of the eighth transistor), the first electrode T53 of the fifth transistor, and the second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) may be located between the second scan signal line Gate2 and another reset signal line Reset, wherein the first electrode T23 of the second transistor (also the second electrode T84 of the eighth transistor) may be located on a side of the first electrode T53 of the fifth transistor close to the second scan signal line Gate2, and the second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) may be located on a side of the first electrode T53 of the fifth transistor away from the second scan signal line Gate2.
  • the first scan signal line Gate1 and the second scan signal line Gate2 are located between the two reset signal lines Reset, and the first scan signal line Gate1 is located on a side
  • the reset signal line Reset near the first scan signal line Gate1 may include: a signal main body portion 22 extending along a first direction X and a signal connection block 23 extending along a second direction Y.
  • the signal connection block 23 is located on a side of the signal main body portion 22 near the first scan signal line Gate1.
  • the orthographic projection of the signal connection block 23 on the substrate partially overlaps with the orthographic projection of the fifth via on the substrate.
  • the reset signal line Reset near the first scan signal line is connected to the control electrode of the first transistor through the fifth via.
  • the shape of the reset signal line Reset near the second scan signal line Gate2 may be a line shape extending along the first direction X.
  • the orthographic projection of the reset signal line Reset near the second scan signal line Gate2 on the substrate partially overlaps with the orthographic projection of the ninth via hole on the substrate.
  • the reset signal line Reset near the second scan signal line Gate2 is connected to the control electrode of the seventh transistor through the ninth via hole.
  • the shape of the main portion of the first scan signal line Gate1 may be a line shape extending along the first direction X.
  • the orthographic projection of the first scan signal line Gate1 on the substrate partially overlaps the orthographic projection of the eighth via hole on the substrate.
  • the first scan signal line Gate1 is connected to the control electrode of the fourth transistor (also the control electrode of the eighth transistor) through the eighth via hole.
  • the shape of the main portion of the second scan signal line Gate2 may be a line shape extending along the first direction X.
  • the orthographic projection of the second scan signal line Gate2 on the substrate partially overlaps the orthographic projection of the sixth via hole on the substrate.
  • the second scan signal line Gate2 is connected to the control electrode of the second transistor through the sixth via hole.
  • the shape of the first electrode T23 of the second transistor may be a line shape extending along the second direction Y.
  • the orthographic projection of the first electrode T23 of the second transistor (also the second electrode T84 of the eighth transistor) on the substrate overlaps at least partially with the orthographic projections of the first via hole and the seventh via hole on the substrate.
  • the first electrode T23 of the second transistor (also the second electrode T84 of the eighth transistor) is connected to the first region of the active layer of the second transistor (also the second region of the active layer of the eighth transistor) through the first via hole, and is connected to the first plate of the first capacitor (also the control electrode of the third transistor) through the seventh via hole.
  • the shape of the first electrode T43 of the fourth transistor can be block-shaped.
  • the orthographic projection of the first electrode T43 of the fourth transistor on the substrate overlaps at least partially with the orthographic projection of the second via hole on the substrate.
  • the first electrode of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the second via hole.
  • the shape of the first electrode T53 of the fifth transistor may be a “T-shaped” with an irregular boundary.
  • the orthographic projection of the first electrode T53 of the fifth transistor on the substrate may overlap with the orthographic projection of the third via hole, the light emitting signal line, the second electrode plate of the first capacitor, and the third electrode plate of the second capacitor on the substrate.
  • the first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the third via hole.
  • the first electrodes T53 of the fifth transistors of adjacent sub-pixels located in the same row are connected to each other.
  • the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) can be a block structure.
  • the orthographic projection of the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) on the substrate can overlap with the orthographic projection of the fourth via hole and the light-emitting signal line on the substrate.
  • the second electrode T64 of the sixth transistor (the second electrode T74 of the seventh transistor) is connected to the second area of the active layer of the sixth transistor (also the second area of the active layer of the seventh transistor) through the fourth via hole.
  • the two reset signal lines Reset, the first scanning signal line Gate1, and the second scanning signal line Gate2 can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • Forming a fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, as shown in FIG. 30 , which is a schematic diagram of the display substrate provided in FIG. 8 after the fifth insulating layer pattern is formed.
  • the plurality of via holes of the fifth insulating layer of each sub-pixel includes at least a tenth via hole V10 , an eleventh via hole V11 , and a twelfth via hole V12 .
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the tenth via hole V10 exposes the surface of the first electrode of the fourth transistor, and the tenth via hole V10 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via hole.
  • the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the fourteenth via V14 exposes the surface of the first electrode of the fifth transistor, and the eleventh via V11 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor through the via.
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the third electrode plate of the second capacitor on the substrate, and the third insulating layer and the fourth insulating layer in the twelfth via hole V12 are etched away to expose the surface of the third electrode plate of the second capacitor.
  • the twelfth via hole V12 is configured to connect the first power line formed subsequently to the third electrode plate of the second capacitor through the via hole.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern, as shown in FIGS. 31 and 32 , where FIG. 31 is a schematic diagram of a fourth conductive layer pattern of the display substrate provided in FIG. 8 , and FIG. 32 is a schematic diagram of a display substrate provided in FIG. 8 after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern of each sub-pixel may include at least a first power line VDD and a data signal line Data.
  • the main body of the first power line VDD may be in the shape of a line extending along the second direction Y, and the orthographic projection of the first power line VDD on the substrate overlaps with the orthographic projections of the eleventh via and the twelfth via on the substrate.
  • the first power line VDD is connected to the first electrode of the fifth transistor through the eleventh via, and is connected to the third electrode plate of the second capacitor through the twelfth via, so that the power signal is written into the first electrode of the fifth transistor and the third electrode plate of the second capacitor.
  • the signals transmitted by the first electrode of the fifth transistor, the second electrode plate of the first capacitor and the third electrode plate of the second capacitor are all high-voltage power signals, having the same potential.
  • the shape of the data signal line Data may be a line shape in which the main part extends along the second direction Y, and the orthographic projection of the data signal line Data on the substrate at least partially overlaps with the orthographic projection of the capacitor main part of the third plate of the second capacitor on the substrate of the tenth via hole.
  • the data signal line Data is connected to the first electrode of the fourth transistor through the tenth via hole.
  • the data signal line Data is located in the fourth conductive layer, which can reduce the parasitic capacitance between the data signal line Data and the conductive film layer below it, thereby reducing the load on the data signal line Data, which is conducive to saving charging time and power consumption.
  • the data signal line Data and the first power line VDD may be designed with equal widths, or may be designed with unequal widths, may be straight lines, or may be broken lines, which may not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the width of the first power line VDD may be greater than the width of the data signal line Data.
  • Forming a planar layer pattern may include coating a planar film on the substrate on which the aforementioned pattern is formed, and patterning the planar film using a patterning process to form a planar layer covering the fourth conductive layer pattern.
  • the drive circuit layer of the display substrate provided in FIG. 8 is prepared on the substrate.
  • the drive circuit layer may include a plurality of pixel circuits, and the drive circuit layer also includes: a first scanning signal line, a second scanning signal line, a light emitting signal line, a first initial signal line, a second initial signal line, a data signal line, and a first power line connection.
  • the drive circuit layer may be disposed on the substrate, and the substrate may include a first flexible layer, a barrier layer, a substrate conductive layer, and a second flexible layer stacked.
  • the driving circuit layer may include a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer and a flat layer sequentially arranged on the substrate.
  • the shielding layer may include: a first plate of the second capacitor, the semiconductor layer may include at least an active layer of the first transistor to the eighth transistor, a second plate of the second capacitor, a first initial signal line and a second initial signal line, the first conductive layer may include at least a light-emitting signal line, a control electrode of the first transistor to the seventh transistor and a first plate of the first capacitor, the second conductive layer may include at least a second plate of the first capacitor and a third plate of the second capacitor, the third conductive layer may include at least a first scanning signal line, a second scanning signal line and a reset signal line, and the fourth conductive layer may include at least a data signal line and a first power supply line.
  • the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer may be called a buffer layer
  • the second insulating layer and the third insulating layer may be called a gate insulating (GI) layer
  • the fourth insulating layer may be called an interlayer insulating (ILD) layer
  • the fifth insulating layer may be called a passivation (PVX) layer.
  • the planar layer may be made of
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns.
  • the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • Forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer, wherein a pixel opening is provided on the pixel definition layer of each sub-pixel, and the pixel definition film in the pixel opening is removed to expose the anode of the sub-pixel.
  • the subsequent preparation process may include: first forming an organic light-emitting layer by an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.
  • the embodiment of the present disclosure further provides a method for driving a pixel circuit.
  • the pixel circuit is set to be driven.
  • the method for driving a pixel circuit provided by the embodiment of the present disclosure may include the following steps:
  • Step 100 under the control of the reset signal line, the first scan signal line and the second scan signal line, the node control subcircuit provides the signal of the first initial signal line or the third node to the first node, provides the signal of the second initial signal line to the fourth node, and provides the signal of the data signal line to the second node.
  • Step 200 The storage sub-circuit charges the second node when the first scan signal line is a valid level signal.
  • Step 300 under the control of the first node and the second node of the driving subcircuit, a driving current is provided to the third node, and under the control of the light-emitting signal line, the light-emitting control subcircuit provides the signal of the first power line to the second node and provides the signal of the third node to the fourth node.
  • the embodiment of the present disclosure further provides a display device, including: a display substrate.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • AMOLED active-matrix organic light emitting diode
  • the display device further includes: a gate driving circuit.
  • the gate driving circuit includes: K+2 cascaded shift registers GOA, where K is the total number of rows of pixel circuits.
  • the gate driving circuit may be located in a non-display area of the display device.
  • FIG33 is a connection diagram of a gate driving circuit.
  • the first-stage shift register GOA (1) is connected to the reset signal line Reset connected to the first row of pixel circuits R (1)
  • the second-stage shift register GOA (2) is respectively connected to the first scanning signal line Gate1 connected to the first row of pixel circuits R (1) and the reset signal line Reset connected to the second row of pixel circuits R (2)
  • the i-th stage shift register GOA (i) is respectively connected to the second scanning signal line Gate2 connected to the i-2th row of pixel circuits R (i-2), the i-1th row of pixel circuits R (i-1) and the reset signal line Gate2 connected to the second row of pixel circuits R (i-1).
  • the first scanning signal line Gate1 connected to the pixel circuit R(i) in the i-th row is connected to the reset signal line Reset connected to the pixel circuit R(i) in the i-th row
  • the shift register GOA(K+1) in the K+1th row is connected to the second scanning signal line Gate2 connected to the pixel circuit R(K-1) in the K-th row and the first scanning signal line Gate1 connected to the pixel circuit R(K) in the K-th row
  • FIG. 33 shows only 7 cascaded shift registers, which does not mean that the gate driving circuit only includes 7 cascaded shift registers.
  • the present disclosure connects the reset signal line, the first scanning signal line and the second scanning signal line through the gate driving circuit, so as to reduce the area occupied by the circuit located in the non-display area and realize a narrow frame.
  • the present disclosure uses the pixel circuit, the structure of the display substrate and the driving mode of the gate driving circuit, and combines the above pixel circuit and pixel layout design with the driving mode of GOA to effectively realize high-frequency or even ultra-high-frequency display.
  • the thickness and size of the layer or microstructure are exaggerated. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种像素电路及其驱动方法、显示基板和显示装置，其中，像素电路包括：节点控制子电路，存储子电路、驱动子电路和发光控制子电路；存储子电路，分别与第二节点(N2)和第一电源线(VDD)电连接，被配置为在第一扫描信号线(Gate1)为有效电平信号时，对第二节点(N2)进行充电。

Description

像素电路及其驱动方法、显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种像素电路及其驱动方法、显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种像素电路，被配置为驱动发光器件发光，包括：节点控制子电路，存储子电路、驱动子电路和发光控制子电路；
节点控制子电路，分别与第一节点、第二节点、第三节点、第四节点、第一扫描信号线、第二扫描信号线、第一初始信号线、第二初始信号线、复位信号线、数据信号线和第一电源线电连接，被配置为在复位信号线、第一扫描信号线和第二扫描信号线的控制下，向第一节点提供第一初始信号线或者第三节点的信号，向第四节点提供第二初始信号线的信号，向第二节点提供数据信号线的信号；
存储子电路，分别与第二节点和第一电源线电连接，被配置为在第一扫描信号线为有效电平信号时，对第二节点进行充电
驱动子电路，分别与第一节点、第二节点和第三节点电连接，被配置为 第一节点和第二节点的控制下，向第三节点提供驱动电流；
发光控制子电路，分别与发光信号线、第一电源线、第二节点、第三节点和第四节点电连接，被配置为在发光信号线的控制下，向第二节点提供第一电源线的信号，并向第四节点提供第三节点的信号；
发光器件的第一极与第四节点连接，发光器件的第二极与第二电源线连接。
在示例性实施方式中，复位信号线的信号为有效电平信号的时间段包括第一时间段和第二时间段，第一时间段发生在第二时间段之前；第一扫描信号线的信号为有效电平信号的时间段包括第三时间段和第四时间段，第三时间段发生在第四时间段之前；第二扫描信号线的信号为有效电平信号的时间段包括第五时间段和第六时间段，第五时间段发生在第六时间段之前，所述第二时间段和所述第三时间段至少部分交叠，所述第四时间段和所述第五时间段至少部分交叠；
复位信号线、第一扫描信号线和第二扫描信号线的信号为有效电平信号时，发光信号线的信号为无效电平信号，发光信号线的信号为有效电平信号时，复位信号线、第一扫描信号线和第二扫描信号线的信号为无效电平信号。
在示例性实施方式中，所述节点控制子电路包括：复位子电路、写入子电路和补偿子电路；
所述复位子电路，分别与复位信号线、第一初始信号线、第二初始信号线、第一节点和第四节点电连接，被配置为在复位信号线的控制下，向第一节点提供第一初始信号线的信号，向第四节点提供第二初始信号线的信号；
所述写入子电路，分别与第一扫描信号线、数据信号线和第二节点电连接，被配置为在第一扫描信号线的控制下，向第二节点提供数据信号线的信号；
所述补偿子电路，分别与第二扫描信号线、第一节点和第三节点电连接，被配置为在第二扫描信号线的控制下，向第一节点提供第三节点的信号；
所述储能子电路，分别与第一节点和第一电源线电连接，且被配置为存储第一节点和第一电源线之间的信号的电压差。
在示例性实施方式中，所述复位子电路还与第一扫描信号线连接，被配置为在复位信号线和第一扫描信号线的控制下，向第一节点提供第一初始信号线的信号，向第四节点提供第二初始信号线的信号。
在示例性实施方式中，所述复位子电路包括第一晶体管和第七晶体管，所述写入子电路包括第四晶体管，所述补偿子电路包括：第二晶体管，所述储能子电路包括：第一电容；
第一晶体管的控制极与复位信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第二扫描信号线电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第三节点电连接；
第四晶体管的控制极与第一扫描信号线电连接，第四晶体管的第一极与数据信号线电连接，第四晶体管的第二极与第二节点电连接；
第七晶体管的控制极与复位信号线电连接，第七晶体管的第一极与第二初始信号线电连接，第七晶体管的第二极与第四节点电连接；
第一电容的一端与第一电源线电连接，第一电容的另一端与第一节点电连接。
在示例性实施方式中，所述复位子电路包括第一晶体管、第七晶体管和第八晶体管，所述写入子电路包括第四晶体管，所述补偿子电路包括：第二晶体管，所述储能子电路包括：第一电容；
第一晶体管的控制极与复位信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第八晶体管的第一极电连接；
第二晶体管的控制极与第二扫描信号线电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第三节点电连接；
第四晶体管的控制极与第一扫描信号线电连接，第四晶体管的第一极与数据信号线电连接，第四晶体管的第二极与第二节点电连接；
第七晶体管的控制极与复位信号线电连接，第七晶体管的第一极与第二初始信号线电连接，第七晶体管的第二极与第四节点电连接；
第八晶体管的控制极与第一扫描信号线电连接，第八晶体管的第二极与 第一节点电连接；
第一电容的一端与第一节点电连接，第一电容的另一端与第一电源线电连接。
在示例性实施方式中，所述存储子电路包括：第二电容；
第二电容的一端与第一电源线电连接，第二电容的另一端与第二节点电连接。
在示例性实施方式中，所述节点控制子电路包括：第一晶体管、第二晶体管、第四晶体管、第七晶体管和第一电容，所述存储子电路包括：第二电容；所述驱动子电路包括第三晶体管，所述发光控制子电路包括：第五晶体管和第六晶体管；
第一晶体管的控制极与复位信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第二扫描信号线电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第三节点电连接；
第三晶体管的控制极与第一节电连接，第三晶体管的第一极与第二节点电连接，第三晶体管的第二极与第三节点电连接；
第四晶体管的控制极与第一扫描信号线电连接，第四晶体管的第一极与数据信号线电连接，第四晶体管的第二极与第二节点电连接；
第五晶体管的控制极与发光信号线电连接，第五晶体管的第一极与第一电源线电连接，第五晶体管的第二极与第二节点电连接；
第六晶体管的控制极与发光信号线电连接，第六晶体管的第一极与第三节点电连接，第六晶体管的第二极与第四节点电连接；
第七晶体管的控制极与复位信号线电连接，第七晶体管的第一极与第二初始信号线电连接，第七晶体管的第二极与第四节点电连接；
第一电容的一端与第一电源线电连接，第一电容的另一端与第一节点电连接；
第二电容的一端与第一电源线电连接，第二电容的另一端与第二节点电 连接。
在示例性实施方式中，所述节点控制子电路包括：第一晶体管、第二晶体管、第四晶体管、第七晶体管、第八晶体管和第一电容；所述存储子电路包括：第二电容；所述驱动子电路包括第三晶体管，所述发光控制子电路包括：第五晶体管和第六晶体管；
第一晶体管的控制极与复位信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第八晶体管的第一极电连接；
第二晶体管的控制极与第二扫描信号线电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第三节点电连接；
第三晶体管的控制极与第一节电连接，第三晶体管的第一极与第二节点电连接，第三晶体管的第二极与第三节点电连接；
第四晶体管的控制极与第一扫描信号线电连接，第四晶体管的第一极与数据信号线电连接，第四晶体管的第二极与第二节点电连接；
第五晶体管的控制极与发光信号线电连接，第五晶体管的第一极与第一电源线电连接，第五晶体管的第二极与第二节点电连接；
第六晶体管的控制极与发光信号线电连接，第六晶体管的第一极与第三节点电连接，第六晶体管的第二极与第四节点电连接；
第七晶体管的控制极与复位信号线电连接，第七晶体管的第一极与第二初始信号线电连接，第七晶体管的第二极与第四节点电连接；
第八晶体管的控制极与第一扫描信号线电连接，第八晶体管的第二极与第一节点电连接；
第一电容的一端与第一电源线电连接，第一电容的另一端与第一节点电连接；
第二电容的一端与第一电源线电连接，第二电容的另一端与第二节点电连接。
第二方面，本公开还提供了一种显示基板，包括：基底以及依次设置在基底上的驱动电路层和发光结构层，所述驱动电路层包括上述像素电路、多条第一初始信号线、多条第二初始信号线、多条第一扫描信号线、多条第二 扫描信号线、多条复位信号线、多条第一电源线和多条数据信号线，所述发光结构层包括：发光器件。
在示例性实施方式中，所述驱动电路层包括：依次叠设在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层和第四导电层，所述像素电路包括：多个晶体管、第一电容和第二电容，第一电容和第二电容包括：第一极板和第二极板；
半导体层至少包括：多个晶体管的有源层和第二电容的第一极板；
第一导电层至少包括：复位信号线、发光信号线、多个晶体管的控制极、第一电容的第一极板；
第二导电层至少包括：第二初始信号线、第一电容的第二极板和第二电容的第二极板；
第三导电层至少包括：第一扫描信号线和第二扫描信号线；
第四导电层至少包括：第一初始信号线、第一电源线和数据信号线。
在示例性实施方式中，所述像素电路包括第一晶体管至第七晶体管，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区；
第三晶体管的有源层的第一区沿第一方向的长度大于第三晶体管的有源层的第二区沿第一方向的长度，所述第三晶体管的有源层的第一区复用为第二电容的第一极板。
在示例性实施方式中，对于同一像素电路，第一电容的第二极板与第二电容的第二极板连接，位于同一行的第N列像素电路的第二电容的第二极板与第N+1列像素电路的第一电容的第二极板连接；
第一电容的第二极板沿第二方向的长度小于第二电容的第二极板沿第二方向的长度，所述第一方向和所述第二方向相交。
在示例性实施方式中，第二电容的第二极板包括：沿第二方向延伸的电容主体部以及沿第一方向延伸的第一连接块和第二连接块；第一连接块和第二连接块分别与电容主体部连接，第一连接块和第二连接块平行设置，且位于电容主体部远离第一电容的第二极板的一侧；
电容主体部在基底上的正投影与第二电容的第一极板在基底上的正投影至少部分交叠，第一连接块在基底上的正投影与位于第二晶体管的控制极之间的第二晶体管的有源层在基底上的正投影部分交叠，第二连接块在基底上的正投影与第三晶体管的有源层在基底上的正投影部分交叠；
对于同一像素电路，第一电容的第二极板与电容主体部连接，位于同一行的第N列像素电路的第二连接块与第N+1列像素电路的第一电容的第二极板连接。
在示例性实施方式中，第一电源线沿第一方向的长度大于数据信号线沿第一方向的长度，且大于第一初始信号线沿第一方向的长度，第一初始信号线沿第一方向的长度大于数据信号线沿第一方向的长度。
在示例性实施方式中，所述驱动电路层包括：遮挡层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层和第四导电层，所述像素电路包括：多个晶体管、第一电容和第二电容，第一电容包括：第一极板和第二极板，第二电容包括：第一极板、第二极板和第三极板；
遮挡层至少包括：第二电容的第一极板，所述遮挡层被配置为传输高压电源信号；
半导体层至少包括：多个晶体管的有源层、第二电容的第二极板、第一初始信号线和第二初始信号线；
第一导电层至少包括：发光信号线、多个晶体管的控制极和第一电容的第一极板；
第二导电层至少包括：第一电容的第二极板和第二电容的第三极板；
第三导电层至少包括：两条复位信号线、第一扫描信号线和第二扫描信号线；
第四导电层可以包括：第一电源线和数据信号线。
在示例性实施方式中，多个晶体管包括：第一晶体管至第八晶体管，所述遮挡层还包括：第一遮挡结构、第二遮挡结构、第一遮挡连接结构、第二遮挡连接结构、第三遮挡连接结构和第四遮挡连接结构，第二电容的第一极 板复用为第二遮挡结构；
第一遮挡连接结构和第二遮挡结构分别位于第一遮挡结构相对设置的两侧，且与第一遮挡结构连接，第二遮挡连接结构位于第二遮挡结构远离第一遮挡结构的一侧，且与第二遮挡结构连接。第三遮挡连接结构和第四遮挡连接结构分别位于第一遮挡结构相对设置的另外两侧，且第三遮挡连接结构与第二遮挡结构连接，第四遮挡连接结构与第一遮挡结构连接；
第一遮挡结构在基底上的正投影与第三晶体管的有源层的沟道区在基底上的正投影至少部分交叠，第二遮挡结构在基底上的正投影与第二电容的第二极板在基底上的正投影至少部分交叠，第三遮挡连接结构在基底上的正投影与第一晶体管的有源层在基底上的正投影至少部分交叠，第四遮挡连接结构在基底上的正投影与第七晶体管的有源层基底上的正投影至少部分交叠。
在示例性实施方式中，位于同一行的第N列子像素的第二遮挡结构位于第N列子像素的第一遮挡结构靠近第N+1列子像素的第一遮挡结构的一侧，位于同一行的第N列子像素的第一遮挡连接结构位于第N列子像素的第一遮挡结构靠近第N-1列子像素的第一遮挡结构的一侧，且与第N-1列子像素的第四遮挡连接结构连接。位于同一行的第N列子像素的第二遮挡连接结构与第N+1列子像素的第一遮挡连接结构连接；位于同一列的第M行子像素的第三遮挡连接结构位于第M行子像素的第一遮挡结构11靠近第M-1行子像素的第一遮挡结构的一侧，且与第M-1行子像素的第四遮挡连接结构连接。位于同一列的第M行子像素的第四遮挡连接结构位于第M行子像素的第一遮挡结构靠近第M+1行子像素的第一遮挡结构的一侧，且与第M+1行子像素的第五遮挡连接结构连接。
在示例性实施方式中，对于同一子像素，第一电容的第二极板和第二电容的第三极板相互连接；
对于同一行的子像素，第N列子像素的第二电容的第三极板位于第N列子像素的第一电容的第二极板靠近第N+1列子像素的第一电容的第二极板，且与第N+1列子像素的第一电容的第二极板连接；
第一电容的第二极板沿第二方向的长度小于第二电容的第三极板沿第二方向的长度。
第四方面，本公开还提供了一种显示装置，包括：上述显示基板。
在示例性实施方式中，还包括：栅极驱动电路，栅极驱动电路包括：K+2个级联的移位寄存器，K为像素电路的总行数；
第一级移位寄存器与第一行像素电路所连接的复位信号线连接，第二级移位寄存器分别与第一行像素电路所连接的第一扫描信号线和第二行像素电路所连接的复位信号线连接，第i级移位寄存器分别与第i-2行像素电路所连接的第二扫描信号线、第i-1行像素电路所连接的第一扫描信号线和第i行像素电路所连接的复位信号线连接，第K+1级移位寄存器分别与第K-1行像素电路所连接的第二扫描信号线和第K行像素电路所连接的第一扫描信号线连接，第K+2级移位寄存器分别与第K行像素电路的所连接的第二扫描信号线连接，i＝3,4,…,K。
第四方面，本公开还提供了一种像素电路的驱动方法，被配置为驱动上述像素电路，所述方法包括：
节点控制子电路在复位信号线、第一扫描信号线和第二扫描信号线的控制下，向第一节点提供第一初始信号线或者第三节点的信号，向第四节点提供第二初始信号线的信号，向第二节点提供数据信号线的信号；
存储子电路在第一扫描信号线为有效电平信号时，对第二节点进行充电；
驱动子电路第一节点和第二节点的控制下，向第三节点提供驱动电流；
发光控制子电路在发光信号线的控制下，向第二节点提供第一电源线的信号，并向第四节点提供第三节点的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的像素电路的结构示意图；
图2为一种节点控制子电路的结构示意图；
图3为另一节点控制子电路的结构示意图；
图4为一种像素电路的等效电路图；
图5为另一像素电路的等效电路图；
图6为图4和图5提供的像素电路的工作时序图；
图7为本公开实施例提供的显示基板的结构示意图一；
图8为本公开实施例提供的显示基板的结构示意图二；
图9为图7提供的显示基板形成半导体层图案后的示意图；
图10为图7提供的显示基板的第一导电层图案的示意图；
图11为图7提供的显示基板形成第一导电层图案后的示意图；
图12为图7提供的显示基板的第二导电层图案的示意图；
图13为图7提供的显示基板形成第二导电层图案后的示意图；
图14为图7提供的显示基板形成第三绝缘层后的示意图；
图15为图7提供的显示基板第三导电层图案的示意图；
图16为图7提供的显示基板形成第三导电层图案后的示意图；
图17为图7提供的显示基板形成第四绝缘层图案后的示意图；
图18为图7提供的显示基板的第四导电层图案的示意图；
图19为图7提供的显示基板形成第四导电层图案后的示意图；
图20为图8提供的显示基板形成遮挡层图案后的示意图；
图21为图8提供的显示基板的半导体层图案的示意图；
图22为图8提供的显示基板形成半导体层图案后的示意图；
图23为图8提供的显示基板的第一导电层图案的示意图；
图24为图8提供的显示基板形成第一导电层图案后的示意图；
图25为图8提供的显示基板的第二导电层图案的示意图；
图26为图8提供的显示基板形成第二导电层图案后的示意图；
图27为图8提供的显示基板形成第四绝缘层图案后的示意图；
图28为图8提供的显示基板的第三导电层图案的示意图；
图29为图8提供的显示基板形成第三导电层图案后的示意图；
图30为图8提供的显示基板形成第五绝缘层图案后的示意图；
图31为图8提供的显示基板的第四导电层图案的示意图；
图32为图8提供的显示基板形成第四导电层图案后的示意图；
图33为一种栅极驱动电路的连接示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构 造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通 过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
随着OLED技术的逐渐趋于成熟，相关产品已广泛运用与各大手机厂商推出的产品中，且还在不断的拓展其运用领域。为了满足专用户需求，显示产品存在高刷新率需求，高刷新率会导致像素电路中的充电时间不足，进而使得显示效果不佳。
图1为本公开实施例提供的像素电路的结构示意图。如图1所示，本公开实施例提供的像素电路，被配置为驱动发光器件发光，包括：节点控制子电路，存储子电路、驱动子电路和发光控制子电路。
如图1所示，节点控制子电路，分别与第一节点N1、第二节点N2、第三节点N3、第四节点N4、第一扫描信号线Gate1、第二扫描信号线Gate2、第一初始信号线INIT1、第二初始信号线INIT2、复位信号线Reset、数据信号线Data和第一电源线VDD电连接，被配置为在复位信号线Reset、第一扫描信号线Gate1和第二扫描信号线Gate2的控制下，向第一节点N1提供第一初始信号线INIT1或者第三节点N3的信号，向第四节点N4提供第二初始信号线INIT2的信号，向第二节点N2提供数据信号线Data的信号；存储子电路，分别与第二节点N2和第一电源线VDD电连接，被配置为在第一扫描信号线Gate1为有效电平信号时，对第二节点N2进行充电；驱动子电路，分别与第一节点N1、第二节点N2和第三节点N3电连接，被配置为第一节点N1和第二节点N2的控制下，向第三节点N3提供驱动电流；发光控制子电路，分别与发光信号线EM、第一电源线VDD、第二节点N2、第三节点N3和第四节点N4电连接，被配置为在发光信号线EM的控制下，向第二节点N2提供第一电源线VDD的信号，并向第四节点N4提供第三节点N3的 信号；发光器件的第一极与第四节点N4连接，发光器件的第二极与第二电源线VSS连接。
在一种示例性实施例中，第一电源线VDD持续提供高压电源信号，第二电源线VSS持续提供低压电源信号。
在一种示例性实施例中，第一初始信号线INIT1和第二初始信号线INIT2的初始信号可以相同，或者可以不同。在第一初始信号线INIT1和第二初始信号线INIT2的初始信号相同时，第一初始信号线INIT1和第二初始信号线INIT2可以采用同一信号线，或者可以采用不同信号线，本公开对此不做任何限定。
在一种示例性实施例中，发光器件，分别与第四节点N4和第二电源线VSS电连接。
在一种示例性实施例中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。示例性地，有机发光二极管的阳极与第四节点N4电连接，有机发光二极管的阴极与第二电源线VSS电连接。
在一种示例性实施例中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(EMectron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(EMectron Transport Layer，简称ETL)和电子注入层(EMectron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
本公开实施例提供了一种像素电路，本公开通过设置存储子电路使得在第一扫描信号线Gate1为有效电平信号时，对第二节点N2进行充电，可以在第一扫描信号线Gate1的信号为有效电平信号之后放电，在保证显示产品 的高刷新率的情况下延长对第一节点N1的充电时间，提升了显示产品的显示效果。
在示例性实施方式中，复位信号线Reset的信号为有效电平信号的时间段包括第一时间段和第二时间段，第一时间段发生在第二时间段之前；第一扫描信号线Gate1的信号为有效电平信号的时间段包括第三时间段和第四时间段，第三时间段发生在第四时间段之前；第二扫描信号线Gate2的信号为有效电平信号的时间段包括第五时间段和第六时间段，第五时间段发生在第六时间段之前，第二时间段和第三时间段至少部分交叠，第四时间段和第五时间段至少部分交叠。示例性地，第二时间段和第三时间段可以为同一时间段，第四时间段和第五时间段可以为同一时间段。
在示例性实施方式中，复位信号线Reset、第一扫描信号线Gate1和第二扫描信号线Gate2的信号为有效电平信号时，发光信号线EM的信号为无效电平信号，发光信号线EM的信号为有效电平信号时，复位信号线Reset、第一扫描信号线Gate1和第二扫描信号线Gate2的信号为无效电平信号。
图2为一种节点控制子电路的结构示意图。如图2所示，在示例性实施方式中，节点控制子电路可以包括：复位子电路、写入子电路、补偿子电路和储能子电路。
如图2所示，复位子电路，分别与复位信号线Reset、第一初始信号线INIT1、第二初始信号线INIT2、第一节点N1和第四节点N4电连接，被配置为在复位信号线Reset的控制下，向第一节点N1提供第一初始信号线INIT1的信号，向第四节点N4提供第二初始信号线INIT2的信号；写入子电路，分别与第一扫描信号线Gate1、数据信号线Data和第二节点N2电连接，被配置为在第一扫描信号线Gate1的控制下，向第二节点N2提供数据信号线Data的信号；补偿子电路，分别与第二扫描信号线Gate2、第一电源线VDD、第一节点N1和第三节点N3电连接，被配置为在第二扫描信号线Gate2的控制下，向第一节点N1提供第三节点N3的信号，储能子电路，分别与第一节点N1和第一电源线VDD电连接，被配置为存储第一节点N1和第一电源线VDD之间的信号的电压差。
图3为另一节点控制子电路的结构示意图。如图3所示，在示例性实施 方式中，复位子电路还与第一扫描信号线Gate1连接，被配置为在复位信号线Reset和第一扫描信号线Gate1的控制下，向第一节点N1提供第一初始信号线INIT1的信号，向第四节点N4提供第二初始信号线INIT2的信号。
图4为一种像素电路的等效电路图。如图4所示，在示例性实施方式中，复位子电路可以包括第一晶体管T1和第七晶体管T7，写入子电路可以包括第四晶体管T4，补偿子电路可以包括：第二晶体管T2，储能子电路可以包括：第一电容C1。
如图4所示，第一晶体管T1的控制极与复位信号线Reset电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第二扫描信号线Gate2电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第三节点N3电连接；第四晶体管T4的控制极与第一扫描信号线Gate1电连接，第四晶体管T4的第一极与数据信号线Data电连接，第四晶体管T4的第二极与第二节点N2电连接；第七晶体管T7的控制极与复位信号线Reset电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与第四节点N4电连接；第一电容C1的一端与第一电源线VDD电连接，第一电容C1的另一端与第一节点N1电连接。
图5为另一像素电路的等效电路图。如图5所示，在示例性实施方式中，复位子电路可以包括第一晶体管T1、第七晶体管T7和第八晶体管T8，写入子电路包括第四晶体管T4，补偿子电路可以包括：第二晶体管T2，储能子电路可以包括：第一电容C1。
如图5所示，第一晶体管T1的控制极与复位信号线Reset电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第八晶体管T8的第一极电连接；第二晶体管T2的控制极与第二扫描信号线Gate2电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第三节点N3电连接；第四晶体管T4的控制极与第一扫描信号线Gate1电连接，第四晶体管T4的第一极与数据信号线Data电连接，第四晶体管T4的第二极与第二节点N2电连接；第七晶体管T7的控制极与复位信号线Reset电连接，第七晶体管T7的第一极与第二初始信号线INIT2 电连接，第七晶体管T7的第二极与第四节点N4电连接；第八晶体管T8的控制极与第一扫描信号线Gate1电连接，第八晶体管T8的第二极与第一节点N1电连接；第一电容C1的一端与第一节点N1电连接，第一电容C1的另一端与第一电源线VDD电连接。
如图4和图5所示，在示例性实施方式中，存储子电路可以包括：第二电容C2。其中，第二电容C2的一端与第一电源线VDD电连接，第二电容C2的另一端与第二节点N2电连接。
如图4所示，在示例性实施方式中，节点控制子电路可以包括：第一晶体管T1、第二晶体管T2、第四晶体管T4、第七晶体管T7和第一电容C1，述存储子电路可以包括：第二电容C2；驱动子电路可以包括第三晶体管T3，发光控制子电路可以包括：第五晶体管T5和第六晶体管T6。其中，第一晶体管T1的控制极与复位信号线Reset电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第二扫描信号线Gate2电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第三节点N3电连接；第三晶体管T3的控制极与第一节电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接；第四晶体管T4的控制极与第一扫描信号线Gate1电连接，第四晶体管T4的第一极与数据信号线Data电连接，第四晶体管T4的第二极与第二节点N2电连接；第五晶体管T5的控制极与发光信号线EM电连接，第五晶体管T5的第一极与第一电源线VDD电连接，第五晶体管T5的第二极与第二节点N2电连接；第六晶体管T6的控制极与发光信号线EM电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第四节点N4电连接；第七晶体管T7的控制极与复位信号线Reset电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与第四节点N4电连接；第一电容C1的一端与第一电源线VDD电连接，第一电容C1的另一端与第一节点N1电连接；第二电容C2的一端与第一电源线VDD电连接，第二电容C2的另一端与第二节点N2电连接。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当 晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
如图5所示，在示例性实施方式中，节点控制子电路可以包括：第一晶体管T1、第二晶体管T2、第四晶体管T4、第七晶体管T7、第八晶体管T8和第一电容C1；存储子电路可以包括：第二电容C2；驱动子电路可以包括第三晶体管T3，发光控制子电路可以包括：第五晶体管T5和第六晶体管T6。其中，第一晶体管T1的控制极与复位信号线Reset电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第八晶体管T8的第一极电连接；第二晶体管T2的控制极与第二扫描信号线Gate2电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第三节点N3电连接；第三晶体管T3的控制极与第一节电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第 三节点N3电连接；第四晶体管T4的控制极与第一扫描信号线Gate1电连接，第四晶体管T4的第一极与数据信号线Data电连接，第四晶体管T4的第二极与第二节点N2电连接；第五晶体管T5的控制极与发光信号线EM电连接，第五晶体管T5的第一极与第一电源线VDD电连接，第五晶体管T5的第二极与第二节点N2电连接；第六晶体管T6的控制极与发光信号线EM电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第四节点N4电连接；第七晶体管T7的控制极与复位信号线Reset电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与第四节点N4电连接；第八晶体管T8的控制极与第一扫描信号线Gate1电连接，第八晶体管T8的第二极与第一节点N1电连接；第一电容C1的一端与第一电源线VDD电连接，第一电容C1的另一端与第一节点N1电连接；第二电容C2的一端与第一电源线VDD电连接，第二电容C2的另一端与第二节点N2电连接。本公开通过设置第八晶体管，可以避免第一节点N1漏电，提升像素电路的可靠性。
在示例性实施方式中，第一晶体管T1到第八晶体管T8可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第八晶体管T8可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
一种示例性实施例中，第三晶体管T3可以称为驱动晶体管，第三晶体 管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流经的驱动电流。
一种示例性实施例中，第五晶体管T5和第六晶体管T6可以称为发光晶体管。当发光信号线EM的信号为有效电平信号时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
图4和图5中示出了节点控制子电路、存储子电路、驱动子电路和发光控制子电路的一个示例性结构。本领域技术人员容易理解是，节点控制子电路、存储子电路、驱动子电路和发光控制子电路的实现方式不限于此。
图6为图4和图5提供的像素电路的工作时序图，图6是以像素电路中的所有晶体管为P型晶体管为例进行说明的。
在示例性实施方式中，数据信号线Data可以在第二阶段S2和/或第三阶段S3输出数据电压，图6是以数据信号线Data在第二阶段S2和第三阶段S3输出数据电压为例进行说明的。
在示例性实施方式中，像素电路所在的显示基板包括：至少一个栅极驱动电路，至少一个栅极驱动电路与第一扫描信号线、第二扫描信号线、发光信号线和复位信号线中的至少一种信号线电连接，栅极驱动电路包括：多个移位寄存器，当多个移位寄存器之间存在级联关系时，数据信号线Data可以只在第三阶段S3或第二阶段S2输出数据电压。数据信号线Data在第三阶段S3或第二阶段S2输出数据电压可以避免信号之间的串扰，可以提升像素电路所在的显示基板的显示效果。
图4的像素电路的工作过程可以包括：
第一阶段S1，称为初始化阶段，复位信号线Reset的信号为低电平信号，第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM的信号为高电平信号。复位信号线Reset为低电平信号，第一晶体管T1和第七晶体管T7导通，第一初始信号线INIT1的信号通过导通的第一晶体管T1写入第一节点N1，对第一节点N1进行初始化(复位)，清空其内部的预存电压，完成初始化，第二初始信号线INIT2的信号通过导通的第七晶体管T7写入第 四节点N4，对第四节点N4进行初始化(复位)，清空其内部的预存电压，完成初始化。第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM的信号为高电平信号的信号为高电平信号，第二晶体管T2、第四晶体管T4、第五晶体管T5和第六晶体管T6和第七晶体管T7截止，此阶段，发光器件L不发光。
第二阶段S2，称为充电阶段，复位信号线Reset和第一扫描信号线Gate1的信号为低电平信号，第二扫描信号线Gate2和发光信号线EM的信号为高电平信号，数据信号线Data输出数据电压。复位信号线Reset为低电平信号，第一晶体管T1和第七晶体管T7持续导通，第一初始信号线INIT1的信号通过导通的第一晶体管T1写入第一节点N1，对第一节点N1持续进行初始化(复位)，清空其内部的预存电压，完成初始化，第二初始信号线INIT2的信号通过导通的第七晶体管T7写入第四节点N4，对第四节点N4持续进行初始化(复位)，清空其内部的预存电压，完成初始化，第一扫描信号线Gate1的信号为低电平信号，第四晶体管T4导通，数据信号线Data的信号通过导通的第四晶体管T4写入第二节点N2，以对第二电容C2进行充电，第二扫描信号线Gate2和发光信号线EM的信号为高电平信号的信号为高电平信号，第二晶体管T2、第五晶体管T5和第六晶体管T6第七晶体管T7截止，此阶段，发光器件L不发光。
第三阶段S3、称为数据写入阶段，第一扫描信号线Gate1和第二扫描信号线Gate2的信号为低电平信号，复位信号线Reset和发光信号线EM的信号为高电平信号，数据信号线Data输出数据电压。第一节点N1为低电平信号，第三晶体管T3导通。第一扫描信号线Gate1和第二扫描信号线Gate2的信号为低电平信号，第二晶体管T2和第四晶体管T4导通，数据信号线Data输出的数据电压对第一节点N1进行充电，数据信号线Data输出的数据电压经过导通的第四晶体管T4、第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2写入第一节点N1。复位信号线Reset和发光信号线EM的信号为高电平信号，第一晶体管T1、第五晶体管T5、第六晶体管T6和第七晶体管T7截止。此阶段，第一节点N1的电压小于Vd-|Vth|，第三晶体管T3持续导通，发光器件L不发光。
第四阶段S4、称为放电阶段，第二扫描信号线Gate2的信号为低电平信号，第一扫描信号线Gate1、复位信号线Reset和发光信号线EM的信号为高电平信号。第三晶体管T3持续导通。第二扫描信号线Gate2的信号为低电平信号，第四晶体管T4持续导通，第二电容C2继续对第一节点N1进行充电，第二节点N2的信号经过导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管T3的阈值电压。第一扫描信号线Gate1、复位信号线Reset和发光信号线EM的信号为高电平信号，第一晶体管T1、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7截止。此阶段，发光器件L不发光。
第五阶段S5、称为发光阶段，发光信号线EM的信号为低电平信号，第一扫描信号线Gate1、第二扫描信号线Gate2和复位信号线的信号为高电平信号。第一扫描信号线Gate1、第二扫描信号线Gate2和复位信号线的信号为高电平信号，第一晶体管T1、第二晶体管T2、第四晶体管T4和第七晶体管T7截止。发光信号线EM的信号为低电平信号，第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第二节点N2、第三晶体管T3、第三节点N3、导通的第六晶体管T6和第四节点N4向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vdd为第一电源线VDD输出的电源电压。
本公开通过设置第二电容C2可以在第三阶段即数据写入阶段之后在第四阶段S4继续对第一节点N1进行充电，延长了对第一节点N1的充电时间，有效地解决了像素电路充电不足的技术问题。
在示例性实施方式中，如图5和图6所示，图5的像素电路的工作过程可以包括：
第一阶段S1，称为初始化阶段，复位信号线Reset的信号为低电平信号，第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM的信号为高电平信号。复位信号线Reset为低电平信号，第一晶体管T1和第七晶体管T7导通，第二初始信号线INIT2的信号通过导通的第七晶体管T7写入第四节点N4，对第四节点N4进行初始化(复位)，清空其内部的预存电压，完成初始化。第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM的信号为高电平信号的信号为高电平信号，第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8截止，此阶段，发光器件L不发光。
第二阶段S2，称为充电阶段，复位信号线Reset和第一扫描信号线Gate1的信号为低电平信号，第二扫描信号线Gate2和发光信号线EM的信号为高电平信号，数据信号线Data输出数据电压。复位信号线Reset为低电平信号，第一晶体管T1和第七晶体管T7持续导通，第一扫描信号线Gate1的信号为低电平信号，第八晶体管T8导通，第一初始信号线INIT1的信号通过导通的第一晶体管T1和导通的第八晶体管T8写入第一节点N1，对第一节点N1持续进行初始化(复位)，清空其内部的预存电压，完成初始化，第二初始信号线INIT2的信号通过导通的第七晶体管T7写入第四节点N4，对第四节点N4持续进行初始化(复位)，清空其内部的预存电压，完成初始化，第一扫描信号线Gate1的信号为低电平信号，第四晶体管T4导通，数据信号线Data的信号通过导通的第四晶体管T4写入第二节点N2，以对第二电容C2进行充电，第二扫描信号线Gate2和发光信号线EM的信号为高电平信号的信号为高电平信号，第二晶体管T2、第五晶体管T5和第六晶体管T6第七晶体管T7截止，此阶段，发光器件L不发光。
第三阶段S3、称为数据写入阶段，第一扫描信号线Gate1和第二扫描信号线Gate2的信号为低电平信号，复位信号线Reset和发光信号线EM的信号为高电平信号，数据信号线Data输出数据电压。第一节点N1为低电平信号，第三晶体管T3导通。第一扫描信号线Gate1和第二扫描信号线Gate2 的信号为低电平信号，第二晶体管T2、第四晶体管T4和第八晶体管T8导通，数据信号线Data输出的数据电压对第一节点N1进行充电，数据信号线Data输出的数据电压经过导通的第四晶体管T4、第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2写入第一节点N1。复位信号线Reset和发光信号线EM的信号为高电平信号，第一晶体管T1、第五晶体管T5、第六晶体管T6和第七晶体管T7截止。此阶段，第一节点N1的电压小于Vd-|Vth|，第三晶体管T3持续导通，发光器件L不发光。
第四阶段S4、称为放电阶段，第二扫描信号线Gate2的信号为低电平信号，第一扫描信号线Gate1、复位信号线Reset和发光信号线EM的信号为高电平信号。第三晶体管T3持续导通。第二扫描信号线Gate2的信号为低电平信号，第四晶体管T4持续导通，第二电容C2继续对第一节点N1进行充电，第二节点N2的信号经过导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管T3的阈值电压。第一扫描信号线Gate1、复位信号线Reset和发光信号线EM的信号为高电平信号，第一晶体管T1、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8截止。此阶段，发光器件L不发光。
第五阶段S5、称为发光阶段，发光信号线EM的信号为低电平信号，第一扫描信号线Gate1、第二扫描信号线Gate2和复位信号线的信号为高电平信号。第一扫描信号线Gate1、第二扫描信号线Gate2和复位信号线的信号为高电平信号，第一晶体管T1、第二晶体管T2、第四晶体管T4和第七晶体管T7截止。发光信号线EM的信号为低电平信号，第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第二节点N2、第三晶体管T3、第三节点N3、导通的第六晶体管T6和第四节点N4向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vdd为第一电源线VDD输出的电源电压。
本公开通过设置第二电容C2可以在第三阶段即数据写入阶段之后在第四阶段S4继续对第一节点N1进行充电，延长了对第一节点N1的充电时间，有效地解决了像素电路充电不足的技术问题，可以提升显示产品的显示效果。
本公开实施例还提供一种显示基板，图7为本公开实施例提供的显示基板的结构示意图一，图8为本公开实施例提供的显示基板的结构示意图二。如图7和图8所示，显示基板可以包括：基底以及依次设置在基底上的驱动电路层和发光结构层，驱动电路层包括像素电路、多条第一初始信号线INIT1、多条第二初始信号线INIT2、多条第一扫描信号线Gate1、多条第二扫描信号线Gate2、多条复位信号线Reset、多条第一电源线VDD和多条数据信号线Data，发光结构层包括：发光器件。图7是以显示基板包括图4提供像素电路为例进行说明的，图8是以显示基板包括图5提供的像素电路为例进行说明的。
像素电路为前述任一个实施例提供的像素电路，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示基板还可以包括设置在发光结构层远离基底一侧的封装结构层。显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，在平行于显示基板的平面上，显示基板可以包括：多个子像素，至少一个子像素可以包括：像素电路和发光器件，像素电路被配置为向所连接的发光器件输出相应的电流，使该发光器件发出相应亮度的光。
在示例性实施方式中，多个子像素可以包括多个像素行和多个像素列。沿着水平方向依次排布的多个子像素可以称为像素行，沿着竖直方向依次排布的多个子像素可以称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
在示例性实施方式中，多个子像素构成一个像素单元，像素单元可以包括第一子像素、第二子像素和第三子像素，或者第一子像素、第二子像素、第三子像素和第四子像素。
在示例性实施方式中，当像素单元包括第一子像素、第二子像素和第三子像素时，第一子像素可以是出射红色光线的红色子像素(R)，第二子像素可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)，三个子像素的形状可以是三角形、矩形状、菱形、五边形或六边形等，本公开在此不做限定。在像素行方向上，第一子像素、第二子像素和第三子像素可以按照对齐方式依次设置，在像素列方向上，第一子像素、第二子像素和第三子像素可以按照错位方式依次设置，形成子像素的品字布局。例如，奇数行中的第一子像素可以位于偶数行中相邻的第二子像素和第三子像素之间，或者，偶数行中的第一子像素可以位于奇数行中相邻的第二子像素和第三子像素之间。又如，奇数行中的第二子像素可以位于偶数行中相邻的第一子像素和第三子像素之间，或者，偶数行中的第二子像素可以位于奇数行中相邻的第一子像素和第三子像素之间。再如，奇数行中的第三子像素可以位于偶数行中相邻的第一子像素和第二子像素之间，或者，偶数行中的第三子像素可以位于奇数行中相邻的第一子像素和第二子像素之间。
在示例性实施方式中，像素单元包括第一子像素、第二子像素、第三子像素和第四子像素时，第一子像素可以是出射红色光线的红色子像素(R)，第二子像素可以是出射蓝色光线的蓝色子像素(B)，第三子像素和第四子像素可以是出射绿色光线的绿色子像素(G)，三个子像素的形状可以是三角形、矩形状、菱形、五边形或六边形等，本公开在此不做限定。在示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。四个子像素可以采用正方形(Square)方式排列，形成GGRB像素排布。在另一种示例性实施方式中，四个子像素可以采用钻石形(Diamond)方式排列，形成RGGB像素排布。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装 层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，显示基板可以为低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)显示基板或者低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板。
在一种示例性实施例中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、导电箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在一种示例性实施例中，发光结构层包括：依次叠设在基底上的阳极层、像素定义层、有机结构层和阴极层；所述阳极层包括：阳极，所述有机结构层包括：有机发光层，所述阴极层包括：阴极。
在示例性实施方式中，驱动电路层包括：依次叠设在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层和第四导电层，像素电路包括：多个晶体管、第一电容和第二电容，第一电容和第二电容包括：第一极板和第二极板；
半导体层至少包括：多个晶体管的有源层和第二电容的第一极板；
第一导电层至少包括：复位信号线、发光信号线、多个晶体管的控制极、第一电容的第一极板；
第二导电层至少包括：第二初始信号线、第一电容的第二极板和第二电容的第二极板；
第三导电层至少包括：第一扫描信号线和第二扫描信号线；
第四导电层至少包括：第一初始信号线、第一电源线和数据信号线。
在示例性实施方式中，像素电路包括第一晶体管至第七晶体管，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区；
第三晶体管的有源层的第一区沿第一方向的长度大于第三晶体管的有源层的第二区沿第一方向的长度，所述第三晶体管的有源层的第一区复用为第 二电容的第一极板。
在示例性实施方式中，对于同一像素电路，第一电容的第二极板与第二电容的第二极板连接，位于同一行的第N列像素电路的第二电容的第二极板与第N+1列像素电路的第一电容的第二极板连接；
第一电容的第二极板沿第二方向的长度小于第二电容的第二极板沿第二方向的长度，第一方向和第二方向相交。
在示例性实施方式中，第二电容的第二极板包括：沿第二方向延伸的电容主体部以及沿第一方向延伸的第一连接块和第二连接块；第一连接块和第二连接块分别与电容主体部连接，第一连接块和第二连接块平行设置，且位于电容主体部远离第一电容的第二极板的一侧；
电容主体部在基底上的正投影与第二电容的第一极板在基底上的正投影至少部分交叠，第一连接块在基底上的正投影与位于第二晶体管的控制极之间的第二晶体管的有源层在基底上的正投影部分交叠，第二连接块在基底上的正投影与第三晶体管的有源层在基底上的正投影部分交叠；
对于同一像素电路，第一电容的第二极板与电容主体部连接，位于同一行的第N列像素电路的第二连接块与第N+1列像素电路的第一电容的第二极板连接。
在示例性实施方式中，第一电源线的沿第一方向的长度大于数据信号线沿第一方向的长度，且大于第一初始信号线的沿第一方向的长度，第一初始信号线的沿第一方向的长度大于数据信号线的沿第一方向的长度。
在示例性实施方式中，驱动电路层包括：遮挡层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层和第四导电层，像素电路包括：多个晶体管、第一电容和第二电容，第一电容包括：第一极板和第二极板，第二电容包括：第一极板、第二极板和第三极板；
遮挡层至少包括：第二电容的第一极板，遮挡层被配置为传输高压电源信号；
半导体层至少包括：多个晶体管的有源层、第二电容的第二极板、第一 初始信号线和第二初始信号线；
第一导电层至少包括：发光信号线、多个晶体管的控制极和第一电容的第一极板；
第二导电层至少包括：第一电容的第二极板和第二电容的第三极板；
第三导电层至少包括：两条复位信号线、第一扫描信号线和第二扫描信号线；
第四导电层至少包括：第一电源线和数据信号线。
在示例性实施方式中，多个晶体管包括：第一晶体管至第八晶体管，遮挡层还包括：第一遮挡结构、第二遮挡结构、第一遮挡连接结构、第二遮挡连接结构、第三遮挡连接结构和第四遮挡连接结构，第二电容的第一极板复用为第二遮挡结构；
第一遮挡连接结构和第二遮挡结构分别位于第一遮挡结构相对设置的两侧，且与第一遮挡结构连接，第二遮挡连接结构位于第二遮挡结构远离第一遮挡结构的一侧，且与第二遮挡结构连接，第三遮挡连接结构和第四遮挡连接结构分别位于第一遮挡结构相对设置的另外两侧，且第三遮挡连接结构与第二遮挡结构连接，第四遮挡连接结构与第一遮挡结构连接；
第一遮挡结构在基底上的正投影与第三晶体管的有源层的沟道区在基底上的正投影至少部分交叠，第二遮挡结构在基底上的正投影与第二电容的第二极板在基底上的正投影至少部分交叠，第三遮挡连接结构在基底上的正投影与第一晶体管的有源层在基底上的正投影至少部分交叠，第四遮挡连接结构在基底上的正投影与第七晶体管的有源层基底上的正投影至少部分交叠。
在示例性实施方式中，位于同一行的第N列子像素的第二遮挡结构位于第N列子像素的第一遮挡结构靠近第N+1列子像素的第一遮挡结构的一侧，位于同一行的第N列子像素的第一遮挡连接结构位于第N列子像素的第一遮挡结构靠近第N-1列子像素的第一遮挡结构的一侧，且与第N-1列子像素的第四遮挡连接结构连接，位于同一行的第N列子像素的第二遮挡连接结构与第N+1列子像素的第一遮挡连接结构连接；位于同一列的第M行子像素的第三遮挡连接结构位于第M行子像素的第一遮挡结构11靠近第M-1行子像 素的第一遮挡结构的一侧，且与第M-1行子像素的第四遮挡连接结构连接，位于同一列的第M行子像素的第四遮挡连接结构位于第M行子像素的第一遮挡结构靠近第M+1行子像素的第一遮挡结构的一侧，且与第M+1行子像素的第五遮挡连接结构连接。
在示例性实施方式中，对于同一子像素，第一电容的第二极板和第二电容的第三极板相互连接；
对于同一行的子像素，第N列子像素的第二电容的第三极板位于第N列子像素的第一电容的第二极板靠近第N+1列子像素的第一电容的第二极板，且与第N+1列子像素的第一电容的第二极板连接；
第一电容的第二极板沿第二方向的长度小于第二电容的第三极板沿第二方向的长度。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开在此不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
下面以一行两列像素电路说明图7提供的显示基板的制备过程。一种示例性实施例提供的显示基板的制备过程可以包括：
(1)在基底上形成半导体层图案。在示例性实施方式中，形成半导体层 图案可以包括：在基底上依次沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图9所示，图9为图7提供的显示基板形成半导体层图案后的示意图。
在示例性实施方式中，如图9所示，每个子像素的半导体层图案至少可以包括：第一晶体管的有源层T11至第七晶体管的有源层T71。
在示例性实施方式中，如图9所示，第一晶体管的有源层T11至第六晶体管的有源层T61为相互连接的一体结构。
在示例性实施方式中，如图9所示，在第一方向X上，第二晶体管的有源层T21和第六晶体管的有源层T61可以位于本子像素中第三晶体管的有源层T31的同一侧，第四晶体管的有源层T41和第五晶体管的有源层T51可以位于本子像素中第三晶体管的有源层T31的同一侧，第二晶体管的有源层T21和第四晶体管的有源层T41可以位于本子像素的第三晶体管的有源层T31的不同侧。在第二方向Y上，第一晶体管的有源层T11、第二晶体管的有源层T21、第四晶体管的有源层T41和第七晶体管的有源层T71可以位于本子像素中第三晶体管的有源层T31的同一层，第五晶体管的有源层T51和第六晶体管的有源层T61可以位于本子像素中第三晶体管的有源层T31的另一侧。
在示例性实施方式中，如图9所示，第一晶体管的有源层T11的形状可以呈“n”字形，第二晶体管的有源层T21的形状可以呈“L”字形，第三晶体管的有源层T31的形状可以呈“Ω”字形，第四晶体管的有源层T41、第五晶体管的有源层T51、第六晶体管的有源层T61和第七晶体管的有源层T71的形状可以呈“I”字形。
在示例性实施方式中，如图9所示，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一晶体管的有源层T11的第二区T11_2可以作为第二晶体管的有源层T21的第一区T21_1，第三晶体管的有源层T31的第一区T31_1可以同时作为第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2，第三晶体管的有源层T31的第二区T31_2可以同时作为第二晶体管的有源层T21的第二区T21_2和第六晶体管的有源层T61的第一区T61_1， 第六晶体管的有源层T61的第二区T61_2可以作为第七晶体管的有源层T71的第二区T71_2，第一晶体管的有源层T11的第一区T11_1、第四晶体管的有源层T41的第一区T41_1、第五晶体管的有源层T51_1的第一区T51_1和第七晶体管的有源层T71的第一区T71_1可以单独设置。
在示例性实施方式中，如图9所示，第三晶体管的有源层T31的第一区T31_1(也是第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2)的形状可以为沿第二方向Y延伸的条状结构，且沿第一方向X的长度大于第四晶体管的有源层T41的第一区T41_1和第五晶体管的有源层T51的第一区T51_1沿第一方向的长度。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及位于第一绝缘层上的第一导电层图案，如图10和图11所示，其中，图10为图7提供的显示基板的第一导电层图案的示意图，图11为图7提供的显示基板形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，每个子像素的第一导电层图案至少可以包括：复位信号线Reset、发光信号线EM、第一晶体管的控制极T12至第七晶体管的控制极T72、第一电容的第一极板C11。
在示例性实施方式中，如图10和图11所示，第一电容的第一极板C11的形状可以为矩形状，且矩形状的角部可以设置倒角，第一电容的第一极板C11在基底上的正投影与第三晶体管T3的有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一电容的第一极板C11可以同时作为第三晶体管T3的控制极T32。
在示例性实施方式中，如图10和图11所示，复位信号线Reset的形状可以为沿着第一方向X延伸的线形状，复位信号线Reset可以位于第一电容的第一极板C11远离发光信号线EM的一侧。复位信号线Reset与第一晶体管T1的有源层相重叠的区域作为第一晶体管的控制极T12，复位信号线Reset与第七晶体管的有源层相重叠的区域作为第七晶体管的控制极T72。由于第 一晶体管的有源层T11的形状可以呈“n”字形，因此，复位信号线Reset与第一晶体管的有源层相重叠的区域有两个，也就是说，第一晶体管的控制极T12有两个，第一晶体管为双栅结构。
在示例性实施方式中，发光信号线EM的形状可以为沿着第一方向X延伸的线形状，发光信号线EM与第五晶体管T5的有源层相重叠的区域作为第五晶体管T5的控制极T52，发光信号线EM与第六晶体管T6的有源层相重叠的区域作为第六晶体管T6的控制极T62。
在示例性实施方式中，如图10和图11所示，第二晶体管T2的控制极T22和第四晶体管T4的控制极T42可以位于第一电容的第一极板C11靠近复位信号线Reset的一侧，且本子像素的第四晶体管的控制极T42位于本子像素的第二晶体管T2的控制极T22靠近相邻列子像素的第二晶体管T2的控制极T22的一侧。
在示例性实施方式中，如图10和图11所示，第二晶体管的控制极T22可以包括第一电极连接部T22A和第二电极连接部T22B，且第一电极连接部T22A位于第二电极连接部T22B远离第四晶体管的控制极T42的一侧，第一电极连接部T22A为沿第一方向X延伸的线形状，第二电极连接部T22B为沿第二方向Y延伸的线形状，第一电极连接部T22A和第二电极连接部T22B在基底上的正投影与第二晶体管的有源层在基底上的正投影部分交叠，因此，第二晶体管的控制极T22与第二晶体管的有源层T21相重叠的区域有两个，也就是说，第二晶体管的控制极T22有两个，第二晶体管为双栅结构。
在示例性实施方式中，第四晶体管的控制极T42的形状可以为沿着第一方向X延伸的线形状。
在示例性实施方式中，复位信号线Reset和发光信号线EM可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区，未被第一导电层遮挡区域的半 导体层被导体化，即第一晶体管的有源层至第七晶体管的有源层的第一区和第二区均被导体化，且导体化后的第三晶体管的有源层的第一区(也是第四晶体管的有源层的第二区和第五晶体管的有源层的第二区)可以同时作为第三晶体管的第一极T33、第四晶体管的第二极T44、第五晶体管的第二极T54和第二电容的第一极板C21，导体化后的第三晶体管的有源层T31的第二区T31_2(也是第二晶体管的有源层T21的第二区T21_2和第六晶体管的有源层T61的第一区T61_1)也是同时作为第二晶体管的第二极T24、第三晶体管的第二极T34和第六晶体管的第一极T63。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第二绝缘层薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，在第二绝缘层上形成第二导电层图案。图12和图13所示，图12为图7提供的显示基板的第二导电层图案的示意图，图13为图7提供的显示基板形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图12和图13所示，每个子像素的第二导电层图案至少可以包括：第二初始信号线INIT2、第一电容的第二极板C12和第二电容的第二极板C22。
在示例性实施方式中，如图12和图13所示，第一电容的第二极板C12和第二电容的第二极板C22为相互连接的一体结构。
在示例性实施方式中，如图12和图13所示，第一电容的第二极板C12的形状可以为矩形状，且矩形状的角部可以设置倒角，第一电容的第二极板C12在基底上的正投影与第一电容的第一极板在基底上的正投影至少部分交叠。第一电容的第二极板C12上设置有开口V0，开口V0的形状可以为矩形状，可以位于第一电容的第二极板C12的中部，使第一电容的第二极板C12形成环形结构。开口暴露出覆盖第一电容的第一极板的第二绝缘层，且第一电容的第一极板在基底上的正投影包含开口V0在基底上的正投影。
在示例性实施方式中，如图12和图13所示，第二电容的第二极板C22可以包括：相互连接的电容主体部C22_1、第一连接块C22_2和第二连接块C22_3。电容主体部C22_1的形状可以为沿第二方向Y延伸的线形状，第一 连接块C22_2和第二连接块C22_3的形状可以为沿第一方向X延伸的线形状，。第一连接块C22_2和第二连接块C22_3可以位于电容主体部C22_1远离第一电容的第二极板C12的一侧，且第一连接块C22_2和第二连接块C22_3沿第二方向Y排布，即第二电容的第二极板C22可以为梳妆结构，电容主体部C22_1可以作为梳背，第一连接块C22_2和第二连接块C22_3分别作为梳齿。
在示例性实施方式中，如图12和图13所示，电容主体部C22_1在基底上的正投影与第二电容的第一极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图12和图13所示，第一连接块C22_2在基底上的正投影与位于第二晶体管的控制极之间的第二晶体管的有源层在基底上的正投影至少部分交叠。第一连接块在基底上的正投影与位于第二晶体管的控制极之间的第二晶体管的有源层在基底上的正投影至少部分交叠，可以使得位于第二晶体管的控制极之间的第二晶体管的有源层被第一连接块遮挡屏蔽，可以有效地防止漏电，从而改善了显示基板的信赖性。
在示例性实施方式中，如图12和图13所示，第二连接块C22_3在基底上的正投影与第三晶体管的有源层的第二区(也是第二晶体管的有源层的第二区和第六晶体管的有源层的第一区)在基底上的正投影至少部分交叠。
在示例性实施方式中，如图12和图13所示，沿第一方向X延伸的虚拟直线不同时穿过第一电容的第二极板C12和第一连接块C22_2，沿第一方向延伸的虚拟直线穿过第一电容的第二极板C12和第一连接块C22_2。
在示例性实施方式中，如图12和图13所示，本子像素中的第一电容的第二极板C12与第二电容的第二极板C22的电容主体部连接。本子像素的第二连接块与相邻子像素的第一电容的第二极板C12连接。
在示例性实施方式中，如图12和图13所示，第一电容的第二极板C12沿第二方向Y的长度小于第二电容的第二极板C22沿第二方向Y的长度。在示例性实施方式中，第一连接块C22_2沿第二方向Y的长度可以与第二连接块C22_3沿第二方向Y的长度相同，或者不同，本公开对此不作任何限定。
在示例性实施方式中，如图12和图13所示，第二初始信号线INIT2可以为沿第一方向X延伸的线形状，第二初始信号线INIT2可以位于复位信号 线远离第一电容的第一极板的一侧。第二初始信号线INIT2在基底上的正投影可以与第七晶体管的有源层和第一晶体管的有源层在基底上的正投影部分交叠。
在一种示例性实施例中，沿第一方向X排布的子像素的第一电容的第二极板C12与相邻子像素的第二电容的第二极板C22连接，可使得沿第一方向X排布的子像素的第一电容的第二极板C12和第二电容的第二极板C22流经的信号相同，可以提升显示基板显示的均一性。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图14所示，图14为图7提供的显示基板形成第三绝缘层后的示意图。
在示例性实施方式中，如图14所示，每个子像素的第三绝缘层的多个过孔至少可以包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10和第十一过孔V11。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第一晶体管的有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第一区的表面，第一过孔V1被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一晶体管的有源层的第一区连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)在基底上的正投影的范围之内，第二过孔V2内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)的表面，第二过孔V2被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管的第一极)通过该过孔与第一晶体管的有源层的第一区(也是第二晶体管的有源层的第一区)连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第四晶体管 的有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第三过孔V3被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第五晶体管的有源层的第一区在基底上的正投影的范围之内，第四过孔V4内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第五晶体管的有源层的第一区的表面，第四过孔V4被配置为使后续形成的第五晶体管的第一极通过该过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)在基底上的正投影的范围之内，第五过孔V5内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)的表面，第五过孔V5被配置为使后续形成的第六晶体管T1的第二极(也是第七晶体管的第二极)通过该过孔与第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第七晶体管的有源层的第一区在基底上的正投影的范围之内，第六过孔V6内的第一绝缘层和第二绝缘层被刻蚀掉，暴露出第七晶体管的有源层的第一区的表面，第六过孔V6被配置为使后续形成的第七晶体管的第一极通过该过孔与第七晶体管的有源层的第一区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第二晶体管的控制极的第二电极连接部在基底上的正投影的范围之内，第七过孔V7内的第二绝缘层被刻蚀掉，暴露出第二晶体管的控制极的表面，第七过孔V7被配置为使后续形成的第二扫描信号线通过该过孔与第二晶体管的控制极连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于开口在基底上的正投影的范围之内，第八过孔V8内的第二绝缘层被刻蚀掉，暴露出第一电容的第一极板(也是第三晶体管的控制极)的表面，第八过孔V8被配 置为使后续形成的第一晶体管的第二极(也是第二晶体管的第一极)通过该过孔与第一电容的第一极板(也是第三晶体管的控制极)连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第四晶体管的控制极在基底上的正投影的范围之内，第九过孔V9内的第二绝缘层被刻蚀掉，暴露出第四晶体管的控制极的表面，第九过孔V9被配置为使后续形成的第一扫描信号线通过该过孔与第四晶体管的控制极连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第二初始信号线INIT2在基底上的正投影的范围之内，第十过孔V10暴露出第二初始信号线INIT2的表面，第十过孔V10被配置为使后续形成的第七晶体管的第一极通过该过孔与第二初始信号线INIT2连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第一电容的第二极板(也是第二电容的第二极板)在基底上的正投影的范围之内，第十一过孔V11暴露出第一电容的第二极板(也是第二电容的第二极板)的表面，第十一过孔V11被配置为使后续形成的第五晶体管的第一极通过该过孔与第一电容的第二极板(也是第二电容的第二极板)连接。在示例性实施方式中，第十一过孔V11可以是多个，多个第十一过孔V11可以沿着第二方向Y依次设置，以提高连接可靠性。
在示例性实施例中，沿第二方向延伸的虚拟直线可以经过第二过孔V2和第八过孔V8。
在示例性实施例中，沿第二方向延伸的虚拟直线可以经过第四过孔V4和第九过孔V9。
在示例性实施例中，沿第二方向延伸的虚拟直线经过第五过孔V5和第七过孔V7。
在示例性实施例中，沿第二方向延伸的虚拟直线经过第六过孔V6和第十过孔V10。
(5)形成第三导电层。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，图15和图16所 示，图15为图7提供的显示基板第三导电层图案的示意图，图16为图7提供的显示基板形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图15和图16所示，每个子像素的第三导电层图案至少可以包括：第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第一极T73和第二极T74，第一扫描信号线Gate1和第二扫描信号线Gate2。
在示例性实施方式中，如图15和图16所示，第一晶体管的第二极T14可以同时作为第二晶体管的第一极T23、第六晶体管的第二极T64可以同时作为第七晶体管的第二极T74，第一晶体管的第一极T13、第四晶体管的第一极T43、第五晶体管的第一极T53和第七晶体管的第一极T73可以单独设置。
在示例性实施方式中，如图15和图16所示，第一晶体管的第一极T13、第四晶体管的第一极T43和第七晶体管的第一极T73可以位于第一扫描信号线Gate1远离第二扫描信号线Gate2的一侧，且第四晶体管的第一极T43和第七晶体管的第一极T73分别位于第一晶体管的第一极T13的两侧。
在示例性实施方式中，如图15和图16所示，第一晶体管的第二极T14(也是第二晶体管的第一极T23)、第五晶体管的第一极T53和第六晶体管的第二极T64(第七晶体管的第二极T74)可以位于第二扫描信号线Gate2远离第一扫描信号线Gate1的一侧。且第六晶体管的第二极T64(第七晶体管的第二极T74)和第五晶体管的第一极T53分别位于第一晶体管的第二极T14(也是第二晶体管的第一极T23)的两侧。
在示例性实施方式中，如图15和图16所示，第一晶体管的第一极T13的形状可以为块状结构，第一晶体管的第一极T13。第一晶体管的第一极T13在基底上的正投影可以与第一过孔和复位信号线RESET在基底上的正投影部分交叠。第一晶体管的第一极T13通过第一过孔与第一晶体管的有源层的第一区连接。
在示例性实施方式中，如图15和图16所示，第一晶体管的第二极T14 (也是第二晶体管的第一极T23)的形状可以为沿第二方向Y延伸的线型状。第一晶体管的第二极T14(也是第二晶体管的第一极T23)在基底上的正投影可以与第二过孔、第八过孔、第一电容的第一极板和第一电容的第二极板在基底上的正投影部分交叠。第一晶体管的第二极T14(也是第二晶体管的第一极T23)通过第二过孔与第一晶体管的有源层的第二区(也是第二晶体管的有源层的第一区)连接，且通过第八过孔与第一电容的第一极板连接。
在示例性实施方式中，如图15和图16所示，第四晶体管的第一极T43的形状可以为沿第二方向Y延伸的线型状。第四晶体管的第一极T43在基底上的正投影与第三过孔和复位信号线Reset在基底上的正投影至少部分交叠。第四晶体管的第一极通过第三过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，如图15和图16所示，第五晶体管的第一极T53的形状可以为沿第二方向Y延伸的线型状。第五晶体管的第一极T53在基底上的正投影可以与第四过孔、第十一过孔、发光信号线EM和第一电容的第二极板(也是第二电容的第二极板)在基底上的正投影至少部分交叠。第五晶体管的第一极T53通过第四过孔与第五晶体管的有源层的第一区连接，且通过第十一过孔与第一电容的第二极板(也是第二电容的第二极板)在基底上的正投影交叠。
在示例性实施方式中，如图15和图16所示，第六晶体管的第二极T64(第七晶体管的第二极T74)可以为块状结构。第六晶体管的第二极T64(第七晶体管的第二极T74)在基底上的正投影可以与第五过孔和发光信号线EM在基底上的正投影至少部分交叠。第六晶体管的第二极T64(第七晶体管的第二极T74)通过第五过孔V5与第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)连接。
在示例性实施方式中，如图15和图16所示，第七晶体管的第一极T73可以为沿第二方向Y延伸的线型状。第七晶体管的第一极T73在基底上的正投影与第六过孔、第十过孔、复位信号线Reset和第二初始信号线INIT2在基底上的正投影至少部分交叠。第七晶体管的第一极通过第六过孔V6与第七晶体管的有源层的第一区连接，且通过第十过孔与第二初始信号线INIT2连接。
在示例性实施方式中，如图15和图16所示，第一扫描信号线Gate1的形状可以为沿着第一方向X延伸的线形状，第一扫描信号线Gate1可以位于第二扫描信号线Gate2靠近第一晶体管的第一极T13的一侧。第一扫描信号线Gate1在基底上的正投影可以与第九过孔和第四晶体管的控制极在基底上的正投影至少部分交叠。第一扫描信号线Gate1通过第九过孔与第四晶体管的控制极连接。
在示例性实施方式中，如图15和图16所示，第二扫描信号线Gate2的形状可以为沿着第一方向X延伸的线形状，第二扫描信号线Gate2可以位于第一扫描信号线Gate1靠近第五晶体管的第一极T53的一侧。第二扫描信号线Gate2在基底上的正投影可以与第七过孔、第二晶体管的控制极的第二电极连接部和第二电容的第二极板的电容主体部在基底上的正投影至少部分交叠。第二扫描信号线Gate2通过第七过孔与第二晶体管的控制极连接。
在示例性实施方式中，第一扫描信号线Gate1和第二扫描信号线Gate2可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(6)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层的第四绝缘层，第三绝缘层上设置有多个过孔，如图17所示，图17为图7提供的显示基板形成第四绝缘层图案后的示意图。
在示例性实施方式中，如图17所示，每个子像素的第四绝缘层的多个过孔至少可以包括：第十二过孔V12、第十三过孔V13、第十四过孔V14和第十五过孔V15。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第一晶体管的第一极在基底上的正投影的范围之内，第十二过孔V12暴露出第一晶体管的第一极的表面，第十二过孔V12被配置为使后续形成的第一初始信号线通过该过孔与第一晶体管的第一极连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第四晶体 管的第一极在基底上的正投影的范围之内，第十三过孔V13暴露出第四晶体管的第一极的表面，第十三过孔V13被配置为使后续形成的数据信号线通过该过孔与第四晶体管的第一极连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影位于第五晶体管的第一极在基底上的正投影的范围之内，第十四过孔V14暴露出第五晶体管的第一极的表面，第十四过孔V14被配置为使后续形成的第一电源线通过该过孔与第五晶体管的第一极连接。
在示例性实施方式中，第十五过孔V15在基底上的正投影位于第六晶体管的第二极(也是第七晶体管的第二极)在基底上的正投影的范围之内，第十五过孔V15暴露出第六晶体管的第二极(也是第七晶体管的第二极)的表面，第十五过孔V15被配置为使后续形成的连接电极通过该过孔与第六晶体管的第二极(也是第七晶体管的第二极)连接。
(7)形成第四导电层图案，在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成第四导电层图案，如图18和图19所示，图18为图7提供的显示基板的第四导电层图案的示意图，图19为图7提供的显示基板形成第四导电层图案后的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图18和图19所示，每个子像素的第四导电层图案至少可以包括：第一初始信号线INIT1、连接电极VL、第一电源线VDD和数据信号线Data。
在示例性实施方式中，如图18和图19所示，连接电极VL可以位于第一初始信号线INIT1远离第一电源线VDD的一侧，第一电源线VDD位于第一初始信号线INIT1和数据信号线Data之间。
在示例性实施方式中，如图18和图19所示，连接电极VL的形状可以为条形状。连接电极VL在基底上的正投影与第十五过孔在基底上的正投影交叠。连接电极VL通过第十五过孔与作为第六晶体管T6的第二极(也是第七晶体管T7的第二极)第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，连接电极VL被配置为与后续形成的阳极连接。
在示例性实施方式中，如图18和图19所示，第一初始信号线INIT1的形状可以为主体部分沿着第二方向Y延伸的线形状。第一初始信号线INIT1在基底上的正投影与第二过孔、第八过孔、第十二过孔和第一晶体管的第二极(也是第二晶体管的第一极)在基底上的正投影至少部分交叠。第一初始信号线INIT1通过第十二过孔与第一晶体管的第一极连接。第一初始信号线在基底上的正投影与第八过孔在基底上的正投影至少部分交叠，可以防止其他信号对于第一节点的干扰，可以有效地提升第一节点的稳定性。第一初始信号线在基底上的正投影与第十二过孔在基底上正投影部分交叠，可以使得位于第一晶体管的控制极之间的第一晶体管的有源层被第一初始信号线遮挡屏蔽，可以有效地防止漏电，从而改善了显示基板的信赖性。
在示例性实施方式中，如图18和图19所示，第一初始信号线位于第四导电层，且主体部分沿第二方向延伸，由于第一初始信号线的信号是通过位于绑定区域的芯片给入到显示区域的，因此，主体部分沿第二方向延伸的第一初始信号线是设计上最短的路径，第一初始信号线可以直接从下方给入，可以更有利于加快第一节点的初始化。
在示例性实施方式中，如图18和图19所示，第一电源线VDD的主体部分的形状可以为沿着第二方向Y延伸的线形状，第一电源线VDD在基底上的正投影与第九过孔、第十四过孔、第四晶体管的控制极、第一电容的第二极板和第二电容的第二极板的电容主体部在基底上的正投影交叠。第一电源线VDD通过第十四过孔与第五晶体管的第一极连接，实现了将电源信号写入了第五晶体管的第一极，第五晶体管的第一极与第一电容的第二极板和第二电容的第二极板连接，因此，第五晶体管的第一极、第一电容的第二极板和第二电容的第二极板具有相同的电位。
在示例性实施方式中，如图18和图19所示，第一电源线VDD在基底上的正投影位于第八过孔在基底上的正投影与数据信号线Data在基底上的正投影之间，使得第一电源线VDD对第一节点和数据信号线Data之间进行屏蔽间隔，有效地预防了数据信号线Data的跳变对第一节点的影响，从而防止了信号串扰的发生，提升了显示基板的可靠性。
在示例性实施方式中，如图18和图19所示，数据信号线Data的形状可 以为主体部分沿着第二方向Y延伸的线形状，数据信号线Data在基底上的正投影与第十三过孔、第二电容的第二极板的电容主体部以及第四晶体管的控制极在基底上的正投影至少部分交叠。数据信号线Data通过第十三过孔与第四晶体管的第一极连接。
在示例性实施方式中，如图18和图19所示，数据信号线Data位于第四导电层，可以减小数据信号线Data和其下方导电膜层之间的寄生电容，从而减小数据信号线Data上的负载，有利于节省充电时间和节省功耗。
在示例性实施方式中，第一初始信号线INIT1、数据信号线Data和第一电源线VDD可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。示例性地，第一电源线VDD的宽度可以大于数据信号线Data的宽度，且大于第一初始信号线INIT1的宽度，第一初始信号线INIT1的宽度可以大于数据信号线Data的宽度。
(8)形成平坦层图案。在示例性实施方式中，形成平坦层图案可以包括：在形成前述图案的基底上，涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第四导电层图案的平坦层。
至此，在基底上制备完成图7提供的显示基板的驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个像素电路，驱动电路层还包括：第一扫描信号线、第二扫描信号线、发光信号线、第一初始信号线、第二初始信号线、数据信号线和第一电源线连接。在垂直于显示基板的平面内，驱动电路层可以设置在基底上，基底可以包括叠设的第一柔性层、阻挡层、基底导电层和第二柔性层。
驱动电路层可以包括在基底上依次设置的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层和平坦层。半导体层可以至少包括第一晶体管至第七晶体管的有源层以及第二电容的第一极板，第一导电层可以至少包括复位信号线、发光信号线、第一晶体管至第七晶体管的控制极和第一电容的第一极板，第二导电层可以至少包括第一电容的第二极板、第二电容的第二极板和第二初始信号线，第三导电层可以至少包括第一扫描信号线和第二扫描信号线，第四导 电层可以至少包括：第一初始信号线、数据信号线、第一电源线和连接电极。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层和第三绝缘层可以称为栅绝缘(GI)层，第四绝缘层可以称为层间绝缘(ILD)层，第五绝缘层可以称为钝化(PVX)层。平坦层可以采用有机材料，如树脂等。
下面以一行两列像素电路说明图8提供的显示基板的制备过程。一种示例性实施例提供的显示基板的制备过程可以包括：
(1)在基底上形成遮挡层图案。在示例性实施方式中，形成遮挡层图案可以包括：在基底上依次沉积遮挡导电薄膜，通过图案化工艺对遮挡导电薄膜进行图案化，形成遮挡层图案，如图20所示，图20为图8提供的显示基板形成遮挡层图案后的示意图。
在示例性实施方式中，如图20所示，每个子像素的遮挡层图案至少可以包括第一遮挡结构11、第二遮挡结构12、第一遮挡连接结构13、第二遮挡连接结构14、第三遮挡连接结构15、第四遮挡连接结构16和第二电容的第一极板C21。其中，第二遮挡结构12也是第二电容的第一极板C21。
在示例性实施方式中，遮挡层被配置为传输高压电源信号。
在示例性实施例方式中，如图20所示，对于同一子像素，第一遮挡连接结构13和第二遮挡结构12分别位于第一遮挡结构11相对设置的两侧，且与第一遮挡结构11连接。第二遮挡连接结构14位于第二遮挡结构12(也是第二电容的第一极板C21)远离第一遮挡结构11的一侧，且与第二遮挡结构12(也是第二电容的第一极板C21)连接。第三遮挡连接结构15和第四遮挡连接结构16分别位于第一遮挡结构11相对设置的另外两侧，且第三遮挡连 接结构15与第二遮挡结构12(也是第二电容的第一极板C21)连接，第四遮挡连接结构16与第一遮挡结构11连接。
在示例性实施例方式中，如图20所示，位于同一行的第N列子像素的第二遮挡结构12(也是第二电容的第一极板C21)位于本子像素的第一遮挡结构11靠近第N+1列子像素的第一遮挡结构11的一侧、位于同一行的第N列子像素的第一遮挡连接结构13位于本子像素的第一遮挡结构11靠近第N-1列子像素的第一遮挡结构11的一侧，且与第N-1列子像素的第四遮挡连接结构14连接。位于同一行的第N列子像素的第二遮挡连接结构14与第N+1列子像素的第一遮挡连接结构13连接。
在示例性实施例方式中，如图20所示，位于同一列的第M行子像素的第三遮挡连接结构15位于本子像素的第一遮挡结构11靠近第M-1行子像素的第一遮挡结构11的一侧，且与第M-1行子像素的第四遮挡连接结构16连接。位于同一列的第M行子像素的第四遮挡连接结构16位于本子像素的第一遮挡结构11靠近第M+1行子像素的第一遮挡结构11的一侧，且与第M+1行子像素的第五遮挡连接结构15连接。
在示例性实施例方式中，如图20所示，沿第二方向Y延伸的虚拟直线穿过第三遮挡连接结构15和第四遮挡连接结构16。
在示例性实施方式中，如图20所示，第一遮挡结构11的形状可以为矩形，矩形状的角部可以设置倒角。第二遮挡结构12的形状可以为沿第二方向Y延伸的线形状。第一遮挡连接结构13的形状和第二遮挡连接结构14的形状可以为沿第一方向X延伸的线形状。第三遮挡连接结构15的主体的形状可以为沿第二方向Y延伸的折线状。第四遮挡连接结构16的形状可以为沿第二方向Y延伸的线形状。
在示例性实施方式中，如图20所示，第一遮挡结构11沿第一方向X的长度大于第二遮挡结构12沿第一方向X的长度，第一遮挡结构11沿第二方向Y的长度小于第二遮挡结构12沿第二方向Y的长度。
在示例性实施方式中，多个子像素中的遮挡层的形状可以相同。
在示例性实施方式中，所有子像素的遮挡层连接成一体，且呈网状，可 以保证显示基板中的遮挡层具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
(2)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在形成前述图案的基底上，沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖遮挡层图案的第一绝缘层，以及位于第一绝缘层上的半导体层图案，如图21和图22所示，图21为图8提供的显示基板的半导体层图案的示意图，图22为图8提供的显示基板形成半导体层图案后的示意图。
在示例性实施方式中，如图21和图22所示，每个子像素的半导体层图案至少可以包括：第一晶体管的有源层T11至第八晶体管的有源层T81。
在示例性实施方式中，如图21和图22所示，第一晶体管的有源层T11至第八晶体管的有源层T81为相互连接的一体结构。
在示例性实施方式中，如图21和图22所示，在第一方向X上，第二晶体管的有源层T21和第六晶体管的有源层T61可以位于本子像素中第三晶体管的有源层T31的同一侧，第四晶体管的有源层T41和第五晶体管的有源层T51可以位于本子像素中第三晶体管的有源层T31的同一侧，第二晶体管的有源层T21和第四晶体管的有源层T41可以位于本子像素的第三晶体管的有源层T31的不同侧。在第二方向Y上，第一晶体管的有源层T11、第二晶体管的有源层T21、第四晶体管的有源层T41和第八晶体管的有源层T81可以位于本子像素中第三晶体管的有源层T31的同一侧，第五晶体管的有源层T51、第六晶体管的有源层T61和第七晶体管的有源层T71可以位于本子像素中第三晶体管的有源层T31的另一侧。
在示例性实施方式中，如图21和图22所示，第一晶体管的有源层T11的形状可以呈“T”字形，第二晶体管的有源层T21的形状可以呈水平翻转“7”字形，第三晶体管的有源层T31的形状可以呈“Ω”字形，第四晶体管的有源层T41、第五晶体管的有源层T51、第六晶体管的有源层T61和第八晶体管的有源层T81的形状可以呈“I”字形，第七晶体管的有源层T71的形状可以成“⊥”。
在示例性实施方式中，如图21和图22所示，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一晶体管的有源层T11的第二区T11_2可以作为第八晶体管的有源层T81的第一区T81_1，第八晶体管的有源层T81的第二区T81_2可以作为第二晶体管的有源层T21的第一区T21_1，第三晶体管的有源层T31的第一区T31_1可以同时作为第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2，第三晶体管的有源层T31的第二区T31_2可以同时作为第二晶体管的有源层T21的第二区T21_2和第六晶体管的有源层T61的第一区T61_1，第六晶体管的有源层T61的第二区T61_2可以作为第七晶体管的有源层T71的第二区T71_2，第一晶体管的有源层T11的第一区T11_1、第四晶体管的有源层T41的第一区T41_1、第五晶体管的有源层T51_1的第一区T51_1和第七晶体管的有源层T71的第一区T71_1可以单独设置。
在示例性实施方式中，如图21和图22所示，第一晶体管的有源层T11的第一区T11_1包括：沿第一方向X延伸的第一连接部T11_1A和沿第二方向Y延伸的第二连接部T11_1B。
在示例性实施方式中，如图21和图22所示，位于同一行的相邻子像素的第一晶体管的有源层T11的第一区T11_1相互连接。其中，位于同一行的相邻子像素的第一晶体管的有源层T11的第一区T11_1的第一连接部T11_1A相互连接。
在示例性实施方式中，如图21和图22所示，第七晶体管的有源层T71的第一区T71_1包括：沿第一方向X延伸的第三连接部T71_1A和沿第二方向Y延伸的第四连接部T71_1B。
在示例性实施方式中，如图21和图22所示，位于同一行的相邻子像素的第七晶体管的有源层T71的第一区T71_1相互连接。其中，位于同一行的相邻子像素的第七晶体管的有源层T71的第一区T71_1的第三连接部T71_1A相互连接。
在示例性实施方式中，如图21和图22所示，第一遮挡结构在基底上的正投影与第三晶体管的有源层T31的沟道区在基底上的正投影至少部分交叠， 第二遮挡结构在基底上的正投影与第三晶体管的有源层T31的第一区T31_1(第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2)在基底上的正投影至少部分交叠。第三遮挡连接结构在基底上的正投影与第一晶体管的有源层T11的第一区T11_1在基底上的正投影至少部分交叠。第四遮挡连接结构在基底上的正投影与第七晶体管的有源层T71的第一区T71_1基底上的正投影至少部分交叠。
本公开中，第一遮挡结构在基底上的正投影与第三晶体管的有源层T31的沟道区在基底上的正投影至少部分交叠，可以提升第三晶体管即驱动晶体管的性能，进而提升显示基板的可靠性。
(3)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及位于第二绝缘层上的第一导电层图案，如图23和图24所示，其中，图23为图8提供的显示基板的第一导电层图案的示意图，图24为图8提供的显示基板形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，每个子像素的第一导电层图案至少可以包括：发光信号线EM、第一晶体管的控制极T12至第八晶体管的控制极T82、第一电容的第一极板C11。
在示例性实施方式中，如图23和图24所示，第一电容的第一极板C11的形状可以为矩形状，且矩形状的角部可以设置倒角，第一电容的第一极板C11在基底上的正投影与第三晶体管T3的有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一电容的第一极板C11可以同时作为第三晶体管T3的控制极T32。
在示例性实施方式中，如图23和图24所示，发光信号线EM的形状可以为沿着第一方向X延伸的线形状，发光信号线EM与第五晶体管T5的有源层相重叠的区域作为第五晶体管T5的控制极T52，发光信号线EM与第六晶体管T6的有源层相重叠的区域作为第六晶体管T6的控制极T62。
在示例性实施方式中，如图23和图24所示，第一晶体管T1的控制极 T12、第二晶体管T2的控制极T22、第四晶体管T4的控制极T42、第八晶体管T8的控制极T82可以位于第一电容的第一极板C11远离发光信号线EM的一侧，第四晶体管T4的控制极T42和第八晶体管T8的控制极T82位于第二晶体管T2的控制极T22远离第一电容的第一极板C11的一侧，第一晶体管T1的控制极T12位于第四晶体管T4的控制极T42和第八晶体管T8的控制极T82远离第一电容的第一极板C11的一侧。第七晶体管T72的控制极位于发光信号线EM远离第一电容的第一极板C11的一侧。
在示例性实施方式中，如图23和图24所示，第一晶体管的控制极T12和第七晶体管的控制极T72的形状可以为沿着第一方向X延伸的线形状。
在示例性实施方式中，如图23和图24所示，第四晶体管的控制极T42可以同时作为第八晶体管的控制极T82。第四晶体管的控制极T42(也是第八晶体管的控制极T82)的形状可以为沿着第一方向X延伸的线形状。
在示例性实施方式中，如图23和图24所示，第二晶体管的控制极T22可以包括沿第一方向X延伸的第一电极连接部T22A和沿第二方向Y延伸的第二电极连接部T22B，第一电极连接部T22A和第二电极连接部T22B在基底上的正投影与第二晶体管的有源层在基底上的正投影部分交叠，因此，第二晶体管的控制极T22与第二晶体管的有源层T21相重叠的区域有两个，也就是说，第二晶体管的控制极T22有两个，第二晶体管为双栅结构。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第八晶体管T8的沟道区，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管的有源层至第八晶体管的有源层的第一区和第二区均被导体化。导体化后的第一晶体管的有源层T11的第一区T11_1可以同时作为第一晶体管的第一极T13和第一初始信号线INIT1，导体化后的第一晶体管的有源层T11的第二区T11_2(也是第八晶体管的有源层T81的第一区T81_1)可以同时作为第一晶体管的第二极T14和第八晶体管的第一极T83，导体化后的第三晶体管的有源层T31的第一区T31_1(也是第四晶体管的有源层T41的第二区T41_2和第五晶体管的有源层T51的第二区T51_2)可以同时作为第三晶体管的第一极T33、第四晶体管的第二极T44、 第五晶体管的第二极T54和第二电容的第二极板C22，导体化后的第三晶体管的有源层T31的第二区T31_2(也是第二晶体管的有源层T21的第二区T21_2和第六晶体管的有源层T61的第一区T61_1)也是同时作为第二晶体管的第二极T24、第三晶体管的第二极T34和第六晶体管的第一极T63，导体化后的第七晶体管的有源层T71的第一区T71_1可以同时作为第七晶体管的第一极T73和第二初始信号线INIT2。
在示例性实施方式中，第一初始信号线INIT1、第二初始信号线INIT2和发光信号线EM可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(4)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第三绝缘层薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，在第三绝缘层上形成第二导电层图案。图25和图26所示，图25为图8提供的显示基板的第二导电层图案的示意图，图26为图8提供的显示基板形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图25和图26所示，每个子像素的第二导电层图案至少包括：第一电容的第二极板C12、第二电容的第三极板C23和屏蔽电极21。
在示例性实施方式中，如图25和图26所示，对于同一子像素，第一电容的第二极板C12和第二电容的第三极板C23相互连接，屏蔽电极21单独设置。
在示例性实施方式中，如图25和图26所示，对于同一行的子像素，第N列子像素的第二电容的第三极板C23位于第N列子像素的第一电容的第二极板C12靠近第N+1列子像素的第一电容的第二极板C12，且与第N+1列子像素的第一电容的第二极板C12连接。在第N列子像素的第二电容的第三极板C23与第N+1列子像素的第一电容的第二极板C12连接可使得沿第一方向X排布的相邻子像素的第一电容的第二极板C12和第二电容的第三极板C23流经的信号相同，可以提升显示基板显示的均一性。
在示例性实施方式中，第二电容包括：位于遮挡层的第一极板、位于半导体层的第二极板和位于第二导电层的第三极板，其中，第一极板和第三极板均传输高压电源信号。本公开通过设置第二电容包括：位于遮挡层的第一极板、位于半导体层的第二极板和位于第二导电层的第三极板可以使得第二电容可以存储的电荷较多，提升第二第二电容的充电性能，可以延长像素电路中的第一节点的充电时间，提升了显示基板的性能，有利于实现高刷新率。
在示例性实施方式中，如图25和图26所示，第一电容的第二极板C12可以包括：相互连接的电容主体部C12A和连接部C12B。连接部C12B和第二电容的第三极板C23分别位于电容主体部C12A相对设置的两侧，且分别与电容主体部C12A连接。第N+1列子像素的连接部C12B与第N列子像素的第二电容的第三极板C23连接。
在示例性实施方式中，如图25和图26所示，电容主体部C12A的形状可以为矩形状，且矩形状的角部可以设置倒角，电容主体部C12A在基底上的正投影与第一电容的第一极板在基底上的正投影至少部分交叠。电容主体部C12A上设置有开口V0，开口V0的形状可以为矩形状，可以位于电容主体部C12A的中部，使电容主体部C12A形成环形结构。开口V0暴露出覆盖第一电容的第一极板的第三绝缘层，且第一电容的第一极板在基底上的正投影包含开口V0在基底上的正投影。
在示例性实施方式中，如图25和图26所示，连接部C12B的形状可以为沿第一方向X延伸的线形状。
在示例性实施方式中，如图25和图26所示，第二电容的第三极板C23的形状可以为沿第二方向X延伸的折线状。第二电容的第三极板C23在基底上的正投影与第二电容的第二极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图25和图26所示，第一电容的第二极板C12沿第二方向Y的长度小于第二电容的第三极板C23沿第二方向Y的长度。
在示例性实施方式中，如图25和图26所示，对于同一列的子像素，第M+1行子像素的屏蔽电极21位于第M+1行子像素的第一电容的第二极板C12靠近第M行子像素的第一电容的第二极板C12的一侧。对于同一行的子像素，第N+1列子像素的屏蔽电极21与第N列子像素的第二电容的第三极 板C23电连接。
在示例性实施方式中，如图25和图26所示，屏蔽电极21的形状可以为块状。屏蔽电极21在基底上的正投影与位于第二晶体管的控制极之间的第二晶体管的有源层在基底上的正投影至少部分交叠。屏蔽电极21在基底上的正投影与位于第二晶体管的控制极之间的第二晶体管的有源层在基底上的正投影至少部分交叠可以使得位于第二晶体管的控制极之间的第二晶体管的有源层被屏蔽电极遮挡屏蔽，可以有效地防止漏电，从而改善了显示基板的信赖性。
(5)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图27所示，图27为图8提供的显示基板形成第四绝缘层图案后的示意图。
在示例性实施方式中，如图27所示，每个子像素的第四绝缘层的多个过孔至少可以包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第二晶体管的有源层T21的第一区(也是第八晶体管的有源层的第二区)在基底上的正投影的范围之内，第一过孔V1内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第二晶体管的有源层的第一区(也是第八晶体管的有源层的第二区)的表面，第一过孔V1被配置为使后续形成的第二晶体管的第一极(也是第八晶体管的第二极)通过该过孔与第二晶体管的有源层的第一区(也是第八晶体管的有源层的第二区)连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第四晶体管的有源层的第一区在基底上的正投影的范围之内，第二过孔V2内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第二过孔V2被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五晶体管 的有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第五晶体管的有源层的第一区的表面，第三过孔V3被配置为使后续形成的第五晶体管的第一极通过该过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)的表面，第五过孔V5被配置为使后续形成的第六晶体管的第二极(也是第七晶体管的第二极)通过该过孔与第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第一晶体管的控制极在基底上的正投影的范围之内，第五过孔V5内的第三绝缘层被刻蚀掉，暴露出第一晶体管的控制极的表面，第五过孔V5被配置为使后续形成的其中一条复位信号线通过该过孔与第一晶体管的控制极连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第二晶体管的控制极在基底上的正投影的范围之内，第六过孔V6内的第三绝缘层被刻蚀掉，暴露出第二晶体管的控制极的表面，第六过孔V6被配置为使后续形成的第一扫描信号线通过该过孔与第二晶体管的控制极连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于开口在基底上的正投影的范围之内，第七过孔V7内的第三绝缘层被刻蚀掉，暴露出第一电容的第一极板(也是第三晶体管的控制极)的表面，第七过孔V7被配置为使后续形成的第二晶体管的第一极(也是第八晶体管的第二极)通过该过孔与第一电容的第一极板(也是第三晶体管的控制极)连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第四晶体管的控制极(也是第八晶体管的控制极)在基底上的正投影的范围之内，第八过孔V8内的第三绝缘层被刻蚀掉，暴露出第四晶体管的控制极(也是第八晶体管的控制极)的表面，第八过孔V8被配置为使后续形成的第二扫描信号线通过该过孔与第四晶体管的控制极(也是第八晶体管的控制极)连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第七晶体管的控制极在基底上的正投影的范围之内，第九过孔V9内的第三绝缘层被刻蚀掉，暴露出第七晶体管的控制极的表面，第九过孔V9被配置为使后续形成的另一条复位信号线通过该过孔与第七晶体管的控制极连接。
(6)形成第三导电层。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，图28和图29所示，图28为图8提供的显示基板的第三导电层图案的示意图，图29为图8提供的显示基板形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图28和图29所示，每个子像素的第三导电层图案至少可以包括：两条复位信号线Reset、第一扫描信号线Gate1和第二扫描信号线Gate2、第二晶体管的第一极T23、第四晶体管的第一极T43、第五晶体管的第一极T53、第六晶体管的第二极T64、第七晶体管的第二极T74和第八晶体管的第二极T84。其中，第二晶体管的第一极T23可以同时作为第八晶体管的第二极T84、第六晶体管的第二极T64可以同时作为第七晶体管的第二极T74，第四晶体管的第一极T43和第五晶体管的第一极T53可以单独设置。
在示例性实施方式中，如图28和图29所示，第四晶体管的第一极T43可以位于其中一条复位信号线Reset和第一扫描信号线Gate1之间。第二晶体管的第一极T23(也是第八晶体管的第二极T84)、第五晶体管的第一极T53和第六晶体管的第二极T64(也是第七晶体管的第二极T74)可以位于第二扫描信号线Gate2和另一条复位信号线Reset之间，其中，第二晶体管的第一极T23(也是第八晶体管的第二极T84)可以位于第五晶体管的第一极T53靠近第二扫描信号线Gate2的一侧，第六晶体管的第二极T64(也是第七晶体管的第二极T74)可以位于第五晶体管的第一极T53远离第二扫描信号线Gate2的一侧。第一扫描信号线Gate1和第二扫描信号线Gate2位于两条复位信号线Reset之间，且第一扫描信号线Gate1位于第二扫描信号线Gate2靠近第四晶体管的第一极T43的一侧。
在示例性实施方式中，如图28和图29所示，靠近第一扫描信号线Gate1的复位信号线Reset可以包括：沿第一方向X延伸的信号主体部22和沿第二方向Y延伸的信号连接块23。信号连接块23位于信号主体部22靠近第一扫描信号线Gate1的一侧。信号连接块23在基底上的正投影与第五过孔在基底上的正投影部分交叠。靠近第一扫描信号线的复位信号线Reset通过第五过孔与第一晶体管的控制极连接。
在示例性实施方式中，如图28和图29所示，靠近第二扫描信号线Gate2的复位信号线Reset的形状可以为沿第一方向X延伸的线形状。靠近第二扫描信号线Gate2的复位信号线Reset在基底上的正投影与第九过孔在基底上的正投影部分交叠。靠近第二扫描信号线Gate2的复位信号线Reset通过第九过孔与第七晶体管的控制极连接。
在示例性实施方式中，如图28和图29所示，第一扫描信号线Gate1的主体部分的形状可以为沿第一方向X延伸的线形状。第一扫描信号线Gate1在基底上的正投影与第八过孔在基底上的正投影部分交叠。第一扫描信号线Gate1通过第八过孔与第四晶体管的控制极(也是第八晶体管的控制极)连接。
在示例性实施方式中，如图28和图29所示，第二扫描信号线Gate2的主体部分的形状可以为沿第一方向X延伸的线形状。第二扫描信号线Gate2在基底上的正投影与第六过孔在基底上的正投影部分交叠。第二扫描信号线Gate2通过第六过孔与第二晶体管的控制极连接。
在示例性实施方式中，如图28和图29所示，第二晶体管的第一极T23(也是第八晶体管的第二极T84)的形状可以为沿第二方向Y延伸的线形状。第二晶体管的第一极T23(也是第八晶体管的第二极T84)在基底上的正投影与第一过孔和第七过孔在基底上的正投影至少部分交叠。第二晶体管的第一极T23(也是第八晶体管的第二极T84)通过第一过孔与第二晶体管的有源层的第一区(也是第八晶体管的有源层的第二区)连接，且通过第七过孔与第一电容的第一极板(也是第三晶体管的控制极)连接。
在示例性实施方式中，如图28和图29所示，第四晶体管的第一极T43的形状可以块状。第四晶体管的第一极T43在基底上的正投影与第二过孔在 基底上的正投影至少部分交叠。第四晶体管的第一极通过第二过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，如图28和图29所示，第五晶体管的第一极T53的形状可以为边界不规则的“T型”。第五晶体管的第一极T53在基底上的正投影可以与第三过孔、发光信号线、第一电容的第二极板和第二电容的第三极板在基底上的正投影部分交叠。第五晶体管的第一极T53通过第三过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，如图28和图29所示，位于同一行的相邻子像素的第五晶体管的第一极T53相互连接。
在示例性实施方式中，如图28和图29所示，第六晶体管的第二极T64(第七晶体管的第二极T74)可以为块状结构。第六晶体管的第二极T64(第七晶体管的第二极T74)在基底上的正投影可以与第四过孔和发光信号线在基底上的正投影部分交叠。第六晶体管的第二极T64(第七晶体管的第二极T74)通过第四过孔与第六晶体管的有源层的第二区(也是第七晶体管的有源层的第二区)连接。
在示例性实施方式中，两条复位信号线Reset、第一扫描信号线Gate1和第二扫描信号线Gate2可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(7)形成第五绝缘层图案。在示例性实施方式中，形成第五绝缘层图案可以包括：在形成前述图案的基底上，沉积第五绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第三导电层的第五绝缘层，第五绝缘层上设置有多个过孔，如图30所示，图30为图8提供的显示基板形成第五绝缘层图案后的示意图。
在示例性实施方式中，如图30所示，每个子像素的第五绝缘层的多个过孔至少包括：第十过孔V10、第十一过孔V11和第十二过孔V12。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第四晶体管的第一极在基底上的正投影的范围之内，第十过孔V10暴露出第四晶体管的第一极的表面，第十过孔V10被配置为使后续形成的数据信号线通过该过孔 与第四晶体管的第一极连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第五晶体管的第一极在基底上的正投影的范围之内，第十四过孔V14暴露出第五晶体管的第一极的表面，第十一过孔V11被配置为使后续形成的第一电源线通过该过孔与第五晶体管的第一极连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第二电容的第三极板在基底上的正投影的范围之内，第十二过孔V12内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二电容的第三极板的表面。第十二过孔V12被配置为使后续形成的第一电源线通过该过孔与第二电容的第三极板连接。
(8)形成第四导电层图案，在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成第四导电层图案，如图31和图32所示，图31为图8提供的显示基板的第四导电层图案的示意图，图32为图8提供的显示基板形成第四导电层图案后的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图31和图32所示，每个子像素的第四导电层图案至少可以包括：第一电源线VDD和数据信号线Data。
在示例性实施方式中，如图31和图32所示，第一电源线VDD的主体部分的形状可以为沿着第二方向Y延伸的线形状，第一电源线VDD在基底上的正投影与第十一过孔和第十二过孔在基底上的正投影交叠。第一电源线VDD通过第十一过孔与第五晶体管的第一极连接，且通过第十二过孔与第二电容的第三极板连接，实现了将电源信号写入了第五晶体管的第一极和第二电容的第三极板，由于第一电容的第二极板和第二电容的第三极板连接，因此，第五晶体管的第一极、第一电容的第二极板和第二电容的第三极板传输的信号均为高压电源信号，具有相同的电位。
在示例性实施方式中，如图31和图32所示，数据信号线Data的形状可以为主体部分沿着第二方向Y延伸的线形状，数据信号线Data在基底上的正投影与第十过孔和第二电容的第三极板的电容主体部在基底上的正投影至少部分交叠。数据信号线Data通过第十过孔与第四晶体管的第一极连接。数 据信号线Data位于第四导电层，可以减小数据信号线Data和其下方导电膜层之间的寄生电容，从而减小数据信号线Data上的负载，有利于节省充电时间和节省功耗。
在示例性实施方式中，数据信号线Data和第一电源线VDD可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。示例性地，第一电源线VDD的宽度可以大于数据信号线Data的宽度。
(9)形成平坦层图案。在示例性实施方式中，形成平坦层图案可以包括：在形成前述图案的基底上，涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第四导电层图案的平坦层。
至此，在基底上制备完成图8提供的显示基板的驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个像素电路，驱动电路层还包括：第一扫描信号线、第二扫描信号线、发光信号线、第一初始信号线、第二初始信号线、数据信号线和第一电源线连接。在垂直于显示基板的平面内，驱动电路层可以设置在基底上，基底可以包括叠设的第一柔性层、阻挡层、基底导电层和第二柔性层。
驱动电路层可以包括在基底上依次设置的遮挡层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层、第四导电层和平坦层。遮挡层可以包括：第二电容的第一极板，半导体层可以至少包括第一晶体管至第八晶体管的有源层、第二电容的第二极板、第一初始信号线和第二初始信号线，第一导电层可以至少包括发光信号线、第一晶体管至第七晶体管的控制极和第一电容的第一极板，第二导电层可以至少包括第一电容的第二极板、第二电容的第三极板，第三导电层可以至少包括第一扫描信号线、第二扫描信号线和复位信号线，第四导电层可以至少包括：数据信号线和第一电源线。
在示例性实施方式中，遮挡层、第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌 合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层和第三绝缘层可以称为栅绝缘(GI)层，第四绝缘层可以称为层间绝缘(ILD)层，第五绝缘层可以称为钝化(PVX)层。平坦层可以采用有
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(10)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层，阳极导电层至少包括多个阳极图案。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
(11)形成像素定义层图案。在示例性实施方式中，形成像素定义层图案可以包括：在形成前述图案的基底上，涂覆像素定义薄膜，采用图案化工艺对像素定义薄膜进行图案化，形成像素定义层，每个子像素的像素定义层上设置有像素开口，像素开口内的像素定义薄膜被去掉，暴露出所在子像素的阳极。
在示例性实施方式中，后续制备流程可以包括：先采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
本公开实施例还提供了一种像素电路的驱动方法，设置驱动像素电路，本公开实施例提供的像素电路的驱动方法可以包括以下步骤：
步骤100、节点控制子电路在复位信号线、第一扫描信号线和第二扫描信号线的控制下，向第一节点提供第一初始信号线或者第三节点的信号，向第四节点提供第二初始信号线的信号，向第二节点提供数据信号线的信号。
步骤200、存储子电路在第一扫描信号线为有效电平信号时，对第二节点进行充电。
步骤300、驱动子电路第一节点和第二节点的控制下，向第三节点提供驱动电流，发光控制子电路在发光信号线的控制下，向第二节点提供第一电源线的信号，并向第四节点提供第三节点的信号。
本公开实施例还提供了一种显示装置，包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在示例性实施方式中，显示装置还包括：栅极驱动电路。栅极驱动电路包括：K+2个级联的移位寄存器GOA，K为像素电路的总行数。栅极驱动电路可以位于显示装置的非显示区域。
在示例性实施方式中，图33为一种栅极驱动电路的连接示意图。如图33所示，第一级移位寄存器GOA(1)与第一行像素电路R(1)所连接的复位信号线Reset连接，第二级移位寄存器GOA(2)分别与第一行像素电路R(1)所连接的第一扫描信号线Gate1和第二行像素电路R(2)所连接的复位信号线Reset连接，第i级移位寄存器GOA(i)分别与第i-2行像素电路R(i-2)所连接的第二扫描信号线Gate2、第i-1行像素电路R(i-1)所连接的第一扫描信号线线Gate1和第i行像素电路R(i)所连接的复位信号线Reset连接，第K+1级移位寄存器GOA(K+1)分别与第K-1行像素电路R(K-1)所连接的第二扫描信号线Gate2和第K行像素电路R(K)所连接的第一扫描信号线线Gate1连接，第K+2级移位寄存器GOA(K+2)分别与第K行像素电路R(K)的所连接的第二扫描信号线Gate2连接，i＝3,4,…,K。 图33仅示出7个级联的移位寄存器，并不意味着栅极驱动电路仅包括7个级联的移位寄存器。
本公开通过栅极驱动电路与复位信号线、第一扫描信号线和第二扫描信号线均连接，可以减少位于非显示区域的电路所占用的面积，可以实现窄边框，且本公开通过像素电路、显示基板的结构以及栅极驱动电路的驱动模式，通过以上像素电路和像素Layout设计结合GOA的驱动模式，可以有效的实现高频甚至超高频的显示。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (22)

  1. 一种像素电路，被配置为驱动发光器件发光，包括：节点控制子电路，存储子电路、驱动子电路和发光控制子电路；
    节点控制子电路，分别与第一节点、第二节点、第三节点、第四节点、第一扫描信号线、第二扫描信号线、第一初始信号线、第二初始信号线、复位信号线、数据信号线和第一电源线电连接，被配置为在复位信号线、第一扫描信号线和第二扫描信号线的控制下，向第一节点提供第一初始信号线或者第三节点的信号，向第四节点提供第二初始信号线的信号，向第二节点提供数据信号线的信号；
    存储子电路，分别与第二节点和第一电源线电连接，被配置为在第一扫描信号线为有效电平信号时，对第二节点进行充电；
    驱动子电路，分别与第一节点、第二节点和第三节点电连接，被配置为第一节点和第二节点的控制下，向第三节点提供驱动电流；
    发光控制子电路，分别与发光信号线、第一电源线、第二节点、第三节点和第四节点电连接，被配置为在发光信号线的控制下，向第二节点提供第一电源线的信号，并向第四节点提供第三节点的信号；
    发光器件的第一极与第四节点连接，发光器件的第二极与第二电源线连接。
  2. 根据权利要求1所述的像素电路，其中，复位信号线的信号为有效电平信号的时间段包括第一时间段和第二时间段，第一时间段发生在第二时间段之前；第一扫描信号线的信号为有效电平信号的时间段包括第三时间段和第四时间段，第三时间段发生在第四时间段之前；第二扫描信号线的信号为有效电平信号的时间段包括第五时间段和第六时间段，第五时间段发生在第六时间段之前，所述第二时间段和所述第三时间段至少部分交叠，所述第四时间段和所述第五时间段至少部分交叠；
    复位信号线、第一扫描信号线和第二扫描信号线的信号为有效电平信号时，发光信号线的信号为无效电平信号，发光信号线的信号为有效电平信号时，复位信号线、第一扫描信号线和第二扫描信号线的信号为无效电平信号。
  3. 根据权利要求1所述的像素电路，其中，所述节点控制子电路包括：复位子电路、写入子电路、补偿子电路和储能子电路；
    所述复位子电路，分别与复位信号线、第一初始信号线、第二初始信号线、第一节点和第四节点电连接，被配置为在复位信号线的控制下，向第一节点提供第一初始信号线的信号，向第四节点提供第二初始信号线的信号；
    所述写入子电路，分别与第一扫描信号线、数据信号线和第二节点电连接，被配置为在第一扫描信号线的控制下，向第二节点提供数据信号线的信号；
    所述补偿子电路，分别与第二扫描信号线、第一节点和第三节点电连接，被配置为在第二扫描信号线的控制下，向第一节点提供第三节点的信号；
    所述储能子电路，分别与第一节点和第一电源线电连接，被配置为存储第一节点和第一电源线之间的信号的电压差。
  4. 根据权利要求3所述的像素电路，其中，所述复位子电路还与第一扫描信号线连接，被配置为在复位信号线和第一扫描信号线的控制下，向第一节点提供第一初始信号线的信号，向第四节点提供第二初始信号线的信号。
  5. 根据权利要求3所述的像素电路，其中，所述复位子电路包括第一晶体管和第七晶体管，所述写入子电路包括第四晶体管，所述补偿子电路包括：第二晶体管，所述储能子电路包括：第一电容；
    第一晶体管的控制极与复位信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第二扫描信号线电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第三节点电连接；
    第四晶体管的控制极与第一扫描信号线电连接，第四晶体管的第一极与数据信号线电连接，第四晶体管的第二极与第二节点电连接；
    第七晶体管的控制极与复位信号线电连接，第七晶体管的第一极与第二初始信号线电连接，第七晶体管的第二极与第四节点电连接；
    第一电容的一端与第一电源线电连接，第一电容的另一端与第一节点电连接。
  6. 根据权利要求4所述的像素电路，其中，所述复位子电路包括第一晶体管、第七晶体管和第八晶体管，所述写入子电路包括第四晶体管，所述补偿子电路包括：第二晶体管，所述储能子电路包括：第一电容；
    第一晶体管的控制极与复位信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第八晶体管的第一极电连接；
    第二晶体管的控制极与第二扫描信号线电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第三节点电连接；
    第四晶体管的控制极与第一扫描信号线电连接，第四晶体管的第一极与数据信号线电连接，第四晶体管的第二极与第二节点电连接；
    第七晶体管的控制极与复位信号线电连接，第七晶体管的第一极与第二初始信号线电连接，第七晶体管的第二极与第四节点电连接；
    第八晶体管的控制极与第一扫描信号线电连接，第八晶体管的第二极与第一节点电连接；
    第一电容的一端与第一节点电连接，第一电容的另一端与第一电源线电连接。
  7. 根据权利要求1所述的像素电路，其中，所述存储子电路包括：第二电容；
    第二电容的一端与第一电源线电连接，第二电容的另一端与第二节点电连接。
  8. 根据权利要求1所述的像素电路，其中，所述节点控制子电路包括：第一晶体管、第二晶体管、第四晶体管、第七晶体管和第一电容，所述存储子电路包括：第二电容；所述驱动子电路包括第三晶体管，所述发光控制子电路包括：第五晶体管和第六晶体管；
    第一晶体管的控制极与复位信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第二扫描信号线电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第三节点电连接；
    第三晶体管的控制极与第一节电连接，第三晶体管的第一极与第二节点 电连接，第三晶体管的第二极与第三节点电连接；
    第四晶体管的控制极与第一扫描信号线电连接，第四晶体管的第一极与数据信号线电连接，第四晶体管的第二极与第二节点电连接；
    第五晶体管的控制极与发光信号线电连接，第五晶体管的第一极与第一电源线电连接，第五晶体管的第二极与第二节点电连接；
    第六晶体管的控制极与发光信号线电连接，第六晶体管的第一极与第三节点电连接，第六晶体管的第二极与第四节点电连接；
    第七晶体管的控制极与复位信号线电连接，第七晶体管的第一极与第二初始信号线电连接，第七晶体管的第二极与第四节点电连接；
    第一电容的一端与第一电源线电连接，第一电容的另一端与第一节点电连接；
    第二电容的一端与第一电源线电连接，第二电容的另一端与第二节点电连接。
  9. 根据权利要求1所述的像素电路，其中，所述节点控制子电路包括：第一晶体管、第二晶体管、第四晶体管、第七晶体管、第八晶体管和第一电容；所述存储子电路包括：第二电容；所述驱动子电路包括第三晶体管，所述发光控制子电路包括：第五晶体管和第六晶体管；
    第一晶体管的控制极与复位信号线电连接，第一晶体管的第一极与第一初始信号线电连接，第一晶体管的第二极与第八晶体管的第一极电连接；
    第二晶体管的控制极与第二扫描信号线电连接，第二晶体管的第一极与第一节点电连接，第二晶体管的第二极与第三节点电连接；
    第三晶体管的控制极与第一节电连接，第三晶体管的第一极与第二节点电连接，第三晶体管的第二极与第三节点电连接；
    第四晶体管的控制极与第一扫描信号线电连接，第四晶体管的第一极与数据信号线电连接，第四晶体管的第二极与第二节点电连接；
    第五晶体管的控制极与发光信号线电连接，第五晶体管的第一极与第一电源线电连接，第五晶体管的第二极与第二节点电连接；
    第六晶体管的控制极与发光信号线电连接，第六晶体管的第一极与第三节点电连接，第六晶体管的第二极与第四节点电连接；
    第七晶体管的控制极与复位信号线电连接，第七晶体管的第一极与第二初始信号线电连接，第七晶体管的第二极与第四节点电连接；
    第八晶体管的控制极与第一扫描信号线电连接，第八晶体管的第二极与第一节点电连接；
    第一电容的一端与第一电源线电连接，第一电容的另一端与第一节点电连接；
    第二电容的一端与第一电源线电连接，第二电容的另一端与第二节点电连接。
  10. 一种显示基板，包括：基底以及依次设置在基底上的驱动电路层和发光结构层，所述驱动电路层包括如权利要求1至9任一项所述的像素电路、多条第一初始信号线、多条第二初始信号线、多条第一扫描信号线、多条第二扫描信号线、多条复位信号线、多条第一电源线和多条数据信号线，所述发光结构层包括：发光器件。
  11. 根据权利要求10所述的显示基板，其中，所述驱动电路层包括：依次叠设在所述基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层和第四导电层，所述像素电路包括：多个晶体管、第一电容和第二电容，第一电容和第二电容包括：第一极板和第二极板；
    半导体层至少包括：多个晶体管的有源层和第二电容的第一极板；
    第一导电层至少包括：复位信号线、发光信号线、多个晶体管的控制极、第一电容的第一极板；
    第二导电层至少包括：第二初始信号线、第一电容的第二极板和第二电容的第二极板；
    第三导电层至少包括：第一扫描信号线和第二扫描信号线；
    第四导电层至少包括：第一初始信号线、第一电源线和数据信号线。
  12. 根据权利要求11所述的显示基板，其中，所述像素电路包括第一晶 体管至第七晶体管，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区；
    第三晶体管的有源层的第一区沿第一方向的长度大于第三晶体管的有源层的第二区沿第一方向的长度，所述第三晶体管的有源层的第一区复用为第二电容的第一极板。
  13. 根据权利要求11所述的显示基板，其中，对于同一像素电路，第一电容的第二极板与第二电容的第二极板连接，位于同一行的第N列像素电路的第二电容的第二极板与第N+1列像素电路的第一电容的第二极板连接；
    第一电容的第二极板沿第二方向的长度小于第二电容的第二极板沿第二方向的长度，所述第一方向和所述第二方向相交。
  14. 根据权利要求13所述的显示基板，其中，第二电容的第二极板包括：沿第二方向延伸的电容主体部以及沿第一方向延伸的第一连接块和第二连接块；第一连接块和第二连接块分别与电容主体部连接，第一连接块和第二连接块平行设置，且位于电容主体部远离第一电容的第二极板的一侧；
    电容主体部在基底上的正投影与第二电容的第一极板在基底上的正投影至少部分交叠，第一连接块在基底上的正投影与位于第二晶体管的控制极之间的第二晶体管的有源层在基底上的正投影部分交叠，第二连接块在基底上的正投影与第三晶体管的有源层在基底上的正投影部分交叠；
    对于同一像素电路，第一电容的第二极板与电容主体部连接，位于同一行的第N列像素电路的第二连接块与第N+1列像素电路的第一电容的第二极板连接。
  15. 根据权利要求11所述的显示基板，其中，第一电源线沿第一方向的长度大于数据信号线沿第一方向的长度，且大于第一初始信号线沿第一方向的长度，第一初始信号线沿第一方向的长度大于数据信号线沿第一方向的长度。
  16. 根据权利要求10所述的显示基板，其中，所述驱动电路层包括：遮挡层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层和第四导电层，所述像素 电路包括：多个晶体管、第一电容和第二电容，第一电容包括：第一极板和第二极板，第二电容包括：第一极板、第二极板和第三极板；
    遮挡层至少包括：第二电容的第一极板，所述遮挡层被配置为传输高压电源信号；
    半导体层至少包括：多个晶体管的有源层、第二电容的第二极板、第一初始信号线和第二初始信号线；
    第一导电层至少包括：发光信号线、多个晶体管的控制极和第一电容的第一极板；
    第二导电层至少包括：第一电容的第二极板和第二电容的第三极板；
    第三导电层至少包括：两条复位信号线、第一扫描信号线和第二扫描信号线；
    第四导电层至少包括：第一电源线和数据信号线。
  17. 根据权利要求16所述的显示基板，其中，多个晶体管包括：第一晶体管至第八晶体管，所述遮挡层还包括：第一遮挡结构、第二遮挡结构、第一遮挡连接结构、第二遮挡连接结构、第三遮挡连接结构和第四遮挡连接结构，第二电容的第一极板复用为第二遮挡结构；
    第一遮挡连接结构和第二遮挡结构分别位于第一遮挡结构相对设置的两侧，且与第一遮挡结构连接，第二遮挡连接结构位于第二遮挡结构远离第一遮挡结构的一侧，且与第二遮挡结构连接，第三遮挡连接结构和第四遮挡连接结构分别位于第一遮挡结构相对设置的另外两侧，且第三遮挡连接结构与第二遮挡结构连接，第四遮挡连接结构与第一遮挡结构连接；
    第一遮挡结构在基底上的正投影与第三晶体管的有源层的沟道区在基底上的正投影至少部分交叠，第二遮挡结构在基底上的正投影与第二电容的第二极板在基底上的正投影至少部分交叠，第三遮挡连接结构在基底上的正投影与第一晶体管的有源层在基底上的正投影至少部分交叠，第四遮挡连接结构在基底上的正投影与第七晶体管的有源层基底上的正投影至少部分交叠。
  18. 根据权利要求17所述的显示基板，其中，位于同一行的第N列子像素的第二遮挡结构位于第N列子像素的第一遮挡结构靠近第N+1列子像素 的第一遮挡结构的一侧，位于同一行的第N列子像素的第一遮挡连接结构位于第N列子像素的第一遮挡结构靠近第N-1列子像素的第一遮挡结构的一侧，且与第N-1列子像素的第四遮挡连接结构连接，位于同一行的第N列子像素的第二遮挡连接结构与第N+1列子像素的第一遮挡连接结构连接；位于同一列的第M行子像素的第三遮挡连接结构位于第M行子像素的第一遮挡结构11靠近第M-1行子像素的第一遮挡结构的一侧，且与第M-1行子像素的第四遮挡连接结构连接，位于同一列的第M行子像素的第四遮挡连接结构位于第M行子像素的第一遮挡结构靠近第M+1行子像素的第一遮挡结构的一侧，且与第M+1行子像素的第五遮挡连接结构连接。
  19. 根据权利要求16所述的显示基板，其中，对于同一子像素，第一电容的第二极板和第二电容的第三极板相互连接；
    对于同一行的子像素，第N列子像素的第二电容的第三极板位于第N列子像素的第一电容的第二极板靠近第N+1列子像素的第一电容的第二极板，且与第N+1列子像素的第一电容的第二极板连接；
    第一电容的第二极板沿第二方向的长度小于第二电容的第三极板沿第二方向的长度。
  20. 一种显示装置，包括：如权利要求10至19任一项所述的显示基板。
  21. 根据权利要求20所述的显示装置，还包括：栅极驱动电路，栅极驱动电路包括：K+2个级联的移位寄存器，K为像素电路的总行数；
    第一级移位寄存器与第一行像素电路所连接的复位信号线连接，第二级移位寄存器分别与第一行像素电路所连接的第一扫描信号线和第二行像素电路所连接的复位信号线连接，第i级移位寄存器分别与第i-2行像素电路所连接的第二扫描信号线、第i-1行像素电路所连接的第一扫描信号线和第i行像素电路所连接的复位信号线连接，第K+1级移位寄存器分别与第K-1行像素电路所连接的第二扫描信号线和第K行像素电路所连接的第一扫描信号线连接，第K+2级移位寄存器分别与第K行像素电路的所连接的第二扫描信号线连接，i＝3,4,…,K。
  22. 一种像素电路的驱动方法，被配置为驱动如权利要求1至9任一项所述的像素电路，所述方法包括：
    节点控制子电路在复位信号线、第一扫描信号线和第二扫描信号线的控制下，向第一节点提供第一初始信号线或者第三节点的信号，向第四节点提供第二初始信号线的信号，向第二节点提供数据信号线的信号；
    存储子电路在第一扫描信号线为有效电平信号时，对第二节点进行充电；
    驱动子电路第一节点和第二节点的控制下，向第三节点提供驱动电流；
    发光控制子电路在发光信号线的控制下，向第二节点提供第一电源线的信号，并向第四节点提供第三节点的信号。
PCT/CN2022/122558 2022-09-29 2022-09-29 像素电路及其驱动方法、显示基板和显示装置 Ceased WO2024065388A1 (zh)

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