WO2024130591A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024130591A1
WO2024130591A1 PCT/CN2022/140692 CN2022140692W WO2024130591A1 WO 2024130591 A1 WO2024130591 A1 WO 2024130591A1 CN 2022140692 W CN2022140692 W CN 2022140692W WO 2024130591 A1 WO2024130591 A1 WO 2024130591A1
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Prior art keywords
transistor
signal line
driving circuit
line
substrate
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PCT/CN2022/140692
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English (en)
French (fr)
Inventor
徐光华
白露
储小东
黄世雄
魏玉龙
张代应
谢涛峰
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/140692 priority Critical patent/WO2024130591A1/zh
Publication of WO2024130591A1 publication Critical patent/WO2024130591A1/zh

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  • the present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, comprising: a substrate and a driving circuit layer disposed on the substrate, wherein the substrate comprises: a display area and a non-display area, and the driving circuit layer comprises: a pixel driving circuit located in the display area, a gate driving circuit located in the non-display area, and at least one initial power supply line, wherein at least a portion of the initial power supply line extends along a first direction;
  • the gate driving circuit is configured to provide a driving signal to the pixel driving circuit, and the initial power supply line is configured to provide an initial signal to the pixel driving circuit;
  • An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of the gate driving circuit on the substrate.
  • the gate driving circuit includes: a plurality of driving circuits arranged along a second direction, the first direction intersecting the second direction;
  • An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of a driving circuit close to the display area among the plurality of driving circuits on the substrate.
  • the pixel driving circuit includes: a light emitting transistor and a writing transistor, the plurality of driving circuits include: a light emitting driving circuit and a scanning driving circuit, the light emitting driving circuit is electrically connected to the light emitting transistor, the scanning driving circuit is electrically connected to the writing transistor, and the scanning driving circuit is located on a side of the light emitting driving circuit close to the display area;
  • An orthographic projection of at least one initial power supply line on the substrate at least partially overlaps with an orthographic projection of the scan driving circuit on the substrate.
  • the pixel driving circuit includes: a light emitting transistor, a writing transistor and a control transistor
  • the plurality of driving circuits include: a light emitting driving circuit, a scanning driving circuit and a control driving circuit, the light emitting driving circuit is electrically connected to the light emitting transistor, the scanning driving circuit is electrically connected to the writing transistor, the control driving circuit is electrically connected to the control transistor, and the transistor types of the writing transistor and the control transistor are opposite; the light emitting driving circuit and the control driving circuit are located on a side of the scanning driving circuit away from the display area;
  • An orthographic projection of at least one of the initial power supply lines on the substrate at least partially overlaps with an orthographic projection of the scan driving circuit on the substrate.
  • the at least one initial power supply line includes: a first initial power supply line to an Nth initial power supply line, where N is a positive integer greater than or equal to 1;
  • N initial power supply lines are arranged along the second direction, and the orthographic projections of K adjacent initial power supply lines away from the display area on the substrate at least partially overlap with the orthographic projection of the scan drive circuit on the substrate, and K is a positive integer less than or equal to N.
  • the driving circuit layer further includes: a first clock signal line, a second clock signal line, a first initial signal line, a first power line, and a second power line located in the non-display area, the first clock signal line, the second clock signal line, the first initial signal line, the first power line, and the second power line at least partially extending along the first direction;
  • the scan driving circuit is electrically connected to the first clock signal line, the second clock signal line, the first power line, the second power line and the first initial signal line respectively;
  • the second clock signal line is located on a side of the first clock signal line away from the display area
  • the second power line is located on a side of the first clock signal line close to the display area
  • the first initial signal line is located on a side of the second power line close to the display area
  • the first power line is located on a side of the first initial signal line close to the display area
  • the at least one initial power supply line is located on a side of the first power line close to the display area.
  • the driving circuit layer further includes: a second initial signal line located in the non-display area, the second initial signal line at least partially extending along the first direction;
  • the light emitting driving circuit is electrically connected to the second initial signal line, and the second initial signal line is located between the second power line and the first initial signal line.
  • the driving circuit layer further includes: a first output signal line and a second output signal line located in the non-display area, the first output signal line and the second output signal line at least partially extending along the second direction;
  • the first output signal line is located on a side of the scan driving circuit close to the display area, and is electrically connected to the scan driving circuit and the pixel driving circuit respectively;
  • the second output signal line passes through the scan driving circuit and is electrically connected to the pixel driving circuit and one of the light emitting driving circuit and the control driving circuit.
  • the driving circuit layer further includes: a first output connection line and a second output connection line located in the display area and the non-display area, the first output connection line and the second output connection line at least partially extending along the second direction;
  • the first output connection line is electrically connected to the first output signal line and the pixel driving circuit respectively;
  • the second output connection line is electrically connected to the second output signal line and the pixel driving circuit respectively.
  • the driving circuit layer further includes: a third output connection line and a fourth output connection line, the third output connection line and the fourth output connection line at least partially extending along the second direction;
  • the third output connection line is electrically connected to the first initial power supply line and the pixel driving circuit respectively;
  • the fourth output connection line is electrically connected to the second initial power supply line and the pixel driving circuit respectively.
  • the boundary of the display area includes an arc-shaped boundary, and the non-display area outside the arc-shaped boundary is called a rounded corner area;
  • the scanning driving circuit comprises: a plurality of scanning shift registers and a plurality of virtual scanning shift registers, the plurality of scanning shift registers are cascaded, and the plurality of virtual scanning shift registers are interspersed between the plurality of scanning shift registers;
  • a plurality of dummy scan shift registers are at least partially located in the rounded corner area.
  • the scan shift register includes: a plurality of transistors and a plurality of capacitors;
  • the orthographic projection of the initial power supply line overlapping with the scan driving circuit on the substrate at least partially overlaps with the orthographic projection of the plurality of capacitors on the substrate.
  • a distance between the initial power supply line overlapping the scan driving circuit and the display region is smaller than a distance between at least one of the plurality of capacitors and the display region.
  • the number of transistors in the dummy scan shift register is less than or equal to the number of transistors in the scan shift register
  • the width of the virtual scan shift register is smaller than or equal to the width of the scan shift register.
  • a distance between a boundary of a second clock signal line located on a side of the virtual scan shift register away from the display area and a boundary of an initial power line of at least one initial power line close to the display area close to the display area is smaller than a distance between a boundary of a second clock signal line located on a side of the scan shift register away from the display area and a boundary of an initial power line of at least one initial power line close to the display area close to the display area.
  • the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence;
  • the semiconductor layer at least includes: an active layer of a plurality of transistors;
  • the first conductive layer at least includes: control electrodes of a plurality of transistors and first plates of a plurality of capacitors;
  • the second conductive layer at least includes: second plates of a plurality of capacitors, a first output signal line and a third output signal line;
  • the third conductive layer at least includes: a second power supply line, a first electrode and a second electrode of at least one transistor, and a fourth output signal line;
  • the fourth conductive layer at least includes: a first initial signal line, a second initial signal line and a first power line.
  • the driving circuit layer further includes: a fifth conductive layer located on a side of the fourth conductive layer away from the substrate;
  • the fifth conductive layer at least includes: a first output connection line, a second output connection line, a third output connection line and a fourth output connection line.
  • the initial power supply line is a single-layer structure, and the initial power supply line is located in the fourth conductive layer.
  • the initial power supply line includes: a first initial subsegment and a second initial subsegment connected to each other, an orthographic projection of the first initial subsegment on the substrate at least partially overlapping an orthographic projection of the second initial subsegment on the substrate;
  • the first initial sub-segment is located in the third conductive layer, and the second initial sub-segment is located in the fourth conductive layer.
  • the first clock signal line and the second clock signal line are of a single-layer structure, and the first clock signal line and the second clock signal line are located in a fourth conductive layer.
  • the clock signal line includes: a first clock sub-segment and a second clock sub-segment connected to each other, the clock signal line includes a first clock signal line and a second clock signal line, an orthographic projection of the first clock sub-segment on a substrate at least partially overlaps with an orthographic projection of the second clock sub-segment on a substrate;
  • the first clock sub-segment is located on the third conductive layer, and the second clock sub-segment is located on the fourth conductive layer close to the substrate.
  • the second output signal line has a single-layer structure, and the second output signal line is located in the second conductive layer.
  • the driving circuit layer further includes: a sixth conductive layer located between the second conductive layer and the third conductive layer;
  • the second output signal line includes a plurality of first output sub-segments and a plurality of second output sub-segments, adjacent first output sub-segments are electrically connected via the second output sub-segments, adjacent second output sub-segments include the first output sub-segments being electrically connected, the orthographic projection of the second output sub-segments on the substrate at least partially overlaps with the orthographic projection of the electrically connected first output sub-segments on the substrate, and the orthographic projection of the first output sub-segments on the substrate at least partially overlaps with the orthographic projection of the electrically connected second output sub-segments on the substrate;
  • the first output sub-segment is located at the second conductive layer, and the second output sub-segment is located at the sixth conductive layer.
  • the present disclosure further provides a display device, comprising the above-mentioned display substrate.
  • FIG. 1A is a schematic structural diagram of a display substrate
  • FIG. 1B is a schematic diagram showing area division of a display substrate
  • FIG2 is a schematic structural diagram of another display substrate
  • FIG3A is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG3B is a working timing diagram of the pixel driving circuit provided in FIG3A ;
  • FIG4A is a schematic diagram of an equivalent circuit of another pixel driving circuit
  • FIG4B is a working timing diagram of the pixel driving circuit provided in FIG4A ;
  • FIG5A is a first structural schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG5B is a partial schematic diagram of the display substrate provided in FIG5A ;
  • FIG6A is a second structural schematic diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG6B is a partial schematic diagram of the display substrate provided in FIG6A ;
  • FIG7A is an equivalent circuit diagram of a shift register in a display substrate
  • FIG7B is a timing diagram of the shift register provided in FIG7A ;
  • FIG8A is an equivalent circuit diagram of a virtual scan shift register
  • FIG8B is an equivalent circuit diagram of another virtual scan shift register
  • FIG9A is a partial schematic diagram of a display substrate
  • FIG9B is a partial schematic diagram of the display substrate in the rounded corner area provided in FIG9A ;
  • FIG10A is another partial schematic diagram of a display substrate
  • FIG10B is another partial schematic diagram of a display substrate
  • FIG12 is a partial schematic diagram of yet another display substrate
  • FIG13 is a schematic diagram of the structure of a second output signal line
  • FIG14 is a schematic diagram of FIG9A after the semiconductor layer pattern is formed
  • FIG15 is a schematic diagram of the first conductive layer pattern of FIG9A ;
  • FIG16 is a schematic diagram of FIG9A after forming a first conductive layer pattern
  • FIG17 is a schematic diagram of a second conductive layer pattern of FIG9A ;
  • FIG18 is a schematic diagram of FIG9A after forming a second conductive layer pattern
  • FIG19 is a schematic diagram of FIG9A after forming a third insulating layer pattern
  • FIG20 is a schematic diagram of a third conductive layer pattern of FIG9A ;
  • FIG21 is a schematic diagram of FIG9A after forming a third conductive layer pattern
  • FIG22 is a schematic diagram of FIG9A after forming a fourth insulating layer pattern
  • FIG23 is a schematic diagram of the fourth conductive layer of FIG9A ;
  • FIG24 is a schematic diagram of forming a fourth conductive layer in FIG9A ;
  • FIG25 is a schematic diagram of FIG10A after a semiconductor layer pattern is formed
  • FIG26 is a schematic diagram of the first conductive layer pattern of FIG10A ;
  • FIG27 is a schematic diagram of FIG10A after forming a first conductive layer pattern
  • FIG28 is a schematic diagram of FIG10A after forming a third insulating layer pattern
  • FIG29 is a schematic diagram of a third conductive layer pattern of FIG10A.
  • FIG30 is a schematic diagram of FIG10A after forming a third conductive layer pattern
  • FIG31 is a schematic diagram of the fourth conductive layer of FIG10A.
  • FIG32 is a schematic diagram of forming a fourth conductive layer in FIG10A.
  • FIG33 is a schematic diagram of FIG10B after forming a semiconductor layer pattern
  • FIG34 is a schematic diagram of the first conductive layer pattern of FIG10B ;
  • FIG35 is a schematic diagram of FIG10B after the first conductive layer pattern is formed
  • FIG36 is a schematic diagram of FIG10B after forming a third insulating layer pattern
  • FIG37 is a schematic diagram of a third conductive layer pattern of FIG10B ;
  • FIG38 is a schematic diagram of FIG10B after forming a third conductive layer pattern
  • FIG39 is a schematic diagram of the fourth conductive layer of FIG10B ;
  • FIG. 40 is a schematic diagram of forming a fourth conductive layer in FIG. 10B .
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” can be interchanged.
  • conductive layer can be replaced by “conductive film” in some cases.
  • insulating film can be replaced by “insulating layer” in some cases.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • the display substrate has the advantages of high resolution, high response speed, high brightness, high aperture ratio, etc., and has a wide range of application prospects.
  • narrow borders are the main development direction of display.
  • a driving circuit is provided in the display substrate to drive the pixel driving circuit to emit light, thereby realizing display.
  • the display substrate cannot achieve a narrow border.
  • FIG1A is a schematic diagram of the structure of a display substrate
  • FIG1B is a schematic diagram of the region division of a display substrate
  • FIG2 is a schematic diagram of the structure of another display substrate.
  • the display substrate may include: a display area 100 and a non-display area 200
  • the boundary of the display area 100 includes at least one arc-shaped boundary C
  • the non-display area includes: a rounded corner area CR located outside the arc-shaped boundary C.
  • the shape of the border of the display area may be a rounded rectangle, which is not limited in the present disclosure.
  • the display substrate provided by the present disclosure can realize the large-angle bending function on four sides, improve the module fitting wrinkle problem, and improve the product yield.
  • the display area may include: pixel units P arranged in an array, at least one pixel unit includes at least three sub-pixels, and at least one sub-pixel includes: a pixel driving circuit and a light-emitting device.
  • the pixel driving circuit located in the same sub-pixel is electrically connected to the light-emitting device and is configured to drive the light-emitting device to emit light.
  • a pixel unit may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure.
  • the shape of the sub-pixels in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangle pattern.
  • the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern, which is not limited in the present disclosure.
  • the light emitting device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), wherein the OLED may include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the electron transport layers of all sub-pixels may be a common layer connected together
  • the hole blocking layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the non-display area 200 may include a binding area located on one side of the display area 100 and a bezel area located on the other side of the display area 100 .
  • the binding area may include a lead area, a bending area and a composite circuit area arranged in sequence along a direction away from the display area, the lead area is connected to the display area 100, the bending area is connected to the lead area, and the composite circuit area is connected to the bending area.
  • a plurality of lead lines may be provided in the lead area, one end of a portion of the plurality of lead lines may be connected to a plurality of data fan-out lines in the display area 100, one end of another portion of the plurality of lead lines may be connected to a plurality of data lines in the display area 100, and the other ends of the plurality of lead lines may cross the bending area to connect to the integrated circuit in the composite circuit area, so that the integrated circuit applies data signals to the data lines through the lead lines and the data fan-out lines.
  • the bending area can be bent at a curvature, and the surface of the composite circuit area can be reversed, that is, the surface of the composite circuit area facing upward can be converted to face downward by bending the bending area.
  • the composite circuit area when the bending area is bent, can overlap the display area 100.
  • the composite circuit area may include an anti-static area, a driving chip area and a binding pin area, an integrated circuit (IC) may be bound and connected to the driving chip area, and a flexible printed circuit (FPC) may be bound and connected to the binding pin area.
  • IC integrated circuit
  • FPC flexible printed circuit
  • the integrated circuit may generate a driving signal required for driving the sub-pixel, and may provide the driving signal to the sub-pixel in the display area 100.
  • the driving signal may be a data signal for driving the sub-pixel to emit light at a brightness.
  • the integrated circuit may be bound and connected to the driver chip area through an anisotropic conductive film or other means.
  • the binding pin area may be provided with a pad including a plurality of pins (PINs), and the flexible circuit board may be bound and connected to the pad.
  • the display substrate may include a timing controller, a data driving circuit, a gate driving circuit, and a pixel array
  • the timing controller is respectively connected to the data driving circuit and the gate driving circuit
  • the data driving circuit is respectively connected to the data signal line Data
  • the gate multifunctional circuit is connected to the gate line
  • the gate line may include one or more of the light emitting signal line EM, the scanning signal line Gate or Scan.
  • the pixel driving circuit may be respectively connected to the gate line and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driving circuit to the data driving circuit, may provide a clock signal, a start signal, etc. suitable for the specifications of the gate driving circuit to the gate driving circuit, and may provide a clock signal, an emission stop signal, etc. suitable for the specifications of the light emitting driving circuit to the light emitting driving circuit.
  • the data driving circuit may generate a data voltage to be provided to the data signal line using the grayscale value and the control signal received from the timing controller. For example, the data driving circuit may sample the grayscale value using the clock signal, and apply a data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.
  • the gate drive circuit may generate a scan signal to be provided to the gate line by receiving a clock signal, a start signal, etc. from a timing controller.
  • the gate drive circuit may sequentially provide a signal having an on-level pulse to the gate line.
  • the gate drive circuit may be configured in the form of a shift register, and may sequentially transmit a start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal to generate a scan signal.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.
  • FIG3A is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (first transistor M1 to seventh transistor M7), 1 capacitor C and 8 signal lines (data signal line Data, scan signal line Gate, reset signal line Reset, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, high level power line VDD and low level power line VSS).
  • the first electrode of the capacitor C is connected to the high-level power supply line VDD, and the second electrode of the capacitor C is connected to the first node N1.
  • the control electrode of the first transistor M1 is connected to the reset signal line Reset, the first electrode of the first transistor M1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1;
  • the control electrode of the second transistor M2 is connected to the scan signal line Gate, the first electrode of the second transistor M2 is connected to the first node N1, and the second electrode of the second transistor M2 is connected to the second node N2.
  • the control electrode of the third transistor M3 is connected to the first node N1, the first electrode of the third transistor M3 is connected to the second node N2, and the second electrode of the third transistor M3 is connected to the third node N3.
  • the control electrode of the fourth transistor M4 is connected to the scan signal line GATE, the first electrode of the fourth transistor M4 is connected to the data signal line Data, and the second electrode of the fourth transistor M4 is connected to the second node N2.
  • the control electrode of the fifth transistor M5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the high level power line VDD, and the second electrode of the fifth transistor M5 is connected to the second node N2; the control electrode of the sixth transistor M6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L.
  • the control electrode of the seventh transistor M7 is connected to the reset signal line Reset or the scanning signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device is connected to the low level power line VSS.
  • FIG. 3A is described by taking the control electrode of the seventh transistor M7 and the reset signal line Reset as an example.
  • the first transistor M1 may be referred to as a node reset transistor, and when the reset signal line Reset inputs an active level signal, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.
  • the second transistor M2 may be referred to as a compensation transistor, and when the control signal line SL inputs an active level signal, the second transistor M2 transmits a signal of the second node N2 to the first node N1 to compensate for the signal of the first node N1.
  • the third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines a driving current flowing between the high-level power line VDD and the low-level power line VSS according to a potential difference between the control electrode and the first electrode.
  • the fourth transistor M4 may be referred to as a write transistor or the like, and when the scan signal line Gate inputs an active level signal, the fourth transistor M4 inputs a data voltage of the data signal line Data to the third node N3 .
  • the fifth transistor M5 and the sixth transistor M6 may be referred to as light emitting transistors.
  • the fifth transistor M5 and the sixth transistor M6 enable the light emitting device to emit light by forming a driving current path between the high level power line VDD and the low level power line VSS.
  • the seventh transistor M7 can be called an anode reset transistor.
  • the reset signal line Reset or the scan signal line Gate inputs a valid level signal
  • the seventh transistor M7 transmits an initialization voltage to the first electrode of the light emitting device L to initialize the charge amount of the first electrode of the light emitting device L.
  • the signal of the high-level power line VDD is a continuously provided high-level signal
  • the signal of the low-level power line VSS is a low-level signal
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor M1 to the seventh transistor M7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor M1 to the seventh transistor M7 may include a P-type transistor and an N-type transistor.
  • the first transistor M1 to the seventh transistor M7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, realize low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the first transistor T1 and the second transistor T2 may be N-type transistors, and the remaining transistors may be P-type transistors.
  • the first transistor M1 to the seventh transistor M7 may be P-type transistors.
  • the first transistor T1 and the second transistor T2 when the display substrate is an LTPO display substrate, when the first transistor T1 and the second transistor T2 are N-type transistors, the first transistor T1 and the second transistor T2 can also be called control transistors. Similarly, the N-type transistor in the pixel driving circuit can be called a control transistor.
  • FIG3B is a timing diagram of the operation of the pixel driving circuit provided in FIG3A.
  • FIG3B is illustrated by taking the transistors in FIG3A as an example that all the transistors are P-type transistors.
  • the following is an exemplary embodiment of the present disclosure described by the operation process of the pixel driving circuit illustrated in FIG3B.
  • the operation process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signals of the scanning signal line Gate and the light-emitting signal line EM are both high-level signals, and the signal of the reset signal line Reset is a low-level signal.
  • the signal of the reset signal line Reset is a high-level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is provided to the first node N1, the capacitor C is initialized, and the original data voltage in the capacitor C is cleared, the seventh transistor M7 is turned on, and the initial voltage of the second initial signal line INIT2 is provided to the first electrode of the light-emitting device L, the first electrode of the light-emitting device L is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.
  • the signals of the scanning signal line Gate and the light-emitting signal line EM are high-level signals, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, and the light-emitting device L does not emit light in this stage.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the scanning signal line Gate is a low-level signal
  • the signals of the light-emitting signal line EM and the reset signal line Reset are high-level signals
  • the data signal line Data outputs a data voltage.
  • the third transistor M3 is turned on.
  • the signal of the scanning signal line Gate is a low-level signal, the second transistor T2 and the fourth transistor M4 are turned on, and the second transistor M2 and the fourth transistor M4 are turned on so that the data voltage output by the data signal line Data passes through the second node N, the turned-on third transistor M3, the third node N3 and the turned-on second transistor M2 to provide to the first node N1, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the signal of the reset signal line Reset is a high-level signal, and the first transistor M1 is turned off.
  • the signal of the light emitting signal line EM is a high level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off
  • the third stage A3 is called the light-emitting stage, the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals, and the signal of the light-emitting signal line EM is a low-level signal.
  • the signal of the light-emitting signal line EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the high-level power supply line VDD.
  • FIG4A is a schematic diagram of an equivalent circuit of another pixel driving circuit.
  • the pixel driving circuit may include 8 transistors (first transistor M1 to eighth transistor M8), 1 capacitor C and 9 signal lines (data signal line Data, control signal line Scan, scan signal line Gate, reset signal line Reset, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, high level power line VDD and low level power line VSS).
  • the pixel driving circuit provided in FIG. 4A is suitable for use in an LTPO display substrate.
  • a first electrode of the capacitor C is connected to a high-level power supply line VDD, and a second electrode of the capacitor C is connected to a first node N1.
  • a control electrode of the first transistor M1 is connected to a reset signal line Reset, a first electrode of the first transistor M1 is connected to a first initial signal line INIT1, and a second electrode of the first transistor is connected to a fourth node N4.
  • a control electrode of the second transistor M2 is connected to a scan signal line Gate, a first electrode of the second transistor M2 is connected to a fourth node N4, and a second electrode of the second transistor M2 is connected to a second node N2.
  • a control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to a second node N2, and a second electrode of the third transistor M3 is connected to a third node N3.
  • a control electrode of the fourth transistor M4 is connected to a scan signal line Gate, a first electrode of the fourth transistor M4 is connected to a data signal line Data, and a second electrode of the fourth transistor M4 is connected to a third node N3.
  • a control electrode of the fifth transistor M5 is connected to a light-emitting signal line EM, a first electrode of the fifth transistor M5 is connected to a high-level power supply line VDD, and a second electrode of the fifth transistor M5 is connected to a third node N3.
  • the control electrode of the sixth transistor M6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the second node N2, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L.
  • the control electrode of the seventh transistor M7 is connected to the reset signal line Reset, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is connected to the low level power line VSS.
  • the control electrode of the eighth transistor M8 is connected to the control signal line SCAN, the first electrode of the eighth transistor M8 is connected to the first node N1, and the second electrode of the eighth transistor M8 is connected to the fourth node N4.
  • control electrode of the seventh transistor M7 can also be connected to the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is connected to the low-level power line VSS.
  • the first transistor M1 may be referred to as a node reset transistor, and when the reset signal line RESET inputs an active level signal, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.
  • the eighth transistor M8 can be called a compensation reset transistor.
  • the eighth transistor M8 transmits the signal of the fourth node N4 to the first node N1, which can not only initialize the charge amount of the first node, but also perform threshold compensation on the third transistor M3.
  • the second transistor M2 may be referred to as a compensation transistor, and when the scan signal line Gate inputs an active level signal, the second transistor M2 allows the signal of the second node N2 to be written to the fourth node N4.
  • the third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines a driving current flowing between the high-level power terminal VDD and the low-level power terminal VSS according to a potential difference between the control electrode and the first electrode.
  • the fourth transistor M4 may be referred to as a write transistor, and when the scan signal line GATE inputs an active level signal, the fourth transistor M4 allows the data voltage of the data signal line Data to be input to the pixel driving circuit.
  • the fifth transistor M5 and the sixth transistor M6 may be referred to as light emitting transistors.
  • the fifth transistor M5 and the sixth transistor M6 enable the light emitting device to emit light by forming a driving current path between the high level power line VDD and the low level power line VSS.
  • the signal of the high-level power line VDD is a continuously provided high-level signal
  • the signal of the low-level power line VSS is a low-level signal
  • the eighth transistor M8 is a metal oxide transistor and is an N-type transistor
  • the first to seventh transistors M1 to M7 are low temperature polysilicon transistors and are P-type transistors.
  • the eighth transistor M8 may be referred to as a control transistor.
  • the eighth transistor M8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce power consumption of the pixel driving circuit.
  • FIG4B is a timing diagram of the operation of the pixel driving circuit provided in FIG4A.
  • the following describes an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG4B.
  • the operation process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signals of the control signal line Scan, the light-emitting signal line EM and the scanning signal line Gate are all high-level signals, and the signal of the reset signal line Reset is a low-level signal.
  • the signal of the reset signal line Reset is a low-level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is provided to the fourth node N4, the seventh transistor M7 is turned on, and the initial voltage of the second initial signal line INIT2 is provided to the first electrode of the light-emitting device L, and the first electrode of the light-emitting device L is initialized (reset), for example: the pre-stored voltage inside it is cleared, the initialization is completed, and the light-emitting device L is ensured not to emit light.
  • the signal of the control signal line Scan is a high-level signal
  • the eighth transistor M8 is turned on
  • the signal of the fourth node N4 is provided to the first node N1
  • the capacitor C is initialized
  • the original data voltage in the capacitor C is cleared.
  • the signals of the scanning signal line Gate and the light-emitting signal line EM are high-level signals
  • the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off, and in this stage, the light-emitting device L does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the scanning signal line Gate is a low level signal
  • the signals of the reset signal line Reset, the luminous signal line EM and the control signal line Scan are high level signals
  • the data signal line Data outputs a data voltage.
  • the third transistor M3 is turned on.
  • the signal of the scanning signal line Gate is a low level signal
  • the second transistor M2 and the fourth transistor M4 are turned on
  • the signal of the control signal line Scan is a high level signal
  • the eighth transistor M8 is turned on.
  • the second transistor M2, the fourth transistor M4 and the eighth transistor M8 are turned on so that the data voltage output by the data signal line Data is provided to the first node N1 through the third node N3, the turned-on third transistor M3, the second node N2, the turned-on second transistor M2, the fourth node N4 and the turned-on eighth transistor M8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off.
  • the signal of the luminous signal line EM is a high-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signals of the control signal line Scan and the light-emitting signal line EM are both low-level signals, and the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals.
  • the signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off.
  • the control signal line SCAN is a low-level signal, the signals of the scanning signal line GATE and the reset signal line Reset are high-level signals, and the second transistor M2, the fourth transistor M4 and the eighth transistor M8 are turned off.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the fifth transistor M5 and the sixth transistor M6 are turned on
  • the power supply voltage output by the high-level power supply terminal VDD provides a driving voltage to the first pole of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the high-level power supply terminal VDD.
  • FIG5A is a schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure
  • FIG5B is a partial schematic diagram of the display substrate provided in FIG5A
  • FIG6A is a schematic diagram of the structure of the display substrate provided in the embodiment of the present disclosure
  • FIG6B is a partial schematic diagram of the display substrate provided in FIG6A.
  • the display substrate provided in the embodiment of the present disclosure may include: a substrate and a driving circuit layer disposed on the substrate, the substrate may include: a display area 100 and a non-display area 200, the driving circuit layer may include: a pixel driving circuit PE located in the display area 100 and a gate driving circuit located in the non-display area 200 and at least one initial power supply line, and the initial power supply line at least partially extends along the first direction D1.
  • At least one initial power supply line includes: a first initial power supply line to an Nth initial power supply line, where N is a positive integer greater than or equal to 1; when N is greater than or equal to 2, the N initial power supply lines are arranged along the second direction D2, and Figures 5A, 5B, 6A and 6B are illustrated by taking two initial power supply lines, and the two initial power supply lines are the first initial power supply line INITL1 and the second initial power supply line INITL2 as examples.
  • the gate driving circuit is configured to provide a driving signal to the pixel driving circuit P
  • the initial power supply line is configured to provide an initial signal to the pixel driving circuit.
  • the positive projection of at least one initial power supply line on the substrate at least partially overlaps with the positive projection of the gate driving circuit on the substrate.
  • Figures 5A, 5B, 6A and 6B are explained by taking the overlap of the second initial power supply line INITL2 and the gate driving circuit as an example.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the display substrate may be an LTPO display substrate or an LTPS display substrate.
  • the driving circuits in the display substrate may be two, three or more types, depending on the structure of the display substrate, which is not limited in the present disclosure.
  • the light emitting device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the display area includes: a first side and a second side arranged opposite to each other, and the gate driving circuit can be located on the first side and/or the second side of the display area.
  • FIG. 5A and FIG. 6A are described by taking the gate driving circuit being located on one side of the display area as an example.
  • the driving circuit layer may further include: at least one initial signal line at least partially located in the display area, the initial signal line may extend at least partially along the second direction, at least one initial signal line corresponds one-to-one with at least one initial power supply line, and the initial signal line is electrically connected to the corresponding initial power supply line.
  • the display substrate may further include: a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the display substrate may include other film layers, such as a touch control structure layer, etc., which is not limited in the present disclosure.
  • the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode 304, the anode is connected to the pixel driving circuit through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer 44 arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer.
  • the first touch metal layer may include a plurality of bridging electrodes
  • the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes
  • the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.
  • the present disclosure can reduce the area occupied by the frame region of the display substrate and achieve a narrow frame by at least partially overlapping the orthographic projection of at least one initial power supply line on the substrate with the orthographic projection of the gate driving circuit on the substrate.
  • the gate driving circuit may include: a plurality of driving circuits arranged along a second direction, the first direction intersecting the second direction.
  • An orthographic projection of at least one initial power supply line on the substrate at least partially overlaps an orthographic projection of a driving circuit close to the display area among the plurality of driving circuits on the substrate.
  • the positional relationship of the plurality of driving circuits may be determined according to the structure and function of the display substrate, which is not limited in the present disclosure.
  • the driving circuit may include a plurality of cascaded shift registers.
  • the pixel driving circuit includes: a light emitting transistor and a writing transistor.
  • the plurality of driving circuits may include: a light emitting driving circuit and a scanning driving circuit, the light emitting driving circuit is electrically connected to the light emitting transistor, the scanning driving circuit is electrically connected to the writing transistor, and the scanning driving circuit is located on a side of the light emitting driving circuit close to the display area 100.
  • the positive projection of at least one initial power supply line on the substrate overlaps with the positive projection of the scanning driving circuit on the substrate at least partially.
  • FIG6A and FIG6B are explained by taking the overlap of the second initial power supply line INITL2 and the scanning driving circuit as an example.
  • the light emitting driving circuit may include: a plurality of cascaded light emitting shift registers EM-GOA
  • the scanning driving circuit may include: a plurality of scanning shift registers Pgate-GOA and a plurality of dummy scanning shift registers DPgate-GOA.
  • the driving circuit layer may further include: a light emitting signal line and a scanning signal line at least partially located in the display area.
  • the light emitting shift register is electrically connected to the pixel driving circuit through the light emitting signal line
  • the scanning shift register is electrically connected to the pixel driving circuit through the scanning signal line
  • the virtual scanning shift register is not electrically connected to the scanning signal line.
  • the pixel driving circuit includes: a light emitting transistor, a writing transistor, and a control transistor.
  • the plurality of driving circuits may include: a light emitting driving circuit, a scanning driving circuit, and a control driving circuit, wherein the light emitting driving circuit is electrically connected to the light emitting transistor, the scanning driving circuit is electrically connected to the writing transistor, the control driving circuit is electrically connected to the control transistor, and the transistor types of the writing transistor and the control transistor are opposite; the light emitting driving circuit and the control driving circuit are located on the side of the scanning driving circuit away from the display area.
  • FIGS. 6A and 6B are illustrated by taking the overlap of the second initial power supply line INITL2 and the scanning driving circuit as an example.
  • control transistor may be an N-type transistor in a pixel driving circuit.
  • the light emitting driving circuit may be located on a side of the control driving circuit close to the display area, or may be located on a side of the control driving circuit away from the display area.
  • FIGS. 5A and 5B show that the light emitting driving circuit is located on a side of the control driving circuit away from the display area.
  • the light emitting driving circuit may include: a plurality of cascaded light emitting shift registers EM-GOA
  • the control driving circuit may include: a plurality of cascaded control shift registers Ngate-GOA
  • the scanning driving circuit may include: a plurality of scanning shift registers Pgate-GOA and a plurality of virtual scanning shift registers DPgate-GOA.
  • a plurality of scan shift registers Pgate-GOA are cascaded, a plurality of DPgate-GOA virtual scan shift registers are interspersed between the plurality of scan shift registers Pgate-GOA, and the plurality of virtual scan shift registers are at least partially located in the rounded corner area.
  • the orthographic projections of K adjacent initial power supply lines far from the display area on the substrate at least partially overlap with the orthographic projection of the scan driving circuit on the substrate, and K is a positive integer less than or equal to N.
  • the orthographic projections of the first initial power supply line and the second initial power supply line on the substrate may both at least partially overlap with the orthographic projection of the scan driving circuit on the substrate.
  • the scanning shift register or the virtual scanning shift register may include: a plurality of transistors and a plurality of capacitors.
  • the circuit structure of the scanning shift register or the virtual scanning shift register may be 8T2C, which is not limited in the present disclosure.
  • Fig. 7A is an equivalent circuit diagram of a shift register in a display substrate
  • Fig. 7B is a timing diagram of the shift register provided in Fig. 7A.
  • the shift register may be a scanning shift register or a virtual scanning shift register.
  • the shift register includes: a first transistor T1 to an eighth transistor T8, a first capacitor C1 and a second capacitor C2.
  • a control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first transistor T1 is electrically connected to the input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the first node G1; a control electrode of the second transistor T2 is electrically connected to the first node G1, a first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and a second electrode of the second transistor T2 is electrically connected to the second node G2; a control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and a second electrode of the third transistor T3 is electrically connected to the second node G2; a control electrode of the fourth transistor T4 is electrically connected to the second node G2, a first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1, and a second electrode
  • the first to eighth transistors T1 to T8 may be P-type transistors or may be N-type transistors.
  • the first power terminal V1 continuously provides a high level signal
  • the second power terminal V2 continuously provides a low level signal
  • the working process of the shift register includes the following stages:
  • the signals of the first clock signal terminal CK1 and the input terminal IN are low-level signals, and the signal of the second clock signal terminal CK2 is a high-level signal. Since the signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1 is turned on, and the signal of the input terminal IN is transmitted to the first node G1 via the first transistor T1. Since the signal of the eighth transistor T8 receives the low-level signal of the second power supply terminal V2, the eighth transistor T8 is in an on state.
  • the level of the third node G3 can be turned on by the fifth transistor T5, and the signal of the second clock signal terminal CK2 is transmitted to the output terminal OUT via the fifth transistor T5, that is, in the input stage B1, the output terminal OUT is the signal of the second clock signal terminal CK2 of the high-level signal.
  • the third transistor T3 since the signal of the first clock signal terminal CK1 is a low-level signal, the third transistor T3 is turned on, and the low-level signal of the second power supply terminal V2 is transmitted to the second node G2 via the third transistor T3.
  • the fourth transistor T4 and the sixth transistor T6 are both turned on. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is turned off.
  • the signal of the first clock signal terminal CK1 is a high level signal
  • the signal of the second clock signal terminal CK2 is a low level signal
  • the signal of the input terminal IN is a high level signal.
  • the fifth transistor T5 is turned on, and the signal of the second clock signal terminal CK2 is used as the signal of the output terminal OUT via the fifth transistor T5.
  • the level of one end of the second capacitor C2 connected to the output terminal OUT is changed to the signal of the second power supply terminal V2. Due to the bootstrap effect of the second capacitor C2, the eighth transistor T8 is turned off, the fifth transistor T5 can be better opened, and the signal of the output terminal OUT is a low level signal.
  • the signal of the first clock signal terminal CK1 is a high level signal, so that the first transistor T1 and the third transistor T3 are both turned off.
  • the second transistor T2 is turned on, and the high level signal of the first clock signal terminal CK1 is transmitted to the second node G2 via the second transistor T2, thereby, the fourth transistor T4 and the sixth transistor T6 are both turned off. Since the signal of the second clock signal terminal CK2 is a low level signal, the seventh transistor T7 is turned on.
  • the signals of the first clock signal terminal CK1 and the second clock signal terminal CK2 are both high-level signals
  • the signal of the input terminal IN is a high-level signal
  • the fifth transistor T5 is turned on
  • the second clock signal terminal CK2 is used as an output signal via the fifth transistor T5. Due to the bootstrap effect of the second capacitor C2, the level of the first node G1 becomes V2-Vth.
  • the signal of the first clock signal terminal CK1 is a high-level signal, so that the first transistor T1 and the third transistor T3 are both turned off, the eighth transistor T8 is turned on, the second transistor T2 is turned on, and the high-level signal of the first clock signal terminal CK1 is transmitted to the second node G2 via the second transistor T2, thereby, the fourth transistor T4 and the sixth transistor T6 are both turned off. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is turned off.
  • the signal of the first clock signal terminal CK1 is a low-level signal
  • the signals of the second clock signal terminal CK2 and the input terminal IN are high-level signals. Since the signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1 is turned on, the signal of the input terminal IN is transmitted to the first node G1 via the first transistor T1, and the second transistor T2 is turned off. Since the eighth transistor T8 is in the on state, the fifth transistor T5 is turned off.
  • the third transistor T3 is turned on, the fourth transistor T4 and the sixth transistor T6 are both turned on, and the high-level signal of the first power supply terminal V1 is transmitted to the output terminal OUT via the fourth transistor T4, that is, the signal of the output terminal OUT is a high-level signal.
  • the signal of the first clock signal terminal CK1 is a high-level signal
  • the signal of the second clock signal terminal CK2 is a low-level signal
  • the signal of the input terminal IN is a high-level signal.
  • the fifth transistor T5 and the second transistor T2 are both turned off.
  • the signal of the first clock signal terminal CK1 is a high-level signal, so that the first transistor T1 and the third transistor T3 are both turned off. Due to the holding effect of the first capacitor C1, the fourth transistor T4 and the sixth transistor T6 are both turned on, and the high-level signal is transmitted to the output terminal OUT via the fourth transistor T4, that is, the signal of the output terminal OUT is a high-level signal.
  • the seventh transistor T7 is turned on, so that the high-level signal is transmitted to the third node G3 and the first node G1 via the sixth transistor T6 and the seventh transistor T7, so that the signals at the third node G3 and the first node G1 remain high-level signals.
  • the signals of the first clock signal terminal CK1 and the second clock signal CK2 are both high-level signals, and the signal of the input terminal IN is a high-level signal.
  • the fifth transistor T5 and the second transistor T2 are turned off.
  • the signal of the first clock signal terminal CK1 is a high-level signal, so that the first transistor T1 and the third transistor T3 are both turned off, and the fourth transistor T4 and the sixth transistor T6 are both turned on.
  • the high-level signal is transmitted to the output terminal OUT via the fourth transistor T4, that is, the signal of the output terminal OUT is a high-level signal.
  • the number of transistors in the dummy scan shift register may be less than or equal to the number of transistors in the scan shift register.
  • the width of the dummy scan shift register may be less than or equal to the width of the scan shift register.
  • the circuit structure of the virtual scanning shift register can be the same as the circuit structure of the scanning shift register.
  • the width of the virtual scanning shift register can be equal to the width of the scanning shift register, and the width is the length in a direction perpendicular to the extension direction of the second power line VGL connected to the shift register.
  • the shift register includes a virtual scanning shift register or a scanning shift register.
  • the width of the dummy scan shift register may be smaller than the width of the scan shift register.
  • the present disclosure can save enough area for the wiring of the scan shift register by reducing the width of the virtual scan shift register, thereby reducing the area occupied by the rounded corner area and realizing a narrow frame of the display substrate.
  • FIG8A is an equivalent circuit diagram of a virtual scan shift register
  • FIG8B is an equivalent circuit diagram of another virtual scan shift register.
  • the circuit structure of the virtual scan shift register may be FIG8A or FIG8B, wherein the circuit structures provided in FIG8A and FIG8B do not have capacitors.
  • the virtual scan shift register may include: a first transistor DT1, a second transistor DT2, and a fourth transistor DT4 to an eighth transistor DT8.
  • the control electrode, the first electrode, and the second electrode of the first transistor DT1 are electrically connected to the second power supply terminal V2
  • the control electrode, the first electrode, and the second electrode of the second transistor DT2 are electrically connected to the second power supply terminal V2
  • the control electrode, the first electrode, and the second electrode of the fourth transistor DT4 are electrically connected to the second power supply terminal V2
  • the first electrode and the second electrode of the fifth transistor DT5 are electrically connected to the second power supply terminal V2
  • the control electrode of the fifth transistor DT5 is electrically connected to the second electrode of the eighth transistor DT8
  • the control electrode and the first electrode of the sixth transistor DT6 are electrically connected to the second power supply terminal V2
  • the second electrode of the sixth transistor DT6 is electrically connected to the first electrode of the seventh transistor DT7, the control electrode and the second
  • the virtual scan shift register may include: a first transistor DT1, a second transistor DT2, and a sixth transistor DT6 to an eighth transistor DT8.
  • the control electrode, the first electrode, and the second electrode of the first transistor DT1 are electrically connected to the second power supply terminal V2
  • the control electrode, the first electrode, and the second electrode of the second transistor DT2 are electrically connected to the second power supply terminal V2
  • the control electrode and the first electrode of the sixth transistor DT6 are electrically connected to the second power supply terminal V2
  • the second electrode of the sixth transistor DT6 is electrically connected to the first electrode of the seventh transistor DT7
  • the control electrode and the second electrode of the seventh transistor DT7 are electrically connected to the second power supply terminal V2
  • the control electrode, the first electrode, and the second electrode of the eighth transistor DT8 are electrically connected to the second power supply terminal V2.
  • the circuit structure of the light emitting shift register or the control register may be 13T3C or 10T3C, which is not limited in the present disclosure.
  • the display substrate may further include other film layers, such as spacers and columns, etc., which are not limited in the present disclosure.
  • Figure 9A is a partial schematic diagram of a display substrate
  • Figure 9B is a partial schematic diagram of the display substrate in the rounded corner area provided by Figure 9A
  • Figure 10A is another partial schematic diagram of the display substrate
  • Figure 10B is another partial schematic diagram of the display substrate
  • Figure 11 is a partial schematic diagram of the display substrate in the rounded corner area provided by Figures 10A and 10B.
  • the driving circuit layer may also include: a first initial signal line GSTV, a first clock signal line GCK1, a second clock signal line GCK2, a first power line VGH, and a second power line VGL located in a non-display area, and the scan driving circuit is electrically connected to the first clock signal line GCK1, the second clock signal line GCK2, the first power line VGH, the second power line VGL, and the first initial signal line GSTV, respectively.
  • the first clock signal line GCK1 , the second clock signal line GCK2 , the first initial signal line GSTV , the first power line VGH, and the second power line VGL may at least partially extend in the first direction D1 .
  • the input terminal of the first-stage shift register is electrically connected to the first initial signal line, and the output terminal of the i-th stage shift register is electrically connected to the input terminal of the i+1-th stage shift register;
  • the first clock signal terminal of the i-th stage shift register is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the second clock signal line,
  • the first clock signal terminal of the i+1-th stage shift register is electrically connected to the second clock signal line, and the second clock signal terminal is electrically connected to the first clock signal line
  • the first power supply terminal of the i-th stage shift register is electrically connected to the first power supply line
  • the second power supply terminal of the i-th stage shift register is electrically connected to the second power supply line.
  • the second clock signal line GCK2 is located at a side of the first clock signal line GCK1 away from the display area
  • the second power line VGL is located at a side of the first clock signal line close to the display area
  • the first initial signal line GSTV is located at a side of the second power line VGL close to the display area
  • the first power line VGH is located at a side of the first initial signal line GSTV close to the display area
  • at least one initial power supply line is located at a side of the first power line VGH close to the display area.
  • FIGS. 9A to 11 are described by taking two initial power supply lines, the first initial power supply line INITL1 and the second initial power supply line INTIL2 as examples.
  • the driving circuit layer may further include: a second initial signal line ESTV located in the non-display area, the second initial signal line ESTV at least partially extending along the first direction D1.
  • the light emitting driving circuit is electrically connected to the second initial signal line ESTV, and the second initial signal line ESTV is located between the second power line VGL and the first initial signal line GSTV.
  • the driving circuit layer may further include: first and second output signal lines OUTL1 and OUTL2 located in the non-display area, the first and second output signal lines OUTL1 and OUTL2 at least partially extending along the second direction D2 .
  • the first output signal line OUTL1 is located at a side of the scan driving circuit close to the display area, and is electrically connected to the scan driving circuit and the pixel driving circuit, respectively.
  • the second output signal line OUTL2 passes through the scan driving circuit and is electrically connected to the pixel driving circuit and one of the light emitting driving circuit and the control driving circuit, respectively.
  • the positive projection of the initial power supply line overlapping with the scan driving circuit on the substrate at least partially overlaps with the positive projection of multiple capacitors on the substrate.
  • the positive projection of the second initial signal line INITL2 on the substrate at least partially overlaps with the positive projection of multiple capacitors on the substrate.
  • the distance between the initial power supply line overlapping with the scan driving circuit and the boundary of the display area is less than the distance between at least one of the multiple capacitors and the boundary of the display area.
  • the distance between the second initial power supply line INITL2 and the boundary of the display area is less than the distance between at least one of the multiple capacitors and the boundary of the display area, that is, the second initial power supply line INITL2 overlaps with the capacitor but does not overlap with the transistor, which can improve the reliability of the scan shift register.
  • a distance L2 between a boundary of the second clock signal line located on the side of the virtual scan shift register away from the display area and a boundary of the initial power line of at least one initial power line close to the display area close to the display area is smaller than a distance L1 between a boundary of the second clock signal line located on the side of the scan shift register away from the display area and a boundary of the initial power line of at least one initial power line close to the display area close to the display area.
  • Figure 12 is a partial schematic diagram of another display substrate.
  • the driving circuit layer may also include: a first output connection line CL1 and a second output connection line CL2 located in the display area and the non-display area, and the first output connection line CL1 and the second output connection line CL at least partially extend along the second direction.
  • the first output connection lines may be electrically connected to the first output signal line OUTL1 and the pixel driving circuit, respectively, and the second output connection lines may be electrically connected to the second output signal line OUTL2 and the pixel driving circuit, respectively.
  • the first output connection line is electrically connected to the pixel driving circuit through the scanning signal line.
  • the second output connection line is electrically connected to the pixel driving circuit through the light emitting signal line or the control signal line, and when the second output signal line connected to the second output connection line is electrically connected to the light emitting driving circuit, the second output connection line is electrically connected to the pixel driving circuit through the light emitting signal line, and when the second output signal line connected to the second output connection line is electrically connected to the control driving circuit, the second output connection line is electrically connected to the pixel driving circuit through the control signal line.
  • the driving circuit layer may further include: a third output connection line CL3 and a fourth output connection line CL4, and a small portion of the third output connection line CL3 and the fourth output connection line CL4 extends along the second direction D2.
  • the third output connection line CL3 is electrically connected to the first initial power supply line and the pixel driving circuit respectively; the fourth output connection line CL4 is electrically connected to the second initial power supply line and the pixel driving circuit respectively.
  • the driving circuit layer may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence;
  • the semiconductor layer includes at least: an active layer of a plurality of transistors;
  • the first conductive layer at least includes: control electrodes of a plurality of transistors and first plates of a plurality of capacitors;
  • the second conductive layer at least includes: second plates of a plurality of capacitors, a first output signal line and a third output signal line;
  • the third conductive layer at least includes: a second power supply line, a first electrode and a second electrode of at least one transistor, and a fourth output signal line;
  • the fourth conductive layer at least includes: a first initial signal line, a second initial signal line and a first power line.
  • the driving circuit layer further includes: a fifth conductive layer located on a side of the fourth conductive layer away from the substrate;
  • the fifth conductive layer at least includes: a first output connection line and a second output connection line.
  • the first output connection line and the second output connection line are located in the fifth conductive layer to further reduce the space occupied by the non-display area.
  • the first output connection line is connected from the non-display area to the display area, and a cross-layer connection is made within the display area to connect to the corresponding pixel driving circuit.
  • a dummy line may be interspersed between the first output connection line and the second output connection line, wherein the dummy line is a signal line that does not provide a signal.
  • the dummy line may be interspersed between the first output connection line and the second output connection line to ensure the etching uniformity of the fifth conductive layer and the reliability of the display substrate.
  • the initial power supply line may be a single-layer structure, or may be a multi-layer structure, which is not limited in the present disclosure.
  • the initial power supply line is a single-layer structure, and the initial power supply line is located in the fourth conductive layer.
  • the initial power supply line may be a single-layer structure.
  • the initial power supply line includes: a first initial subsegment and a second initial subsegment connected to each other, an orthographic projection of the first initial subsegment on the substrate at least partially overlaps with an orthographic projection of the second initial subsegment on the substrate.
  • the first initial sub-segment is located in the third conductive layer and the second initial sub-segment is located in the fourth conductive layer.
  • the initial power supply line adopts a stacking design to reduce the load difference of the initial power supply line and also meet the jumper rule of the display substrate to avoid the risk of static electricity in the display substrate.
  • the first clock signal line and the second clock signal line may be a single-layer structure, or may be a multi-layer structure, which is not limited in the present disclosure.
  • the first clock signal line and the second clock signal line are a single-layer structure, and the first clock signal line and the second clock signal line are located in the fourth conductive layer.
  • the clock signal line may include: a first clock sub-segment and a second clock sub-segment connected to each other, the clock signal line includes the first clock signal line and the second clock signal line, and an orthographic projection of the first clock sub-segment on the substrate at least partially overlaps with an orthographic projection of the second clock sub-segment on the substrate;
  • the first clock sub-segment is located on the third conductive layer, and the second clock sub-segment is located on the fourth conductive layer close to the side of the substrate.
  • the first clock signal line and the second clock signal line adopt a stacked design to reduce the load difference between the first clock signal line and the second clock signal line, and can also meet the jumper rule of the display substrate to avoid static electricity risks in the display substrate.
  • the second output signal line may be a single-layer structure, or may be a multi-layer structure, which is not limited in the present disclosure.
  • the second output signal line is a single-layer structure, and the second output signal line is located in the second conductive layer.
  • FIG. 13 is a schematic diagram of the structure of the second output signal line.
  • the driving circuit layer further includes: a sixth conductive layer located between the second conductive layer and the third conductive layer; wherein the second output signal line includes a plurality of first output sub-segments OUTL2A and a plurality of second output sub-segments OUTL2B, adjacent first output sub-segments OUTL2A are electrically connected through the second output sub-segments OUTL2B, adjacent second output sub-segments OUTL2B are electrically connected through the first output sub-segments OUTL2A, the orthographic projection of the second output sub-segments OUTL2B on the substrate at least partially overlaps with the orthographic projection of the electrically connected first output sub-segments OUTL2A on the substrate, and the orthographic projection of the first output sub-segment OUTL2A on the substrate at least partially overlaps
  • the second output signal line includes a first output sub-segment and a second output sub-segment located in different film layers, which can avoid the risk of static electricity caused by the long second output signal line.
  • the "patterning process” mentioned in the present disclosure includes the processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes the processes of coating organic materials, mask exposure and development, etc. for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate.
  • the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A contains the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • FIG. 9A The following is an exemplary description of the preparation process of the display substrate provided by FIG. 9A , in which FIG. 9A is described by taking the second output signal line as a single-layer structure as an example.
  • forming a semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern, as shown in FIG. 14 , which is a schematic diagram of FIG. 9A after forming a semiconductor layer pattern.
  • the semiconductor layer pattern may include an active layer T11 of a first transistor to an active layer T81 of an eighth transistor.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc.
  • the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).
  • its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.
  • PI1 first flexible
  • a-si amorphous silicon
  • the semiconductor layer film can be made of various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene polythiophene
  • the active layer T21 of the second transistor and the active layer T31 of the third transistor may be an integral structure
  • the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be an integral structure
  • the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor may be an integral structure
  • the active layer T11 of the first transistor and the active layer T81 of the eighth transistor may be separately provided.
  • the active layer T81 of the eighth transistor and the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the active layer T11 of the first transistor, and in the second direction D2, the active layer T11 of the first transistor, the active layer T81 of the eighth transistor, the active layer T41 of the fourth transistor, and the active layer T51 of the fifth transistor, the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the active layer T11 of the first transistor.
  • the structure is located on the same side of the integrated structure of the active layer T21 of the second transistor and the active layer T31 of the third transistor, the integrated structure of the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor, and the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the active layer T81 of the eighth transistor, and the active layer T11 of the first transistor of the scanning shift register at this level is located on the side of the active layer T81 of the eighth transistor of the scanning shift register at this level close to the scanning shift register of the previous level.
  • the active layer T11 of the first transistor may extend along the second direction D2 and be a strip-shaped structure.
  • the integrated structure of the active layer T21 of the second transistor and the active layer T31 of the third transistor, the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor, and the active layer T81 of the eighth transistor may be in an "I" shape.
  • the integrated structure of the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may include two "I"-shaped structures, and the two "I"-shaped structures are arranged along the second direction D2.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region T21_2 of the active layer of the second transistor may serve as the second region T31_2 of the active layer of the third transistor
  • the second region T41_2 of the active layer of the fourth transistor may serve as the second region T51_2 of the active layer of the fifth transistor
  • the second region T61_2 of the active layer of the sixth transistor may serve as the first region T71_1 of the active layer of the seventh transistor, the first region T11_1 and the second region T11_2 of the active layer of the first transistor, the first region T21_1 of the active layer of the second transistor, the first region T31_1 of the active layer of the third transistor, the first region T41_1 of the active layer of the fourth transistor, the first region T51_1 of the active layer of the fifth transistor, the first region T61_1 of the active layer of the sixth transistor, the first region T71_
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 15 and 16 , where FIG. 15 is a schematic diagram of the first conductive layer pattern of FIG. 9A , and FIG. 16 is a schematic diagram of FIG. 9A after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern may include at least: control electrodes T12 to T82 of the first to eighth transistors, first plates C11 and C21 of the first and second capacitors, and a first connection line VL1 .
  • the first plate C11 of the first capacitor, the control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor are an integrated structure
  • the first plate C21 of the second capacitor and the control electrode T52 of the fifth transistor are an integrated structure.
  • the first plate C11 of the first capacitor and the first plate C21 of the second capacitor may be arranged along the first direction D1, and the first plate C11 of the first capacitor may be located on a side of the first plate C21 of the second capacitor close to the previous stage scan shift register.
  • the area of the first plate C21 of the second capacitor may be greater than the area of the first plate C11 of the first capacitor.
  • the first plate C11 of the first capacitor may be in a square shape and may be located on a side of the control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor close to the display area.
  • the control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor may be in a strip shape extending along the second direction D2.
  • the first electrode plate C21 of the second capacitor may be in a square shape and may be located on a side of the control electrode T52 of the fifth transistor close to the display area.
  • the control electrode T52 of the fifth transistor may include a plurality of strip structures extending along the second direction D2, and the integrated structure of the control electrode T52 of the fifth transistor and the first electrode plate C21 of the second capacitor may be a comb structure, with the control electrode T52 of the fifth transistor serving as comb teeth and the first electrode plate C21 of the second capacitor serving as a comb back.
  • control electrode T12 of the first transistor may be located on a side of the first electrode plate C11 of the first capacitor away from the display area.
  • the shape of the control electrode T12 of the first transistor may be a right-rotated "F" shape, and the opening faces the control electrode T22 of the second transistor.
  • control electrode T22 of the second transistor and the control electrode T32 of the third transistor may be a strip-shaped structure extending along the second direction D2 .
  • control electrode T72 of the seventh transistor may be a left-rotated “n” shape, and the lengths of the two sides of n are different.
  • control electrode T82 of the eighth transistor at least partially extends along the second direction D2 and has a zigzag shape.
  • the first connection line VL1 may be in a strip shape extending along the second direction D2 and located at a side of the control electrode T42 of the fourth transistor close to the previous stage shift register.
  • the control electrode T12 of the first transistor is arranged across the active layer of the first transistor
  • the control electrode T22 of the second transistor is arranged across the active layer of the second transistor
  • the control electrode T32 of the third transistor is arranged across the active layer of the third transistor
  • the control electrode T42 of the fourth transistor is arranged across the active layer of the fourth transistor
  • the control electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor
  • the control electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor
  • the control electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor, and the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.
  • the first conductive layer can be used as a shield to perform conductor processing on the semiconductor layer, and the semiconductor layer in the area shielded by the first conductive layer forms the channel area of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the first transistor T1 to the seventh transistor are both conductorized.
  • the integrated structure of the second area of the active layer of the sixth transistor and the first area of the active layer of the seventh transistor is reused as the second electrode T64 of the sixth transistor and the first electrode T73 of the seventh transistor.
  • forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process, forming a second insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 17 and 18 , where FIG. 17 is a schematic diagram of the second conductive layer pattern of FIG. 9A , and FIG. 18 is a schematic diagram of FIG. 9A after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern may include at least a second plate C12 of the first capacitor, a second plate C22 of the second capacitor, a first output signal line OUTL1 , a second output signal line OUTL2 , and a third output signal line OUTL3 .
  • the second plate C22 of the second capacitor and the first output signal line OUTL1 may be an integral structure, and the first output signal line OUTL1 is located on a side of the second plate C22 of the second capacitor close to the display area.
  • the profile of the second plate C12 of the first capacitor can be a sickle shape rotated to the left, and the orthographic projection of the second plate C12 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate C11 of the first capacitor on the substrate.
  • the contour of the second plate C22 of the second capacitor may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the second plate C22 of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate C21 of the second capacitor on the substrate.
  • the first output signal line OUTL1 , the second output signal line OUTL2 , and the third output signal line OUTL3 may at least partially extend along the second direction D2 , and may be in a zigzag line shape.
  • the second output signal line OUTL2 may be located on a side of the first output signal line OUTL1 close to the previous level scan shift register
  • the third output signal line OUTL3 may be located on a side of the first output signal line OUTL1 close to the next level scan shift register
  • the third output signal line OUTL3 is located on a side of the second plate C12 of the first capacitor close to the display area.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of via patterns are disposed on the third insulating layer, as shown in FIG. 19 , which is a schematic diagram of FIG. 9A after the third insulating layer pattern is formed.
  • the plurality of via hole patterns may include at least first to twenty-second via holes H1 to H22 .
  • the orthographic projection of the first via hole H1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the first via hole H1 are etched away to expose the surface of the first region of the active layer of the first transistor, and the first via hole H1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first region of the active layer of the first transistor through the via hole.
  • the orthographic projection of the second via hole H2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the second via hole H2 are etched away to expose the surface of the second region of the active layer of the first transistor, and the second via hole H2 is configured to connect the second electrode of the subsequently formed first transistor T1 to the second region of the active layer of the first transistor through the via hole.
  • the orthographic projection of the third via hole H3 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the second transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the third via hole H3 are etched away to expose the surface of the first region of the active layer of the second transistor, and the third via hole H3 is configured to connect the first electrode of the subsequently formed second transistor to the first region of the active layer of the second transistor through the via hole.
  • the orthographic projection of the fourth via H4 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the second transistor (also the second area of the active layer of the third transistor) on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the fourth via H4 are etched away to expose the surface of the second area of the active layer of the second transistor (also the second area of the active layer of the third transistor), and the fourth via H4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the second area of the active layer of the second transistor (also the second area of the active layer of the third transistor) through the via.
  • the orthographic projection of the fifth via H5 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the third transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the fifth via H5 are etched away to expose the surface of the first area of the active layer of the third transistor, and the fifth via H5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of the active layer of the third transistor through the via.
  • the orthographic projection of the sixth via H6 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fourth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the sixth via H6 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the sixth via H6 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active layer of the fourth transistor through the via.
  • the orthographic projection of the seventh via H7 on the substrate is located within the range of the orthographic projection of the second area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor) on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the seventh via H7 are etched away to expose the surface of the second area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor), and the seventh via H7 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second area of the active layer of the fourth transistor (also the second area of the active layer of the fifth transistor) through the via.
  • the orthographic projection of the eighth via H8 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the fifth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighth via H8 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the eighth via H8 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of the active layer of the fifth transistor through the via.
  • the orthographic projection of the ninth via H9 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the sixth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the ninth via H9 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the ninth via H9 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of the active layer of the sixth transistor through the via.
  • the orthographic projection of the tenth via hole H10 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the seventh transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the tenth via hole H10 are etched away to expose the surface of the second region of the active layer of the fourth transistor, and the tenth via hole H10 is configured to connect the second electrode of the subsequently formed seventh transistor to the second region of the active layer of the seventh transistor through the via hole.
  • the orthographic projection of the eleventh via hole H11 on the substrate is located within the range of the orthographic projection of the first area of the active layer of the eighth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eleventh via hole H11 are etched away to expose the surface of the first area of the active layer of the fourth transistor, and the eleventh via hole H11 is configured to connect the first electrode of the subsequently formed eighth transistor to the first area of the active layer of the eighth transistor through the via hole.
  • the orthographic projection of the twelfth via H12 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth transistor on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the twelfth via H12 are etched away to expose the surface of the first region of the active layer of the fourth transistor, and the twelfth via H12 is configured to connect the second electrode of the subsequently formed eighth transistor to the second region of the active layer of the eighth transistor through the via.
  • the orthographic projection of the thirteenth via H13 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor on the substrate, the third insulating layer and the second insulating layer in the thirteenth via H13 are etched away to expose the surface of the control electrode of the first transistor, and the thirteenth via H13 is configured to connect the first clock sub-segment of the second clock signal line formed subsequently and the first electrode of the second transistor to the control electrode of the first transistor through the via.
  • the orthographic projection of the fourteenth via H14 on the substrate is located within the range of the orthographic projection of the control electrode of the second transistor on the substrate, the third insulating layer and the second insulating layer in the fourteenth via H14 are etched away to expose the surface of the control electrode of the second transistor, and the fourteenth via H14 is configured to connect the second electrode of the subsequently formed first transistor (which is also the second electrode of the seventh transistor and the first electrode of the eighth transistor) to the control electrode of the first transistor through the via.
  • the orthographic projection of the fifteenth via H15 on the substrate is located within the range of the orthographic projection of the control electrode of the third transistor on the substrate, the third insulating layer and the second insulating layer in the fifteenth via H15 are etched away to expose the surface of the control electrode of the second transistor, and the fifteenth via H15 is configured to connect the first clock sub-segment of the second clock signal line formed subsequently to the control electrode of the third transistor through the via.
  • the orthographic projection of the sixteenth via H16 on the substrate is located within the range of the orthographic projection of the control electrode of the fifth transistor on the substrate, the third insulating layer and the second insulating layer in the sixteenth via H16 are etched away to expose the surface of the control electrode of the fifth transistor, and the sixteenth via H16 is configured to connect the second electrode of the subsequently formed eighth transistor to the control electrode of the fifth transistor through the via.
  • the orthographic projection of the seventeenth via H17 on the substrate is located within the range of the orthographic projection of the control electrode of the sixth transistor on the substrate, the third insulating layer and the second insulating layer in the seventeenth via H17 are etched away to expose the surface of the control electrode of the sixth transistor, and the seventeenth via H17 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) to the control electrode of the sixth transistor through the via.
  • the orthographic projection of the eighteenth via H18 on the substrate is located within the range of the orthographic projection of the control electrode of the seventh transistor on the substrate, the third insulating layer and the second insulating layer in the eighteenth via H18 are etched away to expose the surface of the control electrode of the seventh transistor, and the eighteenth via H18 is configured to connect the first electrode and the first clock signal line and the first clock sub-segment of the subsequently formed fifth transistor to the control electrode of the seventh transistor through the via.
  • the orthographic projection of the nineteenth via hole H19 on the substrate is located within the range of the orthographic projection of the control electrode of the eighth transistor on the substrate, the third insulating layer and the second insulating layer in the nineteenth via hole H19 are etched away to expose the surface of the control electrode of the eighth transistor, and the nineteenth via hole H19 is configured to connect the first electrode of the subsequently formed third transistor to the control electrode of the eighth transistor through the via hole.
  • the orthographic projection of the twentieth via hole H20 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the third insulating layer and the second insulating layer in the twentieth via hole H20 are etched away to expose the surface of the first connecting line, and the twentieth via hole H20 is configured to connect the first electrode of a first transistor formed subsequently to the first connecting line through the via hole.
  • the orthographic projection of the twenty-first via H21 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate, the third insulating layer in the twenty-first via H21 is etched away to expose the surface of the second plate of the first capacitor, and the twenty-first via H21 is configured to connect the first electrode of the subsequently formed fourth transistor to the second plate of the first capacitor through the via.
  • the orthographic projection of the twenty-second via H22 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the third insulating layer in the twenty-second via H22 is etched away to expose the surface of the second plate of the second capacitor, and the twenty-second via H22 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second plate of the second capacitor through the via.
  • the orthographic projection of the twenty-third via H23 on the substrate is located within the range of the orthographic projection of the third output signal line on the substrate, the third insulating layer in the twenty-third via H23 is etched away to expose the surface of the third output signal line, and the twenty-third via H23 is configured to connect a first initial sub-segment of a first initial power supply line formed subsequently to the third output signal line through the via.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in FIGS. 20 and 21 , where FIG. 20 is a schematic diagram of the third conductive layer pattern of FIG. 9A , and FIG. 21 is a schematic diagram of FIG. 9A after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may include at least: a first clock sub-segment GCK1A of the first clock signal line, a first clock sub-segment GCK2A of the second clock signal line, a second power line VGL, a first initial sub-segment INITL1A of the first initial power supply line, a first initial sub-segment INITL2A of the second initial power supply line, a fourth output signal line OUTL4, the first electrode T13 and the second electrode T14 of the first transistor to the first electrode T53 and the second electrode T54 of the fifth transistor, the first electrode T63 of the sixth transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 and the second electrode T84 of the eighth transistor.
  • the shape of the first clock sub-segment GCK2A of the second clock signal line can be a line shape extending at least partially along the first direction D1, and the first clock sub-segment GCK2A of the second clock signal line is connected to the control electrode of the first transistor through the thirteenth via, and is connected to the control electrode of the third transistor through the fifteenth via.
  • the shape of the first clock sub-segment GCK1A of the first clock signal line can be a line shape extending at least partially along the first direction D1, and is located on the side of the first clock sub-segment GCK2A of the second clock signal line close to the display area, and the first clock sub-segment GCK1A of the first clock signal line is connected to the control electrode of the seventh transistor through the eighteenth via.
  • the first clock sub-segment GCK2A of the second clock signal line and the first clock sub-segment GCK1A of the first clock signal line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the scan drive circuit, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the second power line VGL and the first electrode T33 of the third transistor are an integral structure
  • the shape of the second power line VGL may be a line shape extending at least partially along the first direction D1, and is located on a side of the first clock subsegment GCK1A of the first clock signal line close to the display area
  • the first electrode T33 of the third transistor is located on a side of the second power line VGL close to the display area
  • the first electrode T33 of the third transistor is connected to the first area of the active layer of the third transistor through a fifth via
  • the width of the second power line VGL may be smaller than the width of the first clock sub-segment GCK2A of the second clock signal line or the first clock sub-segment GCK1A of the first clock signal line.
  • the first electrode T13 of the first transistor can extend along the second direction D2
  • the first electrode T13 of the first transistor is connected to the first area of the active layer of the first transistor through the first via, and is connected to the first connecting line through the twentieth via
  • the first connecting line is connected to the second electrode of the fourth transistor of the previous level scanning shift register (also connected to the second electrode of the fifth transistor) to achieve cascading with the scanning shift register of this level and the scanning shift register of the previous level.
  • the second electrode T14 of the first transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor may be an integral structure, and may be connected to the second region of the active layer of the first transistor through a second via, to the control electrode of the second transistor through a fourteenth via, to the second region of the active layer of the seventh transistor through a tenth via, and to the first region of the active layer of the eighth transistor through an eleventh via.
  • the first electrode T23 of the second transistor may be in a line shape extending along the first direction D1, wherein the first electrode T23 of the second transistor may be connected to the first region of the active layer of the second transistor through the third via hole, and connected to the control electrode of the first transistor through the thirteenth via hole.
  • the second electrode T24 of the second transistor and the second electrode T34 of the third transistor are an integrated structure and may be a line shape extending along the second direction D2.
  • the integrated structure of the second electrode T24 of the second transistor and the second electrode T34 of the third transistor may be connected to the second region of the active layer of the second transistor (also the second region of the active layer of the third transistor) through the fourth via hole, and connected to the control electrode of the sixth transistor through the seventeenth via hole.
  • the second electrode T24 of the second transistor and the second electrode T34 of the third transistor are an integrated structure and can be a line shape extending along the second direction D2.
  • the integrated structure of the second electrode T24 of the second transistor and the second electrode T34 of the third transistor can be connected to the second region of the active layer of the second transistor (also the second region of the active layer of the third transistor) through the fourth via hole, and connected to the control electrode of the sixth transistor through the seventeenth via hole.
  • the first electrode T43 of the fourth transistor and the first electrode T63 of the sixth transistor may be an integral structure and may extend at least partially along the second direction D2, and the integral structure of the first electrode T43 of the fourth transistor and the first electrode T63 of the sixth transistor may be connected to the first region of the active layer of the fourth transistor through a sixth via, connected to the first region of the active layer of the sixth transistor through a ninth via, and connected to the second plate of the first capacitor through a twenty-first via.
  • the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor are an integrated structure, and the shape may be a horizontally flipped "F" shape.
  • the integrated structure of the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor may be connected to the second region of the active layer of the fourth transistor (also the second region of the active layer of the fifth transistor) through the seventh via hole, and connected to the second plate of the second capacitor through the twenty-second via hole.
  • the shape of the first electrode T53 of the fifth transistor may be an "n" shape with an opening toward the display area.
  • the first electrode T53 of the fifth transistor may be connected to the first region of the active layer of the fifth transistor through the eighth via hole, and connected to the control electrode of the seventh transistor through the eighteenth via hole.
  • the second electrode T84 of the eighth transistor may at least partially extend along the second direction D2.
  • the second electrode T84 of the eighth transistor may be connected to the second region of the active layer of the eighth transistor through the twelfth via hole, and connected to the control electrode of the fifth transistor through the sixteenth via hole.
  • the first initial sub-segment INITL2A of the second initial power supply line and the fourth output signal line OUTL4 are integrally structured, and the fourth output signal line OUTL4 is located on a side of the first initial sub-segment INITL2A of the second initial power supply line close to the display area.
  • the shape of the first initial sub-segment INITL2A of the second initial power supply line can be a line shape extending at least partially along the first direction D1, and include a plurality of power supply electrodes arranged at intervals, and the first initial sub-segment INITL2A of the second initial power supply line can be located on a side of the integrated structure of the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor close to the display area.
  • the fourth output signal line OUTL4 may at least partially extend in the second direction D2 .
  • an orthographic projection of the first initial subsegment INITL2A of the second initial power supply line on the substrate at least partially overlaps an orthographic projection of the second plate of the first capacitor and the second plate of the second capacitor on the substrate.
  • the shape of the first initial sub-segment INITL1A of the first initial power supply line may be a line shape extending at least partially along the first direction D1 and include a plurality of power supply electrodes arranged at intervals, and the first initial sub-segment INITL1A of the first initial power supply line may be located on a side of the first initial sub-segment INITL2A of the second initial power supply line close to the display area.
  • the first initial sub-segment INITL1A of the first initial power supply line and the first initial sub-segment INITL2A of the second initial power supply line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the scan drive circuit, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG. 22 , which is a schematic diagram of FIG. 9A after the fourth insulating layer pattern is formed.
  • the plurality of via holes include at least a twenty-fourth via hole H24 to a twenty-eighth via hole H28.
  • the orthographic projection of the twenty-fourth via H24 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fourth insulating layer of the twenty-fourth via H24 is etched away to expose the surface of the first electrode of the fourth transistor, and the twenty-fourth via H24 is configured to connect a subsequently formed first power line to the first electrode of the fourth transistor through the via.
  • the orthographic projection of the twenty-fifth via H25 on the substrate is located within the range of the orthographic projection of the first clock sub-segment of the second clock signal line on the substrate, the fourth insulating layer of the twenty-fourth via H24 is etched away to expose the surface of the first clock sub-segment of the second clock signal line, and the twenty-fourth via H24 is configured to connect the subsequently formed second clock sub-segment of the second clock signal line with the first clock sub-segment of the second clock signal line through the via.
  • the orthographic projection of the twenty-sixth via H26 on the substrate is located within the range of the orthographic projection of the first clock sub-segment of the first clock signal line on the substrate, the fourth insulating layer of the twenty-fifth via H25 is etched away to expose the surface of the first clock sub-segment of the first clock signal line, and the twenty-fifth via H25 is configured to connect the subsequently formed second clock sub-segment of the first clock signal line to the first clock sub-segment of the first clock signal line through the via.
  • the orthographic projection of the twenty-seventh via H27 on the substrate is located within the range of the orthographic projection of the first initial subsegment of the second initial power supply line on the substrate, the fourth insulating layer of the twenty-seventh via H27 is etched away to expose the surface of the first initial subsegment of the second initial power supply line, and the twenty-seventh via H27 is configured to connect the second initial subsegment of the second initial power supply line formed subsequently to the first initial subsegment of the second initial power supply line through the via.
  • the orthographic projection of the twenty-eighth via H28 on the substrate is located within the range of the orthographic projection of the first initial sub-segment of the first initial power supply line on the substrate, the fourth insulating layer of the twenty-eighth via H28 is etched away to expose the surface of the first initial sub-segment of the first initial power supply line, and the twenty-eighth via H28 is configured to connect the subsequently formed second initial sub-segment of the first initial power supply line to the first initial sub-segment of the first initial power supply line through the via.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 23 and 24 , where FIG. 23 is a schematic diagram of the fourth conductive layer of FIG. 9A , and FIG. 24 is a schematic diagram of forming the fourth conductive layer of FIG. 9A .
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern may include at least: a second clock sub-segment GCK1B of the first clock signal line, a second clock sub-segment GCK2B of the second clock signal line, a first power line VGH, a second initial sub-segment INITL1B of the first initial power line, a second initial sub-segment INITL2B of the second initial power line, a first initial signal line GSTV, and a second initial signal line ESTV.
  • the shape of the second clock sub-segment GCK2B of the second clock signal line can be a line shape extending at least partially along the first direction D1, and the orthographic projection of the second clock sub-segment GCK2B of the second clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock sub-segment of the second clock signal line on the substrate, and is connected to the first clock sub-segment of the second clock signal line through the twenty-fifth via to form a second clock signal line.
  • the shape of the second clock sub-segment GCK1B of the first clock signal line can be a line shape extending at least partially along the first direction D1
  • the orthographic projection of the second clock sub-segment GCK1B of the first clock signal line on the substrate at least partially overlaps with the orthographic projection of the first clock sub-segment of the first clock signal line on the substrate, and is connected to the first clock sub-segment of the first clock signal line through the twenty-sixth via to form the first clock signal line.
  • the second initial sub-segment GCK2B of the second clock signal line and the second clock sub-segment GCK1B of the first clock signal line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the scan drive circuit, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the second initial signal line ESTV is located on a side of the second clock sub-segment GCK1B of the first clock signal line close to the display area, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first electrode of the third transistor on the substrate.
  • the first initial signal line GSTV is located on a side of the second initial signal line ESTV close to the display area, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the control electrode of the eighth transistor on the substrate.
  • the second initial signal line ESTV and the first initial signal line GSTV can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the scan drive circuit, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the shape of the first power line VGH can be a line shape extending at least partially along the first direction D1, and the orthographic projection of the first power line VGH on the substrate at least partially overlaps with the second electrode of the fourth transistor (also the second electrode of the fifth transistor) and the orthographic projection of the first electrode of the fourth transistor on the substrate, and is connected to the first electrode of the fourth transistor through the twenty-fourth via.
  • the shape of the second initial sub-segment INITL2B of the second initial power supply line can be a line shape extending at least partially along the first direction D1, the orthographic projection of the second initial sub-segment INITL2B of the second initial power supply line on the substrate at least partially overlaps with the orthographic projection of the first initial sub-segment of the second initial power supply line on the substrate, and is connected to the first initial sub-segment of the second initial power supply line through the twenty-seventh via hole to form a second initial power supply line.
  • the shape of the second initial sub-segment INITL1B of the first initial power supply line can be a line shape extending at least partially along the first direction D1
  • the orthographic projection of the second initial sub-segment INITL1B of the first initial power supply line on the substrate at least partially overlaps with the orthographic projection of the first initial sub-segment of the first initial power supply line on the substrate, and is connected to the first initial sub-segment of the first initial power supply line through the twenty-eighth via hole to form the first initial power supply line.
  • the second initial sub-segment INITL2B of the second initial power supply line and the second initial sub-segment INITL1B of the first initial power supply line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the scan drive circuit, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • Forming a fifth conductive layer pattern may include: depositing a fifth insulating film and a fifth conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film through a patterning process, forming a fourth insulating layer covering the fourth conductive layer pattern, and a fifth conductive layer pattern disposed on the fourth insulating layer.
  • the fifth conductive layer may be referred to as a third source-drain metal (SD3) layer.
  • the fifth conductive layer pattern may include at least a first output connection line, a second output connection line, a third output connection line, and a fourth output connection line.
  • the first output connection line is connected to the first output signal line
  • the second output connection line is connected to the second output signal line
  • the third output connection line is connected to the third output signal line
  • the fourth output connection line is connected to the fourth output signal line.
  • the driving circuit layer is prepared on the substrate.
  • the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a fifth conductive layer sequentially arranged on the substrate.
  • the semiconductor layer may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, or may be a double layer, or may be a multilayer.
  • the active layer film may be made of various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide oxide technology, silicon technology, and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene polythiophene, etc.
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer
  • the third insulating layer and the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer
  • the fifth insulating layer may be referred to as a passivation (PVX) layer.
  • the second conductive layer pattern formed in step (3) includes the first output sub-segment of the second output signal line
  • steps (3) and (4) may include: forming a sixth conductive layer pattern.
  • Forming the sixth conductive layer pattern may include: depositing a sixth insulating film and a sixth conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film through a patterning process, forming a sixth insulating layer covering the second conductive layer pattern, and a sixth conductive layer pattern disposed on the sixth insulating layer.
  • the sixth conductive layer pattern may include at least a second output sub-segment of the second output signal line.
  • step (4) forms a fourth insulating layer covering the sixth conductive layer, and the subsequent steps are the same as the process of forming FIG. 9A in the aforementioned embodiment, and will not be described in detail in the present disclosure.
  • the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the sixth insulating layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • forming the light-emitting structure layer may include: coating a first flat film on the substrate formed with the aforementioned pattern, patterning the first flat film using a patterning process to form a first flat layer, depositing an anode conductive film on the substrate formed with the aforementioned pattern, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, coating a pixel definition film on the substrate formed with the aforementioned pattern, patterning the pixel definition film using a patterning process to form a pixel definition layer, first forming an organic light-emitting layer on the substrate formed with the aforementioned pattern using an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer.
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the material of the pixel definition layer may include polyimide, acryl, or polyethylene terephthalate.
  • the planarization layer may employ an organic material.
  • the anode thin film may employ indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the cathode film may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.
  • the following is an exemplary description of the preparation process of FIG. 10A , which shows a virtual scanning shift register.
  • the virtual scanning shift register includes a first transistor DT1 , a second transistor DT2 , and fourth to eighth transistors DT4 to DT8 .
  • Forming a semiconductor layer pattern on a substrate may include: depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern, as shown in FIG. 25 , which is a schematic diagram of FIG. 10A after forming a semiconductor layer pattern.
  • the semiconductor layer pattern may include an active layer DT11 of a first transistor, an active layer DT21 of a second transistor, and active layers DT41 to DT81 of fourth to eighth transistors.
  • the positions and structures of the active layers DT11 of the first transistor, DT21 of the second transistor, DT61 of the sixth transistor to DT81 of the eighth transistor in FIG25 are the same as those of the active layers T11 of the first transistor, T21 of the second transistor, T61 of the sixth transistor to T81 of the eighth transistor in FIG14.
  • the difference is that the integrated structure of the active layers DT41 of the fourth transistor and DT51 of the fifth transistor in FIG25 may be in an "I".
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 26 and 27 , where FIG. 26 is a schematic diagram of the first conductive layer pattern of FIG. 10A , and FIG. 27 is a schematic diagram of FIG. 10A after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern may include at least a control electrode DT12 of the first transistor, a control electrode DT22 of the second transistor, a control electrode DT42 of the fourth transistor to a control electrode DT82 of the eighth transistor, and a first connection line VL1 .
  • control electrode DT42 of the fourth transistor, the control electrode DT62 of the sixth transistor to the control electrode DT82 of the eighth transistor are an integrated structure, and the control electrode DT12 of the first transistor, the control electrode DT22 of the second transistor and the control electrode DT52 of the fifth transistor can be set separately.
  • shapes of the control electrodes T12 and DT22 of the first and second transistors and the first connection line VL1 in FIG. 26 are the same as those in FIG. 15 .
  • the control electrode DT42 of the fourth transistor may be a comb structure with an opening toward the display area
  • the control electrodes DT62 of the sixth transistor to DT82 of the eighth transistor are located on the side of the comb back of the control electrode DT42 of the fourth transistor away from the display area
  • the control electrode DT62 of the sixth transistor and the control electrode DT72 of the seventh transistor may be a line shape extending along the second direction D2
  • the control electrode DT82 of the eighth transistor may be an "n" type with an opening toward the display area.
  • forming the third insulating layer pattern may include: depositing a second insulating film and a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film and the third insulating film using a patterning process to form a second insulating layer and a third insulating layer covering the first conductive layer, wherein a plurality of via patterns are disposed on the third insulating layer, as shown in FIG. 28 , which is a schematic diagram of FIG. 10A after the third insulating layer pattern is formed.
  • the plurality of via patterns may include at least the first via H1 to the seventeenth via H17.
  • the first via H1 to the eleventh via H11 are opened in the first insulating layer to the third insulating layer, and the twelfth via H12 to the seventeenth via H17 are opened in the second insulating layer and the third insulating layer.
  • the first via H1 exposes the first area of the active layer of the first transistor
  • the second via H2 exposes the second area of the active layer of the first transistor
  • the third via H3 exposes the first area of the active layer of the second transistor
  • the fourth via H4 exposes the second area of the active layer of the second transistor
  • the fifth via H5 exposes the first area of the active layer of the fourth transistor
  • the sixth via H6 exposes the second area of the active layer of the fourth transistor (the second area of the active layer of the fifth transistor)
  • the seventh via H7 exposes the second area of the active layer of the fourth transistor (the second area of the active layer of the fifth transistor).
  • the first area of the active layer of the fifth transistor is exposed
  • the eighth via hole H8 exposes the first area of the active layer of the sixth transistor
  • the ninth via hole H9 exposes the second area of the active layer of the seventh transistor
  • the tenth via hole H10 exposes the first area of the active layer of the eighth transistor
  • the eleventh via hole H11 exposes the second area of the active layer of the eighth transistor
  • the twelfth via hole H12 exposes the control electrode of the first transistor
  • the thirteenth via hole H13 exposes the control electrode of the second transistor
  • the fourteenth via hole H14 exposes the control electrode of the sixth transistor
  • the fifteenth via hole H15 exposes the control electrode of the fifth transistor
  • the sixteenth via hole H16 exposes the control electrode of the fourth transistor
  • the seventeenth via hole H17 exposes the first connecting line.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in FIGS. 29 and 30 , where FIG. 29 is a schematic diagram of the third conductive layer pattern of FIG. 10A , and FIG. 30 is a schematic diagram of FIG. 10A after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may include at least a first clock subsegment GCK1A of a first clock signal line, a first clock subsegment GCK2A of a second clock signal line, a second power line VGL, a first initial subsegment INITL1A of a first initial power supply line, a first initial subsegment INITL2A of a second initial power supply line, a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 and a second electrode T24 of a second transistor, a first electrode T43 and a second electrode T44 of a fourth transistor, a first electrode T53 and a second electrode T54 of a fifth transistor, a first electrode T63 of a sixth transistor, a second electrode T74 of a seventh transistor, and a first electrode T83 and a second electrode T84 of an eighth transistor.
  • the first clock sub-segment GCK2A of the second clock signal line, the first clock sub-segment GCK1A of the first clock signal line, the second power line VGL, the first initial sub-segment INITL1A of the first initial power line, and the first initial sub-segment INITL2A of the second initial power line in Figures 29 and 30 are the same as the first clock sub-segment GCK2A of the second clock signal line, the first clock sub-segment GCK1A of the first clock signal line, the second power line VGL, the first initial sub-segment INITL1A of the first initial power line, and the first initial sub-segment INITL2A of the second initial power line in Figures 20 and 21.
  • the second power line VGL is an integrated structure with the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor.
  • the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor are located on a side of the second power line VGL close to the display area.
  • the integrated structure of the second power line VGL, the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor is connected to the first area of the active layer of the first transistor through the second via hole, to the first area of the active layer of the second transistor through the third via hole, to the second area of the active layer of the second transistor through the fourth via hole, to the second area of the active layer of the seventh transistor through the ninth via hole, to the first area of the active layer of the eighth transistor through the tenth via hole H10, and to the control electrode of the first transistor through the twelfth via hole.
  • the first electrode T13 of the first transistor shown in FIGS. 29 and 30 is the same as the first electrode T13 of the first transistor in FIGS. 20 and 21 .
  • the first electrode T43 and the second electrode T44 of the fourth transistor, the first electrode T53 and the second electrode T54 of the fifth transistor, the first electrode T63 of the sixth transistor and the second electrode T84 of the eighth transistor are an integrated structure, and are connected to the first area of the active layer of the fourth transistor through a fifth via, connected to the second area of the active layer of the fourth transistor (the second area of the active layer of the fifth transistor) through a sixth via, connected to the first area of the active layer of the fifth transistor through a seventh via, connected to the first area of the active layer of the sixth transistor through an eighth via, connected to the second area of the active layer of the eighth transistor through an eleventh via, connected to the control electrode of the second transistor through a thirteenth via, connected to the control electrode of the fifth transistor through a fifteenth via, and connected to the control electrode of the fourth transistor through a sixteenth via.
  • forming the fourth conductive layer may include: depositing a fourth insulating film and a fourth conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film and the fourth conductive film using a patterning process to form a fourth insulating layer covering the third conductive layer and a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 31 and 32 , where FIG. 31 is a schematic diagram of the fourth conductive layer of FIG. 10A , and FIG. 32 is a schematic diagram of forming the fourth conductive layer of FIG. 10A .
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern may include at least: a second clock sub-segment GCK1B of the first clock signal line, a second clock sub-segment GCK2B of the second clock signal line, a first power line VGH, a second initial sub-segment INITL1B of the first initial power line, a second initial sub-segment INITL2B of the second initial power line, a first initial signal line GSTV, and a second initial signal line ESTV.
  • the second clock sub-segment GCK1B of the first clock signal line, the second clock sub-segment GCK2B of the second clock signal line, the first power line VGH, the second initial sub-segment INITL1B of the first initial power line, the second initial sub-segment INITL2B of the second initial power line, the first initial signal line GSTV and the second initial signal line ESTV in Figures 31 and 32 have the same structure as the second clock sub-segment GCK1B of the first clock signal line, the second clock sub-segment GCK2B of the second clock signal line, the first power line VGH, the second initial sub-segment INITL1B of the first initial power line, the second initial sub-segment INITL2B of the second initial power line, the first initial signal line GSTV and the second initial signal line ESTV in Figures 23 and 24, and the difference lies in the spacing between the signal lines.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer is consistent with the preparation process provided in the above embodiment and will not be repeated here.
  • the following is an exemplary description of the preparation process of FIG. 10B , which shows a virtual scanning shift register.
  • the virtual scanning shift register includes a first transistor DT1 , a second transistor DT2 , and a sixth transistor DT6 to an eighth transistor DT8 .
  • Forming a semiconductor layer pattern on a substrate may include: depositing a semiconductor thin film on a substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern, as shown in FIG. 33 , which is a schematic diagram of FIG. 10B after forming a semiconductor layer pattern.
  • the semiconductor layer pattern may include an active layer DT11 of a first transistor, an active layer DT21 of a second transistor, and active layers DT61 to DT81 of sixth to eighth transistors.
  • the active layer DT11 of the first transistor, the active layer DT21 of the second transistor, and the active layer DT61 of the sixth transistor to the active layer DT81 of the eighth transistor in FIG33 are the same in position and structure as the active layer T11 of the first transistor, the active layer T21 of the second transistor, and the active layer T61 of the sixth transistor to the active layer T81 of the eighth transistor in FIG14.
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 34 and 35 , where FIG. 34 is a schematic diagram of the first conductive layer pattern of FIG. 10B , and FIG. 35 is a schematic diagram of FIG. 10B after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern may include at least a control electrode DT12 of a first transistor, a control electrode DT22 of a second transistor, control electrodes DT62 to DT82 of sixth to eighth transistors, a first connection line VL1 and a second connection line VL2.
  • control electrodes T62 of the sixth transistor to DT82 of the eighth transistor are an integrated structure, and the control electrodes DT12 of the first transistor and DT22 of the second transistor are integrated.
  • shapes of the control electrodes T12 and DT22 of the first and second transistors and the first connection line VL1 in FIG. 34 are the same as those of the control electrodes DT12 and DT22 of the first and second transistors and the first connection line VL1 in FIG. 25 .
  • forming the third insulating layer pattern may include: depositing a second insulating film and a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film and the third insulating film using a patterning process to form a second insulating layer and a third insulating layer covering the first conductive layer, wherein a plurality of via patterns are disposed on the third insulating layer, as shown in FIG. 36 , which is a schematic diagram of FIG. 10B after the third insulating layer pattern is formed.
  • the plurality of via patterns may include at least first to thirteenth vias H1 to H13 .
  • the first to eighth vias H1 to H8 are opened in the first to third insulating layers, and the ninth to thirteenth vias H9 to H13 are opened in the second and third insulating layers.
  • the first via hole H1 exposes the first area of the active layer of the first transistor
  • the second via hole H2 exposes the second area of the active layer of the first transistor
  • the third via hole H3 exposes the first area of the active layer of the second transistor
  • the fourth via hole H4 exposes the second area of the active layer of the second transistor
  • the fifth via hole H5 exposes the first area of the active layer of the sixth transistor
  • the sixth via hole H6 exposes the second area of the active layer of the seventh transistor
  • the seventh via hole H7 exposes the first area of the active layer of the eighth transistor
  • the eighth via hole H8 exposes the second area of the active layer of the eighth transistor
  • the ninth via hole H9 exposes the control electrode of the first transistor
  • the tenth via hole H10 exposes the control electrode of the second transistor
  • the eleventh via hole H11 exposes the integrated structure of the control electrodes of the sixth transistor
  • the twelfth via hole H12 exposes the first connecting line
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in FIGS. 37 and 38 , where FIG. 37 is a schematic diagram of the third conductive layer pattern of FIG. 10B , and FIG. 38 is a schematic diagram of FIG. 10B after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may include at least: a first clock sub-segment GCK1A of the first clock signal line, a first clock sub-segment GCK2A of the second clock signal line, a second power line VGL, a first initial sub-segment INITL1A of the first initial power supply line, a first initial sub-segment INITL2A of the second initial power supply line, a first electrode T13 and a second electrode T14 of the first transistor, a first electrode T23 and a second electrode T24 of the second transistor, a first electrode T63 of the sixth transistor, a second electrode T74 of the seventh transistor, and a first electrode T83 and a second electrode T84 of the eighth transistor.
  • the first clock sub-segment GCK2A of the second clock signal line, the first clock sub-segment GCK1A of the first clock signal line, the second power line VGL, the first initial sub-segment INITL1A of the first initial power line, and the first initial sub-segment INITL2A of the second initial power line in Figures 37 and 38 are the same as the first clock sub-segment GCK2A of the second clock signal line, the first clock sub-segment GCK1A of the first clock signal line, the second power line VGL, the first initial sub-segment INITL1A of the first initial power line, and the first initial sub-segment INITL2A of the second initial power line in Figures 20 and 21.
  • the second power line VGL is an integrated structure with the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor.
  • the 37 and 28 is the same as the second power line VGL, the second electrode of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the second electrode T74 of the seventh transistor, and the first electrode T83 of the eighth transistor in FIGS. 30 and 31 , and is connected to the first region of the active layer of the first transistor through the second via hole, to the first region of the active layer of the second transistor through the third via hole, to the second region of the active layer of the second transistor through the fourth via hole, to the second region of the active layer of the seventh transistor through the sixth via hole, to the first region of the active layer of the eighth transistor through the seventh via hole, and to the control electrode of the first transistor through the ninth via hole.
  • the first electrode T13 of the first transistor, the first electrode T63 of the sixth transistor and the second electrode T84 of the eighth transistor are an integrated structure, and are connected to the first area of the active layer of the first transistor through a first via, are connected to the first connecting line through a twelfth via, are connected to the first area of the active layer of the sixth transistor through a fifth via, are connected to the second area of the active layer of the eighth transistor through an eighth via, the integrated structure of the control electrode of the sixth transistor, the control electrode of the seventh transistor and the control electrode of the eighth transistor are exposed through an eleventh via, and are connected to the second connecting line through a thirteenth via.
  • forming the fourth conductive layer may include: depositing a fourth insulating film and a fourth conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film and the fourth conductive film using a patterning process to form a fourth insulating layer covering the third conductive layer and a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 39 and 40 , where FIG. 39 is a schematic diagram of the fourth conductive layer of FIG. 10B , and FIG. 40 is a schematic diagram of forming the fourth conductive layer of FIG. 10B .
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern may include at least: a second clock sub-segment GCK1B of the first clock signal line, a second clock sub-segment GCK2B of the second clock signal line, a first power line VGH, a second initial sub-segment INITL1B of the first initial power supply line, a second initial sub-segment INITL2B of the second initial power supply line, a first initial signal line GSTV, and a second initial signal line ESTV.
  • the second clock sub-segment GCK1B of the first clock signal line, the second clock sub-segment GCK2B of the second clock signal line, the first power line VGH, the second initial sub-segment INITL1B of the first initial power line, the second initial sub-segment INITL2B of the second initial power line, the first initial signal line GSTV and the second initial signal line ESTV in Figures 39 and 40 have the same structure as the second clock sub-segment GCK1B of the first clock signal line, the second clock sub-segment GCK2B of the second clock signal line, the first power line VGH, the second initial sub-segment INITL1B of the first initial power line, the second initial sub-segment INITL2B of the second initial power line, the first initial signal line GSTV and the second initial signal line ESTV in Figures 23 and 24, and the difference lies in the spacing between the signal lines.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer is consistent with the preparation process provided in the above embodiment and will not be repeated here.
  • the width of the scanning shift register in the display substrate provided by the embodiment of the present disclosure may be approximately 200 micrometers to 220 micrometers.
  • the width of the scanning shift register in the display substrate may be approximately 210 micrometers.
  • the load at the same position of the display substrate provided by the embodiment of the present disclosure and the reference display substrate and the rising edge time and falling edge of the data signal were compared, and it was found that the difference between the two was not large, that is, the display substrate provided by the embodiment of the present disclosure reduces the area occupied by the border area of the display substrate without affecting the image quality, thereby achieving a narrow border.
  • the display substrate of the embodiment of the present disclosure can be applied to display products of any resolution.
  • the embodiment of the present disclosure further provides a display device, including: a display substrate.
  • the display device may be a monitor, a television, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product, or any product or component having a display function.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the thickness and size of the layer or microstructure are exaggerated. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种显示基板和显示装置，其中，显示基板包括：基底以及设置在基底上的驱动电路层，基底包括：显示区域(100)和非显示区域(200)，驱动电路层包括：位于显示区域(100)的像素驱动电路(PE)以及位于非显示区域(200)的栅极驱动电路和至少一条初始供电线，初始供电线至少部分沿第一方向(D1)延伸；栅极驱动电路被配置为向像素驱动电路(PE)提供驱动信号，初始供电线被配置为向像素驱动电路(PE)提供初始信号；至少一条初始供电线在基底上的正投影与栅极驱动电路在基底上的正投影至少部分交叠。

Description

显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，特别涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：基底以及设置在所述基底上的驱动电路层，所述基底包括：显示区域和非显示区域，所述驱动电路层包括：位于所述显示区域的像素驱动电路以及位于所述非显示区域的栅极驱动电路和至少一条初始供电线，所述初始供电线至少部分沿第一方向延伸；
所述栅极驱动电路被配置为向像素驱动电路提供驱动信号，所述初始供电线被配置为向像素驱动电路提供初始信号；
至少一条所述初始供电线在基底上的正投影与所述栅极驱动电路在基底上的正投影至少部分交叠。
在示例性实施方式中，所述栅极驱动电路包括：沿第二方向排布的多个驱动电路，所述第一方向与所述第二方向相交；
至少一条所述初始供电线在基底上的正投影与多个驱动电路中靠近显示区域的驱动电路在基底上的正投影至少部分交叠。
在示例性实施方式中，所述像素驱动电路包括：发光晶体管和写入晶体管，所述多个驱动电路包括：发光驱动电路和扫描驱动电路，所述发光驱动电路与发光晶体管电连接，所述扫描驱动电路与写入晶体管电连接，所述扫描驱动电路位于所述发光驱动电路靠近显示区域的一侧；
至少一条初始供电线在基底上的正投影与所述扫描驱动电路在基底上的正投影至少部分交叠。
在示例性实施方式中，所述像素驱动电路包括：发光晶体管、写入晶体管和控制晶体管，所述多个驱动电路包括：发光驱动电路、扫描驱动电路和控制驱动电路，所述发光驱动电路与发光晶体管电连接，所述扫描驱动电路与写入晶体管电连接，所述控制驱动电路与控制晶体管电连接，所述写入晶体管和所述控制晶体管的晶体管类型相反；所述发光驱动电路和所述控制驱动电路位于扫描驱动电路远离显示区域的一侧；
至少一条所述初始供电线在基底上的正投影与所述扫描驱动电路在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一条初始供电线包括：第一条初始供电线至第N条初始供电线，N为大于或者等于1的正整数；
当N大于或者等于2时，N条初始供电线沿第二方向排布，远离显示区域的K条相邻的初始供电线在基底上的正投影与所述扫描驱动电路在基底上的正投影至少部分交叠，K为小于或者等于N的正整数。
在示例性实施方式中，所述驱动电路层还包括：位于非显示区域的第一时钟信号线、第二时钟信号线、第一初始信号线、第一电源线和第二电源线，所述第一时钟信号线、所述第二时钟信号线、所述第一初始信号线、所述第一电源线和所述第二电源线至少部分沿第一方向延伸；
所述扫描驱动电路分别与第一时钟信号线、第二时钟信号线、第一电源线、第二电源线和第一初始信号线电连接；
所述第二时钟信号线位于所述第一时钟信号线远离显示区域的一侧，所述第二电源线位于所述第一时钟信号线靠近显示区域的一侧，所述第一初始信号线位于所述第二电源线靠近显示区域的一侧，所述第一电源线位于所述 第一初始信号线靠近显示区域的一侧，所述至少一条初始供电线位于所述第一电源线靠近显示区域的一侧。
在示例性实施方式中，所述驱动电路层还包括：位于非显示区域的第二初始信号线，所述第二初始信号线至少部分沿第一方向延伸；
所述发光驱动电路与所述第二初始信号线与电连接，所述第二初始信号线位于第二电源线和第一初始信号线之间。
在示例性实施方式中，所述驱动电路层还包括：位于非显示区域的第一输出信号线和第二输出信号线，所述第一输出信号线和所述第二输出信号线至少部分沿第二方向延伸；
所述第一输出信号线位于扫描驱动电路靠近显示区域的一侧，且分别与扫描驱动电路和像素驱动电路电连接；
所述第二输出信号线穿过所述扫描驱动电路，且分别与像素驱动电路以及发光驱动电路和控制驱动电路中的其中一个驱动电路电连接。
在示例性实施方式中，所述驱动电路层还包括：位于显示区域和非显示区域的第一输出连接线和第二输出连接线，所述第一输出连接线和所述第二输出连接线至少部分沿第二方向延伸；
所述第一输出连接线，分别与第一输出信号线和像素驱动电路电连接；
所述第二输出连接线，分别与第二输出信号线和像素驱动电路电连接。
在示例性实施方式中，当N＝2时，所述驱动电路层还包括：第三输出连接线和第四输出连接线，所述第三输出连接线和所述第四输出连接线至少部分沿第二方向延伸；
所述第三输出连接线，分别与第一条初始供电线和像素驱动电路电连接；
所述第四输出连接线，分别与第二条初始供电线和像素驱动电路电连接。
在示例性实施方式中，所述显示区域的边界包括弧形边界，位于弧形边界外侧的非显示区域称为圆角区域；
所述扫描驱动电路包括：多个扫描移位寄存器和多个虚拟扫描移位寄存器，多个扫描移位寄存器级联，多个虚拟扫描移位寄存器穿插设置在多个扫 描移位寄存器之间；
多个虚拟扫描移位寄存器至少部分位于圆角区域。
在示例性实施方式中，所述扫描移位寄存器包括：多个晶体管和多个电容；
与扫描驱动电路存在交叠的初始供电线在基底上的正投影与所述多个电容在基底上的正投影至少部分交叠。
在示例性实施方式中，与扫描驱动电路存在交叠的初始供电线远离显示区域的边界与显示区域之间的距离小于多个电容中的至少一个电容远离显示区域的边界与显示区域之间的距离。
在示例性实施方式中，所述虚拟扫描移位寄存器中的晶体管的数量小于或者等于所述扫描移位寄存器中的晶体管的数量；
所述虚拟扫描移位寄存器的宽度小于或者等于所述扫描移位寄存器的宽度。
在示例性实施方式中，位于虚拟扫描移位寄存器侧面的第二时钟信号线的远离显示区域的边界和至少一条初始供电线中靠近显示区域的初始供电线的靠近显示区域的边界之间的距离小于位于扫描移位寄存器侧面的第二时钟信号线的远离显示区域的边界和至少一条初始供电线中靠近显示区域的初始供电线的靠近显示区域的边界之间的距离。
在示例性实施方式中，所述驱动电路层包括：依次叠设的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；
所述半导体层至少包括：多个晶体管的有源层；
所述第一导电层至少包括：多个晶体管的控制极和多个电容的第一极板；
所述第二导电层至少包括：多个电容的第二极板、第一输出信号线和第三输出信号线；
所述第三导电层至少包括：第二电源线以及至少一个晶体管的第一极和第二极以及第四输出信号线；
所述第四导电层至少包括：第一初始信号线、第二初始信号线和第一电 源线。
在示例性实施方式中，所述驱动电路层还包括：位于第四导电层远离基底一侧的第五导电层；
所述第五导电层至少包括：第一输出连接线、第二输出连接线、第三输出连接线和第四输出连接线。
在示例性实施方式中，所述初始供电线为单层结构，且所述初始供电线位于第四导电层。
在示例性实施方式中，所述初始供电线包括：相互连接的第一初始子段和第二初始子段，所述第一初始子段在基底上的正投影与所述第二初始子段在基底上的正投影至少部分交叠；
所述第一初始子段位于第三导电层，所述第二初始子段位于第四导电层。
在示例性实施方式中，所述第一时钟信号线和所述第二时钟信号线为单层结构，且所述第一时钟信号线和所述第二时钟信号线位于第四导电层。
在示例性实施方式中，时钟信号线包括：相互连接的第一时钟子段和第二时钟子段，所述时钟信号线包括第一时钟信号线和第二时钟信号线，所述第一时钟子段在基底上的正投影与所述第二时钟子段在基底上的正投影至少部分交叠；
所述第一时钟子段位于第三导电层，所述第二时钟子段第四导电层靠近基底的一侧。
在示例性实施方式中，所述第二输出信号线为单层结构，且所述第二输出信号线位于第二导电层。
在示例性实施方式中，所述驱动电路层还包括：位于所述第二导电层和所述第三导电层之间的第六导电层；
所述第二输出信号线包括多个第一输出子段和多个第二输出子段，相邻第一输出子段通过第二输出子段电连接，相邻第二输出子段包括第一输出子段电连接，第二输出子段在基底上的正投影与电连接的第一输出子段在基底上的正投影至少部分交叠，第一输出子段在基底上的正投影与电连接的第二输出子段在基底上的正投影至少部分交叠；
所述第一输出子段位于第二导电层，所述第二输出子段位于第六导电层。
第二方面，本公开还提供了一种显示装置，包括上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1A为一种显示基板的结构示意图；
图1B为一种显示基板的区域划分的示意图；
图2为另一显示基板的结构示意图；
图3A为一个像素驱动电路的等效电路示意图；
图3B为图3A提供的像素驱动电路的工作时序图；
图4A为另一像素驱动电路的等效电路示意图；
图4B为图4A提供的像素驱动电路的工作时序图；
图5A为本公开实施例提供的显示基板的结构示意图一；
图5B为图5A提供的显示基板的局部示意图；
图6A为本公开实施例提供的显示基板的结构示意图二；
图6B为图6A提供的显示基板的局部示意图；
图7A为一种显示基板中的移位寄存器的等效电路图；
图7B为图7A提供的移位寄存器的时序图；
图8A为一种虚拟扫描移位寄存器的等效电路图；
图8B为另一虚拟扫描移位寄存器的等效电路图；
图9A为显示基板的一个局部示意图；
图9B为图9A提供的显示基板在圆角区域的部分示意图；
图10A为显示基板的另一局部示意图；
图10B为显示基板的又一局部示意图；
图11为图10A和图10B提供的显示基板在圆角区域的部分示意图；
图12为再一显示基板的局部示意图；
图13为第二输出信号线的结构示意图；
图14为图9A形成半导体层图案后的示意图；
图15为图9A的第一导电层图案的示意图；
图16为图9A形成第一导电层图案后的示意图；
图17为图9A的第二导电层图案的示意图；
图18为图9A形成第二导电层图案后的示意图；
图19为图9A形成第三绝缘层图案后的示意图；
图20为图9A的第三导电层图案的示意图；
图21为图9A形成第三导电层图案后的示意图；
图22为图9A形成第四绝缘层图案后的示意图；
图23为图9A的第四导电层的示意图；
图24为图9A的形成第四导电层的示意图；
图25为图10A形成半导体层图案后的示意图；
图26为图10A的第一导电层图案的示意图；
图27为图10A形成第一导电层图案后的示意图；
图28为图10A形成第三绝缘层图案后的示意图；
图29为图10A的第三导电层图案的示意图；
图30为图10A形成第三导电层图案后的示意图；
图31为图10A的第四导电层的示意图；
图32为图10A的形成第四导电层的示意图；
图33为图10B形成半导体层图案后的示意图；
图34为图10B的第一导电层图案的示意图；
图35为图10B形成第一导电层图案后的示意图；
图36为图10B形成第三绝缘层图案后的示意图；
图37为图10B的第三导电层图案的示意图；
图38为图10B形成第三导电层图案后的示意图；
图39为图10B的第四导电层的示意图；
图40为图10B形成第四导电层的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述， 而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层” 换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示基板拥有高分辨率、高反应速度、高亮度、高开口率等优势，具有广泛的应用前景。为了获得更佳的视觉体验，窄边框是显示主要的发展方向。显示基板中设置有驱动电路以驱动像素驱动电路进行发光，从而实现显示。显示基板无法实现窄边框。
图1A为一种显示基板的结构示意图，图1B为一种显示基板的区域划分的示意图，图2为另一显示基板的结构示意图。如图1A、图1B和图2所示，显示基板可以包括：显示区域100和非显示区域200，显示区域100的边界包括至少一个弧形边界C，非显示区域包括：位于弧形边界C的外侧的圆角区域CR。
在示例性实施方式中，显示区域的边界的形状可以为圆角矩形，本公开对此不作任何限定。
本公开提供的显示基板可以实现四边大角度弯折功能，改善模组贴合褶皱问题，提升了产品良率。
在示例性实施方式中，如图1A和图2所示，显示区域可以包括：阵列排布的像素单元P，至少一个像素单元包括至少三个子像素，至少一个子像素包括：像素驱动电路和发光器件。位于同一子像素中的像素驱动电路与发光器件电连接，且设置为驱动发光器件发光。
在示例性实施方式中，像素单元中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。
在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、 五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)或者量子点发光二极管(QLED)。其中，OLED可以包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，如图1A所示，非显示区域200可以包括：位于显示区域100一侧的绑定区域和位于显示区域100其他侧的边框区域。
在示例性实施方式中，绑定区域可以包括沿着远离显示区域方向依次设置的引线区、弯折区和复合电路区，引线区连接到显示区域100，弯折区连接到引线区，复合电路区连接到弯折区。
在示例性实施方式中，引线区可以设置多条引出线，一部分多条引出线的一端与显示区域100中的多条数据扇出线对应连接，另一部分多条引出线的一端与显示区域100中的多条数据线对应连接，多条引出线的另一端跨过弯折区连接复合电路区的集成电路，使得集成电路通过引出线和数据扇出线将数据信号施加到数据线。
在示例性实施方式中，弯折区可以以一曲率弯曲，可以将复合电路区的 表面反转，即复合电路区朝向上方的表面可以通过弯折区的弯曲转换成面朝向下方。在示例性实施方式中，当弯折区被弯曲时，复合电路区可以与显示区域100重叠。
在示例性实施方式中，复合电路区可以包括防静电区、驱动芯片区和绑定引脚区，集成电路(Integrate Circuit，简称IC)可以绑定连接在驱动芯片区，柔性电路板(Flexible Printed Circuit，简称FPC)可以绑定连接在绑定引脚区。
在示例性实施方式中，集成电路可以产生用于驱动子像素所需的驱动信号，并且可以将驱动信号提供给在显示区域100中的子像素。例如，驱动信号可以是驱动子像素发光亮度的数据信号。在示例性实施方式中，集成电路可以通过各向异性导电膜或者其它方式绑定连接在驱动芯片区。在示例性实施方式中，绑定引脚区可以设置包括多个引脚(PIN)的焊盘，柔性电路板可以绑定连接到焊盘上。
在示例性实施方式中，如图2所示，显示基板可以包括时序控制器、数据驱动电路、栅极驱动电路和像素阵列，时序控制器分别与数据驱动电路和栅极驱动电路连接，数据驱动电路分别与数据信号线Data连接，栅极去哦多功能电路与栅线连接，栅线可以包括发光信号线EM、扫描信号线Gate或者Scan中的一种或者多种。像素驱动电路可以分别与栅线和数据信号线连接。
在示例性实施方式中，时序控制器可以将适合于数据驱动电路的规格的灰度值和控制信号提供到数据驱动电路，可以将适合于栅极驱动电路的规格的时钟信号、起始信号等提供到栅极驱动电路，可以将适合于发光驱动电路的规格的时钟信号、发射停止信号等提供到发光驱动电路。数据驱动电路可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线的数据电压。例如，数据驱动电路可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线。
在示例性实施方式中，栅极驱动电路可以通过从时序控制器接收时钟信号、起始信号等来产生将提供到栅线的扫描信号。例如，栅极驱动电路可以将具有导通电平脉冲的信号顺序地提供到栅线。例如，栅极驱动电路可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电 平脉冲形式提供的起始信号传输到下一级电路的方式产生扫描信号。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。
在示例性实施方式中，图3A为一个像素驱动电路的等效电路示意图。如图3A所示，像素驱动电路可以包括7个晶体管(第一晶体管M1到第七晶体管M7)、1个电容C和8个信号线(数据信号线Data、扫描信号线Gate、复位信号线Reset、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、高电平电源线VDD和低电平电源线VSS)。
如图3A所示，电容C的第一极板与高电平电源线VDD连接，电容C的第二极板与第一节点N1连接。第一晶体管M1的控制极与复位信号线Reset连接，第一晶体管M1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第一节点N1连接；第二晶体管M2的控制极与扫描信号线Gate连接，第二晶体管M2的第一极与第一节点N1连接，第二晶体管M2的第二极与第二节点N2连接。第三晶体管M3的控制极与第一节点N1连接，第三晶体管M3的第一极与第二节点N2连接，第三晶体管M3的第二极与第三节点N3连接。第四晶体管M4的控制极与扫描信号线GATE连接，第四晶体管M4的第一极与数据信号线Data连接，第四晶体管M4的第二极与第二节点N2连接。第五晶体管M5的控制极与发光信号线EM连接，第五晶体管M5的第一极与高电平电源线VDD连接，第五晶体管M5的第二极与第二节点N2连接；第六晶体管M6的控制极与发光信号线EM连接，第六晶体管M6的第一极与第三节点N3连接，第六晶体管M6的第二极与发光器件L的第一极连接。第七晶体管M7的控制极与复位信号线Reset或者扫描信号线Gate连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件的第二极与低电平电源线VSS连接，图3A是以第七晶体管M7的控制极与复位信号线Reset为例进行说明的。
在示例性实施方式中，第一晶体管M1可以称为节点复位晶体管，当复位信号线Reset输入有效电平信号时，第一晶体管M1将初始化电压传输到第一节点N1，以使第一节点N1的电荷量初始化。
在示例性实施方式中，第二晶体管M2可以称为补偿晶体管，当控制信号线SL输入有效电平信号时，第二晶体管M2将第二节点N2的信号传输到第一节点N1，以对第一节点N1的信号进行补偿。
在示例性实施方式中，第三晶体管M3可以称为驱动晶体管，第三晶体管M3根据控制极与第一极之间的电位差来确定在高电平电源线VDD与低电平电源线VSS之间流动的驱动电流。
在示例性实施方式中，第四晶体管M4可以称为写入晶体管等，当扫描信号线Gate输入有效电平信号时，第四晶体管M4使数据信号线Data的数据电压输入到第三节点N3。
在示例性实施方式中，第五晶体管M5和第六晶体管M6可以称为发光晶体管。当发光信号线EM输入有效电平信号时，第五晶体管M5和第六晶体管M6通过在高电平电源线VDD与低电平电源线VSS之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，第七晶体管M7可以称为阳极复位晶体管，当复位信号线Reset或者扫描信号线Gate输入有效电平信号时，第七晶体管M7将初始化电压传输到发光器件L的第一极，以使发光器件L的第一极的电荷量初始化。
在示例性实施方式中，高电平电源线VDD的信号为持续提供高电平信号，低电平电源线VSS的信号为低电平信号。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管M1到第七晶体管M7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管M1到第七晶体管M7可以包括P型晶体管和N型 晶体管。
在示例性实施方式中，第一晶体管M1到第七晶体管M7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施例中，当显示基板为LTPO显示基板时，第一晶体管T1和第二晶体管T2可以为N型晶体管，其余晶体管为P型晶体管。当显示基板为LTPS显示基板时，第一晶体管M1至第七晶体管M7为P型晶体管。
在示例性实施方式中，当显示基板为LTPO显示基板时，第一晶体管T1和第二晶体管T2为N型晶体管时，第一晶体管T1和第二晶体管T2还可以称为控制晶体管，同理，像素驱动电路中的N型晶体管可以称为控制晶体管。
图3B为图3A提供的像素驱动电路的工作时序图，图3B是以图3A中的晶体管均为P型晶体管为例进行说明的。下面通过图3B示例的像素驱动电路的工作过程说明本公开示例性实施例。在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，扫描信号线Gate和发光信号线EM的信号均为高电平信号，复位信号线Reset的信号为低电平信号。复位信号线Reset的信号为高电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号提供至第一节点N1，对电容C进行初始化，清除电容C中原有数据电压,第七晶体管M7导通，第二初始信号线INIT2的初始电压提供至发光器件L的第一极，对发光器件L的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化。扫描信号线Gate和发光信号线EM的信号为高电平信号，第二晶体管M2、第四晶体管M4、第五晶体管M5和第六晶体管M6断开，此阶段发光器件L不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate为低电平信号，发光信号线EM和和复位信号线Reset的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管M3导通。扫描信号线Gate的信号为低电平信号，第二晶体管T2和第四晶体管M4导通，第二晶体管M2和第四晶体管M4导通使得数据信号线Data输出的数据电压经过第二节点N、导通的第三晶体管M3、2第三节点N3和导通的第二晶体管M2提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压，确保发光器件L不发光。复位信号线Reset的信号为高电平信号，第一晶体管M1断开。发光信号线EM的信号为高电平信号，第五晶体管M5和第六晶体管M6断开。
第三阶段A3、称为发光阶段，扫描信号线Gate和复位信号线Reset的信号为高电平信号，发光信号线EM的信号为低电平信号。发光信号线EM的信号为低电平信号，第五晶体管M5和第六晶体管M6导通，高电平电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管M3的控制极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为高电平电源线VDD输出的电源电压。
在示例性实施方式中，图4A为另一像素驱动电路的等效电路示意图。如图4A所示，像素驱动电路可以包括8个晶体管(第一晶体管M1到第八晶体管M8)、1个电容C和9个信号线(数据信号线Data、控制信号线Scan、扫描信号线Gate、复位信号线Reset、发光信号线EM、第一初始信号线INIT1、 第二初始信号线INIT2、高电平电源线VDD和低电平电源线VSS)。
在示例性实施方式中，图4A提供的像素驱动电路适用于LTPO显示基板中。
在示例性实施方式中，电容C的第一极板与高电平电源线VDD连接，电容C的第二极板与第一节点N1连接。第一晶体管M1的控制极与复位信号线Reset连接，第一晶体管M1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第四节点N4连接。第二晶体管M2的控制极与扫描信号线Gate连接，第二晶体管M2的第一极与第四节点N4连接，第二晶体管M2的第二极与第二节点N2连接。第三晶体管M3的控制极与第一节点N1连接，第三晶体管M3的第一极与第二节点N2连接，第三晶体管M3的第二极与第三节点N3连接。第四晶体管M4的控制极与扫描信号线Gate连接，第四晶体管M4的第一极与数据信号线Data连接，第四晶体管M4的第二极与第三节点N3连接。第五晶体管M5的控制极与发光信号线EM连接，第五晶体管M5的第一极与高电平电源线VDD连接，第五晶体管M5的第二极与第三节点N3连接。第六晶体管M6的控制极与发光信号线EM连接，第六晶体管M6的第一极与第二节点N2连接，第六晶体管M6的第二极与发光器件L的第一极连接。第七晶体管M7的控制极与复位信号线Reset连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件L的第二极与低电平电源线VSS连接。第八晶体管M8的控制极与控制信号线SCAN连接，第八晶体管M8的第一极与第一节点N1连接，第八晶体管M8的第二极与第四节点N4连接。
在示例性实施方式中，第七晶体管M7的控制极还可以与扫描信号线Gate连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件L的第一极连接，发光器件L的第二极与低电平电源线VSS连接。
在示例性实施方式中，第一晶体管M1可以称为节点复位晶体管，当复位信号线RESET输入有效电平信号时，第一晶体管M1将初始化电压传输到第一节点N1，以使第一节点N1的电荷量初始化。
在示例性实施方式中，第八晶体管M8可以称为补偿复位晶体管，当控制信号线Scan输入有效电平信号时，第八晶体管M8将第四节点N4的信号传输至第一节点N1，不仅可以将第一节点的电荷量初始化，还可以对第三晶体管M3进行阈值补偿。
在示例性实施方式中，第二晶体管M2可以称为补偿晶体管，当扫描信号线Gate输入有效电平信号时，第二晶体管M2使第二节点N2的信号写入至第四节点N4。
在示例性实施方式中，第三晶体管M3可以称为驱动晶体管，第三晶体管M3根据控制极与第一极之间的电位差来确定在高电平电源端VDD与低电平电源端VSS之间流动的驱动电流。
在示例性实施方式中，第四晶体管M4可以称为写入晶体管，当扫描信号线GATE输入有效电平信号时，第四晶体管M4使数据信号线Data的数据电压输入到像素驱动电路。
在示例性实施方式中，第五晶体管M5和第六晶体管M6可以称为发光晶体管。当发光信号线EM输入有效电平信号时，第五晶体管M5和第六晶体管M6通过在高电平电源线VDD与低电平电源线VSS之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，第七晶体管M7可以称为阳极复位晶体管，当复位信号线Reset或者扫描信号线Gate输入有效电平信号时，第七晶体管M7将初始化电压传输到发光器件L的第一极，以使发光器件L的第一极的电荷量初始化。
在示例性实施方式中，高电平电源线VDD的信号为持续提供高电平信号，低电平电源线VSS的信号为低电平信号。
在示例性实施方式中，第八晶体管M8为金属氧化物晶体管，且为N型晶体管，第一晶体管M1至第七晶体管M7为低温多晶硅晶体管，且为P型晶体管。
在示例性实施方式中，第八晶体管M8可以称为控制晶体管。
在示例性实施方式中，第八晶体管M8为氧化物晶体管可以减少漏电流， 提升像素驱动电路的性能，可以降低像素驱动电路的功耗。
图4B为图4A提供的像素驱动电路的工作时序图。下面通过图4B示例的像素驱动电路的工作过程说明本公开示例性实施例。像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，控制信号线Scan、发光信号线EM和扫描信号线Gate的信号均为高电平信号，复位信号线Reset的信号为低电平信号。复位信号线Reset的信号为低电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号提供至第四节点N4，第七晶体管M7导通，第二初始信号线INIT2的初始电压提供至发光器件L的第一极，对发光器件L的第一极进行初始化(复位)，例如：清空其内部的预存电压，完成初始化，确保发光器件L不发光。控制信号线Scan的信号为高电平信号，第八晶体管M8导通，第四节点N4的信号提供至第一节点N1，对电容C进行初始化，清除电容C中原有数据电压。扫描信号线Gate和发光信号线EM的信号为高电平信号，第二晶体管M2、第四晶体管M4、第五晶体管M5和第六晶体管M6第七晶体管M7截止，此阶段，发光器件L不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate的信号为低电平信号，复位信号线Reset、发光信号线EM和控制信号线Scan的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管M3导通。扫描信号线Gate的信号为低电平信号，第二晶体管M2和第四晶体管M4导通，控制信号线Scan的信号为高电平信号，第八晶体管M8导通。第二晶体管M2、第四晶体管M4和第八晶体管M8导通使得数据信号线Data输出的数据电压经过第三节点N3、导通的第三晶体管M3、第二节点N2、导通的第二晶体管M2、第四节点N4和导通的第八晶体管M8提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压。复位信号线Reset的信号为低电平信号，第一晶体管M1和第七晶体管M7断开。发光信号线EM的信号为高电平信号，第五晶体管M5和第六晶体管M6断开。
第三阶段A3、称为发光阶段，控制信号线Scan和发光信号线EM的信号均为低电平信号，扫描信号线Gate和复位信号线Reset的信号为高电平信号。复位信号线Reset的信号为低电平信号，第一晶体管M1和第七晶体管M7截止。控制信号线SCAN为低电平信号、扫描信号线GATE和复位信号线Reset的信号为高电平信号，第二晶体管M2、第四晶体管M4和第八晶体管M8截止。发光信号线EM的信号为低电平信号，第五晶体管M5和第六晶体管M6导通，高电平电源端VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管M3的控制极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为高电平电源端VDD输出的电源电压。
图5A为本公开实施例提供的显示基板的结构示意图一，图5B为图5A提供的显示基板的局部示意图，图6A为本公开实施例提供的显示基板的结构示意图二，图6B为图6A提供的显示基板的局部示意图。如图5A、图5B、图6A和图6B所示，本公开实施例提供的显示基板可以包括：基底以及设置在基底上的驱动电路层，基底可以包括：显示区域100和非显示区域200，驱动电路层可以包括：位于显示区域100的像素驱动电路PE以及位于非显示区域200的栅极驱动电路和至少一条初始供电线，初始供电线至少部分沿第一方向D1延伸。
在示例性实施方式中，至少一条初始供电线包括：第一条初始供电线至第N条初始供电线，N为大于或者等于1的正整数；当N大于或者等于2时，N条初始供电线沿第二方向D2排布，图5A、图5B、图6A和图6B是以两条初始供电线，且两条初始供电线分别为第一条初始供电线INITL1和 第二条初始供电线INITL2为例进行说明的。
在示例性实施方式中，栅极驱动电路被配置为向像素驱动电路P提供驱动信号，初始供电线被配置为向像素驱动电路提供初始信号。
在示例性实施方式中，至少一条初始供电线在基底上的正投影与栅极驱动电路在基底上的正投影至少部分交叠，图5A、图5B、图6A和图6B是以第二条初始供电线INITL2与栅极驱动电路交叠为例进行说明的。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，显示基板可以为LTPO显示基板或者LTPS显示基板。
在示例性实施方式中，显示基板中的驱动电路可以为两种、三种或者多种，取决于显示基板的结构，本公开对此不作任何限定。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)或者量子点发光二极管(QLED)。
在示例性实施方式中，显示区域包括：相对设置的第一侧和第二侧，栅极驱动电路可以位于显示区域的第一侧和/或第二侧。图5A和图6A是以栅极驱动电路位于显示区域的一侧为例进行说明的。
在示例性实施方式中，驱动电路层还可以包括：至少部分位于显示区域的至少一条初始信号线，初始信号线可以至少部分沿第二方向延伸，至少一条初始信号线与至少一条初始供电线一一对应，初始信号线与对应的初始供电线电连接。
在示例性实施方式中，显示基板还可以包括：设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，发光结构层可以包括阳极、像素定义层、有机发光层和阴极304，阳极通过过孔与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，触控结构层可以包括设置在封装结构层上的第一触控绝缘层、设置在第一触控绝缘层上的第一触控金属层、覆盖第一触控金属层的第二触控绝缘层、设置在第二触控绝缘层上的第二触控金属层44和覆盖第二触控金属层的触控保护层，第一触控金属层可以包括多个桥接电极，第二触控金属层可以包括多个第一触控电极和第二触控电极，第一触控电极或第二触控电极可以通过过孔与桥接电极连接。
本公开通过至少一条初始供电线在基底上的正投影与栅极驱动电路在基底上的正投影至少部分交叠，可以减少显示基板的边框区域所占用的面积，实现窄边框。
在示例性实施方式中，栅极驱动电路可以包括：沿第二方向排布的多个驱动电路，第一方向与第二方向相交。至少一条初始供电线在基底上的正投影与多个驱动电路中靠近显示区域的驱动电路在基底上的正投影至少部分交叠。
在示例性实施方式中，多个驱动电路的位置关系可以根据显示基板的结构以及功能确定，本公开对此不作任何限定。
在示例性实施方式中，驱动电路可以包括多个级联的移位寄存器。
在示例性实施方式中，如图6A和图6B所示，像素驱动电路包括：发光晶体管和写入晶体管。多个驱动电路可以包括：发光驱动电路和扫描驱动电路，发光驱动电路与发光晶体管电连接，扫描驱动电路与写入晶体管电连接，扫描驱动电路位于发光驱动电路靠近显示区域100的一侧，此时，至少一条 初始供电线在基底上的正投影与扫描驱动电路在基底上的正投影至少部分交叠，图6A和图6B是以第二条初始供电线INITL2与扫描驱动电路交叠为例进行说明的。
在示例性实施方式中，发光驱动电路可以包括：多个级联的发光移位寄存器EM-GOA，扫描驱动电路可以包括：多个扫描移位寄存器Pgate-GOA和多个虚拟扫描移位寄存器DPgate-GOA。
在示例性实施方式中，驱动电路层还可以包括：至少部分位于显示区域的发光信号线和扫描信号线。发光移位寄存器通过发光信号线与像素驱动电路电连接，扫描移位寄存器通过扫描信号线与像素驱动电路电连接，虚拟扫描移位寄存器不与扫描信号线电连接。
在示例性实施方式中，如图5A和图5B所示，像素驱动电路包括：发光晶体管、写入晶体管和控制晶体管。多个驱动电路可以包括：发光驱动电路、扫描驱动电路和控制驱动电路，发光驱动电路与发光晶体管电连接，扫描驱动电路与写入晶体管电连接，控制驱动电路与控制晶体管电连接，写入晶体管和控制晶体管的晶体管类型相反；发光驱动电路和控制驱动电路位于扫描驱动电路远离显示区域的一侧。至少一条初始供电线在基底上的正投影与扫描驱动电路在基底上的正投影至少部分交叠。图6A和图6B是以第二条初始供电线INITL2与扫描驱动电路交叠为例进行说明的。
在示例性实施方式中，控制晶体管可以为像素驱动电路中的N型晶体管。
在示例性实施方式中，发光驱动电路可以控制驱动电路靠近显示区域的一侧，或者可以位于控制驱动电路远离显示区域的一侧，图5A和图5B是以发光驱动电路位于控制驱动电路远离显示区域的一侧。
在示例性实施方式中，如图6B所示，发光驱动电路可以包括：多个级联的发光移位寄存器EM-GOA，控制驱动电路可以包括：多个级联的控制移位寄存器Ngate-GOA，扫描驱动电路可以包括：多个扫描移位寄存器Pgate-GOA和多个虚拟扫描移位寄存器DPgate-GOA。
在示例性实施方式中，如图5B和图6B所示，多个扫描移位寄存器Pgate-GOA级联，多个DPgate-GOA虚拟扫描移位寄存器穿插设置在多个扫描移位寄存器Pgate-GOA之间，多个虚拟扫描移位寄存器至少部分位于圆角 区域。
在示例性实施方式中，远离显示区域的K条相邻的初始供电线在基底上的正投影与扫描驱动电路在基底上的正投影至少部分交叠，K为小于或者等于N的正整数。示例性地，第一条初始供电线和第二条初始供电线在基底上的正投影可以均与扫描驱动电路在基底上的正投影至少部分交叠。
在示例性实施方式中，扫描移位寄存器或者虚拟扫描移位寄存器可以包括：多个晶体管和多个电容，扫描移位寄存器或者虚拟扫描移位寄存器的电路结构可以为8T2C，本公开对此不作任何限定。
图7A为一种显示基板中的移位寄存器的等效电路图，图7B为图7A提供的移位寄存器的时序图，移位寄存器可以为扫描移位寄存器或者虚拟扫描移位寄存器。如图7A所示，移位寄存器包括：第一晶体管T1至第八晶体管T8、第一电容C1和第二电容C2。
在示例性实施方式中，第一晶体管T1的控制极与第一时钟信号端CK1电连接，第一晶体管T1的第一极与输入端IN电连接，第一晶体管T1的第二极与第一节点G1电连接；第二晶体管T2的控制极与第一节点G1电连接，第二晶体管T2的第一极与第一时钟信号端CK1电连接，第二晶体管T2的第二极与第二节点G2电连接；第三晶体管T3的控制极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与第二电源端V2电连接，第三晶体管T3的第二极与第二节点G2电连接；第四晶体管T4的控制极与第二节点G2电连接，第四晶体管T4的第一极与第一电源端V1电连接，第四晶体管T4的第二极与输出端OUT电连接；第五晶体管T5的控制极与第三节点G3电连接，第五晶体管T5的第一极与第二时钟信号端CK2电连接，第五晶体管T5的第二极与输出端OUT电连接；第六晶体管T6的控制极与第二节点G2电连接，第六晶体管T6的第一极与第一电源端VH电连接，第六晶体管T6的第二极与第七晶体管T7的第一极电连接；第七晶体管T7的控制极与第二时钟信号端CK2电连接，第七晶体管T7的第二极与第一节点G1电连接；第八晶体管T8的控制极与第二电源端V2电连接，第八晶体管T8的第一极与第一节点G1电连接，第八晶体管T8的第二极与第三节点G3电连接；第一电容C1的第一极板C11与第一电源端V1电连接，第一电容C1的第二极 板C12与第二节点G2电连接；第二电容C2的第一极板C21与输出端OUT电连接，第二电容C2的第二极板C22与第三节点G3电连接。
在示例性实施方式中，第一晶体管T1至第八晶体管T8可以为P型晶体管或者可以为N型晶体管。
在示例性实施方式中，第一电源端V1持续提供高电平信号，第二电源端V2持续提供低电平信号。
以第一晶体管T1至第八晶体管T8为P型晶体管为例，如图7B所示，一种示例性实施例提供的移位寄存器的工作过程包括以下阶段：
在输入阶段B1，第一时钟信号端CK1和输入端IN的信号为低电平信号，第二时钟信号端CK2的信号为高电平信号。由于第一时钟信号端CK1的信号为低电平信号，第一晶体管T1导通，输入端IN的信号经由第一晶体管T1传输至第一节点G1。由于第八晶体管T8的信号接收第二电源端V2的低电平信号，从而第八晶体管T8处于开启状态。第三节点G3的电平可以第五晶体管T5导通，第二时钟信号端CK2的信号经由第五晶体管T5传输至输出端OUT，即在输入阶段B1，输出端OUT为高电平信号的第二时钟信号端CK2的信号。另外，由于第一时钟信号端CK1的信号为低电平信号，第三晶体管T3导通，第二电源端V2的低电平信号经由第三晶体管T3传输至第二节点G2。此时，第四晶体管T4和第六晶体管T6均导通。由于第二时钟信号端CK2的信号为高电平信号，第七晶体管T7截止。
在输出阶段B2，第一时钟信号端CK1的信号为高电平信号，第二时钟信号端CK2的信号为低电平信号，输入端IN的信号为高电平信号。第五晶体管T5导通，第二时钟信号端CK2的信号经由第五晶体管T5作为输出端OUT的信号。在输出阶段B2，第二电容C2的连接输出端OUT的一端的电平变为第二电源端V2的信号，由于第二电容C2的自举作用，第八晶体管T8截止，第五晶体管T5可以更好地打开，输出端OUT的信号为低电平信号。另外，第一时钟信号端CK1的信号为高电平信号，从而第一晶体管T1和第三晶体管T3均截止。第二晶体管T2导通，第一时钟信号端CK1的高电平信号经由第二晶体管T2传输至第二节点G2，由此，第四晶体管T4和第六晶体管T6均截止。由于第二时钟信号端CK2的信号为低电平信号，第 七晶体管T7导通。
在缓冲阶段B3，第一时钟信号端CK1和第二时钟信号端CK2的信号均为高电平信号，输入端IN的信号为高电平信号，第五晶体管T5导通，第二时钟信号端CK2经由第五晶体管T5作为输出信号。由于第二电容C2的自举作用，第一节点G1的电平变为V2-Vth。另外，第一时钟信号端CK1的信号为高电平信号，从而第一晶体管T1和第三晶体管T3均截止，第八晶体管T8导通，第二晶体管T2导通，第一时钟信号端CK1的高电平信号经由第二晶体管T2传输至第二节点G2，由此，第四晶体管T4和第六晶体管T6均截止。由于第二时钟信号端CK2的信号为高电平信号，第七晶体管T7截止。
在稳定阶段B4的第一子阶段B41中，第一时钟信号端CK1的信号为低电平信号，第二时钟信号端CK2和输入端IN的信号为高电平信号。由于第一时钟信号端CK1的信号为低电平信号，第一晶体管T1导通，输入端IN的信号经由第一晶体管T1传输至第一节点G1，第二晶体管T2截止。由于第八晶体管T8处于开启状态，第五晶体管T5截止。由于第一时钟信号端CK1的信号为低电平，第三晶体管T3导通，第四晶体管T4和第六晶体管T6均导通，第一电源端V1的高电平信号经由第四晶体管T4传输至输出端OUT，即输出端OUT的信号为高电平信号。
在稳定阶段B4的第二子阶段B42中，第一时钟信号端CK1的信号为高电平信号，第二时钟信号端CK2的信号为低电平信号，输入端IN的信号为高电平信号。第五晶体管T5和第二晶体管T2均截止。第一时钟信号端CK1的信号为高电平信号，从而第一晶体管T1和第三晶体管T3均截止，由于第一电容C1的保持作用下，第四晶体管T4和第六晶体管T6均导通，高电平信号经由第四晶体管T4传输至输出端OUT，即输出端OUT的信号为高电平信号。
在第二子阶段B42中，由于第二时钟信号端CK2的信号为低电平信号，第七晶体管T7导通，从而高电平信号经由第六晶体管T6和第七晶体管T7被传输至第三节点G3和第一节点G1，以使第三节点G3和第一节点G1的信号保持为高电平信号。
在第三子阶段B43中，第一时钟信号端CK1和第二时钟信号CK2的信 号均为高电平信号，输入端IN的信号为高电平信号。第五晶体管T5和第二晶体管T2截止。第一时钟信号端CK1的信号为高电平信号，从而第一晶体管T1和第三晶体管T3均截止，第四晶体管T4和第六晶体管T6均导通。高电平信号经由第四晶体管T4传输至输出端OUT，即输出端OUT的信号为高电平信号。
在示例性实施方式中，虚拟扫描移位寄存器中的晶体管的数量可以小于或者等于扫描移位寄存器中的晶体管的数量。
在示例性实施方式中，虚拟扫描移位寄存器的宽度可以小于或者等于扫描移位寄存器的宽度。
在示例性实施方式中，当虚拟扫描移位寄存器的晶体管的数量等于扫描移位寄存器中的晶体管的数量时，虚拟扫描移位寄存器的电路结构可以与扫描移位寄存器的电路结构相同，此时，虚拟扫描移位寄存器的宽度可以等于扫描移位寄存器的宽度，宽度为垂直于移位寄存器所连接的第二电源线VGL的延伸方向的方向的长度，移位寄存器包括虚拟扫描移位寄存器或者扫描移位寄存器。
在示例性实施方式中，当虚拟扫描移位寄存器的晶体管的数量小于扫描移位寄存器中的晶体管的数量时，虚拟扫描移位寄存器的宽度可以小于扫描移位寄存器的宽度。
在示例性实施方式中，为了保证圆角区域的显示效果，靠近圆角区域的像素驱动电路的保留的较多，而本公开通过减少虚拟扫描移位寄存器的宽度可以节省为扫描移位寄存器的布线提供足够的区域，减少了圆角区域所占用的面积，可以实现显示基板的窄边框。
在示例性实施方式中，图8A为一种虚拟扫描移位寄存器的等效电路图，图8B为另一虚拟扫描移位寄存器的等效电路图。当虚拟扫描移位寄存器中的晶体管的数量小于扫描移位寄存器中的晶体管的数量时，虚拟扫描移位寄存器的电路结构可以为图8A或者图8B，其中，图8A和图8B提供的电路结构没有设置电容。
在示例性实施方式中，如图8A所示，虚拟扫描移位寄存器可以包括：第一晶体管DT1、第二晶体管DT2、第四晶体管DT4至第八晶体管DT8。 其中，第一晶体管DT1的控制极、第一极和第二极与第二电源端V2电连接，第二晶体管DT2的控制极、第一极和第二极与第二电源端V2电连接，第四晶体管DT4的控制极、第一极和第二极与第二电源端V2电连接，第五晶体管DT5的第一极和第二极与第二电源端V2电连接，第五晶体管DT5的控制极与第八晶体管DT8的第二极电连接，第六晶体管DT6的控制极和第一极与第二电源端V2电连接，第六晶体管DT6的第二极与第七晶体管DT7的第一极电连接，第七晶体管DT7的控制极与第二极与第二电源端V2电连接，第八晶体管DT8的控制极和第一极与与第二电源端V2电连接。
在示例性实施方式中，如图8B所示，虚拟扫描移位寄存器可以包括：第一晶体管DT1、第二晶体管DT2、第六晶体管DT6至第八晶体管DT8。其中，第一晶体管DT1的控制极、第一极和第二极与第二电源端V2电连接，第二晶体管DT2的控制极、第一极和第二极与第二电源端V2电连接，第六晶体管DT6的控制极和第一极与第二电源端V2电连接，第六晶体管DT6的第二极与第七晶体管DT7的第一极电连接，第七晶体管DT7的控制极与第二极与第二电源端V2电连接，第八晶体管DT8的控制极、第一极和第二极与第二电源端V2电连接。
在示例性实施方式中，发光移位寄存器或者控制寄存器的电路结构可以为13T3C或者10T3C，本公开对此不作任何限定。
在示例性实施方式中，显示基板还可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
图9A为显示基板的一个局部示意图，图9B为图9A提供的显示基板在圆角区域的部分示意图，图10A为显示基板的另一局部示意图，图10B为显示基板的又一局部示意图，图11为图10A和图10B提供的显示基板在圆角区域的部分示意图，如图9A至图11所示，在示例性实施方式中，驱动电路层还可以包括：位于非显示区域的第一初始信号线GSTV、第一时钟信号线GCK1、第二时钟信号线GCK2、第一电源线VGH和第二电源线VGL，扫描驱动电路分别与第一时钟信号线GCK1、第二时钟信号线GCK2、第一电源线VGH、第二电源线VGL和第一初始信号线GSTV电连接。
在示例性实施方式中，如图9A至图11所示，第一时钟信号线GCK1、 第二时钟信号线GCK2、第一初始信号线GSTV、第一电源线VGH和第二电源线VGL可以至少部分沿第一方向D1延伸。
在示例性实施方式中，第一级移位寄存器的输入端与第一初始信号线电连接，第i级移位寄存器的输出端与第i+1级移位寄存器的输入端电连接；第i级移位寄存器的第一时钟信号端与第一时钟信号线电连接，第二时钟信号端与第二时钟信号线电连接，第i+1级移位寄存器的第一时钟信号端与第二时钟信号线电连接，第二时钟信号端与第一时钟信号线电连接，第i级移位寄存器的第一电源端与第一电源线电连接，第i级移位寄存器的第二电源端与第二电源线电连接。
在示例性实施方式中，如图9A至图11所示，第二时钟信号线GCK2位于第一时钟信号线GCK1远离显示区域的一侧，第二电源线VGL位于第一时钟信号线靠近显示区域的一侧，第一初始信号线GSTV位于第二电源线VGL靠近显示区域的一侧，第一电源线VGH位于第一初始信号线GSTV靠近显示区域的一侧，至少一条初始供电线位于第一电源线VGH靠近显示区域的一侧。图9A至图11是以两条初始供电线，第一条初始供电线INITL1和第二条初始供电线INTIL2为例进行说明的。
在示例性实施方式中，如图9A至图11所示，驱动电路层还可以包括：位于非显示区域的第二初始信号线ESTV，第二初始信号线ESTV至少部分沿第一方向D1延伸。发光驱动电路与第二初始信号线ESTV与电连接，第二初始信号线ESTV位于第二电源线VGL和第一初始信号线GSTV之间。
在示例性实施方式中，如图9A所示，驱动电路层还可以包括：位于非显示区域的第一输出信号线OUTL1和第二输出信号线OUTL2，第一输出信号线OUTL1和第二输出信号线OUTL2至少部分沿第二方向D2延伸。
在示例性实施方式中，如图9A所示，第一输出信号线OUTL1位于扫描驱动电路靠近显示区域的一侧，且分别与扫描驱动电路和像素驱动电路电连接。
在示例性实施方式中，如图9A所示，第二输出信号线OUTL2穿过扫描驱动电路，且分别与像素驱动电路以及发光驱动电路和控制驱动电路中的其中一个驱动电路电连接。
在示例性实施方式中，与扫描驱动电路存在交叠的初始供电线在基底上的正投影与多个电容在基底上的正投影至少部分交叠，如图9A所示，第二条初始信号线INITL2在基底上的正投影与多个电容在基底上的正投影至少部分重叠。
在示例性实施方式中，与扫描驱动电路存在交叠的初始供电线远离显示区域的边界与显示区域之间的距离小于多个电容中的至少一个电容远离显示区域的边界与显示区域之间的距离。以图8A为例，第二条初始供电线INITL2远离显示区域的边界与显示区域之间的距离小于多个电容中的至少一个电容远离显示区域的边界与显示区域之间的距离即第二条初始供电线INITL2与电容交叠，没有与晶体管交叠，可以提升扫描移位寄存器的可靠性。
在示例性实施方式中，结合图9B、图10A、图10B和图11所示，位于虚拟扫描移位寄存器侧面的第二时钟信号线的远离显示区域的边界和至少一条初始供电线中靠近显示区域的初始供电线的靠近显示区域的边界之间的距离L2小于位于扫描移位寄存器侧面的第二时钟信号线的远离显示区域的边界和至少一条初始供电线中靠近显示区域的初始供电线的靠近显示区域的边界之间的距离L1。
在示例性实施方式中，图12为再一显示基板的局部示意图，如图12所示，驱动电路层还可以包括：位于显示区域和非显示区域的第一输出连接线CL1和第二输出连接线CL2，第一输出连接线CL1和第二输出连接线CL至少部分沿第二方向延伸。
在示例性实施方式中，第一输出连接线可以分别与第一输出信号线OUTL1和像素驱动电路电连接，第二输出连接线可以分别与第二输出信号线OUTL2和像素驱动电路电连接。
在示例性实施方式中，第一输出连接线通过扫描信号线与像素驱动电路电连接。第二输出连接线通过发光信号线或者控制信号线与像素驱动电路电连接，当第二输出连接线所连接的第二输出信号线与发光驱动电路电连接时，第二输出连接线通过发光信号线与像素驱动电路电连接，当第二输出连接线所连接的第二输出信号线与控制驱动电路电连接时，第二输出连接线通过控制信号线与像素驱动电路电连接。
在示例性实施方式中，当N＝2时，如图12所示，驱动电路层还可以包括：第三输出连接线CL3和第四输出连接线CL4，第三输出连接线CL3和第四输出连接线至CL4少部分沿第二方向D2延伸。其中，第三输出连接线CL3，分别与第一条初始供电线和像素驱动电路电连接；第四输出连接线CL4，分别与第二条初始供电线和像素驱动电路电连接。
在示例性实施方式中，驱动电路层可以包括：依次叠设的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；
半导体层至少包括：多个晶体管的有源层；
第一导电层至少包括：多个晶体管的控制极和多个电容的第一极板；
第二导电层至少包括：多个电容的第二极板、第一输出信号线和第三输出信号线；
第三导电层至少包括：第二电源线以及至少一个晶体管的第一极和第二极以及第四输出信号线；
第四导电层至少包括：第一初始信号线、第二初始信号线和第一电源线。
在示例性实施方式中，驱动电路层还包括：位于第四导电层远离基底一侧的第五导电层；
第五导电层至少包括：第一输出连接线和第二输出连接线。
在示例性实施方式中，第一输出连接线和第二输出连接线位于第五导电层可以进一步减少非显示区域所占用的空间，通过第一输出连接线从非显示区域连接至显示区域，在显示区域内进行跨层连接以连接至对应的像素驱动电路中。
在示例性实施方式中，第一输出连接线和第二输出连接线之间可以穿插设置虚拟走线，其中，虚拟走线为不提供信号的信号走线。第一输出连接线和第二输出连接线之间可以穿插设置虚拟走线可以保证第五导电层的刻蚀均一性，可以保证显示基板的可靠性。
在示例性实施方式中，初始供电线可以为单层结构，或者可以为多层结构，本公开对此不做任何限定。
在示例性实施方式中，初始供电线为单层结构，且初始供电线位于第四 导电层。
在示例性实施方式中，当显示基板为LTPO显示基板时，初始供电线可以为单层结构。
在示例性实施方式中，初始供电线包括：相互连接的第一初始子段和第二初始子段，第一初始子段在基底上的正投影与第二初始子段在基底上的正投影至少部分交叠。
在示例性实施方式中，第一初始子段位于第三导电层，第二初始子段位于第四导电层。
在示例性实施方式中，初始供电线采用叠层设计可以降低初始供电线的负载差异，还可以满足显示基板的跳线规则，以规避显示基板中的静电风险。
在示例性实施方式中，第一时钟信号线和第二时钟信号线可以为单层结构，或者可以为多层结构，本公开对此不做任何限定。
在示例性实施方式中，第一时钟信号线和第二时钟信号线为单层结构，且第一时钟信号线和第二时钟信号线位于第四导电层。
在示例性实施方式中，时钟信号线可以包括：相互连接的第一时钟子段和第二时钟子段，时钟信号线包括第一时钟信号线和第二时钟信号线，第一时钟子段在基底上的正投影与第二时钟子段在基底上的正投影至少部分交叠；
在示例性实施方式中，第一时钟子段位于第三导电层，第二时钟子段第四导电层靠近基底的一侧。
在示例性实施方式中，第一时钟信号线和第二时钟信号线采用叠层设计可以降低第一时钟信号线和第二时钟信号线的负载差异，还可以满足显示基板的跳线规则，以规避显示基板中的静电风险。
在示例性实施方式中，第二输出信号线可以为单层结构，或者可以为多层结构，本公开对此不做任何限定。
在示例性实施方式中，第二输出信号线为单层结构，且第二输出信号线位于第二导电层。
在示例性实施方式中，图13为第二输出信号线的结构示意图，如图13所示，驱动电路层还包括：位于第二导电层和第三导电层之间的第六导电层； 其中，第二输出信号线包括多个第一输出子段OUTL2A和多个第二输出子段OUTL2B，相邻第一输出子段OUTL2A通过第二输出子段OUTL2B电连接，相邻第二输出子段OUTL2B通过第一输出子段OUTL2A电连接，第二输出子段OUTL2B在基底上的正投影与电连接的第一输出子段OUTL2A在基底上的正投影至少部分交叠，第一输出子段OUTL2A在基底上的正投影与电连接的第二输出子段OUTL2B在基底上的正投影至少部分交叠。第一输出子段OUTL2A位于第二导电层，第二输出子段OUTL2B位于第六导电层。
在示例性实施方式中，第二输出信号线包括位于不同膜层的第一输出子段和第二输出子段，可以规避由于第二输出信号线较长导致的静电风险。
本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
下面通过图9A提供的显示基板的制备过程进行示例性说明，图9A是以第二输出信号线为单层结构为例进行说明的。
(1)在基底上形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图14所示，图14为图9A形成半导体层 图案后的示意图。
在示例性实施方式中，如图14所示，半导体层图案可以包括：第一晶体管的有源层T11至第八晶体管的有源层T81。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
在示例性实施方式中，半导体层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
在示例性实施方式中，如图14所示，第二晶体管的有源层T21和第三晶体管的有源层T31可以为一体结构，第四晶体管的有源层T41和第五晶体管的有源层T51可以一体结构，第六晶体管的有源层T61与第七晶体管的有源层T71可以为一体结构，第一晶体管的有源层T11和第八晶体管的有源层 T81单独设置。
在示例性实施方式中，如图14所示，在第一方向D1上，第八晶体管的有源层T81以及第六晶体管的有源层T61与第七晶体管的有源层T71的一体结构位于第一晶体管的有源层T11的同一侧，在第二方向D2上，第一晶体管的有源层T11、第八晶体管的有源层T81、第四晶体管的有源层T41和第五晶体管的有源层T51的一体结构、第六晶体管的有源层T61与第七晶体管的有源层T71的一体结构以及位于第二晶体管的有源层T21和第三晶体管的有源层T31的一体结构的同一侧，第四晶体管的有源层T41和第五晶体管的有源层T51的一体结构、第六晶体管的有源层T61与第七晶体管的有源层T71的一体结构位于第八晶体管的有源层T81的同一侧，本级扫描移位寄存器的第一晶体管的有源层T11位于本级扫描移位寄存器的第八晶体管的有源层T81靠近上一级扫描移位寄存器的一侧。
在示例性实施例方式中，第一晶体管的有源层T11可以沿第二方向D2延伸，且为条状结构。第二晶体管的有源层T21和第三晶体管的有源层T31的一体结构、第六晶体管的有源层T61与第七晶体管的有源层T71的一体结构以及第八晶体管的有源层T81的形状可以呈“I”字型。第四晶体管的有源层T41和第五晶体管的有源层T51的一体结构可以包括两个“I”字型结构，且两个“I”字型沿第二方向D2排布。
在示例性实施例方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第二晶体管的有源层的第二区T21_2可以作为第三晶体管的有源层的第二区T31_2，第四晶体管的有源层的第二区T41_2可以作为第五晶体管的有源层的第二区T51_2，第六晶体管的有源层的第二区T61_2可以作为第七晶体管的有源层的第一区T71_1，第一晶体管的有源层的第一区T11_1和第二区T11_2、第二晶体管的有源层的第一区T21_1、第三晶体管的有源层的第一区T31_1、第四晶体管的有源层的第一区T41_1、第五晶体管的有源层的第一区T51_1、第六晶体管的有源层的第一区T61_1、第七晶体管的有源层的第一区T71_2以及第八晶体管的有源层的第一区T81_1和第二区T81_2可以单独设置。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案 可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及设置在第一绝缘层上的第一导电层图案，如图15和图16所示，图15为图9A的第一导电层图案的示意图，图16为图9A形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图15和图16所示，第一导电层图案至少可以包括：第一晶体管的控制极T12至第八晶体管的控制极T82、第一电容的第一极板C11和第二电容的第一极板C21和第一连接线VL1。
在示例性实施方式中，如图15和图16所示，第一电容的第一极板C11、第四晶体管的控制极T42和第六晶体管的控制极T62为一体结构，第二电容的第一极板C21和第五晶体管的控制极T52为一体结构。
在示例性实施方式中，如图15和图16所示，第一电容的第一极板C11和第二电容的第一极板C21可以沿第一方向D1排布，且第一电容的第一极板C11可以位于第二电容的第一极板C21靠近上一级扫描移位寄存器的一侧。
在示例性实施方式中，如图15和图16所示，第二电容的第一极板C21的面积可以大于第一电容的第一极板C11的面积。
在示例性实施方式中，如图15和图16所示，第一电容的第一极板C11的形状可以为方形，且可以位于第四晶体管的控制极T42和第六晶体管的控制极T62靠近显示区域的一侧。第四晶体管的控制极T42和第六晶体管的控制极T62的形状可以为沿第二方向D2延伸的条状。
在示例性实施方式中，如图15和图16所示，第二电容的第一极板C21的形状可以为方形，且可以位于第五晶体管的控制极T52靠近显示区域的一侧。第五晶体管的控制极T52可以包括多条沿第二方向D2延伸的条状结构，第五晶体管的控制极T52和第二电容的第一极板C21的一体结构可为梳妆结构，第五晶体管的控制极T52作为梳齿，第二电容的第一极板C21作为梳背。
在示例性实施方式中，如图15和图16所示，第一晶体管的控制极T12可以位于第一电容的第一极板C11远离显示区域的一侧。其中，第一晶体管 的控制极T12的形状可以呈向右旋转的“F”字型，且开口朝向第二晶体管的控制极T22。
在示例性实施方式中，如图15和图16所示，第二晶体管的控制极T22和第三晶体管的控制极T32可以为沿第二方向D2延伸的条状结构。
在示例性实施方式中，如图15和图16所示，第七晶体管的控制极T72可以为向左旋转的“n”字型，且n的两条边的长度不同。
在示例性实施方式中，如图15和图16所示，第八晶体管的控制极T82至少部分沿第二方向D2延伸，且为折线状。
在示例性实施方式中，如图15和图16所示，第一连接线VL1可以为沿第二方向D2延伸的条状，且位于第四晶体管的控制极T42靠近上一级移位寄存器的一侧。
在示例性实施方式中，如图15和图16所示，第一晶体管的控制极T12跨设在第一晶体管的有源层上，第二晶体管的控制极T22跨设在第二晶体管的有源层上，第三晶体管的控制极T32跨设在第三晶体管的有源层上，第四晶体管的控制极T42跨设在第四晶体管的有源层上，第五晶体管的控制极T52跨设在第五晶体管的有源层上，第六晶体管的控制极T62跨设在第六一晶体管的有源层上，第七晶体管的控制极T72跨设在第七晶体管的有源层上，至少一个晶体管的控制极的延伸方向与有源层的延伸方向相互垂直。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管T1至第七晶体管的第一区和第二区均被导体化。第六晶体管的有源层的第二区和第七晶体管的有源层的第一区的一体结构复用为第六晶体管的第二极T64和第七晶体管的第一极T73。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层图案的第二绝缘层，以及设置在第二绝缘层上的第二导电层图案，如图17和图 18所示，图17为图9A的第二导电层图案的示意图，图18为图9A形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图17和图18所示，第二导电层图案至少可以包括：第一电容的第二极板C12、第二电容的第二极板C22、第一输出信号线OUTL1、第二输出信号线OUTL2和第三输出信号线OUTL3。
在示例性实施方式中，如图17和图18所示，第二电容的第二极板C22和第一输出信号线OUTL1可以为一体结构，且第一输出信号线OUTL1位于第二电容的第二极板C22靠近显示区域的一侧。
在示例性实施方式中，如图17和图18所示，第一电容的第二极板C12的轮廓可以为向左旋转的镰刀形状，第一电容的第二极板C12在基底上的正投影与第一电容的第一极板C11在基底上的正投影至少部分交叠。
在示例性实施方式中，如图17和图18所示，第二电容的第二极板C22的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二电容的第二极板C22在基底上的正投影与第二电容的第一极板C21在基底上的正投影至少部分交叠。
在示例性实施方式中，如图17和图18所示，第一输出信号线OUTL1、第二输出信号线OUTL2和第三输出信号线OUTL3可以至少部分沿第二方向D2延伸，且可以为折线状。
在示例性实施方式中，如图17和图18所示，第二输出信号线OUTL2可以为位于第一输出信号线OUTL1靠近上一级扫描移位寄存器的一侧，第三输出信号线OUTL3可以为位于第一输出信号线OUTL1靠近下一级扫描移位寄存器的一侧，第三输出信号线OUTL3位于第一电容的第二极板C12靠近显示区域的一侧。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔图案，如图19所示，图19为图9A形成第三绝缘层图 案后的示意图。
在示例性实施方式中，如图19所示，多个过孔图案至少可以包括第一过孔H1至第二十二过孔H22。
在示例性实施方式中，如图19所示，第一过孔H1在基底上的正投影位于第一晶体管的有源层的第一区在基底上的正投影的范围之内，第一过孔H1内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第一区的表面，第一过孔H1被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一晶体管的有源层的第一区连接。
在示例性实施方式中，如图19所示，第二过孔H2在基底上的正投影位于第一晶体管的有源层的第二区在基底上的正投影的范围之内，第二过孔H2内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第一晶体管的有源层的第二区的表面，第二过孔H2被配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一晶体管的有源层的第二区连接。
在示例性实施方式中，如图19所示，第三过孔H3在基底上的正投影位于第二晶体管的有源层的第一区在基底上的正投影的范围之内，第三过孔H3内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第二晶体管的有源层的第一区的表面，第三过孔H3被配置为使后续形成的第二晶体管的第一极通过该过孔与第二晶体管的有源层的第一区连接。
在示例性实施方式中，如图19所示，第四过孔H4在基底上的正投影位于第二晶体管的有源层的第二区(也是第三晶体管的有源层的第二区)在基底上的正投影的范围之内，第四过孔H4内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第二晶体管的有源层的第二区(也是第三晶体管的有源层的第二区)的表面，第四过孔H4被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极)通过该过孔与第二晶体管的有源层的第二区(也是第三晶体管的有源层的第二区)连接。
在示例性实施方式中，如图19所示，第五过孔H5在基底上的正投影位于第三晶体管的有源层的第一区在基底上的正投影的范围之内，第五过孔H5内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三晶体管的有源层的第一区的表面，第五过孔H5被配置为使后续形成的第三晶体管的 第一极通过该过孔与第三晶体管的有源层的第一区连接。
在示例性实施方式中，如图19所示，第六过孔H6在基底上的正投影位于第四晶体管的有源层的第一区在基底上的正投影的范围之内，第六过孔H6内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第六过孔H6被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源层的第一区连接。
在示例性实施方式中，如图19所示，第七过孔H7在基底上的正投影位于第四晶体管的有源层的第二区(也是第五晶体管的有源层的第二区)在基底上的正投影的范围之内，第七过孔H7内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第二区(也是第五晶体管的有源层的第二区)的表面，第七过孔H7被配置为使后续形成的第四晶体管的第二极(也是第五晶体管的第二极)通过该过孔与第四晶体管的有源层的第二区(也是第五晶体管的有源层的第二区)连接。
在示例性实施方式中，如图19所示，第八过孔H8在基底上的正投影位于第五晶体管的有源层的第一区在基底上的正投影的范围之内，第八过孔H8内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第八过孔H8被配置为使后续形成的第五晶体管的第一极通过该过孔与第五晶体管的有源层的第一区连接。
在示例性实施方式中，如图19所示，第九过孔H9在基底上的正投影位于第六晶体管的有源层的第一区在基底上的正投影的范围之内，第九过孔H9内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第九过孔H9被配置为使后续形成的第六晶体管的第一极通过该过孔与第六晶体管的有源层的第一区连接。
在示例性实施方式中，如图19所示，第十过孔H10在基底上的正投影位于第七晶体管的有源层的第二区在基底上的正投影的范围之内，第十过孔H10内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第二区的表面，第十过孔H10被配置为使后续形成的第七晶体管的第二极通过该过孔与第七晶体管的有源层的第二区连接。
在示例性实施方式中，如图19所示，第十一过孔H11在基底上的正投 影位于第八晶体管的有源层的第一区在基底上的正投影的范围之内，第十一过孔H11内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第十一过孔H11被配置为使后续形成的第八晶体管的第一极通过该过孔与第八晶体管的有源层的第一区连接。
在示例性实施方式中，如图19所示，第十二过孔H12在基底上的正投影位于第八晶体管的有源层的第二区在基底上的正投影的范围之内，第十二过孔H12内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第四晶体管的有源层的第一区的表面，第十二过孔H12被配置为使后续形成的第八晶体管的第二极通过该过孔与第八晶体管的有源层的第二区连接。
在示例性实施方式中，如图19所示，第十三过孔H13在基底上的正投影位于第一晶体管的控制极在基底上的正投影的范围之内，第十三过孔H13内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一晶体管的控制极的表面，第十三过孔H13被配置为使后续形成的第二时钟信号线的第一时钟子段和第二晶体管的第一极通过该过孔与第一晶体管的控制极连接。
在示例性实施方式中，如图19所示，第十四过孔H14在基底上的正投影位于第二晶体管的控制极在基底上的正投影的范围之内，第十四过孔H14内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二晶体管的控制极的表面，第十四过孔H14被配置为使后续形成的第一晶体管的第二极(也是第七晶体管的第二极和第八晶体管的第一极)通过该过孔与第一晶体管的控制极连接。
在示例性实施方式中，如图19所示，第十五过孔H15在基底上的正投影位于第三晶体管的控制极在基底上的正投影的范围之内，第十五过孔H15内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二晶体管的控制极的表面，第十五过孔H15被配置为使后续形成的第二时钟信号线的第一时钟子段通过该过孔与第三晶体管的控制极连接。
在示例性实施方式中，如图19所示，第十六过孔H16在基底上的正投影位于第五晶体管的控制极在基底上的正投影的范围之内，第十六过孔H16内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五晶体管的控制极的表面，第十六过孔H16被配置为使后续形成的第八晶体管的第二极通过该过孔与第五晶体管的控制极连接。
在示例性实施方式中，如图19所示，第十七过孔H17在基底上的正投影位于第六晶体管的控制极在基底上的正投影的范围之内，第十七过孔H17内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六晶体管的控制极的表面，第十七过孔H17被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极)通过该过孔与第六晶体管的控制极连接。
在示例性实施方式中，如图19所示，第十八过孔H18在基底上的正投影位于第七晶体管的控制极在基底上的正投影的范围之内，第十八过孔H18内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七晶体管的控制极的表面，第十八过孔H18被配置为使后续形成的第五晶体管的第一极和第一时钟信号线和第一时钟子段通过该过孔与第七晶体管的控制极连接。
在示例性实施方式中，如图19所示，第十九过孔H19在基底上的正投影位于第八晶体管的控制极在基底上的正投影的范围之内，第十九过孔H19内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八晶体管的控制极的表面，第十九过孔H19被配置为使后续形成的第三晶体管的第一极通过该过孔与第八晶体管的控制极连接。
在示例性实施方式中，如图19所示，第二十过孔H20在基底上的正投影位于第一连接线在基底上的正投影的范围之内，第二十过孔H20内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一连接线的表面，第二十过孔H20被配置为使后续形成的第一晶体管的第一极通过该过孔与第一连接线连接。
在示例性实施方式中，如图19所示，第二十一过孔H21在基底上的正投影位于第一电容的第二极板在基底上的正投影的范围之内，第二十一过孔H21内的第三绝缘层被刻蚀掉，暴露出第一电容的第二极板的表面，第二十一过孔H21被配置为使后续形成的第四晶体管的第一极通过该过孔与第一电容的第二极板连接。
在示例性实施方式中，如图19所示，第二十二过孔H22在基底上的正投影位于第二电容的第二极板在基底上的正投影的范围之内，第二十二过孔H22内的第三绝缘层被刻蚀掉，暴露出第二电容的第二极板的表面，第二十二过孔H22被配置为使后续形成的第四晶体管的第二极(也是第五晶体管的第二极)通过该过孔与第二电容的第二极板连接。
在示例性实施方式中，如图19所示，第二十三过孔H23在基底上的正投影位于第三输出信号线在基底上的正投影的范围之内，第二十三过孔H23内的第三绝缘层被刻蚀掉，暴露出第三输出信号线的表面，第二十三过孔H23被配置为使后续形成的第一条初始供电线的第一初始子段通过该过孔与第三输出信号线连接。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，如图20和图21所示，图20为图9A的第三导电层图案的示意图，图21为图9A形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图20和图21所示，第三导电层图案至少可以包括：第一时钟信号线的第一时钟子段GCK1A、第二时钟信号线的第一时钟子段GCK2A、第二电源线VGL、第一条初始供电线的第一初始子段INITL1A、第二条初始供电线的第一初始子段INITL2A、第四输出信号线OUTL4、第一晶体管的第一极T13和第二极T14至第五晶体管的第一极T53和第二极T54、第六晶体管的第一极T63、第七晶体管的第二极T74和第八晶体管的第一极T83和第二极T84。
在示例性实施方式中，如图20和图21所示，第二时钟信号线的第一时钟子段GCK2A的形状可以为至少部分沿第一方向D1延伸的线形状，第二时钟信号线的第一时钟子段GCK2A通过第十三过孔与第一晶体管的控制极连接，且通过第十五过孔与第三晶体管的控制极连接。
在示例性实施方式中，如图20和图21所示，第一时钟信号线的第一时钟子段GCK1A的形状可以为至少部分沿第一方向D1延伸的线形状，且位于第二时钟信号线的第一时钟子段GCK2A靠近显示区域的一侧，第一时钟信号线的第一时钟子段GCK1A通过第十八过孔与第七晶体管的控制极连接。
在示例性实施方式中，如图20和图21所示，第二时钟信号线的第一时钟子段GCK2A和第一时钟信号线的第一时钟子段GCK1A可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便 于扫描驱动电路的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，如图20和图21所示，第二电源线VGL与第三晶体管的第一极T33为一体结构，第二电源线VGL的形状可以为至少部分沿第一方向D1延伸的线形状，且位于第一时钟信号线的第一时钟子段GCK1A靠近显示区域的一侧，第三晶体管的第一极T33位于第二电源线VGL靠近显示区域的一侧，第三晶体管的第一极T33通过第五过孔与第三晶体管的有源层的第一区连接，且通过第十九过孔与第八晶体管的控制极连接。
在示例性实施方式中，第二电源线VGL的宽度可以小于第二时钟信号线的第一时钟子段GCK2A或者第一时钟信号线的第一时钟子段GCK1A的宽度。
在示例性实施方式中，如图20和图21所示，第一晶体管的第一极T13可以沿第二方向D2延伸，第一晶体管的第一极T13通过第一过孔与第一晶体管的有源层的第一区连接，且通过第二十过孔与第一连接线连接，第一连接线与上一级扫描移位寄存器的第四晶体管的第二极(也是第五晶体管的第二极连接)，以实现与本级扫描移位寄存器与上一级扫描移位寄存器的级联。
在示例性实施方式中，如图20和图21所示，第一晶体管的第二极T14、第七晶体管的第二极T74和第八晶体管的第一极T83可以为一体结构，且可以通过第二过孔与第一晶体管的有源层的第二区、通过第十四过孔与第二晶体管的控制极连接，通过第十过孔与第七晶体管的有源层的第二区和通过第十一过孔与第八晶体管的有源层的第一区连接。
在示例性实施方式中，如图20和图21所示，第二晶体管的第一极T23可以为沿第一方向D1延伸的线形状。其中，第二晶体管的第一极T23可以通过第三过孔与第二晶体管的有源层的第一区连接，且通过第十三过孔与第一晶体管的控制极连接。
在示例性实施方式中，如图20和图21所示，第二晶体管的第二极T24和第三晶体管的第二极T34为一体结构，且可以为沿第二方向D2延伸的线形状。其中，第二晶体管的第二极T24和第三晶体管的第二极T34的一体结构可以通过第四过孔与第二晶体管的有源层的第二区(也是第三晶体管的有 源层的第二区)连接，且通过第十七过孔与第六晶体管的控制极连接。
在示例性实施方式中，如图20和图21所示，第二晶体管的第二极T24和第三晶体管的第二极T34为一体结构，且可以为沿第二方向D2延伸的线形状。其中，第二晶体管的第二极T24和第三晶体管的第二极T34的一体结构可以通过第四过孔与第二晶体管的有源层的第二区(也是第三晶体管的有源层的第二区)连接，且通过第十七过孔与第六晶体管的控制极连接。
在示例性实施方式中，如图20和图21所示，第四晶体管的第一极T43和第六晶体管的第一极T63可以为一体结构，且可以至少部分沿第二方向D2延伸，第四晶体管的第一极T43和第六晶体管的第一极T63的一体结构可以通过第六过孔与第四晶体管的有源层的第一区连接，通过第九过孔与第六晶体管的有源层的第一区连接，且通过第二十一过孔与第一电容的第二极板连接。
在示例性实施方式中，如图20和图21所示，第四晶体管的第二极T44和第五晶体管的第二极T54为一体结构，且形状可以呈水平翻转的“F”字型。其中，第四晶体管的第二极T44和第五晶体管的第二极T54的一体结构可以通过第七过孔与第四晶体管的有源层的第二区(也是第五晶体管的有源层的第二区)连接，且通过第二十二过孔与第二电容的第二极板连接。
在示例性实施方式中，如图20和图21所示，第五晶体管的第一极T53的形状可以呈开口朝向显示区域的“n”字型。其中，第五晶体管的第一极T53可以通过第八过孔与第五晶体管的有源层的第一区连接，且通过第十八过孔与第七晶体管的控制极连接。
在示例性实施方式中，如图20和图21所示，第八晶体管的第二极T84可以至少部分沿第二方向D2延伸。其中，第八晶体管的第二极T84可以通过第十二过孔与第八晶体管的有源层的第二区连接，且通过第十六过孔与第五晶体管的控制极连接。
在示例性实施方式中，如图20和图21所示，第二条初始供电线的第一初始子段INITL2A与第四输出信号线OUTL4为一体结构，且第四输出信号线OUTL4位于第二条初始供电线的第一初始子段INITL2A靠近显示区域的一侧。
在示例性实施方式中，如图20和图21所示，第二条初始供电线的第一初始子段INITL2A的形状可以为至少部分沿第一方向D1延伸的线形状，且包括多个间隔设置的供电电极，第二条初始供电线的第一初始子段INITL2A可以位于第四晶体管的第二极T44和第五晶体管的第二极T54的一体结构靠近显示区域的一侧。
在示例性实施方式中，如图20和图21所示，第四输出信号线OUTL4可以至少部分沿第二方向D2延伸。
在示例性实施方式中，如图20和图21所示，第二条初始供电线的第一初始子段INITL2A在基底上的正投影与第一电容的第二极板和第二电容的第二极板在基底上的正投影至少部分交叠。
在示例性实施方式中，如图20和图21所示，第一条初始供电线的第一初始子段INITL1A的形状可以为至少部分沿第一方向D1延伸的线形状，且包括多个间隔设置的供电电极，第一条初始供电线的第一初始子段INITL1A可以位于第二条初始供电线的第一初始子段INITL2A靠近显示区域的一侧。
在示例性实施方式中，如图20和图21所示，第一条初始供电线的第一初始子段INITL1A和第二条初始供电线的第一初始子段INITL2A可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于扫描驱动电路的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(6)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第三导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图22所示，图22为图9A形成第四绝缘层图案后的示意图。
在示例性实施方式中，多个过孔至少包括：第二十四过孔H24至第二十八过孔H28。
在示例性实施方式中，如图22所示，第二十四过孔H24在基底上的正投影位于第四晶体管的第一极在基底上的正投影的范围之内，第二十四过孔H24的第四绝缘层被刻蚀掉，暴露出第四晶体管的第一极的表面，第二十四 过孔H24被配置为使后续形成的第一电源线通过该过孔与第四晶体管的第一极连接。
在示例性实施方式中，如图22所示，第二十五过孔H25在基底上的正投影位于第二时钟信号线的第一时钟子段在基底上的正投影的范围之内，第二十四过孔H24的第四绝缘层被刻蚀掉，暴露出第二时钟信号线的第一时钟子段的表面，第二十四过孔H24被配置为使后续形成的第二时钟信号线的第二时钟子段通过该过孔与第二时钟信号线的第一时钟子段连接。
在示例性实施方式中，如图22所示，第二十六过孔H26在基底上的正投影位于第一时钟信号线的第一时钟子段在基底上的正投影的范围之内，第二十五过孔H25的第四绝缘层被刻蚀掉，暴露出第一时钟信号线的第一时钟子段的表面，第二十五过孔H25被配置为使后续形成的第一时钟信号线的第二时钟子段通过该过孔与第一时钟信号线的第一时钟子段连接。
在示例性实施方式中，如图22所示，第二十七过孔H27在基底上的正投影位于第二条初始供电线的第一初始子段在基底上的正投影的范围之内，第二十七过孔H27的第四绝缘层被刻蚀掉，暴露出第二条初始供电线的第一初始子段的表面，第二十七过孔H27被配置为使后续形成的第二条初始供电线的第二初始子段通过该过孔与第二条初始供电线的第一初始子段连接。
在示例性实施方式中，如图22所示，第二十八过孔H28在基底上的正投影位于第一条初始供电线的第一初始子段在基底上的正投影的范围之内，第二十八过孔H28的第四绝缘层被刻蚀掉，暴露出第一条初始供电线的第一初始子段的表面，第二十八过孔H28被配置为使后续形成的第一条初始供电线的第二初始子段通过该过孔与第一条初始供电线的第一初始子段连接。
(7)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第四绝缘层上的第四导电层，如图23和图24所示，图23为图9A的第四导电层的示意图，图24为图9A的形成第四导电层的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图23和图24所示，第四导电层图案可以至少 包括：第一时钟信号线的第二时钟子段GCK1B、第二时钟信号线的第二时钟子段GCK2B、第一电源线VGH、第一条初始供电线的第二初始子段INITL1B、第二条初始供电线的第二初始子段INITL2B、第一初始信号线GSTV和第二初始信号线ESTV。
在示例性实施方式中，如图23和图24所示，第二时钟信号线的第二时钟子段GCK2B的形状可以为至少部分沿第一方向D1延伸的线形状，第二时钟信号线的第二时钟子段GCK2B在基底上的正投影与第二时钟信号线的第一时钟子段在基底上的正投影至少部分交叠，且通过第二十五过孔与第二时钟信号线的第一时钟子段连接，形成第二时钟信号线。
在示例性实施方式中，如图23和图24所示，第一时钟信号线的第二时钟子段GCK1B的形状可以为至少部分沿第一方向D1延伸的线形状，第一时钟信号线的第二时钟子段GCK1B在基底上的正投影与第一时钟信号线的第一时钟子段在基底上的正投影至少部分交叠，且通过第二十六过孔与第一时钟信号线的第一时钟子段连接，形成第一时钟信号线。
在示例性实施方式中，如图23和图24所示，第二时钟信号线的第二初始子段GCK2B和第一时钟信号线的第二时钟子段GCK1B可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于扫描驱动电路的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，如图23和图24所示，第二初始信号线ESTV位于第一时钟信号线的第二时钟子段GCK1B靠近显示区域的一侧，且在基底上的正投影与第三晶体管的第一极在基底上的正投影至少部分交叠。
在示例性实施方式中，如图23和图24所示，第一初始信号线GSTV位于第二初始信号线ESTV靠近显示区域的一侧，且在基底上的正投影与第八晶体管的控制极在基底上的正投影至少部分交叠。
在示例性实施方式中，如图23和图24所示，第二初始信号线ESTV和第一初始信号线GSTV可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于扫描驱动电路的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，如图23和图24所示，第一电源线VGH的形状可以为至少部分沿第一方向D1延伸的线形状，第一电源线VGH在基底上的正投影与第四晶体管的第二极(也是第五晶体管的第二极)和第四晶体管的第一极在基底上的正投影至少部分交叠，且通过第二十四过孔与第四晶体管的第一极连接。
在示例性实施方式中，如图23和图24所示，第二条初始供电线的第二初始子段INITL2B的形状可以为至少部分沿第一方向D1延伸的线形状，第二条初始供电线的第二初始子段INITL2B在基底上的正投影与第二条初始供电线的第一初始子段在基底上的正投影至少部分交叠，且通过第二十七过孔与第二条初始供电线的第一初始子段连接，形成第二条初始供电线。
在示例性实施方式中，如图23和图24所示，第一条初始供电线的第二初始子段INITL1B的形状可以为至少部分沿第一方向D1延伸的线形状，第一条初始供电线的第二初始子段INITL1B在基底上的正投影与第一条初始供电线的第一初始子段在基底上的正投影至少部分交叠，且通过第二十八过孔与第一条初始供电线的第一初始子段连接，形成第一条初始供电线。
在示例性实施方式中，如图23和图24所示，第二条初始供电线的第二初始子段INITL2B和第一条初始供电线的第二初始子段INITL1B可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于扫描驱动电路的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
(8)形成第五导电层图案。在示例性实施方式中，形成第五导电层图案可以包括：在形成前述图案的基底上，依次沉积第五绝缘薄膜和第五导电薄膜，通过图案化工艺对第五导电薄膜进行图案化，形成覆盖第四导电层图案的第四绝缘层，以及设置在第四绝缘层上的第五导电层图案。在示例性实施方式中，第五导电层可以称为第三源漏金属(SD3)层。
在示例性实施方式中，第五导电层图案可以至少包括：第一输出连接线、第二输出连接线、第三输出连接线和第四输出连接线。
在示例性实施方式中，第一输出连接线与第一输出信号线连接，第二输出连接线与第二输出信号线连接，第三输出连接线与第三输出信号线连接， 第四输出连接线与第四输出信号线连接。
至此，在基底上制备完成驱动电路层。驱动电路层可以包括在基底上依次设置的半导体层、第一绝缘层、、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层、第五绝缘层和第五导电层。
在示例性实施方式中，半导体层可以为金属氧化物层。金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层和第二绝缘层可以称为栅绝缘(GI)层，第三绝缘层和第四绝缘层可以称为层间绝缘(ILD)层，第五绝缘层可以称为钝化(PVX)层。
在示例性实施方式中，当第二输出信号线为双层结构时，步骤(3)形成的第二导电层图案包括的是第二输出信号线的第一输出子段，在步骤(3)和(4)之间可以包括：形成第六导电层图案。形成第六导电层图案可以包括：在形成前述图案的基底上，依次沉积第六绝缘薄膜和第六导电薄膜，通过图案化工艺对第六导电薄膜进行图案化，形成覆盖第二导电层图案的第六绝缘层，以及设置在第六绝缘层上的第六导电层图案。
在示例性实施方式中，第六导电层图案可以至少包括第二输出信号线的第二输出子段。
在示例性实施方式中，步骤(4)形成的是覆盖第六导电层的第四绝缘层，后续步骤与前述实施例形成图9A的流程相同，本公开对此不再赘述。
在示例性实施方式中，第六导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(9)形成发光结构层。在示例性实施方式中，形成发光结构层可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成第一平坦层，在形成前述图案上沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在平坦层上的阳极导电层，阳极导电层至少包括多个阳极图案，在形成前述图案的基底上，涂覆像素定义薄膜，采用图案化工艺对像素定义薄膜进行图案化，形成像素定义层，在形成前述图案的基底上，先采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，像素定义层的材料可以包括聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。
在示例性实施方式中，平坦层可以采用有机材料。
在示例性实施方式中，阳极薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。
在示例性实施方式中，阴极薄膜可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
下面通过图10A的制备过程进行示例性说明，图10A示出的是一个虚拟扫描移位寄存器，虚拟扫描移位寄存器包括第一晶体管DT1、第二晶体管DT2以及第四晶体管DT4至第八晶体管DT8。
(1)在基底上形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图25所示，图25为图10A形成半导体层图案后的示意图。
在示例性实施方式中，如图25所示，半导体层图案可以包括：第一晶体管的有源层DT11、第二晶体管的有源层DT21以及第四晶体管的有源层DT41至第八晶体管的有源层DT81。
在示例性实施方式中，图25的第一晶体管的有源层DT11、第二晶体管的有源层DT21、第六晶体管的有源层DT61至第八晶体管的有源层DT81与图14中的第一晶体管的有源层T11、第二晶体管的有源层T21、第六晶体管的有源层T61至第八晶体管的有源层T81的位置以及结构均相同。不同之处在于，图25中的第四晶体管的有源层DT41和第五晶体管的有源层DT51的一体结构可以呈“I”。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及设置在第一绝缘层上的第一导电层图案，如图26和图27所示，图26为图10A的第一导电层图案的示意图，图27为图10A形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图26和图27所示，第一导电层图案至少可以包括：第一晶体管的控制极DT12、第二晶体管的控制极DT22、第四晶体管的控制极DT42至第八晶体管的控制极DT82和第一连接线VL1。
在示例性实施方式中，如图26和图27所示，第四晶体管的控制极DT42、第六晶体管的控制极DT62至第八晶体管的控制极DT82为一体结构，第一晶体管的控制极DT12、第二晶体管的控制极DT22和第五晶体管的控制极DT52可以单独设置。
在示例性实施方式中，图26中的第一晶体管的控制极T12和第二晶体管的控制极DT22以及第一连接线VL1的形状与图15中的第一晶体管的控制极DT12和第二晶体管的控制极DT22以及第一连接线VL1的形状相同。
在示例性实施方式中，如图26和图27所示，第四晶体管的控制极DT42可为开口朝向显示区域的梳妆结构，第六晶体管的控制极DT62至第八晶体管的控制极DT82位于第四晶体管的控制极DT42的梳背远离显示区域的一侧，第六晶体管的控制极DT62和第七晶体管的控制极DT72可以为沿第二方向D2延伸的线形状，第八晶体管的控制极DT82可以为开口朝向显示区域的“n”字型。
(3)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第二绝缘薄膜和第三绝缘薄膜，采用图案化工艺对第二绝缘薄膜和第三绝缘薄膜进行图案化，形成覆盖第一导电层的第二绝缘层和第三绝缘层，第三绝缘层上设置有多个过孔图案，如图28所示，图28为图10A形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图28所示，多个过孔图案至少可以包括第一过孔H1至第十七过孔H17。第一过孔H1至第十一过孔H11开设在第一绝缘层至第三绝缘层，第十二过孔H12至第十七过孔H17开设在第二绝缘层和第三绝缘层。其中，第一过孔H1暴露出第一晶体管的有源层的第一区，第二过孔H2暴露出第一晶体管的有源层的第二区，第三过孔H3暴露出第二晶体管的有源层的第一区，第四过孔H4暴露出第二晶体管的有源层的第二区，第五过孔H5暴露出第四晶体管的有源层的第一区，第六过孔H6暴露出第四晶体管的有源层的第二区(第五晶体管的有源层的第二区)，第七过孔H7 暴露出第五晶体管的有源层的第一区，第八过孔H8暴露出第六晶体管的有源层的第一区，第九过孔H9暴露出第七晶体管的有源层的第二区，第十过孔H10暴露出第八晶体管的有源层的第一区，第十一过孔H11暴露出第八晶体管的有源层的第二区，第十二过孔H12暴露出第一晶体管的控制极，第十三过孔H13暴露出第二晶体管的控制极，第十四过孔H14暴露出第六晶体管的控制极，第十五过孔H15暴露出第五晶体管的控制极，第十六过孔H16暴露出第四晶体管的控制极，第十七过孔H17暴露出第一连接线。
(4)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，如图29和图30所示，图29为图10A的第三导电层图案的示意图，图30为图10A形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图29和图30所示，第三导电层图案至少可以包括：第一时钟信号线的第一时钟子段GCK1A、第二时钟信号线的第一时钟子段GCK2A、第二电源线VGL、第一条初始供电线的第一初始子段INITL1A、第二条初始供电线的第一初始子段INITL2A、第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23和第二极T24、第四晶体管的第一极T43和第二极T44、第五晶体管的第一极T53和第二极T54、第六晶体管的第一极T63、第七晶体管的第二极T74和第八晶体管的第一极T83和第二极T84。
在示例性实施方式中，图29和图30中的第二时钟信号线的第一时钟子段GCK2A、第一时钟信号线的第一时钟子段GCK1A、第二电源线VGL、第一条初始供电线的第一初始子段INITL1A和第二条初始供电线的第一初始子段INITL2A与图20和图21中的第二时钟信号线的第一时钟子段GCK2A、第一时钟信号线的第一时钟子段GCK1A、第二电源线VGL、第一条初始供电线的第一初始子段INITL1A和第二条初始供电线的第一初始子段INITL2A相同。
在示例性实施方式中，如图29和图30所示，第二电源线VGL与第一 晶体管的第二极、第二晶体管的第一极T23和第二极T24、第七晶体管的第二极T74和第八晶体管的第一极T83为一体结构，第一晶体管的第二极、第二晶体管的第一极T23和第二极T24、第七晶体管的第二极T74和第八晶体管的第一极T83位于第二电源线VGL靠近显示区域的一侧，第二电源线VGL、第一晶体管的第二极、第二晶体管的第一极T23和第二极T24、第七晶体管的第二极T74和第八晶体管的第一极T83的一体结构通过第二过孔与第一晶体管的有源层的第一区连接，通过第三过孔与第二晶体管的有源层的第一区连接，通过第四过孔与第二晶体管的有源层的第二区连接，通过第九过孔与第七晶体管的有源层的第二区连接，通过第十过孔H10与第八晶体管的有源层的第一区连接，通过第十二过孔与第一晶体管的控制极连接。
在示例性实施方式中，图29和图30所示的第一晶体管的第一极T13与图20和图21中的第一晶体管的第一极T13相同。
在示例性实施方式中，如图29和图30所示，第四晶体管的第一极T43和第二极T44、第五晶体管的第一极T53和第二极T54、第六晶体管的第一极T63和第八晶体管的第二极T84为一体结构，且通过第五过孔与第四晶体管的有源层的第一区连接，通过第六过孔与第四晶体管的有源层的第二区(第五晶体管的有源层的第二区)连接，通过第七过孔与第五晶体管的有源层的第一区连接，通过第八过孔与第六晶体管的有源层的第一区连接，通过第十一过孔与第八晶体管的有源层的第二区连接，通过第十三过孔与第二晶体管的控制极连接，通过第十五过孔与第五晶体管的控制极连接，通过第十六过孔与第四晶体管的控制极连接。
(5)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第四导电薄膜，采用图案化工艺对第四绝缘薄膜和第四导电薄膜进行图案化，形成覆盖第三导电层上的第四绝缘层以及设置在第四绝缘层上的第四导电层，如图31和图32所示，图31为图10A的第四导电层的示意图，图32为图10A的形成第四导电层的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图31和图32所示，第四导电层图案可以至少 包括：第一时钟信号线的第二时钟子段GCK1B、第二时钟信号线的第二时钟子段GCK2B、第一电源线VGH、第一条初始供电线的第二初始子段INITL1B、第二条初始供电线的第二初始子段INITL2B、第一初始信号线GSTV和第二初始信号线ESTV。图31和图32中的第一时钟信号线的第二时钟子段GCK1B、第二时钟信号线的第二时钟子段GCK2B、第一电源线VGH、第一条初始供电线的第二初始子段INITL1B、第二条初始供电线的第二初始子段INITL2B、第一初始信号线GSTV和第二初始信号线ESTV与图23和图24中的第一时钟信号线的第二时钟子段GCK1B、第二时钟信号线的第二时钟子段GCK2B、第一电源线VGH、第一条初始供电线的第二初始子段INITL1B、第二条初始供电线的第二初始子段INITL2B、第一初始信号线GSTV和第二初始信号线ESTV结构相同，不同之处在于信号线之间的间距。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程与前述实施例提供的制备过程一致，在此不再赘述。
下面通过图10B的制备过程进行示例性说明，图10B示出的是一个虚拟扫描移位寄存器，虚拟扫描移位寄存器包括第一晶体管DT1、第二晶体管DT2、第六晶体管DT6至第八晶体管DT8。
(1)在基底上形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图33所示，图33为图10B形成半导体层图案后的示意图。
在示例性实施方式中，如图33所示，半导体层图案可以包括：第一晶体管的有源层DT11、第二晶体管的有源层DT21以及第六晶体管的有源层DT61至第八晶体管的有源层DT81。
在示例性实施方式中，图33的第一晶体管的有源层DT11、第二晶体管的有源层DT21、第六晶体管的有源层DT61至第八晶体管的有源层DT81与图14中的第一晶体管的有源层T11、第二晶体管的有源层T21、第六晶体管的有源层T61至第八晶体管的有源层T81的位置以及结构均相同。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及设置在第一绝缘层上的第一导电层图案，如图34和图35所示，图34为图10B的第一导电层图案的示意图，图35为图10B形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图34和图35所示，第一导电层图案至少可以包括：第一晶体管的控制极DT12、第二晶体管的控制极DT22、第六晶体管的控制极DT62至第八晶体管的控制极DT82、第一连接线VL1和第二连接线VL2。
在示例性实施方式中，如图34和图35所示，第六晶体管的控制极T62至第八晶体管的控制极DT82为一体结构，第一晶体管的控制极DT12和第二晶体管的控制极DT22。
在示例性实施方式中，图34中的第一晶体管的控制极T12和第二晶体管的控制极DT22以及第一连接线VL1的形状与图25中的第一晶体管的控制极DT12和第二晶体管的控制极DT22以及第一连接线VL1的形状相同。
(3)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第二绝缘薄膜和第三绝缘薄膜，采用图案化工艺对第二绝缘薄膜和第三绝缘薄膜进行图案化，形成覆盖第一导电层的第二绝缘层和第三绝缘层，第三绝缘层上设置有多个过孔图案，如图36所示，图36为图10B形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图36所示，多个过孔图案至少可以包括第一过孔H1至第十三过孔H13。第一过孔H1至第八过孔H8开设在第一绝缘层至第三绝缘层，第九过孔H9至第十三过孔H13开设在第二绝缘层和第三绝缘层。其中，第一过孔H1暴露出第一晶体管的有源层的第一区，第二过孔H2暴露出第一晶体管的有源层的第二区，第三过孔H3暴露出第二晶体管的有源层的第一区，第四过孔H4暴露出第二晶体管的有源层的第二区，第五过孔H5暴露出第六晶体管的有源层的第一区，第六过孔H6暴露出第七晶体管 的有源层的第二区，第七过孔H7暴露出第八晶体管的有源层的第一区，第八过孔H8暴露出第八晶体管的有源层的第二区，第九过孔H9暴露出第一晶体管的控制极，第十过孔H10暴露出第二晶体管的控制极，第十一过孔H11暴露出第六晶体管的控制极、第七晶体管的控制极和第八晶体管的控制极的一体结构，第十二过孔H12暴露出第一连接线，第十三过孔H13暴露出第二连接线。
(4)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，如图37和图38所示，图37为图10B的第三导电层图案的示意图，图38为图10B形成第三导电层图案后的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图37和图38所示，第三导电层图案至少可以包括：第一时钟信号线的第一时钟子段GCK1A、第二时钟信号线的第一时钟子段GCK2A、第二电源线VGL、第一条初始供电线的第一初始子段INITL1A、第二条初始供电线的第一初始子段INITL2A、第一晶体管的第一极T13和第二极T14、第二晶体管的第一极T23和第二极T24、第六晶体管的第一极T63、第七晶体管的第二极T74和第八晶体管的第一极T83和第二极T84。
在示例性实施方式中，图37和图38中的第二时钟信号线的第一时钟子段GCK2A、第一时钟信号线的第一时钟子段GCK1A、第二电源线VGL、第一条初始供电线的第一初始子段INITL1A和第二条初始供电线的第一初始子段INITL2A与图20和图21中的第二时钟信号线的第一时钟子段GCK2A、第一时钟信号线的第一时钟子段GCK1A、第二电源线VGL、第一条初始供电线的第一初始子段INITL1A和第二条初始供电线的第一初始子段INITL2A相同。
在示例性实施方式中，如图37和图38所示，第二电源线VGL与第一晶体管的第二极、第二晶体管的第一极T23和第二极T24、第七晶体管的第二极T74和第八晶体管的第一极T83为一体结构，图37和图28中的第二电 源线VGL、第一晶体管的第二极、第二晶体管的第一极T23和第二极T24、第七晶体管的第二极T74和第八晶体管的第一极T83的一体结构与图30和图31中的中的第二电源线VGL、第一晶体管的第二极、第二晶体管的第一极T23和第二极T24、第七晶体管的第二极T74和第八晶体管的第一极T83相同，且通过第二过孔与第一晶体管的有源层的第一区连接，通过第三过孔与第二晶体管的有源层的第一区连接，通过第四过孔与第二晶体管的有源层的第二区连接，通过第六过孔与第七晶体管的有源层的第二区连接，通过第七过孔与第八晶体管的有源层的第一区连接，通过第九过孔与第一晶体管的控制极连接。
在示例性实施方式中，如图37和图38所示，第一晶体管的第一极T13、第六晶体管的第一极T63和第八晶体管的第二极T84为一体结构，且通过第一过孔与第一晶体管的有源层的第一区，通过第十二过孔与第一连接线连接，通过第五过孔与第六晶体管的有源层的第一区连接，通过第八过孔与第八晶体管的有源层的第二区连接，通过第十一过孔暴露出第六晶体管的控制极、第七晶体管的控制极和第八晶体管的控制极的一体结构，通过第十三过孔与第二连接线连接。
(5)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第四导电薄膜，采用图案化工艺对第四绝缘薄膜和第四导电薄膜进行图案化，形成覆盖第三导电层上的第四绝缘层以及设置在第四绝缘层上的第四导电层，如图39和图40所示，图39为图10B的第四导电层的示意图，图40为图10B形成第四导电层的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图39和图40所示，第四导电层图案可以至少包括：第一时钟信号线的第二时钟子段GCK1B、第二时钟信号线的第二时钟子段GCK2B、第一电源线VGH、第一条初始供电线的第二初始子段INITL1B、第二条初始供电线的第二初始子段INITL2B、第一初始信号线GSTV和第二初始信号线ESTV。图39和图40中的第一时钟信号线的第二时钟子段GCK1B、第二时钟信号线的第二时钟子段GCK2B、第一电源线 VGH、第一条初始供电线的第二初始子段INITL1B、第二条初始供电线的第二初始子段INITL2B、第一初始信号线GSTV和第二初始信号线ESTV与图23和图24中的第一时钟信号线的第二时钟子段GCK1B、第二时钟信号线的第二时钟子段GCK2B、第一电源线VGH、第一条初始供电线的第二初始子段INITL1B、第二条初始供电线的第二初始子段INITL2B、第一初始信号线GSTV和第二初始信号线ESTV结构相同，不同之处在于信号线之间的间距。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程与前述实施例提供的制备过程一致，在此不再赘述。
本公开实施例提供的显示基板中的扫描移位寄存器的宽度可以约为200微米至220微米，示例性地，显示基板中的扫描移位寄存器的宽度可以约为210微米。
经仿真，对本公开实施例提供的显示基板与基准显示基板的同位置的负载以及数据信号的上升沿的时间和下降沿进行对比，发现二者差异不大，即本公开实施例提供的显示基板在不影响画质的情况下，减少了显示基板的边框区域所占用的面积，实现了窄边框。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。本公开
本公开实施例还提供一种显示装置，包括：显示基板。
在示例性实施方式中，显示装置可以为显示器、电视、手机、平板电脑、导航仪、数码相框、可穿戴显示产品具有任何显示功能的产品或者部件。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上” 或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (24)

  1. 一种显示基板，包括：基底以及设置在所述基底上的驱动电路层，所述基底包括：显示区域和非显示区域，所述驱动电路层包括：位于所述显示区域的像素驱动电路以及位于所述非显示区域的栅极驱动电路和至少一条初始供电线，所述初始供电线至少部分沿第一方向延伸；
    所述栅极驱动电路被配置为向像素驱动电路提供驱动信号，所述初始供电线被配置为向像素驱动电路提供初始信号；
    至少一条所述初始供电线在基底上的正投影与所述栅极驱动电路在基底上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示基板，其中，所述栅极驱动电路包括：沿第二方向排布的多个驱动电路，所述第一方向与所述第二方向相交；
    至少一条所述初始供电线在基底上的正投影与多个驱动电路中靠近显示区域的驱动电路在基底上的正投影至少部分交叠。
  3. 根据权利要求2所述的显示基板，其中，所述像素驱动电路包括：发光晶体管和写入晶体管，所述多个驱动电路包括：发光驱动电路和扫描驱动电路，所述发光驱动电路与发光晶体管电连接，所述扫描驱动电路与写入晶体管电连接，所述扫描驱动电路位于所述发光驱动电路靠近显示区域的一侧；
    至少一条初始供电线在基底上的正投影与所述扫描驱动电路在基底上的正投影至少部分交叠。
  4. 根据权利要求2所述的显示基板，其中，所述像素驱动电路包括：发光晶体管、写入晶体管和控制晶体管，所述多个驱动电路包括：发光驱动电路、扫描驱动电路和控制驱动电路，所述发光驱动电路与发光晶体管电连接，所述扫描驱动电路与写入晶体管电连接，所述控制驱动电路与控制晶体管电连接，所述写入晶体管和所述控制晶体管的晶体管类型相反；所述发光驱动电路和所述控制驱动电路位于扫描驱动电路远离显示区域的一侧；
    至少一条所述初始供电线在基底上的正投影与所述扫描驱动电路在基底上的正投影至少部分交叠。
  5. 根据权利要求3或4所述的显示基板，其中，至少一条初始供电线包括：第一条初始供电线至第N条初始供电线，N为大于或者等于1的正整数；
    当N大于或者等于2时，N条初始供电线沿第二方向排布，远离显示区域的K条相邻的初始供电线在基底上的正投影与所述扫描驱动电路在基底上的正投影至少部分交叠，K为小于或者等于N的正整数。
  6. 根据权利要求5所述的显示基板，其中，所述驱动电路层还包括：位于非显示区域的第一时钟信号线、第二时钟信号线、第一初始信号线、第一电源线和第二电源线，所述第一时钟信号线、所述第二时钟信号线、所述第一初始信号线、所述第一电源线和所述第二电源线至少部分沿第一方向延伸；
    所述扫描驱动电路分别与第一时钟信号线、第二时钟信号线、第一电源线、第二电源线和第一初始信号线电连接；
    所述第二时钟信号线位于所述第一时钟信号线远离显示区域的一侧，所述第二电源线位于所述第一时钟信号线靠近显示区域的一侧，所述第一初始信号线位于所述第二电源线靠近显示区域的一侧，所述第一电源线位于所述第一初始信号线靠近显示区域的一侧，所述至少一条初始供电线位于所述第一电源线靠近显示区域的一侧。
  7. 根据权利要求6所述的显示基板，其中，所述驱动电路层还包括：位于非显示区域的第二初始信号线，所述第二初始信号线至少部分沿第一方向延伸；
    所述发光驱动电路与所述第二初始信号线与电连接，所述第二初始信号线位于第二电源线和第一初始信号线之间。
  8. 根据权利要求7所述的显示基板，其中，所述驱动电路层还包括：位于非显示区域的第一输出信号线和第二输出信号线，所述第一输出信号线和所述第二输出信号线至少部分沿第二方向延伸；
    所述第一输出信号线位于扫描驱动电路靠近显示区域的一侧，且分别与扫描驱动电路和像素驱动电路电连接；
    所述第二输出信号线穿过所述扫描驱动电路，且分别与像素驱动电路以及发光驱动电路和控制驱动电路中的其中一个驱动电路电连接。
  9. 根据权利要求8所述的显示基板，其中，所述驱动电路层还包括：位于显示区域和非显示区域的第一输出连接线和第二输出连接线，所述第一输出连接线和所述第二输出连接线至少部分沿第二方向延伸；
    所述第一输出连接线，分别与第一输出信号线和像素驱动电路电连接；
    所述第二输出连接线，分别与第二输出信号线和像素驱动电路电连接。
  10. 根据权利要求9所述的显示基板，其中，当N＝2时，所述驱动电路层还包括：第三输出连接线和第四输出连接线，所述第三输出连接线和所述第四输出连接线至少部分沿第二方向延伸；
    所述第三输出连接线，分别与第一条初始供电线和像素驱动电路电连接；
    所述第四输出连接线，分别与第二条初始供电线和像素驱动电路电连接。
  11. 根据权利要求6至10任一项所述的显示基板，其中，所述显示区域的边界包括弧形边界，位于弧形边界外侧的非显示区域称为圆角区域；
    所述扫描驱动电路包括：多个扫描移位寄存器和多个虚拟扫描移位寄存器，多个扫描移位寄存器级联，多个虚拟扫描移位寄存器穿插设置在多个扫描移位寄存器之间；
    多个虚拟扫描移位寄存器至少部分位于圆角区域。
  12. 根据权利要求11所述的显示基板，其中，所述扫描移位寄存器包括：多个晶体管和多个电容；
    与扫描驱动电路存在交叠的初始供电线在基底上的正投影与所述多个电容在基底上的正投影至少部分交叠。
  13. 根据权利要求12所述的显示基板，其中，与扫描驱动电路存在交叠的初始供电线远离显示区域的边界与显示区域之间的距离小于多个电容中的至少一个电容远离显示区域的边界与显示区域之间的距离。
  14. 根据权利要求12或13所述的显示基板，所述虚拟扫描移位寄存器中的晶体管的数量小于或者等于所述扫描移位寄存器中的晶体管的数量；
    所述虚拟扫描移位寄存器的宽度小于或者等于所述扫描移位寄存器的宽度。
  15. 根据权利要求14所述的显示基板，其中，位于虚拟扫描移位寄存器侧面的第二时钟信号线的远离显示区域的边界和至少一条初始供电线中靠近显示区域的初始供电线的靠近显示区域的边界之间的距离小于位于扫描移位寄存器侧面的第二时钟信号线的远离显示区域的边界和至少一条初始供电线中靠近显示区域的初始供电线的靠近显示区域的边界之间的距离。
  16. 根据权利要求12所述的显示基板，其中，所述驱动电路层包括：依次叠设的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；
    所述半导体层至少包括：多个晶体管的有源层；
    所述第一导电层至少包括：多个晶体管的控制极和多个电容的第一极板；
    所述第二导电层至少包括：多个电容的第二极板、第一输出信号线和第三输出信号线；
    所述第三导电层至少包括：第二电源线以及至少一个晶体管的第一极和第二极以及第四输出信号线；
    所述第四导电层至少包括：第一初始信号线、第二初始信号线和第一电源线。
  17. 根据权利要求16所述的显示基板，其中，所述驱动电路层还包括：位于第四导电层远离基底一侧的第五导电层；
    所述第五导电层至少包括：第一输出连接线、第二输出连接线、第三输出连接线和第四输出连接线。
  18. 根据权利要求16所述的显示基板，其中，所述初始供电线为单层结构，且所述初始供电线位于第四导电层。
  19. 根据权利要求16所述的显示基板，其中，所述初始供电线包括：相互连接的第一初始子段和第二初始子段，所述第一初始子段在基底上的正投影与所述第二初始子段在基底上的正投影至少部分交叠；
    所述第一初始子段位于第三导电层，所述第二初始子段位于第四导电层。
  20. 根据权利要求16所述的显示基板，其中，所述第一时钟信号线和所述第二时钟信号线为单层结构，且所述第一时钟信号线和所述第二时钟信号线位于第四导电层。
  21. 根据权利要求16所述的显示基板，其中，时钟信号线包括：相互连接的第一时钟子段和第二时钟子段，所述时钟信号线包括第一时钟信号线和第二时钟信号线，所述第一时钟子段在基底上的正投影与所述第二时钟子段在基底上的正投影至少部分交叠；
    所述第一时钟子段位于第三导电层，所述第二时钟子段第四导电层靠近基底的一侧。
  22. 根据权利要求16所述的显示基板，其中，所述第二输出信号线为单层结构，且所述第二输出信号线位于第二导电层。
  23. 根据权利要求16所述的显示基板，其中，所述驱动电路层还包括：位于所述第二导电层和所述第三导电层之间的第六导电层；
    所述第二输出信号线包括多个第一输出子段和多个第二输出子段，相邻第一输出子段通过第二输出子段电连接，相邻第二输出子段通过第一输出子段电连接，第二输出子段在基底上的正投影与电连接的第一输出子段在基底上的正投影至少部分交叠，第一输出子段在基底上的正投影与电连接的第二输出子段在基底上的正投影至少部分交叠；
    所述第一输出子段位于第二导电层，所述第二输出子段位于第六导电层。
  24. 一种显示装置，包括如权利要求1至23任一项所述的显示基板。
PCT/CN2022/140692 2022-12-21 2022-12-21 显示基板和显示装置 WO2024130591A1 (zh)

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