WO2024065314A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024065314A1
WO2024065314A1 PCT/CN2022/122280 CN2022122280W WO2024065314A1 WO 2024065314 A1 WO2024065314 A1 WO 2024065314A1 CN 2022122280 W CN2022122280 W CN 2022122280W WO 2024065314 A1 WO2024065314 A1 WO 2024065314A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
touch
area
line
extension portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/122280
Other languages
English (en)
French (fr)
Other versions
WO2024065314A9 (zh
Inventor
王思雨
王威
张毅
代俊秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2022/122280 priority Critical patent/WO2024065314A1/zh
Priority to US18/881,332 priority patent/US12699471B2/en
Priority to CN202280003333.2A priority patent/CN118103803A/zh
Publication of WO2024065314A1 publication Critical patent/WO2024065314A1/zh
Publication of WO2024065314A9 publication Critical patent/WO2024065314A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • a display panel with a flexible multi-layer on cell (FMLOC) structure needs to have pins for connecting to the touch function layer in the lower border area of the display panel. More pins will limit the width of the lower border of the display panel.
  • FMLOC flexible multi-layer on cell
  • a display panel comprising: a substrate, a touch function layer, a plurality of first binding pins, a plurality of first touch leads, and a plurality of second touch leads.
  • the substrate comprises a display area and a first frame area, wherein the first frame area is located on one side of the display area in a first direction, and the first frame area comprises a binding area;
  • the touch function layer is located on one side of the substrate, and the touch function layer comprises a plurality of first touch electrodes, wherein the orthographic projection of the first touch electrodes on the substrate is located on the display area;
  • the orthographic projections of the plurality of first binding pins on the substrate are located on the binding area, and the first binding pins are arranged corresponding to the first touch electrodes;
  • the first touch leads are connected between the corresponding first binding pins and the first touch electrodes, and the first touch leads are connected to the first end of the first touch electrodes;
  • the second touch leads are connected between the connected first touch electrodes and the
  • the first touch lead includes a first extension portion
  • the second touch lead includes a second extension portion
  • the orthographic projection of the first extension portion on the base substrate and the orthographic projection of the second extension portion on the base substrate are located in the first border area
  • the display panel also includes: a plurality of first bridge wires, the orthographic projection of the first bridge wire on the base substrate is located in the first border area, and the first bridge wire is connected between the first extension portion and the second extension portion connected to the same first touch electrode.
  • the orthographic projections of multiple first extension portions on the base substrate extend along the first direction and are spaced apart along the second direction, and the second direction intersects the first direction; the orthographic projections of multiple second extension portions on the base substrate extend along the first direction and are spaced apart along the second direction, and the first extension portions and the second extension portions are located in the same conductive layer; the orthographic projections of multiple first bridging wires on the base substrate extend along the second direction and are spaced apart along the first direction, the first bridging wires and the first extension portions are located in different conductive layers, and the first bridging wires are connected to the first extension portions and the second extension portions respectively through vias.
  • the first border area also includes a bending area and a first routing area, the bending area is connected between the binding area and the display area, and the first routing area is connected between the bending area and the binding area; the orthographic projection of the first bridging line on the base substrate, the orthographic projection of the first extension portion on the base substrate, and the orthographic projection of the second extension on the base substrate are all located in the first routing area.
  • the first border area also includes a bending area and a second routing area, the bending area is connected between the binding area and the display area, and the second routing area is connected between the bending area and the display area; the orthographic projection of the first bridging line on the substrate is located in the second routing area.
  • a size of the second routing area in a second direction is greater than a size of the bending area in the second direction, and the second direction intersects with the first direction.
  • the touch function layer also includes a second touch electrode, the first touch electrode includes a plurality of first sub-electrodes, and the second touch electrode includes a plurality of second sub-electrodes;
  • the touch function layer includes: a first electrode layer and a second electrode layer, the first electrode layer is located on one side of the base substrate, the first electrode layer includes the first bridging wire and a connecting bridge, the connecting bridge is used to connect adjacent first sub-electrodes, or the connecting bridge is used to connect adjacent second sub-electrodes;
  • the second electrode layer is located on a side of the first electrode layer away from the base substrate, the second electrode layer includes the first extension portion, the second extension portion, the first sub-electrode, and the second sub-electrode.
  • the first border area also includes a bending area, which is connected between the binding area and the display area; the orthographic projection of the first bridging line on the base substrate, the orthographic projection of the first extension portion on the base substrate, and the orthographic projection of the second extension on the base substrate are all located in the bending area.
  • the bending zone includes a thinning zone and a normal zone distributed in the first direction, the thickness of the display panel located in the thinning zone is less than the thickness of the display panel located in the normal zone; the orthographic projection of the first bridging line on the substrate is located in the normal zone.
  • the display panel also includes: a pixel circuit layer, the pixel circuit layer is located between the base substrate and the touch function layer, the pixel circuit layer includes: a first source and drain layer and a second source and drain layer, the first source and drain layer is located between the base substrate and the touch function layer, the first source and drain layer includes the first bridge line; the second source and drain layer is located between the first source and drain layer and the touch function layer, the second source and drain layer includes the first extension portion and the second extension portion.
  • the arrangement order of the orthographic projections of the first binding pins on the base substrate in the second direction is the same as the arrangement order of the orthographic projections of the first extension parts connected thereto on the base substrate in the second direction, and the second direction intersects with the first direction; the arrangement order of the orthographic projections of the first binding pins on the base substrate in the second direction is opposite to the arrangement order of the orthographic projections of the second extension parts connected thereto on the base substrate in the second direction.
  • the first touch lead includes: a first lead, a first connection, and a first sequence change line.
  • the orthographic projection of the first lead on the substrate extends along the first direction, and the first lead is connected to the first binding pin; the orthographic projection of the first connection on the substrate extends along the first direction, and the first connection is connected to the first end of the first touch electrode; the orthographic projection of the first sequence change line on the substrate extends along the second direction, the second direction intersects with the first direction, and the first sequence change line is connected between the first lead and the first connection.
  • the second touch lead includes: a second lead, a second connection, and a second sequence change line.
  • the orthographic projection of the second lead on the substrate extends along the first direction, and the second lead is connected to the first lead, and the orthographic projections of the connected first lead and second lead on the substrate are adjacently arranged; the orthographic projection of the second connection on the substrate extends along the first direction, and the second connection is connected to the second end of the first touch electrode.
  • the orthographic projection of the second sequence change line on the substrate extends along the second direction, and the second sequence change line is connected between the second lead and the second connection.
  • the arrangement order of the orthogonal projections of the first binding pins on the substrate substrate in the second direction is the same as the arrangement order of the orthogonal projections of the first lead wires connected thereto on the substrate substrate in the second direction; the arrangement order of the orthogonal projections of the first binding pins on the substrate substrate in the second direction is the same as the arrangement order of the orthogonal projections of the second lead wires connected thereto on the substrate substrate in the second direction; the arrangement order of the orthogonal projections of the first binding pins on the substrate substrate in the second direction is the same as the arrangement order of the orthogonal projections of the first connecting wires connected thereto on the substrate substrate in the second direction; the arrangement order of the orthogonal projections of the first binding pins on the substrate substrate in the second direction is opposite to the arrangement order of the orthogonal projections of the second connecting wires connected thereto on the substrate substrate in the second direction.
  • the first lead-out line includes a third extension portion, and the orthographic projection of the third extension portion on the substrate extends along the first direction;
  • the second lead-out line includes a fourth extension portion, and the orthographic projection of the fourth extension portion on the substrate extends along the first direction;
  • the first connecting line includes a fifth extension portion, and the orthographic projection of the fifth extension portion on the substrate extends along the first direction;
  • the second connecting line includes a sixth extension portion, and the orthographic projection of the sixth extension portion on the substrate extends along the first direction;
  • the third extension portion, the fourth extension portion, the fifth extension portion, and the sixth extension portion are located in the same conductive layer,
  • the first sequence-change line and the second sequence-change line are located in the same conductive layer, and the first sequence-change line and the third extension portion are located in different conductive layers,
  • the first sequence-change line is connected to the third extension portion and the fifth extension portion respectively through vias
  • the second sequence-change line is connected to the fourth extension portion and the sixth extension portion respectively
  • the first border area also includes a bending area, which is connected between the binding area and the display area; the third extension portion, the fourth extension portion, the fifth extension portion, the sixth extension portion, the first sequence switching line, and the second sequence switching line are projected on the base substrate in the bending area.
  • the display panel also includes: a pixel circuit layer, the pixel circuit layer is located between the base substrate and the touch function layer, the pixel circuit layer includes: a first source and drain layer and a second source and drain layer, the first source and drain layer is located between the base substrate and the touch function layer, the first source and drain layer includes the first sequence switching line and the second sequence switching line; the second source and drain layer is located between the first source and drain layer and the touch function layer, the second source and drain layer includes the third extension portion, the fourth extension portion, the fifth extension portion, and the sixth extension portion.
  • the bending zone includes a thinning zone and a normal zone distributed in the first direction, the thickness of the display panel located in the thinning zone is less than the thickness of the display panel located in the normal zone; the orthographic projections of the first switching line and the second switching line on the substrate are located in the normal zone.
  • the touch function layer also includes: a second touch electrode, the first touch electrode includes a plurality of first sub-electrodes distributed in the same direction, the second touch electrode includes a plurality of second sub-electrodes distributed in the same direction, and the distribution direction of the first sub-electrodes intersects with the distribution direction of the second sub-electrodes; the first sub-electrode and the second sub-electrode are located in the same conductive layer, and the size of the orthographic projection of the first touch electrode on the base substrate in its extension direction is greater than the size of the orthographic projection of the second touch electrode on the base substrate in its extension direction.
  • the display panel also includes: a first protection line, the first protection line is used to provide a touch signal, the first protection line includes: a third lead line, a third connecting line, and a third sequence-changing line, the orthographic projection of the third lead line on the substrate extends along the first direction, the third lead line is connected to the second binding pin, and the orthographic projections of all the first lead lines on the substrate and all the orthographic projections of the second lead lines on the substrate are located on the same side of the orthographic projection of the third lead line on the substrate; a third connecting line, the orthographic projection of the third connecting line on the substrate extends along the first direction, the orthographic projection of the third connecting line on the substrate is located between the orthographic projections of adjacent first connecting line and second connecting line on the substrate; the orthographic projection of the third sequence-changing line on the substrate extends along the second direction, and the third sequence-changing line is connected between the third lead line and the third connection.
  • a third connecting line the orthographic projection of the third connecting line on the substrate extends along the
  • a display device comprising the above-mentioned display panel.
  • FIG1 is a schematic diagram of the structure of a display panel in the related art
  • FIG2 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG3 is a cross-sectional view of the display panel along dotted line AA of FIG2 ;
  • FIG4 is a partial enlarged view of area DD in FIG2 ;
  • FIG5 is a schematic structural diagram of a first border area in an exemplary embodiment of a display panel disclosed herein;
  • FIG6 is a schematic structural diagram of a first border area in another exemplary embodiment of a display panel disclosed herein;
  • FIG7 is a schematic structural diagram of a first border area in another exemplary embodiment of a display panel disclosed herein;
  • FIG8 is a schematic structural diagram of a first border area in another exemplary embodiment of a display panel disclosed herein;
  • FIG9 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;
  • FIG10 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG9 ;
  • FIG11 is a structural layout diagram of a pixel circuit layer in an exemplary embodiment of a display panel disclosed herein;
  • FIG12 is a structural diagram of the active layer in FIG11;
  • FIG13 is a structural layout diagram of the first gate layer in FIG11 ;
  • FIG14 is a structural layout diagram of the second gate layer in FIG11;
  • FIG15 is a structural layout diagram of the first source and drain layer in FIG11 ;
  • FIG16 is a structural layout diagram of the second source and drain layer in FIG11 ;
  • FIG17 is a structural diagram of the anode layer in FIG11 ;
  • FIG18 is a structural layout diagram of the active layer and the first gate layer in FIG11 ;
  • FIG19 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in FIG11 ;
  • FIG20 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source and drain layer in FIG11 ;
  • FIG21 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, the first source and drain layer, and the second source and drain layer in FIG11 ;
  • FIG. 22 is a partial cross-sectional view taken along dashed line EE in FIG. 11 .
  • the display panel may include a display area AA and a first frame area Pad.
  • the display panel may also include a touch function layer, and the touch function layer may include: a first touch electrode Tx and a second touch electrode Rx.
  • the first touch electrode Tx may include a plurality of first sub-electrodes Tx1 and a first connecting bridge Ltx, the first sub-electrodes Tx1 may be spaced along the first direction X, and the first connecting bridge Ltx may be connected between adjacent first sub-electrodes Tx1 in the first direction X.
  • the second touch electrode Rx may include a plurality of second sub-electrodes Rx2 and a second connecting bridge Lrx, the second sub-electrodes Rx2 may be spaced along the second direction Y, and the second connecting bridge Lrx may be connected between adjacent second sub-electrodes Rx2 in the second direction Y.
  • the first touch electrode Tx and the second touch electrode Rx may form a mutual capacitance structure, and the touch position may be determined by the change in capacitance.
  • the display panel may further include a first touch lead L1, a second touch lead L2, and a third touch lead L3.
  • the third touch lead L3 is connected between the second touch electrode Rx and the third binding pin Pin3 located on the first frame area Pad.
  • the first touch lead L1 is connected between the first binding pin Pin1 located on the first frame area Pad and the first end of the first touch electrode Tx
  • the second touch lead L2 is connected between the first binding pin Pin1 located on the first frame area Pad and the second end of the first touch electrode Tx.
  • the display panel can provide a touch signal to the same first touch electrode Tx through the first touch lead L1 and the second touch lead L2, and this setting can improve the touch delay problem.
  • the display panel needs to be provided with more first binding pins Pin1, so that this setting increases the size of the first frame area Pad in the second direction Y.
  • this exemplary embodiment provides a display panel, as shown in Figure 2, which is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed in the present disclosure.
  • the display panel includes: a base substrate, a touch function layer, a plurality of first binding pins Pin1, a plurality of first touch leads L1, and a plurality of second touch leads L2.
  • the base substrate includes a display area AA and a first frame area BB, the first frame area BB is located on one side of the display area AA in the first direction X, and the first frame area BB includes a binding area B1;
  • the touch function layer is located on one side of the base substrate, and the touch function layer includes a plurality of first touch electrodes Tx, and the orthographic projection of the first touch electrode Tx on the base substrate is located in the display area AA;
  • the orthographic projection of a plurality of first binding pins Pin1 on the base substrate is located in the binding area B1, and the first binding pins Pin1 are arranged corresponding to the first touch electrode Tx;
  • the first touch lead L1 is connected between the corresponding first binding pin Pin1 and the first touch electrode Tx, and the first touch lead L1 is connected to the first end of the first touch electrode Tx;
  • the second touch lead L2 is connected between the connected first touch electrode Tx and the first touch lead L1, and the second touch lead L2 is connected to the second end
  • the display panel provided by this exemplary embodiment connects the second touch lead L2 to the first touch lead L1, and the same first binding pin Pin1 can provide touch signals to the first touch lead L1 and the second touch lead L2 at the same time.
  • the display panel can reduce the number of first binding pins while improving touch delay.
  • the display panel may include a base substrate 90, a pixel circuit layer 01, an encapsulation layer 02, a touch function layer, and a protective layer 04, which are stacked in sequence.
  • the pixel circuit layer 01 may include a pixel driving circuit and a light-emitting unit. As shown in FIGS.
  • the touch function layer may include a first electrode layer located on the side of the encapsulation layer 02 away from the base substrate 90, an insulating layer 03 located on the side of the first electrode layer away from the base substrate, and a second electrode layer located on the side of the insulating layer 03 away from the base substrate 90.
  • the first electrode layer may include a first connection bridge Ltx
  • the second electrode layer may include a first sub-electrode Tx1, a second sub-electrode Rx2, and a second connection bridge Lrx.
  • a plurality of second sub-electrodes Rx2 distributed in the second direction Y may be sequentially connected through the second connection bridge Lrx to form a second touch electrode Rx; a plurality of first sub-electrodes Tx1 distributed in the first direction X may be sequentially connected through the first connection bridge Ltx to form a first touch electrode Tx.
  • the first touch electrode Tx and the second touch electrode Rx may form a mutual capacitance structure, and the touch position may be determined by the capacitance change.
  • the first frame area BB may further include a bending area B2, a first routing area B3, and a second routing area B4, wherein the bending area B2 is connected between the display area AA and the binding area B1, the first routing area B3 is connected between the bending area B2 and the binding area B1, and the second routing area B4 is connected between the bending area B2 and the display area AA.
  • the first touch lead line L1 and the second touch lead line L2 located in the bending area B2 may be located in the second source and drain layer in the pixel circuit layer, the first touch lead line L1 and the second touch lead line L2 located in the first routing area B3 and the second routing area B4 may be located in the second electrode layer in the touch function layer, and the size of the second routing area B4 in the second direction Y is greater than the size of the bending area B2 in the second direction Y.
  • the encapsulation layer 02 may not cover the bending area B2, the first routing area B3, and the binding area B1.
  • the first touch lead L1 may include a first extension portion L11
  • the second touch lead L2 may include a second extension portion L22
  • the orthographic projection of the first extension portion L11 on the substrate and the orthographic projection of the second extension portion L22 on the substrate may be located in the first frame area BB
  • the display panel may also include: a plurality of first bridge wires Q1, the orthographic projection of the first bridge wire Q1 on the substrate may be located in the first frame area BB, and the first bridge wire Q1 is connected between the first extension portion L11 and the second extension portion L22 connected to the same first touch electrode.
  • the display panel provided by this exemplary embodiment connects the first touch lead L1 and the second touch lead L2 through the first bridge wire Q1 located in the first frame area BB.
  • the first touch lead L1 and the second touch lead L2 may also have other connection methods, for example, the first touch lead L1 and the second touch lead L2 may be connected through bridge wires located in other frame areas of the display panel.
  • the orthographic projections of the plurality of first extension portions L11 on the base substrate may extend along the first direction X and be spaced apart along the second direction Y, the second direction Y intersecting the first direction X, for example, the first direction X may be a column direction, and the second direction Y may be a row direction.
  • the orthographic projections of the plurality of second extension portions L22 on the base substrate may extend along the first direction X and be spaced apart along the second direction Y, the first extension portion L11 and the second extension portion L22 may be located in the same conductive layer; the orthographic projections of the plurality of first bridge wires Q1 on the base substrate may extend along the second direction Y and be spaced apart along the first direction X, the first bridge wire Q1 and the first extension portion L11 may be located in different conductive layers, and the first bridge wire Q1 may be connected to the first extension portion L11 and the second extension portion L22 through vias, respectively.
  • the size of the orthographic projection of the first touch electrode Tx on the base substrate in the extension direction (first direction X) thereof may be greater than the size of the orthographic projection of the second touch electrode (Rx) on the base substrate in the extension direction (second direction Y) thereof.
  • the first touch electrode Tx may be a driving electrode
  • the second touch electrode Rx may be a sensing electrode.
  • the first touch electrode Tx may also be a sensing electrode
  • the second touch electrode Rx may also be a driving electrode.
  • the orthographic projection of the first touch electrode Tx on the base substrate may also extend along the second direction Y
  • the orthographic projection of the second touch electrode Rx on the base substrate may also extend along the first direction X.
  • the first sub-electrode Tx1 may include a first physical part STx1 and a first virtual part DTx1, the first virtual part DTx1 and the first physical part STx1 are not connected, and the first virtual part DTx1 can adjust the capacitance between the first sub-electrode Tx1 and the second sub-electrode Rx2.
  • the second sub-electrode Rx2 includes a second physical part SRx2 and a second virtual part DRx2, the second virtual part DRx2 and the second physical part SRx2 are not connected, and the second virtual part DRx2 can adjust the capacitance between the first sub-electrode Tx1 and the second sub-electrode Rx2.
  • a plurality of first protrusions Tx11 are arranged at the edge of the first physical part STx1, and a plurality of second protrusions Rx22 are arranged at the edge of the second physical part SRx2, and the first protrusions Tx11 and the second protrusions Rx22 are arranged alternately, so that a lateral capacitor with a large capacitance can be formed between the first sub-electrode Tx1 and the second sub-electrode Rx2.
  • FIG5 it is a schematic diagram of the structure of the first frame area in an exemplary embodiment of the display panel of the present disclosure.
  • the first touch lead wire L1 and the second touch lead wire L2 located in the bending area B2 can be located in the second source and drain layer in the pixel circuit layer
  • the first touch lead wire L1 and the second touch lead wire L2 located in the first wiring area B3 and the second wiring area B4 can be located in the second electrode layer in the touch function layer
  • the first bridge wire Q1 can be located in the first electrode layer in the touch function layer.
  • the first touch lead wire L1 located in the bending area B2 can be connected to the first touch lead wire L1 located in the first wiring area B3 and the second wiring area B4 through the via H, respectively, and the second touch lead wire L2 located in the bending area B2 can be connected to the second touch lead wire L2 located in the first wiring area B3 and the second wiring area B4 through the via.
  • the black circle can represent the position of the via.
  • the orthographic projection of the first bridge line Q1 on the substrate substrate, the orthographic projection of the first extension portion L11 on the substrate substrate, and the orthographic projection of the second extension portion L22 on the substrate substrate can all be located in the first routing area B3.
  • the orthographic projection of the first extension portion L11 on the substrate substrate or the orthographic projection of the second extension portion L22 on the substrate substrate has at least a partial overlap area with the orthographic projection of the first bridge line Q1 on the substrate substrate, that is, at least partially intersects. As shown in FIG5 , the orthographic projection of the first extension portion L11 on the substrate substrate has at least a partial overlap area with the orthographic projection of the first bridge line Q1 on the substrate substrate.
  • the display panel may further include a first protection line Gd1, a second protection line Gd2, a third protection line Gd3, a first ground line GND1, and a second ground line GND2.
  • the orthographic projection of the first protection line Gd1 on the base substrate is located between the orthographic projections of the adjacent first touch lead L1 and the second touch lead L2 on the base substrate.
  • the adjacent first touch lead L1 and the second touch lead L2 may refer to the first touch lead L1 and the second touch lead L2 without the first touch lead L1 or the second touch lead L2 therebetween.
  • the orthographic projection of the second protection line Gd2 on the substrate can be located on a side where the orthographic projections of all second touch leads L2 on the substrate are away from the orthographic projection of the first protection line Gd1 on the substrate;
  • the orthographic projection of the third protection line Gd3 on the substrate can be located on a side where the orthographic projections of all first touch leads L1 on the substrate are away from the orthographic projection of the first protection line Gd1 on the substrate;
  • the orthographic projection of the first ground line GND1 on the substrate is located on a side where the orthographic projection of the third protection line Gd3 on the substrate is away from the orthographic projection of the first touch lead L1 on the substrate, and the orthographic projection of the second ground line GND2 on the substrate is located on a side where the orthographic projection of the second protection line Gd2 on the substrate is away from the orthographic projection of the second touch lead L2 on the substrate.
  • the first protection line Gd1, the second protection line Gd2, the third protection line Gd3, the first ground line GND1, and the second ground line GND2 located in the bending area B2 can be located in the second source and drain layer in the pixel circuit layer; the first protection line Gd1, the second protection line Gd2, the third protection line Gd3, the first ground line GND1, and the second ground line GND2 located in the first routing area B3 and the second routing area B4 can be located in the second electrode layer in the touch function layer.
  • the first protection line Gd1, the second protection line Gd2, and the second ground line GND2 can extend in the extension direction of the second touch lead L2; the third protection line Gd3 and the first ground line GND1 can extend in the extension direction of the first touch lead L1.
  • the first protection line Gd1, the second protection line Gd2, and the third protection line Gd3 can be used to receive touch signals.
  • the first protection line Gd1 and the second protection line Gd2 can make the second touch lead L2 adjacent thereto and other second touch leads L2 have the same electric field environment.
  • the third protection line Gd3 can make the first touch lead L1 adjacent thereto and other first touch leads L1 have the same electric field environment. It should be noted that the first protection line Gd1, the second protection line Gd2, and the third protection line Gd3 are not connected to the first touch electrode Tx and the second touch electrode Rx.
  • the first ground line GND1 and the second ground line GND2 can be used to provide a stable power supply signal. For example, the first ground line GND1 and the second ground line GND2 can be grounded.
  • the first ground line GND1 and the second ground line GND2 can shield the noise interference of other signals on the first touch lead L1 and the second touch lead L2.
  • the first bridge wire may also be located at other positions.
  • FIG6 it is a schematic diagram of the structure of the first border area in another exemplary embodiment of the display panel disclosed in the present invention.
  • the orthographic projections of the first bridge wire Q1, the first extension portion L11, and the second extension portion L22 on the substrate substrate may be located in the second wiring area B4.
  • the first extension portion L11 and the second extension portion L22 may be located in the second electrode layer, and correspondingly, the first bridge wire Q1 may be located in the first electrode layer.
  • first touch lead wire L1 and the second touch lead wire L2 located in the bending area B2 may be located in the second source and drain layer in the pixel circuit layer, and the first touch lead wire L1 and the second touch lead wire L2 located in the first wiring area B3 and the second wiring area B4 may be located in the second electrode layer in the touch function layer.
  • FIG. 7 it is a schematic diagram of the structure of the first border area in another exemplary embodiment of the display panel of the present disclosure.
  • the orthographic projections of the first bridge wire Q1, the first extension portion L11 and the second extension portion L22 on the substrate can be located in the bending area B2.
  • the first extension portion L11 and the second extension portion L22 are located in the second source and drain layer, and accordingly, the first bridge wire Q1 can be located in the first source and drain layer in the pixel circuit layer.
  • first touch lead wire L1 and the second touch lead wire L2 located in the bending area B2 can be located in the second source and drain layer in the pixel circuit layer, and the first touch lead wire L1 and the second touch lead wire L2 located in the first wiring area B3 and the second wiring area B4 can be located in the second electrode layer in the touch function layer.
  • the bending area B2 includes a thinning area B22 and a normal area B21 distributed in the first direction X, and the thickness of the display panel in the thinning area B22 is less than the thickness of the display panel in the normal area B21; the orthographic projection of the first bridge wire Q1 on the base substrate is located in the normal area B21.
  • the display panel may not be provided with a protective layer 04 and/or at least a portion of the inorganic layer in the pixel circuit layer at the location of the thinning area B22, and this arrangement may enable the display panel to bend at a larger bending angle at the location of the thinning area B22. It should be understood that in other exemplary embodiments, the display panel may also reduce the thickness of the display panel in the thinning area B22 by thinning the protective layer 04 and/or at least a portion of the inorganic layer in the pixel circuit layer.
  • the arrangement order of the orthographic projection of the first binding pin Pin1 on the base substrate in the second direction Y and the arrangement order of the orthographic projection of the first extension portion L11 connected thereto on the base substrate in the second direction Y may be the same; the arrangement order of the orthographic projection of the first binding pin Pin1 on the base substrate in the second direction Y and the arrangement order of the orthographic projection of the second extension portion L22 connected thereto on the base substrate in the second direction Y are opposite.
  • the first touch lead L1 and the second touch lead L2 may also have other connection methods.
  • FIG8 it is a schematic diagram of the structure of the first border area in another exemplary embodiment of the display panel of the present disclosure.
  • the first touch lead L1 may include: a first lead L1a, a first connection line L1b, and a first sequence change line L1c, wherein the orthographic projection of the first lead L1a on the base substrate extends along the first direction X, and the first lead L1a is connected to the first binding pin Pin1; the orthographic projection of the first connection line L1b on the base substrate extends along the first direction X, and the first connection line L1b is connected to the first end of the first touch electrode Tx, and the orthographic projection of the first sequence change line L1c on the base substrate extends along the second direction Y, and the first sequence change line L1c is connected between the first lead L1a and the first connection line L1b.
  • the second touch lead L2 may include: a second lead line L2a, a second connection line L2b, and a second sequence-changing line L2c.
  • the orthographic projection of the second lead line L2a on the base substrate extends along the first direction X.
  • the second lead line L2a is connected to the first lead line L1a.
  • the orthographic projections of the connected first lead line L1a and the second lead line L2a on the base substrate are adjacently arranged, that is, no first lead line L1a or second lead line L2a is arranged between the connected first lead line L1a and the second lead line L2a.
  • the orthographic projection of the second connection line L2b on the base substrate extends along the first direction X.
  • the second connection line L2b is connected to the second end of the first touch electrode.
  • the orthographic projection of the second sequence-changing line L2c on the base substrate extends along the second direction Y.
  • the second sequence-changing line L2c is connected between the second lead line L2a and the second connection line L2b.
  • the first touch lead L1 is connected to the second lead wire L2a of the second touch lead L2 through the first lead wire L1a, thereby realizing the connection between the first touch lead L1 and the second touch lead L2.
  • this exemplary embodiment changes the sequence of the first lead wire L1a through the first sequence change line L1c, and changes the sequence of the second lead wire L2a through the second sequence change line L2c, so that the lead-out order of the first connection line L1b and the second connection line L2b meets the requirements of connecting the first touch electrode.
  • the arrangement order of the orthogonal projection of the first binding pin Pin1 on the base substrate in the second direction Y is the same as the arrangement order of the orthogonal projection of the first lead line L1a connected thereto on the base substrate in the second direction Y; the arrangement order of the orthogonal projection of the first binding pin Pin1 on the base substrate in the second direction Y is the same as the arrangement order of the orthogonal projection of the second lead line L2a connected thereto on the base substrate in the second direction Y; the arrangement order of the orthogonal projection of the first binding pin Pin1 on the base substrate in the second direction Y is the same as the arrangement order of the orthogonal projection of the first connecting line L1b connected thereto on the base substrate in the second direction Y; the arrangement order of the orthogonal projection of the first binding pin Pin1 on the base substrate in the second direction Y is opposite to the arrangement order of the orthogonal projection of the second connecting line L2b connected thereto on the base substrate in the second direction Y.
  • the first lead-out line L1a may include a third extension portion L13, the orthographic projection of the third extension portion L13 on the substrate extends along the first direction X;
  • the second lead-out line L2a includes a fourth extension portion L24, the orthographic projection of the fourth extension portion L24 on the substrate extends along the first direction X;
  • the first connecting line L1b includes a fifth extension portion L15, the orthographic projection of the fifth extension portion L15 on the substrate extends along the first direction X;
  • the second connecting line L2b includes a sixth extension portion L26, the orthographic projection of the sixth extension portion L26 on the substrate extends along the first direction X;
  • the third extension portion L13, the fourth extension portion L24, the fifth extension portion L15, and the sixth extension portion L26 Located in the same conductive layer, the first sequence-changing line Lac and the second sequence-changing line L2c are located in the same conductive layer, and the first sequence-changing line L1c and the third extension portion L13 are
  • the orthographic projections of the third extension portion L13 , the fourth extension portion L24 , the fifth extension portion L15 , the sixth extension portion L26 , the first switching line L1c , and the second switching line L2c on the substrate may all be located in the bending area B2 .
  • the first switching line L1c and the second switching line L2c can be located in the first source and drain layer in the pixel circuit layer, and the third extension portion L13, the fourth extension portion L24, the fifth extension portion L15, and the sixth extension portion L26 can be located in the second source and drain layer in the pixel circuit layer.
  • the bending zone B2 may also include a thinning zone B22 and a normal zone B21 distributed in the first direction X, and the thickness of the display panel located in the thinning zone B22 is less than the thickness of the display panel located in the normal zone B21; the orthographic projections of the first switching line L1c and the second switching line L2c on the base substrate may be located in the normal zone B21.
  • the display panel may also include: a first protection line Gd1, the first protection line Gd1 can be used to provide a touch signal, the first protection line Gd1 may include: a third lead line Gd1a, a third connecting line Gd1b, and a third sequence change line Gd1c, the orthographic projection of the third lead line Gd1a on the base substrate extends along the first direction X, the third lead line Gd1a can be connected to the second binding pin Pin2, and the orthographic projection of the second binding pin Pin2 on the base substrate is located in the binding area B1.
  • the orthographic projections of all the first lead wires L1a on the base substrate and the orthographic projections of all the second lead wires L2a on the base substrate are located on the same side of the orthographic projection of the third lead wire Gd1a on the base substrate;
  • the orthographic projection of the third connecting wire Gd1b on the base substrate extends along the first direction X, and the orthographic projection of the third connecting wire Gd1b on the base substrate is located between the orthographic projections of the adjacent first connecting wire L1b and the adjacent second connecting wire L2b on the base substrate;
  • the orthographic projection of the third sequence-changing wire Gd1c on the base substrate extends along the second direction Y, and the third sequence-changing wire Gd1c is connected between the third lead wire Gd1a and the third connecting wire Gd1b.
  • the adjacent first connecting wire L1b and the second connecting wire L2b may refer to the first connecting wire L1b and the second connecting wire L2b between which the first connecting wire L1b or the second connecting wire L2b is not arranged.
  • the orthographic projection of the third lead wire Gd1a on the base substrate may be located in the normal area B21.
  • Figures 1-2 and 5-8 show the relative position relationship of the first border area BB, the display area AA, the binding area B1, the bending area B2, the first routing area B3, the second routing area B4, the normal area B21, and the thinning area B22.
  • the size of each area can also be other values, and the routing in each area can also have other routing methods.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the node N, and the gate is connected to the first reset signal terminal Re1;
  • the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3;
  • the gate is connected to the gate driving signal terminal Gate;
  • the gate of the driving transistor T3 is connected to the node N;
  • the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the gate driving signal terminal Gate;
  • the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the capacitor C is connected between the gate of the driving transistor T3 and the first power supply terminal VDD.
  • the pixel driving circuit can be connected to a light-emitting unit OLED, and the pixel driving circuit can be used to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS.
  • the transistors T1 - T7 may all be P-type transistors.
  • FIG10 it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG9.
  • Gate represents the timing of the gate driving signal terminal Gate
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the reset signal terminal Re1 outputs a low-level signal
  • the first transistor T1 is turned on
  • the first initial signal terminal Vinit1 inputs the first initial signal to the node N.
  • the compensation stage t2 the second reset signal terminal Re2 and the gate driving signal terminal Gate output low-level signals, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and at the same time the data signal terminal Da outputs a driving signal to write a compensation voltage Vdata+Vth to the node N, wherein Vdata is the voltage of the driving signal, Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal Vinit2 inputs the second initial signal to the second electrode of the sixth transistor T6.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit OLED to emit light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the output current formula of the driving transistor I ( ⁇ WCox/2L)(Vgs-Vth)2, where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the threshold of the driving transistor on its output current.
  • the pixel circuit layer may include an active layer, a first gate layer, a second gate layer, a first source-drain layer, a second source-drain layer, and an anode layer stacked sequentially on the base substrate, with an insulating layer disposed between the layers.
  • Figure 11 is a structural layout of a pixel circuit layer in an exemplary embodiment of the display panel disclosed in the present invention
  • Figure 12 is a structural layout of an active layer in Figure 11
  • Figure 13 is a structural layout of a first gate layer in Figure 11
  • Figure 14 is a structural layout of a second gate layer in Figure 11
  • Figure 15 is a structural layout of a first source-drain layer in Figure 11
  • Figure 16 is a structural layout of a second source-drain layer in Figure 11
  • Figure 17 is a structural layout of an anode layer in Figure 11
  • Figure 18 is a structural layout of an active layer and a first gate layer in Figure 11
  • Figure 19 is a structural layout of an active layer, a first gate layer, and a second gate layer in Figure 11
  • Figure 20 is a structural layout of an active layer, a first gate layer, a second gate layer, and a first source-drain layer in Figure 11
  • Figure 21 is a structural layout of an active layer, a first gate layer, a second gate layer
  • the active layer may include a third active portion 43, a fourth active portion 44, a fifth active portion 45, a sixth active portion 46, a seventh active portion 47, an eighth active portion 48, a ninth active portion 49, a tenth active portion 410, an eleventh active portion 411, a twelfth active portion 412, a thirteenth active portion 413, a first sub-active portion 421, a second sub-active portion 422, a third sub-active portion 423, a fourth sub-active portion 414, a fifth sub-active portion 415, and a sixth sub-active portion 416.
  • the first sub-active portion 421 and the second sub-active portion 422 may be used to form a channel region of the second transistor T2, and the fourth sub-active portion 414 and the fifth sub-active portion 415 may be used to form a first transistor T1.
  • the third active portion 43 may be used to form a channel region of the driving transistor T3, the fourth active portion 44 may be used to form a channel region of the fourth transistor T4, the fifth active portion 45 may be used to form a channel region of the fifth transistor T5, the sixth active portion 46 may be used to form a channel region of the sixth transistor T6, the seventh active portion 47 may be used to form a channel region of the seventh transistor T7, the third sub-active portion 423 is connected between the first sub-active portion 421 and the second sub-active portion 422, the sixth sub-active portion 416 is connected to the fourth sub-active portion 414 and the fifth sub-active portion 416.
  • the eighth active portion 48 is connected to one end of the fifth sub-active portion 415 away from the sixth sub-active portion 416
  • the ninth active portion 49 is connected between the second sub-active portion 422 and the fourth sub-active portion 414
  • the tenth active portion 410 is connected to one end of the fourth active portion 44 away from the third active portion 43
  • the eleventh active portion 411 is connected between the seventh active portion 47 and the sixth active portion 46
  • the twelfth active portion 412 is connected to one end of the fifth active portion 45 away from the third active portion 43
  • the thirteenth active portion 413 is connected to one end of the seventh active portion 47 away from the sixth active portion 46.
  • the active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low temperature polysilicon thin film transistors.
  • the first gate layer may include: a first reset signal line Re1, a second reset signal line Re2, a gate drive signal line Gate, an enable signal line EM, and a first conductive portion 11.
  • the first reset signal line Re1 can be used to provide a reset signal to the first reset signal terminal in Figure 9
  • the second reset signal line Re2 can be used to provide a reset signal to the second reset signal terminal in Figure 9
  • the gate drive signal line Gate can be used to provide a drive signal to the gate drive signal terminal in Figure 9
  • the enable signal line EM can be used to provide an enable signal to the enable signal terminal in Figure 9.
  • the positive projections of the first reset signal line Re1, the second reset signal line Re2, the gate drive signal line Gate, and the enable signal line EM on the substrate can all extend along the second direction Y.
  • Part of the structure of the first reset signal line Re1 can be used to form the gate of the first transistor T1
  • the part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7
  • the part of the structure of the gate drive signal line Gate can be used to form the gate of the second transistor and the gate of the fourth transistor
  • the part of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6 and the gate of the fifth transistor T5.
  • the first conductive portion 11 may cover the third active portion 43 when projected on the substrate, and the first conductive portion 11 may be used to form the gate of the driving transistor T3 and an electrode of the capacitor C.
  • the second reset signal line Re2 in the pixel driving circuit of this row may be reused as the first reset signal line Re1 in the pixel driving circuit of the next row.
  • the display panel can use the patterned first gate layer as a mask to perform conductor processing on the active layer, that is, the portion blocked by the first gate layer forms a channel region of the transistor, and the portion not blocked by the first gate layer forms a conductor structure.
  • the second gate layer may include: a first initial signal line Vinit1, a second initial signal line Vinit2, a second conductive portion 22, and a third conductive portion 23.
  • the first initial signal line Vinit1 is used to provide a first initial signal to the first initial signal terminal in Figure 9
  • the second initial signal line Vinit1 is used to provide a second initial signal to the second initial signal terminal in Figure 9.
  • the orthographic projection of the second initial signal line Vinit2 on the substrate substrate may overlap with the orthographic projection of the sixth sub-active portion 416 on the substrate substrate, and the second initial signal line Vinit2 may stabilize the sixth sub-active portion 416, thereby reducing the leakage current of the sixth sub-active portion 416 to the source and drain of the first transistor.
  • the orthographic projection of the second conductive portion 22 on the substrate substrate at least partially overlaps with the orthographic projection of the first conductive portion 11 on the substrate substrate, and the second conductive portion 22 is used to form the second electrode of the capacitor.
  • the third conductive part 23 can be connected to a stable power supply, and the orthographic projection of the third conductive part 23 on the substrate can overlap with the orthographic projection of the third sub-active part 423 on the substrate, and the third conductive part 23 can stabilize the third sub-active part 423, thereby reducing the leakage current of the third sub-active part 423 to the source and drain of the second transistor.
  • the first source-drain layer may include: a first initial connection line 3Vinit1, a second initial connection line 3Vinit2, a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, a fourth bridge portion 34, and a power line VDD.
  • the orthographic projections of the first initial connection line 3Vinit1, the second initial connection line 3Vinit2, and the power line VDD on the substrate may extend along the first direction X.
  • the first bridge portion 31 may be connected to the ninth active portion 49 and the first conductive portion 11 through vias, respectively, to connect the gate of the driving transistor and the second pole of the first transistor and the first pole of the second transistor, and an opening 221 is formed on the second conductive portion 22.
  • the orthographic projection of the via connected between the first conductive portion 11 and the first bridge portion 31 on the substrate substrate may be located within the orthographic projection of the opening 221 on the substrate substrate, so as to insulate the via and the second conductive portion 22.
  • the second bridge portion 32 may be connected to the eleventh active portion 411 through a via to connect the second pole of the sixth transistor.
  • the third bridge portion 33 may be connected to the tenth active portion 410 through a via hole to connect the first electrode of the fourth transistor.
  • the fourth bridge portion 34 may be connected to the first initial signal line Vinit1 and the eighth active portion 48 through via holes to connect the first electrode of the first transistor and the first initial signal terminal.
  • the power line VDD may provide a power signal to the first power terminal in FIG.
  • a first initial connection line 3Vinit1 and a second initial connection line 3Vinit2 are correspondingly provided for every two columns of pixel driving circuits.
  • the first initial connection line 3Vinit1 can be connected to the eighth active part 48 and the first initial signal line Vinit1 through vias to connect the first electrode and the first initial signal end of the first transistor.
  • the first initial connection line 3Vinit1 can form a grid structure of the first initial signal line Vinit1 to reduce the resistance of the first initial signal line Vinit1.
  • the second initial connection line 3Vinit2 can be connected to the second initial signal line Vinit2 and the thirteenth active part 413 through vias to connect the first electrode and the second initial signal end of the seventh transistor.
  • the second initial connection line 3Vinit2 can form a grid structure of the second initial signal line Vinit2 to reduce the resistance of the second initial signal line Vinit2.
  • the second source-drain layer may include: a data line Da and a fifth bridge portion 55, the orthographic projection of the data line Da on the substrate may extend along the first direction X, the data line Da may provide a driving signal to the data signal terminal in FIG. 9, and the data line Da may be connected to the third bridge portion 33 through a via hole to connect the first electrode of the fourth transistor and the data signal terminal.
  • the fifth bridge portion 55 may be connected to the second bridge portion 32 through a via hole.
  • the anode layer may include a plurality of anode portions, and the plurality of anode portions may include a first anode portion R, a second anode portion G, and a third anode portion B.
  • the first anode portion R is used to form an anode of a red light-emitting unit
  • the second anode portion G is used to form an anode of a green light-emitting unit
  • the third anode portion B is used to form an anode of a blue light-emitting unit.
  • the anode portion may be connected to the fifth bridge portion 55 through a via hole.
  • the black squares drawn on the side of the anode layer away from the substrate substrate indicate that the anode layer is connected to the via holes of other levels facing the substrate substrate side; the black squares drawn on the side of the second source and drain layer away from the substrate substrate indicate that the second source and drain layer is connected to the via holes of other levels facing the substrate substrate side; the black squares drawn on the side of the first source and drain layer away from the substrate substrate indicate that the first source and drain layer is connected to the via holes of other levels facing the substrate substrate side.
  • the black squares indicate the positions of the via holes, and different via holes represented by black squares at different positions can pass through different insulating layers.
  • the pixel circuit layer may also include a pixel definition layer and a light-emitting unit layer located on the side of the anode layer away from the substrate substrate.
  • the display panel may also include: a first insulating layer 91, a second insulating layer 92, a dielectric layer 93, a passivation layer 94, a first flat layer 95, and a second flat layer 96.
  • the base substrate 90, the active layer, the first insulating layer 91, the first gate layer, the second insulating layer 92, the second gate layer, the dielectric layer 93, the first source and drain layer, the passivation layer 94, the first flat layer 95, the second source and drain layer, the second flat layer 96, and the anode layer may be stacked in sequence.
  • the first insulating layer 91 and the second insulating layer 92 may be silicon oxide layers; the dielectric layer 93 may be a silicon nitride layer; the passivation layer 94 may be a silicon nitride layer; the materials of the first flat layer 95 and the second flat layer 96 may be transparent polyimide (CPI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and the like.
  • the material of the first gate layer and the second gate layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a stack, etc.
  • the material of the first source and drain layer and the second source and drain layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a stack, etc., or a titanium/aluminum/titanium stack.
  • the anode layer may include an indium tin oxide layer and a silver layer. The square resistance of any conductive layer in the first gate layer and the second gate layer may be greater than the square resistance of the first source and drain layer and the second source and drain layer.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure.
  • the drawings described in the present disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structural names, and they do not have a specific order and quantity.
  • the positive projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as the positive projection of the structure on the substrate substrate extending straight or bending along the direction.
  • a transistor refers to an element including at least three terminals: a gate, a drain and a source.
  • the transistor has a channel region between the drain (drain electrode terminal, a drain region or a drain electrode) and the source (source electrode terminal, a source region or a source electrode), and the current can flow through the drain, the channel region and the source.
  • the channel region refers to the area where the current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate electrode may also be referred to as a control electrode.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

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Abstract

一种显示面板和显示装置。显示面板包括；衬底基板(90)、触控功能层、多个第一绑定引脚(Pin1)、多条第一触控引线(L1)、多条第二触控引线(L2 )，衬底基板(90)包括显示区(AA)和第一边框区(BB)，第一边框区(BB)位于显示区(AA)在第一方向(X)上的一侧，第一边框区(BB)包括绑定区(B1)；触控功能层位于衬底基板(90)的一侧，触控功能层包括多条第一触控电极(Tx)，第一触控电极(Tx)在衬底基板(90)上的正投影位于显示区(AA )；多个第一绑定引脚(Pin1)在衬底基板(90)上的正投影位于绑定区(B1)，第一绑定引脚(Pin1)与第一触控电极(Tx)对应设置；第一触控引线(L1)连接于相对应的第一绑定引脚(Pin1)和第一触控电极(Tx)之间，且第一触控引线(L1)连接于第一触控电极(Tx)的第一端；第二触控引线(L2)连接于相连接的第一触控电极(Tx)和第一触控引线(L1)之间，且第二触控引线(L2)连接第一触控电极(Tx)的第二端，其中，第一绑定引脚(Pin1)通过第一触控引线(L1)和第二触控引线(L2)连接第一触控电极(Tx)。该显示面板可以减小显示面板的下边框。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
相关技术中，触控显示一体化(flexible multi-layer on cell，简称FMLOC)结构的显示面板需要在显示面板的下边框区设置用于连接触控功能层的引脚，较多的引脚会限制显示面板下边框的宽度。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括：衬底基板、触控功能层、多个第一绑定引脚、多条第一触控引线、多条第二触控引线。所述衬底基板包括显示区和第一边框区，所述第一边框区位于所述显示区在第一方向上的一侧，所述第一边框区包括绑定区；触控功能层位于所述衬底基板的一侧，所述触控功能层包括多条第一触控电极，所述第一触控电极在所述衬底基板上的正投影位于所述显示区；多个第一绑定引脚在所述衬底基板上的正投影位于所述绑定区，所述第一绑定引脚与所述第一触控电极对应设置；所述第一触控引线连接于相对应的所述第一绑定引脚和所述第一触控电极之间，且所述第一触控引线连接于所述第一触控电极的第一端；所述第二触控引线连接于相连接的所述第一触控电极和所述第一触控引线之间，且所述第二触控引线连接所述第一触控电极的第二端，其中，所述第一绑定引脚通过所述第一触控引线和所述第二触控引线连接所述第一触控电极。
本公开一种示例性实施例中，所述第一触控引线包括第一延伸部，所述第二触控引线包括第二延伸部，所述第一延伸部在所述衬底基板上的正 投影和所述第二延伸部在所述衬底基板上的正投影位于所述第一边框区；所述显示面板还包括：多条第一桥接线，所述第一桥接线在所述衬底基板上的正投影位于所述第一边框区，且所述第一桥接线连接于同一所述第一触控电极连接的所述第一延伸部和所述第二延伸部之间。
本公开一种示例性实施例中，多条所述第一延伸部在所述衬底基板上的正投影沿所述第一方向延伸且沿第二方向间隔分布，所述第二方向和所述第一方向相交；多条所述第二延伸部在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第二方向间隔分布，所述第一延伸部和所述第二延伸部位于同一导电层；多条所述第一桥接线在所述衬底基板上的正投影沿所述第二方向延伸且沿所述第一方向间隔分布，所述第一桥接线和所述第一延伸部位于不同导电层，所述第一桥接线分别通过过孔连接所述第一延伸部、第二延伸部。
本公开一种示例性实施例中，所述第一边框区还包括弯折区和第一走线区，所述弯折区连接于所述绑定区和所述显示区之间，所述第一走线区连接于所述弯折区和所述绑定区之间；所述第一桥接线在所述衬底基板上的正投影、第一延伸部在所述衬底基板上的正投影、所述第二延伸在所述衬底基板上的正投影均位于所述第一走线区。
本公开一种示例性实施例中，所述第一边框区还包括弯折区和第二走线区，所述弯折区连接于所述绑定区和所述显示区之间，所述第二走线区连接于所述弯折区和所述显示区之间；所述第一桥接线在所述衬底基板上的正投影位于所述第二走线区。
本公开一种示例性实施例中，所述第二走线区在第二方向上的尺寸大于所述弯折区在所述第二方向上的尺寸，所述第二方向和所述第一方向相交。
本公开一种示例性实施例中，所述触控功能层还包括第二触控电极，所述第一触控电极包括多个第一子电极，所述第二触控电极包括多个第二子电极；所述触控功能层包括：第一电极层、第二电极层，第一电极层位于所述衬底基板的一侧，所述第一电极层包括所述第一桥接线和连接桥，所述连接桥用于连接相邻的所述第一子电极，或所述连接桥用于连接相邻的所述第二子电极；第二电极层位于所述第一电极层背离所述衬底基板的 一侧，所述第二电极层包括所述第一延伸部、所述第二延伸部、所述第一子电极、所述第二子电极。
本公开一种示例性实施例中，所述第一边框区还包括弯折区，所述弯折区连接于所述绑定区和所述显示区之间；所述第一桥接线在所述衬底基板上的正投影、第一延伸部在所述衬底基板上的正投影、所述第二延伸在所述衬底基板上的正投影均位于所述弯折区。
本公开一种示例性实施例中，所述弯折区包括在所述第一方向上分布的减薄区和正常区，所述显示面板位于所述减薄区的厚度小于所述显示面板位于所述正常区的厚度；所述第一桥接线在所述衬底基板上的正投影位于所述正常区。
本公开一种示例性实施例中，所述显示面板还包括：像素电路层，所述像素电路层位于所述衬底基板和所述触控功能层之间，所述像素电路层包括：第一源漏层、第二源漏层，第一源漏层位于所述衬底基板和所述触控功能层之间，所述第一源漏层包括所述第一桥接线；第二源漏层位于所述第一源漏层和所述触控功能层之间，所述第二源漏层包括所述第一延伸部和所述第二延伸部。
本公开一种示例性实施例中，所述第一绑定引脚在所述衬底基板上的正投影在第二方向上的排列次序和与其连接的所述第一延伸部在所述衬底基板上的正投影在所述第二方向上的排列次序相同，所述第二方向和所述第一方向相交；所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第二延伸部在所述衬底基板上的正投影在所述第二方向上的排列次序相反。
本公开一种示例性实施例中，所述第一触控引线包括：第一引出线、第一连接线、第一换序线，第一引出线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一引出线连接所述第一绑定引脚；第一连接线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一连接线连接所述第一触控电极的第一端，第一换序线在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交，所述第一换序线连接于所述第一引出线和所述第一连接线之间。所述第二触控引线包括：第二引出线、第二连接线、第二换序线，第二引出线在所述衬底基板上的正投影沿所述 第一方向延伸，所述第二引出线连接于所述第一引出线，且相连接的所述第一引出线和所述第二引出线在所述衬底基板上的正投影相邻设置；第二连接线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二连接线连接所述第一触控电极的第二端。第二换序线在所述衬底基板上的正投影沿所述第二方向延伸，所述第二换序线连接于所述第二引出线和所述第二连接线之间。
本公开一种示例性实施例中，所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第一引出线在所述衬底基板上的正投影在所述第二方向上的排列次序相同；所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第二引出线在所述衬底基板上的正投影在所述第二方向上的排列次序相同；所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第一连接线在所述衬底基板上的正投影在所述第二方向上的排列次序相同；所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第二连接线在所述衬底基板上的正投影在所述第二方向上的排列次序相反。
本公开一种示例性实施例中，所述第一引出线包括第三延伸部，所述第三延伸部在所述衬底基板上的正投影沿所述第一方向延伸；所述第二引出线包括第四延伸部，所述第四延伸部在所述衬底基板上的正投影沿所述第一方向延伸；所述第一连接线包括第五延伸部，所述第五延伸部在所述衬底基板上的正投影沿所述第一方向延伸；所述第二连接线包括第六延伸部，所述第六延伸部在所述衬底基板上的正投影沿所述第一方向延伸；所述第三延伸部、第四延伸部、第五延伸部、第六延伸部位于同一导电层，所述第一换序线和所述第二换序线位于同一导电层，且所述第一换序线和所述第三延伸部位于不同导电层，所述第一换序线分别通过过孔连接所述第三延伸部和所述第五延伸部，所述第二换序线分别通过过孔连接所述第四延伸部和所述第六延伸部。
本公开一种示例性实施例中，所述第一边框区还包括弯折区，所述弯折区连接于所述绑定区和所述显示区之间；所述第三延伸部、第四延伸部、第五延伸部、第六延伸部、第一换序线、第二换序线在衬底基板上的正投 影位于所述弯折区。
本公开一种示例性实施例中，所述显示面板还包括：像素电路层，所述像素电路层位于所述衬底基板和所述触控功能层之间，所述像素电路层包括：第一源漏层、第二源漏层，第一源漏层位于所述衬底基板和所述触控功能层之间，所述第一源漏层包括所述第一换序线、第二换序线；第二源漏层位于所述第一源漏层和所述触控功能层之间，所述第二源漏层包括所述第三延伸部、第四延伸部、第五延伸部、第六延伸部。
本公开一种示例性实施例中，所述弯折区包括在所述第一方向上分布的减薄区和正常区，所述显示面板位于所述减薄区的厚度小于所述显示面板位于所述正常区的厚度；所述第一换序线、第二换序线在所述衬底基板上的正投影位于所述正常区。
本公开一种示例性实施例中，所述触控功能层还包括：第二触控电极，所述第一触控电极包括多个沿同一方向分布的第一子电极，所述第二触控电极包括多个沿同一方向分布的第二子电极，所述第一子电极的分布方向和所述第二子电极的分布方向相交；所述第一子电极和所述第二子电极位于同一导电层，且所述第一触控电极在所述衬底基板上的正投影在其延伸方向上的尺寸大于所述第二触控电极在所述衬底基板上的正投影在其延伸方向上的尺寸。
本公开一种示例性实施例中，所述显示面板还包括：第一保护线，所述第一保护线用于提供触控信号，所述第一保护线包括：第三引出线、第三连接线、第三换序线，第三引出线在所述衬底基板上的正投影沿所述第一方向延伸，所述第三引出线连接第二绑定引脚，且所有所述第一引出线在所述衬底基板上的正投影、所有所述第二引出线在所述衬底基板上的正投影均位于所述第三引出线在所述衬底基板上的正投影的同一侧；第三连接线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第三连接线在所述衬底基板上的正投影位于相邻所述第一连接线和所述第二连接线在所述衬底基板上的正投影之间；第三换序线在所述衬底基板上的正投影沿所述第二方向延伸，所述第三换序线连接于所述第三引出线和所述第三连接之间。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示 面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种显示面板的结构示意图；
图2为本公开显示面板一种示例性实施例的结构示意图；
图3为图2所述显示面板沿虚线AA的剖视图；
图4为图2中区域DD的局部放大图；
图5为本公开显示面板一种示例性实施例中第一边框区的结构示意图；
图6为本公开显示面板另一种示例性实施例中第一边框区的结构示意图；
图7为本公开显示面板另一种示例性实施例中第一边框区的结构示意图；
图8为本公开显示面板另一种示例性实施例中第一边框区的结构示意图；
图9为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图；
图10为图9像素驱动电路一种驱动方法中各节点的时序图；
图11为本公开显示面板一种示例性实施例中像素电路层的结构版图；
图12为图11中有源层的结构版图；
图13为图11中第一栅极层的结构版图；
图14为图11中第二栅极层的结构版图；
图15为图11中第一源漏层的结构版图；
图16为图11中第二源漏层的结构版图；
图17为图11中阳极层的结构版图；
图18为图11中有源层、第一栅极层的结构版图；
图19为图11中有源层、第一栅极层、第二栅极层的结构版图；
图20为图11中有源层、第一栅极层、第二栅极层、第一源漏层的结构版图；
图21为图11中有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层的结构版图；
图22为图11中沿虚线EE的部分剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中一种显示面板的结构示意图。该显示面板可以包括显示区AA和第一边框区Pad。该显示面板还可以包括触控功能层，触控功能层可以包括：第一触控电极Tx和第二触控电极Rx。其中，第一触控电极Tx可以包括多个第一子电极Tx1和第一连接桥Ltx，第一子电极Tx1可以沿第一方向X间隔分布，第一连接桥Ltx可以连接于在第一方向X上相邻的第一子电极Tx1之间。第二触控电极Rx可以包括多个第二子电极Rx2和第二连接桥Lrx，第二子电极Rx2可以沿第二方向Y间隔分布，第二连接桥Lrx可以连接于在第二方向Y上相邻的第二子电极Rx2之间。第一触控电极Tx和第二触控电极Rx可以形成互容结构，从可以通过电容 变化判断触控位置。
如图1所示，相关技术中，显示面板还可以包括第一触控引线L1、第二触控引线L2、第三触控引线L3。第三触控引线L3连接于第二触控电极Rx和位于第一边框区Pad上的第三绑定引脚Pin3之间。第一触控引线L1连接于位于第一边框区Pad上的第一绑定引脚Pin1和第一触控电极Tx的第一端之间，第二触控引线L2连接于位于第一边框区Pad上的第一绑定引脚Pin1和第一触控电极Tx的第二端之间。该显示面板可以通过第一触控引线L1和第二触控引线L2向同一第一触控电极Tx提供触控信号，该设置可以改善触控延时问题。然而，该显示面板需要设置较多的第一绑定引脚Pin1，从而该设置增加了第一边框区Pad在第二方向Y上的尺寸。
基于此，本示例性实施例提供一种显示面板，如图2所示，为本公开显示面板一种示例性实施例的结构示意图。所述显示面板包括：衬底基板、触控功能层、多个第一绑定引脚Pin1、多条第一触控引线L1、多条第二触控引线L2。所述衬底基板包括显示区AA和第一边框区BB，所述第一边框区BB位于所述显示区AA在第一方向X上的一侧，所述第一边框区BB包括绑定区B1；触控功能层位于所述衬底基板的一侧，所述触控功能层包括多条第一触控电极Tx，所述第一触控电极Tx在所述衬底基板上的正投影位于所述显示区AA；多个第一绑定引脚Pin1在所述衬底基板上的正投影位于所述绑定区B1，所述第一绑定引脚Pin1与所述第一触控电极Tx对应设置；所述第一触控引线L1连接于相对应的所述第一绑定引脚Pin1和所述第一触控电极Tx之间，且所述第一触控引线L1连接于所述第一触控电极Tx的第一端；所述第二触控引线L2连接于相连接的所述第一触控电极Tx和所述第一触控引线L1之间，且所述第二触控引线L2连接所述第一触控电极Tx的第二端。
本示例性实施例提供的显示面板将第二触控引线L2连接于第一触控引线L1，同一第一绑定引脚Pin1可以同时向第一触控引线L1和第二触控引线L2提供触控信号。该显示面板可以在改善触控延时的同时，降低第一绑定引脚的数量。
本示例性实施例中，如图3所示，为图2所述显示面板沿虚线AA的剖视图。该显示面板可以包括依次层叠设置的衬底基板90、像素电路层 01、封装层02、触控功能层、保护层04。其中，像素电路层01可以包括像素驱动电路以及发光单元。如图2、3所示，触控功能层可以包括位于封装层02背离衬底基板90一侧的第一电极层、位于第一电极层背离衬底基板一侧的绝缘层03、位于绝缘层03背离衬底基板90一侧的第二电极层。其中，第一电极层可以包括第一连接桥Ltx，第二电极层可以包括第一子电极Tx1、第二子电极Rx2、第二连接桥Lrx。在第二方向Y上分布的多个第二子电极Rx2可以通过第二连接桥Lrx依次连接以形成第二触控电极Rx；在第一方向X上分布的多个第一子电极Tx1可以通过第一连接桥Ltx依次连接以形成第一触控电极Tx。第一触控电极Tx和第二触控电极Rx可以形成互容结构，从可以通过电容变化判断触控位置。
如图2所示，第一边框区BB还可以包括弯折区B2、第一走线区B3、第二走线区B4，其中，弯折区B2连接于显示区AA和绑定区B1之间，第一走线区B3连接于所述弯折区B2和所述绑定区B1之间，第二走线区B4连接于弯折区B2和显示区AA之间。其中，位于弯折区B2的第一触控引出线L1和第二触控引出线L2可以位于像素电路层中的第二源漏层，位于第一走线区B3、第二走线区B4中的第一触控引出线L1和第二触控引出线L2可以位于触控功能层中的第二电极层，所述第二走线区B4在第二方向Y上的尺寸大于所述弯折区B2在所述第二方向Y上的尺寸。本示例性实施例中，封装层02可以不覆盖弯折区B2、第一走线区B3、绑定区B1。
本示例性实施例中，如图2所示，所述第一触控引线L1可以包括第一延伸部L11，所述第二触控引线L2可以包括第二延伸部L22，所述第一延伸部L11在所述衬底基板上的正投影和所述第二延伸部L22在所述衬底基板上的正投影可以位于所述第一边框区BB；所述显示面板还可以包括：多条第一桥接线Q1，所述第一桥接线Q1在所述衬底基板上的正投影可以位于所述第一边框区BB，且所述第一桥接线Q1连接于同一所述第一触控电极连接的所述第一延伸部L11和所述第二延伸部L22之间。即本示例性实施例提供的显示面板通过位于第一边框区BB的第一桥接线Q1连接第一触控引线L1和第二触控引线L2。应该理解的是，在其他示例性实施例中，第一触控引线L1和第二触控引线L2还可以有其他连接方式，例如，第一触控引线L1和第二触控引线L2可以通过位于显示面板其他边框区的桥接 线相连接。
本示例性实施例中，多条所述第一延伸部L11在所述衬底基板上的正投影可以沿所述第一方向X延伸且沿第二方向Y间隔分布，所述第二方向Y和所述第一方向X相交，例如，第一方向X可以为列方向，第二方向Y可以为行方向。多条所述第二延伸部L22在所述衬底基板上的正投影可以沿所述第一方向X延伸且沿所述第二方向Y间隔分布，所述第一延伸部L11和所述第二延伸部L22可以位于同一导电层；多条所述第一桥接线Q1在所述衬底基板上的正投影沿所述第二方向Y延伸且沿所述第一方向X间隔分布，所述第一桥接线Q1和所述第一延伸部L11可以位于不同导电层，所述第一桥接线Q1可以分别通过过孔连接所述第一延伸部L11、第二延伸部L22。
本示例性实施例中，如图2所示，第一触控电极Tx在所述衬底基板上的正投影在其延伸方向(第一方向X)上的尺寸可以大于所述第二触控电极(Rx)在所述衬底基板上的正投影在其延伸方向(第二方向Y)上的尺寸。其中，第一触控电极Tx可以为驱动电极，第二触控电极Rx可以为感测电极。应该理解的是，在其他示例性实施例中，第一触控电极Tx也可以为感测电极，第二触控电极Rx也可以为驱动电极。此外，在其他示例性实施例中，第一触控电极Tx在衬底基板上的正投影也可以沿第二方向Y延伸，第二触控电极Rx在衬底基板上的正投影也可以沿第一方向X延伸。
本示例性实施例中，如图4所示，为图2中区域DD的局部放大图。其中，第一子电极Tx1可以包括第一实体部STx1和第一虚拟部DTx1，第一虚拟部DTx1和第一实体部STx1不连接，第一虚拟部DTx1可以调节第一子电极Tx1和第二子电极Rx2之间的电容容量。第二子电极Rx2包括第二实体部SRx2和第二虚拟部DRx2，第二虚拟部DRx2和第二实体部SRx2不连接，第二虚拟部DRx2可以调节第一子电极Tx1和第二子电极Rx2之间的电容容量。第一实体部STx1的边沿设置有多个第一凸起部Tx11，第二实体部SRx2的边沿设置有多个第二凸起部Rx22，第一凸起部Tx11和第二凸起部Rx22交错设置，从而第一子电极Tx1和第二子电极Rx2之间可以形成容量较大的侧向电容。
如图5所示，为本公开显示面板一种示例性实施例中第一边框区的结构示意图。其中，位于弯折区B2的第一触控引出线L1和第二触控引出线L2可以位于像素电路层中的第二源漏层，位于第一走线区B3、第二走线区B4中的第一触控引出线L1和第二触控引出线L2可以位于触控功能层中的第二电极层，第一桥接线Q1可以位于触控功能层中的第一电极层。如图5所示，位于弯折区B2第一触控引出线L1可以分别通过过孔H连接位于第一走线区B3、第二走线区B4中的第一触控引出线L1，位于弯折区B2第二触控引出线L2可以分别通过过孔连接位于第一走线区B3、第二走线区B4中的第二触控引出线L2。本示例性实施例中，黑色圆形可以表示过孔的位置。本示例性实施例中，如图5所示，第一桥接线Q1在衬底基板上的正投影、第一延伸部L11在衬底基板上的正投影、第二延伸部L22在衬底基板上的正投影均可以位于第一走线区B3。在一些实施例中，第一延伸部L11在衬底基板上的正投影或第二延伸部L22在衬底基板上的正投影，与第一桥接线Q1在衬底基板上的正投影至少具有部分重叠区域，也即至少部分相交。如图5所示，第一延伸部L11在衬底基板上的正投影与第一桥接线Q1在衬底基板上的正投影至少具有部分重叠区域。
如图5所示，显示面板还可以包括第一保护线Gd1、第二保护线Gd2、第三保护线Gd3、第一接地线GND1、第二接地线GND2。其中，第一保护线Gd1在衬底基板上的正投影位于相邻第一触控引线L1和第二触控引线L2在衬底基板上的正投影之间。相邻第一触控引线L1和第二触控引线L2可以指，之间没有第一触控引线L1或第二触控引线L2的第一触控引线L1和第二触控引线L2。第二保护线Gd2在衬底基板上的正投影可以位于所有第二触控引线L2在衬底基板上的正投影远离第一保护线Gd1在衬底基板上的正投影的一侧；第三保护线Gd3在衬底基板上的正投影可以位于所有第一触控引线L1在衬底基板上的正投影远离第一保护线Gd1在衬底基板上的正投影的一侧；第一接地线GND1在衬底基板上的正投影位于第三保护线Gd3在衬底基板上的正投影远离第一触控引线L1在衬底基板上的正投影的一侧，第二接地线GND2在衬底基板上的正投影位于第二保护线Gd2在衬底基板上的正投影远离第二触控引线L2在衬底基板上的正投影的一侧。位于弯折区B2的第一保护线Gd1、第二保护线Gd2、第三保护线Gd3、 第一接地线GND1、第二接地线GND2可以位于像素电路层中的第二源漏层；位于第一走线区B3、第二走线区B4中的第一保护线Gd1、第二保护线Gd2、第三保护线Gd3、第一接地线GND1、第二接地线GND2可以位于触控功能层中的第二电极层。第一保护线Gd1、第二保护线Gd2、第二接地线GND2可以随第二触控引线L2的延伸方向延伸；第三保护线Gd3、第一接地线GND1可以随第一触控引线L1的延伸方向延伸。第一保护线Gd1、第二保护线Gd2、第三保护线Gd3可以用于接收触控信号，第一保护线Gd1、第二保护线Gd2可以使得与其相邻的第二触控引线L2和其他第二触控引线L2具有相同的电场环境，第三保护线Gd3可以使得与其相邻的第一触控引线L1和其他第一触控引线L1具有相同的电场环境。需要说明的是，第一保护线Gd1、第二保护线Gd2、第三保护线Gd3与第一触控电极Tx、第二触控电极Rx均不连接。第一接地线GND1、第二接地线GND2可以同于提供稳定的电源信号，例如，第一接地线GND1、第二接地线GND2可以接地，第一接地线GND1、第二接地线GND2可以屏蔽其他信号对第一触控引线L1、第二触控引线L2的噪音干扰。
在其他示例性实施例中，第一桥接线还可以位于其他位置。例如，如图6所示，为本公开显示面板另一种示例性实施例中第一边框区的结构示意图。其中，所述第一桥接线Q1、第一延伸部L11和第二延伸部L22在所述衬底基板上的正投影可以位于所述第二走线区B4。第一延伸部L11和第二延伸部L22可以位于第二电极层，相应的，第一桥接线Q1可以位于第一电极层。此外，同样的，位于弯折区B2的第一触控引出线L1和第二触控引出线L2可以位于像素电路层中的第二源漏层，位于第一走线区B3、第二走线区B4中的第一触控引出线L1和第二触控引出线L2可以位于触控功能层中的第二电极层。
再例如，如图7所示，为本公开显示面板另一种示例性实施例中第一边框区的结构示意图。其中，所述第一桥接线Q1、第一延伸部L11和第二延伸部L22在所述衬底基板上的正投影可以位于弯折区B2。第一延伸部L11和第二延伸部L22和位于第二源漏层，相应的，第一桥接线Q1可以位于像素电路层中的第一源漏层。同样的，位于弯折区B2的第一触控引出线L1和第二触控引出线L2可以位于像素电路层中的第二源漏层，位于第 一走线区B3、第二走线区B4中的第一触控引出线L1和第二触控引出线L2可以位于触控功能层中的第二电极层。
本示例性实施例中，如图7所示，所述弯折区B2包括在所述第一方向X上分布的减薄区B22和正常区B21，所述显示面板位于所述减薄区B22的厚度小于所述显示面板位于所述正常区B21的厚度；所述第一桥接线Q1在所述衬底基板上的正投影位于所述正常区B21。本示例性实施例中，显示面板位于减薄区B22的位置可以不设置保护层04和/或像素电路层中的至少部分无机层，该设置可以使得显示面板在减薄区B22位置能够以较大弯折角度弯折。应该理解的是，在其他示例性实施例中，显示面板也可以通过减薄保护层04和/或像素电路层中的至少部分无机层以降低显示面板位于减薄区B22的厚度。
本示例性实施例中，如图5、6、7所示，所述第一绑定引脚Pin1在所述衬底基板上的正投影在第二方向Y上的排列次序和与其连接的所述第一延伸部L11在所述衬底基板上的正投影在所述第二方向Y上的排列次序可以相同；所述第一绑定引脚Pin1在所述衬底基板上的正投影在所述第二方向Y上的排列次序和与其连接的所述第二延伸部L22在所述衬底基板上的正投影在所述第二方向Y上的排列次序相反。
在其他示例性实施例中，第一触控引线L1和第二触控引线L2还可以有其他连接方式。例如，如图8所示，为本公开显示面板另一种示例性实施例中第一边框区的结构示意图。本示例性实施例中，所述第一触控引线L1可以包括：第一引出线L1a、第一连接线L1b、第一换序线L1c，第一引出线L1a在所述衬底基板上的正投影沿所述第一方向X延伸，所述第一引出线L1a连接所述第一绑定引脚Pin1；第一连接线L1b在所述衬底基板上的正投影沿所述第一方向X延伸，所述第一连接线L1b连接所述第一触控电极Tx的第一端，第一换序线L1c在所述衬底基板上的正投影沿第二方向Y延伸，所述第一换序线L1c连接于所述第一引出线L1a和所述第一连接线L1b之间。所述第二触控引线L2可以包括：第二引出线L2a、第二连接线L2b、第二换序线L2c，第二引出线L2a在所述衬底基板上的正投影沿所述第一方向X延伸，所述第二引出线L2a连接于所述第一引出线L1a，且相连接的所述第一引出线L1a和所述第二引出线L2a在所述衬底基板上 的正投影相邻设置，即相连接的所述第一引出线L1a和所述第二引出线L2a之间没有设置第一引出线L1a或第二引出线L2a；第二连接线L2b在所述衬底基板上的正投影沿所述第一方向X延伸，所述第二连接线L2b连接所述第一触控电极的第二端。第二换序线L2c在所述衬底基板上的正投影沿所述第二方向Y延伸，所述第二换序线L2c连接于所述第二引出线L2a和所述第二连接线L2b之间。本示例性实施例中，第一触控引线L1通过第一引出线L1a连接第二触控引线L2的第二引出线L2a，从而实现了第一触控引线L1和第二触控引线L2的连接，同时本示例性实施例通过第一换序线L1c对第一引出线L1a进行换序，通过第二换序线L2c对第二引出线L2a进行换序，从而使得第一连接线L1b和第二连接线L2b的引出次序符合连接第一触控电极的需求。
本示例性实施例中，所述第一绑定引脚Pin1在所述衬底基板上的正投影在所述第二方向Y上的排列次序和与其连接的所述第一引出线L1a在所述衬底基板上的正投影在所述第二方向Y上的排列次序相同；所述第一绑定引脚Pin1在所述衬底基板上的正投影在所述第二方向Y上的排列次序和与其连接的所述第二引出线L2a在所述衬底基板上的正投影在所述第二方向Y上的排列次序相同；所述第一绑定引脚Pin1在所述衬底基板上的正投影在所述第二方向Y上的排列次序和与其连接的所述第一连接线L1b在所述衬底基板上的正投影在所述第二方向Y上的排列次序相同；所述第一绑定引脚Pin1在所述衬底基板上的正投影在所述第二方向Y上的排列次序和与其连接的所述第二连接线L2b在所述衬底基板上的正投影在所述第二方向Y上的排列次序相反。
本示例性实施例中，如图8所示，所述第一引出线L1a可以包括第三延伸部L13，所述第三延伸部L13在所述衬底基板上的正投影沿所述第一方向X延伸；所述第二引出线L2a包括第四延伸部L24，所述第四延伸部L24在所述衬底基板上的正投影沿所述第一方向X延伸；所述第一连接线L1b包括第五延伸部L15，所述第五延伸部L15在所述衬底基板上的正投影沿所述第一方向X延伸；所述第二连接线L2b包括第六延伸部L26，所述第六延伸部L26在所述衬底基板上的正投影沿所述第一方向X延伸；所述第三延伸部L13、第四延伸部L24、第五延伸部L15、第六延伸部L26 位于同一导电层，所述第一换序线Lac和所述第二换序线L2c位于同一导电层，且所述第一换序线L1c和所述第三延伸部L13位于不同导电层，所述第一换序线L1c分别通过过孔连接所述第三延伸部L13和所述第五延伸部L15，所述第二换序线L2c分别通过过孔连接所述第四延伸部L24和所述第六延伸部L26。
本示例性实施例中，所述第三延伸部L13、第四延伸部L24、第五延伸部L15、第六延伸部L26、第一换序线L1c、第二换序线L2c在衬底基板上的正投影均可以位于所述弯折区B2。
本示例性实施例中，如图8所示，第一换序线L1c、第二换序线L2c可以位于像素电路层中的第一源漏层，第三延伸部L13、第四延伸部L24、第五延伸部L15、第六延伸部L26可以位于像素电路层中的第二源漏层。
本示例性实施例中，如图8所示，所述弯折区B2同样可以包括在所述第一方向X上分布的减薄区B22和正常区B21，所述显示面板位于所述减薄区B22的厚度小于所述显示面板位于所述正常区B21的厚度；所述第一换序线L1c、第二换序线L2c在所述衬底基板上的正投影可以位于所述正常区B21。
本示例性实施例中，如图8所示，该显示面板同样可以包括：第一保护线Gd1，所述第一保护线Gd1可以用于提供触控信号，所述第一保护线Gd1可以包括：第三引出线Gd1a、第三连接线Gd1b、第三换序线Gd1c，第三引出线Gd1a在所述衬底基板上的正投影沿所述第一方向X延伸，所述第三引出线Gd1a可以连接第二绑定引脚Pin2，第二绑定引脚Pin2在衬底基板上的正投影位于绑定区B1。且所有所述第一引出线L1a在所述衬底基板上的正投影、所有所述第二引出线L2a在所述衬底基板上的正投影均位于所述第三引出线Gd1a在所述衬底基板上的正投影的同一侧；第三连接线Gd1b在所述衬底基板上的正投影沿所述第一方向X延伸，所述第三连接线Gd1b在所述衬底基板上的正投影位于相邻所述第一连接线L1b和所述第二连接线L2b在所述衬底基板上的正投影之间；第三换序线Gd1c在所述衬底基板上的正投影沿所述第二方向Y延伸，所述第三换序线Gd1c连接于所述第三引出线Gd1a和所述第三连接线Gd1b之间。相邻所述第一连接线L1b和所述第二连接线L2b可以指，之间没有设置第一连接线L1b 或所述第二连接线L2b的第一连接线L1b和所述第二连接线L2b。第三引出线Gd1a在衬底基板上的正投影可以位于正常区B21。
需要说明的是，图1-2、5-8示出了第一边框区BB、显示区AA、绑定区B1、弯折区B2、第一走线区B3、第二走线区B4、正常区B21、减薄区B22的相对位置关系，各个区域的尺寸大小还可以为其他值，且各个区域中的走线还可以有其他走线方式。
如图9所示，为本公开显示面板一种示例性实施例中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接第一初始信号端Vinit1，第二极连接节点N，栅极连接第一复位信号端Re1；第二晶体管T2第一极连接节点N，第二极连接驱动晶体管T3的第二极；栅极连接栅极驱动信号端Gate；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第七晶体管T7的第一极连接第二初始信号端Vinit2，第二极连接第六晶体管T6的第二极，栅极连接第二复位信号端Re2。电容C连接于驱动晶体管T3的栅极和第一电源端VDD之间。该像素驱动电路可以连接一发光单元OLED，像素驱动电路可以用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，晶体管T1-T7可以均为P型晶体管。
如图10所示，为图9像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re1输出低电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入第一初始信号。在补偿阶段t2：第二复位信号端Re2、栅极驱 动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2、第七晶体管T7导通，同时数据信号端Da输出驱动信号以向节点N写入补偿电压Vdata+Vth，其中，Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压，第二初始信号端Vinit2向第六晶体管T6的第二极输入第二初始信号。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下驱动发光单元OLED发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth)2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth)2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例中，像素电路层可以包括依次层叠设置于衬底基板的有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层、阳极层。上述层级之间设置有绝缘层。如图11-21所示，图11为本公开显示面板一种示例性实施例中像素电路层的结构版图，图12为图11中有源层的结构版图；图13为图11中第一栅极层的结构版图；图14为图11中第二栅极层的结构版图；图15为图11中第一源漏层的结构版图；图16为图11中第二源漏层的结构版图；图17为图11中阳极层的结构版图；图18为图11中有源层、第一栅极层的结构版图；图19为图11中有源层、第一栅极层、第二栅极层的结构版图；图20为图11中有源层、第一栅极层、第二栅极层、第一源漏层的结构版图；图21为图11中有源层、第一栅极层、第二栅极层、第一源漏层、第二源漏层的结构版图。
如图11、12、18所示，有源层可以包括第三有源部43、第四有源部44、第五有源部45、第六有源部46、第七有源部47、第八有源部48、第九有源部49、第十有源部410、第十一有源部411、第十二有源部412、第十三有源部413、第一子有源部421、第二子有源部422、第三子有源部423、第四子有源部414、第五子有源部415、第六子有源部416。其中，第一子有源部421、第二子有源部422可以用于形成第二晶体管T2的沟道区，第四子有源部414、第五子有源部415可以用于形成第一晶体管T1 的沟道区，第三有源部43可以用于形成驱动晶体管T3的沟道区，第四有源部44可以用于形成第四晶体管T4的沟道区，第五有源部45可以用于形成第五晶体管T5的沟道区，第六有源部46可以用于形成第六晶体管T6的沟道区，第七有源部47可以用于形成第七晶体管T7的沟道区，第三子有源部423连接于第一子有源部421和第二子有源部422之间，第六子有源部416连接于第四子有源部414和第五子有源部415之间，第八有源部48连接于第五子有源部415远离第六子有源部416的一端，第九有源部49连接于第二子有源部422和第四子有源部414之间，第十有源部410连接于第四有源部44远离第三有源部43的一端，第十一有源部411连接于第七有源部47和第六有源部46之间，第十二有源部412连接于第五有源部45远离第三有源部43的一端，第十三有源部413连接于第七有源部47远离第六有源部46的一端。有源层可以由多晶硅材料形成，相应的，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图11、13、18所示，第一栅极层可以包括：第一复位信号线Re1、第二复位信号线Re2、栅极驱动信号线Gate、使能信号线EM、第一导电部11。其中，第一复位信号线Re1可以用于向图9中第一复位信号端提供复位信号，第二复位信号线Re2可以用于向图9中第二复位信号端提供复位信号，栅极驱动信号线Gate可以用于向图9中栅极驱动信号端提供驱动信号，使能信号线EM可以用于向图9中使能信号端提供使能信号。第一复位信号线Re1、第二复位信号线Re2、栅极驱动信号线Gate、使能信号线EM在衬底基板的正投影均可以沿第二方向Y延伸。第一复位信号线Re1的部分结构可以用于形成第一晶体管T1的栅极，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极，栅极驱动信号线Gate的部分结构可以用于形成第二晶体管的栅极和第四晶体管的栅极，使能信号线EM的部分结构可以用于形成第六晶体管T6和第五晶体管T5的栅极。第一导电部11在衬底基板正投影可以覆盖第三有源部43，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的一电极。其中，本行像素驱动电路中的第二复位信号线Re2可以复用为下一行像素驱动电路中第一复位 信号线Re1。
该显示面板可以通过图案化的第一栅极层为掩膜版对有源层进行导体化处理，即被第一栅极层遮挡的部分形成晶体管的沟道区，未被第一栅极层遮挡的部分形成导体结构。
如图11、14、19所示，第二栅极层可以包括：第一初始信号线Vinit1、第二初始信号线Vinit2、第二导电部22、第三导电部23。第一初始信号线Vinit1用于向图9中的第一初始信号端提供第一初始信号，第二初始信号线Vinit1用于向图9中的第二初始信号端提供第二初始信号。第二初始信号线Vinit2在衬底基板上的正投影可以与第六子有源部416在衬底基板上的正投影交叠，第二初始信号线Vinit2可以对第六子有源部416起到稳压作用，从而降低第六子有源部416向第一晶体管源漏极的漏电流。第二导电部22在衬底基板上的正投影和第一导电部11在衬底基板上的正投影至少部分交叠，第二导电部22用于形成电容的第二电极。第三导电部23可以连接一稳定电源，第三导电部23在衬底基板上的正投影可以与第三子有源部423在衬底基板上的正投影交叠，第三导电部23可以对第三子有源部423起到稳压作用，从而降低第三子有源部423向第二晶体管源漏极的漏电流。
如图11、15、20所示，第一源漏层可以包括：第一初始连接线3Vinit1、第二初始连接线3Vinit2、第一桥接部31、第二桥接部32、第三桥接部33、第四桥接部34、电源线VDD。第一初始连接线3Vinit1、第二初始连接线3Vinit2、电源线VDD在衬底基板上的正投影可以沿第一方向X延伸。其中，第一桥接部31可以分别通过过孔连接第九有源部49和第一导电部11，以连接驱动晶体管的栅极和第一晶体管的第二极、第二晶体管的第一极，第二导电部22上形成有开口221，连接于第一导电部11和第一桥接部31之间的过孔在衬底基板上的正投影可以位于开口221在衬底基板上的正投影以内，以使该过孔和第二导电部22绝缘。第二桥接部32可以通过过孔连接第十一有源部411，以连接第六晶体管的第二极。第三桥接部33可以通过过孔连接第十有源部410，以连接第四晶体管的第一极。第四桥接部34可以分别通过过孔连接第一初始信号线Vinit1和第八有源部48，以连接第一晶体管的第一极和第一初始信号端。电源线VDD可以向图9中 的第一电源端提供电源信号，电源线VDD可以分别通过过孔连接第十二有源部412、第二导电部22、第三导电部23。在第二方向Y上分布的第二导电部22可以相互连接，相互连接的第二导电部22和电源线VDD可以形成网格结构，以降低电源线的电阻。本示例性实施例中，每两列像素驱动电路对应设置一条第一初始连接线3Vinit1和一条第二初始连接线3Vinit2。第一初始连接线3Vinit1可以分别通过过孔连接第八有源部48、第一初始信号线Vinit1，以连接第一晶体管的第一极和第一初始信号端，第一初始连接线3Vinit1可以将第一初始信号线Vinit1形成网格结构，以降低第一初始信号线Vinit1的电阻。第二初始连接线3Vinit2可以分别通过过孔连接第二初始信号线Vinit2、第十三有源部413，以连接第七晶体管的第一极和第二初始信号端，同时，第二初始连接线3Vinit2可以将第二初始信号线Vinit2形成网格结构，从而降低第二初始信号线Vinit2的电阻。
如图11、16、21所示，第二源漏层可以包括：数据线Da和第五桥接部55，数据线Da在衬底基板上的正投影可以沿第一方向X延伸，数据线Da可以向图9中的数据信号端提供驱动信号，数据线Da可以通过过孔连接第三桥接部33，以连接第四晶体管的第一极和数据信号端。第五桥接部55可以通过过孔连接第二桥接部32。
如图11、17所示，阳极层可以包括多个阳极部，多个阳极部可以包括第一阳极部R、第二阳极部G、第三阳极部B，第一阳极部R用于形成红色发光单元的阳极，第二阳极部G用于形成绿色发光单元的阳极，第三阳极部B用于形成蓝色发光单元的阳极。阳极部可以通过过孔连接第五桥接部55。
需要说明的是，如图11、20、21所示，画于阳极层背离衬底基板一侧的黑色方块表示阳极层连接面向衬底基板一侧的其他层级的过孔；画于第二源漏层背离衬底基板一侧的黑色方块表示第二源漏层连接面向衬底基板一侧的其他层级的过孔；画于第一源漏层背离衬底基板一侧的黑色方块表示第一源漏层连接面向衬底基板一侧的其他层级的过孔。该黑色方块表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。此外，该像素电路层还可以包括位于阳极层背离衬底基板一侧的像素定义层、发光单元层。
如图22所示，为图11中沿虚线EE的部分剖视图。该显示面板还可以包括：第一绝缘层91、第二绝缘层92、介电层93、钝化层94、第一平坦层95、第二平坦层96。其中、衬底基板90、有源层、第一绝缘层91、第一栅极层、第二绝缘层92、第二栅极层、介电层93、第一源漏层、钝化层94、第一平坦层95、第二源漏层、第二平坦层96、阳极层可以依次层叠设置。其中，第一绝缘层91、第二绝缘层92可以为氧化硅层；介电层93可以为氮化硅层；钝化层94可以为氮化硅层；第一平坦层95、第二平坦层96的材料可以为透明聚酰亚胺(CPI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)等材料。第一栅极层、第二栅极层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第一源漏层、第二源漏层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。阳极层可以包括氧化铟锡层、银层。第一栅极层、第二栅极层中任一导电层的方块电阻可以大于第一源漏层、第二源漏层的方块电阻。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序和数量的含义。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流能够流过漏极、沟道区以及源极。在本示例性实施例中，沟道区是指电流主要流过的区域。在本示例性实施例中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源极”及“漏极”的功能有时互相调换。因此，在本示例性实施例中，“源极”和“漏极”可 以互相调换。另外，栅极还可以称为控制极。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    衬底基板，所述衬底基板包括显示区和第一边框区，所述第一边框区位于所述显示区在第一方向上的一侧，所述第一边框区包括绑定区；
    触控功能层，位于所述衬底基板的一侧，所述触控功能层包括多条第一触控电极，所述第一触控电极在所述衬底基板上的正投影位于所述显示区；
    多个第一绑定引脚，在所述衬底基板上的正投影位于所述绑定区，所述第一绑定引脚与所述第一触控电极对应设置；
    多条第一触控引线，所述第一触控引线连接于相对应的所述第一绑定引脚和所述第一触控电极之间，且所述第一触控引线连接于所述第一触控电极的第一端；
    多条第二触控引线，所述第二触控引线连接于相连接的所述第一触控电极和所述第一触控引线之间，且所述第二触控引线连接所述第一触控电极的第二端，其中，所述第一绑定引脚通过所述第一触控引线和所述第二触控引线连接所述第一触控电极。
  2. 根据权利要求1所述的显示面板，其中，所述第一触控引线包括第一延伸部，所述第二触控引线包括第二延伸部，所述第一延伸部在所述衬底基板上的正投影和所述第二延伸部在所述衬底基板上的正投影位于所述第一边框区；
    所述显示面板还包括：
    多条第一桥接线，所述第一桥接线在所述衬底基板上的正投影位于所述第一边框区，且所述第一桥接线连接于同一所述第一触控电极连接的所述第一延伸部和所述第二延伸部之间。
  3. 根据权利要求2所述的显示面板，其中，多条所述第一延伸部在所述衬底基板上的正投影沿所述第一方向延伸且沿第二方向间隔分布，所述第二方向和所述第一方向相交；
    多条所述第二延伸部在所述衬底基板上的正投影沿所述第一方向延伸且沿所述第二方向间隔分布，所述第一延伸部和所述第二延伸部位于同一导电层；
    多条所述第一桥接线在所述衬底基板上的正投影沿所述第二方向延伸且沿所述第一方向间隔分布，所述第一桥接线和所述第一延伸部位于不同导电层，所述第一桥接线分别通过过孔连接所述第一延伸部、第二延伸部。
  4. 根据权利要求2所述的显示面板，其中，所述第一边框区还包括弯折区和第一走线区，所述弯折区连接于所述绑定区和所述显示区之间，所述第一走线区连接于所述弯折区和所述绑定区之间；
    所述第一桥接线在所述衬底基板上的正投影、第一延伸部在所述衬底基板上的正投影、所述第二延伸在所述衬底基板上的正投影均位于所述第一走线区。
  5. 根据权利要求2所述的显示面板，其中，所述第一边框区还包括弯折区和第二走线区，所述弯折区连接于所述绑定区和所述显示区之间，所述第二走线区连接于所述弯折区和所述显示区之间；
    所述第一桥接线在所述衬底基板上的正投影、第一延伸部在所述衬底基板上的正投影、所述第二延伸在所述衬底基板上的正投影均位于所述第二走线区。
  6. 根据权利要求5所述的显示面板，其中，所述第二走线区在第二方向上的尺寸大于所述弯折区在所述第二方向上的尺寸，所述第二方向和所述第一方向相交。
  7. 根据权利要求4-6任一项所述的显示面板，其中，所述触控功能层还包括第二触控电极，所述第一触控电极包括多个第一子电极，所述第二触控电极包括多个第二子电极；
    所述触控功能层包括：
    第一电极层，位于所述衬底基板的一侧，所述第一电极层包括所述第一桥接线和连接桥，所述连接桥用于连接相邻的所述第一子电极，或所述连接桥用于连接相邻的所述第二子电极；
    第二电极层，位于所述第一电极层背离所述衬底基板的一侧，所述第二电极层包括所述第一延伸部、所述第二延伸部、所述第一子电极、所述第二子电极。
  8. 根据权利要求2所述的显示面板，其中，所述第一边框区还包括 弯折区，所述弯折区连接于所述绑定区和所述显示区之间；
    所述第一桥接线在所述衬底基板上的正投影、第一延伸部在所述衬底基板上的正投影、所述第二延伸在所述衬底基板上的正投影均位于所述弯折区。
  9. 根据权利要求8所述的显示面板，其中，所述弯折区包括在所述第一方向上分布的减薄区和正常区，所述显示面板位于所述减薄区的厚度小于所述显示面板位于所述正常区的厚度；
    所述第一桥接线在所述衬底基板上的正投影位于所述正常区。
  10. 根据权利要求8所述的显示面板，其中，所述显示面板还包括：像素电路层，所述像素电路层位于所述衬底基板和所述触控功能层之间，所述像素电路层包括：
    第一源漏层，位于所述衬底基板和所述触控功能层之间，所述第一源漏层包括所述第一桥接线；
    第二源漏层，位于所述第一源漏层和所述触控功能层之间，所述第二源漏层包括所述第一延伸部和所述第二延伸部。
  11. 根据权利要求2所述的显示面板，其中，所述第一绑定引脚在所述衬底基板上的正投影在第二方向上的排列次序和与其连接的所述第一延伸部在所述衬底基板上的正投影在所述第二方向上的排列次序相同，所述第二方向和所述第一方向相交；
    所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第二延伸部在所述衬底基板上的正投影在所述第二方向上的排列次序相反。
  12. 根据权利要求1所述的显示面板，其中，所述第一触控引线包括：
    第一引出线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第一引出线连接所述第一绑定引脚；
    第一连接线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第一连接线连接所述第一触控电极的第一端；
    所述第二触控引线包括：
    第二引出线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第二引出线连接于所述第一引出线，且相连接的所述第一引出线和所述第 二引出线在所述衬底基板上的正投影相邻设置；
    第二连接线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第二连接线连接所述第一触控电极的第二端；
    第一换序线，在所述衬底基板上的正投影沿第二方向延伸，所述第二方向和所述第一方向相交，所述第一换序线连接于所述第一引出线和所述第一连接线之间；
    第二换序线，在所述衬底基板上的正投影沿所述第二方向延伸，所述第二换序线连接于所述第二引出线和所述第二连接线之间。
  13. 根据权利要求12所述的显示面板，其中，所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第一引出线在所述衬底基板上的正投影在所述第二方向上的排列次序相同；
    所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第二引出线在所述衬底基板上的正投影在所述第二方向上的排列次序相同；
    所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第一连接线在所述衬底基板上的正投影在所述第二方向上的排列次序相同；
    所述第一绑定引脚在所述衬底基板上的正投影在所述第二方向上的排列次序和与其连接的所述第二连接线在所述衬底基板上的正投影在所述第二方向上的排列次序相反。
  14. 根据权利要求12所述的显示面板，其中，所述第一引出线包括第三延伸部，所述第三延伸部在所述衬底基板上的正投影沿所述第一方向延伸；
    所述第二引出线包括第四延伸部，所述第四延伸部在所述衬底基板上的正投影沿所述第一方向延伸；
    所述第一连接线包括第五延伸部，所述第五延伸部在所述衬底基板上的正投影沿所述第一方向延伸；
    所述第二连接线包括第六延伸部，所述第六延伸部在所述衬底基板上的正投影沿所述第一方向延伸；
    所述第三延伸部、第四延伸部、第五延伸部、第六延伸部位于同一导电层，所述第一换序线和所述第二换序线位于同一导电层，且所述第一换序线和所述第三延伸部位于不同导电层，所述第一换序线分别通过过孔连接所述第三延伸部和所述第五延伸部，所述第二换序线分别通过过孔连接所述第四延伸部和所述第六延伸部。
  15. 根据权利要求14所述的显示面板，其中，所述第一边框区还包括弯折区，所述弯折区连接于所述绑定区和所述显示区之间；
    所述第三延伸部、第四延伸部、第五延伸部、第六延伸部、第一换序线、第二换序线在衬底基板上的正投影位于所述弯折区。
  16. 根据权利要求15所述的显示面板，其中，所述显示面板还包括：像素电路层，所述像素电路层位于所述衬底基板和所述触控功能层之间，所述像素电路层包括：
    第一源漏层，位于所述衬底基板和所述触控功能层之间，所述第一源漏层包括所述第一换序线、第二换序线；
    第二源漏层，位于所述第一源漏层和所述触控功能层之间，所述第二源漏层包括所述第三延伸部、第四延伸部、第五延伸部、第六延伸部。
  17. 根据权利要求15所述的显示面板，其中，所述弯折区包括在所述第一方向上分布的减薄区和正常区，所述显示面板位于所述减薄区的厚度小于所述显示面板位于所述正常区的厚度；
    所述第一换序线、第二换序线在所述衬底基板上的正投影位于所述正常区。
  18. 根据权利要求1所述的显示面板，其中，所述触控功能层还包括：第二触控电极，所述第一触控电极包括多个沿同一方向分布的第一子电极，所述第二触控电极包括多个沿同一方向分布的第二子电极，所述第一子电极的分布方向和所述第二子电极的分布方向相交；
    所述第一子电极和所述第二子电极位于同一导电层，且所述第一触控电极在所述衬底基板上的正投影在其延伸方向上的尺寸大于所述第二触控电极在所述衬底基板上的正投影在其延伸方向上的尺寸。
  19. 根据权利要求12所述的显示面板，其中，所述显示面板还包括：第一保护线，所述第一保护线用于提供触控信号，所述第一保护线包括：
    第三引出线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第三引出线连接第二绑定引脚，且所有所述第一引出线在所述衬底基板上的正投影、所有所述第二引出线在所述衬底基板上的正投影均位于所述第三引出线在所述衬底基板上的正投影的同一侧；
    第三连接线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第三连接线在所述衬底基板上的正投影位于相邻所述第一连接线和所述第二连接线在所述衬底基板上的正投影之间；
    第三换序线，在所述衬底基板上的正投影沿所述第二方向延伸，所述第三换序线连接于所述第三引出线和所述第三连接之间。
  20. 一种显示装置，其中，所述显示装置包括权利要求1-19任一项所述的显示面板。
PCT/CN2022/122280 2022-09-28 2022-09-28 显示面板及显示装置 Ceased WO2024065314A1 (zh)

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