WO2024063315A1 - Mémoire tridimensionnelle ayant une structure à double jonction - Google Patents

Mémoire tridimensionnelle ayant une structure à double jonction Download PDF

Info

Publication number
WO2024063315A1
WO2024063315A1 PCT/KR2023/011128 KR2023011128W WO2024063315A1 WO 2024063315 A1 WO2024063315 A1 WO 2024063315A1 KR 2023011128 W KR2023011128 W KR 2023011128W WO 2024063315 A1 WO2024063315 A1 WO 2024063315A1
Authority
WO
WIPO (PCT)
Prior art keywords
junction
vertical channel
memory
pattern
dimensional memory
Prior art date
Application number
PCT/KR2023/011128
Other languages
English (en)
Korean (ko)
Inventor
송창은
송윤흡
Original Assignee
페디셈 주식회사
한양대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 페디셈 주식회사, 한양대학교 산학협력단 filed Critical 페디셈 주식회사
Publication of WO2024063315A1 publication Critical patent/WO2024063315A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Definitions

  • the following embodiments are technologies related to three-dimensional memory, its operation method, and its manufacturing method.
  • existing 3D NAND flash memory can implement a large storage capacity, but has the problem of not supporting byte-level random access because memory operations are performed on a page-by-page or block-by-block basis.
  • the existing 3D NAND flash memory forms a P-type channel in the channel pattern 110 to transmit data of “0”.
  • a write operation (erase operation)
  • a negative voltage (-V write0) is applied to the selected gate electrode 120 corresponding to the target memory cell
  • a positive pass voltage (-V write0 ) is applied to the remaining gate electrodes 130. Since +V pass ) is applied, an NPN junction is formed in the channel pattern 110. Accordingly, the erase operation on the target memory cell 111 is not performed. Accordingly, the existing 3D NAND flash memory performs an erase operation on a page-by-page or block-by-block basis using the GIDL method, and has a problem in that it cannot support random access on a byte-by-byte basis.
  • Embodiments propose a three-dimensional memory, an operating method, and a manufacturing method that enables high-speed memory operation by supporting random access while implementing a large storage space.
  • a three-dimensional memory includes gate electrodes that extend in the horizontal direction on a substrate and are spaced apart in the vertical direction and are stacked; and vertical channel structures penetrating the gate electrodes and extending in the vertical direction - each of the vertical channel structures includes a vertical channel pattern and a data storage pattern, and different types of structures are located on top of each of the vertical channel structures. It may include the formation of a dual junction, each doped with an impurity.
  • the dual junction may include an N+ doped N+ junction and a P+ doped P+ junction.
  • the N+ junction and the P+ junction may have a structure that is symmetrical to each other so as to have the same contact area with respect to the vertical channel pattern.
  • one of the N+ junction and the P+ junction responds to a voltage applied to a selected gate electrode corresponding to a target memory cell that is the target of the memory operation among the gate electrodes during a memory operation, It may be selectively activated to form a channel in the vertical channel pattern.
  • the N+ junction may form an N-type channel in the vertical channel pattern in response to a positive voltage applied to the selected gate electrode.
  • the N-type channel may be formed to extend in the vertical direction to connect to the N+ junction.
  • the P+ junction may form a P-type channel in the vertical channel pattern in response to a negative voltage applied to the selected gate electrode.
  • the P-type channel is,
  • It may be characterized as extending in the vertical direction to connect to the P+ junction.
  • the dual junction may be connected to a bit line plug through a contact plug disposed at the top.
  • the dual junction may be formed at the bottom of each of the vertical channel structures.
  • a source region may be formed at the bottom of each of the vertical channel structures.
  • the three-dimensional memory may be characterized as having a source free structure in which a source area is omitted at the bottom of each of the vertical channel structures.
  • gate electrodes are formed to extend in the horizontal direction on the substrate and are spaced apart in the vertical direction and are stacked; and vertical channel structures penetrating the gate electrodes and extending in the vertical direction - each of the vertical channel structures includes a vertical channel pattern and a data storage pattern, and different types of structures are located on top of each of the vertical channel structures.
  • the memory operation method of the three-dimensional memory which includes forming dual junctions of a double structure each doped with impurities, is a method of operating a memory on a selected gate electrode corresponding to a target memory cell that is the target of a memory operation among the gate electrodes. applying a voltage; and performing a memory operation by forming a channel in the vertical channel pattern by selectively activating one of the N+ junction and the P+ junction included in the dual junction in response to the voltage applied to the selected gate electrode. can do.
  • the applying step includes applying a positive voltage to the selected gate electrode
  • the performing the memory operation includes, in response to the positive voltage applied to the selected gate electrode
  • the method may include performing a recording operation by forming an N-type channel in the vertical channel pattern through the N+ junction.
  • the applying step includes adjusting the value of the positive voltage applied to the selected gate electrode
  • the step of performing the memory operation includes adjusting the value of the positive voltage applied to the selected gate electrode. It may be characterized by including the step of performing a recording operation of the multi-valued value.
  • the applying step includes applying a negative voltage to the selected gate electrode, and the performing the memory operation includes responding to the negative voltage applied to the selected gate electrode.
  • the applying step may be characterized by including the step of forming a P-type channel in the vertical channel pattern through the P+ junction and performing a recording operation.
  • the applying step includes adjusting the value of the negative voltage applied to the selected gate electrode
  • the step of performing the memory operation includes adjusting the value of the negative voltage applied to the selected gate electrode.
  • a memory operation method of a three-dimensional memory comprising the step of performing a recording operation of a multivalued value according to .
  • the step of performing the memory operation includes selectively activating one of the N+ junction and the P+ junction included in the dual junction formed at the bottom of each of the vertical channel structures, thereby forming the vertical channel pattern. It may further include forming a channel to perform a memory operation.
  • a method of manufacturing a three-dimensional memory including dual junctions of a dual structure each doped with different types of impurities includes stacked structures extending in the horizontal direction on a substrate and spaced apart in the vertical direction. gate electrodes; and preparing a semiconductor structure including vertical channel structures extending in the vertical direction and penetrating the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern.
  • first mask pattern disposing a first mask pattern on the semiconductor structure to cover a portion of a top surface of each of the vertical channel structures; Using the first mask pattern, forming an N+ doped N+ junction in a remaining area of the upper surface of each of the vertical channel structures that is not obscured by the first mask pattern; disposing a second mask pattern on the semiconductor structure to cover the remaining upper surface area of each of the vertical channel structures; and using the second mask pattern to form a P+ doped P+ junction in a portion of the upper surface of each of the vertical channel structures that is not obscured by the second mask pattern.
  • the first mask pattern and the second mask pattern each cover symmetrical areas of the same area so that the N+ junction and the P+ junction in each of the vertical channel structures have a structure that is symmetrical to each other. You can do this.
  • the step of preparing the semiconductor structure may be characterized as preparing the semiconductor structure in which the dual junction is formed at the bottom of each of the vertical channel structures.
  • the step of preparing the semiconductor structure may be characterized in that the step of preparing the semiconductor structure in which a source region is formed at the bottom of each of the vertical channel structures.
  • the step of preparing the semiconductor structure is a step of preparing the semiconductor structure having a source free structure in which a source region is omitted at the bottom of each of the vertical channel structures. can do.
  • Embodiments may propose a three-dimensional memory, an operating method, and a manufacturing method that enables high-speed memory operation by supporting random access while implementing a large storage space.
  • Figure 1 is a diagram to explain problems with existing 3D NAND flash memory.
  • Figure 2 is a simplified circuit diagram showing an array of three-dimensional memory according to one embodiment.
  • Figure 3 is a plan view showing the structure of a three-dimensional memory according to an embodiment.
  • FIGS. 4A to 4C are cross-sectional views showing the structure of a three-dimensional memory according to an embodiment, and correspond to a cross-section taken along line A-A' of FIG. 3.
  • Figure 5 is a flow chart showing a memory operation method of a 3D memory according to an embodiment.
  • FIGS. 6A and 6B are cross-sectional views showing the structure of the 3D memory in order to explain the memory operation method of the 3D memory shown in FIG. 5.
  • FIGS. 7A to 7B are diagrams for explaining an improved memory window of a 3D memory according to an embodiment.
  • FIG. 8 is a diagram illustrating a memory window to explain a read operation of a 3D memory according to an embodiment.
  • 9A to 9B are diagrams showing a memory window to explain an erase operation of a 3D memory according to an embodiment.
  • Figure 10 is a flow chart showing a method of manufacturing a 3D memory according to an embodiment.
  • first and second are used in this specification to describe various areas, directions, and shapes, these areas, directions, and shapes should not be limited by these terms. These terms are merely used to distinguish one area, direction or shape from another area, direction or shape. Accordingly, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.
  • Figure 2 is a simplified circuit diagram showing an array of three-dimensional memory according to one embodiment.
  • the three-dimensional memory array includes a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a common source line (CSL) and bit lines (BL0, It may include a plurality of cell strings (CSTR) arranged between BL1 and BL2).
  • the bit lines BL0, BL1, and BL2 may extend in the second direction D2 and be spaced apart from each other in the first direction D1 and may be arranged two-dimensionally.
  • the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and may form a rectangular coordinate system defined by the X, Y, and Z axes.
  • a plurality of cell strings may be connected in parallel to each of the bit lines (BL0, BL1, and BL2).
  • the cell strings CSTR may be provided between the bit lines BL0, BL1, and BL2 and one common source line CSL and may be commonly connected to the common source line CSL.
  • a plurality of common source lines may be provided, and the plurality of common source lines (CSL) may extend in the first direction (D1) and be spaced apart from each other along the second direction (D2), forming a two-dimensional can be arranged sequentially.
  • the same electrical voltage may be applied to the plurality of common source lines (CSL), but this is not limited or limited, and each of the plurality of common source lines (CSL) is electrically independently controlled, so that different voltages may be applied. there is.
  • the cell strings CSTR may extend in the third direction D3 and be arranged to be spaced apart from each other along the second direction D2 for each bit line.
  • each of the cell strings (CSTR) is connected to a ground selection transistor (GST) connected to the common source line (CSL), the bit lines (BL0, BL1, BL2), and the first and second strings connected in series.
  • GST ground selection transistor
  • Memory cell transistors (MCT) and erase control transistor (ECT) arranged in series between the selection transistors (SST1, SST2), the ground selection transistor (GST) and the first and second string selection transistors (SST1, SST2) ) can be composed of.
  • each memory cell transistor (MCT) may include a data storage element.
  • each cell string CSTR may include first and second string selection transistors SST1 and SST2 connected in series, and the second string selection transistor SST2 may be connected to the bit lines BL0 and BL1. , BL2) can be connected to one of the following.
  • each cell string CSTR may include one string select transistor.
  • the ground selection transistor GST in each cell string CSTR may be composed of a plurality of MOS transistors connected in series, similar to the first and second string selection transistors SST1 and SST2. .
  • One cell string may be composed of a plurality of memory cell transistors (MCT) having different distances from the common source lines (CSL). That is, the memory cell transistors MCT may be connected in series while being arranged along the third direction D3 between the first string selection transistor SST1 and the ground selection transistor GST.
  • the erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL).
  • Each of the cell strings (CSTR) is between the first string select transistor (SST1) and the highest one of the memory cell transistors (MCT) and between the ground select transistor (GST) and the lowest one of the memory cell transistors (MCT). It may further include dummy cell transistors (DMC) each connected to each other.
  • the first string selection transistor SST1 may be controlled by the first string selection lines SSL1-1, SSL1-2, and SSL1-3
  • the second string selection transistor SST2 may be controlled by the first string selection lines SSL1-1, SSL1-2, and SSL1-3. It can be controlled by 2 string selection lines (SSL2-1, SSL2-2, SSL2-3).
  • the memory cell transistors (MCT) may each be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may each be controlled by a dummy word line (DWL).
  • the ground select transistor GST may be controlled by the ground select lines GSL0, GSL1, and GSL2, and the erase control transistor ECT may be controlled by the erase control line ECL.
  • a plurality of erase control transistors (ECT) may be provided.
  • Common source lines (CSL) may be commonly connected to sources of erase control transistors (ECT).
  • the gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and be in an equipotential state. .
  • the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be controlled independently. there is.
  • Ground selection lines extends along the first direction (D1), are spaced apart from each other in the second direction (D2), and may be arranged two-dimensionally.
  • Ground selection lines GSL0, GSL1, GSL2, first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string provided at substantially the same level from the common source lines (CSL)
  • the selection lines SSL2-1, SSL2-2, and SSL2-3) may be electrically separated from each other.
  • the erase control transistors ECT of different cell strings CSTR may be controlled by a common erase control line ECL.
  • Erase control transistors may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array.
  • GDL gate induced drain leakage
  • an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and/or the common source lines (CSL), and the string select transistor (SST) and/or Alternatively, gate-induced leakage current may be generated in the erase control transistors (ECT).
  • the string selection line (SSL) described above may be expressed as an upper selection line (USL), and the ground selection line (GSL) may be expressed as a lower selection line.
  • FIG. 3 is a plan view showing the structure of a three-dimensional memory according to an embodiment
  • FIGS. 4A to 4C are cross-sectional views showing the structure of a three-dimensional memory according to an embodiment, with FIG. 3 taken along line A-A'. Applies to cross section.
  • the substrate may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a monocrystalline silicon substrate.
  • the substrate SUB may be doped with a first conductivity type impurity (eg, a P- impurity).
  • Stacked structures may be disposed on the substrate (SUB).
  • the stacked structures ST may extend in the first direction D1 and be two-dimensionally arranged along the second direction D2. Additionally, the stacked structures ST may be spaced apart from each other in the second direction D2.
  • Each of the stacked structures ST includes gate electrodes EL1, EL2, and EL3 and interlayer insulating films ILD that are alternately stacked in a vertical direction perpendicular to the top surface of the substrate SUB (for example, in the third direction D3).
  • the stacked structures ST may have a substantially flat top surface. That is, the top surface of the stacked structures ST may be parallel to the top surface of the substrate SUB.
  • the vertical direction means the third direction D3 or the reverse direction of the third direction D3.
  • each of the gate electrodes includes an erase control line (ECL), ground selection lines (GSL0, GSL1, GSL2), and a word line sequentially stacked on the substrate (SUB). (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) It can be.
  • Each of the gate electrodes EL1, EL2, and EL3 may extend in the first direction D1 and have substantially the same thickness in the third direction D3.
  • thickness refers to the thickness in the third direction (D3).
  • Each of the gate electrodes EL1, EL2, and EL3 may be formed of a conductive material.
  • each of the gate electrodes EL1, EL2, and EL3 is made of a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).
  • Each of the gate electrodes EL1, EL2, and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal materials described.
  • the gate electrodes EL1, EL2, and EL3 include the first gate electrode EL1 at the bottom, the third gate electrode EL3 at the top, and the first gate electrode EL1 and the third gate electrode EL3. It may include a plurality of second gate electrodes EL2 therebetween.
  • the first gate electrode EL1 and the third gate electrode EL3 are each shown and described in singular form, but this is illustrative and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural.
  • the first gate electrode EL1 may correspond to one of the ground selection lines GSL0, GSL1, and GLS2 shown in FIG. 2.
  • the second gate electrode EL2 may correspond to one of the word lines WL0-WLn and DWL shown in FIG. 2.
  • the third gate electrode EL3 is connected to one of the first string selection lines SSL1-1, SSL1-2, and SSL1-3 or the second string selection lines SSL2-1 and SSL2-2 shown in FIG. 2. , SSL2-3) may apply.
  • an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the length of the gate electrodes EL1, EL2, and EL3 of the stacked structures ST may decrease in the first direction D1 as the distance from the substrate SUB increases.
  • the third gate electrode EL3 may have the smallest length in the first direction D1 and the greatest distance from the substrate SUB in the third direction D3.
  • the first gate electrode EL1 may have the greatest length in the first direction D1 and the smallest distance from the substrate SUB in the third direction D3.
  • each of the stacked structures may decrease as it moves away from the outer-most one of the vertical channel structures (VS), which will be described later, and the gate electrodes (EL1, The side walls of EL2 and EL3) may be spaced apart at regular intervals along the first direction D1 from a plan view.
  • each of the interlayer dielectric layers may have different thicknesses.
  • the lowest and uppermost of the interlayer insulating layers (ILD) may have a smaller thickness than the other interlayer insulating layers (ILD).
  • the thickness of each interlayer dielectric layer (ILD) may have a different thickness depending on the characteristics of the semiconductor device, or may all be set to be the same.
  • the interlayer insulating films ILD may be formed of an insulating material to insulate the gate electrodes EL1, EL2, and EL3.
  • the interlayer insulating films (ILD) may be formed of silicon oxide.
  • a plurality of channel holes CH may be provided penetrating a portion of the stacked structures ST and the substrate SUB.
  • Vertical channel structures (VS) may be provided within the channel holes (CH).
  • the vertical channel structures VS are a plurality of cell strings CSTR shown in FIG. 2 and may be connected to the substrate SUB and extend in the third direction D3.
  • the connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by the lower surface of a portion of each of the vertical channel structures (VS) contacting the upper surface of the substrate (SUB), but is not limited or limited thereto. It may also be buried inside the substrate (SUB). When a portion of each of the vertical channel structures (VS) is buried inside the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).
  • a plurality of rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided.
  • rows of three vertical channel structures (VS) may penetrate one of the stacked structures (ST).
  • four or more rows of vertical channel structures (VS) pass through one of the stacked structures (ST), or one or two or more rows of vertical channel structures (VS) are stacked. It can penetrate one of the structures (ST).
  • the vertical channel structures (VS) corresponding to one column may be shifted in the first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent column.
  • D1 first direction
  • the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1.
  • the vertical channel structures VS may be arranged side by side in rows and columns.
  • Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3.
  • each of the vertical channel structures (VS) is shown as having a pillar shape with the same width at the top and bottom, but it is not limited or limited thereto, and as it moves toward the third direction (D3), the first direction (D1) and the second direction (D2) may have a shape in which the width is increased.
  • the upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.
  • Each of the vertical channel structures may include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical semiconductor pattern (VSP), and a dual junction (DJ).
  • the data storage pattern (DSP) may have a pipe shape with an open bottom or a macaroni shape
  • the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. It can have a shape.
  • the vertical semiconductor pattern (VSP) can fill the space surrounded by the vertical channel pattern (VCP) and dual junction (DJ).
  • the data storage pattern (DSP) covers the inner wall of each of the channel holes (CH), surrounds the outer wall of the vertical channel pattern (VCP) on the inside, and the side walls of the gate electrodes (EL1, EL2, EL3) on the outside. can come into contact with Accordingly, the areas corresponding to the second gate electrodes EL2 in the data storage pattern DSP are the second gate electrodes together with the areas corresponding to the second gate electrodes EL2 in the vertical channel pattern VCP.
  • Memory cells in which a memory operation program operation, read operation, or erase operation
  • the memory cells correspond to memory cell transistors (MCT) shown in FIG. 2.
  • the data storage pattern DSP is a data storage element that represents data values by trapping charges by a voltage applied through the second gate electrodes EL2 or maintaining the state of the charges (e.g., the polarization state of the charges). It can be.
  • the data storage pattern may be formed of a ferroelectric material to represent a binary data value or a multi-valued data value in a polarization state of charge.
  • the ferroelectric material is HfO x having an orthorhombic crystal structure , HfO (SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi(Sr, Ti)O 3 ), barium titanate , BaTiO 3 ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x or InO x .
  • the data storage pattern is formed by ONO (Tunneling Oxide-Charge trap Nitride-Blocking Oxide), which traps charges in the charge trap nitride layer to create binary data values or multi-valued data. It can represent a value.
  • ONO Treatment Oxide-Charge trap Nitride-Blocking Oxide
  • the data storage pattern (DSP) is shown extending in a vertical direction (e.g., in the third direction (D3)), but is not limited to this and is not limited to this and is formed on the outer wall of the vertical channel pattern (VCP) and in the channel holes (CH). It may have a plurality of segmented structures that are spaced apart only in areas corresponding to the second gate electrodes EL2 on each inner wall.
  • the vertical channel pattern (VCP) may cover the inner wall of the data storage pattern (DSP) and may extend in a vertical direction (eg, third direction D3).
  • the vertical channel pattern (VCP) may include a first part (VCP1) and a second part (VCP2) on the first part (VCP1).
  • the first portion (VCP1) of the vertical channel pattern (VCP) may be provided below each of the channel holes (CH) and may be in contact with the substrate (SUB).
  • the first part (VCP1) of the vertical channel pattern (VCP) may be used to block, suppress, or minimize leakage current in each of the vertical channel structures (VS) and/or as an epitaxial pattern.
  • the thickness of the first portion (VCP1) of the vertical channel pattern (VCP) may be greater than the thickness of the first gate electrode (EL1).
  • a sidewall of the first portion (VCP1) of the vertical channel pattern (VCP) may be surrounded by a data storage pattern (DSP).
  • the top surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located at a higher level than the top surface of the first gate electrode (EL1). More specifically, the top surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located between the top surface of the first gate electrode (EL1) and the bottom surface of the lowest one of the second gate electrodes (EL2). The bottom surface of the first portion VCP1 of the vertical channel pattern VCP may be located at a lower level than the top surface of the substrate SUB (that is, the bottom surface of the lowest one of the interlayer insulating layers ILD). A portion of the first portion (VCP1) of the vertical channel pattern (VCP) may overlap the first gate electrode (EL1) in the horizontal direction.
  • the horizontal direction means any direction extending on a plane parallel to the first direction D1 and the second direction D2.
  • the second part (VCP2) of the vertical channel pattern (VCP) may extend from the top surface of the first part (VCP1) in the third direction (D3).
  • the second part (VCP2) of the vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the vertical semiconductor pattern (VSP) and may correspond to the second gate electrodes (EL2). Accordingly, the second part (VCP2) of the vertical channel pattern (VCP), together with the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP), as described above, may form memory cells. .
  • the top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be substantially coplanar with the top surface of the vertical semiconductor pattern (VSP).
  • the top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be located at a higher level than the top surface of the uppermost one of the second gate electrodes (EL2). More specifically, the top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be located between the top and bottom surfaces of the third gate electrode (EL3).
  • the vertical channel pattern (VCP) is a component that transfers charges or holes to the data storage pattern (DSP), and may be formed of single crystalline silicon or polysilicon to form a channel or be boosted by an applied voltage.
  • the vertical channel pattern (VCP) may be formed of an oxide semiconductor material that can block, suppress, or minimize leakage current.
  • the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material containing at least one of In, Zn, or Ga with excellent leakage current characteristics.
  • the vertical channel pattern (VCP) may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO.
  • the vertical channel pattern can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and at least one of the gate electrodes (EL1, EL2, EL3)
  • the characteristics of any one transistor for example, threshold voltage distribution and speed of program/read operations
  • the electrical characteristics of the three-dimensional memory can be improved.
  • the vertical channel pattern is formed of a low-concentration p-doped material or a low-concentration n-doped material as well as single crystalline silicon or polysilicon for the channel formation operation of the dual junction (DJ) described later. It can be.
  • the vertical channel pattern (VCP) has been described as having a structure including a first part (VCP1) and a second part (VCP2), it is not limited or limited thereto and may have a structure excluding the first part (VCP1). .
  • the vertical channel pattern (VCP) is provided between the vertical semiconductor pattern (VSP) and the data storage pattern (DSP) formed to extend to the substrate (SUB) and is formed to extend to the substrate (SUB) to contact the substrate (SUB). You can.
  • the bottom surface of the vertical channel pattern (VCP) may be located at a lower level than the top surface of the substrate (SUB) (the bottom surface of the lowest one of the interlayer dielectric layers (ILD)), and the top surface of the vertical channel pattern (VCP) may be located at a lower level than the top surface of the substrate (SUB). It can be substantially coplanar with the top surface of the pattern (VSP).
  • the vertical semiconductor pattern (VSP) may be surrounded by the second portion (VCP2) of the vertical channel pattern (VCP).
  • the upper surface of the vertical semiconductor pattern (VSP) may contact the dual junction (DJ), and the lower surface of the vertical semiconductor pattern (VSP) may contact the first portion (VCP1) of the vertical channel pattern (VCP).
  • the vertical semiconductor pattern VSP may be spaced apart from the substrate SUB in the third direction D3. In other words, the vertical semiconductor pattern VSP may be electrically floating from the substrate SUB.
  • the vertical semiconductor pattern (VSP) may be formed of a material that helps diffusion of charges or holes in the vertical channel pattern (VCP). More specifically, the vertical semiconductor pattern (VSP) can be formed of a material with excellent charge and hole mobility.
  • the vertical semiconductor pattern (VSP) may be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material that is not doped with an impurity, or a polycrystalline semiconductor material.
  • the vertical semiconductor pattern VSP may be formed of polysilicon doped with the same first conductivity type impurity (eg, P- impurity) as the substrate SUB. In other words, the vertical semiconductor pattern (VSP) can improve the speed of memory operation by improving the electrical characteristics of 3D flash memory.
  • the vertical channel structures include the vertical semiconductor pattern (VSP)
  • the present invention is not limited or limited thereto and the vertical semiconductor pattern (VSP) may be omitted.
  • each of the vertical channel structures VS may not only have a structure omitting the vertical semiconductor pattern VSP, but may also have a structure including a back gate BG (not shown).
  • the back gate (BG) may be in contact with at least a portion of the back gate (BG) surrounded by the vertical channel pattern (VCP), and may be a component that applies a voltage to the vertical channel pattern (VCP) for a memory operation.
  • the vertical channel structures include an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT). ) may correspond to the channels.
  • ECT erase control transistor
  • SST1, SST2 first and second string select transistors
  • GST ground select transistor
  • MCT memory cell transistors
  • a dual junction may be provided on the top surface of the vertical channel pattern (VCP). That is, the dual junction (DJ) is located at the top of each of the vertical channel structures (VS) and connected to the top of the vertical channel pattern (VCP), so that it can operate as a drain junction (Drain junction).
  • a dual junction (DJ) may have a dual structure, each doped with different types of impurities. More specifically, the dual junction (DJ) may have a dual structure consisting of an N+ doped N+ junction and a P+ doped P+ junction.
  • the N+ junction and P+ junction of the dual junction are the target memory cells that are the target of the memory operation among the gate electrodes EL1, EL2, and EL3 (more specifically, the second gate electrodes EL2) during the memory operation.
  • the selected gate electrode (Sel EL) may be selectively activated to form a channel in the vertical channel pattern (VCP).
  • the N+ junction forms an N-type channel in the vertical channel pattern (VCP) in response to a positive voltage applied to the selected gate electrode (Sel EL), thereby recording “1” data (program operation). can be performed.
  • the P+ junction forms a P-type channel in the vertical channel pattern (VCP) in response to a negative voltage applied to the selected gate electrode (Sel EL), thereby performing a write operation (erase operation) that records “0” data. ) can be performed. That is, the N-type channel can be formed to extend vertically to connect to the N+ junction, and the P-type channel can also be formed to extend vertically to connect to the P+ junction.
  • the N+ junction and P+ junction of the dual junction may have a structure that is symmetrical to each other so as to have the same contact area with respect to the vertical channel pattern (VCP).
  • the N+ junction and the P+ junction may be formed to symmetrically bisect the space located above the vertical channel pattern (VCP) as shown in the drawing.
  • the dual junction (DJ) is not limited or limited thereto, and may include an N+ junction and a P+ junction configured to have different contact areas with respect to the vertical channel pattern (VCP).
  • the contact area for the vertical channel pattern (VCP) of each of the N+ junction and P+ junction in the dual junction (DJ) varies with the vertical channel pattern (VCP) according to the voltage applied through the gate electrodes (EL1, EL2, and EL3). It can be adjusted and determined based on the operation of forming an N-type channel and the operation of forming a P-type channel.
  • the speed of forming an N-type channel in the vertical channel pattern (VCP) in response to a positive voltage applied to the selected gate electrode (Sel EL) and the negative voltage applied to the selected gate electrode (Sel EL) In response, the contact area for each vertical channel pattern (VCP) of the N+ junction and P+ junction is adjusted and adjusted so that the speed of forming a P-type channel in the vertical channel pattern (VCP) is satisfied. can be decided.
  • the top surface of the dual junction (DJ) may be substantially coplanar with the top surface of each of the stacked structures (ST) (that is, the top surface of the uppermost one of the interlayer dielectric layers (ILD)).
  • the lower surface of the dual junction (DJ) may be located at a lower level than the upper surface of the third gate electrode (EL3). More specifically, the lower surface of the dual junction (DJ) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the dual junction DJ may overlap the third gate electrode EL3 in the horizontal direction.
  • a contact plug (CPG) connected to a bit line plug (BLPG) may be placed on top of the dual junction (DJ). That is, the dual junction (DJ) can be connected to the bit line plug (BLPG) through the contact plug (CPG).
  • the dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG), meaning that the cross-sectional area of the bit line plug (BLPG) applies voltage to each of the N+ junction and P+ junction of the dual junction (DJ). This is because it has an insufficient size (not enough to provide current for each of the N+ junction and P+ junction of the dual junction (DJ)). Therefore, the contact plug (CPG) has a sufficient area to apply voltage to each of the N+ junction and P+ junction of the dual junction (DJ) (capable of providing current to each of the N+ junction and P+ junction of the dual junction (DJ)). (sufficient area).
  • the contact plug (CPG) may be formed of a material that can reduce contact resistance between the dual junction (DJ) and the bit line plug (BLPG).
  • the contact plug (CPG) may be formed of a semiconductor or conductive material doped with impurities.
  • the contact plug (CPG) may contain impurities (more precisely, a second conductivity type (e.g., N-) different from the first conductivity type (e.g., P-) than the substrate (SUB) or vertical semiconductor pattern (VSP). Impurities) may be formed from a doped semiconductor material.
  • the dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG), but this is not limited or limited and the contact plug (CPG) may be omitted.
  • the bit line plug (BLPG) has sufficient area to apply voltage to each of the N+ junction and P+ junction of the dual junction (DJ) (to provide current to each of the N+ junction and P+ junction of the dual junction (DJ)). It is composed of a sufficient area to apply voltage or provide current directly to the dual junction (DJ).
  • a dual junction (DJ) may also be provided below the vertical channel pattern (VCP) as shown in FIG. 4B. That is, the dual junction (DJ) is located at the bottom of each of the vertical channel structures (VS) and connected to the bottom of the vertical channel pattern (VCP), so that it can operate as a source junction. Since the dual junction (DJ) operating as a source junction also has the same structure as the dual junction (DJ) operating as a drain junction described above, a detailed description thereof will be omitted.
  • a source region (SR) may be formed below the dual junction (DJ), which operates as a source junction in each of the vertical channel structures (VS).
  • the source regions SR of each of the vertical channel structures VS are connected to each other through separate wiring (not shown) in the substrate SUB, and thus may correspond to the common source line CSL of FIG. 2 .
  • the source region SR of each of the vertical channel structures VS may have a structure that is not connected to each other so that each vertical channel structure VS operates independently.
  • the source region (SR) may be omitted.
  • the dual junction (DJ) which operates as a source junction in each of the vertical channel structures (VS)
  • the substrate (SUB) so that the common source of FIG. 2 It may correspond to line (CSL).
  • the dual junction (DJ) operating as a source junction in each of the vertical channel structures (VS) may have a structure that is not connected to each other so that each vertical channel structure (VS) operates independently.
  • a source region (SR) is formed under the lower surface of the vertical channel pattern (VCP) as shown in FIG. 4A. You can.
  • the source regions SR of each of the vertical channel structures VS are connected to each other through separate wiring (not shown) in the substrate SUB, and thus may correspond to the common source line CSL of FIG. 2 .
  • the source region SR of each of the vertical channel structures VS may have a structure that is not connected to each other so that each vertical channel structure VS operates independently.
  • each of the vertical channel structures has a source area ( It may also have a source free structure with SR) omitted.
  • a separation trench TR extending in the first direction D1 may be provided between adjacent stacked structures ST.
  • the common source region (CSR) may be provided inside the substrate (SUB) exposed by the isolation trench (TR).
  • the common source region CSR may extend in the first direction D1 within the substrate SUB.
  • the common source region CSR may be formed of a semiconductor material doped with a second conductivity type impurity (eg, N+ impurity).
  • the common source region (CSR) may correspond to the common source line (CSL) of FIG. 2.
  • a common source plug may be provided in the isolation trench (TR).
  • the common source plug (CSP) may be connected to the common source region (CSR).
  • the top surface of the common source plug (CSP) may be substantially coplanar with the top surface of each of the stacked structures (ST) (that is, the top surface of the uppermost one of the interlayer insulating layers (ILD)).
  • the common source plug (CSP) may have a plate shape extending in the first direction (D1) and the third direction (D3). At this time, the common source plug (CSP) may have a shape whose width in the second direction (D2) increases as it moves toward the third direction (D3).
  • Insulating spacers may be interposed between the common source plug (CSP) and the stacked structures (ST). Insulating spacers SP may be provided between adjacent stacked structures ST to face each other.
  • the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material with a low dielectric constant.
  • a capping insulating layer may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP).
  • the capping insulating layer (CAP) may cover the top surface of the uppermost one of the interlayer insulating layers (ILD), the top surface of the dual junction (DJ), and the top surface of the common source plug (CSP).
  • the capping insulating film (CAP) may be formed of an insulating material different from the interlayer insulating films (ILD).
  • a contact plug (CPG) and a bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP).
  • the bit line contact plug BLPG may have a shape whose width in the first direction D1 and the second direction D2 increases as it moves toward the third direction D3.
  • a bit line (BL) may be provided on the capping insulating film (CAP) and the bit line contact plug (BLPG).
  • the bit line BL corresponds to one of the plurality of bit lines BL0, BL1, and BL2 shown in FIG. 2 and may be formed to extend along the second direction D2 using a conductive material.
  • the conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1, EL2, and EL3 described above.
  • the bit line BL may be electrically connected to the vertical channel structures VS through a bit line contact plug (BLPG).
  • BLPG bit line contact plug
  • the fact that the bit line (BL) is connected to the vertical channel structures (VS) may mean that it is connected to the vertical channel pattern (VCP) through the dual junction (DJ) included in the vertical channel structures (VS). .
  • Each bit line contact plug may have a structure that is offset from each other so as to be connected to each of the fields BL0, BL1, and BL2. For example, as shown in FIG.
  • the first vertical channel structure VS1 may include a bit line contact plug BLPG that is biased in the first direction D1 on a plane to be connected to the bit line BL0
  • the second vertical channel structure (VS2) may include a bit line contact plug (BLPG) located at the center of the plane so as to be connected to the bit line (BL1)
  • the third vertical channel structure (VS3) may include a bit line (BL2). It may include a bit line contact plug (BLPG) that is biased in a direction opposite to the first direction (D1) on a plane so as to be connected to.
  • the three-dimensional memory is not limited or limited to the described structure, and depending on the implementation example, it may include a vertical channel pattern (VCP), a dual junction (DJ), a data storage pattern (DSP), and gate electrodes (EL1, EL2). , EL3), can be implemented in various structures provided that it includes a bit line (BL).
  • VCP vertical channel pattern
  • DJ dual junction
  • DSP data storage pattern
  • EL1, EL2 gate electrodes
  • EL3 gate electrodes
  • BL bit line
  • FIG. 5 is a flow chart showing a memory operation method of a three-dimensional memory according to an embodiment
  • FIGS. 6A to 6B show the structure of a three-dimensional memory to explain the memory operation method of the three-dimensional memory shown in FIG. 5.
  • FIGS. 7A and 7B are diagrams for explaining an improved memory window of a three-dimensional memory according to an embodiment
  • FIG. 8 is a diagram for explaining a read operation of a three-dimensional memory according to an embodiment.
  • 9A to 9B are diagrams showing a memory window to explain an erase operation of a three-dimensional memory according to an embodiment.
  • the three-dimensional memory corresponds to the target memory cell that is the target of the memory operation among the gate electrodes EL1, EL2, and EL3 (more precisely, the second gate electrode EL2).
  • a voltage can be applied to the selected gate electrode (Sel EL).
  • the three-dimensional memory in response to the voltage applied to the selected gate electrode (Sel EL), includes an N+ junction included in the dual junction (DJ) formed at the top of each of the vertical channel structures (VS), and As one of the P+ junctions is selectively activated, a memory operation can be performed by forming a channel in a vertical channel pattern (VCP).
  • VCP vertical channel pattern
  • the 3D memory is generated by applying a positive voltage to the gate electrode (Sel EL) selected in step S510, through the N+ junction of the dual junction (DJ) in step S520.
  • a recording operation can be performed by forming an N-type channel in a vertical channel pattern (VCP).
  • the 3D memory applies a positive voltage to the gate electrode (Sel EL) selected in step S510, thereby creating a vertical channel pattern (VCP) through the N+ junction of the dual junction (DJ) in step S520.
  • a recording operation (program operation) of recording “1” data can be performed by forming an N-type channel. Accordingly, the N-type channel may be formed to extend vertically to connect to the N+ junction.
  • the 3D memory applies a negative voltage to the gate electrode (Sel EL) selected in step S520, as shown in FIG. 6B, and connects the P+ junction of the dual junction (DJ) in step S520.
  • a recording operation can be performed by forming a P-type channel in the vertical channel pattern (VCP).
  • the three-dimensional memory records data of "0" by applying a negative voltage to the gate electrode (Sel EL) selected in step S520 and forming a P-type channel in step S520.
  • An operation (erase operation) can be performed. Accordingly, the P-type channel may be formed to extend vertically to connect to the P+ junction.
  • the three-dimensional memory can perform a memory operation by forming a channel in the vertical channel pattern (VCP) using a dual junction (DJ) formed at the bottom of each of the vertical channel structures (VS).
  • VCP vertical channel pattern
  • DJ dual junction
  • the three-dimensional memory implements a write operation (erase operation) that forms a P-type channel by applying a negative voltage to the selected gate electrode (Sel EL) based on a dual junction (DJ), By supporting random access, high-speed memory operation is possible.
  • the three-dimensional memory can implement multi-valued memory by adjusting the value of the voltage applied to the selected gate electrode (Sel EL) to a plurality of various values.
  • 3D memory can select the value of the voltage applied to the selected gate electrode (Sel EL) within the positive as well as negative range, the existing 3D NAND flash memory as shown in FIG. 7A It is possible to implement multi-value conversion of 5 bits or more as shown in FIG. 7B, which is more improved than multi-value conversion of 4 bits.
  • the three-dimensional memory is multi-valued according to the adjusted positive voltage value and the adjusted negative voltage value by adjusting the value of the positive voltage and negative voltage applied to the selected gate electrode (Sel EL).
  • a recording operation (program operation) of the specified value can be performed.
  • the erase operation may be performed on a page-by-page or block-by-block basis.
  • the 3D memory can perform an erase operation in two steps as shown in FIGS. 9A and 9B.
  • three-dimensional memory has the first stage of moving memory cells programmed with negative voltage around the threshold voltage (V th ) of 0V and the first step of moving memory cells programmed with positive voltage around the threshold voltage (V th ) of 0V.
  • the erase operation can be performed in two steps: moving to .
  • the program operation may be performed by applying a positive voltage or a negative voltage, as described above.
  • the erase operation performed in two steps requires an erase voltage (V erase ) of 25V or more to move the threshold voltage (V th ) of +6V to -4V in the existing 3D NAND flash memory.
  • V erase erase voltage
  • a voltage of +/- 20V or less is applied to move +6V to the threshold voltage (V th ) of 0V and -6V to the threshold voltage (V th ) of 0V. Therefore, it has the advantage of taking less time than a few ms.
  • Figure 10 is a flow chart showing a method of manufacturing a 3D memory according to an embodiment.
  • the manufacturing method described below is for manufacturing a three-dimensional memory with the structure described above with reference to FIGS. 2 to 4, and is assumed to be performed by an automated and mechanized manufacturing system.
  • the manufacturing system can prepare a semiconductor structure (SEMI-STR).
  • the semiconductor structure (SEM-STR) includes gate electrodes (EL1, EL2, EL3) extending in the horizontal direction on the substrate (SUB) and stacked while being spaced apart in the vertical direction; and vertical channel structures VS extending in the vertical direction and penetrating the gate electrodes EL1, EL2, and EL3.
  • the semiconductor structure (SEMI-STR) may include the stacked structures (ST) and vertical channel structures (VS) of the structures described above with reference to FIGS. 2 to 4. However, a dual junction (DJ) is not formed in the vertical channel structures (VS).
  • the manufacturing system can prepare a semiconductor structure (SEMI-STR) in which a source region is formed at the bottom of each of the vertical channel structures (VS).
  • the manufacturing system may prepare a semiconductor structure having a source-free structure in which the source region is omitted at the bottom of each of the vertical channel structures (VS).
  • step S1010 the manufacturing system produces a semiconductor structure (SEMI) in which a dual junction is formed at the bottom of each of the vertical channel structures (VS).
  • SEMI semiconductor structure in which a dual junction is formed at the bottom of each of the vertical channel structures (VS).
  • -STR can be prepared.
  • the manufacturing system may place a first mask pattern (MASK 1) that covers a portion of the upper surface of each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).
  • MASK 1 a first mask pattern that covers a portion of the upper surface of each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).
  • step S1030 the manufacturing system uses the first mask pattern (MASK 1) to apply N+ doped N+ to the remaining area of the upper surface that is not obscured by the first mask pattern (MASK 1) in each of the vertical channel structures (VS). A junction can be formed.
  • the manufacturing system may place a second mask pattern (MASK 2) that covers the remaining upper surface area of each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).
  • a second mask pattern (MASK 2) that covers the remaining upper surface area of each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).
  • step S1050 the manufacturing system uses the second mask pattern (MASK 2) to apply P+ doped P+ to a portion of the upper surface that is not obscured by the second mask pattern (MASK 2) in each of the vertical channel structures (VS). A P+ junction can be formed.
  • the first mask pattern (MASK 1) and the second mask pattern (MASK 2) each point to symmetrical areas of the same area so that the N+ junction and P+ junction in each of the vertical channel structures (VS) have a symmetrical structure. It can be configured and arranged as follows.
  • a dual junction (DJ) including an N+ junction and a P+ junction may be formed in each of the vertical channel structures (VS).
  • steps S1020 to S1030 are performed after steps S1040 to S1050, so that the P+ junction can be formed before the N+ junction.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

La divulgation concerne une mémoire tridimensionnelle ayant une structure à double jonction. Selon un mode de réalisation, la mémoire tridimensionnelle peut comprendre : des électrodes de grille espacées et empilées dans une direction verticale tout en s'étendant dans la direction horizontale sur un substrat; et des structures de canal vertical passant à travers les électrodes de grille et s'étendant dans la direction verticale, chacune des structures de canal vertical comprenant un motif de canal vertical et un motif de stockage de données et ayant, sur son extrémité supérieure, une double jonction d'une double structure dopée avec différents types d'impuretés.
PCT/KR2023/011128 2022-07-12 2023-07-31 Mémoire tridimensionnelle ayant une structure à double jonction WO2024063315A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR20220085360 2022-07-12
KR1020220118987A KR20240008762A (ko) 2022-07-12 2022-09-21 듀얼 정션 구조를 갖는 3차원 메모리
KR10-2022-0118987 2022-09-21

Publications (1)

Publication Number Publication Date
WO2024063315A1 true WO2024063315A1 (fr) 2024-03-28

Family

ID=89717761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2023/011128 WO2024063315A1 (fr) 2022-07-12 2023-07-31 Mémoire tridimensionnelle ayant une structure à double jonction

Country Status (2)

Country Link
KR (1) KR20240008762A (fr)
WO (1) WO2024063315A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008004765A (ja) * 2006-06-22 2008-01-10 Toshiba Corp 不揮発性半導体記憶装置
KR20120067024A (ko) * 2010-12-15 2012-06-25 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
KR20160004470A (ko) * 2014-07-02 2016-01-13 삼성전자주식회사 3차원 반도체 메모리 장치
KR20200078779A (ko) * 2018-12-21 2020-07-02 삼성전자주식회사 수직형 메모리 장치
KR20220101784A (ko) * 2021-01-12 2022-07-19 한양대학교 산학협력단 Igzo 채널층의 컨택트 저항을 개선하는 3차원 플래시 메모리

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008004765A (ja) * 2006-06-22 2008-01-10 Toshiba Corp 不揮発性半導体記憶装置
KR20120067024A (ko) * 2010-12-15 2012-06-25 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
KR20160004470A (ko) * 2014-07-02 2016-01-13 삼성전자주식회사 3차원 반도체 메모리 장치
KR20200078779A (ko) * 2018-12-21 2020-07-02 삼성전자주식회사 수직형 메모리 장치
KR20220101784A (ko) * 2021-01-12 2022-07-19 한양대학교 산학협력단 Igzo 채널층의 컨택트 저항을 개선하는 3차원 플래시 메모리

Also Published As

Publication number Publication date
KR20240008762A (ko) 2024-01-19

Similar Documents

Publication Publication Date Title
KR102612195B1 (ko) 반도체 장치 및 반도체 장치의 제조 방법
WO2011004945A1 (fr) Dispositif à semi-conducteurs à structure en réseaux empilés, réseau de mémoire flash de type non-et utilisant ce dispositif, et procédé de fabrication correspondant
WO2010041838A2 (fr) Assemblage de cellules de mémoire flash à haute densité, chaîne d'assemblages de cellules et leur procédé de fabrication
KR20190092808A (ko) 반도체 장치
KR20190118751A (ko) 반도체 장치
KR20180113069A (ko) 수직 적층 메모리 소자
WO2019235701A1 (fr) Dispositif de mémoire de type vertical et son procédé de fabrication
KR20210022797A (ko) 반도체 장치
WO2020204314A1 (fr) Mémoire flash tridimensionnelle à base de matériau ferroélectrique et procédé de fabrication associé
WO2022154248A1 (fr) Mémoire flash tridimensionnelle permettant d'améliorer la résistance de contact d'une couche de canal d'igzo
KR20210122399A (ko) 반도체 소자
WO2024063315A1 (fr) Mémoire tridimensionnelle ayant une structure à double jonction
WO2017175955A1 (fr) Dispositif de mémoire ayant une colonne à semi-conducteurs verticale
WO2022215917A1 (fr) Procédé de fabrication d'une mémoire flash tridimensionnelle ferroélectrique
WO2023195688A1 (fr) Procédé de fabrication d'une mémoire flash tridimensionnelle faisant appel à un processus d'empilement
WO2023195684A1 (fr) Mémoire flash tridimensionnelle reposant sur un processus d'empilement et son procédé de fabrication
WO2021246825A1 (fr) Mémoire flash tridimensionnelle à base de matériau ferroélectrique et son procédé de fonctionnement
WO2023153671A1 (fr) Procédé de fonctionnement d'une mémoire flash tridimensionnelle à base ferroélectrique comprenant un motif de stockage de données
WO2023153670A1 (fr) Procédé de fonctionnement pour mémoire flash tridimensionnelle comprenant un motif de stockage de données à base ferroélectrique et une grille arrière
WO2023033338A1 (fr) Mémoire flash tridimensionnelle à base ferroélectrique
WO2023068833A1 (fr) Mémoire flash tridimensionnelle et son procédé de fonctionnement
WO2024128521A1 (fr) Mémoire tridimensionnelle présentant une structure comprenant des fils d'écriture et des fils de lecture séparés
WO2024191270A1 (fr) Mémoire flash tridimensionnelle qui améliore le courant de fuite
KR102621680B1 (ko) 강유전체 분극 특성을 개선하는 3차원 플래시 메모리 및 그 제조 방법
WO2024191272A1 (fr) Mémoire flash tridimensionnelle pour améliorer la distribution de courant de cellule

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23868375

Country of ref document: EP

Kind code of ref document: A1