WO2024063315A1

WO2024063315A1 - Three-dimensional memory having dual junction structure

Info

Publication number: WO2024063315A1
Application number: PCT/KR2023/011128
Authority: WO
Inventors: 송창은; 송윤흡
Original assignee: 페디셈 주식회사; 한양대학교 산학협력단
Priority date: 2022-07-12
Filing date: 2023-07-31
Publication date: 2024-03-28
Also published as: KR20240008762A

Abstract

Disclosed is a three-dimensional memory having a dual junction structure. According to an embodiment, the three-dimensional memory may comprise: gate electrodes spaced apart and stacked in a vertical direction while extending in the horizontal direction on a substrate; and vertical channel structures passing through the gate electrodes and extending in the vertical direction, wherein each of the vertical channel structures comprises a vertical channel pattern and a data storage pattern and has, on the upper end thereof, a dual junction of a double structure doped with different types of impurities from each other.

Description

3D memory with dual junction structure

The following embodiments are technologies related to three-dimensional memory, its operation method, and its manufacturing method.

Existing DRAM supports random access in byte units, enabling high-speed memory operations, but has the disadvantage of low storage space.

On the other hand, existing 3D NAND flash memory can implement a large storage capacity, but has the problem of not supporting byte-level random access because memory operations are performed on a page-by-page or block-by-block basis.

In more detail, referring to FIG. 1 to explain the problems of the existing 3D NAND flash memory, the existing 3D NAND flash memory forms a P-type channel in the channel pattern 110 to transmit data of “0”. When performing a write operation (erase operation), a negative voltage (-V write0) is applied to the selected gate electrode 120 corresponding to the target memory cell, and a positive pass voltage (-V _write0 ) is applied to the remaining gate electrodes 130. Since +V _pass ) is applied, an NPN junction is formed in the channel pattern 110. Accordingly, the erase operation on the target memory cell 111 is not performed. Accordingly, the existing 3D NAND flash memory performs an erase operation on a page-by-page or block-by-block basis using the GIDL method, and has a problem in that it cannot support random access on a byte-by-byte basis.

Meanwhile, through the popularization of digital devices and sensors, big data is being generated at a scale that is difficult to estimate in real life. With the development of big data, there is a demand in the field of memory technology for memory that supports random access, enables high-speed memory operation, and provides a large storage space.

Accordingly, in the following embodiments, we propose a three-dimensional memory that supports random access, enables high-speed memory operation, and implements a large storage space.

Embodiments propose a three-dimensional memory, an operating method, and a manufacturing method that enables high-speed memory operation by supporting random access while implementing a large storage space.

However, the technical problems to be solved by the present invention are not limited to the above problems, and may be expanded in various ways without departing from the technical spirit and scope of the present invention.

According to one embodiment, a three-dimensional memory includes gate electrodes that extend in the horizontal direction on a substrate and are spaced apart in the vertical direction and are stacked; and vertical channel structures penetrating the gate electrodes and extending in the vertical direction - each of the vertical channel structures includes a vertical channel pattern and a data storage pattern, and different types of structures are located on top of each of the vertical channel structures. It may include the formation of a dual junction, each doped with an impurity.

According to one aspect, the dual junction may include an N+ doped N+ junction and a P+ doped P+ junction.

According to another aspect, the N+ junction and the P+ junction may have a structure that is symmetrical to each other so as to have the same contact area with respect to the vertical channel pattern.

According to another aspect, one of the N+ junction and the P+ junction responds to a voltage applied to a selected gate electrode corresponding to a target memory cell that is the target of the memory operation among the gate electrodes during a memory operation, It may be selectively activated to form a channel in the vertical channel pattern.

According to another aspect, the N+ junction may form an N-type channel in the vertical channel pattern in response to a positive voltage applied to the selected gate electrode.

According to another aspect, the N-type channel may be formed to extend in the vertical direction to connect to the N+ junction.

According to another aspect, the P+ junction may form a P-type channel in the vertical channel pattern in response to a negative voltage applied to the selected gate electrode.

According to another aspect, the P-type channel is,

It may be characterized as extending in the vertical direction to connect to the P+ junction.

According to another aspect, the dual junction may be connected to a bit line plug through a contact plug disposed at the top.

According to another aspect, the dual junction may be formed at the bottom of each of the vertical channel structures.

According to another aspect, a source region may be formed at the bottom of each of the vertical channel structures.

According to another aspect, the three-dimensional memory may be characterized as having a source free structure in which a source area is omitted at the bottom of each of the vertical channel structures.

According to one embodiment, gate electrodes are formed to extend in the horizontal direction on the substrate and are spaced apart in the vertical direction and are stacked; and vertical channel structures penetrating the gate electrodes and extending in the vertical direction - each of the vertical channel structures includes a vertical channel pattern and a data storage pattern, and different types of structures are located on top of each of the vertical channel structures. The memory operation method of the three-dimensional memory, which includes forming dual junctions of a double structure each doped with impurities, is a method of operating a memory on a selected gate electrode corresponding to a target memory cell that is the target of a memory operation among the gate electrodes. applying a voltage; and performing a memory operation by forming a channel in the vertical channel pattern by selectively activating one of the N+ junction and the P+ junction included in the dual junction in response to the voltage applied to the selected gate electrode. can do.

According to one aspect, the applying step includes applying a positive voltage to the selected gate electrode, and the performing the memory operation includes, in response to the positive voltage applied to the selected gate electrode, The method may include performing a recording operation by forming an N-type channel in the vertical channel pattern through the N+ junction.

According to another aspect, the applying step includes adjusting the value of the positive voltage applied to the selected gate electrode, and the step of performing the memory operation includes adjusting the value of the positive voltage applied to the selected gate electrode. It may be characterized by including the step of performing a recording operation of the multi-valued value.

According to another aspect, the applying step includes applying a negative voltage to the selected gate electrode, and the performing the memory operation includes responding to the negative voltage applied to the selected gate electrode. Thus, it may be characterized by including the step of forming a P-type channel in the vertical channel pattern through the P+ junction and performing a recording operation.

According to another aspect, the applying step includes adjusting the value of the negative voltage applied to the selected gate electrode, and the step of performing the memory operation includes adjusting the value of the negative voltage applied to the selected gate electrode. A memory operation method of a three-dimensional memory, comprising the step of performing a recording operation of a multivalued value according to .

According to another aspect, the step of performing the memory operation includes selectively activating one of the N+ junction and the P+ junction included in the dual junction formed at the bottom of each of the vertical channel structures, thereby forming the vertical channel pattern. It may further include forming a channel to perform a memory operation.

According to one embodiment, a method of manufacturing a three-dimensional memory including dual junctions of a dual structure each doped with different types of impurities includes stacked structures extending in the horizontal direction on a substrate and spaced apart in the vertical direction. gate electrodes; and preparing a semiconductor structure including vertical channel structures extending in the vertical direction and penetrating the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern. disposing a first mask pattern on the semiconductor structure to cover a portion of a top surface of each of the vertical channel structures; Using the first mask pattern, forming an N+ doped N+ junction in a remaining area of the upper surface of each of the vertical channel structures that is not obscured by the first mask pattern; disposing a second mask pattern on the semiconductor structure to cover the remaining upper surface area of each of the vertical channel structures; and using the second mask pattern to form a P+ doped P+ junction in a portion of the upper surface of each of the vertical channel structures that is not obscured by the second mask pattern.

According to one aspect, the first mask pattern and the second mask pattern each cover symmetrical areas of the same area so that the N+ junction and the P+ junction in each of the vertical channel structures have a structure that is symmetrical to each other. You can do this.

According to another aspect, the step of preparing the semiconductor structure may be characterized as preparing the semiconductor structure in which the dual junction is formed at the bottom of each of the vertical channel structures.

According to another aspect, the step of preparing the semiconductor structure may be characterized in that the step of preparing the semiconductor structure in which a source region is formed at the bottom of each of the vertical channel structures.

According to another aspect, the step of preparing the semiconductor structure is a step of preparing the semiconductor structure having a source free structure in which a source region is omitted at the bottom of each of the vertical channel structures. can do.

Embodiments may propose a three-dimensional memory, an operating method, and a manufacturing method that enables high-speed memory operation by supporting random access while implementing a large storage space.

However, the effects of the present invention are not limited to the above effects, and may be expanded in various ways without departing from the technical spirit and scope of the present invention.

Figure 1 is a diagram to explain problems with existing 3D NAND flash memory.

Figure 2 is a simplified circuit diagram showing an array of three-dimensional memory according to one embodiment.

Figure 3 is a plan view showing the structure of a three-dimensional memory according to an embodiment.

FIGS. 4A to 4C are cross-sectional views showing the structure of a three-dimensional memory according to an embodiment, and correspond to a cross-section taken along line A-A' of FIG. 3.

Figure 5 is a flow chart showing a memory operation method of a 3D memory according to an embodiment.

FIGS. 6A and 6B are cross-sectional views showing the structure of the 3D memory in order to explain the memory operation method of the 3D memory shown in FIG. 5.

7A to 7B are diagrams for explaining an improved memory window of a 3D memory according to an embodiment.

FIG. 8 is a diagram illustrating a memory window to explain a read operation of a 3D memory according to an embodiment.

9A to 9B are diagrams showing a memory window to explain an erase operation of a 3D memory according to an embodiment.

Figure 10 is a flow chart showing a method of manufacturing a 3D memory according to an embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or limited by the examples. Additionally, the same reference numerals in each drawing indicate the same members.

Additionally, terminologies used in this specification are terms used to appropriately express preferred embodiments of the present invention, and may vary depending on the intention of the viewer, operator, or customs in the field to which the present invention belongs. Therefore, definitions of these terms should be made based on the content throughout this specification. For example, in this specification, singular forms also include plural forms unless specifically stated otherwise in the context. Additionally, as used herein, “comprises” and/or “comprising” refers to a referenced component, step, operation, and/or element that includes one or more other components, steps, operations, and/or elements. It does not exclude the presence or addition of elements. Additionally, although terms such as first and second are used in this specification to describe various areas, directions, and shapes, these areas, directions, and shapes should not be limited by these terms. These terms are merely used to distinguish one area, direction or shape from another area, direction or shape. Accordingly, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

Additionally, it should be understood that the various embodiments of the present invention are different from one another but are not necessarily mutually exclusive. For example, specific shapes, structures and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. Additionally, it should be understood that the location, arrangement, or configuration of individual components in each presented embodiment category may be changed without departing from the technical spirit and scope of the present invention.

Hereinafter, with reference to the drawings, a three-dimensional memory that enables high-speed memory operation by supporting random access while implementing a large storage space, a method of operating the same, and a method of manufacturing the same will be described in detail.

Referring to FIG. 2, the three-dimensional memory array according to one embodiment includes a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a common source line (CSL) and bit lines (BL0, It may include a plurality of cell strings (CSTR) arranged between BL1 and BL2).

The bit lines BL0, BL1, and BL2 may extend in the second direction D2 and be spaced apart from each other in the first direction D1 and may be arranged two-dimensionally. Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and may form a rectangular coordinate system defined by the X, Y, and Z axes.

A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, and BL2). The cell strings CSTR may be provided between the bit lines BL0, BL1, and BL2 and one common source line CSL and may be commonly connected to the common source line CSL. At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may extend in the first direction (D1) and be spaced apart from each other along the second direction (D2), forming a two-dimensional can be arranged sequentially. The same electrical voltage may be applied to the plurality of common source lines (CSL), but this is not limited or limited, and each of the plurality of common source lines (CSL) is electrically independently controlled, so that different voltages may be applied. there is.

The cell strings CSTR may extend in the third direction D3 and be arranged to be spaced apart from each other along the second direction D2 for each bit line. According to the embodiment, each of the cell strings (CSTR) is connected to a ground selection transistor (GST) connected to the common source line (CSL), the bit lines (BL0, BL1, BL2), and the first and second strings connected in series. Memory cell transistors (MCT) and erase control transistor (ECT) arranged in series between the selection transistors (SST1, SST2), the ground selection transistor (GST) and the first and second string selection transistors (SST1, SST2) ) can be composed of. Additionally, each memory cell transistor (MCT) may include a data storage element.

As an example, each cell string CSTR may include first and second string selection transistors SST1 and SST2 connected in series, and the second string selection transistor SST2 may be connected to the bit lines BL0 and BL1. , BL2) can be connected to one of the following. However, without being limited or limited thereto, each cell string CSTR may include one string select transistor. As another example, the ground selection transistor GST in each cell string CSTR may be composed of a plurality of MOS transistors connected in series, similar to the first and second string selection transistors SST1 and SST2. .

One cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from the common source lines (CSL). That is, the memory cell transistors MCT may be connected in series while being arranged along the third direction D3 between the first string selection transistor SST1 and the ground selection transistor GST. The erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) is between the first string select transistor (SST1) and the highest one of the memory cell transistors (MCT) and between the ground select transistor (GST) and the lowest one of the memory cell transistors (MCT). It may further include dummy cell transistors (DMC) each connected to each other.

According to an embodiment, the first string selection transistor SST1 may be controlled by the first string selection lines SSL1-1, SSL1-2, and SSL1-3, and the second string selection transistor SST2 may be controlled by the first string selection lines SSL1-1, SSL1-2, and SSL1-3. It can be controlled by 2 string selection lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may each be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may each be controlled by a dummy word line (DWL). The ground select transistor GST may be controlled by the ground select lines GSL0, GSL1, and GSL2, and the erase control transistor ECT may be controlled by the erase control line ECL. A plurality of erase control transistors (ECT) may be provided. Common source lines (CSL) may be commonly connected to sources of erase control transistors (ECT).

The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and be in an equipotential state. . However, without being limited or limited thereto, even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be controlled independently. there is.

Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string selection lines (SSL2-1, SSL2-2, SSL2-3) ) extends along the first direction (D1), are spaced apart from each other in the second direction (D2), and may be arranged two-dimensionally. Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string provided at substantially the same level from the common source lines (CSL) The selection lines (SSL2-1, SSL2-2, and SSL2-3) may be electrically separated from each other. Additionally, the erase control transistors ECT of different cell strings CSTR may be controlled by a common erase control line ECL. Erase control transistors (ECT) may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, during an erase operation of the memory cell array, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and/or the common source lines (CSL), and the string select transistor (SST) and/or Alternatively, gate-induced leakage current may be generated in the erase control transistors (ECT).

The string selection line (SSL) described above may be expressed as an upper selection line (USL), and the ground selection line (GSL) may be expressed as a lower selection line.

FIG. 3 is a plan view showing the structure of a three-dimensional memory according to an embodiment, and FIGS. 4A to 4C are cross-sectional views showing the structure of a three-dimensional memory according to an embodiment, with FIG. 3 taken along line A-A'. Applies to cross section.

Referring to FIGS. 3 and 4A to 4C, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a monocrystalline silicon substrate. there is. The substrate SUB may be doped with a first conductivity type impurity (eg, a P- impurity).

Stacked structures (ST) may be disposed on the substrate (SUB). The stacked structures ST may extend in the first direction D1 and be two-dimensionally arranged along the second direction D2. Additionally, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1, EL2, and EL3 and interlayer insulating films ILD that are alternately stacked in a vertical direction perpendicular to the top surface of the substrate SUB (for example, in the third direction D3). may include. The stacked structures ST may have a substantially flat top surface. That is, the top surface of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or the reverse direction of the third direction D3.

Referring again to FIG. 2, each of the gate electrodes (EL1, EL2, EL3) includes an erase control line (ECL), ground selection lines (GSL0, GSL1, GSL2), and a word line sequentially stacked on the substrate (SUB). (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) It can be.

Each of the gate electrodes EL1, EL2, and EL3 may extend in the first direction D1 and have substantially the same thickness in the third direction D3. Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes EL1, EL2, and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1, EL2, and EL3 is made of a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1, EL2, and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal materials described.

More specifically, the gate electrodes EL1, EL2, and EL3 include the first gate electrode EL1 at the bottom, the third gate electrode EL3 at the top, and the first gate electrode EL1 and the third gate electrode EL3. It may include a plurality of second gate electrodes EL2 therebetween. The first gate electrode EL1 and the third gate electrode EL3 are each shown and described in singular form, but this is illustrative and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0, GSL1, and GLS2 shown in FIG. 2. The second gate electrode EL2 may correspond to one of the word lines WL0-WLn and DWL shown in FIG. 2. The third gate electrode EL3 is connected to one of the first string selection lines SSL1-1, SSL1-2, and SSL1-3 or the second string selection lines SSL2-1 and SSL2-2 shown in FIG. 2. , SSL2-3) may apply.

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the length of the gate electrodes EL1, EL2, and EL3 of the stacked structures ST may decrease in the first direction D1 as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the greatest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the greatest length in the first direction D1 and the smallest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures (ST) may decrease as it moves away from the outer-most one of the vertical channel structures (VS), which will be described later, and the gate electrodes (EL1, The side walls of EL2 and EL3) may be spaced apart at regular intervals along the first direction D1 from a plan view.

Each of the interlayer dielectric layers (ILD) may have different thicknesses. For example, the lowest and uppermost of the interlayer insulating layers (ILD) may have a smaller thickness than the other interlayer insulating layers (ILD). However, this is an example and is not limited to this, and the thickness of each interlayer dielectric layer (ILD) may have a different thickness depending on the characteristics of the semiconductor device, or may all be set to be the same. The interlayer insulating films ILD may be formed of an insulating material to insulate the gate electrodes EL1, EL2, and EL3. As an example, the interlayer insulating films (ILD) may be formed of silicon oxide.

A plurality of channel holes CH may be provided penetrating a portion of the stacked structures ST and the substrate SUB. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures VS are a plurality of cell strings CSTR shown in FIG. 2 and may be connected to the substrate SUB and extend in the third direction D3. The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by the lower surface of a portion of each of the vertical channel structures (VS) contacting the upper surface of the substrate (SUB), but is not limited or limited thereto. It may also be buried inside the substrate (SUB). When a portion of each of the vertical channel structures (VS) is buried inside the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

A plurality of rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided. For example, as shown in FIG. 3 , rows of three vertical channel structures (VS) may penetrate one of the stacked structures (ST). However, without being limited or limited thereto, four or more rows of vertical channel structures (VS) pass through one of the stacked structures (ST), or one or two or more rows of vertical channel structures (VS) are stacked. It can penetrate one of the structures (ST). In a pair of adjacent columns, the vertical channel structures (VS) corresponding to one column may be shifted in the first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent column. there is. From a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited or restricted thereto, the vertical channel structures VS may be arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures (VS) is shown as having a pillar shape with the same width at the top and bottom, but it is not limited or limited thereto, and as it moves toward the third direction (D3), the first direction (D1) and the second direction (D2) may have a shape in which the width is increased. The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical semiconductor pattern (VSP), and a dual junction (DJ). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape with an open bottom or a macaroni shape, and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. It can have a shape. The vertical semiconductor pattern (VSP) can fill the space surrounded by the vertical channel pattern (VCP) and dual junction (DJ).

The data storage pattern (DSP) covers the inner wall of each of the channel holes (CH), surrounds the outer wall of the vertical channel pattern (VCP) on the inside, and the side walls of the gate electrodes (EL1, EL2, EL3) on the outside. can come into contact with Accordingly, the areas corresponding to the second gate electrodes EL2 in the data storage pattern DSP are the second gate electrodes together with the areas corresponding to the second gate electrodes EL2 in the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by voltage applied through (EL2) can be configured. The memory cells correspond to memory cell transistors (MCT) shown in FIG. 2. To this end, the data storage pattern DSP is a data storage element that represents data values by trapping charges by a voltage applied through the second gate electrodes EL2 or maintaining the state of the charges (e.g., the polarization state of the charges). It can be.

For example, the data storage pattern (DSP) may be formed of a ferroelectric material to represent a binary data value or a multi-valued data value in a polarization state of charge. The _{ferroelectric} material is HfO _x having an orthorhombic _crystal structure _, HfO (SrBi ₂ Ti ₂ O ₃ ), BLT(Bi(La, Ti)O ₃ ), PLZT(Pb(La, Zr)TiO ₃ ), BST(Bi(Sr, Ti)O ₃ ), barium titanate , BaTiO ₃ ), P(VDF-TrFE), PVDF, AlO _x , ZnO _x , TiO _x , TaO _x or InO _x .

For another example, the data storage pattern (DSP) is formed by ONO (Tunneling Oxide-Charge trap Nitride-Blocking Oxide), which traps charges in the charge trap nitride layer to create binary data values or multi-valued data. It can represent a value.

In the drawing, the data storage pattern (DSP) is shown extending in a vertical direction (e.g., in the third direction (D3)), but is not limited to this and is not limited to this and is formed on the outer wall of the vertical channel pattern (VCP) and in the channel holes (CH). It may have a plurality of segmented structures that are spaced apart only in areas corresponding to the second gate electrodes EL2 on each inner wall.

The vertical channel pattern (VCP) may cover the inner wall of the data storage pattern (DSP) and may extend in a vertical direction (eg, third direction D3). The vertical channel pattern (VCP) may include a first part (VCP1) and a second part (VCP2) on the first part (VCP1).

The first portion (VCP1) of the vertical channel pattern (VCP) may be provided below each of the channel holes (CH) and may be in contact with the substrate (SUB). The first part (VCP1) of the vertical channel pattern (VCP) may be used to block, suppress, or minimize leakage current in each of the vertical channel structures (VS) and/or as an epitaxial pattern. For example, the thickness of the first portion (VCP1) of the vertical channel pattern (VCP) may be greater than the thickness of the first gate electrode (EL1). A sidewall of the first portion (VCP1) of the vertical channel pattern (VCP) may be surrounded by a data storage pattern (DSP). The top surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located at a higher level than the top surface of the first gate electrode (EL1). More specifically, the top surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located between the top surface of the first gate electrode (EL1) and the bottom surface of the lowest one of the second gate electrodes (EL2). The bottom surface of the first portion VCP1 of the vertical channel pattern VCP may be located at a lower level than the top surface of the substrate SUB (that is, the bottom surface of the lowest one of the interlayer insulating layers ILD). A portion of the first portion (VCP1) of the vertical channel pattern (VCP) may overlap the first gate electrode (EL1) in the horizontal direction. Hereinafter, the horizontal direction means any direction extending on a plane parallel to the first direction D1 and the second direction D2.

The second part (VCP2) of the vertical channel pattern (VCP) may extend from the top surface of the first part (VCP1) in the third direction (D3). The second part (VCP2) of the vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the vertical semiconductor pattern (VSP) and may correspond to the second gate electrodes (EL2). Accordingly, the second part (VCP2) of the vertical channel pattern (VCP), together with the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP), as described above, may form memory cells. .

The top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be substantially coplanar with the top surface of the vertical semiconductor pattern (VSP). The top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be located at a higher level than the top surface of the uppermost one of the second gate electrodes (EL2). More specifically, the top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be located between the top and bottom surfaces of the third gate electrode (EL3).

The vertical channel pattern (VCP) is a component that transfers charges or holes to the data storage pattern (DSP), and may be formed of single crystalline silicon or polysilicon to form a channel or be boosted by an applied voltage. However, without being limited or limited thereto, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material that can block, suppress, or minimize leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material containing at least one of In, Zn, or Ga with excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and at least one of the gate electrodes (EL1, EL2, EL3) The characteristics of any one transistor (for example, threshold voltage distribution and speed of program/read operations) can be improved, and as a result, the electrical characteristics of the three-dimensional memory can be improved.

In particular, the vertical channel pattern (VCP) is formed of a low-concentration p-doped material or a low-concentration n-doped material as well as single crystalline silicon or polysilicon for the channel formation operation of the dual junction (DJ) described later. It can be.

Although the vertical channel pattern (VCP) has been described as having a structure including a first part (VCP1) and a second part (VCP2), it is not limited or limited thereto and may have a structure excluding the first part (VCP1). . For example, the vertical channel pattern (VCP) is provided between the vertical semiconductor pattern (VSP) and the data storage pattern (DSP) formed to extend to the substrate (SUB) and is formed to extend to the substrate (SUB) to contact the substrate (SUB). You can. In this case, the bottom surface of the vertical channel pattern (VCP) may be located at a lower level than the top surface of the substrate (SUB) (the bottom surface of the lowest one of the interlayer dielectric layers (ILD)), and the top surface of the vertical channel pattern (VCP) may be located at a lower level than the top surface of the substrate (SUB). It can be substantially coplanar with the top surface of the pattern (VSP).

The vertical semiconductor pattern (VSP) may be surrounded by the second portion (VCP2) of the vertical channel pattern (VCP). The upper surface of the vertical semiconductor pattern (VSP) may contact the dual junction (DJ), and the lower surface of the vertical semiconductor pattern (VSP) may contact the first portion (VCP1) of the vertical channel pattern (VCP). The vertical semiconductor pattern VSP may be spaced apart from the substrate SUB in the third direction D3. In other words, the vertical semiconductor pattern VSP may be electrically floating from the substrate SUB.

The vertical semiconductor pattern (VSP) may be formed of a material that helps diffusion of charges or holes in the vertical channel pattern (VCP). More specifically, the vertical semiconductor pattern (VSP) can be formed of a material with excellent charge and hole mobility. For example, the vertical semiconductor pattern (VSP) may be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material that is not doped with an impurity, or a polycrystalline semiconductor material. For a more specific example, the vertical semiconductor pattern VSP may be formed of polysilicon doped with the same first conductivity type impurity (eg, P- impurity) as the substrate SUB. In other words, the vertical semiconductor pattern (VSP) can improve the speed of memory operation by improving the electrical characteristics of 3D flash memory.

Although it has been described above that the vertical channel structures (VS) include the vertical semiconductor pattern (VSP), the present invention is not limited or limited thereto and the vertical semiconductor pattern (VSP) may be omitted.

Additionally, each of the vertical channel structures VS may not only have a structure omitting the vertical semiconductor pattern VSP, but may also have a structure including a back gate BG (not shown). In this case, the back gate (BG) may be in contact with at least a portion of the back gate (BG) surrounded by the vertical channel pattern (VCP), and may be a component that applies a voltage to the vertical channel pattern (VCP) for a memory operation.

Referring again to FIG. 2, the vertical channel structures (VS) include an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT). ) may correspond to the channels.

As shown in FIG. 4A, a dual junction (DJ) may be provided on the top surface of the vertical channel pattern (VCP). That is, the dual junction (DJ) is located at the top of each of the vertical channel structures (VS) and connected to the top of the vertical channel pattern (VCP), so that it can operate as a drain junction (Drain junction).

A dual junction (DJ) may have a dual structure, each doped with different types of impurities. More specifically, the dual junction (DJ) may have a dual structure consisting of an N+ doped N+ junction and a P+ doped P+ junction.

The N+ junction and P+ junction of the dual junction (DJ) are the target memory cells that are the target of the memory operation among the gate electrodes EL1, EL2, and EL3 (more specifically, the second gate electrodes EL2) during the memory operation. In response to the voltage applied to the selected gate electrode (Sel EL) corresponding to , it may be selectively activated to form a channel in the vertical channel pattern (VCP). For example, the N+ junction forms an N-type channel in the vertical channel pattern (VCP) in response to a positive voltage applied to the selected gate electrode (Sel EL), thereby recording “1” data (program operation). can be performed. For another example, the P+ junction forms a P-type channel in the vertical channel pattern (VCP) in response to a negative voltage applied to the selected gate electrode (Sel EL), thereby performing a write operation (erase operation) that records “0” data. ) can be performed. That is, the N-type channel can be formed to extend vertically to connect to the N+ junction, and the P-type channel can also be formed to extend vertically to connect to the P+ junction.

At this time, the N+ junction and P+ junction of the dual junction (DJ) may have a structure that is symmetrical to each other so as to have the same contact area with respect to the vertical channel pattern (VCP). For example, the N+ junction and the P+ junction may be formed to symmetrically bisect the space located above the vertical channel pattern (VCP) as shown in the drawing. However, the dual junction (DJ) is not limited or limited thereto, and may include an N+ junction and a P+ junction configured to have different contact areas with respect to the vertical channel pattern (VCP).

In this way, the contact area for the vertical channel pattern (VCP) of each of the N+ junction and P+ junction in the dual junction (DJ) varies with the vertical channel pattern (VCP) according to the voltage applied through the gate electrodes (EL1, EL2, and EL3). It can be adjusted and determined based on the operation of forming an N-type channel and the operation of forming a P-type channel. For example, the speed of forming an N-type channel in the vertical channel pattern (VCP) in response to a positive voltage applied to the selected gate electrode (Sel EL) and the negative voltage applied to the selected gate electrode (Sel EL) In response, the contact area for each vertical channel pattern (VCP) of the N+ junction and P+ junction is adjusted and adjusted so that the speed of forming a P-type channel in the vertical channel pattern (VCP) is satisfied. can be decided.

The top surface of the dual junction (DJ) may be substantially coplanar with the top surface of each of the stacked structures (ST) (that is, the top surface of the uppermost one of the interlayer dielectric layers (ILD)). The lower surface of the dual junction (DJ) may be located at a lower level than the upper surface of the third gate electrode (EL3). More specifically, the lower surface of the dual junction (DJ) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the dual junction DJ may overlap the third gate electrode EL3 in the horizontal direction.

A contact plug (CPG) connected to a bit line plug (BLPG) may be placed on top of the dual junction (DJ). That is, the dual junction (DJ) can be connected to the bit line plug (BLPG) through the contact plug (CPG).

The dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG), meaning that the cross-sectional area of the bit line plug (BLPG) applies voltage to each of the N+ junction and P+ junction of the dual junction (DJ). This is because it has an insufficient size (not enough to provide current for each of the N+ junction and P+ junction of the dual junction (DJ)). Therefore, the contact plug (CPG) has a sufficient area to apply voltage to each of the N+ junction and P+ junction of the dual junction (DJ) (capable of providing current to each of the N+ junction and P+ junction of the dual junction (DJ)). (sufficient area).

In addition, the reason why the dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG) is to reduce the contact resistance between the dual junction (DJ) and the bit line plug (BLPG). Accordingly, the contact plug (CPG) may be formed of a material that can reduce contact resistance between the dual junction (DJ) and the bit line plug (BLPG). For example, the contact plug (CPG) may be formed of a semiconductor or conductive material doped with impurities. For example, the contact plug (CPG) may contain impurities (more precisely, a second conductivity type (e.g., N-) different from the first conductivity type (e.g., P-) than the substrate (SUB) or vertical semiconductor pattern (VSP). Impurities) may be formed from a doped semiconductor material.

Above, it has been described that the dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG), but this is not limited or limited and the contact plug (CPG) may be omitted. In this case, the bit line plug (BLPG) has sufficient area to apply voltage to each of the N+ junction and P+ junction of the dual junction (DJ) (to provide current to each of the N+ junction and P+ junction of the dual junction (DJ)). It is composed of a sufficient area to apply voltage or provide current directly to the dual junction (DJ).

A dual junction (DJ) may also be provided below the vertical channel pattern (VCP) as shown in FIG. 4B. That is, the dual junction (DJ) is located at the bottom of each of the vertical channel structures (VS) and connected to the bottom of the vertical channel pattern (VCP), so that it can operate as a source junction. Since the dual junction (DJ) operating as a source junction also has the same structure as the dual junction (DJ) operating as a drain junction described above, a detailed description thereof will be omitted. A source region (SR) may be formed below the dual junction (DJ), which operates as a source junction in each of the vertical channel structures (VS). The source regions SR of each of the vertical channel structures VS are connected to each other through separate wiring (not shown) in the substrate SUB, and thus may correspond to the common source line CSL of FIG. 2 . However, without being limited or limited thereto, the source region SR of each of the vertical channel structures VS may have a structure that is not connected to each other so that each vertical channel structure VS operates independently.

Additionally, when a dual junction (DJ) is located at the bottom of each of the vertical channel structures (VS), the source region (SR) may be omitted. In this case, the dual junction (DJ), which operates as a source junction in each of the vertical channel structures (VS), is connected to each other through a separate wiring (not shown) in the substrate (SUB), so that the common source of FIG. 2 It may correspond to line (CSL). However, without being limited or limited thereto, the dual junction (DJ) operating as a source junction in each of the vertical channel structures (VS) may have a structure that is not connected to each other so that each vertical channel structure (VS) operates independently.

When the dual junction (DJ) is located only at the top of each of the vertical channel structures (VS), a source region (SR) is formed under the lower surface of the vertical channel pattern (VCP) as shown in FIG. 4A. You can. The source regions SR of each of the vertical channel structures VS are connected to each other through separate wiring (not shown) in the substrate SUB, and thus may correspond to the common source line CSL of FIG. 2 . However, without being limited or limited thereto, the source region SR of each of the vertical channel structures VS may have a structure that is not connected to each other so that each vertical channel structure VS operates independently.

In addition, when the dual junction (DJ) is located only on the top of each of the vertical channel structures, each of the vertical channel structures (VS) has a source area ( It may also have a source free structure with SR) omitted.

In addition, although not shown in the drawing, a separation trench TR extending in the first direction D1 may be provided between adjacent stacked structures ST. The common source region (CSR) may be provided inside the substrate (SUB) exposed by the isolation trench (TR). The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with a second conductivity type impurity (eg, N+ impurity). The common source region (CSR) may correspond to the common source line (CSL) of FIG. 2.

A common source plug (CSP) may be provided in the isolation trench (TR). The common source plug (CSP) may be connected to the common source region (CSR). The top surface of the common source plug (CSP) may be substantially coplanar with the top surface of each of the stacked structures (ST) (that is, the top surface of the uppermost one of the interlayer insulating layers (ILD)). The common source plug (CSP) may have a plate shape extending in the first direction (D1) and the third direction (D3). At this time, the common source plug (CSP) may have a shape whose width in the second direction (D2) increases as it moves toward the third direction (D3).

Insulating spacers (SP) may be interposed between the common source plug (CSP) and the stacked structures (ST). Insulating spacers SP may be provided between adjacent stacked structures ST to face each other. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material with a low dielectric constant.

A capping insulating layer (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating layer (CAP) may cover the top surface of the uppermost one of the interlayer insulating layers (ILD), the top surface of the dual junction (DJ), and the top surface of the common source plug (CSP). The capping insulating film (CAP) may be formed of an insulating material different from the interlayer insulating films (ILD). A contact plug (CPG) and a bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug BLPG may have a shape whose width in the first direction D1 and the second direction D2 increases as it moves toward the third direction D3.

A bit line (BL) may be provided on the capping insulating film (CAP) and the bit line contact plug (BLPG). The bit line BL corresponds to one of the plurality of bit lines BL0, BL1, and BL2 shown in FIG. 2 and may be formed to extend along the second direction D2 using a conductive material. The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1, EL2, and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through a bit line contact plug (BLPG). Here, the fact that the bit line (BL) is connected to the vertical channel structures (VS) may mean that it is connected to the vertical channel pattern (VCP) through the dual junction (DJ) included in the vertical channel structures (VS). .

As described above, as the columns of the three vertical channel structures (VS) pass through the stacked structures (ST), the three vertical channel structures (VS) located in the same row are connected to the bit line located on the same plane. Each bit line contact plug (BLPG) may have a structure that is offset from each other so as to be connected to each of the fields BL0, BL1, and BL2. For example, as shown in FIG. 3, the first vertical channel structure VS1 may include a bit line contact plug BLPG that is biased in the first direction D1 on a plane to be connected to the bit line BL0, The second vertical channel structure (VS2) may include a bit line contact plug (BLPG) located at the center of the plane so as to be connected to the bit line (BL1), and the third vertical channel structure (VS3) may include a bit line (BL2). It may include a bit line contact plug (BLPG) that is biased in a direction opposite to the first direction (D1) on a plane so as to be connected to.

The three-dimensional memory according to one embodiment is not limited or limited to the described structure, and depending on the implementation example, it may include a vertical channel pattern (VCP), a dual junction (DJ), a data storage pattern (DSP), and gate electrodes (EL1, EL2). , EL3), can be implemented in various structures provided that it includes a bit line (BL).

The operation method and manufacturing method for the three-dimensional memory having a structure including a dual junction (DJ) as described above will be described below.

FIG. 5 is a flow chart showing a memory operation method of a three-dimensional memory according to an embodiment, and FIGS. 6A to 6B show the structure of a three-dimensional memory to explain the memory operation method of the three-dimensional memory shown in FIG. 5. It is a cross-sectional view, and FIGS. 7A and 7B are diagrams for explaining an improved memory window of a three-dimensional memory according to an embodiment, and FIG. 8 is a diagram for explaining a read operation of a three-dimensional memory according to an embodiment. 9A to 9B are diagrams showing a memory window to explain an erase operation of a three-dimensional memory according to an embodiment.

Hereinafter, the memory operation method described is assumed to be performed by a three-dimensional memory having the structure described above with reference to FIGS. 2 to 4.

Referring to FIG. 5, in step S510, the three-dimensional memory corresponds to the target memory cell that is the target of the memory operation among the gate electrodes EL1, EL2, and EL3 (more precisely, the second gate electrode EL2). A voltage can be applied to the selected gate electrode (Sel EL).

Accordingly, in step S520, the three-dimensional memory, in response to the voltage applied to the selected gate electrode (Sel EL), includes an N+ junction included in the dual junction (DJ) formed at the top of each of the vertical channel structures (VS), and As one of the P+ junctions is selectively activated, a memory operation can be performed by forming a channel in a vertical channel pattern (VCP).

For example, as shown in FIG. 6A, the 3D memory is generated by applying a positive voltage to the gate electrode (Sel EL) selected in step S510, through the N+ junction of the dual junction (DJ) in step S520. A recording operation can be performed by forming an N-type channel in a vertical channel pattern (VCP). For a more specific example, the 3D memory applies a positive voltage to the gate electrode (Sel EL) selected in step S510, thereby creating a vertical channel pattern (VCP) through the N+ junction of the dual junction (DJ) in step S520. ), a recording operation (program operation) of recording “1” data can be performed by forming an N-type channel. Accordingly, the N-type channel may be formed to extend vertically to connect to the N+ junction.

For another example, the 3D memory applies a negative voltage to the gate electrode (Sel EL) selected in step S520, as shown in FIG. 6B, and connects the P+ junction of the dual junction (DJ) in step S520. A recording operation can be performed by forming a P-type channel in the vertical channel pattern (VCP). For a more specific example, the three-dimensional memory records data of "0" by applying a negative voltage to the gate electrode (Sel EL) selected in step S520 and forming a P-type channel in step S520. An operation (erase operation) can be performed. Accordingly, the P-type channel may be formed to extend vertically to connect to the P+ junction.

At this time, in step S520, the three-dimensional memory can perform a memory operation by forming a channel in the vertical channel pattern (VCP) using a dual junction (DJ) formed at the bottom of each of the vertical channel structures (VS). there is. Since using the dual junction (DJ) formed at the bottom of each of the vertical channel structures (VS) is done through the same process as using the dual junction (DJ) formed at the top of each of the vertical channel structures (VS), Detailed description will be omitted.

As such, the three-dimensional memory according to one embodiment implements a write operation (erase operation) that forms a P-type channel by applying a negative voltage to the selected gate electrode (Sel EL) based on a dual junction (DJ), By supporting random access, high-speed memory operation is possible.

Additionally, the three-dimensional memory can implement multi-valued memory by adjusting the value of the voltage applied to the selected gate electrode (Sel EL) to a plurality of various values. In particular, since 3D memory can select the value of the voltage applied to the selected gate electrode (Sel EL) within the positive as well as negative range, the existing 3D NAND flash memory as shown in FIG. 7A It is possible to implement multi-value conversion of 5 bits or more as shown in FIG. 7B, which is more improved than multi-value conversion of 4 bits. In other words, the three-dimensional memory is multi-valued according to the adjusted positive voltage value and the adjusted negative voltage value by adjusting the value of the positive voltage and negative voltage applied to the selected gate electrode (Sel EL). A recording operation (program operation) of the specified value can be performed.

When the value of the voltage applied to the selected gate electrode (Sel EL) is selected within the positive and negative ranges, the read voltage (V _read ) and pass voltage (V _pass ) applied during the read operation are shown in FIG. 8 As shown in

Additionally, in this case, the erase operation may be performed on a page-by-page or block-by-block basis. Specifically, the 3D memory can perform an erase operation in two steps as shown in FIGS. 9A and 9B. For example, three-dimensional memory has the first stage of moving memory cells programmed with negative voltage around the threshold voltage (V _th ) of 0V and the first step of moving memory cells programmed with positive voltage around the threshold voltage (V _th ) of 0V. The erase operation can be performed in two steps: moving to . Accordingly, the program operation may be performed by applying a positive voltage or a negative voltage, as described above.

As shown in Figure 9c, the erase operation performed in two steps requires an erase voltage (V _erase ) of 25V or more to move the threshold voltage (V _th ) of +6V to -4V in the existing 3D NAND flash memory. Unlike the erase operation that is applied, which takes several ms, a voltage of +/- 20V or less is applied to move +6V to the threshold voltage (V _th ) of 0V and -6V to the threshold voltage (V _th ) of 0V. Therefore, it has the advantage of taking less time than a few ms.

The manufacturing method described below is for manufacturing a three-dimensional memory with the structure described above with reference to FIGS. 2 to 4, and is assumed to be performed by an automated and mechanized manufacturing system.

Referring to FIG. 10, in step S1010, the manufacturing system can prepare a semiconductor structure (SEMI-STR). Here, the semiconductor structure (SEM-STR) includes gate electrodes (EL1, EL2, EL3) extending in the horizontal direction on the substrate (SUB) and stacked while being spaced apart in the vertical direction; and vertical channel structures VS extending in the vertical direction and penetrating the gate electrodes EL1, EL2, and EL3. That is, the semiconductor structure (SEMI-STR) may include the stacked structures (ST) and vertical channel structures (VS) of the structures described above with reference to FIGS. 2 to 4. However, a dual junction (DJ) is not formed in the vertical channel structures (VS).

Here, the manufacturing system can prepare a semiconductor structure (SEMI-STR) in which a source region is formed at the bottom of each of the vertical channel structures (VS). Alternatively, the manufacturing system may prepare a semiconductor structure having a source-free structure in which the source region is omitted at the bottom of each of the vertical channel structures (VS).

As described above, when a dual junction is formed at the bottom of each of the vertical channel structures (VS), in step S1010, the manufacturing system produces a semiconductor structure (SEMI) in which a dual junction is formed at the bottom of each of the vertical channel structures (VS). -STR) can be prepared.

In step S1020, the manufacturing system may place a first mask pattern (MASK 1) that covers a portion of the upper surface of each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).

In step S1030, the manufacturing system uses the first mask pattern (MASK 1) to apply N+ doped N+ to the remaining area of the upper surface that is not obscured by the first mask pattern (MASK 1) in each of the vertical channel structures (VS). A junction can be formed.

In step S1040, the manufacturing system may place a second mask pattern (MASK 2) that covers the remaining upper surface area of each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).

In step S1050, the manufacturing system uses the second mask pattern (MASK 2) to apply P+ doped P+ to a portion of the upper surface that is not obscured by the second mask pattern (MASK 2) in each of the vertical channel structures (VS). A P+ junction can be formed.

Here, the first mask pattern (MASK 1) and the second mask pattern (MASK 2) each point to symmetrical areas of the same area so that the N+ junction and P+ junction in each of the vertical channel structures (VS) have a symmetrical structure. It can be configured and arranged as follows.

In this way, through steps S1010 to S1050, a dual junction (DJ) including an N+ junction and a P+ junction may be formed in each of the vertical channel structures (VS).

The manufacturing method in which the P+ junction is formed after the N+ junction is formed has been described above, but the manufacturing method is not limited or limited thereto and the N+ junction may be formed after the P+ junction is formed. In this case, steps S1020 to S1030 are performed after steps S1040 to S1050, so that the P+ junction can be formed before the N+ junction.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims

Gate electrodes extending in the horizontal direction on the substrate and spaced apart in the vertical direction are stacked; and

Vertical channel structures extend through the gate electrodes and extend in the vertical direction - each of the vertical channel structures includes a vertical channel pattern and a data storage pattern, and different types of impurities are placed on top of each of the vertical channel structures. A dual junction with a dual structure doped with

3D memory containing.
According to paragraph 1,

The dual junction is,

A three-dimensional memory comprising an N+ doped N+ junction and a P+ doped P+ junction.
According to paragraph 2,

The N+ junction and the P+ junction are,

A three-dimensional memory characterized by having a structure that is symmetrical to each other so as to have the same contact area with respect to the vertical channel pattern.
According to paragraph 2,

Either of the N+ junction and the P+ junction,

During a memory operation, a three-dimensional device is selectively activated in response to a voltage applied to a selected gate electrode corresponding to a target memory cell that is the target of the memory operation among the gate electrodes to form a channel in the vertical channel pattern. Memory.
According to paragraph 4,

The N+ junction is,

A three-dimensional memory characterized in that an N-type channel is formed in the vertical channel pattern in response to a positive voltage applied to the selected gate electrode.
According to clause 5,

The N-type channel is,

A three-dimensional memory, characterized in that it extends in the vertical direction to connect to the N+ junction.
According to paragraph 4,

The P+ junction is,

A three-dimensional memory characterized in that a P-type channel is formed in the vertical channel pattern in response to a negative voltage applied to the selected gate electrode.
In clause 7,

The P-type channel is,

A three-dimensional memory, characterized in that it extends in the vertical direction to connect to the P+ junction.
According to paragraph 1,

The dual junction is,

A three-dimensional memory characterized by being connected to a bit line plug through a contact plug placed at the top.
According to paragraph 1,

The dual junction is,

A three-dimensional memory, characterized in that formed at the bottom of each of the vertical channel structures.
According to paragraph 1,

At the bottom of each of the vertical channel structures,

A three-dimensional memory characterized by the formation of a source region.
According to paragraph 1,

The three-dimensional memory is,

A three-dimensional memory characterized in that it has a source free structure with a source area omitted at the bottom of each of the vertical channel structures.
Gate electrodes extending in the horizontal direction on the substrate and spaced apart in the vertical direction are stacked; and vertical channel structures penetrating the gate electrodes and extending in the vertical direction - each of the vertical channel structures includes a vertical channel pattern and a data storage pattern, and different types of structures are located on top of each of the vertical channel structures. In the memory operation method of a three-dimensional memory, including the formation of dual junctions of a dual structure each doped with impurities,

applying a voltage to a selected gate electrode corresponding to a target memory cell that is a target of a memory operation among the gate electrodes; and

In response to the voltage applied to the selected gate electrode, one of the N+ junction and the P+ junction included in the dual junction is selectively activated to form a channel in the vertical channel pattern to perform a memory operation.

A memory operation method of a three-dimensional memory including.
According to clause 13,

The authorizing step is,

Applying a positive voltage to the selected gate electrode

Including,

The step of performing the memory operation is,

In response to a positive voltage applied to the selected gate electrode, forming an N-type channel in the vertical channel pattern through the N+ junction to perform a write operation.

A memory operation method of a three-dimensional memory comprising:
According to clause 14,

The authorizing step is,

Adjusting the value of positive voltage applied to the selected gate electrode

Including,

The step of performing the memory operation is,

Performing a recording operation of a multi-valued value according to the value of the adjusted positive voltage.

A memory operation method of a three-dimensional memory comprising:
According to clause 13,

The authorizing step is,

Applying a negative voltage to the selected gate electrode

Including,

The step of performing the memory operation is,

In response to a negative voltage applied to the selected gate electrode, forming a P-type channel in the vertical channel pattern through the P+ junction to perform a write operation.

A memory operation method of a three-dimensional memory comprising:
According to clause 16,

The authorizing step is,

Adjusting the value of the negative voltage applied to the selected gate electrode

Including,

The step of performing the memory operation is,

Performing a recording operation of a multi-valued value according to the adjusted negative voltage value.

A memory operation method of a three-dimensional memory comprising:
According to clause 13,

The step of performing the memory operation is,

performing a memory operation by forming a channel in the vertical channel pattern by selectively activating one of the N+ junction and the P+ junction included in the dual junction formed at the bottom of each of the vertical channel structures.

A memory operation method of a three-dimensional memory further comprising:
In the method of manufacturing a three-dimensional memory including dual junctions of a dual structure each doped with different types of impurities,

Gate electrodes extending in the horizontal direction on the substrate and spaced apart in the vertical direction are stacked; and preparing a semiconductor structure including vertical channel structures extending in the vertical direction and penetrating the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern.

disposing a first mask pattern on the semiconductor structure to cover a portion of a top surface of each of the vertical channel structures;

Using the first mask pattern, forming an N+ doped N+ junction in a remaining area of the upper surface of each of the vertical channel structures that is not obscured by the first mask pattern;

disposing a second mask pattern on the semiconductor structure to cover the remaining upper surface area of each of the vertical channel structures; and

Using the second mask pattern, forming a P+ doped P+ junction in a portion of the upper surface that is not obscured by the second mask pattern in each of the vertical channel structures.

A method of manufacturing a three-dimensional memory comprising.
According to clause 19,

The first mask pattern and the second mask pattern are,

A method of manufacturing a three-dimensional memory, characterized in that each of the vertical channel structures covers a symmetrical area of the same area so that the N+ junction and the P+ junction have a structure that is symmetrical to each other.
According to clause 19,

The step of preparing the semiconductor structure is,

A method of manufacturing a three-dimensional memory, characterized in that the step of preparing the semiconductor structure in which the dual junction is formed at the bottom of each of the vertical channel structures.
According to clause 19,

The step of preparing the semiconductor structure is,

A method of manufacturing a three-dimensional memory, characterized in that the step of preparing the semiconductor structure in which a source region is formed at the bottom of each of the vertical channel structures.
According to clause 19,

The step of preparing the semiconductor structure is,

A method of manufacturing a three-dimensional memory, characterized in that the step of preparing the semiconductor structure having a source free structure in which a source region is omitted at the bottom of each of the vertical channel structures.