WO2024060758A1 - Réseau de mémoire et son procédé de fabrication, mémoire, dispositif électronique et procédé de lecture-écriture - Google Patents

Réseau de mémoire et son procédé de fabrication, mémoire, dispositif électronique et procédé de lecture-écriture Download PDF

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Publication number
WO2024060758A1
WO2024060758A1 PCT/CN2023/103514 CN2023103514W WO2024060758A1 WO 2024060758 A1 WO2024060758 A1 WO 2024060758A1 CN 2023103514 W CN2023103514 W CN 2023103514W WO 2024060758 A1 WO2024060758 A1 WO 2024060758A1
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WIPO (PCT)
Prior art keywords
layer
electrode
hole
storage
channel
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PCT/CN2023/103514
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English (en)
Chinese (zh)
Inventor
景蔚亮
孙莹
黄凯亮
王正波
廖恒
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华为技术有限公司
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Publication of WO2024060758A1 publication Critical patent/WO2024060758A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Definitions

  • Embodiments of the present application relate to the technical field of storage devices, and specifically relate to a storage array and a manufacturing method thereof, a memory, an electronic device, and a reading and writing method.
  • a storage array includes a substrate and a storage string disposed on the substrate.
  • the storage string includes a plurality of storage transistors arranged sequentially in a direction perpendicular to the substrate.
  • the plurality of storage transistors are connected in series, and each storage transistor is used for data storage.
  • multiple transistors in the memory string are connected in series. When data is read, all transistors in the memory string need to be in a conductive state, resulting in slower data reading.
  • Embodiments of the present application provide a storage array, a manufacturing method thereof, a memory, an electronic device, and a reading and writing method to solve the problem of slow data reading in the storage array.
  • embodiments of the present application provide a memory array, including a substrate and a stacked structure provided on the substrate.
  • the stacked structure includes a plurality of device layers arranged in a stack, and each device layer includes a first electrode layer arranged in a stack.
  • a first isolation layer and a second electrode layer, the first isolation layer is provided between the first electrode layer and the second electrode layer; the first electrode layers in each device layer are all electrically connected.
  • the stacked structure also includes a gate post.
  • the stacked structure is provided with a through hole, the through hole penetrates each stacked structure, and the gate post is inserted into the through hole.
  • the first electrode layer in each device layer serves as the first electrode of a storage transistor
  • the electrode plate in the device layer serves as the second electrode of the corresponding storage transistor
  • the gate pillar serves as the gate electrode of the corresponding storage transistor.
  • the storage transistor is used for Store data.
  • each first electrode layer is electrically connected, so the gate pillar and the memory transistor formed by each device layer are connected in parallel.
  • power can be supplied to the first electrode layer and the gate pillar, that is, the gate
  • Each memory transistor formed by the pole and each device layer is in a state where data can be read.
  • the data in the memory transistor corresponding to the second electrode layer can be read through the second electrode layer, without the need to connect the gate pillar and Each storage transistor formed in each device layer is in an on state, which improves the data reading speed.
  • each device layer further includes a dielectric layer and a channel layer
  • the through hole includes a sub-through hole that penetrates each device layer.
  • the dielectric layer is arranged on the gate column corresponding to the sub-through hole, the channel layer covers the hole wall of the sub-through hole, and the channel layer is in contact with the dielectric layer, the first electrode layer and the second electrode layer. Through the above arrangement, the dielectric layer can store electrons.
  • the dielectric layer covers the entire gate pillar corresponding to the sub-via hole, that is, the dielectric layer is in a tube shape. Such an arrangement can increase the area of the dielectric layer, thereby improving the ability of the dielectric layer to store electrons.
  • the channel layer covers the entire hole wall of the through hole, that is, the channel layer is continuously arranged along the hole wall of the through hole, and the channel layer covers the entire hole wall of the through hole (the channel layer is tubular).
  • Such an arrangement can increase the contact area between the channel layer and the first electrode layer, the second electrode layer and the dielectric layer, that is, increase the area of the conductive channel formed by the channel layer and the dielectric layer, so as to increase the turn-on voltage of the storage transistor, thereby improving the performance of the storage array.
  • each device layer further includes a dielectric layer and a channel layer
  • the through hole includes a sub-via hole that penetrates each device layer
  • the dielectric layer is disposed corresponding to the hole wall of the sub-via hole.
  • the gate pillar there is a gap between the first isolation layer and the hole wall of the sub-via hole, the gap is connected with the sub-via hole
  • the channel layer includes a first channel layer arranged in the gap, the first channel layer and the dielectric layer , the first electrode layer and the second electrode layer are all in contact.
  • Such an arrangement can prevent the conductive channel from occupying the space in the through hole, thereby increasing the area of the dielectric layer and improving the electron storage capacity of the dielectric layer.
  • the channel layer further includes a second channel layer disposed on a surface of the first isolation layer facing the second electrode layer, the second channel layer being in contact with the first channel layer .
  • a second channel layer disposed on a surface of the first isolation layer facing the second electrode layer, the second channel layer being in contact with the first channel layer .
  • the channel layer further includes a third channel layer disposed on a surface of the first isolation layer facing the first electrode layer, the third channel layer being in contact with the first channel layer .
  • Such an arrangement can increase the contact area between the channel layer and the first electrode layer, thereby reducing the resistance between the channel layer and the first electrode layer.
  • each device layer further includes a dielectric layer and a channel layer
  • the through hole includes a sub-through hole that penetrates each device layer; there is a gap between the first isolation layer and the hole wall of the sub-through hole, the gap is connected to the through hole, and an extension portion is provided on the gate column, and the extension portion is provided in the gap.
  • the extension portion can be made of the same material as the gate column, so that the extension portion and the gate column can form an integrated structure to reduce the resistance between the extension portion and the gate column.
  • the dielectric layer includes a first dielectric layer and a second dielectric layer.
  • the first dielectric layer is arranged on the gate pillar corresponding to the hole wall of the sub-via hole, and the second dielectric layer wraps around the extension part.
  • the first dielectric layer and the second dielectric layer are in contact.
  • the channel layer includes a first channel layer and a second channel layer.
  • the first channel layer is arranged between the hole wall of the sub-via hole and the first dielectric layer.
  • the second channel layer is arranged between the second dielectric layer and the gap. between side walls. The first channel layer and the second channel layer are in contact.
  • the dielectric layers in adjacent device layers are in contact, that is, each dielectric layer is continuously arranged in a direction parallel to the center line of the gate pillar. Such arrangement can increase the size of the dielectric layer. area, thereby improving the storage capacity of electrons.
  • the stacked structure further includes a second isolation layer.
  • One second isolation layer is stacked between adjacent device layers. Through the second isolation layer Layers provide isolation between adjacent device layers.
  • the second isolation layer is in contact with the dielectric layer, that is, the channel layer on adjacent sub-via holes is isolated by the second isolation layer to avoid The channel layers influence each other.
  • the second electrode layer includes a plurality of second electrode lines spaced apart in a direction parallel to the substrate; the through hole penetrates one second electrode line; the stacked structure further includes a plurality of second electrode lines that penetrate through each device layer.
  • the connection hole, the projection of the connection hole on the substrate is located between the projections of two adjacent second electrode lines on the substrate in the same device layer; the connection hole is filled with a conductor, and the conductor is in contact with each first electrode layer.
  • an embodiment of the present application provides a storage array, including a storage string, a first electrode line, and a plurality of second electrode lines, wherein the storage string includes a plurality of storage transistors, and the gates of the storage transistors are electrically connected.
  • the first electrode line is electrically connected to the first electrode in each storage transistor in the storage string.
  • a second electrode line is electrically connected to the second electrode of a storage transistor in the storage string, and data can be written into the corresponding storage transistor or read from the corresponding storage transistor through the second electrode line.
  • the memory array provided in this embodiment can supply power to the first electrode line and the gate of each storage transistor in the memory string when reading data, so that each storage transistor in the memory string is in a state where data can be read. , and then the data in the storage transistor corresponding to the second electrode line can be read through the second electrode line, without turning on each storage transistor in the storage string, which improves the data reading speed.
  • an embodiment of the present application provides a memory, including the storage array in the above embodiment and a controller, and the controller is electrically connected to the storage array.
  • the stacked structure in the memory array includes a plurality of stacked device layers.
  • Each device layer includes a stacked first electrode layer, a first isolation layer and a second electrode layer.
  • the first isolation layer Disposed between the first electrode layer and the second electrode layer; the first electrode layers in each device layer are all electrically connected.
  • the stacked structure also includes a gate pillar.
  • the stacked structure is provided with a through hole, the through hole penetrates each stacked structure, and the gate pillar is inserted into the through hole.
  • the first electrode layer in each device layer serves as the first electrode of a memory transistor
  • the second electrode layer in the device layer serves as the second electrode of the corresponding memory transistor
  • the gate pillar serves as the opposite electrode.
  • the gate of the storage transistor should be used for storing data.
  • each first electrode layer is electrically connected, so the gate pillar and the memory transistor formed by each device layer are connected in parallel.
  • power can be supplied to the first electrode layer and the gate pillar, that is, the gate
  • Each memory transistor formed by the pole and each device layer is in a state where data can be read.
  • the data in the memory transistor corresponding to the second electrode layer can be read through the second electrode layer, without the need to connect the gate pillar and Each storage transistor formed in each device layer is in an on state, which improves the data reading speed.
  • embodiments of the present application provide an electronic device, including the memory in the above embodiment and a circuit board, and the memory is disposed on the circuit board.
  • the stacked structure in the storage array includes a plurality of device layers arranged in a stack.
  • Each device layer includes a first electrode layer, a first isolation layer and a second electrode layer arranged in a stack.
  • the first isolation layer Disposed between the first electrode layer and the second electrode layer; the first electrode layers in each device layer are all electrically connected.
  • the stacked structure also includes a gate pillar.
  • the stacked structure is provided with a through hole, the through hole penetrates each stacked structure, and the gate pillar is inserted into the through hole.
  • the first electrode layer in each device layer serves as the first electrode of a storage transistor
  • the second electrode layer in the device layer serves as the second electrode of the corresponding storage transistor
  • the gate pillar serves as the gate electrode of the corresponding storage transistor
  • the storage transistor Used for data storage
  • each first electrode layer is electrically connected, so the gate pillar and the memory transistor formed by each device layer are connected in parallel.
  • power can be supplied to the first electrode layer and the gate pillar, that is, the gate
  • Each memory transistor formed by the pole and each device layer is in a state where data can be read.
  • the data in the memory transistor corresponding to the second electrode layer can be read through the second electrode layer, without the need to connect the gate pillar and Each storage transistor formed in each device layer is in an on state, which improves the data reading speed.
  • embodiments of the present application also provide a reading and writing method for a storage array.
  • the storage array includes a storage string.
  • the storage string includes a plurality of storage transistors. Reading data in the storage transistors includes: storing data in each storage string. A first voltage is applied to the gate electrode of the transistor and the first electrode of each storage transistor; the current of the second electrode of the storage transistor is obtained; and the data stored in the storage transistor is obtained through the current.
  • each storage transistor in the storage string is in a state where data can be read, and the data stored in the storage transistor can be read through the second electrode corresponding to the storage transistor, without the need for each storage transistor in the storage string to be in an on state. , improving the data reading speed.
  • writing data within the storage transistor includes:
  • a third voltage is applied to the gate electrode of each storage transistor in the storage string and the second electrode of the storage transistor to which data is to be written, and the third voltage is less than the second voltage, so as to write into the storage transistor to which data is to be written.
  • Second data is applied to the gate electrode of each storage transistor in the storage string and the second electrode of the storage transistor to which data is to be written, and the third voltage is less than the second voltage, so as to write into the storage transistor to which data is to be written.
  • embodiments of the present application also provide a storage array manufacturing method, including:
  • a stacked structure is formed on the substrate;
  • the stacked structure includes a plurality of device layers arranged in a stack, and each device layer includes a first intermediate layer, a first isolation layer and a second intermediate layer arranged in a stack, and the first isolation layer is located in the first intermediate layer. and the second intermediate layer; the second intermediate layer is provided with a first opening penetrating it, and the first opening is filled with an electrode plate;
  • each device layer serves as the first electrode of a storage transistor.
  • the electrode plate in the device layer serves as the second electrode of the corresponding storage transistor.
  • the gate pillar As the gate electrode of the corresponding storage transistor; each first electrode layer is electrically connected.
  • the stacked structure includes a plurality of device layers arranged in a stack.
  • Each device layer includes a first electrode layer, a first isolation layer and an electrode plate arranged in a stack.
  • the first isolation layer The first electrode layer is located between the first electrode layer and the electrode plate, and each first electrode layer is electrically connected.
  • the stacked structure is provided with through holes, and the through holes penetrate each second electrode.
  • Each first electrode layer is provided with a gate pillar in the through hole.
  • the first electrode layer in each device layer serves as the first electrode of a storage transistor, and the electrode plate in the device layer serves as the second electrode of the corresponding storage transistor.
  • the electrode and gate post serve as the gate of the corresponding storage transistor.
  • each first electrode layer is electrically connected, the gate pillar and the memory transistor formed by each device layer are connected in parallel.
  • power can be supplied to the first electrode layer and the gate pillar, that is, the gate pillar is connected to each device layer.
  • Each storage transistor formed by the device layer is in a state where data can be read. At this time, the data in the storage transistor corresponding to the electrode plate can be read through the electrode plate. There is no need to connect the gate pillar with each storage transistor formed by each device layer. are all turned on, improving the data reading speed.
  • the method before forming the gate pillar in the through hole, the method further includes: forming a channel layer and a dielectric layer in sequence on the hole wall of the through hole; the channel layer covers the entire hole wall of the through hole, and the dielectric layer covers the entire channel layer.
  • the area of the dielectric layer can be increased, thereby improving the ability of the dielectric layer to store electrons.
  • the area of the conductive channel is also increased, thereby increasing the turn-on voltage of the storage transistor and improving the performance of the storage array.
  • forming the stacked structure on the substrate further includes: forming an intermediate isolation layer between adjacent device layers; and after forming the gate pillar, further includes: removing the intermediate isolation layer and the intermediate isolation layer The corresponding channel layer is layered to form a first gap layer, and a second isolation layer is formed in the first gap layer.
  • the second isolation layer can also isolate the channel layers in adjacent device layers.
  • the method before forming a gate column in the through hole, also includes: forming a dielectric layer on the hole wall of the through hole, the dielectric layer covering the entire hole wall of the through hole; after forming the gate column in the through hole, the method also includes: forming a connecting hole on the stacked structure, the connecting hole passing through each device layer; and removing the first isolation layer through the connecting hole to form a second void layer; forming a channel layer on the side wall of the second void layer, the channel layer covering the dielectric layer, the electrode plate and the first intermediate layer corresponding to the second void layer; and forming a third isolation layer in the second void layer.
  • the contact area between the channel layer and the electrode plate, and between the channel layer and the first electrode layer can be increased, thereby reducing the contact area between the channel layer and the electrode plate, and between the channel layer and the first electrode layer. resistance between the first electrode layers.
  • the channel layer is disposed in the second gap layer, which can prevent the channel layer from occupying the space of the through hole, increases the area of the dielectric layer in the through hole, and thereby improves the ability of the dielectric layer to store electrons.
  • the method before forming the gate pillar in the through hole, further includes: removing part of the first isolation layer through the through hole to form a gap; and forming a first channel layer on the hole wall of the through hole. , a second channel layer is formed on the sidewall of the gap, and the second channel layer is in contact with the first channel layer; a first dielectric layer is formed on the first channel layer, and a second dielectric layer is formed on the second channel layer.
  • forming the gate pillar in the through hole includes: filling the through hole and the gap with conductive material to form an extension located in the gap and a gate electrode located in the through hole post, and the extension contacts the gate post.
  • the second dielectric layer and the second channel layer in the gap also form a conductive channel, which can increase the conductivity.
  • the area of the channel increases the turn-on voltage of the memory transistor to improve the performance of the memory array.
  • forming the stacked structure on the substrate further includes: forming a second opening penetrating the first intermediate layer, filling the source plate in the second opening, and in the same device layer, The projection of the source plate on the substrate completely coincides with the projection of the electrode plate on the substrate.
  • the through hole penetrates the source plate and the electrode plate with overlapping projections, and the gate pillar, the source plate and the electrode plate constitute a memory transistor.
  • the first intermediate layer is replaced by a first electrode layer
  • the electrical connection of each first electrode layer includes: forming a connection hole through the stacked structure, and removing the first intermediate layer through the connection hole, To form a third gap layer, conductive material is filled in the connection hole and the third gap layer to form a first electrode layer and a conductor connecting each first electrode layer.
  • the electrical connection between adjacent first electrode layers can be realized through the conductor, and the structure is simple and easy to manufacture.
  • the method further includes: forming a conductive connector in the second intermediate layer, and the conductive connector contacts the electrode plate to form a second electrode line.
  • Figure 1 is a schematic diagram of the connection between memory transistors in the memory string in the related art
  • Figure 2 is a schematic structural diagram of a storage array provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram 2 of a storage array provided by an embodiment of the present application.
  • Figure 4 is a partial enlarged view of position A in Figure 2;
  • Figure 5 is a schematic structural diagram three of a storage array provided by an embodiment of the present application.
  • Figure 6 is a partial enlarged view of B in Figure 5;
  • Figure 7 is a schematic structural diagram 4 of a storage array provided by an embodiment of the present application.
  • Figure 8 is a partial enlarged view of C in Figure 7;
  • Figure 9 is a flow chart of a storage array manufacturing method provided by an embodiment of the present application.
  • Figure 10 is a schematic structural diagram after forming a stacked structure in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 11 is a schematic structural diagram after forming the first process hole in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 12 is a schematic structural diagram after filling the first insulating block in the first process hole in the memory array manufacturing method provided by the embodiment of the present application;
  • Figure 13 is a schematic structural diagram after forming through holes in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 14 is a schematic structural diagram after forming the first opening in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 15 is a schematic structural diagram after forming through holes in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 16 is a schematic structural diagram after forming gate pillars in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 17 is a schematic structural diagram after forming connection holes in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 18 is a schematic structural diagram after forming the third gap layer in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 19 is a schematic structural diagram after forming the first electrode layer and the conductor in the memory array manufacturing method provided by the embodiment of the present application;
  • Figure 20 is a schematic structural diagram after forming the first gap layer in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 21 is a schematic structural diagram after forming the second isolation layer in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 22 is a schematic structural diagram after forming the second process hole in the memory array manufacturing method provided by the embodiment of the present application.
  • FIG23 is a schematic diagram of the structure after a conductive connector is formed in the memory array manufacturing method provided in an embodiment of the present application.
  • FIG24 is a schematic diagram of the structure after the first insulating block is removed in the storage array manufacturing method provided in an embodiment of the present application;
  • FIG25 is a schematic structural diagram of a memory array manufacturing method provided in an embodiment of the present application after a conductive connector is formed by using a first process hole;
  • Figure 26 is a schematic structural diagram after using the first process hole to form the first gap layer in the memory array manufacturing method provided by the embodiment of the present application;
  • Figure 27 is a schematic structural diagram after using the first process hole to form the second isolation layer in the memory array manufacturing method provided by the embodiment of the present application;
  • Fig. 28 is a cross-sectional view taken along the line A-A in Fig. 15;
  • FIG29 is a schematic diagram of a structure after a gate pillar is formed in a memory array manufacturing method provided in an embodiment of the present application;
  • Figure 30 is a schematic structural diagram of the memory array manufacturing method provided by the embodiment of the present application after using connection holes to remove the first isolation layer;
  • Figure 31 is a schematic structural diagram after forming the third isolation layer in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 32 is a schematic structural diagram after forming the first electrode layer and the conductor in the memory array manufacturing method provided by the embodiment of the present application;
  • Figure 33 is a schematic structural diagram of the memory array manufacturing method provided by the embodiment of the present application after using through holes to form gaps;
  • Figure 34 is a schematic structural diagram after forming a channel layer in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 35 is a schematic structural diagram after forming a dielectric layer in the storage array manufacturing method provided by the embodiment of the present application.
  • Figure 36 is a schematic structural diagram after forming gate pillars in the memory array manufacturing method provided by the embodiment of the present application.
  • Figure 37 is a circuit diagram of a memory array provided by an embodiment of the present application.
  • Figure 38 is a flow chart of the reading and writing method provided by the embodiment of the present application.
  • Figure 1 is a schematic diagram of the connection between the storage transistors in the storage string in the related art.
  • the storage array (NAND flash memory) includes a storage string.
  • the storage string includes a plurality of storage transistors 101 arranged in sequence. Each storage transistor 101 are used for data storage. Multiple storage transistors 101 are connected in series. Taking the orientation shown in Figure 1 as an example, from bottom to top, the drain of the first storage transistor 101 is connected to the source line (SL) through the ground select transistor 102 (Ground select transistor).
  • SL source line
  • Ground select transistor ground select transistor
  • the source of one storage transistor 101 is connected to the drain of the second storage transistor 101, the source of the second storage transistor 101 is connected to the drain of the third storage transistor 101, and so on; the storage transistor at the top
  • the source of 101 is connected to the word line (BL1) through the word line select transistor 103 (BL select transistor), and the gate of each storage transistor 101 is connected to a gate line (WL).
  • BL1 word line
  • BL select transistor word line select transistor
  • WL gate line
  • the conductive channel in the memory transistor 101 is generally made of semiconductor materials such as polysilicon and oxide semiconductor, the mobility of the conductive channel is low and the transmission current is small, resulting in a long time required to turn on all the memory transistors 101 in the memory string. , which in turn causes the storage array to read data slowly.
  • embodiments of the present application provide a storage array and a manufacturing method thereof, a memory, an electronic device, and a reading and writing method.
  • a stacking structure is provided on the substrate of the storage array.
  • the stacking structure includes a plurality of device layers arranged in a stack. Each device The layer includes a stacked first electrode layer, a first isolation layer and a second electrode layer. Each first electrode layer is electrically connected.
  • a through hole is provided on the stacked structure.
  • the first electrode layer in each device layer serves as a memory transistor.
  • the first electrode in the device layer serves as the second electrode of the corresponding storage transistor, and the gate pillar serves as the gate electrode of the corresponding storage transistor; that is to say, the storage transistor includes a gate pillar and a device layer.
  • Embodiments of the present application provide an electronic device that has a data storage function.
  • the electronic device may include a central processing unit (CPU), a power management device, etc.
  • the electronic device includes a circuit board and a memory provided on the circuit board, and the memory is used to store data; it can be understood that the circuit board can also be provided with other electronic devices, which is not limited in this example.
  • the memory includes a storage array and a controller.
  • the controller is electrically connected to the storage array.
  • the controller is used to access the storage array to write data into the storage array or read data from the storage array.
  • FIG2 is a structural schematic diagram of a storage array provided in an embodiment of the present application.
  • an embodiment of the present application provides a storage array, including a substrate 10 and a stacked structure 20 disposed on the substrate 10, wherein the substrate 10 is in a plate shape, and the material of the substrate 10 may include silicon, germanium, etc., and this embodiment does not limit the material of the substrate 10.
  • the stacked structure 20 includes a plurality of device layers 201 stacked, each device layer 201 includes a first electrode layer 204, a first isolation layer 203, and a second electrode layer 202 stacked, the first isolation layer 203 is disposed between the first electrode layer 204 and the second electrode layer 202, and the first electrode layer 204 may be located on a side of the first isolation layer 203 close to the substrate 10.
  • the first electrode layer 204 may include a plurality of first electrode lines 2043 arranged parallel and spaced apart in a direction parallel to the substrate 10
  • the second electrode layer 202 may include a plurality of second electrode lines 2043 arranged parallel and spaced apart in a direction parallel to the substrate 10 2021, the projection of the first electrode line 2043 on the substrate 10 is perpendicular to the projection of the second electrode line 2021 on the substrate 10.
  • the materials of the first electrode wire 2043 and the second electrode wire 2021 may include titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (In- One or more of Ti-O ITO), aluminum (Al), copper (Cu), ruthenium (Ru), and silver (Ag).
  • the first isolation layer 203 is used to isolate the first electrode line and the second electrode line.
  • the first isolation layer 203 is an insulating layer.
  • the material of the first isolation layer 203 may include: silicon oxide (SIO_2), aluminum oxide ( Al_2O_3), hafnium oxide (HfO_2), pickaxe oxide (ZrO_2), titanium oxide (TiO_2), yttrium oxide (Y_2O_3), silicon nitride (Si_3N_4), etc.
  • first isolation block 2024 may be provided between adjacent second electrode lines 2021 to achieve isolation between adjacent second electrode lines 2021.
  • a second isolation block 2044 may be provided between adjacent first electrode lines 2043 to achieve isolation between adjacent first electrode lines 2043 through the second isolation block 2044.
  • the material of the first isolation block 2024 and the second isolation block 2044 may be the same as the material of the first isolation layer 203.
  • the first isolation block 2024 and the second isolation block 2044 may also be The insulating material may be other insulating materials, which is not limited in this embodiment.
  • the stacked structure 20 also includes a second isolation layer 206.
  • One second isolation layer 206 is stacked between adjacent device layers 201. Adjacent devices can be implemented through the second isolation layer 206. Isolation between layers 201.
  • the material of the second isolation layer 206 can be the same as the material of the first isolation layer 203.
  • the second isolation layer 206 can also be made of other insulating materials, which is not limited in this embodiment.
  • the stacked structure 20 also includes a gate post 209.
  • the stacked structure 20 is provided with a through hole 205, the through hole 205 penetrates the stacked structure 20, and the gate post 209 is inserted through the through hole.
  • the first electrode layer 204 in each device layer 201 serves as the first electrode of a storage transistor 101
  • the second electrode layer 201 in the device layer 201 serves as the second electrode of the corresponding storage transistor 101
  • the gate pillar 209 serves as the corresponding storage transistor 101.
  • the gate of the transistor 101, the storage transistor 101 is used to store data. That is to say, the gate pillar 209 and each device layer 201 form a memory transistor 101.
  • the first electrode layer 204 serves as the first electrode of the memory transistor 101
  • the second electrode layer 201 serves as a memory transistor.
  • the second electrode of transistor 101, gate post 209, serves as the gate electrode of memory transistor 101.
  • the gate pillar 209 is a conductive pillar.
  • the gate pillar 209 can be made of the same material as the first electrode line 2043 and the second electrode line 2021.
  • the gate pillar 209 can also be made of other conductive materials. , this embodiment does not limit this.
  • the second electrode layer 202 includes a plurality of second electrode lines 2021
  • the first electrode layer 204 includes a plurality of first electrode lines 2043
  • the second electrode lines 2021 are perpendicular to the first electrode lines 2043
  • the same device layer The projections of a second electrode line 2021 and a first electrode line 2043 in 201 on the substrate 10 have an overlapping area, and the projection of the through hole 205 on the substrate 10 is located in the overlapping area; that is, the through hole 205 penetrates the second The overlapping portion of the electrode line 2021 and the first electrode line 2043.
  • the second electrode line 2021 serves as the second electrode of a storage transistor 101
  • the first electrode line 2043 serves as the first electrode of the storage transistor 101
  • the gate pillar 209 serves as the gate electrode of the storage transistor 101
  • the second The electrode may be the drain of the storage transistor 101
  • the first electrode may be the source of the storage transistor 101
  • the gate post 209 may be the gate of the storage transistor 101
  • the second electrode may be the source of the storage transistor 101
  • the first electrode is the drain of the storage transistor 101
  • the gate post 209 is the gate of the storage transistor 101 .
  • each device layer 201 is roughly the same, and the through hole 205 penetrates each device layer 201.
  • each storage transistor 101 formed between the gate column 209 and each device layer 201 constitutes a storage string, that is, each storage transistor 101 in the storage string is arranged in sequence along a direction roughly perpendicular to the substrate 10.
  • each gate pillar 209 and each device layer 201 form a memory string, which improves the storage capacity of the memory array.
  • the first electrode layers 204 in each device layer 201 are all electrically connected. That is to say, in the same memory string, the first electrode layers 204 are electrically connected. With this arrangement, the first electrode layers 204 in the same memory string are electrically connected. The sources of each storage transistor 101 are electrically connected.
  • the gate pillar 209 serves as the gate electrode of each memory transistor 101 in the same memory string, that is, the gate electrodes of each memory transistor 101 in the same memory string are electrically connected, so that each memory transistor 101 in the same memory string is connected in parallel.
  • each storage transistor 101 in the storage string where the gate pillar 209 is located is in a state where data can be read.
  • the electrode layer 202 can read the data in the storage transistor corresponding to the second electrode layer 202.
  • the first electrode layer 204 includes a plurality of first electrode lines 2043 arranged parallel and spaced apart in a direction parallel to the substrate 10
  • the second electrode layer 202 includes a plurality of first electrode lines 2043 arranged parallel to the substrate 10 .
  • a plurality of second electrode lines 2021 are arranged parallel and spaced in the direction of the substrate 10; the through hole 205 penetrates one of the second electrode lines 2021; the stacked structure 20 also includes a connection hole 2041 that penetrates each device layer 201, and the connection hole 2041 is The projection on the substrate 10 is located between the projections of two adjacent second electrode lines 2021 on the substrate 10 in the same device layer 201; the connection hole 2041 is filled with a conductor 2042, and the conductor 2042 is connected to each of the second electrode lines 2021 in the same storage string.
  • An electrode wire 2043 is in contact. That is to say, the connection holes 2041 penetrate each first electrode line 2043 corresponding to the memory string, and the formed conductor 2042 can realize electrical connection between each first electrode line 2043 corresponding to the memory string. With such an arrangement, the structure is simple and easy to manufacture.
  • the material of the conductor 2042 can be the same as the material of the first electrode wires 2043. After the conductor 2042 contacts each first electrode wire 2043, the conductor 2042 can form an integrated structure with each first electrode wire 2043. This can reduce the conduction The resistance between the electric body 2042 and each first electrode line 2043 is to improve the performance of the memory array.
  • the same first electrode line 2043 may correspond to multiple memory strings, that is to say, the same first electrode line may be penetrated by multiple through holes 205 .
  • a connection hole 2041 can be provided between two adjacent through holes 205, and each connection hole 2041 is filled with conductors 2042.
  • the plurality of conductors 2042 are used to realize electrical connections between the first electrode lines 2043 corresponding to the same memory string, which can improve the voltage uniformity on the first electrode lines 2043 and thereby improve the performance of the memory array.
  • Figure 3 is a second structural schematic diagram of a memory array provided by an embodiment of the present application. Please refer to Figure 3.
  • the first electrode layer 204 in the same device layer 201 can be a whole layer structure.
  • different device layers The first electrode layers 204 in 201 can be electrically connected through peripheral circuits (not shown). This embodiment does not limit the electrical connection method between the first electrode layers 204 .
  • the stacked structure 20 includes a plurality of device layers 201 arranged in a stack.
  • Each device layer 201 includes a first electrode layer 204, a first isolation layer 203 and a second electrode layer 202 arranged in a stack.
  • the first The isolation layer 203 is located between the first electrode layer 204 and the second electrode layer 202, and the first electrode layers 204 are electrically connected to each other.
  • the stacked structure 20 is provided with a through hole 205, which penetrates each second electrode layer 202 and each first electrode layer 204.
  • the through hole 205 is provided with a gate post 209, and the first electrode in each device layer 201
  • the layer 204 serves as a first electrode of a storage transistor 101
  • the second electrode layer 202 in the device layer 201 serves as a second electrode of the corresponding storage transistor 101
  • the gate post 209 serves as a gate electrode of the corresponding storage transistor 101 . Since each first electrode layer 204 is electrically connected, the gate pillar 209 and the memory transistor 101 formed by each device layer 201 are connected in parallel.
  • power can be supplied to the first electrode layer 204 and the gate pillar 209, that is, Each storage transistor 101 formed by the gate pillar 209 and each device layer 201 can be in a state where data can be read.
  • the memory transistor 101 corresponding to the second electrode layer 202 can be read through the second electrode layer 202 data, there is no need to turn on each storage transistor 101 formed by the gate pillar 209 and each device layer 201, thereby improving the data reading speed.
  • each device layer 201 also includes a dielectric layer 207 and a channel layer 208.
  • the through hole 205 includes a through hole that penetrates each device layer 201.
  • the sub-vias 2051 that is to say, the sub-vias 2051 that penetrate the device layer 201 are connected in sequence and form a through-hole 205 .
  • the dielectric layer 207 is disposed on the gate pillar 209 corresponding to the sub-via hole 2051.
  • the channel layer 208 is in contact with the dielectric layer 207, the first electrode layer 204 and the second electrode layer 202.
  • the storage transistor 101 also includes the dielectric layer 207, and The channel layer 208 is in contact with the material layer 207, the first electrode layer 204 and the second electrode layer 202.
  • the dielectric layer 207 can store electrons.
  • applying a small voltage to the gate pillar 209 and the first electrode layer 204 can make the storage transistor 101 in the on state.
  • detection can be
  • the dielectric layer 207 does not store electrons and a small voltage is applied to the gate pillar 209 and the first electrode layer 204, the storage transistor 101 is difficult to turn on, and the current obtained is small.
  • the current that is It can realize data reading, has a simple structure and is easy to produce.
  • the dielectric layer 207 is used to store electrons, and the dielectric layer 207 may include a stacked silicon oxide layer (SiO_x), a silicon nitride layer (SiN_x), and a silicon oxide layer (SiO_x).
  • the dielectric layer 207 is insulated by silicon oxide (SiO_2), aluminum oxide (Al_2O_3), hafnium oxide (HfO_2), pickaxe oxide (ZrO_2), titanium oxide (TiO_2), yttrium oxide (Y_2O_3), silicon nitride (Si_3N_4), etc.
  • silicon oxide SiO_2
  • Al_2O_3 aluminum oxide
  • hafnium oxide HfO_2
  • pickaxe oxide ZrO_2
  • TiO_2 titanium oxide
  • Y_2O_3 silicon nitride
  • Si_3N_4 silicon nitride
  • the dielectric layer 207 can also be pickaxe (ZrO_2), hafnium oxide (HfO_2), aluminum (Al) doped with hafnium oxide (HfO_2), silicon (Si) doped with hafnium oxide (HfO_2), pickaxe (Zr) doped with Ferroelectric materials such as hafnium oxide (HfO_2), lanthanum (La) doped with hafnium oxide (HfO_2), yttrium (Y) doped with hafnium oxide (HfO_2), or the dielectric layer 207 is based on ferroelectric materials and is doped with other elements. Material, the dielectric layer 207 may also be one or a combination of more of the above materials.
  • a first voltage can be applied to the gate pillar 209 and the first electrode layer 204. If the data stored in the storage transistor 101 is "1", electrons are stored in the dielectric layer 207 at this time. Under the combined action of a voltage and electrons, the storage transistor 101 can be in an on state. At this time, the first current can be obtained through the second electrode layer 202 connected to the storage transistor 101; if the data stored in the storage transistor 101 is "0" ”, the dielectric layer 207 does not store electrons, and the storage transistor 101 is difficult to turn on. At this time, the second current can be obtained through the second electrode layer 202 connected to the storage transistor 101. The second current is smaller than the first current. By analyzing the first current and The second current can obtain the data stored in the storage transistor 101, thereby realizing reading of the data.
  • the gate pillar 209 and the second electrode connected to the storage transistor 101 can The layer 202 applies a second voltage so that the storage transistor 101 is in an on state. Under the action of the second voltage, electrons are injected into the dielectric layer 207 and remain in the dielectric layer 207. At this time, the data stored in the storage transistor 101 Can be "1". If a second voltage is applied to the gate pillar 209 and a third voltage is applied to the second electrode layer 202 connected to the memory transistor 101, and the third voltage is lower than the second voltage, electrons will not be injected into the dielectric layer 207 at this time. The data stored in the corresponding storage transistor 101 may be "0".
  • the dielectric layer 207 can cover the entire gate pillar 209 corresponding to the sub-through hole 2051, that is, the dielectric layer 207 is continuously arranged along the center line direction of the sub-gate pillar 209, and the dielectric layer 207 covers the entire gate pillar 209 (the dielectric layer 207 is tubular). Such an arrangement can increase the area of the dielectric layer 207, thereby improving the ability of the dielectric layer 207 to store electrons.
  • the dielectric layers 207 in adjacent device layers 201 are in contact.
  • the dielectric layers 207 in adjacent device layers 201 may be an integral structure. With this arrangement, the area of the dielectric layer 207 can be further increased, thereby improving the electronic storage capability of the dielectric layer 207 and improving the performance of the storage array layer.
  • Each dielectric layer 207 can also cover the entire gate pillar 209. That is to say, each dielectric layer 207 constitutes a continuous tube, which can further increase the area of the dielectric layer 207.
  • the channel layer 208 is in contact with the first electrode layer 204, the second electrode layer 202, and the dielectric layer 207; the channel layer 208 can have multiple structures and locations, which will be divided into multiple scenarios below. introduce:
  • the channel layer 208 covers the hole wall of the sub-via hole 2051
  • the dielectric layer 207 covers the gate pillar 209 corresponding to the sub-via hole 2051 to realize the connection between the channel layer 208 and the second Contact between the electrode layer 202, the first electrode layer 204 and the dielectric layer 207.
  • the channel layer 208 and the dielectric layer 207 can be sequentially formed on the hole wall of the sub-via hole 2051 during fabrication, which simplifies the fabrication difficulty of the memory array.
  • the channel layer 208 can cover the entire hole wall of the sub-via hole 2051, that is to say, the channel layer 208 is tubular in the sub-via hole 2051; correspondingly, the dielectric layer 207 can cover the entire side wall of the gate pillar 209, that is, That is, the dielectric layer 207 is also in the shape of a tube.
  • the contact area between the channel layer 208 and the first electrode layer 204, the second electrode layer 202 and the dielectric layer 207 can be increased, that is, the area of the conductive channel formed by the channel layer 208 and the dielectric layer 207 can be increased.
  • the turn-on voltage of the memory transistor 101 is increased, thereby improving the performance of the memory array.
  • the dielectric layers 207 in adjacent device layers 201 are in contact.
  • each dielectric layer 207 forms a tube covering the entire gate pillar 209 to increase the size of the dielectric layer. 207, thereby improving the electronic storage capacity of the dielectric layer 207.
  • the second isolation layer 206 may be in contact with the dielectric layer 207 , that is, the channel layer 208 on adjacent sub-vias 2051 is isolated by the second isolation layer 206 to avoid trenches on adjacent sub-vias 2051 The Tao layers 208 influence each other.
  • Figure 5 is a schematic structural diagram three of the storage array provided by the embodiment of the present application.
  • Figure 6 is a partial enlarged view of B in Figure 5. Please refer to Figures 5 and 6.
  • the difference between this scenario and scenario one is that first There is a gap 2031 between the isolation layer 203 and the hole wall of the sub-through hole 2051.
  • the gap 2031 is connected with the sub-through hole 2051. That is to say, the side wall of the sub-through hole 2051 corresponding to the first isolation layer 203 faces the first isolation layer 203. recessed inside to form a gap 2031.
  • the channel layer 208 includes a first channel layer 2081 disposed in the gap 2031 to achieve contact between the channel layer 208 and the second electrode layer 202, the first electrode layer 204 and the dielectric layer 207.
  • Such an arrangement can prevent the conductive channel from occupying the space in the through hole 205, thereby increasing the area of the dielectric layer 207 and improving the electron storage capacity of the dielectric layer 207.
  • the channel layer 208 also includes a second channel layer 2082 disposed on the surface of the first isolation layer 203 facing the second electrode layer 202 , and the second channel layer 2082 is in contact with the first channel layer 2081 ; That is to say, the second channel layer 2082 is sandwiched between the second electrode layer 202 and the first isolation layer 203, and the second channel layer 2082 is in contact with the second electrode layer 202.
  • the contact area between the channel layer 208 and the second electrode layer 202 can be increased, thereby reducing the resistance between the channel layer 208 and the second electrode layer 202 .
  • the first channel layer 2081 and the second channel layer 2082 may be made of the same material, so that after the first channel layer 2081 contacts the second channel layer 2082, the first channel layer 2081 and the second channel layer 2082 are in contact with each other.
  • the channel layer 2082 forms an integrated structure to reduce the resistance between the first channel layer 2081 and the second channel layer 2082.
  • the channel layer 208 further includes a third channel layer 2083 disposed on a surface of the first isolation layer 203 facing the first electrode layer 204 , and the third channel layer 2083 is in contact with the first channel layer 2081 ; That is to say, the third channel layer 2083 is sandwiched between the first electrode layer 204 and the first isolation layer 203, and the third channel layer 2083 is in contact with the first electrode layer 204.
  • Such an arrangement can increase the contact area between the channel layer 208 and the first electrode layer 204, thereby reducing the resistance between the channel layer 208 and the first electrode layer 204.
  • the channel layer 208 includes a first channel layer 2081, a second channel layer 2082, and a third channel layer 2083
  • the first channel layer 2081, the second channel layer 2082, and the third channel layer The material of the layer 2083 can be the same, so that after the first channel layer 2081 contacts the second channel layer 2082 and the third channel layer 2083, the first channel layer 2081, the second channel layer 2082, and the third channel layer 2083 are in contact with each other.
  • the channel layer 2083 forms an integrated structure to reduce the resistance between the first channel layer 2081 and the second channel layer 2082 and the third channel layer 2083.
  • Figure 7 is a structural schematic diagram four of the storage array provided by the embodiment of the present application.
  • Figure 8 is a partial enlarged view of C in Figure 7. Please refer to Figures 7 and 8.
  • the difference between this scenario and scenario one and scenario two is that , there is a gap 2032 between the first isolation layer 203 and the hole wall of the sub-through hole 2051, and the gap 2032 is connected with the through hole 205. That is to say, the hole wall corresponding to the sub-through hole 2051 and the first isolation layer 203 faces the first isolation layer.
  • Layer 203 is recessed to form gap 2032.
  • the gate pillar 209 is provided with an extension part 2091 , and the extension part 2091 is arranged in the gap 2032 .
  • the extension part 2091 is made of conductive material.
  • the extension part 2091 can be made of the same material as the gate post 209 so that the extension part 2091 and the gate post 209 can form an integrated structure to reduce the weight of the extension part 2091 and the gate post 209 resistance between.
  • the material of the extension part 2091 can also be different from that of the gate post 209. This embodiment does not limit this, as long as the extension part 2091 and the gate post 209 are electrically connected.
  • the dielectric layer 207 includes a first dielectric layer 2071 and a second dielectric layer 2072.
  • the first dielectric layer 2071 is located on the gate pillar 209 corresponding to the sub-via hole 2051, and the second dielectric layer 2072 wraps around the extension 2091; that is, The second dielectric layer 2072 is located between the extension part 2091 and the second electrode layer 202 , between the extension part 2091 and the first isolation layer 203 , and between the extension part 2091 and the first electrode layer 204 .
  • the first dielectric layer 2071 and the second dielectric layer 2072 are in contact.
  • the first dielectric layer 2071 and the second dielectric layer 2072 can be made of the same material, so that after the first dielectric layer 2071 and the second dielectric layer 2072 come into contact, the first dielectric layer 2071 and the second dielectric layer 2072 can form one body. structure to increase the area of the dielectric layer 207 and improve the electronic storage capacity of the dielectric layer 207.
  • the channel layer 208 includes a first channel layer 2081 and a second channel layer 2082.
  • the first channel layer 2081 is provided between the hole wall of the sub-via hole 2051 and the first dielectric layer 2071.
  • the second channel layer 2082 is provided Between the second dielectric layer 2072 and the sidewall of the gap 2032; that is, the second channel layer 2082 is located between the second dielectric layer 2072 and the second electrode layer 202, and between the second dielectric layer 2072 and the first isolation layer 203 between the second dielectric layer 2072 and the first electrode layer 204 .
  • the first channel layer 2081 and the second channel layer 2082 are in contact.
  • the second dielectric layer 2072 and the second channel layer 2082 in the gap 2032 also form a conductive channel. , which can increase the area of the conductive channel, thereby increasing the turn-on voltage of the memory transistor, thereby improving the performance of the memory array.
  • the width of the gap 2032 in the direction perpendicular to the second electrode lines 2021 may be greater than or equal to the second electrode line. 2021, so that the gap 2032 has a large enough space to accommodate more second dielectric layers 2072 and second channel layers 2082.
  • the width of the gap 2032 in the direction parallel to the second electrode line can be greater than or equal to the width of the first electrode line 2043 (as shown in FIG. 2 ), or the gap 2032 can have a large enough space to accommodate more. multiple second dielectric layers 2072 and second channel layers 2082.
  • the first dielectric layer 2071 may also cover the gate pillars 209 between adjacent device layers 201 to increase the area of the first dielectric layer 2071, thereby improving the electron storage capacity of the dielectric layer 207. Accordingly, the second isolation layer 206 may contact the first dielectric layer 2071, that is, the first channel layers 2081 on adjacent sub-through holes 2051 are isolated by the second isolation layer 206 to prevent the first channel layers 2081 on adjacent sub-through holes 2051 from affecting each other.
  • This embodiment provides a storage array manufacturing method, which can be used to manufacture the storage array in Embodiment 1.
  • Figure 9 is a flow chart of a storage array manufacturing method provided by an embodiment of the present application. Please refer to Figure 9.
  • the storage array manufacturing method provided by this embodiment includes:
  • S101 Form a stacked structure on the substrate.
  • Figure 10 is a schematic structural diagram after forming a stacked structure in the memory array manufacturing method provided by the embodiment of the present application. Please refer to Figure 10.
  • the substrate 10 serves as the basis of the entire memory array.
  • the substrate 10 can be in a plate shape, and the material of the substrate 10 can include silicon. , germanium, etc.
  • the stacked structure 20 includes a plurality of stacked device layers 201.
  • Each device layer 201 includes a stacked first intermediate layer 301, a first isolation layer 203 and a second intermediate layer 302.
  • the first isolation layer 203 is located in the first intermediate layer.
  • the second intermediate layer 302 can be located on the side of the first isolation layer 203 away from the substrate 10, and the second intermediate layer 302 is provided with a first opening 3021 penetrating it (as shown in Figure 11 ), the first opening 3021 is filled with the electrode plate 2022.
  • the method of fabricating the stacked structure 20 on the substrate 10 may include: alternately forming the first intermediate layer 301 , the first isolation layer 203 and the second intermediate layer 302 on the substrate 10 to form a stacked structure.
  • device layer 201 that is to say, first form a first intermediate layer 301 on the substrate 10, then form the first isolation layer 203 on the first intermediate layer 301, and then form the second intermediate layer 302 on the first isolation layer 203 to complete. Preparation of one device layer 201; after that, repeat the above steps to form multiple stacked device layers 201 in sequence.
  • an intermediate isolation layer 303 can be formed on the device layer 201, and then the next device layer 201 is produced; that is, an intermediate isolation layer is provided between adjacent device layers 201. 303 to achieve isolation between adjacent device layers 201.
  • Figure 11 is a schematic diagram of the structure after the first process hole is formed in the storage array manufacturing method provided in an embodiment of the present application. Please refer to Figure 11.
  • a first process hole 304 can be formed on the stack structure 20.
  • the first process hole 304 penetrates the stack structure 20.
  • a first insulating block 305 is filled in the first process hole 304 (as shown in Figure 12).
  • the first insulating block 305 can connect the film layers in the stack structure 20 to improve the connection force between the film layers in the stack structure 20.
  • FIG. 13 is a schematic structural diagram after forming through holes in the memory array manufacturing method provided by the embodiment of the present application. Please refer to Figure 13.
  • a through hole 306 can be formed on the stacked structure 20.
  • the through hole 306 It penetrates the stacked structure 20 and the projection of the through hole 306 on the substrate 10 is located outside the projection of the first insulating block 305 on the substrate 10 .
  • FIG. 14 is a schematic structural diagram after forming the first opening in the memory array manufacturing method provided by the embodiment of the present application. Please refer to FIG. 14 to remove part of the second intermediate layer 302 through the through hole 306 to form a second intermediate layer 302 on the second intermediate layer 302 . First opening 3021.
  • FIG. 15 is a schematic structural diagram after forming a through hole in the memory array manufacturing method provided by the embodiment of the present application. Please refer to FIG. Electrode Plate 2022.
  • the memory array manufacturing method in this embodiment also includes:
  • S102 Form a through hole on the stacked structure, the through hole penetrates the stacked structure, and the projection of the through hole on the substrate is located within the projection of the electrode plate on the substrate.
  • the projection of the through hole 306 on the substrate 10 shown in FIG. 14 can be located within the projection of the through hole 205 on the substrate 10 , so that the through hole 205 can be formed during the process of forming the through hole 205 .
  • the conductive material in 306 is removed to avoid connection between the electrode plates 2022.
  • the projection of the through hole 205 on the substrate 10 can completely coincide with the projection of the through hole 306 on the substrate 10; or, the projected area of the through hole 205 on the substrate 10 is larger than the projected area of the through hole 306 on the substrate 10. , in this way, the conductive material in the through hole 306 can be removed to avoid residual conductive material in the through hole 306 .
  • the storage array manufacturing method in this embodiment also includes:
  • Figure 16 is a schematic structural diagram after forming the gate pillars in the memory array manufacturing method provided by the embodiment of the present application.
  • the first electrode layer in each device layer 201 serves as a The first electrode of the storage transistor 101
  • the electrode plate 2022 in the device layer 201 serves as the second electrode corresponding to the storage transistor 101
  • the gate pillar 209 serves as the gate electrode corresponding to the storage transistor 101.
  • the storage transistor is used to store data.
  • the gate pillar 209 can be the gate electrode in the storage transistor, the first electrode is the source electrode in the storage transistor, and the second electrode is the drain electrode in the storage transistor; or the gate pillar 209 can be the gate electrode in the storage transistor.
  • the first electrode is the drain electrode in the storage transistor
  • the second electrode is the source electrode in the storage transistor.
  • the memory array fabricated by the memory array fabrication method provided in this embodiment comprises a stacked structure 20 including a plurality of device layers 201 arranged in a stacked manner, each device layer 201 including a first electrode layer, a first isolation layer 203 and an electrode plate 2022 arranged in a stacked manner, the first isolation layer 203 and an electrode plate 2022
  • the layer 203 is located between the first electrode layer and the electrode plate 2022, and each first electrode layer is electrically connected.
  • a through hole 205 is provided on the stacked structure 20, and the through hole 205 penetrates each second electrode layer 202 and each first electrode layer.
  • a gate column 209 is penetrated in the through hole 205.
  • the first electrode layer in each device layer 201 serves as a first electrode of a storage transistor 101
  • the electrode plate 2022 in the device layer 201 serves as a second electrode of the corresponding storage transistor 101
  • the gate column 209 serves as a gate of the corresponding storage transistor 101. Since the first electrode layers are electrically connected, the gate column 209 and the storage transistors formed by the device layers 201 are connected in parallel.
  • power can be supplied to the first electrode layer and the gate column 209, so that the gate column 209 and the storage transistors formed by the device layers 201 are all in a state where data can be read.
  • the data in the storage transistor corresponding to the electrode plate 2022 can be read through the electrode plate 2022, and there is no need to turn on the gate column 209 and the storage transistors formed by the device layers 201, thereby improving the data reading speed.
  • the memory array manufacturing method in this embodiment can It has the following production scenarios:
  • the gate pillar 209 in the through hole 205 before forming the gate pillar 209 in the through hole 205 , it also includes: sequentially forming a channel layer 208 and a dielectric layer 207 on the hole wall of the through hole 205 ; the channel layer 208 covers the entire hole wall of the through hole 205 , the dielectric layer 207 covers the entire channel layer 208. That is to say, the channel layer 208 and the dielectric layer 207 both have a tubular shape in the through hole 205 . With this arrangement, the area of the dielectric layer 207 can be increased, thereby improving the ability of the dielectric layer 207 to store electrons. In addition, the area of the conductive channel is increased, thereby increasing the turn-on voltage of the memory transistor and improving the performance of the memory array.
  • the dielectric layer 207 is used to store electrons.
  • the dielectric layers 207 in adjacent device layers can be in contact and form an integrated structure.
  • the corresponding dielectric layer 207 can cover the entire through hole 205, that is, the dielectric layer 207 covers the entire gate column. 209. In this way, the electronic storage capacity of the dielectric layer 207 can be further improved.
  • the channel layer 208 and the dielectric layer 207 are sandwiched between the gate pillar 209 and the hole wall of the through hole 205, and the channel layer 208 is located between the dielectric layer 207 and the through hole.
  • hole 205 between the hole walls.
  • the gate pillar 209, the dielectric layer 207, the channel layer 208, the electrode plate 2022 and the first electrode layer 204 constitute a memory transistor.
  • FIG. 17 is a schematic diagram of the structure after forming the connection holes in the storage array manufacturing method provided in the embodiment of the present application. Please refer to FIG. 17.
  • the first intermediate layer 301 is replaced by the first electrode layer, and the electrical connection of each first electrode layer includes: forming a connection hole 2041 that penetrates the stacked structure 20, and the projection of the connection hole 2041 on the substrate 10 is located outside the projection of the electrode plate 2022 on the substrate 10.
  • FIG. 18 is a schematic diagram of the structure after forming the third gap layer in the storage array manufacturing method provided in the embodiment of the present application. Please refer to FIG. 18. Then, the first intermediate layer 301 is removed through the connection hole 2041 to form the third gap layer 3011.
  • FIG. 18 is a schematic diagram of the structure after forming the connection holes in the storage array manufacturing method provided in the embodiment of the present application. Please refer to FIG. 18. Then, the first intermediate layer 301 is removed through the connection hole 2041 to form the third gap layer 3011.
  • FIG. 18 is a schematic diagram of the structure after
  • FIG. 19 is a schematic diagram of the structure after forming the first electrode layer and the conductor in the storage array manufacturing method provided in the embodiment of the present application. Please refer to FIG. 19. After that, the conductive material is filled in the connection hole 2041 and the third gap layer 3011 to form the first electrode layer 204 located in the third gap layer and the conductor 2042 connecting each first electrode layer 204.
  • the electrical connection between adjacent first electrode layers 204 can be achieved through the conductor 2042 , and the structure is simple and easy to manufacture.
  • FIG. 20 is a schematic diagram of the structure after the first gap layer is formed in the storage array manufacturing method provided in the embodiment of the present application. Please refer to FIG. 20.
  • the intermediate isolation layer 303 and the channel layer 208 corresponding to the intermediate isolation layer 303 are removed to form a first gap layer 3031.
  • the first gap layer 3031 can interrupt the channel layer 208 between adjacent device layers 201, thereby avoiding the connection of the channel layers 208 between adjacent device layers 201.
  • FIG. 21 is a schematic diagram of the structure after the second isolation layer is formed in the storage array manufacturing method provided in the embodiment of the present application. Please refer to FIG. 21.
  • a second isolation layer 206 is formed in the first gap layer 3031. While isolating the adjacent device layers 201, the second isolation layer 206 can also isolate the channel layers 208 in the adjacent device layers 201.
  • the intermediate isolation layer 303 before removing the first intermediate layer 301, can be removed through the connection holes 2041, and then the second isolation layer 206 is filled into the first gap layer 3031 through the connection holes 2041. It can be understood that during the process of forming the second isolation layer 206, part of the insulating material will be filled in the connection hole 2041; accordingly, before removing the first intermediate layer 301, the insulating material in the connection hole 2041 can be removed, so as to Avoid affecting subsequent processes.
  • the memory array manufacturing method further includes forming a conductive connector in the second intermediate layer 302, and the conductive connector contacts the electrode plate 2022 to form a third Two electrode wires. Data can be read and written through the second electrode line.
  • the conductive connector and the electrode plate 2022 can be made of the same material, so that after the conductive connector is formed, the conductive connector and the electrode plate 2022 form an integrated structure to reduce the friction between the conductive connector and the electrode plate. resistance between 2022.
  • each electrode plate 2022 is provided with a through hole 205, and each through hole 205 is provided with Such arrangement of the gate pillars 209 can increase the number of storage transistors, thereby improving the storage capacity of the storage array.
  • Figure 22 is a schematic structural diagram after forming the second process hole in the memory array manufacturing method provided by the embodiment of the present application. Please refer to Figure 22.
  • the first process hole can be formed.
  • a second process hole 307 is formed on the insulating block 305 , the second process hole 307 penetrates to the substrate 10 , and the projection of the second process hole 307 on the substrate 10 is located within the projection of the first process hole 304 on the substrate 10 .
  • the second process hole 307 extends in a direction parallel to the substrate 10 and penetrates to the second intermediate layer 302 between adjacent electrode plates 2022 .
  • FIG23 is a schematic diagram of the structure after the conductive connector is formed in the storage array manufacturing method provided in an embodiment of the present application.
  • the second intermediate layer 302 outside the electrode plate 2022 can be removed through the second process hole 307, that is, the second intermediate layer 302 between adjacent electrode plates 2022 is removed, and a conductive connector 2023 is formed in the second intermediate layer 302, that is, the conductive connector 2023 is located between adjacent electrode plates 2022, and the conductive connector 2023 is in contact with the electrode plate 2022 to form a second electrode line.
  • a second insulating block 3071 can be filled in the second process hole 307 to close the second process hole 307.
  • FIG24 is a schematic diagram of the structure after the first insulating block is removed in the storage array manufacturing method provided in the embodiment of the present application. As shown in FIG24, in this scenario, after the gate pillar 209 is formed, the first insulating block 305 can also be removed to expose the first process hole 304.
  • FIG25 is a schematic diagram of the structure after the conductive connector is formed by using the first process hole in the storage array manufacturing method provided in the embodiment of the present application. As shown in FIG25, the second intermediate layer 302 between the adjacent electrode plates 2022 is then removed through the first process hole 304, and a conductive connector 2023 is formed between the adjacent electrode plates 2022, and the conductive connector 2023 is in contact with the electrode plate 2022 to form a second electrode line.
  • Figure 26 is a schematic structural diagram after using the first process hole to form the first gap layer in the memory array manufacturing method provided by the embodiment of the present application.
  • the intermediate isolation layer can be removed through the first process hole 304. 303, and the channel layer 208 corresponding to the intermediate isolation layer 303 to form a first gap layer 3031, thereby causing the channel layer 208 between adjacent device layers 201 to be disconnected.
  • Figure 27 is a schematic structural diagram of the second isolation layer formed by using the first process hole in the memory array manufacturing method provided by the embodiment of the present application.
  • the first process hole 304 is then used to form the second isolation layer in the first gap layer 3031.
  • a second isolation layer 206 is formed, and the second isolation layer 206 is in contact with the dielectric layer 207 corresponding to the first gap layer 3031, so as to achieve isolation of the channel layer 208 in the device layer 201 through the second isolation layer 206.
  • the first intermediate layer 301 may also be removed through the first process hole 304 to form a third gap layer, and then the first electrode layer 204 is formed in the third gap layer.
  • the first electrode layer 204 may have a whole-layer structure, and accordingly, each first electrode layer 204 may be electrically connected through a peripheral circuit.
  • a second opening penetrating the first intermediate layer 301 is formed, and the source plate is filled in the second opening.
  • the source plate is The projection on the substrate 10 completely coincides with the projection of the electrode plate 2022 on the substrate 10 .
  • the through hole 205 penetrates the overlapping source plate and the electrode plate 2022, and the gate pillar 209 and the source plate and the electrode plate 2022 constitute a memory transistor.
  • the first intermediate layer 301 outside the source plate is removed through the first process hole 304 to form a third gap layer, and then a conductive material is formed in the third gap layer, and the conductive material contacts the source plate to form a first electrode layer 204.
  • FIG28 is a cross-sectional view taken along the line A-A in FIG15 .
  • scenario 1 the difference between this scenario and scenario 1 is that after forming the through hole 205 and before forming the gate column 209, the following steps are included:
  • Figure 29 is a schematic structural diagram after the gate pillars are formed in the memory array manufacturing method provided by the embodiment of the present application.
  • a dielectric layer 207 is formed on the hole wall of the through hole 205, and the dielectric layer 207 covers the entire through hole 205.
  • the hole wall; that is, the dielectric layer 207 is tubular in the through hole 205, and the dielectric layer 207 is directly in contact with the hole wall of the through hole 205.
  • a gate pillar 209 is formed in the through hole 205 , the dielectric layer 207 is located between the gate pillar 209 and the wall of the through hole 205 , and the dielectric layer 207 is in contact with the gate pillar 209 .
  • FIG. 30 is a schematic structural diagram of the memory array manufacturing method provided by the embodiment of the present application after using connection holes to remove the first isolation layer. Please refer to FIG. 30 to remove the first isolation layer 203 through the connection holes 2041 to form the second gap layer 308 .
  • Figure 31 is a schematic structural diagram after forming the third isolation layer in the memory array manufacturing method provided by the embodiment of the present application. Please refer to Figure 31.
  • a channel layer 208 is formed on the side wall of the second gap layer 308, and the channel layer 208 covers The second gap layer 308 is on the corresponding dielectric layer 207, the electrode plate 2022 and the first intermediate layer 301.
  • a third isolation layer 210 may be formed in the second void layer 308 through the connection hole 2041, and the third isolation layer 210 fills the second void layer 308.
  • the channel layer 208 formed at this time includes a first channel layer 2081 in contact with the dielectric layer 207, a second channel layer 2082 in contact with the electrode plate 2022, and a third channel in contact with the first intermediate layer 301.
  • the channel layer 2083, the first channel layer 2081, the second channel layer 2082 and the third channel layer 2083 are an integrated structure.
  • the channel layer 208 is disposed in the second gap layer 308, which can prevent the channel layer 208 from occupying the space of the through hole 205, increases the area of the dielectric layer 207 in the through hole 205, and thereby improves the ability of the dielectric layer 207 to store electrons. ability.
  • Figure 32 is a schematic structural diagram after forming the first electrode layer and the conductor in the memory array manufacturing method provided by the embodiment of the present application. Please refer to Figure 32.
  • the projection of the connection hole 2041 on the substrate 10 is located on the electrode plate 2022. Outside the projection on the substrate 10 , after the third isolation layer 210 is formed, the first intermediate layer 301 can be removed through the connection holes 2041 to form a third void layer. Then, conductive material is filled in the connection holes 2041 and the third gap layer to form the first electrode layer 204 and the conductor 2042 connecting each first electrode layer 204.
  • the electrical connection between adjacent first electrode layers 204 can be achieved through the conductor 2042, which has a simple structure and is easy to manufacture.
  • connection hole 2041 when forming the third isolation layer 210, part of the insulating material will be filled in the connection hole 2041.
  • the insulating material in the connection hole 2041 can be removed before removing the first intermediate layer 301 to avoid the influence of the insulating material. The subsequent process is carried out.
  • conductive connectors can be formed to connect adjacent electrode plates 2022 (for specific steps, please refer to Scenario 1), thereby forming a memory array as shown in FIG. 5 .
  • Figure 33 is a schematic structural diagram of the memory array manufacturing method provided by the embodiment of the present application after using through holes to form gaps. Please refer to Figure 33.
  • the difference between this scenario and Scenario 1 and Scenario 2 is that a gate is formed in the through hole 205.
  • the pole 209 also previously includes removing part of the first isolation layer 203 through the through hole 205 to form a gap 2032 extending within the first isolation layer 203 .
  • FIG. 34 is a schematic structural diagram after the channel layer is formed in the memory array manufacturing method provided by the embodiment of the present application. Please refer to FIG.
  • a second channel layer 2082 is formed on the sidewall, the first channel layer 2081 and the second channel layer 2082 are in contact, and the first channel layer 2081 and the second channel layer 2082 constitute the channel layer 208 .
  • the material of the first channel layer 2081 and the second channel layer 2082 can be the same, so that the first channel layer 2081 and the second channel layer 2082 can be formed at the same time, thereby simplifying the manufacturing difficulty of the memory array. .
  • the first channel layer 2081 and the second channel layer 2082 contact to form an integrated structure, which can reduce the resistance between channel layers 2082.
  • Figure 35 is a schematic structural diagram after forming the dielectric layer in the memory array manufacturing method provided by the embodiment of the present application. Please refer to Figure 35.
  • the first channel layer 2081 and the second channel layer 2082 are formed, the first channel layer A first dielectric layer 2071 is formed on the second channel layer 2081, and a second dielectric layer 2072 is formed on the second channel layer 2082.
  • the first dielectric layer 2071 and the second dielectric layer 2072 are in layer contact. That is to say, the first dielectric layer 2071 covers the first channel layer 2081, and the second dielectric layer 2072 covers the second channel layer 2082.
  • the first dielectric layer 2071 and the second dielectric layer 2072 may be made of the same material, so that the first dielectric layer 2071 and the second dielectric layer 2072 may be formed at the same time, and after the first dielectric layer 2071 and the second dielectric layer 2072 are formed, the first The dielectric layer 2071 and the second dielectric layer 2072 are in contact to form an integrated structure.
  • Figure 36 is a schematic structural diagram after forming gate pillars in the memory array manufacturing method provided by the embodiment of the present application. As shown in Figure 36, after forming the first channel layer 2081 and the second channel layer 2082, in the through hole 205 The conductive material is filled in the gap 2032 to form the extension portion 2091 located in the gap 2032 and the gate pillar 209 located in the through hole 205, and the extension portion 2091 is in contact with the gate. It can be understood that the extension part 2091 and the gate post 209 can be made of the same material. Accordingly, the extension part 2091 and the gate post 209 can be formed at the same time, and the extension part 2091 and the gate post 209 form an integrated structure after contact to reduce the Extension 2091 and gate post 209.
  • the second dielectric layer 2072 and the second channel layer 2082 in the gap 2032 also form a conductive channel. , which can increase the area of the conductive channel, thereby increasing the turn-on voltage of the memory transistor, thereby improving the performance of the memory array.
  • the first intermediate layer 301 is replaced with the first electrode layer 204, and a conductive connector is formed to connect the adjacent electrode plates 2022 (for specific steps, please refer to Scenario 1 and Scenario 2), and then the formation is shown in Figure 7 storage array.
  • Figure 37 is a circuit diagram of a memory array provided by an embodiment of the present application. As shown in Figure 37, an embodiment of the present application also provides a memory array, including a memory string 100.
  • the memory string 100 includes a plurality of memory transistors 101 arranged in sequence.
  • the gate of the storage transistor 101 is electrically connected. For example, the gates of each storage transistor 101 may be connected through the gate line WL.
  • this embodiment is not limited to this, and the gates of each storage transistor 101 may also be electrically connected through other structures.
  • the memory array in this embodiment also includes a first electrode line 2043 and a plurality of second electrode lines 2021.
  • the first electrode line 2043 is electrically connected to the first electrode in each memory transistor 101 in the memory string 100.
  • a second electrode line 2021 is electrically connected to the second electrode of a storage transistor 101 in the memory string 100, so that data can be written into the corresponding storage transistor 101 through the second electrode line 2021, or data can be written into the corresponding storage transistor 101 through the second electrode line 2021. Read data.
  • the first electrode may be the source electrode of each storage transistor 101, and correspondingly, the second electrode may be the drain electrode of each storage transistor 101.
  • the first electrode is the drain of each storage transistor 101, and correspondingly, the second electrode is the source of each storage transistor 101.
  • multiple storage strings 100 there may be multiple storage strings 100, and multiple storage strings 100 may improve the data storage capacity of the storage array.
  • each storage transistor 101 in the memory string 100 is electrically connected, the first electrode line 2043 is electrically connected to the first electrode of each storage transistor 101 in the memory string 100, and each second electrode line 2021 It is electrically connected to the second electrode of one storage transistor 101 in the storage string 100; when reading data, power can be supplied to the first electrode line 2043 and the gate of each storage transistor 101 in the storage string 100, so that the storage string
  • Each storage transistor 101 in 100 is in a data-readable state, and the data in the storage transistor 101 corresponding to the second electrode line 2021 can be read through the second electrode line 2021 without turning on each of the storage transistors 100 in the storage string 100.
  • the storage transistor 101 improves the data reading speed.
  • Embodiments of the present application also provide a reading and writing method for a storage array, wherein the storage array includes a storage string, the storage string includes a plurality of storage transistors, and each storage transistor is used to store data.
  • the memory array further includes a substrate, and the plurality of memory transistors in the memory string may be spaced apart in a direction substantially perpendicular to the substrate. There can be multiple storage strings to improve the data storage capacity of the storage array.
  • the storage array in this embodiment can be the storage array in the above embodiment.
  • the storage array can also be other storage arrays, which is not limited in this embodiment.
  • Figure 38 is a flow chart of the reading and writing method provided by the embodiment of the present application. Please refer to Figure 38.
  • the reading and writing method provided by this embodiment, reading the data in the storage transistor includes:
  • S201 Apply a first voltage to the gate electrode of each storage transistor in the memory string and the first electrode of each storage transistor.
  • the first electrode may be the source or drain of the storage transistor, which is not limited in this embodiment.
  • the reading and writing method in this embodiment further includes:
  • the first electrode is the source of the storage transistor, and correspondingly, the second electrode is the drain of the storage transistor; in other implementations, the first electrode is the drain of the storage transistor, and correspondingly, the second electrode is the drain of the storage transistor.
  • the electrode is the source of the storage transistor.
  • the reading and writing method in this embodiment also includes:
  • the storage transistor is in an on state; by analyzing the current, the data in the storage transistor can be obtained.
  • the storage transistor if the data stored in the storage transistor is "1", electrons are stored in the dielectric layer of the storage transistor, and under the action of the first voltage and the electrons, the storage transistor is in an on state, and the current obtained at this time is greater than the preset value. If the data stored in the storage transistor is "0", no electrons are stored in the dielectric layer of the storage transistor, and under the action of the first voltage, the storage transistor cannot be turned on, and the current obtained at this time is less than the preset value, and the data stored in the storage transistor can be obtained by analyzing the current.
  • the data stored in the storage transistor can be "0"
  • electrons are stored in the dielectric layer of the storage transistor.
  • the storage transistor Under the action of the first voltage and electrons, the storage transistor is in an on state, and the current obtained at this time is greater than the preset value. If the data stored in the storage transistor is "1" and there are no electrons stored in the dielectric layer of the storage transistor, the storage transistor cannot be turned on under the action of the first voltage, and the current obtained at this time is less than the preset value.
  • each storage transistor in the storage string is in a state where data can be read, and the data stored in the storage transistor can be read through the second electrode corresponding to the storage transistor, without the need for each storage transistor in the storage string to be in an on state. , improving the data reading speed.
  • writing data into the storage transistor includes: applying a second voltage to the gate electrode of each storage transistor in the storage string and the second electrode of the storage transistor to be written data, so that the storage transistor to be written data is in an on state to write first data into the storage transistor to which data is to be written; or, to apply a third voltage to the gate of each storage transistor in the storage string and the second electrode of the storage transistor to which data is to be written, The third voltage is less than the second voltage, so as to write the second data into the storage transistor where the data is to be written.
  • a second voltage may be applied to the gate and the second electrode of the storage transistor, so that the storage transistor is in an on state. Under the action of the second voltage, electrons are injected into the dielectric layer of the storage transistor and retained in the dielectric layer, so that the first data is stored in the storage transistor. If the second voltage is applied to the gate and a third voltage is applied to the second electrode of the storage transistor, the third voltage being lower than the second voltage, electrons will not be injected into the dielectric layer, so that the second data is stored in the storage transistor.
  • first data may be “1", and correspondingly, the second data may be “0"; or, the first data may be "0", and correspondingly, the second data may be "1".
  • connection should be understood in a broad sense.
  • it can be a fixed connection or an integral connection; it can also be It can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediary, or an internal connection between two components.
  • connection should be understood in a broad sense.
  • it can be a fixed connection or an integral connection; it can also be It can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediary, or an internal connection between two components.

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Abstract

Les modes de réalisation de la présente demande appartiennent au domaine technique des dispositifs de mémoire, et concernent en particulier un réseau de mémoire et son procédé de fabrication, une mémoire, un dispositif électronique et un procédé de lecture-écriture. Les modes de réalisation de la présente demande visent à résoudre le problème de lecture lente de données de réseaux de mémoire. Dans le réseau de mémoire, le procédé de fabrication de réseau de mémoire et le procédé de lecture-écriture décrits dans les modes de réalisation de la présente demande, chaque couche de dispositif comprend une première couche d'électrode, une première couche d'isolation et une plaque d'électrode qui sont empilées ; et les premières couches d'électrode sont électriquement connectées l'une à l'autre. Pendant la lecture de données, les premières couches d'électrode et un pilier de grille peuvent être alimentés, ce qui permet à chaque transistor de mémoire formé par le pilier de grille et à chaque couche de dispositif d'être dans un état lisible par des données ; au moyen des plaques d'électrode, des données dans les transistors de mémoire correspondant aux plaques d'électrode peuvent alors être lues, de sorte que tous les transistors de mémoire formés par le pilier de grille et les couches de dispositif doivent être dans un état de mise sous tension, ce qui permet d'augmenter la vitesse de lecture de données.
PCT/CN2023/103514 2022-09-21 2023-06-28 Réseau de mémoire et son procédé de fabrication, mémoire, dispositif électronique et procédé de lecture-écriture WO2024060758A1 (fr)

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CN202211153886.4 2022-09-21

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KR101056113B1 (ko) * 2010-07-02 2011-08-10 서울대학교산학협력단 분리 절연막 스택으로 둘러싸인 차폐전극을 갖는 3차원 수직형 메모리 셀 스트링, 이를 이용한 메모리 어레이 및 그 제조 방법
KR20120085528A (ko) * 2011-01-24 2012-08-01 김진선 3차원 비휘발성 메모리 소자, 그 동작 방법 및 그 제조 방법
CN113284898A (zh) * 2020-01-31 2021-08-20 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN113488504A (zh) * 2020-06-18 2021-10-08 台湾积体电路制造股份有限公司 存储器器件及其形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101056113B1 (ko) * 2010-07-02 2011-08-10 서울대학교산학협력단 분리 절연막 스택으로 둘러싸인 차폐전극을 갖는 3차원 수직형 메모리 셀 스트링, 이를 이용한 메모리 어레이 및 그 제조 방법
KR20120085528A (ko) * 2011-01-24 2012-08-01 김진선 3차원 비휘발성 메모리 소자, 그 동작 방법 및 그 제조 방법
CN113284898A (zh) * 2020-01-31 2021-08-20 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN113488504A (zh) * 2020-06-18 2021-10-08 台湾积体电路制造股份有限公司 存储器器件及其形成方法

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