WO2024055781A1 - Super-junction device integrated with gate-drain capacitor and fabrication method - Google Patents

Super-junction device integrated with gate-drain capacitor and fabrication method Download PDF

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Publication number
WO2024055781A1
WO2024055781A1 PCT/CN2023/111899 CN2023111899W WO2024055781A1 WO 2024055781 A1 WO2024055781 A1 WO 2024055781A1 CN 2023111899 W CN2023111899 W CN 2023111899W WO 2024055781 A1 WO2024055781 A1 WO 2024055781A1
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Prior art keywords
gate
polysilicon
area
field plate
region
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PCT/CN2023/111899
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French (fr)
Chinese (zh)
Inventor
赵东艳
肖超
陈燕宁
邵瑾
董广智
付振
刘芳
张泉
尹强
田俊
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北京芯可鉴科技有限公司
北京智芯微电子科技有限公司
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Publication of WO2024055781A1 publication Critical patent/WO2024055781A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side

Definitions

  • the present application relates to the field of semiconductors, and specifically to a superjunction device with integrated gate-drain capacitance and a manufacturing method of the superjunction device.
  • Power semiconductor devices are widely used in clean and green energy fields.
  • Traditional power semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) device, IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) device, SGT (Shield Gate Trench, Shield Gate Trench) ) device.
  • Superjunction (SJ) devices use a charge-balanced withstand voltage layer structure, which breaks the so-called "silicon limit”. Compared with traditional power semiconductor devices, it can significantly reduce the on-resistance of the device and improve system efficiency.
  • the charge balance withstand voltage structure of the superjunction device will cause the depletion layer to expand along the horizontal and vertical directions, causing the capacitance of the device to decrease sharply as the voltage increases, showing serious nonlinear characteristics.
  • the capacitive nonlinear characteristics of superjunction devices can cause problems such as uncontrollable gates, voltage and current oscillations, device voltage breakdown, and EMI (electromagnetic interference) during the switching process of superjunction devices.
  • the existing technology mainly improves the above problems at two levels: system and device.
  • system level on the one hand, by adjusting the gate resistance connected externally to the device, the dv/dt (voltage change rate) and di/dt (current change rate) during the switching process of the device are controlled; on the other hand, by adjusting the gate-source or drain A high-voltage capacitor is connected in parallel between the sources to adjust the switching speed of the device.
  • the gate-drain capacitance is integrated in the active area of the device to adjust the switching speed of the device; on the other hand, the internal gate resistor is integrated at the gate pad position of the device to control the dv/dt and dv/dt during the switching process of the device. di/dt.
  • the above two methods will occupy the effective area of the active area and affect the output current capability of the device.
  • embodiments of the present application provide a superjunction device with integrated gate-drain capacitance and a manufacturing method.
  • a superjunction device with integrated gate-drain capacitance including an active region and a terminal region.
  • the active region includes a source electrode, a gate electrode, and a body region.
  • the terminal region It includes a cut-off ring region, the terminal region is integrated with a flat capacitor structure; the flat capacitor structure is connected to the gate and the cut-off ring zone, and the flat capacitor structure serves as the gate-drain capacitance of the superjunction device.
  • the plate capacitor structure includes N levels of plate capacitors connected in series.
  • Each level of plate capacitor includes a polysilicon field plate, a metal field plate and an interlayer dielectric layer, where N is a positive integer greater than 1.
  • each level of flat capacitor is connected to the polysilicon field plate of the subsequent level of flat capacitor through the contact hole, or the polysilicon field plate of each level of flat capacitor is connected to the metal field plate of the subsequent level of flat capacitor through the contact hole. connected.
  • a transition region is included, and a gate bus connected to the gate is provided in the transition region.
  • the polysilicon field plate of the first-level flat capacitor is connected to the gate bus line, and the metal field plate of the N-th level flat capacitor is connected to the cutoff ring. Districts are connected.
  • the terminal area is also integrated with a resistive structure, and the resistive structure is disposed between any two series-connected plate capacitors.
  • the resistor structure is a polysilicon resistor, and the polysilicon resistor is formed of non-doped polysilicon material or doped polysilicon material.
  • the polysilicon resistor is connected to the polysilicon field plate of the flat capacitor.
  • the terminal area further includes an integrated diode, and the integrated diode is located between any two series-connected plate capacitors.
  • the integrated diode is connected to the polysilicon field plate of the flat capacitor.
  • the integrated diode includes one PN junction or multiple back-to-back PN junctions.
  • a method for manufacturing a superjunction device is provided.
  • the superjunction device is the superjunction device with integrated gate-to-drain capacitance provided in the first aspect.
  • the method includes:
  • the polysilicon gate electrode in the active area and the polysilicon field plate in the terminal area are formed;
  • the source metal of the active area and the metal field plate of the terminal area are formed at the same time.
  • the method further includes: forming a field oxide layer on the drift region; defining the patterns of the active region, the terminal region and the cut-off ring region through photolithography; and using wet etching to remove the fields of the active region and the cut-off ring region. oxide layer.
  • the simultaneous formation of the polysilicon gate in the active area and the polysilicon field plate in the terminal area includes: thermally oxidizing and growing a gate oxide layer in the active area; depositing polysilicon; and using a dry etching process to simultaneously form the active area. the polysilicon gate and the polysilicon field plate in the termination areas.
  • the method further includes: using a polysilicon gate as a barrier layer, injecting boron ions into a preset region and pushing the junction at high temperature to form a P-type body region of the active region; injecting arsenic ions into the preset region and pushing the junction, The N-type body region of the active region and the cut-off ring region of the terminal region are formed.
  • the deposition forms an interlayer dielectric layer, including:
  • a dielectric material is deposited on the surface of the semiconductor substrate where the polysilicon gate electrode and polysilicon field plate are formed to form an interlayer dielectric, and a reflow process is used for surface planarization; the interlayer dielectric is etched to form an interlayer dielectric layer and contact holes.
  • the method further includes: forming one or more back-to-back PN junctions in the terminal area to form an integrated diode.
  • the method further includes: forming a polysilicon resistor in the process of forming the polysilicon field plate in the terminal area;
  • the process of forming a polysilicon field plate in the terminal area to form a polysilicon resistor includes: depositing non-doped polysilicon, defining a pattern area of the polysilicon resistor through photolithography, and performing non-doped polysilicon processing on the non-doped polysilicon outside the pattern area of the polysilicon resistor.
  • Phosphorus ion implantation, undoped polysilicon without phosphorus ion implantation is used as a polysilicon resistor; alternatively, doped polysilicon is deposited, the doped polysilicon pattern area is defined by photolithography, and the required width-to-length ratio is adjusted by adjusting the doped polysilicon pattern of doped polysilicon resistors.
  • the superjunction device is an SJ-IGBT device, an SJ-MOSFET device or an SJ-SGT device.
  • the superjunction device provided by the embodiment of the present application integrates a flat capacitor structure connected to the gate and the cutoff ring area in the terminal area.
  • This flat capacitor structure serves as a gate-drain capacitor, which can reduce the nonlinear characteristics of the superjunction device capacitance, thereby increasing
  • the controllability of the gate drive of the superjunction device slows down the voltage and current ringing of the superjunction device, prevents voltage breakdown and damages the device, and improves the EMI quality of the device.
  • integrating gate-to-drain capacitance (feedback capacitance) in the terminal area of the superjunction device does not require additional area in the active area of the device, will not cause degradation of other parameters of the device, and will not affect the output current capability of the device; Moreover, integrating gate-to-drain capacitance in the terminal area of a superjunction device can effectively reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the device, and is less likely to cause switching oscillation of the device.
  • ESR equivalent series resistance
  • ESL equivalent series inductance
  • Figure 1 is a schematic plan view of a superjunction device with integrated gate-drain capacitance provided by an embodiment of the present application
  • Figure 2 is a schematic cross-sectional view of a superjunction device with integrated gate-drain capacitance provided in Embodiment 1 of the present application;
  • Figure 3 is a schematic cross-sectional view of a superjunction device with integrated gate-drain capacitance provided in Embodiment 1 of the present application;
  • Figure 4 is an equivalent symbol diagram of a superjunction device with integrated gate-drain capacitance provided in Embodiment 1 of the present application;
  • Figure 5 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and resistance provided in Embodiment 2 of the present application;
  • Figure 6 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and resistance provided in Embodiment 2 of the present application;
  • Figure 7 is an equivalent symbol diagram of a superjunction device integrating gate-to-drain capacitance and resistance provided in Embodiment 2 of the present application;
  • Figure 8 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and diode provided in Embodiment 3 of the present application;
  • Figure 9 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and diode provided in Embodiment 3 of the present application;
  • Figures 10 to 13 are equivalent symbol diagrams of a superjunction device integrating gate-drain capacitance and diode provided in Embodiment 3 of the present application;
  • Figure 14 is a comparison chart of the capacitance curves of existing superjunction devices and traditional power MOSFET devices
  • Figure 15 is a comparison chart of feedback capacitance curves between a superjunction device with integrated gate-drain capacitance and an existing superjunction device provided by an embodiment of the present application;
  • FIG. 16 is a flow chart of a manufacturing method of a superjunction device provided by an embodiment of the present application.
  • connection In this application, unless otherwise clearly stated and limited, the terms “installation”, “connection”, “connection”, “fixing” and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated; it can be mechanical connection, electrical connection or mutual communication; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction between two elements.
  • connection connection
  • fixing and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated; it can be mechanical connection, electrical connection or mutual communication; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction between two elements.
  • the specific meanings of the above terms in this application can be understood according to specific circumstances.
  • the existing technology mainly improves the problem of capacitance nonlinear characteristics of superjunction devices through two levels: system and device.
  • system level on the one hand, by adjusting the gate resistance connected externally to the device, the dv/dt (voltage change rate) and di/dt (current change rate) during the switching process of the device are controlled; on the other hand, by adjusting the gate-source or drain A high-voltage capacitor is connected in parallel between the sources to adjust the switching speed of the device.
  • the gate-drain capacitance is integrated in the active area of the device to adjust the switching speed of the device; on the other hand, the internal gate resistor is integrated at the gate pad position of the device to control the dv/dt and dv/dt during the switching process of the device. di/dt.
  • the above two methods will occupy the effective area of the active area and affect the output current capability of the device.
  • embodiments of the present invention provide a superjunction device with integrated gate-drain capacitance, which includes an active region and a terminal region.
  • the active region includes a source, a gate, and a body region.
  • the terminal area includes a cut-off ring area.
  • the terminal area is integrated with a flat capacitor structure.
  • the flat capacitor structure is connected to the gate and the cut-off ring area.
  • the flat capacitor structure serves as the gate-drain capacitance of the superjunction device.
  • the embodiment of the present application integrates a flat capacitor structure connected to the gate and the cutoff ring area in the terminal area of the super junction device.
  • This flat capacitor structure serves as a gate-drain capacitor, which can reduce the nonlinear characteristics of the super junction device capacitance, thereby increasing the gate
  • the driver controls the gate of the superjunction device, slows down the voltage and current ringing of the superjunction device, prevents voltage breakdown from damaging the device, and improves the EMI quality of the device.
  • integrating gate-to-drain capacitance (feedback capacitance) in the terminal area of the superjunction device does not require additional area in the active area of the device, will not cause degradation of other parameters of the device, and will not affect the output current capability of the device; Moreover, integrating gate-to-drain capacitance in the terminal area of a superjunction device can effectively reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the device, and is less likely to cause switching oscillation of the device.
  • ESR equivalent series resistance
  • ESL equivalent series inductance
  • FIG. 1 is a schematic plan view of a superjunction device with integrated gate-drain capacitance provided by an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional view of a superjunction device with integrated gate-drain capacitance provided by Embodiment 1 of the present application.
  • Figure 1 is a schematic plan view
  • Figure 2 is a cross-sectional view along the A-A' direction of Figure 1.
  • the superjunction device provided by this embodiment includes an active region, a transition region and a terminal region.
  • the active region, transition region and terminal region are all provided with N pillars 101 and P pillars 102 arranged alternately.
  • the alternately arranged N pillars 101 and P pillars 102 constitute a drift region.
  • the alternating N-pillars 101 and P-pillars 102 in the transition area and the terminal area have the same width as the alternating N-pillars 101 and P-pillars 102 in the active area.
  • the active area includes a source electrode 113, a gate electrode 114 and a body area 115.
  • the terminal area includes a cutoff ring area 108, and the terminal area is integrated with a plate capacitor structure.
  • a field oxide layer 103 Above the drift region in the terminal region is a field oxide layer 103, and above the field oxide layer 103 is a plate capacitor structure.
  • the two electrodes of the flat capacitor structure are connected to the gate electrode 114 of the active region and the cutoff ring region 108 of the terminal region.
  • the cutoff ring region 108 is connected to the drain of the superjunction device (not shown in the drawings).
  • the flat capacitor structure As the gate-to-drain capacitance of superjunction devices.
  • a gate bus 111 connected to the gate 114 of the active area is provided in the transition area, and is connected to the gate pad (G) of the device through the gate bus 111, so that the gate pad Electrical signals can reach each gate in the active area at the same time, ensuring that the transistors in the active area can be turned on at the same time.
  • the body region 115 can be limited to the active region, or it can span both the active region and the transition region.
  • the plate capacitor structure consists of multiple levels of plate capacitors connected in series. In this embodiment, the flat capacitor structure includes six levels of flat capacitors connected in series. Each level of flat capacitor includes a polysilicon field plate 105, a metal field plate 106 and an interlayer Dielectric layer 104.
  • the metal field plate 106 of each level of flat capacitor is connected to the polysilicon field plate 105 of the subsequent level of flat capacitor through contact holes 107, as shown in FIG. 2 .
  • the polysilicon field plate 105 of the first-level flat capacitor is connected to the gate bus 111 in the transition area, and the metal field plate 106 of the sixth-level flat capacitor is connected to the cut-off ring area 108 of the terminal area.
  • the position of the contact hole 107 in FIG. 1 may be at a corner position of the overall layout, or may be at a horizontal and/or vertical position.
  • the polysilicon field plate 105 of each level of flat capacitor is connected to the metal field plate 106 of the subsequent level of flat capacitor through contact holes 107, as shown in FIG. 3 .
  • the metal field plate 106 of the first-level flat capacitor is connected to the gate bus 111 in the transition area, and the polysilicon field plate 105 of the last-level flat capacitor is connected to the cut-off ring area 108 of the terminal area.
  • the spacing of the metal field plates of the multiple series-connected flat capacitors is in a decreasing distribution
  • the spacing of the polysilicon field plates of the multiple series-connected flat capacitors is in a decreasing distribution.
  • the spacing between every two levels of polysilicon field plates is 0.1um ⁇ 8.0um
  • the spacing between every two levels of metal field plates is 0.1um ⁇ 8.0um.
  • the spacing between the metal field plates of every two levels of flat capacitors can be equal or increasing, or first decreasing and then increasing
  • the spacing between the polycrystalline silicon field plates of every two levels of flat capacitors can be equal or increasing, or first decreasing and then increasing.
  • the design criteria for the spacing of metal field plates or the spacing of polysilicon field plates are determined based on the capacitance value of the flat capacitor structure that needs to be integrated. If the capacitance value of the flat capacitor structure that needs to be integrated is larger, the spacing will be smaller; if it needs to be integrated The smaller the capacitance value of the plate capacitor structure, the larger the spacing. Under the same terminal area conditions, the more plate capacitors are integrated, the minimum size of the spacing is limited by the processing technology node, and the typical value of the spacing can be 0.1um.
  • the thickness of the field oxide layer ranges from 0.1um to 2.0um.
  • the thickness of the polysilicon field plate ranges from 0.1um to 1.2um, and the width ranges from 1.0um to 10.0um.
  • the thickness of the metal field plate ranges from 1um to 6um, and the width ranges from 1.0um to 10.0um.
  • the capacitances C GS0 , CGD0 and C DS0 of the superjunction device respectively represent the intrinsic gate-source capacitance C GS0 , the intrinsic gate-drain capacitance C GD0 and the intrinsic drain-source capacitance C DS0 inside the super-junction device.
  • the polycrystalline silicon field plate and the metal field plate in the terminal area of the superjunction device form a flat capacitor.
  • the two electrodes of the capacitor are connected to the gate and the cut-off ring area respectively. Since the cut-off ring area (channel cut-off area) and the drain metal have The same potential, so the flat capacitor is equivalent to the gate-drain capacitance C GD1 in Figure 4.
  • the gate-drain capacitance C GD1 is connected in parallel with the intrinsic gate-drain capacitance C GD0 .
  • the charge balance structure inside the superjunction device causes the device capacitance to change sharply with voltage, which is highly nonlinear.
  • the principle of the superjunction device provided in this embodiment to improve the nonlinear characteristics of capacitance is as follows: Referring to Figure 14, the superjunction MOS device output capacitance C oss (including gate-drain capacitance C GD and drain-source capacitance C DS ) and feedback capacitance C rss (i.e. The gate-drain capacitance C GD ) becomes smaller as the drain-source voltage V DS increases.
  • FIG. 15 shows a comparison diagram of the feedback capacitance curves of the superjunction device with integrated gate-leakage capacitance and the existing superjunction device provided by the embodiment of the present application.
  • the feedback capacitance C rss of the superjunction device with integrated gate-leakage capacitance is equivalent to the gate Drain capacitance C GD1 + intrinsic gate-to-drain capacitance C GD0
  • the feedback capacitance C rss of existing superjunction devices is the intrinsic gate-to-drain capacitance C GD0 .
  • the plate capacitance C GD1 introduced in the terminal area of the superjunction device can slow down the sharp change of capacitance with voltage and reduce the nonlinear characteristics of the feedback capacitance C rss of the superjunction device.
  • the increase rate of the drain-source voltage V DS is determined by the gate-to-drain capacitance CGD (feedback capacitance).
  • V GD The larger the gate-to-drain capacitance C GD , the smaller the increase rate of drain-source voltage V DS (dV DS ), the stronger the gate controllability, the smaller the voltage and current oscillation, and the smaller the electromagnetic interference to other parts of the system.
  • the size of the gate-to-drain capacitance C GD1 can be adjusted by adjusting the area of the overlapping area of the polysilicon field plate and the metal field plate, and/or adjusting the interlayer dielectric layer between the polysilicon field plate and the metal field plate.
  • the thickness of the gate-drain capacitor C GD1 can be used to adjust the capacitance size.
  • the typical value range of the gate-drain capacitor C GD1 is 0.1pF ⁇ 10pF.
  • the gate-to-drain capacitance CGD1 can be determined as follows.
  • the spacing of the metal field plates of the flat capacitor structure are equal, the spacing of the polysilicon field plates is also equal, and the gate-to-drain capacitance C GD1 is equivalent to six series-connected plate capacitors.
  • C GD1 ⁇ S/(6d);
  • C GD1 ⁇ S/(Nd);
  • the area of the overlapping area of the polysilicon field plate and the metal field plate or the thickness of the interlayer dielectric layer can be calculated through the above formula.
  • the area S of the overlapping area of the polysilicon field plate and the metal field plate ranges from 0.5um to 100um
  • the thickness d of the interlayer dielectric layer ranges from 0.1um to 2um.
  • FIG. 5 is a schematic cross-sectional view of a superjunction device integrating gate-to-drain capacitance and resistance provided in Embodiment 2 of the present application.
  • a schematic plan view of the superjunction device of Embodiment 2 can be seen in FIG. 1 , and it can also be understood that FIG. 5 is a cross-sectional view along the A-A’ direction of FIG. 1 .
  • the superjunction device provided by this embodiment includes an active region, a transition region and a terminal region.
  • the active region, transition region and terminal region are all provided with N pillars 101 and P pillars 102 arranged alternately.
  • the alternately arranged N pillars 101 and P pillars 102 constitute a drift region.
  • the alternating N-pillars 101 and P-pillars 102 in the transition area and the terminal area have the same width as the alternating N-pillars 101 and P-pillars 102 in the active area.
  • the active area includes a source electrode 113, a gate electrode 114 and a body area 115.
  • the terminal area includes a cutoff ring area 108, and the terminal area is integrated with a plate capacitor structure.
  • a field oxide layer 103 Above the drift region in the terminal region is a field oxide layer 103, and above the field oxide layer 103 is a plate capacitor structure.
  • the two electrodes of the flat capacitor structure are connected to the gate electrode 114 of the active region and the cutoff ring region 108 of the terminal region.
  • the cutoff ring region 108 is connected to the drain of the superjunction device (not shown in the drawings).
  • the flat capacitor structure As the gate-to-drain capacitance of superjunction devices.
  • a gate bus 111 connected to the gate 114 of the active area is provided in the transition area.
  • the gate bus 111 is connected to the gate pad (G) of the device, so that the electrical signals from the gate pad can reach the active area at the same time.
  • G gate pad
  • Each gate of the active area ensures that the transistors in the active area can be turned on at the same time.
  • the body region 115 can be limited to the active region, or it can span both the active region and the transition region.
  • the plate capacitor structure includes six levels of plate capacitors connected in series. Each level of plate capacitor includes a polysilicon field plate 105 , a metal field plate 106 and an interlayer dielectric layer 104 .
  • the metal field plate 106 of each level of flat capacitor is connected to the polysilicon field plate 105 of the subsequent level of flat capacitor through contact holes 107 .
  • the polysilicon field plate 105 of the first-level flat capacitor is connected to the gate bus 111 in the transition area, and the metal field plate 106 of the sixth-level flat capacitor is connected to the cut-off ring area 108 of the terminal area.
  • the polysilicon field plate of each level of flat capacitor is connected to the metal field plate of the subsequent level of flat capacitor through contact holes.
  • the metal field plate of the first-level flat capacitor is connected to the gate bus in the transition area, and the polysilicon field plate of the last-level flat capacitor is connected to the cut-off ring area in the terminal area.
  • the terminal area of the superjunction device is also integrated with a resistive structure, which can be placed between any two series-connected plate capacitors.
  • the resistive structure is located between the first-level plate capacitor and the gate bus 111 , and the first-level plate capacitor is connected to the gate bus 111 through the resistive structure.
  • the resistor structure is a polysilicon resistor 109, and the polysilicon resistor 109 is formed of undoped polysilicon material or doped polysilicon material.
  • the polysilicon resistor 109 is connected to the polysilicon field plate 105 of the flat capacitor.
  • the doping ion concentration of the polysilicon resistor 109 is different or the same as the doping ion concentration of the polysilicon field plate 105.
  • polysilicon material can be deposited in the corresponding area and then ion doped to form the polysilicon resistor 109. and the polysilicon field plate 105; different width-to-length ratios can also be set for the doped polysilicon to achieve the required resistance.
  • the capacitances C GS0 , CGD0 and C DS0 of the superjunction device respectively represent the intrinsic gate-source capacitance C GS0 , the intrinsic gate-drain capacitance C GD0 and the intrinsic drain-source capacitance C DS0 inside the super-junction device.
  • the polysilicon field plate and the metal field plate of the flat capacitor structure form a flat capacitor.
  • the polysilicon field plate and the metal field plate serve as the two electrodes of the capacitor.
  • One electrode is connected to the cutoff ring area, and the other electrode is connected to the gate through the resistor structure.
  • the flat capacitor structure Connected in series with the resistor structure to form an RC absorption circuit.
  • the equivalent of the flat capacitor is as shown in Figure 5
  • the gate-to-drain capacitance C GD1 the resistor structure is equivalent to the resistor R in Figure 5.
  • the RC absorption circuit composed of gate-drain capacitance C GD1 and resistor R is connected in parallel with the intrinsic gate-drain capacitance C GD0 , which can reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the device and eliminate parasitic equivalent series resistance. and equivalent series inductance to avoid causing switching oscillation of the device.
  • the terminal area integrates a series-connected flat capacitor structure and a resistor structure.
  • it can reduce the nonlinear characteristics of the superjunction device capacitance, increase the controllability of the device gate, and slow down the voltage of the device. , current ringing to prevent voltage breakdown and damage to the device, and improve the EMI quality of the device; on the other hand, integrated resistors can effectively reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the device, avoiding easy switching of the device. Shock.
  • ESR equivalent series resistance
  • ESL equivalent series inductance
  • FIG. 8 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and diode provided in Embodiment 3 of the present application.
  • a schematic plan view of the superjunction device in Embodiment 3 can be seen in FIG. 1 , and it can also be understood that FIG. 8 is a cross-sectional view along the A-A’ direction in FIG. 1 .
  • the superjunction device provided by this embodiment includes an active region, a transition region, and a terminal region.
  • the active region, transition region, and terminal region are all provided with alternately arranged N pillars 101 and P pillars 102.
  • the alternately arranged N pillars 101 and P pillars 102 constitute a drift region.
  • the alternating N-pillars 101 and P-pillars 102 in the transition area and the terminal area have the same width as the alternating N-pillars 101 and P-pillars 102 in the active area.
  • the active area includes a source electrode 113, a gate electrode 114 and a body area 115.
  • the terminal area includes a cutoff ring area 108, and the terminal area is integrated with a plate capacitor structure.
  • a field oxide layer 103 Above the drift region in the terminal region is a field oxide layer 103, and above the field oxide layer 103 is a plate capacitor structure.
  • the two electrodes of the flat capacitor structure are connected to the gate electrode 114 of the active region and the cutoff ring region 108 of the terminal region.
  • the cutoff ring region 108 is connected to the drain of the superjunction device (not shown in the drawings).
  • the flat capacitor structure As the gate-to-drain capacitance of superjunction devices.
  • a gate bus 111 connected to the gate 114 of the active area is provided in the transition area.
  • the gate bus 111 is connected to the gate pad (G) of the device, so that the electrical signals from the gate pad can reach the active area at the same time.
  • G gate pad
  • Each gate of the active area ensures that the transistors in the active area can be turned on at the same time.
  • the body region 115 can be limited to the active region, or it can span both the active region and the transition region.
  • the plate capacitor structure includes six levels of plate capacitors connected in series. Each level of plate capacitor includes a polysilicon field plate 105 , a metal field plate 106 and an interlayer dielectric layer 104 .
  • the metal field plate 106 of each level of flat capacitor is connected to the polysilicon field plate 105 of the subsequent level of flat capacitor through contact holes 107 .
  • the polysilicon field plate 105 of the first-level flat capacitor is connected to the gate bus 111 in the transition area, and the metal field plate 106 of the sixth-level flat capacitor is connected to the cut-off ring area 108 of the terminal area.
  • the polysilicon field plate of each level of flat capacitor is connected to the metal field plate of the subsequent level of flat capacitor through contact holes.
  • the metal field plate of the first-level flat capacitor is connected to the gate bus in the transition area, and the polysilicon field plate of the last-level flat capacitor is connected to the cut-off ring area in the terminal area.
  • the spacing of the metal field plates of multiple series-connected flat capacitors is in a decreasing distribution, and the spacing of the polysilicon field plates of multiple series-connected flat capacitors is in a decreasing distribution.
  • the spacing between every two levels of polysilicon field plates is 0.1um ⁇ 8.0um
  • the spacing between every two levels of metal field plates is 0.1um ⁇ 8.0um.
  • the spacing between the metal field plates of every two levels of flat capacitors may be equal or increasing, or first decrease and then increase.
  • the spacing between the polycrystalline silicon field plates of every two levels of flat capacitors may be equal or increasing, or first decrease and then increase.
  • the spacing between metal field plates or polysilicon field plates can be determined based on the capacitance value of the flat capacitor structure that needs to be integrated. If the capacitance value of the flat capacitor structure that needs to be integrated is larger, the spacing will be smaller; if the flat capacitor structure that needs to be integrated is larger, the spacing will be smaller; The smaller the capacitance value of the structure, the larger the spacing.
  • the terminal area of the superjunction device also includes an integrated diode 110, which is located between any two series-connected plate capacitors. As shown in Figure 9, the integrated diode 110 is connected to the polysilicon field plate 105 of the planar capacitor.
  • the integrated diode 110 includes one PN junction or multiple back-to-back PN junctions, and the PN junction may be formed of undoped polysilicon material or doped polysilicon material.
  • the capacitances C GS0 , C GD0 and C DS0 of the superjunction device respectively represent the intrinsic gate-source capacitance C GS0 , the intrinsic gate-drain capacitance C GD0 and the intrinsic drain-source capacitance C DS0 inside the super-junction device.
  • the polycrystalline silicon field plate and the metal field plate of the flat capacitor structure form a flat capacitor.
  • the polycrystalline silicon field plate and the metal field plate The field plate serves as two electrodes of the capacitor, one electrode is connected to the cutoff ring area, and the other electrode is connected to the gate through an integrated diode.
  • the plate capacitor is equivalent to the gate-drain capacitance CGD1 .
  • the rectifier circuit composed of the gate-drain capacitor CGD1 and the integrated diode 110 is connected in parallel with the intrinsic gate-drain capacitance CGD0 of the device.
  • the rectifier circuit provides different gate-drain capacitance values for the device to turn on and off the charge and discharge paths.
  • the optimization of dv/dt (voltage change rate) and di/dt (current change rate) during the turn-on and turn-off processes is divided into asymmetric switching speed optimization and symmetric switching speed optimization.
  • Figure 10 is an equivalent symbol diagram of asymmetric switching speed (turn-on speed is less than turn-off speed).
  • the anode of the integrated diode 110 is connected to the gate, and the cathode of the integrated diode 110 is connected to the plate capacitor as the gate drain capacitance C GD1 .
  • the turn-on speed of the device is slower than the turn-off speed.
  • Figure 11 is an equivalent symbol diagram of asymmetric switching speed (turn-on speed is greater than turn-off speed).
  • the anode of the integrated diode 110 is connected to the plate capacitor as the gate-drain capacitance C GD1 , and the cathode of the integrated diode 110 is connected to the gate.
  • the turn-on speed of the device is greater than the turn-off speed.
  • Figure 12 is the equivalent symbol diagram of symmetrical switching speed (common anode connection method).
  • the integrated diode 110 includes two back-to-back diodes, the anodes of the two diodes are connected together, the cathode of one diode is connected to the plate capacitor as the gate-drain capacitance C GD1 , and the cathode of the other diode is connected to the gate to Achieve symmetrical switching speed optimization.
  • Figure 13 is the equivalent symbol diagram of symmetrical switching speed (common cathode connection method).
  • the integrated diode 110 includes two back-to-back diodes, the cathodes of the two diodes are connected together, the anode of one diode is connected to the plate capacitor as the gate-drain capacitance C GD1 , and the anode of the other diode is connected to the gate to Achieve symmetrical switching speed optimization.
  • the terminal area integrates a flat capacitor structure and an integrated diode to form a rectifier circuit.
  • it can reduce the nonlinear characteristics of the capacitance of the superjunction device, increase the controllability of the device gate, and slow down the failure of the device.
  • Voltage and current ringing prevent voltage breakdown from damaging the device and improve the EMI quality of the device; on the other hand, the turn-on and turn-off speeds can be optimized respectively to achieve a balance between speed and power consumption.
  • the superjunction devices with integrated gate-drain capacitance provided in the above-mentioned Embodiments 1 to 3 can be applied to IGBT, MOSFET or SGT devices to form SJ-IGBT devices, SJ-MOSFET devices or SJ-SGT devices.
  • FIG. 16 is a flow chart of a manufacturing method of a superjunction device provided by an embodiment of the present application. As shown in Figure 16, this embodiment provides a method for manufacturing a superjunction device, which method includes the following steps:
  • an N-type silicon epitaxial layer or a P-type silicon epitaxial layer is grown on a semiconductor substrate, and the N-type silicon epitaxial layer or P-type silicon epitaxial layer is etched to form a deep trench.
  • the trench is filled with P-type silicon, or the deep trench of the P-type silicon epitaxial layer is filled with N-type silicon, thereby forming staggered P-pillars and N-pillars.
  • a field oxide layer is formed on the drift region, and the active region, transition region and terminal region are predefined.
  • the patterns of the active area, terminal area and cut-off ring area can be defined through photolithography, and the field oxide layer in the active area and cut-off ring area can be removed by wet etching.
  • a gate oxide layer is thermally oxidized and grown in the active area, polysilicon is deposited, and a dry etching process is used to simultaneously form the polysilicon gate in the active area, the gate bus line in the transition area, and the polysilicon field plate in the terminal area.
  • boron ions are injected into the preset area and pushed through at high temperature to form the P-type body region 1151 of the active area.
  • Arsenic ions are injected into the preset area and pushed through to form the N-type body region of the active area.
  • ILD Inter Layer Dielectric
  • step S3 a metal material is deposited on the semiconductor substrate to form a conductive metal layer, and the conductive metal layer is etched to simultaneously form the source metal of the active region and the metal field plate of the terminal region.
  • the method for manufacturing a superjunction device corresponding to the above-mentioned Embodiment 1 includes the following process flow:
  • the method further includes: forming a polysilicon resistor in the process of forming a polysilicon field plate in the terminal region. Specifically, in the above step S2, non-doped polysilicon is deposited, a pattern area of the polysilicon resistor is defined through photolithography, and phosphorus ions are implanted into the non-doped polysilicon outside the pattern area of the polysilicon resistor.
  • Polycrystalline silicon constitutes a polycrystalline silicon field plate, and undoped polycrystalline silicon that has not been implanted with phosphorus ions is used as a polycrystalline silicon resistor; alternatively, doped polycrystalline silicon is deposited, the doped polycrystalline silicon pattern area is defined by photolithography, and the width-to-length ratio of the doped polycrystalline silicon pattern is adjusted to obtain required doped polysilicon resistor.
  • the method further includes: forming a plurality of back-to-back PN junctions in the terminal region to form an integrated diode.
  • the method includes the following process flow:
  • Photolithography defines the area of the diode PN junction, and then phosphorus ions are implanted and annealed at high temperature to form one or more back-to-back PN junctions;
  • the above-mentioned manufacturing method of superjunction devices can form SJ-IGBT devices, SJ-MOSFET devices or SJ-SGT devices.

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Abstract

The present application relates to the field of semiconductors, and provides a super-junction device integrated with a gate-drain capacitor and a fabrication method. The super-junction device comprises: an active region and a terminal region. The active region comprises a source, a gate, and a body region. The terminal region comprises a cut-off ring region, and the terminal region is integrated with a flat-panel capacitor structure. The flat-panel capacitor structure is connected to the gate and the cut-off ring region, and the flat-panel capacitor structure is used as a gate-drain capacitor of the super-junction device. According to the present application, the terminal region is integrated with the flat-panel capacitor structure connected to the gate and cut-off ring region, and the flat-panel capacitor structure is used as a gate-drain capacitor, so that a nonlinear characteristic of a super-junction device capacitor can be reduced, the controllability of a gate driver on the gate of the super-junction device is improved, the voltage and current ringing of the super-junction device are slowed down, the device is prevented from being damaged by voltage breakdown, and the EMI quality of the device is improved.

Description

集成栅漏电容的超结器件及制造方法Superjunction device with integrated gate-drain capacitance and manufacturing method 技术领域Technical field
本申请涉及半导体领域，具体地涉及一种集成栅漏电容的超结器件以及一种超结器件的制造方法。The present application relates to the field of semiconductors, and specifically to a superjunction device with integrated gate-drain capacitance and a manufacturing method of the superjunction device.
背景技术Background technique
功率半导体器件在清洁、绿色能源领域广泛应用。传统的功率半导体器件例如MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)器件、IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)器件、SGT(Shield GateTrench，屏蔽栅沟槽)器件。超结(Superjunction，简称SJ)器件由于采用电荷平衡耐压层结构，打破了所谓的“硅极限”，相较于传统的功率半导体器件，可显著降低器件的导通电阻，提高系统效率。Power semiconductor devices are widely used in clean and green energy fields. Traditional power semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) device, IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) device, SGT (Shield Gate Trench, Shield Gate Trench) ) device. Superjunction (SJ) devices use a charge-balanced withstand voltage layer structure, which breaks the so-called "silicon limit". Compared with traditional power semiconductor devices, it can significantly reduce the on-resistance of the device and improve system efficiency.
在器件关断过程中，超结器件的电荷平衡耐压结构会导致耗尽层沿着水平和垂直方向扩展，引起器件的电容随电压增加而急剧变小，表现出严重的非线性特性。超结器件的电容非线性特性会引起超结器件开关过程中栅极不可控、电压电流震荡、器件电压击穿和EMI(电磁干扰)等问题。During the device turn-off process, the charge balance withstand voltage structure of the superjunction device will cause the depletion layer to expand along the horizontal and vertical directions, causing the capacitance of the device to decrease sharply as the voltage increases, showing serious nonlinear characteristics. The capacitive nonlinear characteristics of superjunction devices can cause problems such as uncontrollable gates, voltage and current oscillations, device voltage breakdown, and EMI (electromagnetic interference) during the switching process of superjunction devices.
现有技术主要通过系统和器件两个层面改善上述问题。在系统层面：一方面通过调节器件外部连接的栅极电阻，控制器件开关过程中的dv/dt(电压变化率)和di/dt(电流变化率)；另一方面，通过在栅源或者漏源之间并联高压电容，调节器件开关速度。不论是调节栅极电阻还是并联高压电容，都会影响器件的开关速度，增加器件损耗；更重要的是，外部连接的栅极电阻和高压电容不可避免存在寄生电感，会引入新的寄生参数，引起电压电流震荡，造成系统的可靠性问题。在器件层面：一方面是在器件有源区集成栅漏电容，调节器件开关速度；另一方面是在器件的栅极焊盘位置集成内部栅极电阻，控制器件开关过程中的dv/dt和di/dt。但是，上述两种方式都会占用有源区的有效面积，影响器件的输出电流能力。The existing technology mainly improves the above problems at two levels: system and device. At the system level: on the one hand, by adjusting the gate resistance connected externally to the device, the dv/dt (voltage change rate) and di/dt (current change rate) during the switching process of the device are controlled; on the other hand, by adjusting the gate-source or drain A high-voltage capacitor is connected in parallel between the sources to adjust the switching speed of the device. Whether you adjust the gate resistor or connect high-voltage capacitors in parallel, it will affect the switching speed of the device and increase device losses; more importantly, the externally connected gate resistors and high-voltage capacitors inevitably have parasitic inductance, which will introduce new parasitic parameters, causing Voltage and current oscillate, causing system reliability problems. At the device level: on the one hand, the gate-drain capacitance is integrated in the active area of the device to adjust the switching speed of the device; on the other hand, the internal gate resistor is integrated at the gate pad position of the device to control the dv/dt and dv/dt during the switching process of the device. di/dt. However, the above two methods will occupy the effective area of the active area and affect the output current capability of the device.
发明内容Contents of the invention
为了解决上述技术缺陷之一，本申请实施方式提供一种集成栅漏电容的超结器件及制造方法。In order to solve one of the above technical deficiencies, embodiments of the present application provide a superjunction device with integrated gate-drain capacitance and a manufacturing method.
根据本申请实施方式的第一个方面，提供一种集成栅漏电容的超结器件，包括有源区和终端区，所述有源区包括源极、栅极和体区，所述终端区包括截止环区，所述终端区集成有平板电容结构；所述平板电容结构与所述栅极以及所述截止环区相连，所述平板电容结构作为超结器件的栅漏电容。According to a first aspect of the embodiment of the present application, a superjunction device with integrated gate-drain capacitance is provided, including an active region and a terminal region. The active region includes a source electrode, a gate electrode, and a body region. The terminal region It includes a cut-off ring region, the terminal region is integrated with a flat capacitor structure; the flat capacitor structure is connected to the gate and the cut-off ring zone, and the flat capacitor structure serves as the gate-drain capacitance of the superjunction device.
进一步地，所述平板电容结构包括N级串联连接的平板电容，每一级平板电容均包括多晶硅场板、金属场板以及层间介质层，其中N为大于1的正整数。Further, the plate capacitor structure includes N levels of plate capacitors connected in series. Each level of plate capacitor includes a polysilicon field plate, a metal field plate and an interlayer dielectric layer, where N is a positive integer greater than 1.
进一步地，每一级平板电容的金属场板通过接触孔与后一级平板电容的多晶硅场板相连，或者每一级平板电容的多晶硅场板通过接触孔与后一级平板电容的金属场板相连。Further, the metal field plate of each level of flat capacitor is connected to the polysilicon field plate of the subsequent level of flat capacitor through the contact hole, or the polysilicon field plate of each level of flat capacitor is connected to the metal field plate of the subsequent level of flat capacitor through the contact hole. connected.
进一步地，还包括过渡区，所述过渡区内设置有与所述栅极连接的栅极总线。Further, a transition region is included, and a gate bus connected to the gate is provided in the transition region.
进一步地，第一级平板电容的多晶硅场板与所述栅极总线相连，第N级平板电容的金属场板与所述截止环 区相连。Further, the polysilicon field plate of the first-level flat capacitor is connected to the gate bus line, and the metal field plate of the N-th level flat capacitor is connected to the cutoff ring. Districts are connected.
进一步地，所述终端区还集成有电阻结构，所述电阻结构设置于任意两个串联的平板电容之间。Furthermore, the terminal area is also integrated with a resistive structure, and the resistive structure is disposed between any two series-connected plate capacitors.
进一步地，所述电阻结构为多晶硅电阻，所述多晶硅电阻由非掺杂的多晶硅材料或掺杂的多晶硅材料形成。Further, the resistor structure is a polysilicon resistor, and the polysilicon resistor is formed of non-doped polysilicon material or doped polysilicon material.
进一步地，所述多晶硅电阻与所述平板电容的多晶硅场板相连。Further, the polysilicon resistor is connected to the polysilicon field plate of the flat capacitor.
进一步地，所述终端区还包括集成二极管，所述集成二极管位于任意两个串联的平板电容之间。Further, the terminal area further includes an integrated diode, and the integrated diode is located between any two series-connected plate capacitors.
进一步地，所述集成二极管与所述平板电容的多晶硅场板相连。Further, the integrated diode is connected to the polysilicon field plate of the flat capacitor.
进一步地，所述集成二极管包括一个PN结或多个背靠背的PN结。Further, the integrated diode includes one PN junction or multiple back-to-back PN junctions.
根据本申请实施方式的第二个方面，提供一种超结器件的制造方法，所述超结器件为上述第一个方面提供的集成栅漏电容的超结器件，所述方法包括：According to a second aspect of the embodiment of the present application, a method for manufacturing a superjunction device is provided. The superjunction device is the superjunction device with integrated gate-to-drain capacitance provided in the first aspect. The method includes:
在半导体衬底上形成交错排列的P柱和N柱，以形成漂移区；Forming staggered P-pillars and N-pillars on the semiconductor substrate to form a drift region;
同时形成有源区的多晶硅栅极和终端区的多晶硅场板；At the same time, the polysilicon gate electrode in the active area and the polysilicon field plate in the terminal area are formed;
淀积形成层间介质层；Deposition to form an interlayer dielectric layer;
同时形成有源区的源极金属和终端区的金属场板。The source metal of the active area and the metal field plate of the terminal area are formed at the same time.
进一步地，所述方法还包括：在漂移区上形成场氧化层；通过光刻定义有源区、终端区和截止环区的图形；利用湿法刻蚀去除有源区和截止环区的场氧化层。Further, the method further includes: forming a field oxide layer on the drift region; defining the patterns of the active region, the terminal region and the cut-off ring region through photolithography; and using wet etching to remove the fields of the active region and the cut-off ring region. oxide layer.
进一步地，所述同时形成有源区的多晶硅栅极和终端区的多晶硅场板，包括：在有源区热氧化生长栅氧化层；淀积多晶硅；利用干法刻蚀工艺同时形成有源区的多晶硅栅极和终端区的多晶硅场板。Further, the simultaneous formation of the polysilicon gate in the active area and the polysilicon field plate in the terminal area includes: thermally oxidizing and growing a gate oxide layer in the active area; depositing polysilicon; and using a dry etching process to simultaneously form the active area. the polysilicon gate and the polysilicon field plate in the termination areas.
进一步地，所述方法还包括：利用多晶硅栅极作为阻挡层，在预设区域注入硼离子并高温推结，形成有源区的P型体区；在预设区域注入砷离子并推结，形成有源区的N型体区以及终端区的截止环区。Further, the method further includes: using a polysilicon gate as a barrier layer, injecting boron ions into a preset region and pushing the junction at high temperature to form a P-type body region of the active region; injecting arsenic ions into the preset region and pushing the junction, The N-type body region of the active region and the cut-off ring region of the terminal region are formed.
进一步地，所述淀积形成层间介质层，包括：Further, the deposition forms an interlayer dielectric layer, including:
在形成有多晶硅栅极和多晶硅场板的半导体衬底表面淀积介电材料形成层间介质，利用回流工艺进行表面平坦化处理；对层间介质进行刻蚀形成层间介质层和接触孔。A dielectric material is deposited on the surface of the semiconductor substrate where the polysilicon gate electrode and polysilicon field plate are formed to form an interlayer dielectric, and a reflow process is used for surface planarization; the interlayer dielectric is etched to form an interlayer dielectric layer and contact holes.
进一步地，所述方法还包括：在终端区形成一个或多个背靠背的PN结，构成集成二极管。Further, the method further includes: forming one or more back-to-back PN junctions in the terminal area to form an integrated diode.
进一步地，所述方法还包括：在终端区形成多晶硅场板的过程中形成多晶硅电阻；Further, the method further includes: forming a polysilicon resistor in the process of forming the polysilicon field plate in the terminal area;
所述在终端区形成多晶硅场板的过程中形成多晶硅电阻，包括：淀积非掺杂多晶硅，通过光刻定义出多晶硅电阻的图形区域，对多晶硅电阻的图形区域之外的非掺杂多晶硅进行磷离子注入，未进行磷离子注入的非掺杂多晶硅作为多晶硅电阻；或者，淀积掺杂多晶硅，通过光刻定义出掺杂多晶硅图形区域，通过调整掺杂多晶硅图形的宽长比得到所需的掺杂多晶硅电阻。The process of forming a polysilicon field plate in the terminal area to form a polysilicon resistor includes: depositing non-doped polysilicon, defining a pattern area of the polysilicon resistor through photolithography, and performing non-doped polysilicon processing on the non-doped polysilicon outside the pattern area of the polysilicon resistor. Phosphorus ion implantation, undoped polysilicon without phosphorus ion implantation is used as a polysilicon resistor; alternatively, doped polysilicon is deposited, the doped polysilicon pattern area is defined by photolithography, and the required width-to-length ratio is adjusted by adjusting the doped polysilicon pattern of doped polysilicon resistors.
进一步地，所述超结器件为SJ-IGBT器件、SJ-MOSFET器件或SJ-SGT器件。Further, the superjunction device is an SJ-IGBT device, an SJ-MOSFET device or an SJ-SGT device.
本申请实施方式提供的超结器件，在终端区集成与栅极和截止环区相连的平板电容结构，该平板电容结构作为栅漏电容，可以减小超结器件电容的非线性特性，从而增加栅极驱动对超结器件栅极的可控性，减缓超结器件的电压、电流振铃，防止电压击穿损坏器件，改善了器件的EMI品质。更重要的是，在超结器件的终端区集成栅漏电容(反馈电容)，不需要额外占用器件有源区的面积，不会引起器件其它参数的退化，不会影响器件的输出电流能力；而且，在超结器件的终端区集成栅漏电容，可以有效降低器件的等效串联电阻(ESR)和等效串联电感(ESL)，不易引起器件的开关震荡。 The superjunction device provided by the embodiment of the present application integrates a flat capacitor structure connected to the gate and the cutoff ring area in the terminal area. This flat capacitor structure serves as a gate-drain capacitor, which can reduce the nonlinear characteristics of the superjunction device capacitance, thereby increasing The controllability of the gate drive of the superjunction device slows down the voltage and current ringing of the superjunction device, prevents voltage breakdown and damages the device, and improves the EMI quality of the device. More importantly, integrating gate-to-drain capacitance (feedback capacitance) in the terminal area of the superjunction device does not require additional area in the active area of the device, will not cause degradation of other parameters of the device, and will not affect the output current capability of the device; Moreover, integrating gate-to-drain capacitance in the terminal area of a superjunction device can effectively reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the device, and is less likely to cause switching oscillation of the device.
附图说明Description of drawings
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：The drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the attached picture:
图1为本申请实施方式提供的集成栅漏电容的超结器件的平面示意图；Figure 1 is a schematic plan view of a superjunction device with integrated gate-drain capacitance provided by an embodiment of the present application;
图2为本申请实施例一提供的集成栅漏电容的超结器件的截面示意图；Figure 2 is a schematic cross-sectional view of a superjunction device with integrated gate-drain capacitance provided in Embodiment 1 of the present application;
图3为本申请实施例一提供的集成栅漏电容的超结器件的截面示意图；Figure 3 is a schematic cross-sectional view of a superjunction device with integrated gate-drain capacitance provided in Embodiment 1 of the present application;
图4为本申请实施例一提供的集成栅漏电容的超结器件的等效符号图；Figure 4 is an equivalent symbol diagram of a superjunction device with integrated gate-drain capacitance provided in Embodiment 1 of the present application;
图5为本申请实施例二提供的集成栅漏电容和电阻的超结器件的截面示意图；Figure 5 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and resistance provided in Embodiment 2 of the present application;
图6为本申请实施例二提供的集成栅漏电容和电阻的超结器件的截面示意图；Figure 6 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and resistance provided in Embodiment 2 of the present application;
图7为本申请实施例二提供的集成栅漏电容和电阻的超结器件的等效符号图；Figure 7 is an equivalent symbol diagram of a superjunction device integrating gate-to-drain capacitance and resistance provided in Embodiment 2 of the present application;
图8为本申请实施例三提供的集成栅漏电容和二极管的超结器件的截面示意图；Figure 8 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and diode provided in Embodiment 3 of the present application;
图9为本申请实施例三提供的集成栅漏电容和二极管的超结器件的截面示意图；Figure 9 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and diode provided in Embodiment 3 of the present application;
图10至图13为本申请实施例三提供的集成栅漏电容和二极管的超结器件的等效符号图；Figures 10 to 13 are equivalent symbol diagrams of a superjunction device integrating gate-drain capacitance and diode provided in Embodiment 3 of the present application;
图14为现有的超结器件与传统的功率MOSFET器件的电容曲线对比图；Figure 14 is a comparison chart of the capacitance curves of existing superjunction devices and traditional power MOSFET devices;
图15为本申请实施例提供的集成栅漏电容的超结器件与现有的超结器件的反馈电容曲线对比图；Figure 15 is a comparison chart of feedback capacitance curves between a superjunction device with integrated gate-drain capacitance and an existing superjunction device provided by an embodiment of the present application;
图16为本申请实施方式提供的超结器件的制造方法的流程图。FIG. 16 is a flow chart of a manufacturing method of a superjunction device provided by an embodiment of the present application.
附图标记说明
101-N柱，102-P柱，103-场氧化层，104-层间介质层，
105-多晶硅场板，106-金属场板，107-接触孔，108-截止环区，
109-多晶硅电阻，110-集成二极管，111-栅极总线，
112-半导体衬底，113-源极，114-栅极，115-体区，1151-P型体区，1152-N型体区。Explanation of reference signs
101-N pillar, 102-P pillar, 103-field oxide layer, 104-interlayer dielectric layer,
105-polysilicon field plate, 106-metal field plate, 107-contact hole, 108-cut-off ring area,
109-Polysilicon resistor, 110-Integrated diode, 111-Gate bus,
112-semiconductor substrate, 113-source, 114-gate, 115-body region, 1151-P type body region, 1152-N type body region.
具体实施方式Detailed ways
为了使本申请实施例中的技术方案及优点更加清楚明白，以下结合附图对本申请的示例性实施例进行进一步详细的说明，显然，所描述的实施例仅是本申请的一部分实施例，而不是所有实施例的穷举。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。In order to make the technical solutions and advantages in the embodiments of the present application clearer, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application. This is not an exhaustive list of all embodiments. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other.
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。It should be noted that similar reference numerals and letters represent similar items in the following figures, therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures.
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该申请产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的 特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship where the product of this application is commonly placed when used. It is only for the convenience of describing this application and simplifying the description, and is not intended to indicate or imply. The devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as limiting the application. Furthermore, the terms “first”, “second”, “third”, etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, it is limited to "first" and "second" Features may include one or more of these features, explicitly or implicitly. In the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接或可以互相通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。In this application, unless otherwise clearly stated and limited, the terms "installation", "connection", "connection", "fixing" and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated; it can be mechanical connection, electrical connection or mutual communication; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
如背景技术中所介绍的，现有技术主要通过系统和器件两个层面改善超结器件的电容非线性特性的问题。在系统层面：一方面通过调节器件外部连接的栅极电阻，控制器件开关过程中的dv/dt(电压变化率)和di/dt(电流变化率)；另一方面，通过在栅源或者漏源之间并联高压电容，调节器件开关速度。不论是调节栅极电阻还是并联高压电容，都会影响器件的开关速度，增加器件损耗；更重要的是，外部连接的栅极电阻和高压电容不可避免存在寄生电感，会引入新的寄生参数，引起电压电流震荡，造成系统的可靠性问题。在器件层面：一方面是在器件有源区集成栅漏电容，调节器件开关速度；另一方面是在器件的栅极焊盘位置集成内部栅极电阻，控制器件开关过程中的dv/dt和di/dt。但是，上述两种方式都会占用有源区的有效面积，影响器件的输出电流能力。As introduced in the background art, the existing technology mainly improves the problem of capacitance nonlinear characteristics of superjunction devices through two levels: system and device. At the system level: on the one hand, by adjusting the gate resistance connected externally to the device, the dv/dt (voltage change rate) and di/dt (current change rate) during the switching process of the device are controlled; on the other hand, by adjusting the gate-source or drain A high-voltage capacitor is connected in parallel between the sources to adjust the switching speed of the device. Whether you adjust the gate resistor or connect high-voltage capacitors in parallel, it will affect the switching speed of the device and increase device losses; more importantly, the externally connected gate resistors and high-voltage capacitors inevitably have parasitic inductance, which will introduce new parasitic parameters, causing Voltage and current oscillate, causing system reliability problems. At the device level: on the one hand, the gate-drain capacitance is integrated in the active area of the device to adjust the switching speed of the device; on the other hand, the internal gate resistor is integrated at the gate pad position of the device to control the dv/dt and dv/dt during the switching process of the device. di/dt. However, the above two methods will occupy the effective area of the active area and affect the output current capability of the device.
为了改善现有技术中的问题，本发明实施方式提供一种集成栅漏电容的超结器件，包括有源区和终端区，所述有源区包括源极、栅极和体区，所述终端区包括截止环区，所述终端区集成有平板电容结构，平板电容结构与栅极以及截止环区相连，所述平板电容结构作为超结器件的栅漏电容。本申请实施方式在超结器件的终端区集成与栅极和截止环区相连的平板电容结构，该平板电容结构作为栅漏电容，可以减小超结器件电容的非线性特性，从而增加栅极驱动对超结器件栅极的可控性，减缓超结器件的电压、电流振铃，防止电压击穿损坏器件，改善了器件的EMI品质。更重要的是，在超结器件的终端区集成栅漏电容(反馈电容)，不需要额外占用器件有源区的面积，不会引起器件其它参数的退化，不会影响器件的输出电流能力；而且，在超结器件的终端区集成栅漏电容，可以有效降低器件的等效串联电阻(ESR)和等效串联电感(ESL)，不易引起器件的开关震荡。In order to improve the problems in the prior art, embodiments of the present invention provide a superjunction device with integrated gate-drain capacitance, which includes an active region and a terminal region. The active region includes a source, a gate, and a body region. The terminal area includes a cut-off ring area. The terminal area is integrated with a flat capacitor structure. The flat capacitor structure is connected to the gate and the cut-off ring area. The flat capacitor structure serves as the gate-drain capacitance of the superjunction device. The embodiment of the present application integrates a flat capacitor structure connected to the gate and the cutoff ring area in the terminal area of the super junction device. This flat capacitor structure serves as a gate-drain capacitor, which can reduce the nonlinear characteristics of the super junction device capacitance, thereby increasing the gate The driver controls the gate of the superjunction device, slows down the voltage and current ringing of the superjunction device, prevents voltage breakdown from damaging the device, and improves the EMI quality of the device. More importantly, integrating gate-to-drain capacitance (feedback capacitance) in the terminal area of the superjunction device does not require additional area in the active area of the device, will not cause degradation of other parameters of the device, and will not affect the output current capability of the device; Moreover, integrating gate-to-drain capacitance in the terminal area of a superjunction device can effectively reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the device, and is less likely to cause switching oscillation of the device.
实施例一Embodiment 1
图1为本申请实施方式提供的集成栅漏电容的超结器件的平面示意图；图2为本申请实施例一提供的集成栅漏电容的超结器件的截面示意图。图1为平面示意图，图2为沿图1的A-A’方向的横截面图。FIG. 1 is a schematic plan view of a superjunction device with integrated gate-drain capacitance provided by an embodiment of the present application; FIG. 2 is a schematic cross-sectional view of a superjunction device with integrated gate-drain capacitance provided by Embodiment 1 of the present application. Figure 1 is a schematic plan view, and Figure 2 is a cross-sectional view along the A-A' direction of Figure 1.
如图2所示，本实施例提供的超结器件包括有源区、过渡区和终端区，所述有源区、过渡区以及终端区均设置有交替排列的N柱101和P柱102，所述交替排列的N柱101和P柱102构成漂移区。过渡区内和终端区内的相互交替的N柱101和P柱102与有源区内的相互交替的N柱101和P柱102的宽度相同。所述有源区包括源极113、栅极114和体区115，所述终端区包括截止环区108，所述终端区集成有平板电容结构。终端区内的漂移区上方为场氧化层103，场氧化层103的上方为平板电容结构。平板电容结构的两个电极与有源区的栅极114以及终端区的截止环区108相连，截止环区108与超结器件的漏极连接(附图未示出)，所述平板电容结构作为超结器件的栅漏电容。As shown in Figure 2, the superjunction device provided by this embodiment includes an active region, a transition region and a terminal region. The active region, transition region and terminal region are all provided with N pillars 101 and P pillars 102 arranged alternately. The alternately arranged N pillars 101 and P pillars 102 constitute a drift region. The alternating N-pillars 101 and P-pillars 102 in the transition area and the terminal area have the same width as the alternating N-pillars 101 and P-pillars 102 in the active area. The active area includes a source electrode 113, a gate electrode 114 and a body area 115. The terminal area includes a cutoff ring area 108, and the terminal area is integrated with a plate capacitor structure. Above the drift region in the terminal region is a field oxide layer 103, and above the field oxide layer 103 is a plate capacitor structure. The two electrodes of the flat capacitor structure are connected to the gate electrode 114 of the active region and the cutoff ring region 108 of the terminal region. The cutoff ring region 108 is connected to the drain of the superjunction device (not shown in the drawings). The flat capacitor structure As the gate-to-drain capacitance of superjunction devices.
参照图1至图3，过渡区内设置有与有源区的栅极114连接的栅极总线111，通过栅极总线111与器件的栅极焊盘(G)相连，使栅极焊盘的电信号可以同时到达有源区的各个栅极，保证有源区的晶体管能够同时开启。体区115可以限制在有源区，也可以同时横跨有源区和过渡区。平板电容结构由多级串联的平板电容组成。本实施例中，平板电容结构包括六级串联的平板电容，每一级平板电容包括多晶硅场板105、金属场板106以及层间 介质层104。每一级平板电容的金属场板106通过接触孔107与后一级平板电容的多晶硅场板105相连，如图2所示。第一级平板电容的多晶硅场板105与过渡区的栅极总线111相连，第六级平板电容的金属场板106与终端区的截止环区108相连。需要说明的是，图1中接触孔107的位置可以位于整体布局的拐角位置，也可以在水平和/或垂直位置。在其它实施例中还可以，每一级平板电容的多晶硅场板105通过接触孔107与后一级平板电容的金属场板106相连，如图3所示。第一级平板电容的金属场板106与过渡区的栅极总线111相连，最后一级平板电容的多晶硅场板105与终端区的截止环区108相连。Referring to Figures 1 to 3, a gate bus 111 connected to the gate 114 of the active area is provided in the transition area, and is connected to the gate pad (G) of the device through the gate bus 111, so that the gate pad Electrical signals can reach each gate in the active area at the same time, ensuring that the transistors in the active area can be turned on at the same time. The body region 115 can be limited to the active region, or it can span both the active region and the transition region. The plate capacitor structure consists of multiple levels of plate capacitors connected in series. In this embodiment, the flat capacitor structure includes six levels of flat capacitors connected in series. Each level of flat capacitor includes a polysilicon field plate 105, a metal field plate 106 and an interlayer Dielectric layer 104. The metal field plate 106 of each level of flat capacitor is connected to the polysilicon field plate 105 of the subsequent level of flat capacitor through contact holes 107, as shown in FIG. 2 . The polysilicon field plate 105 of the first-level flat capacitor is connected to the gate bus 111 in the transition area, and the metal field plate 106 of the sixth-level flat capacitor is connected to the cut-off ring area 108 of the terminal area. It should be noted that the position of the contact hole 107 in FIG. 1 may be at a corner position of the overall layout, or may be at a horizontal and/or vertical position. In other embodiments, the polysilicon field plate 105 of each level of flat capacitor is connected to the metal field plate 106 of the subsequent level of flat capacitor through contact holes 107, as shown in FIG. 3 . The metal field plate 106 of the first-level flat capacitor is connected to the gate bus 111 in the transition area, and the polysilicon field plate 105 of the last-level flat capacitor is connected to the cut-off ring area 108 of the terminal area.
本实施例中，多个串联的平板电容的金属场板的间距呈递减分布，多个串联的平板电容的多晶硅场板的间距呈递减分布。可选的，每两级多晶硅场板之间的间距为0.1um～8.0um，每两级金属场板之间的间距为0.1um～8.0um。在其它实施例中，每两级平板电容的金属场板的间距可以相等或递增或先递减后递增，每两级平板电容的多晶硅场板的间距可以相等或递增或先递减后递增。金属场板的间距或多晶硅场板的间距的设计准则是依据需要集成的平板电容结构的电容值大小来确定，若需要集成的平板电容结构的电容值越大，则间距越小；若需要集成的平板电容结构的电容值越小，则间距越大。在同样终端区面积条件下，集成的平板电容越多，其间距的最小尺寸受到加工工艺节点限制，间距的典型值可以为0.1um。可选的，所述场氧化层的厚度范围为0.1um～2.0um。所述多晶硅场板的厚度范围为0.1um～1.2um，宽度范围为1.0um～10.0um。所述金属场板的厚度范围为1um～6um，宽度范围为1.0um～10.0um。In this embodiment, the spacing of the metal field plates of the multiple series-connected flat capacitors is in a decreasing distribution, and the spacing of the polysilicon field plates of the multiple series-connected flat capacitors is in a decreasing distribution. Optionally, the spacing between every two levels of polysilicon field plates is 0.1um~8.0um, and the spacing between every two levels of metal field plates is 0.1um~8.0um. In other embodiments, the spacing between the metal field plates of every two levels of flat capacitors can be equal or increasing, or first decreasing and then increasing, and the spacing between the polycrystalline silicon field plates of every two levels of flat capacitors can be equal or increasing, or first decreasing and then increasing. The design criteria for the spacing of metal field plates or the spacing of polysilicon field plates are determined based on the capacitance value of the flat capacitor structure that needs to be integrated. If the capacitance value of the flat capacitor structure that needs to be integrated is larger, the spacing will be smaller; if it needs to be integrated The smaller the capacitance value of the plate capacitor structure, the larger the spacing. Under the same terminal area conditions, the more plate capacitors are integrated, the minimum size of the spacing is limited by the processing technology node, and the typical value of the spacing can be 0.1um. Optionally, the thickness of the field oxide layer ranges from 0.1um to 2.0um. The thickness of the polysilicon field plate ranges from 0.1um to 1.2um, and the width ranges from 1.0um to 10.0um. The thickness of the metal field plate ranges from 1um to 6um, and the width ranges from 1.0um to 10.0um.
参照图4，超结器件的电容CGS0、CGD0和CDS0分别表示超结器件内部的本征栅源电容CGS0、本征栅漏电容CGD0和本征漏源电容CDS0。图2中超结器件终端区的多晶硅场板与金属场板组成平板电容器，该电容器的两个电极分别与栅极和截止环区相连，由于截止环区(沟道截止区)与漏极金属具有相同电位，因此平板电容器等效为图4中的栅漏电容CGD1，栅漏电容CGD1与本征栅漏电容CGD0并联连接。Referring to Figure 4, the capacitances C GS0 , CGD0 and C DS0 of the superjunction device respectively represent the intrinsic gate-source capacitance C GS0 , the intrinsic gate-drain capacitance C GD0 and the intrinsic drain-source capacitance C DS0 inside the super-junction device. In Figure 2, the polycrystalline silicon field plate and the metal field plate in the terminal area of the superjunction device form a flat capacitor. The two electrodes of the capacitor are connected to the gate and the cut-off ring area respectively. Since the cut-off ring area (channel cut-off area) and the drain metal have The same potential, so the flat capacitor is equivalent to the gate-drain capacitance C GD1 in Figure 4. The gate-drain capacitance C GD1 is connected in parallel with the intrinsic gate-drain capacitance C GD0 .
超结器件内部的电荷平衡结构造成器件电容随电压急剧变化，具有高度非线性特征。本实施例提供的超结器件改善电容非线性特性的原理如下：参照图14，超结MOS器件输出电容Coss(包含栅漏电容CGD、漏源电容CDS)和反馈电容Crss(即栅漏电容CGD)随漏源电压VDS增加而变小，漏源电压VDS在20～40V范围内时，输出电容Coss和反馈电容Crss随漏源电压VDS增加而急剧变小，具有高度非线性。超结器件电容非线性导致器件开关过程中出现电压电流震荡，器件电压击穿及EMI问题。改善这些问题的直接方式就是减小超结器件电容的非线性特性。图15示出了本申请实施例提供的集成栅漏电容的超结器件与现有的超结器件的反馈电容曲线对比图，集成栅漏电容的超结器件的反馈电容Crss等效于栅漏电容CGD1+本征栅漏电容CGD0，而现有的超结器件的反馈电容Crss为本征栅漏电容CGD0。参照图15可以看出，集成栅漏电容的超结器件的反馈电容随漏源电压VDS增加而急剧变小的程度，明显小于现有的超结器件的反馈电容的变化程度。由此可见，超结器件在终端区引入的平板电容CGD1可以减缓电容随电压的急剧变化程度，降低超结器件反馈电容Crss的非线性特征。在器件关断过程中，当栅源电压VGS减小到平台电压时，漏源电压VDS开始增加，电压增加速率由下式决定：IG＝CGD*(dVDS)/dt。对于同样的栅极电流IG，漏源电压VDS增加速率由栅漏电容CGD(反馈电容)决定。栅漏电容CGD越大，漏源电压VDS增加速率(dVDS)越小，栅极可控性越强，电压电流震荡越小，对系统其它部分的电磁干扰也越小。The charge balance structure inside the superjunction device causes the device capacitance to change sharply with voltage, which is highly nonlinear. The principle of the superjunction device provided in this embodiment to improve the nonlinear characteristics of capacitance is as follows: Referring to Figure 14, the superjunction MOS device output capacitance C oss (including gate-drain capacitance C GD and drain-source capacitance C DS ) and feedback capacitance C rss (i.e. The gate-drain capacitance C GD ) becomes smaller as the drain-source voltage V DS increases. When the drain-source voltage V DS is in the range of 20 to 40V, the output capacitance C oss and feedback capacitance C rss decrease sharply as the drain-source voltage V DS increases. , highly nonlinear. The nonlinear capacitance of superjunction devices causes voltage and current oscillations, device voltage breakdown and EMI problems during the switching process of the device. The direct way to improve these problems is to reduce the nonlinear characteristics of the superjunction device capacitance. Figure 15 shows a comparison diagram of the feedback capacitance curves of the superjunction device with integrated gate-leakage capacitance and the existing superjunction device provided by the embodiment of the present application. The feedback capacitance C rss of the superjunction device with integrated gate-leakage capacitance is equivalent to the gate Drain capacitance C GD1 + intrinsic gate-to-drain capacitance C GD0 , and the feedback capacitance C rss of existing superjunction devices is the intrinsic gate-to-drain capacitance C GD0 . Referring to Figure 15, it can be seen that the feedback capacitance of the superjunction device with integrated gate-drain capacitance decreases sharply as the drain-source voltage V DS increases, which is significantly smaller than the change in feedback capacitance of the existing superjunction device. It can be seen that the plate capacitance C GD1 introduced in the terminal area of the superjunction device can slow down the sharp change of capacitance with voltage and reduce the nonlinear characteristics of the feedback capacitance C rss of the superjunction device. During the device turn-off process, when the gate-source voltage V GS decreases to the plateau voltage, the drain-source voltage V DS begins to increase, and the voltage increase rate is determined by the following formula: I G =C GD *(dV DS )/dt. For the same gate current I G , the increase rate of the drain-source voltage V DS is determined by the gate-to-drain capacitance CGD (feedback capacitance). The larger the gate-to-drain capacitance C GD , the smaller the increase rate of drain-source voltage V DS (dV DS ), the stronger the gate controllability, the smaller the voltage and current oscillation, and the smaller the electromagnetic interference to other parts of the system.
根据实际应用的不同，可以通过调节多晶硅场板与金属场板的交叠区的面积来调节栅漏电容CGD1的大小，和/或调节多晶硅场板与金属场板之间的层间介质层的厚度来调节栅漏电容CGD1电容大小，栅漏电容CGD1的典型值范围为0.1pF～10pF。举例而言，可以通过如下方式确定栅漏电容CGD1。假设平板电容结构的金属场板的间距 相等，多晶硅场板的间距也相等，栅漏电容CGD1等效为6个串联连接的平板电容。设多晶硅场板与金属场板的交叠区的面积为S，层间介质层的厚度为d，则单级多晶硅场板与单级金属场板构成的单级平板电容可以表示为：Co＝εS/d；其中，ε为介电常数。Depending on the actual application, the size of the gate-to-drain capacitance C GD1 can be adjusted by adjusting the area of the overlapping area of the polysilicon field plate and the metal field plate, and/or adjusting the interlayer dielectric layer between the polysilicon field plate and the metal field plate. The thickness of the gate-drain capacitor C GD1 can be used to adjust the capacitance size. The typical value range of the gate-drain capacitor C GD1 is 0.1pF ~ 10pF. For example, the gate-to-drain capacitance CGD1 can be determined as follows. Assuming the spacing of the metal field plates of the flat capacitor structure are equal, the spacing of the polysilicon field plates is also equal, and the gate-to-drain capacitance C GD1 is equivalent to six series-connected plate capacitors. Assuming that the area of the overlapping area of the polysilicon field plate and the metal field plate is S, and the thickness of the interlayer dielectric layer is d, then the single-stage flat capacitor composed of a single-stage polysilicon field plate and a single-stage metal field plate can be expressed as: C o =εS/d; where, ε is the dielectric constant.
对于6个串联的平板电容，栅漏电容CGD1表示为：CGD1＝εS/(6d)；For six series-connected plate capacitors, the gate-to-drain capacitance C GD1 is expressed as: C GD1 = εS/(6d);
对于N个串联的平板电容，栅漏电容CGD1表示为：CGD1＝εS/(Nd)；For N plate capacitors connected in series, the gate-to-drain capacitance C GD1 is expressed as: C GD1 = εS/(Nd);
通过上述公式可以计算得到多晶硅场板与金属场板的交叠区的面积或层间介质层的厚度。通常，多晶硅场板与金属场板的交叠区的面积S取值范围为0.5um～100um，层间介质层的厚度d取值范围0.1um～2um。The area of the overlapping area of the polysilicon field plate and the metal field plate or the thickness of the interlayer dielectric layer can be calculated through the above formula. Usually, the area S of the overlapping area of the polysilicon field plate and the metal field plate ranges from 0.5um to 100um, and the thickness d of the interlayer dielectric layer ranges from 0.1um to 2um.
实施例二Embodiment 2
图5为本申请实施例二提供的集成栅漏电容和电阻的超结器件的截面示意图。实施例二的超结器件的平面示意图可参见图1，也可以理解为图5是沿图1的A-A’方向的横截面图。FIG. 5 is a schematic cross-sectional view of a superjunction device integrating gate-to-drain capacitance and resistance provided in Embodiment 2 of the present application. A schematic plan view of the superjunction device of Embodiment 2 can be seen in FIG. 1 , and it can also be understood that FIG. 5 is a cross-sectional view along the A-A’ direction of FIG. 1 .
如图5所示，本实施例提供的超结器件包括有源区、过渡区和终端区，所述有源区、过渡区以及终端区均设置有交替排列的N柱101和P柱102，所述交替排列的N柱101和P柱102构成漂移区。过渡区内和终端区内的相互交替的N柱101和P柱102与有源区内的相互交替的N柱101和P柱102的宽度相同。所述有源区包括源极113、栅极114和体区115，所述终端区包括截止环区108，所述终端区集成有平板电容结构。终端区内的漂移区上方为场氧化层103，场氧化层103的上方为平板电容结构。平板电容结构的两个电极与有源区的栅极114以及终端区的截止环区108相连，截止环区108与超结器件的漏极连接(附图未示出)，所述平板电容结构作为超结器件的栅漏电容。过渡区内设置有与有源区的栅极114连接的栅极总线111，通过栅极总线111与器件的栅极焊盘(G)相连，使栅极焊盘的电信号可以同时到达有源区的各个栅极，保证有源区的晶体管能够同时开启。体区115可以限制在有源区，也可以同时横跨有源区和过渡区。As shown in Figure 5, the superjunction device provided by this embodiment includes an active region, a transition region and a terminal region. The active region, transition region and terminal region are all provided with N pillars 101 and P pillars 102 arranged alternately. The alternately arranged N pillars 101 and P pillars 102 constitute a drift region. The alternating N-pillars 101 and P-pillars 102 in the transition area and the terminal area have the same width as the alternating N-pillars 101 and P-pillars 102 in the active area. The active area includes a source electrode 113, a gate electrode 114 and a body area 115. The terminal area includes a cutoff ring area 108, and the terminal area is integrated with a plate capacitor structure. Above the drift region in the terminal region is a field oxide layer 103, and above the field oxide layer 103 is a plate capacitor structure. The two electrodes of the flat capacitor structure are connected to the gate electrode 114 of the active region and the cutoff ring region 108 of the terminal region. The cutoff ring region 108 is connected to the drain of the superjunction device (not shown in the drawings). The flat capacitor structure As the gate-to-drain capacitance of superjunction devices. A gate bus 111 connected to the gate 114 of the active area is provided in the transition area. The gate bus 111 is connected to the gate pad (G) of the device, so that the electrical signals from the gate pad can reach the active area at the same time. Each gate of the active area ensures that the transistors in the active area can be turned on at the same time. The body region 115 can be limited to the active region, or it can span both the active region and the transition region.
平板电容结构包括六级串联的平板电容，每一级平板电容包括多晶硅场板105、金属场板106以及层间介质层104。每一级平板电容的金属场板106通过接触孔107与后一级平板电容的多晶硅场板105相连。第一级平板电容的多晶硅场板105与过渡区的栅极总线111相连，第六级平板电容的金属场板106与终端区的截止环区108相连。在其它实施例中还可以，每一级平板电容的多晶硅场板通过接触孔与后一级平板电容的金属场板相连。第一级平板电容的金属场板与过渡区的栅极总线相连，最后一级平板电容的多晶硅场板与终端区的截止环区相连。The plate capacitor structure includes six levels of plate capacitors connected in series. Each level of plate capacitor includes a polysilicon field plate 105 , a metal field plate 106 and an interlayer dielectric layer 104 . The metal field plate 106 of each level of flat capacitor is connected to the polysilicon field plate 105 of the subsequent level of flat capacitor through contact holes 107 . The polysilicon field plate 105 of the first-level flat capacitor is connected to the gate bus 111 in the transition area, and the metal field plate 106 of the sixth-level flat capacitor is connected to the cut-off ring area 108 of the terminal area. In other embodiments, the polysilicon field plate of each level of flat capacitor is connected to the metal field plate of the subsequent level of flat capacitor through contact holes. The metal field plate of the first-level flat capacitor is connected to the gate bus in the transition area, and the polysilicon field plate of the last-level flat capacitor is connected to the cut-off ring area in the terminal area.
超结器件的终端区还集成有电阻结构，该电阻结构可以设置于任意两个串联的平板电容之间。如图6所示，电阻结构位于第一级平板电容与栅极总线111之间，第一级平板电容通过电阻结构连接到栅极总线111。电阻结构为多晶硅电阻109，多晶硅电阻109由非掺杂的多晶硅材料或掺杂的多晶硅材料形成。多晶硅电阻109与平板电容的多晶硅场板105相连。多晶硅电阻109的掺杂离子浓度与多晶硅场板105的掺杂离子浓度不同或相同，在超结器件的制造过程中，可以在对应区域淀积多晶硅材料再进行离子掺杂，同时形成多晶硅电阻109和多晶硅场板105；也可以对掺杂多晶硅设置不同的宽长比实现需要的电阻。The terminal area of the superjunction device is also integrated with a resistive structure, which can be placed between any two series-connected plate capacitors. As shown in FIG. 6 , the resistive structure is located between the first-level plate capacitor and the gate bus 111 , and the first-level plate capacitor is connected to the gate bus 111 through the resistive structure. The resistor structure is a polysilicon resistor 109, and the polysilicon resistor 109 is formed of undoped polysilicon material or doped polysilicon material. The polysilicon resistor 109 is connected to the polysilicon field plate 105 of the flat capacitor. The doping ion concentration of the polysilicon resistor 109 is different or the same as the doping ion concentration of the polysilicon field plate 105. During the manufacturing process of the superjunction device, polysilicon material can be deposited in the corresponding area and then ion doped to form the polysilicon resistor 109. and the polysilicon field plate 105; different width-to-length ratios can also be set for the doped polysilicon to achieve the required resistance.
参照图7，超结器件的电容CGS0、CGD0和CDS0分别表示超结器件内部的本征栅源电容CGS0、本征栅漏电容CGD0和本征漏源电容CDS0。平板电容结构的多晶硅场板与金属场板组成平板电容器，多晶硅场板与金属场板作为电容器的两个电极，一个电极与截止环区相连，一个电极通过电阻结构与栅极相连，平板电容结构与电阻结构串联连接构成RC吸收电路。由于截止环区(沟道截至区)与漏极具有相同电位，因此平板电容器等效为图5中 的栅漏电容CGD1，电阻结构等效为图5中的电阻R。栅漏电容CGD1和电阻R构成的RC吸收电路与本征栅漏电容CGD0并联连接，可以降低器件的等效串联电阻(ESR)和等效串联电感(ESL)，消除寄生等效串联电阻和等效串联电感的影响，避免引起器件的开关震荡。Referring to Figure 7, the capacitances C GS0 , CGD0 and C DS0 of the superjunction device respectively represent the intrinsic gate-source capacitance C GS0 , the intrinsic gate-drain capacitance C GD0 and the intrinsic drain-source capacitance C DS0 inside the super-junction device. The polysilicon field plate and the metal field plate of the flat capacitor structure form a flat capacitor. The polysilicon field plate and the metal field plate serve as the two electrodes of the capacitor. One electrode is connected to the cutoff ring area, and the other electrode is connected to the gate through the resistor structure. The flat capacitor structure Connected in series with the resistor structure to form an RC absorption circuit. Since the cut-off ring area (channel cut-off area) and the drain have the same potential, the equivalent of the flat capacitor is as shown in Figure 5 The gate-to-drain capacitance C GD1 , the resistor structure is equivalent to the resistor R in Figure 5. The RC absorption circuit composed of gate-drain capacitance C GD1 and resistor R is connected in parallel with the intrinsic gate-drain capacitance C GD0 , which can reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the device and eliminate parasitic equivalent series resistance. and equivalent series inductance to avoid causing switching oscillation of the device.
实施例二提供的超结器件，终端区集成串联连接的平板电容结构和电阻结构，一方面可以减小超结器件电容的非线性特性，增加对器件栅极的可控性，减缓器件的电压、电流振铃，防止电压击穿损坏器件，改善器件的EMI品质；另一方面集成电阻可以有效降低器件的等效串联电阻(ESR)和等效串联电感(ESL)，避免易引起器件的开关震荡。In the superjunction device provided in the second embodiment, the terminal area integrates a series-connected flat capacitor structure and a resistor structure. On the one hand, it can reduce the nonlinear characteristics of the superjunction device capacitance, increase the controllability of the device gate, and slow down the voltage of the device. , current ringing to prevent voltage breakdown and damage to the device, and improve the EMI quality of the device; on the other hand, integrated resistors can effectively reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the device, avoiding easy switching of the device. Shock.
实施例三Embodiment 3
图8为本申请实施例三提供的集成栅漏电容和二极管的超结器件的截面示意图。实施例三的超结器件的平面示意图可参见图1，也可以理解为图8是沿图1的A-A’方向的横截面图。FIG. 8 is a schematic cross-sectional view of a superjunction device integrating gate-drain capacitance and diode provided in Embodiment 3 of the present application. A schematic plan view of the superjunction device in Embodiment 3 can be seen in FIG. 1 , and it can also be understood that FIG. 8 is a cross-sectional view along the A-A’ direction in FIG. 1 .
如图8所示，本实施例提供的超结器件包括有源区、过渡区和终端区，所述有源区、过渡区以及终端区均设置有交替排列的N柱101和P柱102，所述交替排列的N柱101和P柱102构成漂移区。过渡区内和终端区内的相互交替的N柱101和P柱102与有源区内的相互交替的N柱101和P柱102的宽度相同。所述有源区包括源极113、栅极114和体区115，所述终端区包括截止环区108，所述终端区集成有平板电容结构。终端区内的漂移区上方为场氧化层103，场氧化层103的上方为平板电容结构。平板电容结构的两个电极与有源区的栅极114以及终端区的截止环区108相连，截止环区108与超结器件的漏极连接(附图未示出)，所述平板电容结构作为超结器件的栅漏电容。过渡区内设置有与有源区的栅极114连接的栅极总线111，通过栅极总线111与器件的栅极焊盘(G)相连，使栅极焊盘的电信号可以同时到达有源区的各个栅极，保证有源区的晶体管能够同时开启。体区115可以限制在有源区，也可以同时横跨有源区和过渡区。As shown in Figure 8, the superjunction device provided by this embodiment includes an active region, a transition region, and a terminal region. The active region, transition region, and terminal region are all provided with alternately arranged N pillars 101 and P pillars 102. The alternately arranged N pillars 101 and P pillars 102 constitute a drift region. The alternating N-pillars 101 and P-pillars 102 in the transition area and the terminal area have the same width as the alternating N-pillars 101 and P-pillars 102 in the active area. The active area includes a source electrode 113, a gate electrode 114 and a body area 115. The terminal area includes a cutoff ring area 108, and the terminal area is integrated with a plate capacitor structure. Above the drift region in the terminal region is a field oxide layer 103, and above the field oxide layer 103 is a plate capacitor structure. The two electrodes of the flat capacitor structure are connected to the gate electrode 114 of the active region and the cutoff ring region 108 of the terminal region. The cutoff ring region 108 is connected to the drain of the superjunction device (not shown in the drawings). The flat capacitor structure As the gate-to-drain capacitance of superjunction devices. A gate bus 111 connected to the gate 114 of the active area is provided in the transition area. The gate bus 111 is connected to the gate pad (G) of the device, so that the electrical signals from the gate pad can reach the active area at the same time. Each gate of the active area ensures that the transistors in the active area can be turned on at the same time. The body region 115 can be limited to the active region, or it can span both the active region and the transition region.
平板电容结构包括六级串联的平板电容，每一级平板电容包括多晶硅场板105、金属场板106以及层间介质层104。每一级平板电容的金属场板106通过接触孔107与后一级平板电容的多晶硅场板105相连。第一级平板电容的多晶硅场板105与过渡区的栅极总线111相连，第六级平板电容的金属场板106与终端区的截止环区108相连。在其它实施例中还可以，每一级平板电容的多晶硅场板通过接触孔与后一级平板电容的金属场板相连。第一级平板电容的金属场板与过渡区的栅极总线相连，最后一级平板电容的多晶硅场板与终端区的截止环区相连。多个串联的平板电容的金属场板的间距呈递减分布，多个串联的平板电容的多晶硅场板的间距呈递减分布。可选的，每两级多晶硅场板之间的间距为0.1um～8.0um，每两级金属场板之间的间距为0.1um～8.0um。在其它实施例中，每两级平板电容的金属场板的间距可以相等或递增或先减小后递增，每两级平板电容的多晶硅场板的间距可以相等或递增或先减小后递增。金属场板的间距或多晶硅场板的间距可以依据需要集成的平板电容结构的电容值大小来确定，若需要集成的平板电容结构的电容值越大，则间距越小；若需要集成的平板电容结构的电容值越小，则间距越大。The plate capacitor structure includes six levels of plate capacitors connected in series. Each level of plate capacitor includes a polysilicon field plate 105 , a metal field plate 106 and an interlayer dielectric layer 104 . The metal field plate 106 of each level of flat capacitor is connected to the polysilicon field plate 105 of the subsequent level of flat capacitor through contact holes 107 . The polysilicon field plate 105 of the first-level flat capacitor is connected to the gate bus 111 in the transition area, and the metal field plate 106 of the sixth-level flat capacitor is connected to the cut-off ring area 108 of the terminal area. In other embodiments, the polysilicon field plate of each level of flat capacitor is connected to the metal field plate of the subsequent level of flat capacitor through contact holes. The metal field plate of the first-level flat capacitor is connected to the gate bus in the transition area, and the polysilicon field plate of the last-level flat capacitor is connected to the cut-off ring area in the terminal area. The spacing of the metal field plates of multiple series-connected flat capacitors is in a decreasing distribution, and the spacing of the polysilicon field plates of multiple series-connected flat capacitors is in a decreasing distribution. Optionally, the spacing between every two levels of polysilicon field plates is 0.1um~8.0um, and the spacing between every two levels of metal field plates is 0.1um~8.0um. In other embodiments, the spacing between the metal field plates of every two levels of flat capacitors may be equal or increasing, or first decrease and then increase. The spacing between the polycrystalline silicon field plates of every two levels of flat capacitors may be equal or increasing, or first decrease and then increase. The spacing between metal field plates or polysilicon field plates can be determined based on the capacitance value of the flat capacitor structure that needs to be integrated. If the capacitance value of the flat capacitor structure that needs to be integrated is larger, the spacing will be smaller; if the flat capacitor structure that needs to be integrated is larger, the spacing will be smaller; The smaller the capacitance value of the structure, the larger the spacing.
超结器件的终端区还包括集成二极管110，集成二极管110位于任意两个串联的平板电容之间。如图9所示，集成二极管110与平板电容的多晶硅场板105相连。集成二极管110包括一个PN结或者多个背靠背的PN结，所述PN结可采用非掺杂的多晶硅材料或掺杂的多晶硅材料形成。The terminal area of the superjunction device also includes an integrated diode 110, which is located between any two series-connected plate capacitors. As shown in Figure 9, the integrated diode 110 is connected to the polysilicon field plate 105 of the planar capacitor. The integrated diode 110 includes one PN junction or multiple back-to-back PN junctions, and the PN junction may be formed of undoped polysilicon material or doped polysilicon material.
参照图10至图13，超结器件的电容CGS0、CGD0和CDS0分别表示超结器件内部的本征栅源电容CGS0、本征栅漏电容CGD0和本征漏源电容CDS0。平板电容结构的多晶硅场板与金属场板组成平板电容器，多晶硅场板与金 属场板作为电容器的两个电极，一个电极与截止环区相连，一个电极通过集成二极管与栅极相连。由于截止环区与漏极具有相同电位，因此平板电容器等效为栅漏电容CGD1，栅漏电容CGD1和集成二极管110构成的整流电路，与器件的本征栅漏电容CGD0并联连接。整流电路为器件开通和关断充放电路径提供不同的栅漏电容值。对于开通和关断过程中的dv/dt(电压变化率)和di/dt(电流变化率)的优化，分为非对称开关速度优化和对称开关速度优化。Referring to Figures 10 to 13, the capacitances C GS0 , C GD0 and C DS0 of the superjunction device respectively represent the intrinsic gate-source capacitance C GS0 , the intrinsic gate-drain capacitance C GD0 and the intrinsic drain-source capacitance C DS0 inside the super-junction device. . The polycrystalline silicon field plate and the metal field plate of the flat capacitor structure form a flat capacitor. The polycrystalline silicon field plate and the metal field plate The field plate serves as two electrodes of the capacitor, one electrode is connected to the cutoff ring area, and the other electrode is connected to the gate through an integrated diode. Since the cutoff ring region and the drain have the same potential, the plate capacitor is equivalent to the gate-drain capacitance CGD1 . The rectifier circuit composed of the gate-drain capacitor CGD1 and the integrated diode 110 is connected in parallel with the intrinsic gate-drain capacitance CGD0 of the device. The rectifier circuit provides different gate-drain capacitance values for the device to turn on and off the charge and discharge paths. The optimization of dv/dt (voltage change rate) and di/dt (current change rate) during the turn-on and turn-off processes is divided into asymmetric switching speed optimization and symmetric switching speed optimization.
图10为非对称开关速度(开通速度小于关断速度)等效符号图。参见图10，集成二极管110的正极与栅极相连，集成二极管110的负极与作为栅漏电容CGD1的平板电容相连，这种情况下器件的开通速度小于关断速度。Figure 10 is an equivalent symbol diagram of asymmetric switching speed (turn-on speed is less than turn-off speed). Referring to Figure 10, the anode of the integrated diode 110 is connected to the gate, and the cathode of the integrated diode 110 is connected to the plate capacitor as the gate drain capacitance C GD1 . In this case, the turn-on speed of the device is slower than the turn-off speed.
图11为非对称开关速度(开通速度大于关断速度)等效符号图。参见图11，集成二极管110的正极与作为栅漏电容CGD1的平板电容相连，集成二极管110的负极与栅极相连，这种情况下器件的开通速度大于关断速度。Figure 11 is an equivalent symbol diagram of asymmetric switching speed (turn-on speed is greater than turn-off speed). Referring to Figure 11, the anode of the integrated diode 110 is connected to the plate capacitor as the gate-drain capacitance C GD1 , and the cathode of the integrated diode 110 is connected to the gate. In this case, the turn-on speed of the device is greater than the turn-off speed.
图12为对称开关速度等效符号图(共阳极接法)。参见图12，集成二极管110包括两个背对背的二极管，两个二极管的正极共同连接，其中一个二极管的负极与作为栅漏电容CGD1的平板电容相连，另一个二极管的负极与栅极相连，以实现对称开关速度优化。Figure 12 is the equivalent symbol diagram of symmetrical switching speed (common anode connection method). Referring to Figure 12, the integrated diode 110 includes two back-to-back diodes, the anodes of the two diodes are connected together, the cathode of one diode is connected to the plate capacitor as the gate-drain capacitance C GD1 , and the cathode of the other diode is connected to the gate to Achieve symmetrical switching speed optimization.
图13为对称开关速度等效符号图(共阴极接法)。参见图13，集成二极管110包括两个背对背的二极管，两个二极管的负极共同连接，其中一个二极管的正极与作为栅漏电容CGD1的平板电容相连，另一个二极管的正极与栅极相连，以实现对称开关速度优化。Figure 13 is the equivalent symbol diagram of symmetrical switching speed (common cathode connection method). Referring to Figure 13, the integrated diode 110 includes two back-to-back diodes, the cathodes of the two diodes are connected together, the anode of one diode is connected to the plate capacitor as the gate-drain capacitance C GD1 , and the anode of the other diode is connected to the gate to Achieve symmetrical switching speed optimization.
实施例三提供的超结器件，终端区集成平板电容结构和集成二极管，构成整流电路，一方面可以减小超结器件电容的非线性特性，增加对器件栅极的可控性，减缓器件的电压、电流振铃，防止电压击穿损坏器件，改善器件的EMI品质；另一方面可以分别优化开通和关断速度，实现速度与功耗的平衡。In the superjunction device provided in the third embodiment, the terminal area integrates a flat capacitor structure and an integrated diode to form a rectifier circuit. On the one hand, it can reduce the nonlinear characteristics of the capacitance of the superjunction device, increase the controllability of the device gate, and slow down the failure of the device. Voltage and current ringing prevent voltage breakdown from damaging the device and improve the EMI quality of the device; on the other hand, the turn-on and turn-off speeds can be optimized respectively to achieve a balance between speed and power consumption.
上述实施例一至实施例三提供的集成栅漏电容的超结器件，可应用于IGBT、MOSFET或SGT器件，构成SJ-IGBT器件、SJ-MOSFET器件或SJ-SGT器件。The superjunction devices with integrated gate-drain capacitance provided in the above-mentioned Embodiments 1 to 3 can be applied to IGBT, MOSFET or SGT devices to form SJ-IGBT devices, SJ-MOSFET devices or SJ-SGT devices.
图16为本申请实施方式提供的超结器件的制造方法的流程图。如图16所示，本实施方式提供的超结器件的制造方法，该方法包括以下步骤：FIG. 16 is a flow chart of a manufacturing method of a superjunction device provided by an embodiment of the present application. As shown in Figure 16, this embodiment provides a method for manufacturing a superjunction device, which method includes the following steps:
S1、在半导体衬底上形成交错排列的P柱和N柱，以形成漂移区。S1. Form staggered P-pillars and N-pillars on the semiconductor substrate to form a drift region.
具体的，在半导体衬底上生长N型硅外延层或P型硅外延层，对N型硅外延层或P型硅外延层进行刻蚀形成深沟槽，在N型硅外延层的深沟槽内填充P型硅，或者在P型硅外延层的深沟槽内填充N型硅，从而形成交错排列的P柱和N柱。Specifically, an N-type silicon epitaxial layer or a P-type silicon epitaxial layer is grown on a semiconductor substrate, and the N-type silicon epitaxial layer or P-type silicon epitaxial layer is etched to form a deep trench. The trench is filled with P-type silicon, or the deep trench of the P-type silicon epitaxial layer is filled with N-type silicon, thereby forming staggered P-pillars and N-pillars.
S2、同时形成有源区的多晶硅栅极和终端区的多晶硅场板。S2. Form the polysilicon gate in the active area and the polysilicon field plate in the terminal area at the same time.
在步骤S2之前，在漂移区上形成场氧化层，预先定义有源区、过渡区及终端区的区域。其中，可以通过光刻定义出有源区、终端区和截止环区的图形，利用湿法刻蚀去除有源区和截止环区的场氧化层。Before step S2, a field oxide layer is formed on the drift region, and the active region, transition region and terminal region are predefined. Among them, the patterns of the active area, terminal area and cut-off ring area can be defined through photolithography, and the field oxide layer in the active area and cut-off ring area can be removed by wet etching.
接着，在有源区热氧化生长栅氧化层，淀积多晶硅，利用干法刻蚀工艺同时形成有源区的多晶硅栅极、过渡区的栅极总线以及终端区的多晶硅场板。Next, a gate oxide layer is thermally oxidized and grown in the active area, polysilicon is deposited, and a dry etching process is used to simultaneously form the polysilicon gate in the active area, the gate bus line in the transition area, and the polysilicon field plate in the terminal area.
接着，利用多晶硅栅极作为阻挡层，在预设区域注入硼离子并高温推结，形成有源区的P型体区1151，在预设区域注入砷离子并推结，形成有源区的N型体区1152以及终端区的截止环区。 Next, using the polysilicon gate as a barrier layer, boron ions are injected into the preset area and pushed through at high temperature to form the P-type body region 1151 of the active area. Arsenic ions are injected into the preset area and pushed through to form the N-type body region of the active area. The body area 1152 and the cut-off ring area of the terminal area.
S3、淀积形成层间介质层。S3. Deposit to form an interlayer dielectric layer.
在形成有多晶硅栅极和多晶硅场板的半导体衬底表面淀积介电材料(二氧化硅或氮化硅)形成层间介质ILD(Inter Layer Dielectric)，利用回流工艺进行表面平坦化处理，对层间介质进行刻蚀形成接触孔，并进行硼离子注入。Deposit dielectric material (silicon dioxide or silicon nitride) on the surface of the semiconductor substrate where the polysilicon gate electrode and polysilicon field plate are formed to form an interlayer dielectric ILD (Inter Layer Dielectric), and use the reflow process to perform surface planarization. The interlayer dielectric is etched to form contact holes, and boron ions are implanted.
S4、同时形成有源区的源极金属和终端区的金属场板。S4. Form the source metal of the active area and the metal field plate of the terminal area at the same time.
在步骤S3之后的半导体衬底上淀积金属材料形成导电金属层，对导电金属层进行刻蚀，同时形成有源区的源极金属和终端区的金属场板。After step S3, a metal material is deposited on the semiconductor substrate to form a conductive metal layer, and the conductive metal layer is etched to simultaneously form the source metal of the active region and the metal field plate of the terminal region.
在一可选实施例中，对应上述实施例一的超结器件的制造方法，包括以下工艺流程：In an optional embodiment, the method for manufacturing a superjunction device corresponding to the above-mentioned Embodiment 1 includes the following process flow:
(1)在半导体衬底上形成交错排列的P柱和N柱，构成超结器件的漂移区；(1) Form staggered P-pillars and N-pillars on the semiconductor substrate to form the drift region of the superjunction device;
(2)热生长场氧化层，光刻定义出有源区和截止环区；并利用湿法刻蚀去掉有源区和截止环区的场氧化层；(2) Thermal growth field oxide layer, photolithography defines the active area and cut-off ring area; and wet etching is used to remove the field oxide layer in the active area and cut-off ring area;
(3)热氧化生长栅氧化层；(3) Thermal oxidation growth gate oxide layer;
(4)淀积多晶硅，通过光刻和刻蚀工艺形成有源区的多晶硅栅极和终端区的多晶硅场板；(4) Deposit polysilicon, and form the polysilicon gate in the active area and the polysilicon field plate in the terminal area through photolithography and etching processes;
(5)利用多晶硅栅极作为阻挡层注入硼离子，并高温推结形成有源区的P型体区；(5) Use the polysilicon gate as a barrier layer to inject boron ions, and push the junction at high temperature to form the P-type body region of the active region;
(6)注入砷离子并推结，形成有源区的N型体区和截止环区；(6) Inject arsenic ions and push the junction to form the N-type body region and cutoff ring region of the active region;
(7)淀积层间介质ILD，刻蚀形成接触孔；(7) Deposit the interlayer dielectric ILD and etch to form contact holes;
(8)淀积金属铝，形成源极金属和终端区金属场板。(8) Deposit metal aluminum to form source metal and terminal area metal field plates.
在另一可选实施例中，对应上述实施例二的超结器件的制造方法，还包括：在终端区形成多晶硅场板的过程中形成多晶硅电阻。具体的，在上述步骤S2中，淀积非掺杂多晶硅，通过光刻定义出多晶硅电阻的图形区域，对多晶硅电阻的图形区域之外的非掺杂多晶硅进行磷离子注入，进行磷离子注入的多晶硅构成多晶硅场板，未进行磷离子注入的非掺杂多晶硅作为多晶硅电阻；或者，淀积掺杂多晶硅，通过光刻定义出掺杂多晶硅图形区域，通过调整掺杂多晶硅图形的宽长比得到所需的掺杂多晶硅电阻。In another optional embodiment, corresponding to the method for manufacturing a superjunction device in Embodiment 2 above, the method further includes: forming a polysilicon resistor in the process of forming a polysilicon field plate in the terminal region. Specifically, in the above step S2, non-doped polysilicon is deposited, a pattern area of the polysilicon resistor is defined through photolithography, and phosphorus ions are implanted into the non-doped polysilicon outside the pattern area of the polysilicon resistor. Polycrystalline silicon constitutes a polycrystalline silicon field plate, and undoped polycrystalline silicon that has not been implanted with phosphorus ions is used as a polycrystalline silicon resistor; alternatively, doped polycrystalline silicon is deposited, the doped polycrystalline silicon pattern area is defined by photolithography, and the width-to-length ratio of the doped polycrystalline silicon pattern is adjusted to obtain required doped polysilicon resistor.
在一可选实施例中，对应上述实施例三的超结器件的制造方法，还包括：在终端区形成多个背靠背的PN结，以构成集成二极管。具体的，该方法包括以下工艺流程：In an optional embodiment, corresponding to the manufacturing method of the superjunction device in the third embodiment above, the method further includes: forming a plurality of back-to-back PN junctions in the terminal region to form an integrated diode. Specifically, the method includes the following process flow:
(1)在半导体衬底上形成交错排列的P柱和N柱，构成超结器件的漂移区；(1) Form staggered P-pillars and N-pillars on the semiconductor substrate to form the drift region of the superjunction device;
(2)在漂移区上热生长形成场氧化层，光刻定义出有源区和截止环区；并利用湿法刻蚀去掉有源区和截止环区的场氧化层；(2) Thermal growth forms a field oxide layer on the drift area, and photolithography defines the active area and cutoff ring area; and wet etching is used to remove the field oxide layer in the active area and cutoff ring area;
(3)在有源区热氧化生长栅氧化层；(3) Thermal oxidation grows the gate oxide layer in the active area;
(4)淀积非掺杂多晶硅，硼离子注入非掺杂多晶硅；(4) Deposit non-doped polysilicon, and implant boron ions into the non-doped polysilicon;
(5)光刻定义出二极管PN结的区域，然后磷离子注入并高温退火，形成一个或多个背靠背的PN结；(5) Photolithography defines the area of the diode PN junction, and then phosphorus ions are implanted and annealed at high temperature to form one or more back-to-back PN junctions;
(6)利用干法刻蚀工艺形成有源区的多晶硅栅极和终端区的多晶硅场板；(6) Use a dry etching process to form the polysilicon gate in the active area and the polysilicon field plate in the terminal area;
(7)光刻定义P型体区并注入硼离子，高温推结形成有源区的P型体区；(7) Define the P-type body region by photolithography and inject boron ions, and push the junction at high temperature to form the P-type body region of the active region;
(8)注入砷离子并推结，形成有源区的N型体区和终端区的截止环区；(8) Inject arsenic ions and push the junction to form the N-type body region of the active region and the cut-off ring region of the terminal region;
(9)淀积层间介质ILD，刻蚀出接触孔，并进行硼离子注入；(9) Depositing interlayer dielectric ILD, etching contact holes, and performing boron ion implantation;
(10)淀积金属铝，干法刻蚀铝，形成源极金属和终端区金属场板。 (10) Deposit metallic aluminum and dry-etch the aluminum to form source metal and terminal area metal field plates.
上述步骤中涉及的工艺流程与传统超结器件的工艺流程兼容，工艺简单，实用性强。The process flow involved in the above steps is compatible with the process flow of traditional superjunction devices, and the process is simple and highly practical.
上述的超结器件的制造方法，可形成SJ-IGBT器件、SJ-MOSFET器件或SJ-SGT器件。The above-mentioned manufacturing method of superjunction devices can form SJ-IGBT devices, SJ-MOSFET devices or SJ-SGT devices.
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。Although the preferred embodiments of the present application have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of this application.
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。 Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application is also intended to include these modifications and variations.

Claims (15)

  1. 一种集成栅漏电容的超结器件，包括有源区和终端区，所述有源区包括源极、栅极和体区，所述终端区包括截止环区，其特征在于，所述终端区集成有平板电容结构；A superjunction device with integrated gate-drain capacitance, including an active region and a terminal region, the active region including a source, a gate and a body region, the terminal region including a cut-off ring region, characterized in that, the terminal region The area is integrated with a plate capacitor structure;
    所述平板电容结构包括N级串联连接的平板电容，每一级平板电容均包括多晶硅场板、金属场板以及层间介质层，第一级平板电容的多晶硅场板与栅极相连，第N级平板电容的金属场板与所述截止环区相连，所述平板电容结构作为超结器件的栅漏电容；其中，N为大于1的正整数，每一级平板电容的金属场板通过接触孔与后一级平板电容的多晶硅场板相连，或者每一级平板电容的多晶硅场板通过接触孔与后一级平板电容的金属场板相连。The plate capacitor structure includes N levels of plate capacitors connected in series. Each level of plate capacitor includes a polysilicon field plate, a metal field plate and an interlayer dielectric layer. The polysilicon field plate of the first level plate capacitor is connected to the gate, and the Nth level plate capacitor is connected to the gate. The metal field plate of each level of flat capacitor is connected to the cut-off ring area, and the flat capacitor structure serves as the gate-drain capacitance of the superjunction device; where N is a positive integer greater than 1, and the metal field plate of each level of flat capacitor passes through the contact The holes are connected to the polysilicon field plate of the subsequent level of flat capacitor, or the polysilicon field plate of each level of flat capacitor is connected to the metal field plate of the subsequent level of flat capacitor through the contact hole.
  2. 根据权利要求1所述的集成栅漏电容的超结器件，其特征在于，还包括：过渡区，所述过渡区内设置有与所述栅极连接的栅极总线，第一级平板电容的多晶硅场板通过栅极总线与栅极相连。The superjunction device with integrated gate-drain capacitance according to claim 1, further comprising: a transition region, a gate bus connected to the gate is provided in the transition region, and a first-level plate capacitor is provided in the transition region. The polysilicon field plate is connected to the gate via a gate bus.
  3. 根据权利要求1所述的集成栅漏电容的超结器件，其特征在于，所述终端区还集成有电阻结构，所述电阻结构设置于任意两个串联的平板电容之间。The superjunction device with integrated gate-to-leak capacitance according to claim 1, wherein the terminal region is further integrated with a resistance structure, and the resistance structure is disposed between any two series-connected plate capacitors.
  4. 根据权利要求3所述的集成栅漏电容的超结器件，其特征在于，所述电阻结构为多晶硅电阻，所述多晶硅电阻由非掺杂的多晶硅材料或掺杂的多晶硅材料形成。The superjunction device with integrated gate-drain capacitance according to claim 3, wherein the resistor structure is a polysilicon resistor, and the polysilicon resistor is formed of non-doped polysilicon material or doped polysilicon material.
  5. 根据权利要求4所述的集成栅漏电容的超结器件，其特征在于，所述多晶硅电阻与所述平板电容的多晶硅场板相连。The superjunction device with integrated gate-drain capacitor according to claim 4, wherein the polysilicon resistor is connected to the polysilicon field plate of the flat capacitor.
  6. 根据权利要求1所述的集成栅漏电容的超结器件，其特征在于，所述终端区还包括集成二极管，所述集成二极管位于任意两个串联的平板电容之间。The superjunction device with integrated gate-to-drain capacitance according to claim 1, wherein the terminal region further includes an integrated diode, and the integrated diode is located between any two series-connected plate capacitors.
  7. 根据权利要求6所述的集成栅漏电容的超结器件，其特征在于，所述集成二极管与所述平板电容的多晶硅场板相连。The superjunction device with integrated gate-to-drain capacitor according to claim 6, wherein the integrated diode is connected to the polysilicon field plate of the flat capacitor.
  8. 根据权利要求6所述的集成栅漏电容的超结器件，其特征在于，所述集成二极管包括一个PN结或多个背靠背的PN结。The superjunction device with integrated gate-to-drain capacitance according to claim 6, wherein the integrated diode includes one PN junction or multiple back-to-back PN junctions.
  9. 一种超结器件的制造方法，所述超结器件为权利要求1-8中任一项所述的集成栅漏电容的超结器件，其特征在于，所述方法包括：A method of manufacturing a superjunction device, the superjunction device being a superjunction device with integrated gate-drain capacitance according to any one of claims 1 to 8, characterized in that the method includes:
    在半导体衬底上形成交错排列的P柱和N柱，以形成漂移区；Forming staggered P-pillars and N-pillars on the semiconductor substrate to form a drift region;
    同时形成有源区的多晶硅栅极和终端区的多晶硅场板； At the same time, the polysilicon gate electrode in the active area and the polysilicon field plate in the terminal area are formed;
    淀积形成层间介质层；Deposition to form an interlayer dielectric layer;
    同时形成有源区的源极金属和终端区的金属场板。The source metal of the active area and the metal field plate of the terminal area are formed at the same time.
  10. 根据权利要求9所述的超结器件的制造方法，其特征在于，所述方法还包括：The method for manufacturing a superjunction device according to claim 9, wherein the method further includes:
    在漂移区上形成场氧化层；Forming a field oxide layer on the drift region;
    通过光刻定义有源区、终端区和截止环区的图形；Define the pattern of active area, terminal area and cut-off ring area through photolithography;
    利用湿法刻蚀去除有源区和截止环区的场氧化层。Use wet etching to remove the field oxide layer in the active area and cutoff ring area.
  11. 根据权利要求10所述的超结器件的制造方法，其特征在于，所述同时形成有源区的多晶硅栅极和终端区的多晶硅场板，包括：The manufacturing method of a superjunction device according to claim 10, wherein the simultaneous formation of the polysilicon gate electrode of the active region and the polysilicon field plate of the terminal region includes:
    在有源区热氧化生长栅氧化层；The gate oxide layer is grown by thermal oxidation in the active area;
    淀积多晶硅；Deposit polysilicon;
    利用干法刻蚀工艺同时形成有源区的多晶硅栅极和终端区的多晶硅场板。A dry etching process is used to simultaneously form the polysilicon gate in the active area and the polysilicon field plate in the terminal area.
  12. 根据权利要求11所述的超结器件的制造方法，其特征在于，所述方法还包括：The method for manufacturing a superjunction device according to claim 11, wherein the method further includes:
    利用多晶硅栅极作为阻挡层，在预设区域注入硼离子并高温推结，形成有源区的P型体区；Using the polysilicon gate as a barrier layer, boron ions are injected into the preset area and pushed at high temperature to form a P-type body region in the active area;
    在预设区域注入砷离子并推结，形成有源区的N型体区以及终端区的截止环区。Arsenic ions are implanted in the preset area and the junction is pushed to form the N-type body area of the active area and the cut-off ring area of the terminal area.
  13. 根据权利要求11所述的超结器件的制造方法，其特征在于，所述方法还包括：The method for manufacturing a superjunction device according to claim 11, wherein the method further includes:
    在终端区形成一个或多个背靠背的PN结，构成集成二极管。One or more back-to-back PN junctions are formed in the terminal area to form an integrated diode.
  14. 根据权利要求9所述的超结器件的制造方法，其特征在于，所述方法还包括：The method for manufacturing a superjunction device according to claim 9, wherein the method further includes:
    在终端区形成多晶硅场板的过程中形成多晶硅电阻；The polysilicon resistor is formed during the formation of the polysilicon field plate in the terminal area;
    所述在终端区形成多晶硅场板的过程中形成多晶硅电阻，包括：The process of forming a polysilicon field plate in the terminal area to form a polysilicon resistor includes:
    淀积非掺杂多晶硅，通过光刻定义出多晶硅电阻的图形区域，对多晶硅电阻的图形区域之外的非掺杂多晶硅进行磷离子注入，未进行磷离子注入的非掺杂多晶硅作为多晶硅电阻；或者Deposit non-doped polysilicon, define the pattern area of the polysilicon resistor through photolithography, perform phosphorus ion implantation on the non-doped polysilicon outside the pattern area of the polysilicon resistor, and use the non-doped polysilicon without phosphorus ion implantation as the polysilicon resistor; or
    淀积掺杂多晶硅，通过光刻定义出掺杂多晶硅图形区域，通过调整掺杂多晶硅图形的宽长比得到所需的掺杂多晶硅电阻。Deposit doped polysilicon, define the doped polysilicon pattern area through photolithography, and obtain the required doped polysilicon resistance by adjusting the width-to-length ratio of the doped polysilicon pattern.
  15. 根据权利要求9所述的超结器件的制造方法，其特征在于，所述超结器件为SJ-IGBT器件、SJ-MOSFET器件或SJ-SGT器件。 The method for manufacturing a superjunction device according to claim 9, wherein the superjunction device is an SJ-IGBT device, an SJ-MOSFET device or an SJ-SGT device.
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CN113808951A (en) * 2021-11-18 2021-12-17 南京华瑞微集成电路有限公司 Anti-electromagnetic interference super-junction MOS device and manufacturing method thereof
CN115224024A (en) * 2022-09-15 2022-10-21 北京芯可鉴科技有限公司 Super junction device of integrated gate-drain capacitor and manufacturing method

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