CN113471291A - Super junction device and manufacturing method thereof - Google Patents
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- CN113471291A CN113471291A CN202110686877.0A CN202110686877A CN113471291A CN 113471291 A CN113471291 A CN 113471291A CN 202110686877 A CN202110686877 A CN 202110686877A CN 113471291 A CN113471291 A CN 113471291A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 210000000746 body region Anatomy 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 230000000903 blocking effect Effects 0.000 claims abstract description 9
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 238000002347 injection Methods 0.000 claims abstract description 5
- 239000007924 injection Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 68
- 239000000758 substrate Substances 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 230000005684 electric field Effects 0.000 description 19
- 230000015556 catabolic process Effects 0.000 description 11
- 238000009826 distribution Methods 0.000 description 10
- 239000008186 active pharmaceutical agent Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract
The invention provides a super junction device and a manufacturing method thereof, and relates to a power semiconductor device.A floating polycrystalline field plate and a floating metal field plate in the device are not provided with additional doping regions such as a second conductive type protection ring below; and no additional doped region such as a guard ring of the second conductivity type is arranged below the metal gate electrode and the polysilicon gate electrode except the body region of the second conductivity type. Because the main junction is not adopted, the terminal region can still be ensured to bear higher blocking voltage under the condition of not introducing an additional doping region, and because the main junction is not adopted in the design, the p-type body region can adopt the polysilicon gate electrode as an injection blocking layer, so that a photoetching plate of the p-type body region can be omitted, the manufacturing cost is saved, in addition, the chip area can be reduced without the main junction, and the cost is further saved.
Description
Technical Field
The invention relates to a power semiconductor device, in particular to a super junction device and a manufacturing method thereof.
Background
A vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET) is a key semiconductor device in power electronic systems, and is widely applied to various medium-high voltage power control systems, such as motor driving and power conversion. In a conventional silicon power transistor, in order to withstand a high breakdown voltage, the drift layer needs to be doped lightly and thick, which results in a high on-resistance and a high on-loss of the device. Breakdown Voltage (BV) and on-resistance (R) for conventional silicon power transistorsDS(on)) Between which there is an RDS(on)∝BV2.5This relationship is also referred to as the "silicon limit". Therefore, if either of the two is improved, the other is inevitably significantly weakened. In addition, in the design of the device, the actual R may be due to other performance considerations, such as reliabilityDS(on)Usually higher than the theoretical value given by the silicon limit.
A super junction (Superjunction) is a structure that can achieve a better trade-off between breakdown voltage and on-resistance, and is characterized in that a drift layer is no longer a single-doped semiconductor region, but p columns and n columns with higher doping levels are alternately arranged. When the device is in a blocking state, adjacent p columns and n columns in the drift layer can be quickly depleted through lateral expansion of the depletion layer, so that high breakdown voltage is borne. And the higher doping level of the drift layer ensures that the device has lower on-resistance. Therefore, the device with the super junction structure can obtain lower on-resistance with the same breakdown voltage, and the compromise relation can reach RDS(on)∝BV1.33。
A complete super junction metal oxide semiconductor field effect transistor (super junction MOS) includes an active region and a termination region. Active regionAnd the function of providing a current path when the device is switched on is carried out, the termination region is positioned between the boundary of the active region and the scribing groove and surrounds the active region, and the function of the termination region is to reduce the high electric field of the edge region of the device so as to ensure that the device can bear high withstand voltage. Fig. 1 is a schematic cross-sectional view of a prior art superjunction MOS 001. Device 001 has three electrodes: a source electrode (labeled "S" in the figure) at the top (121), a drain electrode (labeled "D" in the figure) at the bottom (122), and a gate electrode (labeled "G" in the figure) (123). N above the drain electrode (122)+A substrate region (107) at n+Above the substrate region (107) are n arranged alternately-A type-doped region (101) and p-A drift layer composed of a type doping region (102), a p type body region (103) is arranged above the drift layer, and n is arranged above the p type body region (103)+A source region (104) and p+A contact region (105) of type, and said n+A source region (104) and p+The type contact region (105) is connected with a source electrode (121), and the source electrode (121) is isolated from a gate electrode (123) through an interlayer dielectric layer. The region where the P-type body region (103) is located is called an active region, and it should be noted that the active region in an actual device may extend continuously to the left side in the figure, and only a part of the active region is shown in fig. 1. The region between the cut-off of the p-type body region (103) and the edge of the device (right side in the figure) is called the termination region. In the terminal region, n-A type-doped region (101) and p-A layer of n distributed uniformly is arranged above the type-doped region (102)-A type-doped region (106) at n-One or more p-type floating empty regions (110) are arranged above the type doping region (106), the p-type floating empty regions (110) extend in a terminal region of the surface of the device to form a closed ring to surround the active region, and the p-type floating empty regions (110) are connected with the metal field plate (124). At the outermost peripheral edge of the device surface there is also typically an n-type termination doped region (104) and a termination field plate (125) above it.
When the device 001 is in the blocking state, the withstand voltage is determined by the withstand voltages of the active region and the termination region together. In the active region, n-A type-doped region (101) and p-The number of impurity ions in the type-doped region (102) is substantially the same, so that charge balance can be achieved more easily after depletion, thereby achieving better balanceHigh withstand voltage. However, in the termination region, not only the withstand voltage in the vertical direction but also the withstand voltage in the horizontal direction, that is, the device edge region, is considered, and if the same drift layer design as that of the active region is adopted, n is likely to occur-The type-doped region (101) has been completely depleted and p-The undepleted part in the type doping region (102) causes the peak value of the transverse electric field to be too high and the withstand voltage to be reduced. Therefore, special design is required in the termination region, generally by adding an additional n-The charge imbalance condition is compensated by the n-type doped region or the p-type doped region which is different from the active region, so that the more uniform surface electric field distribution is realized, and the withstand voltage of the terminal region is ensured.
According to the structure of the device 001 shown in fig. 1, several important process steps are required to fabricate the device 001: 1) forming alternately arranged p columns and n columns on the semiconductor substrate by utilizing multi-step epitaxy or deep groove etching and filling; 2) injecting phosphorus to form an n-type doped region of the terminal region; 3) forming a protection ring by boron implantation; 4) growing a field oxide layer by thermal oxidation, and defining an active region by photoetching; 5) injecting and growing a gate oxide layer by the JFET; 6) depositing n-type polycrystalline silicon to manufacture a polycrystalline silicon gate electrode of the device; 7) injecting boron for the second time and pushing the junction to form a P-type body region; 8) arsenic is injected to form a source electrode and a stop ring of the device; 9) boron implantation to form p+A type contact region; 10) depositing an interlayer dielectric (ILD) and etching a contact hole; 11) and sputtering metal Al to form a metal electrode and a metal field plate of the device.
It can be seen that the super junction MOS in the prior art has many manufacturing steps and high process requirements, which results in high product cost, and cannot fully embody the performance advantages of the super junction technology in competition with the common MOS.
Disclosure of Invention
In order to achieve the above objective, the present invention provides a novel super junction MOS structure and a method for manufacturing the same.
One of the purposes of the invention is to provide a super junction device, which comprises a drain electrode positioned at the bottom, a heavily doped first conduction type substrate region positioned above the drain electrode, a drift layer, an active region and a terminal region, wherein the drift layer is positioned above the heavily doped first conduction type substrate region and consists of a series of first conduction type doped regions and second conduction type doped regions which are alternately arranged; the device comprises a device body, a floating polycrystalline field plate and a floating polycrystalline field plate, wherein the end region comprises a field oxide layer positioned above a drift layer, more than one floating polycrystalline field plate positioned on the upper surface of the field oxide layer, and a floating metal field plate positioned above the floating polycrystalline field plate and at least covering the interval of two adjacent floating polycrystalline field plates, the floating polycrystalline field plate and the floating metal field plate are isolated by an interlayer dielectric layer, the floating polycrystalline field plate extends from the center of a second conductive type doping region to cover the upper position of the adjacent or separated first conductive type doping region, and the floating polycrystalline field plate are not connected with the first conductive type doping region and the second conductive type doping region below. As one of the invention points of the scheme, no extra doped region such as a guard ring of a second conductivity type is arranged below the floating polycrystalline field plate and the floating metal field plate; and no additional doped region such as a guard ring of the second conductivity type is arranged below the metal gate electrode and the polysilicon gate electrode except the body region of the second conductivity type.
The super-junction device comprises an active region, a drift layer, a heavily doped first conductive type source region, a heavily doped second conductive type contact region, a gate electrode and an uppermost source electrode, wherein the active region comprises the second conductive type body region, the heavily doped first conductive type source region and the heavily doped second conductive type contact region are positioned above the drift layer, the gate electrode and the uppermost source electrode are positioned in the heavily doped first conductive type source region and the heavily doped second conductive type contact region, the source electrode is connected with the heavily doped first conductive type source region and the heavily doped second conductive type contact region, and the gate electrode and the source electrode are isolated through an interlayer dielectric layer; a gate oxide layer is arranged between the gate electrode and the second conductive type body region, between the lightly doped first conductive type doping region and between the heavily doped first conductive type source regions. The second conduction type doped regions are mutually independent in the device range (comprising an MOS active region and a terminal region), and the second conduction type body regions in the active region are also mutually independent; wherein potentials of the second conductivity type doped region and the second conductivity type body region are connected through the source electrode.
Further, the length of the terminal area ranges from 50um to 300 um.
Furthermore, the thickness of the field oxide layer under the floating polycrystalline field plate is 0.6 um-2.0 um.
Furthermore, a polysilicon gate electrode is arranged at the joint of the active region and the terminal region, the length of the polysilicon gate electrode extending to the terminal region covers at least one group of the first conductive type doped region and the second conductive type doped region, and a gate oxide layer is arranged below the polysilicon gate electrode.
Furthermore, the coverage length of the polysilicon gate electrode extending to the terminal area is more than 40um, and the thickness of the gate oxide layer is 0.08 um-0.12 um.
Further, the second conductive type doping regions at the corners of the device have a rounded chamfered form arrangement.
Further, the radius of curvature of the chamfer is greater than 50 um.
Furthermore, floating polycrystalline field plates and/or floating metal field plates in the X-axis direction are in floating island structures which are not connected with each other.
The second objective of the present invention is also to provide a method for manufacturing the superjunction device, wherein the method comprises the following steps:
1) forming a drift layer consisting of first conductive type doping regions and second conductive type doping regions which are alternately arranged on a semiconductor substrate;
2) growing a field oxide layer by thermal oxidation, and defining an active region by photoetching;
3) injecting and growing a gate oxide layer by the JFET;
4) depositing first conductive type polycrystalline silicon to manufacture a gate electrode and a floating polycrystalline field plate;
5) injecting boron by taking the polycrystalline silicon as a mask and pushing the junction to form a second conductive type body region;
6) doping and injecting the first conductive type to form a heavily doped first conductive type source region and a first conductive type termination ring of the device;
7) performing boron injection to form a heavily doped second conductive type contact region;
8) depositing an interlayer medium and etching a contact hole;
9) and sputtering metal Al to form a source electrode and a floating metal field plate.
Furthermore, the second conductive type body region adopts a polysilicon gate electrode as an injection blocking layer, and the polysilicon gate electrode and the floating polysilicon field plate are formed simultaneously.
In one embodiment provided by the invention, the invention provides a novel super junction MOS structure which comprises a drain electrode positioned at the bottom, and n arranged on the drain electrode+A substrate region of n+Over the substrate region is a series of n alternately arranged-Type-doped column and p-A drift layer composed of type doped columns, a p-type body region is arranged above the drift layer, and n is arranged above the p-type body region+Type source region and p+A type contact region, and said n+Type source region and p+The type contact region is connected with the source electrode, and the source electrode is isolated from the gate electrode through the interlayer dielectric layer. The region where the p-type body region is located is called an active region, and the region between the cut-off of the p-type body region and the edge of the super junction MOS structure is called a termination region. In the terminal region, n-Type-doped column and p-The type-doped column extends all the way to the semiconductor surface, above which is a field oxide layer. The upper surface of the field oxide layer is provided with a plurality of floating polycrystalline field plates, floating metal field plates are arranged above the floating polycrystalline field plates, and the floating polycrystalline field plates are isolated from the floating metal field plates through interlayer dielectric layers. The super junction MOS device is characterized in that a p-type body region (a main junction region) is not arranged below a gate pad of the super junction MOS device; any p column or n column in the device range (including the MOS active region and the termination region) is independent; and the terminal region only has p columns and n columns which are alternately arranged in the semiconductor, and no additional doped regions such as p-type guard rings and the like exist. The relative position of the polycrystalline field plate and the p column meets the requirement that the polycrystalline field plate extends from the center position of the p column to the terminal direction, and the floating metal field plate is positioned in the horizontal directionIn the middle of the floating polycrystalline field plate, the floating metal field plate and the polycrystalline field plate can be mutually overlapped, or one side of the floating metal field plate and the polycrystalline field plate can be overlapped or both sides of the floating metal field plate and the polycrystalline field plate are not overlapped; the floating metal field plate and the polycrystalline field plate are not connected with the p columns and the n columns which are alternately arranged.
In the above embodiment, since no main junction is required and no additional doped region needs to be introduced into the termination region, a simpler process can be adopted, and the specific steps are as follows:
1) forming alternately arranged p columns and n columns on the semiconductor substrate by utilizing multi-step epitaxy or deep groove etching and filling;
2) growing a field oxide layer by thermal oxidation, and defining an active region by photoetching;
3) injecting and growing a gate oxide layer by the JFET;
4) depositing n-type polycrystalline silicon to manufacture a polycrystalline silicon gate electrode and a polycrystalline field plate of the device;
5) injecting boron by taking the polycrystalline silicon as a mask and pushing the junction to form a P-type body region;
6) arsenic is injected to form a source electrode and a stop ring of the device;
7) boron implantation to form p+A type contact region;
8) depositing an interlayer medium and etching a contact hole;
9) and sputtering metal Al to form a metal electrode and a metal field plate of the device.
As described above, the invention can ensure that the terminal region can bear higher blocking voltage under the condition of not adopting a main junction and not introducing an additional doped region. And because the main junction is not adopted in the design, the p-type body region can adopt the polysilicon gate electrode as an injection blocking layer, so that a photoetching plate of the p-type body region can be saved, and the manufacturing cost is saved. In addition, the chip area can be reduced without a main junction, and the cost is further saved.
In addition, a second conductive type protection ring doping region is not required to be arranged below the floating polycrystalline field plate and the floating metal field plate; besides the P-type body region, a guard ring doping region of the second conduction type is not needed under the metal gate electrode and the polysilicon gate electrode.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a conventional super junction MOS device 001.
Fig. 2 is a schematic top view of a super junction MOS device 002 according to the first embodiment of the present invention.
Fig. 3 shows a super junction MOS device 002 along a according to the first embodiment of the present invention-The cross section structure in the direction A' is schematic.
Fig. 4 shows a super junction MOS device 002 along a according to the first embodiment of the present invention-A' and B-Electric field distribution in the B' direction.
Fig. 5 shows a superjunction MOS device 003 along a according to the second embodiment of the present invention-The cross section structure in the direction A' is schematic.
Fig. 6 is a schematic top-view structure diagram of a super junction MOS device 004 according to the third embodiment of the present invention.
Fig. 7 is a schematic top-view structure diagram of a super junction MOS device 004 according to a fourth embodiment of the present invention.
Detailed Description
Embodiments of the device of the present invention will be specifically exemplified below. It is noted that in the following description of the superjunction MOS device embodiments of the present invention, the semiconductor substrate of the superjunction MOS device is considered to be composed of a silicon (Si) material. However, the substrate may be formed of any other material suitable for fabricating MOS devices, such as germanium (Ge), silicon carbide (SiC), and the like. In the following description, the dielectric material of the superjunction MOS device may be made of silicon oxide (SiO)x) And (4) forming. However, other dielectric materials may be used, such as silicon nitride (Si)xNy) Aluminum oxide (Al)xOy) And silicon oxynitride (Si)xNyOz) And the like. In the following description, the conductivity types of a semiconductor region are classified into p-type and n-type. A p-type conductivity semiconductor region may be formed by doping the original semiconductor region with one or more impurities which may be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), and the like. An n-type conductive semiconductor region may also be formed by doping the original semiconductor region with one or more impurities which may be, but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H)+) And the like.
Example 1
Device 002 is a super junction MOS device according to the first embodiment of the present invention. Similar to the super junction MOS device 001 in the prior art, the drift layer of the super junction MOS device of the present invention has a series of p columns and n columns arranged at intervals, and the widths of the p columns and the n columns may be equal or different. Fig. 3 is a schematic cross-sectional view of device 002 corresponding to AA' in fig. 2. Viewed in cross-section, device 002 has: a drain electrode (222), n, at the bottom+A substrate region (207) is located over the drain electrode (222) at n+Over the substrate region (207) is a series of alternating n-A type-doped region (201) and p-A drift layer consisting of a type doped region (202), a p-type body region (203) is arranged above the drift layer, and n is arranged above the p-type body region (203)+A source region (204) and p+A contact region (205) of type, and said n+A source region (204) and p+The type contact region (205) is connected with a source electrode (221), and the source electrode (221) is isolated from the polysilicon gate electrode (223) through an interlayer dielectric layer. Polysilicon gate electrode (223) and P-type body region (203), n-A type doped region (201) and a portion of n+A gate oxide layer (211) is arranged between the type source regions (204), and the region where the P-type body region (203) is located is called as an active region; the region between the cut-off of the p-type body region (203) and the edge of the device (right side in the figure) is called the termination region. In the terminal region, n-A type-doped region (201) and p-The type-doped region (202) extends all the way to the semiconductor surface, above which is a field oxide layer (212). The upper surface of the field oxide layer (212) is provided with a plurality of floating polycrystalline field plates (226), floating metal field plates (224) are arranged above the space between adjacent floating polycrystalline field plates (226), and the floating polycrystalline field plates (226) and the floating metal field plates (224) are isolated through interlayer dielectric layers. At the outermost peripheral edge of the device surface, there is also an n-type termination ring (206) and a termination field plate (225) above it. As mentioned above, to ensure that the device can withstand a sufficient breakdown voltage, the parameters of the dual-layer floating field plate can be designed as follows: a single floating poly field plate (226) typically more than a few microns wide, positioned from the center of a p-pillar to a location above an adjacent n-pillar, may also cover a group or oneThe upper adjacent p pillars and n pillars are grouped. The floating metal field plate (224) is positioned between the two floating polycrystalline field plates (226) in the horizontal direction, the floating metal field plate (224) and the floating polycrystalline field plate (226) can be mutually overlapped, or one side of the floating metal field plate and the floating polycrystalline field plate can be overlapped or both sides of the floating metal field plate and the floating polycrystalline field plate are not overlapped, and the width of the floating metal field plate and the floating polycrystalline field plate is generally more than a few micrometers. The thickness of a field oxide layer (212) below the floating polycrystalline field plate (226) is 600 nm-2000 nm, and the thickness of an interlayer dielectric (ILD) is 80 nm-2000 nm.
As mentioned above, the device 002 has no main junction occupying a large chip area, and the termination region has no additional doped region, so that the p-type body region 203 can use the polysilicon gate electrode as an implantation barrier, thereby omitting the photolithography of the p-type body region 203, and further reducing the chip area due to the absence of the main junction.
The corresponding fabrication process steps are designed as follows, depending on the structural design of the device 002. 1) Filling the semiconductor substrate by multi-step epitaxy or deep trench etching to form n arranged alternately-A type-doped region (201) and p-A type-doped region (202); 2) growing a field oxide layer (212) by thermal oxidation, and defining an active region by photoetching; 3) injecting and growing a gate oxide layer (211) by the JFET; 4) depositing n-type polycrystalline silicon to manufacture a polycrystalline silicon gate electrode (223) and a floating polycrystalline field plate (226) of the device; 5) injecting boron by taking the polysilicon as a mask and pushing the boron to form a P-type body region (203); 6) arsenic implant to form n of the device+A source region (204) and an n-type termination ring (206);
7) boron implantation to form p+A contact region (205); 8) depositing an interlayer medium and etching a contact hole;
9) and sputtering metal Al to form a source electrode (221), a metal gate electrode (227) and a floating metal field plate (224) of the device.
When the super junction MOS is in a blocking state, adjacent p columns (p) in the drift layer of the active region-Type doped region) and n-pillar (n)-Type doped region) in the horizontal direction, and because the numbers of impurity ions in the p column and the n column are substantially equal, when the p column and the n column are completely depleted, the distribution of a longitudinal electric field in the drift layer is nearly rectangular, and the integral of the longitudinal electric field is the withstand voltage borne by the active region, because the integral of the longitudinal electric field is the withstand voltage borne by the active regionIn theory, the required breakdown voltage can be realized by only selecting the appropriate thickness of the drift layer without using the low-doped drift layer, so that the on-resistance of the super-junction MOS device is effectively reduced. However, the area of the active region is limited, and at the edge cut-off of the active region, an electric field is concentrated due to the influence of the curvature effect of the PN junction, so that the electric field is increased, and the withstand voltage of the device is lowered. In the super junction MOS device, the withstand voltage of the termination region in the vertical direction is similar to that of the active region, and the withstand voltage is maintained by means of mutual depletion between the p column and the n column to achieve charge balance, but the withstand voltage in the horizontal direction needs to be specially designed. Based on this, the present invention uniquely designs the termination region of the superjunction device in conjunction with the actual fabrication of the device.
The principle of withstand voltage of the terminal structure of the present invention is explained as follows: fig. 2 is a top view of the device of the present invention, wherein there are two cross-sections in different directions, i.e. along AA 'and along BB' of the device, and the device structure on the two cross-sections is different. The direction along the AA' position is perpendicular to the p-pillar and n-pillar distribution, so that the alternating arrangement of p-pillars and n-pillars is visible in this cross-section, as shown in fig. 3; the direction along the BB' position is parallel to the p-pillar and n-pillar distribution, so only a single p-pillar or n-pillar is visible on the cross-section. The distribution of the surface electric field is also different due to the difference in device structure across the cross section. Curve 1 in FIG. 4 is the surface electric field distribution along AA', and since the cross section shows the alternating p-pillars and n-pillars, the interface of these p-pillars and n-pillars is the pn junction, the electric field distribution is a wave shape with a plurality of triangles connected. Curve 2 in fig. 4 is the surface electric field distribution along the BB' position, and since a single p-column or n-column is seen on the cross section, the electric field distribution is a uniform straight line, and the electric field value is lower than the peak of the wave-like electric field. Thus, to ensure that the termination region can withstand sufficient breakdown voltage in the horizontal direction, it is necessary to ensure that the surface electric field across the cross-section in both directions does not exceed the critical breakdown voltage for a given breakdown voltage. According to the invention, the peak values of the surface electric fields at AA 'and BB' positions are reduced by optimally designing the floating polycrystalline field plate and the metal field plate. In addition, the existence of the field plate can optimize the electric field and simultaneously can further shield the influence of the electric charges on the electric field of the semiconductor surface.
Example 2
Fig. 5(a) is a schematic cross-sectional structure diagram of a super junction MOS device 003 according to the second embodiment of the present invention. With respect to device 002 of the first embodiment of the present invention, device 003 also has the following characteristics: the length of the polysilicon gate electrode (323) at the junction of the active region and the termination region of the device extending into the termination region is longer, and in general, the polysilicon gate electrode (223) at the junction of the active region and the termination region of the device of the first embodiment covers n-The width and length of the type doped region (201) are generally 10-20 um; the second embodiment has a polysilicon gate electrode (323) at the junction of the active region and the termination region covering more than one set of n-A type-doped region (301) and p-A type-doped region (302) generally greater than 40um in length; and a gate oxide layer (311) is arranged below the polycrystalline silicon gate electrode (323) at the joint of the active region and the terminal region of the device, and the thickness is 0.08 um-0.12 um. This feature of device 003 is beneficial for increasing the gate-drain capacitance C of super junction MOS devicegdCapacitor of gate-drain type CgdThe larger the super junction MOS device is, the slower the switching process is, and the soft switching performance of the device can be improved. FIG. 5(b) shows the gate-drain capacitance CgdWith drain-source voltage VDSGraph of the variation. With drain-source voltage VDSIncrease of (2), gate-drain capacitance CgdSharply decreases when the drain-source voltage VDSAfter the voltage is increased to a certain value (generally 20V-50V, the value is related to the structural parameters of the super junction MOS device), the grid-drain capacitance CgdSlightly increased and finally stabilized to a certain value. For the first embodiment, the gate-drain capacitance CgdAt a high drain-source voltage VDSLower (greater than 100V), grid leakage capacitance CgdLess than 5 pF; by adopting the second embodiment, under the condition that the coverage length of a polysilicon gate electrode (323) at the joint of the active region and the terminal region of the device is more than 40um, the gate-drain capacitance CgdGreater than 10 pF.
Example 3
Fig. 6(a) is a top view of a super junction MOS device 004 according to the third embodiment of the present invention. Comparing the top view of the first embodiment, this exampleThe embodiments have the following characteristics: at the four corners of the device, the p-pillars (402) have a rounded, chamfered arrangement with a radius of curvature (typically greater than 50um) that may be the same or different from the radius of curvature of either the floating poly field plate (426) or the floating metal field plate (424). The characteristic of the device 004 is beneficial to improving the breakdown characteristic of the device and reducing the leakage current of the device. This is because in the actual device manufacturing process, the n pillars (401) and the p pillars (402) arranged in a periodic manner are cut off at the edge of the device, the chamfer arrangement at the four corners is beneficial to the uniformity of the device manufacturing, and the depletion layer can be guaranteed to be limited in the floating metal field plate (424) at the outermost periphery when the device breaks down. FIG. 6(b) shows leakage current I of a device employing the first and third embodimentsDSSAs a result of experiments, the leakage current I of the device can be reduced by adopting the round chamfer arrangement form of the p pillars (402) of the third embodimentDSSAnd a leakage current IDSSThe discreteness is small.
Example 4
Fig. 7 is a top view of a super junction MOS device 005 according to a fourth embodiment of the present invention. Comparing the top view of the third embodiment, this embodiment has the following features: the floating polycrystalline field plate (526) has island-shaped structures in a direction (x-axis direction) perpendicular to the p-pillar (502), and the island-shaped structures are not connected with each other. The position of the p-pillar is positioned between adjacent p-pillars or overlapped with the p-pillar on one side or overlapped with the p-pillars on both sides; the floating polycrystalline field plate (526) is connected with the four chamfer positions into a whole in the direction (z-axis direction) parallel to the p column (502) and has the same potential. The floating metal field plate (524) may have a ring structure as the polycrystalline field plate (426) in fig. 6, or may have a floating island structure in the same form as the floating polycrystalline field plate (526) in fig. 7. The 005 floating island type floating field plate structure of the device is beneficial to reducing the parasitic capacitance of the device and improving the response speed of the device. On the other hand, the floating island type polysilicon floating field plate is beneficial to releasing the stress of polysilicon and improving the reliability of the device.
Claims (10)
1. A super junction device comprises a drain electrode positioned at the bottom, a heavily doped first conduction type substrate area positioned above the drain electrode, a drift layer, an active area and a terminal area, wherein the drift layer is positioned above the heavily doped first conduction type substrate area and consists of a series of first conduction type doped areas and second conduction type doped areas which are alternately arranged; the device is characterized in that the terminal region comprises a field oxide layer positioned above the drift layer, more than one floating polycrystalline field plate positioned on the upper surface of the field oxide layer, and a floating metal field plate positioned above the floating polycrystalline field plate and at least covering the interval of two adjacent floating polycrystalline field plates, wherein the floating polycrystalline field plate is isolated from the floating metal field plate through an interlayer dielectric layer, and the floating polycrystalline field plate extends from the center position of the second conductive type doping region to the position above the adjacent or separated first conductive type doping region.
2. The superjunction device of claim 1, wherein the termination region has a length in a range between 50um and 300 um.
3. The superjunction device of claim 1, wherein a thickness of the field oxide layer under the floating polycrystalline field plate is 0.6um to 2.0 um.
4. The superjunction device of claim 1, wherein a polysilicon gate electrode is disposed at the junction of the active region and the termination region, the polysilicon gate electrode extending to the termination region for a length that covers at least one of the first conductivity-type doped region and the second conductivity-type doped region, and a gate oxide layer is disposed below the polysilicon gate electrode.
5. The superjunction device of claim 4, wherein the cover length is greater than 40um, and the gate oxide layer has a thickness of 0.08um to 0.12 um.
6. The superjunction device of claim 1, wherein the second-conductivity-type-doped regions at the corners of the device have a rounded-off arrangement.
7. The superjunction device of claim 6, wherein a radius of curvature of the chamfer is greater than 50 um.
8. The superjunction device of claim 1, wherein the floating polycrystalline field plates and/or floating metal field plates in the X-axis direction are non-interconnected floating island structures.
9. The method for manufacturing a superjunction device according to any of claims 1 to 8, wherein the method for manufacturing comprises the steps of:
1) forming a drift layer consisting of first conductive type doping regions and second conductive type doping regions which are alternately arranged on a semiconductor substrate;
2) growing a field oxide layer by thermal oxidation, and defining an active region by photoetching;
3) injecting and growing a gate oxide layer by the JFET;
4) depositing first conductive type polycrystalline silicon to manufacture a gate electrode and a floating polycrystalline field plate;
5) injecting boron by taking the polycrystalline silicon as a mask and pushing the junction to form a second conductive type body region;
6) doping and injecting the first conductive type to form a heavily doped first conductive type source region and a first conductive type termination ring of the device;
7) performing boron injection to form a heavily doped second conductive type contact region;
8) depositing an interlayer medium and etching a contact hole;
9) and sputtering metal Al to form a source electrode and a floating metal field plate.
10. The method for manufacturing a superjunction device according to claim 9, wherein the second conductivity type body region uses a polysilicon gate electrode as an implantation blocking layer, and the polysilicon gate electrode and the floating polysilicon field plate are formed simultaneously.
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