WO2024055667A1 - 一种电容结构、电容阵列、存储器及电子设备 - Google Patents

一种电容结构、电容阵列、存储器及电子设备 Download PDF

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Publication number
WO2024055667A1
WO2024055667A1 PCT/CN2023/101624 CN2023101624W WO2024055667A1 WO 2024055667 A1 WO2024055667 A1 WO 2024055667A1 CN 2023101624 W CN2023101624 W CN 2023101624W WO 2024055667 A1 WO2024055667 A1 WO 2024055667A1
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Prior art keywords
field effect
effect transistor
electrode
trench
layer
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PCT/CN2023/101624
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English (en)
French (fr)
Inventor
景蔚亮
殷士辉
章文强
王昭桂
王正波
廖恒
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华为技术有限公司
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Publication of WO2024055667A1 publication Critical patent/WO2024055667A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a capacitor structure, capacitor array, memory and electronic equipment.
  • Decoupling capacitor (DeCAP) circuit is usually placed between the power line and the ground line during circuit design. It can supplement current to the circuit when the transient current increases and the voltage drops. To prevent the power line voltage from dropping or the ground line voltage from rising.
  • the DeCAP circuit In current DRAM chips, the DeCAP circuit has a large area overhead and will reduce the storage density of the memory chip. Therefore, a DeCAP circuit with a smaller area overhead and higher density is urgently needed for DRAM chips.
  • This application provides a capacitor structure, capacitor array, memory and electronic device, which can reduce the area overhead of the DeCAP circuit.
  • the present application provides a capacitor structure, which may include at least one field effect transistor.
  • the at least one field effect transistor mainly includes a stacked structure, a channel layer, a gate oxide layer and a gate electrode.
  • the stacked structure may include a first electrode, a dielectric layer and a second electrode that are stacked sequentially along the stacking direction, wherein the first electrode may be a source electrode and the second electrode may be a drain electrode, or the first electrode may be a drain electrode.
  • pole, the second pole can be the source pole.
  • a trench is provided on the stacked structure, the opening of the trench is located on the upper surface of the second pole, and the trench penetrates the second pole and the dielectric layer.
  • the channel layer can cover the sidewalls and bottom of the trench, and the channel layer does not fill the trench, leaving enough space in the trench to accommodate the gate oxide layer and gate electrode.
  • the gate oxide layer can cover the channel layer, and the gate oxide layer will not fill the trench, leaving enough space in the trench to accommodate the gate electrode, that is, the gate oxide layer will define a space for accommodating the gate electrode. Area.
  • the gate fills the area defined by the gate oxide layer and overflows from the trench, extending above the stacked structure.
  • the first and second electrodes of the field effect transistor need to be short-circuited as a metal layer of the MOS capacitor.
  • the gate of the field effect transistor can be used as another metal layer of the MOS capacitor. Between the gate and source and drain A capacitive electric field is formed between them.
  • the first pole and the second pole may be connected through a via hole, and the via hole may be a connection hole or other vertical interconnection structure.
  • the capacitor structure can be specifically used as a decoupling capacitor structure in memory chips. In order to prevent the power line voltage from dropping or the ground line voltage from rising, the decoupling capacitor structure needs to be connected between the power line and the ground line, and the source and drain of the field effect transistor.
  • the gate of the field effect transistor as another metal layer of the MOS capacitor, can be connected to the other one of the power line or the ground line. Specifically, the source and drain of the field effect transistor can be connected to the power line, and the gate of the field effect transistor can be connected to the ground line; or vice versa.
  • the horizontal projected area can be reduced compared with the planar field effect transistor.
  • the two metal layers forming the capacitor structure are vertically distributed, the horizontal projected area can be reduced compared to the planar capacitor structure, thereby reducing the area overhead of the capacitor.
  • the capacitance value of the capacitor structure can be adjusted by adjusting the groove depth of the trench (that is, the trench length in the stacking direction).
  • the trench in the field effect transistor can be submerged into part of the first electrode, that is, the trench can be submerged into the inside of the first electrode, which can increase the contact area between the channel layer and the first electrode, thereby increasing the contact area between the channel layer and the first electrode. Increase the capacitance value of the capacitor structure.
  • the gate in addition to the gate extending above the stacked structure, can also extend in a plane perpendicular to the stacking direction, which can increase the facing area between the gate and the second electrode, thereby increasing the area between the gate and the second electrode.
  • the capacitance value of the capacitor structure can be increased.
  • both the channel layer and the gate oxide layer can also extend above the stacked structure, and both the channel layer and the gate oxide layer can also extend in a plane perpendicular to the direction of the stacked layer, thereby increasing the The contact area between the second electrode and the channel layer can increase the capacitance value of the capacitor structure.
  • first pole and the second pole of the field effect transistor can be interchanged, and no specific distinction is made.
  • the first pole and the second pole may be formed of conductive materials such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), Al, Cu, Ru, Ag, or any combination thereof, No limitation is made here.
  • the gate may be formed of conductive materials such as metal, such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, or any combination thereof.
  • metal such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, or any combination thereof.
  • the gate oxide layer can be formed using insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof, a stacked structure, or a stacked structure of combined materials, which is not limited here.
  • the channel layer can be formed of semiconductor materials, such as Si, polycrystalline Si, amorphous Si, In-Ga-Zn-O (IGZO) multi-component compounds, ZnO, ITO, TiO2, MoS2 and other semiconductor materials, or their combinations. random combination.
  • semiconductor materials such as Si, polycrystalline Si, amorphous Si, In-Ga-Zn-O (IGZO) multi-component compounds, ZnO, ITO, TiO2, MoS2 and other semiconductor materials, or their combinations. random combination.
  • the dielectric layer may be formed of insulating materials, such as SiO2, Si3N4, Al2O3 and other insulating materials, which are not limited here.
  • the capacitance structure may include a plurality of stacked field effect transistors.
  • the capacitor structure may include a stacked first field effect transistor and a second field effect transistor.
  • the second field effect transistor may be stacked on top of the first field effect transistor.
  • the stacked arrangement of the first field effect transistor and the second field effect transistor can reduce the area overhead of the capacitor structure, and the first field effect transistor and the second field effect transistor can be arranged in parallel to increase the capacitance value.
  • the first electrode and the second electrode of the first field effect transistor can be connected to the gate electrode of the second field effect transistor after being short-circuited.
  • the metal layer can be connected to the power line.
  • the first electrode and the second electrode of the first field effect transistor can be electrically connected to the gate electrode of the second field effect transistor through the same first via hole, and the connection area can be reduced through the same first via hole. area overhead.
  • the first electrode and the second electrode of the second field effect transistor can be connected to the gate electrode of the first field effect transistor after being short-circuited, and another metal layer serving as the capacitor structure can be connected to the ground wire, for example.
  • the first electrode and the second electrode of the second field effect transistor can be electrically connected through the second via hole, and the gate electrode of the first field effect transistor and the first electrode of the second field effect transistor can be stacked so that they are The two are in contact with each other to achieve the relationship that the two are conductive and can transmit electrical signals, which is different from the connection method of conduction through the first via hole and the second via hole.
  • the positions of the first via hole and the second via hole do not overlap and can be arranged at any position, which is not limited here.
  • the projection of the trench center position of the first field effect transistor and the trench center position of the second field effect transistor in the horizontal direction can overlap each other.
  • the trench center positions of the stacked field effect transistors can also be staggered, which is not limited here.
  • the horizontal cross-sectional shape of the trench of the field effect transistor may be circular or other shapes that are convenient for formation.
  • the following description takes the horizontal cross-sectional shape of the trench as circular as an example.
  • the horizontal projections of the trench aperture of the first field effect transistor and the trench aperture of the second field effect transistor can be mutually exclusive. coincide.
  • the trench apertures of the stacked field effect transistors can also be set to be different.
  • the trench aperture of the first field effect transistor can be larger than and cover the trench aperture of the second field effect transistor. .
  • the capacitance value can be controlled by adjusting the trench depth.
  • the present application provides a capacitor array, which may include a plurality of first field effect transistors located in a first-layer memory array and arranged in an array. Wherein, each first field effect transistor can form a capacitor structure.
  • the first field effect transistor has a structure similar to the field effect transistor provided in the first aspect, and mainly includes a stacked structure, a channel layer, a gate oxide layer and a gate electrode.
  • the stacked structure may include a first pole, a dielectric layer and a second pole that are stacked sequentially along the stacking direction, and a trench is provided in the stacked structure. The opening of the trench is located on the upper surface of the second pole, and the trench runs through the third pole. diodes and dielectric layers.
  • the channel layer may cover the sidewalls and bottom of the trench
  • the gate oxide layer may cover the channel layer
  • the gate electrode fills the area defined by the gate oxide layer and overflows from the trench.
  • the first electrode may be a source electrode
  • the second electrode may be a drain electrode, or the first electrode may be a drain electrode, and the second electrode may be a source electrode.
  • the first and second electrodes of the field effect transistor need to be short-circuited as a metal layer of the MOS capacitor.
  • the gate of the field effect transistor can be used as another metal layer of the MOS capacitor. Between the gate and source and drain A capacitive electric field is formed between them.
  • the capacitor structure can be specifically used as a decoupling capacitor structure.
  • the decoupling capacitor structure In order to prevent the power line voltage from dropping or the ground line voltage from rising, the decoupling capacitor structure needs to be connected between the power line and the ground line.
  • the source and drain of the field effect transistor serve as a MOS capacitor.
  • the metal layer can be connected to one of the power line or the ground line, and the gate of the field effect transistor, which is the other metal layer of the MOS capacitor, can be connected to the other of the power line or the ground line.
  • the source and drain of each first field effect transistor can be connected to the power line, and the gate of each first field effect transistor can be connected to the ground line; or vice versa.
  • each first field effect transistor in each row can be arranged at equal intervals, and each first field effect transistor in each column can also be arranged at equal intervals. arrangement.
  • the first pole of each first field effect transistor in each row can be connected to the first connection portion extending along the row direction.
  • the second pole of each first field effect transistor in each row is connected to the second connection portion extending along the row direction, and the first connection portion and the second connection portion of the first field effect transistor in the same row are connected.
  • the connection parts are connected through the first via holes to achieve short-circuiting of the source and drain of each first field effect transistor in the same row.
  • the number of rows of the first field effect transistors may be the same as the number of first via holes.
  • the first field effect transistor in each column The gate of each first field effect transistor may also be connected through a fourth connection portion extending in the column direction so as to be connected to one of the power line or the ground line.
  • first field effect transistors among the plurality of first field effect transistors located in the first layer memory array and arranged in an array.
  • Spaced arrangement means that the first electrodes of the plurality of first field effect transistors can be integrally arranged, the second electrodes of the plurality of first field effect transistors can be integrally arranged, and the gate electrodes of the plurality of first field effect transistors can be integrally arranged.
  • the integrated arrangement mentioned here means that the components are located on the same plane and connected with each other to form a whole. For example, the integrated first pole and the second pole may be short-circuited through a first via hole at the edge of the first field effect transistor in a row.
  • the capacitor array may also include a plurality of first field effect transistors located in the first layer storage array, which are stacked A plurality of second field effect transistors located in the second layer memory array and arranged in an array.
  • the structure of each second field effect transistor is the same as that of each first field effect transistor, and will not be described again here.
  • Each second field effect transistor may independently form a capacitor structure, or each first field effect transistor among the plurality of first field effect transistors may be combined with each second field effect transistor among the plurality of second field effect transistors.
  • the one-to-one corresponding arrangement allows a first field effect transistor and a second field effect transistor arranged in a one-to-one correspondence to be stacked and form a capacitor structure.
  • the first electrode and the second electrode of each second field effect transistor in the plurality of second field effect transistors are connected to each other and connected to the gate electrode of each first field effect transistor; the plurality of second field effect transistors
  • the gate electrode of each second field effect transistor is connected to each other, and is connected to the first electrode and the second electrode of each first field effect transistor.
  • each second field effect transistor in each row of second field effect transistors can be arranged at equal intervals, and each second field effect transistor in each column of second field effect transistors can also be arranged at equal intervals. arrangement.
  • the first electrode of each second field effect transistor in each column can be connected to a fourth connection portion extending along the column direction.
  • the second electrode of each second field effect transistor in each column is connected to the fifth connection part extending along the column direction, and the fourth connection part and the fifth connection part of the second field effect transistor in the same column are connected
  • the connection part is connected through the second via hole, so that the source and drain of each second field effect transistor in the same column of second field effect transistors are short-circuited, and the source and drain of each first field effect transistor in each column of first field effect transistor are short-circuited.
  • the gate electrode may be disposed in contact with the first electrode of the corresponding second field effect transistor so as to be connected to one of the power line or the ground line. Furthermore, the gate electrode of each second field effect transistor in each row may be connected to a third connection part extending along the row direction, and the first connection part, the second connection part and the third connection part in the same row The three connection parts are connected through a first via hole to connect the first pole and the second pole of the first field effect transistor in the same row to the gate of the second field effect transistor so as to be connected to the other one of the power line or the ground line. .
  • the capacitor array in order to increase the circuit density of the capacitor array, there may be no need for a gap between adjacent second field effect transistors among the plurality of second field effect transistors located in the second layer memory array and arranged in an array.
  • the arrangement is spaced, that is, the first electrodes of the plurality of second field effect transistors can be integrally arranged, the second electrodes of the plurality of second field effect transistors can be integrally arranged, and the gate electrodes of the plurality of second field effect transistors can be integrally arranged.
  • the integrated arrangement mentioned here means that the components are located on the same plane and connected with each other to form a whole.
  • the first field effect transistor in a row can be The other side edges of the two field effect transistors short-circuit the integrated first and second electrodes through a second via hole, and the integrated gate of the first field effect transistor and the integrated gate of the second field effect transistor are The first pole can be set in contact.
  • the number and location of the first via holes and the second via holes are not limited.
  • the first via holes and the second via holes can be arranged at the edge of each row or at the edge of each column. , the first via hole can also be provided at the edge of each row, and the second via hole can be provided at the edge of each column.
  • more layers of field effect transistors can also be stacked, so that the capacitor array can have alternately arranged multi-layer first-layer memory arrays and multi-layer second-layer memory arrays, and in a second layer An insulating layer may be provided between the storage array and a first-level storage array thereon.
  • the alternately arranged multi-layer first-layer memory arrays and multi-layer second-layer memory arrays may share the first via hole and the second via hole.
  • the present application provides a memory, which may include a plurality of memory cell arrays (memory arrays) and a memory controller connected to each of the plurality of memory unit arrays.
  • the plurality of memory unit arrays may Some memory cell arrays are used as redundant arrays (dummy arrays), and the redundant arrays can be designed as the above-mentioned capacitor arrays provided in the embodiments of the present application, which can improve the storage efficiency of the memory chip.
  • the line width of the power line and the ground line connected to the capacitor array will be wider than the line width of the signal line in the normal memory cell array.
  • the present application provides an electronic device.
  • the electronic device includes a processor and a memory coupled to the processor.
  • the memory may be the memory provided in the third aspect of the present application.
  • the processor can call the software program stored in the memory to execute the corresponding method and realize the corresponding function of the electronic device.
  • Figure 1 is a circuit schematic diagram of a capacitor structure provided by an embodiment of the present application.
  • Figure 2a is a schematic cross-sectional view of the capacitor structure provided by the embodiment of the present application.
  • Figure 2b is another schematic cross-sectional view of the capacitor structure provided by the embodiment of the present application.
  • Figure 3 is a three-dimensional structural schematic diagram of the capacitor structure provided by the embodiment of the present application.
  • FIG. 4 is another circuit schematic diagram of the capacitor structure provided by the embodiment of the present application.
  • Figure 5a is another schematic cross-sectional view of the capacitor structure provided by the embodiment of the present application.
  • Figure 5b is another schematic cross-sectional view of the capacitor structure provided by the embodiment of the present application.
  • Figure 5c is another schematic cross-sectional view of the capacitor structure provided by the embodiment of the present application.
  • Figure 6 is a schematic diagram of another three-dimensional structure of the capacitor structure provided by the embodiment of the present application.
  • Figure 7 is a schematic circuit diagram of a capacitor array provided by an embodiment of the present application.
  • Figure 8 is a schematic cross-sectional view of a capacitor array provided by an embodiment of the present application.
  • Figure 9 is a schematic diagram of a three-dimensional structure of a capacitor array provided by an embodiment of the present application.
  • Figure 10 is another circuit schematic diagram of a capacitor array provided by an embodiment of the present application.
  • Figure 11 is another schematic cross-sectional view of a capacitor array provided by an embodiment of the present application.
  • Figure 12 is a schematic three-dimensional structural diagram of a capacitor structure in the capacitor array provided by the embodiment of the present application.
  • Figure 13 is another circuit schematic diagram of the capacitor array provided by the embodiment of the present application.
  • Figure 14 is another schematic cross-sectional view of a capacitor array provided by an embodiment of the present application.
  • Figure 15 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • Figure 16 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the DeCAP circuit provided by the embodiment of the present application can be applied to memories such as DRAM.
  • a DeCAP circuit is placed between the power line and the ground line of the memory. It can supplement the current to the circuit when the transient current increases and the voltage drops to prevent the power line voltage from falling or the ground line voltage from rising.
  • This memory can be used for data storage in electronic devices such as mobile phones, tablets, laptops, wearable devices, and vehicle-mounted devices.
  • this application provides The DeCAP circuit and memory can also be applied to other electronic devices without limitation here.
  • MIM capacitors metal-insulator-metal (MIM) capacitors
  • MOM metal-oxide-metal
  • MOS metal oxide semiconductor
  • the MIM capacitor is formed by two parallel metal layers with a high-k dielectric between them.
  • MOM capacitors are similar to MIM capacitors, except that the high-k dielectric is replaced by an oxide, and the metal layer and the oxide are intertwined.
  • the MOS capacitor is formed by short-circuiting the source and drain of the MOS transistor.
  • the gate oxide layer of the MOS transistor serves as the oxide, and the short-circuited source, drain and gate serve as the two metal layers of the MOS capacitor.
  • DeCAP circuits based on MIM capacitors, MOM capacitors or MOS capacitors will occupy memory chip resources, increase area overhead, and reduce the storage density of the memory chip.
  • the chip itself does not have a capacitor used as a DeCAP circuit.
  • the DeCAP circuit needs to be set up to improve the stability of the power line voltage.
  • a DeCAP circuit based on MIM capacitors or MOS capacitors is used, a similar implementation to 1T1C-based DRAM can be achieved.
  • the DeCAP circuit in the chip has a huge process overhead, and the DeCAP circuit will occupy chip resources and reduce the memory unit area efficiency of the chip. Therefore, there is an urgent need for a DeCAP circuit with smaller area overhead and higher density for DRAM chips.
  • This application uses field effect transistors with vertically distributed channel layers to implement the DeCAP circuit, which can reduce the area overhead caused by the DeCAP circuit. And by using an array of field-effect transistors with vertically distributed channel layers, placing them in the memory can increase the density of the DeCAP circuit and the storage density of the memory chip.
  • Figure 1 illustrates a schematic circuit diagram of the capacitor structure provided by the embodiment of the present application.
  • Figure 2a illustrates a schematic cross-sectional view of the capacitor structure provided by the embodiment of the present application.
  • Figure 2b illustrates the capacitor structure provided by the embodiment of the present application.
  • FIG. 3 shows a schematic three-dimensional structure of the capacitor structure provided by the embodiment of the present application.
  • the capacitor structure provided by the embodiment of the present application may include at least one field effect transistor 1; at least one field effect transistor 1 mainly includes a stacked structure 10, a channel layer 11, a gate oxide layer 12 and a gate electrode. 13.
  • the stacked structure 10 may include a first electrode 01 , a dielectric layer 02 and a second electrode 03 that are stacked sequentially along the stacking direction Z, wherein the first electrode 01 may be a source electrode and the second electrode 03 may be a drain electrode, or , the first pole 01 can be the drain, and the second pole 03 can be the source.
  • a trench V is opened on the laminated structure 10 . The opening of the trench V is located on the upper surface of the second pole 03 .
  • the trench V penetrates the second pole 03 and the dielectric layer 02 .
  • the trench V can only penetrate to the surface of the first pole 01, so that the bottom of the trench V is located on the surface of the first pole 01, or, referring to Figure 2b, the trench V can further penetrate to the first pole 01 inside, so that the bottom of the trench V is located inside the first pole 01.
  • the channel layer 11 can cover the sidewalls and bottom of the trench V, and the channel layer 11 will not fill the trench V, leaving enough space in the trench V to accommodate the gate oxide layer 12 and Gate 13.
  • the gate oxide layer 12 can cover the channel layer 11 with a space in between, that is, the gate oxide layer 12 will not fill the trench V, leaving enough space in the trench V to accommodate the gate electrode 13. That is, the gate oxide layer 12 will define a region for accommodating the gate electrode.
  • the gate electrode 13 fills the area defined by the gate oxide layer 12 and overflows from the trench V, extending to above the stacked structure 10 .
  • the first pole 01 and the second pole 03 of the field effect transistor 1 need to be short-circuited as a metal layer of the MOS capacitor.
  • the gate 13 of the field effect transistor 1 can be used as another metal layer of the MOS capacitor.
  • a capacitive electric field is formed between pole 13 and the source and drain.
  • the first pole 01 and the second pole 03 may be connected through a via 14, and the via 14 may be a connection via or other vertical interconnection structure.
  • the capacitor structure can be specifically used as a decoupling capacitor structure in memory chips. In order to prevent the power line voltage from dropping or the ground line voltage from rising, the decoupling capacitor structure needs to be connected between the power line and the ground line.
  • the source of the field effect transistor 1 The drain serves as a metal layer of the MOS capacitor and can be connected to one of the power line or the ground line.
  • the gate 13 of the field effect transistor 1 serves as another metal layer of the MOS capacitor and can be connected to the other of the power line or the ground line. Specifically, the source and drain of the field effect transistor 1 may be connected to the power line VPP, and the gate 13 of the field effect transistor 1 may be connected to the ground line VBB; or vice versa.
  • the horizontal projected area can be reduced compared with a planar field effect transistor.
  • the two metal layers forming the capacitor structure are vertically distributed, the horizontal projected area can be reduced compared to the planar capacitor structure, thereby reducing the area overhead of the capacitor.
  • the capacitance value of the capacitor structure can be adjusted.
  • the trench V in the field effect transistor 1 can be submerged into part of the first pole 01, that is, the trench V can be submerged into the first pole 01, which can increase the size of the channel layer.
  • the contact area between 11 and the first pole 01 thereby increases the capacitance value of the capacitor structure.
  • the gate 13 in addition to extending to the top of the stacked structure 10, can also be on Extending in a plane perpendicular to the stacking direction Z can increase the facing area between the gate electrode 13 and the second electrode 03 , thereby increasing the capacitance value of the capacitor structure.
  • the channel layer 11 and the gate oxide layer 12 can also extend above the stacked structure 10, and the channel layer 11 and the gate oxide layer 12 can also extend in a plane perpendicular to the stacking direction Z, thereby increasing the contact area between the second pole 03 and the channel layer 11, thereby increasing the capacitance value of the capacitor structure.
  • first pole 01 and the second pole 03 of the field effect transistor 1 can be interchanged, and no specific distinction is made.
  • the first pole 01 and the second pole 03 may be made of conductive materials such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), Al, Cu, Ru, Ag or any combination thereof. Formation is not limited here.
  • the gate 13 may be formed of conductive materials such as metal, such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, or any combination thereof.
  • the gate oxide layer 12 can be made of insulating materials such as SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , Si 3 N 4 or any combination thereof, a stacked structure, and The composite material is formed in a laminated structure, which is not limited here.
  • the channel layer 11 can be formed of semiconductor materials, such as Si, polycrystalline Si, amorphous Si, In-Ga-Zn-O (IGZO) multicomponent compound, ZnO, ITO, TiO 2 , MoS 2 and other semiconductor materials. Or any combination of them.
  • semiconductor materials such as Si, polycrystalline Si, amorphous Si, In-Ga-Zn-O (IGZO) multicomponent compound, ZnO, ITO, TiO 2 , MoS 2 and other semiconductor materials. Or any combination of them.
  • the dielectric layer 02 may be formed of insulating materials, such as SiO 2 , Si 3 N 4 , Al 2 O 3 and other insulating materials, which are not limited here.
  • Figure 4 illustrates another schematic circuit diagram of the capacitor structure provided by the embodiment of the present application.
  • Figure 5a illustrates another schematic cross-sectional view of the capacitor structure provided by the embodiment of the present application.
  • Figure 5b illustrates the schematic diagram of another circuit of the capacitor structure provided by the embodiment of the present application.
  • FIG. 5c Another schematic cross-sectional view of the capacitor structure provided by the embodiment of the present application is shown in FIG. 5c
  • FIG. 6 is a schematic diagram of another three-dimensional structure of the capacitor structure provided by the embodiment of the present application. .
  • the capacitance structure may include multiple stacked field effect transistors.
  • the capacitor structure may include a stacked first field effect transistor 1 a and a second field effect transistor 1 b.
  • the second field effect transistor 1 b may be stacked on the first field effect transistor. above 1a.
  • the stacked arrangement of the first field effect transistor 1a and the second field effect transistor 1b can reduce the area overhead of the capacitor structure, and the first field effect transistor 1a and the second field effect transistor 1b can be arranged in parallel to increase the capacitance value.
  • the first electrode 01a and the second electrode 03a of the first field effect transistor 1a can be connected to the gate electrode 13b of the second field effect transistor 1b after being short-circuited.
  • a metal layer of the capacitor structure for example, it can be connected to the power line VPP.
  • the first electrode 01a and the second electrode 03a of the first field effect transistor 1a may be electrically connected to the gate electrode 13b of the second field effect transistor 1b through the same first via hole 14a.
  • the hole 14a connection can reduce the area overhead of the connection area.
  • the first electrode 01b and the second electrode 03b of the second field effect transistor 1b can be connected to the gate electrode 13a of the first field effect transistor 1a after being short-circuited.
  • the capacitor structure As another metal layer of the capacitor structure, for example, it can be connected to the ground line VBB. connect.
  • the first pole 01b and the second pole 03b of the second field effect transistor 1b may be electrically connected through the second via hole 14b
  • the gate electrode 13a of the first field effect transistor 1a and the first pole 03b of the second field effect transistor 1b may be electrically connected through the second via hole 14b.
  • the poles 01b can be stacked so that they are in contact with each other, so that the two are connected and can transmit electrical signals, which is different from the connection method of conducting through the first via hole 14a and the second via hole 14b.
  • the positions of the first via hole 14a and the second via hole 14b do not overlap and can be arranged at any position, which is not limited here.
  • the trench center position of the first field effect transistor 1a and the trench center position of the second field effect transistor 1b coincide with each other.
  • the trench center positions of multiple stacked field effect transistors can also be staggered, which is not limited here.
  • the horizontal cross-sectional shape of the trench of the field effect transistor may be circular or other shapes that are convenient for formation.
  • the following description takes the horizontal cross-sectional shape of the trench as circular as an example.
  • the trench aperture of the first field effect transistor 1a and the trench aperture of the second field effect transistor 1b can be overlap each other.
  • the trench apertures of multiple stacked field effect transistors can also be set to be different.
  • the trench aperture of the first field effect transistor 1a can be larger than and cover the second field effect transistor. Trench aperture of transistor 1b.
  • the capacitance value can be controlled by adjusting the trench depth.
  • embodiments of the present application also provide a capacitor array.
  • Figure 7 illustrates a schematic circuit diagram of the capacitor array provided by the embodiment of the present application.
  • Figure 8 illustrates a schematic cross-sectional view of the capacitor array provided by the embodiment of the present application.
  • Figure 9 illustrates a schematic diagram of the capacitor array provided by the embodiment of the present application. Schematic diagram of a three-dimensional structure of the array.
  • the capacitor array provided by the embodiment of the present application may include a plurality of first field effect transistors 1a located in the first layer of memory array and arranged in an array.
  • Figure 7 illustrates that the capacitor array located in the first layer of memory array is The 12 first field effect transistors 1a are distributed in three rows and four columns in the storage array.
  • each first field effect transistor 1a can constitute a The capacitor structure, the first field effect transistor 1a is similar to the field effect transistor structure shown in Figure 2a, and mainly includes a stacked structure 10, a channel layer 11, a gate oxide layer 12 and a gate electrode 13.
  • the stacked structure 10 may include a first pole 01 , a dielectric layer 02 and a second pole 03 that are stacked sequentially along the stacking direction Z, and a trench is opened on the stacked structure 10 , and the opening of the trench is located at the second pole 03 On the upper surface, the trench penetrates the second pole 03 and the dielectric layer 02 .
  • the channel layer 11 can cover the sidewalls and bottom of the trench V
  • the gate oxide layer 12 can cover the channel layer 11
  • the gate electrode 13 fills the area defined by the gate oxide layer 12 and extends from the trench V.
  • Tank overflows.
  • the first electrode 01 may be a source electrode
  • the second electrode 03 may be a drain electrode
  • the first electrode 01 may be a drain electrode
  • the second electrode 03 may be a source electrode.
  • the first pole 01 and the second pole 03 of the field effect transistor 1 need to be short-circuited as a metal layer of the MOS capacitor.
  • the gate 13 of the field effect transistor 1 can be used as another metal layer of the MOS capacitor. A capacitive electric field is formed between pole 13 and the source and drain.
  • the capacitor structure can be specifically used as a decoupling capacitor structure.
  • the decoupling capacitor structure needs to be connected between the power line and the ground line.
  • the source and drain of the field effect transistor 1 serve as the MOS capacitor.
  • One metal layer may be connected to one of the power line or the ground line, and the gate 13 of the field effect transistor 1 as the other metal layer of the MOS capacitor may be connected to the other one of the power line or the ground line.
  • the source and drain of each first field effect transistor 1a may be connected to the power line VPP, and the gate 13a of each first field effect transistor 1a may be connected to the ground line VBB; or vice versa.
  • each first field effect transistor 1a in each row can be arranged at equal intervals, and each first field effect transistor 1a in each column can be arranged at equal intervals. They can also be arranged at equal intervals.
  • FIG. 8 illustrates a situation in which a row of first field effect transistors 1 a includes four equally spaced first field effect transistors 1 a.
  • the first pole 01a of each first field effect transistor 1a in each row can be connected to the first electrode 01a extending along the row direction.
  • the connecting portion 21 is connected.
  • the second pole 03a of each first field effect transistor 1a in each row is connected to the second connecting portion 22 extending along the row direction.
  • the first field effect transistor 1a in the same row is connected.
  • the connected first connection part 21 and the second connection part 22 are connected through the first via hole 14a to achieve a short circuit between the source and drain of each first field effect transistor 1a in the same row.
  • FIG. 9 illustrates a situation where there are two rows of first field effect transistors 1a and each row of first field effect transistors 1a includes two first field effect transistors 1a.
  • the number of rows of first field effect transistors 1a can be as many as the number of first via holes 14a. The numbers are the same.
  • the gate electrode 13a of each first field effect transistor 1a in each column may also be connected through a fourth connection portion 24 extending along the column direction, so as to be connected to a power line or a ground line. A connection.
  • adjacent first field effect transistors 1 a among the plurality of first field effect transistors 1 a located in the first layer memory array and arranged in an array are There is no need to set intervals, that is, the first poles 01a of the plurality of first field effect transistors 1a can be integrally arranged, the second poles 03a of the plurality of first field effect transistors 1a can be integrally arranged, and the plurality of first field effect transistors 01 can be integrally arranged.
  • the gate 13a may be provided integrally.
  • the integrated arrangement mentioned here means that the components are located on the same plane and connected with each other to form a whole. For example, referring to Fig.
  • the gates 13a of the four first field effect transistors 1a in a row of the first field effect transistors 1a in Fig. 8 are integrally arranged, the first pole 01a is integrally arranged, and the second pole 03a is integrally arranged.
  • the edges of a row of first field effect transistors 1a short-circuit the integrally arranged first pole 01a and the second pole 03a through a first via hole 14a.
  • Figure 10 illustrates another schematic circuit diagram of the capacitor array provided by the embodiment of the present application.
  • Figure 11 illustrates another schematic cross-sectional view of the capacitor array provided by the embodiment of the present application.
  • Figure 12 illustrates the schematic diagram of another circuit of the capacitor array provided by the embodiment of the present application. Schematic diagram of the three-dimensional structure of a capacitor structure in a capacitor array.
  • the capacitor array may also include multiple first fields located in the first layer storage array.
  • a plurality of second field effect transistors 1b located in the second-layer memory array and arranged in an array are stacked.
  • Figure 10 illustrates the second field-effect transistors 1b located in the first-layer memory array and arranged in three rows and two columns. 6 first field effect transistors 1a, and 6 second field effect transistors 1b distributed in three rows and two columns in the second layer memory array.
  • the structure of each second field effect transistor 1b is the same as the structure of each first field effect transistor 1a, and will not be described again here.
  • Each second field effect transistor 1 b may independently form a capacitor structure, or each first field effect transistor 1 a among the plurality of first field effect transistors 1 a and each first field effect transistor 1 b among the plurality of second field effect transistors 1 b may be combined.
  • the two field effect transistors 1b are arranged in one-to-one correspondence, so that a first field effect transistor 1a and a second field effect transistor 1b arranged in a one-to-one correspondence are stacked and form a capacitor structure.
  • first pole 01b and the second pole 03b of each second field effect transistor 1b in the plurality of second field effect transistors 1b are connected to each other and connected to the gate electrode 13a of each first field effect transistor 1a; and more The gate electrode 13b of each second field effect transistor 1b is connected to each other, and is connected to the first electrode 01a and the second electrode 03a of each first field effect transistor 1a.
  • a row of four first field effect transistors 1 a and a row of four second field effect transistors 1 b stacked thereon constitute four capacitor structures.
  • each second field effect transistor 1 b in each row of second field effect transistors 1 b may be arranged at equal intervals.
  • Each second field effect transistor 1 b in each column of the second field effect transistor 1 b may also be arranged at equal intervals.
  • FIG. 11 illustrates a situation in which a row of second field effect transistors 1 b includes four equally spaced second field effect transistors 1 b.
  • the first pole 01b of each second field effect transistor 1b in each column of the second field effect transistor 1b can be connected with a fourth electrode extending along the column direction.
  • the connecting portion 24 is connected.
  • the second pole 03b of each second field effect transistor 1b in each column is connected to the fifth connecting portion 25 extending along the column direction.
  • the second field effect transistor 1b in the same column is connected.
  • the connected fourth connection part 24 and the fifth connection part 25 are connected through the second via hole 14b, so that the source and drain of each second field effect transistor 1b in the same column of second field effect transistors 1b are short-circuited, and the second field effect transistor 1b in each column is connected.
  • the gate electrode 13a of each first field effect transistor 1a in the field effect transistor 1a may be disposed in contact with the first electrode 01b of the corresponding second field effect transistor 1b so as to be connected to one of the power line or the ground line.
  • the gate electrode 13b of each second field effect transistor 1b in each row may be connected to the third connection part 23 extending along the row direction, and the first connection part 21 and the third connection part 23 of the same row.
  • the second connection part 22 and the third connection part 23 are connected through a first via hole 14a to realize the first electrode 01a and the second electrode 03a of the first field effect transistor 1a in the same row and the gate electrode of the second field effect transistor 1b. to connect to the other one of the power or ground wires.
  • the gate 13b may be provided integrally.
  • the integrated arrangement mentioned here means that the components are located on the same plane and connected with each other to form a whole.
  • the gate electrodes 13a of the four first field effect transistors 1a in a row of Figure 11 are integrally provided, the first pole 01a is integrally provided, the second pole 03a is integrally provided, and a row
  • the gate electrodes 13b of the four first field effect transistors 1b of the second field effect transistor 1b are integrally arranged, the first electrode 01b is integrally arranged, and the second electrode 03b is integrally arranged.
  • the integrally arranged first electrode 01a and the second electrode 03a and the integrally arranged gate electrode 13b of the second field effect transistor are short-circuited through a first via hole 14a.
  • the other edge of the second field effect transistor 1b short-circuits the integrally arranged first electrode 01b and the second electrode 03b through a second via hole 14b, and the integrally arranged gate electrode 13a and the second electrode 03b of the first field effect transistor 1a.
  • the integrally arranged first pole 01b of the field effect transistor 1b may be arranged in contact.
  • the number and location of the first via holes 14a and the second via holes 14b are not limited.
  • the first via holes 14a and the second via holes 14b may be arranged at the edge of each row, or may be arranged at At the edge of each column, the first via hole 14a can also be provided at the edge of each row, and the second via hole 14a can be provided at the edge of each column.
  • FIG. 13 illustrates another schematic circuit diagram of the capacitor array provided by the embodiment of the present application
  • FIG. 14 illustrates yet another schematic cross-sectional view of the capacitor array provided by the embodiment of the present application.
  • more layers of field effect transistors can also be stacked, so that the capacitor array can have an alternately arranged multi-layer first-layer memory array and a multi-layer second-layer memory array.
  • an insulating layer 15 may be disposed between a second-level memory array and a first-level memory array above it.
  • the alternately arranged multi-layer first-layer memory arrays and multi-layer second-layer memory arrays may share the first via hole 14a and the second via hole 14b.
  • Figures 13 and 14 illustrate the situation of two layers of first layer storage arrays and two layers of second layer storage arrays.
  • Figure 15 shows a schematic structural diagram of a memory provided by an embodiment of the present application.
  • the memory provided by this embodiment may include multiple memory cell arrays (memory arrays) and a memory controller (not shown in the figure) connected to each of the multiple memory cell arrays.
  • Some of the memory cell arrays in the memory cell array may be used as redundant arrays (dummy arrays), and the redundant arrays may be designed as the above-mentioned capacitor arrays provided in the embodiments of the present application, which can improve the storage efficiency of the memory chip.
  • the line width of the power line and the ground line connected to the capacitor array will be wider than the line width of the signal line in the normal memory cell array.
  • FIG. 16 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device includes a processor 200 and a memory 100 coupled to the processor.
  • the memory 100 may be any memory provided in the above embodiments of the present application.
  • the processor 200 can call the software program stored in the memory 100 to execute the corresponding method and realize the corresponding function of the electronic device.

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Abstract

本申请提供了一种电容结构、电容阵列、存储器及电子设备，电容结构包括至少一个第一极和第二极连接的场效应晶体管，该场效应晶体管包括叠层结构、沟道层、栅氧化层和栅极，叠层结构包括依次层叠设置的第一极、介质层和第二极，且叠层结构上开设有沟槽，沟槽的开口位于第二极的上表面，沟槽贯穿第二极和介质层。沟道层覆盖沟槽的侧壁和底部，栅氧化层覆盖沟道层，栅极填充于栅氧化层所限定的区域且从沟槽中溢出。采用上述场效应晶体管构成电容结构可以减小面积开销，可以增加电容阵列的电路密度，并采用电容阵列作为冗余存储阵列，可以增加存储器的存储密度。

Description

一种电容结构、电容阵列、存储器及电子设备
相关申请的交叉引用
本申请要求在2022年09月15日提交中国专利局、申请号为202211124100.6、申请名称为“一种电容结构、电容阵列、存储器及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种电容结构、电容阵列、存储器及电子设备。
背景技术
在动态随机存储器(dynamic random-access memory，DRAM)等电路运行过程中，大量单元的同时翻转会导致器件充放电和瞬间电流增大，使电路动态供电电压下降或地线电压升高，引起电源线电压不稳定。为了提高电源线电压的稳定性，在电路设计时通常在电源线与地线之间放置去耦电容(decoupling capacitor，DeCAP)电路，它可以在瞬态电流增大和电压下降时向电路补充电流，以防止电源线电压下降或地线电压升高。
在当前的DRAM芯片中DeCAP电路的面积开销较大，且会降低存储芯片的存储密度，因此，对于DRAM芯片亟需一种面积开销较小且密度较高的DeCAP电路。
发明内容
本申请提供一种电容结构、电容阵列、存储器及电子设备，可以减小DeCAP电路的面积开销。
第一方面，本申请提供了一种电容结构，可以包括至少一个场效应晶体管，至少一个场效应晶体管主要包括叠层结构、沟道层、栅氧化层和栅极。叠层结构可以包括沿叠层方向依次层叠设置的第一极、介质层和第二极，其中，第一极可以为源极，第二极可以为漏极，或者，第一极可以为漏极，第二极可以为源极。且叠层结构上开设有沟槽，沟槽的开口位于第二极的上表面，沟槽贯穿第二极和介质层。在场效应晶体管中，沟道层可以覆盖沟槽的侧壁和底部，并且沟道层不会填满沟槽，使沟槽内保留足够的空间以容纳栅氧化层和栅极。在场效应晶体管中，栅氧化层可以覆盖沟道层，并且栅氧化层不会填满沟槽，使沟槽内保留足够的空间以容纳栅极，即栅氧化层会限定出用于容纳栅极的区域。在场效应晶体管中，栅极填充于栅氧化层所限定的区域且从沟槽中溢出，延伸至叠层结构的上方。为实现电容结构，场效应晶体管的第一极和第二极需要短接作为MOS电容的一个金属层，场效应晶体管的栅极可以作为MOS电容的另一个金属层，在栅极和源漏极之间形成电容电场。示例性地，第一极和第二极可以通过过孔连接，过孔具体可以是连接孔或其他垂直互联结构。电容结构具体可以作为应用于存储芯片中的去耦电容结构，去耦电容结构为防止电源线电压下降或地线电压升高，需要连接在电源线和地线之间，场效应晶体管的源漏极作为MOS电容的一个金属层可以与电源线或地线中的一个连接，场效应晶体管的栅极作为MOS电容的另一个金属层可以与电源线或地线中的另一个连接。具体地，场效应晶体管的源漏极可以与电源线连接，场效应晶体管的栅极可以与地线连接；或者反之亦可。
在本申请实施例中，由于场效应晶体管的沟道层呈垂直分布，因此相比平面型的场效应晶体管可以减小水平投影面积。并且，由于形成电容结构的两个金属层呈垂直分布，因此相比平面型的电容结构可以减小水平投影面积，以降低电容的面积开销。并且，在不增加场效应晶体管水平投影面积的情况下，通过调节沟槽的槽深(即在层叠方向的沟槽长度)，可以调节电容结构的电容值。
在一些可能的实施方式中，场效应晶体管中的沟槽可以没入部分第一极，即沟槽可以没入至第一极的里面，这样可以增大沟道层与第一极的接触面积，从而增大电容结构的电容值。
在一些可能的实施方式中，在栅极延伸至叠层结构的上方之外，栅极还可以在垂直于叠层方向的平面延伸，可以增大栅极与第二极的正对面积，从而可以增大电容结构的电容值。
在一些可能的实施方式中，沟道层和栅氧化层均还可以延伸至叠层结构的上方，且沟道层和栅氧化层均还可以在垂直于叠层方向的平面延伸，从而可以增加第二极与沟道层的接触面积，从而可以增大电容结构的电容值。
需要说明的是，在具体实施中，场效应晶体管的第一极和第二极可以互换，不做具体区分。
示例性地，第一极和第二极可以采用例如TiN、Ti、Au、W、Mo、In-Ti-O(ITO)、Al、Cu、Ru、Ag等导电材料或者它们的任意组合形成，在此不作限定。
示例性地，栅极可以采用金属等导电性材料形成，例如TiN、Ti、Au、W、Mo、ITO、Al、Cu、Ru、Ag等导电材料或者它们的任意组合。
示例性地，栅氧化层可以采用SiO2、Al2O3、HfO2、ZrO2、TiO2、Y2O3、Si3N4等绝缘材料或者它们的任意组合材料、叠层结构以及组合材料的叠层结构形成，在此不作限定。
示例性地，沟道层可以采用半导体材料形成，例如Si、多晶Si、非晶Si、In-Ga-Zn-O(IGZO)多元化合物、ZnO、ITO、TiO2、MoS2等半导体材料或者它们的任意组合。
示例性地，介质层可以采用绝缘材料形成，例如SiO2、Si3N4、Al2O3等绝缘材料，在此不作限定。
在一些可能的实施方式中，为了增大电容值，电容结构可以包括多个堆叠设置的场效应晶体管。具体地，电容结构可以包括堆叠设置的第一场效应晶体管和第二场效应晶体管，示例性地，第二场效应晶体管可以堆叠于第一场效应晶体管之上。第一场效应晶体管和第二场效应晶体管堆叠设置可以减小电容结构的面积开销，并且，第一场效应晶体管和第二场效应晶体管可以并联设置，以增大电容值。具体地，第一场效应晶体管的第一极和第二极短接后可以与第二场效应晶体管的栅极连接，作为电容结构的一个金属层例如可以与电源线连接。示例性地，第一场效应晶体管的第一极和第二极可以与第二场效应晶体管的栅极通过同一个第一过孔电连接，通过同一个第一过孔连接可以减小连接区域的面积开销。具体地，第二场效应晶体管的第一极和第二极短接后可以与第一场效应晶体管的栅极连接，作为电容结构的另一个金属层例如可以与地线连接。示例性地，第二场效应晶体管的第一极和第二极可以通过第二过孔电连接，第一场效应晶体管的栅极与第二场效应晶体管的第一极可以堆叠设置，使两者相互接触，达到两者导通可以传递电信号的关系，区别于通过第一过孔和第二过孔导通的连接方式。其中，第一过孔和第二过孔位置不交叠，且可以设置在任何位置，在此不做限定。
在一些可能的实施方式中，为了减小堆叠设置的多个场效应晶体管的水平投影面积，第一场效应晶体管的沟槽中心位置和第二场效应晶体管的沟槽中心位置在水平方向的投影可以相互重合。在本申请另一些实施例中，堆叠设置的多个场效应晶体管的沟槽中心位置也可以错开设置，在此不做限定。
在一些可能的实施方式中，为了便于制作，场效应晶体管的沟槽水平截面形状可以为圆形或其他便于形成的形状，下述均以沟槽的水平截面形状为圆形为例进行说明。在本申请一些实施例中，为了减小堆叠设置的多个场效应晶体管的水平投影面积，第一场效应晶体管的沟槽孔径和第二场效应晶体管的沟槽孔径在水平方向的投影可以相互重合。在本申请另一些实施例中，堆叠设置的多个场效应晶体管的沟槽孔径也可以设置为不同，例如第一场效应晶体管的沟槽孔径可以大于且覆盖第二场效应晶体管的沟槽孔径。在此基础上，可以通过调节沟槽的槽深控制电容值。
第二方面，本申请提供了一种电容阵列，可以包括位于第一层存储阵列内且呈阵列排布的多个第一场效应晶体管。其中，每一个第一场效应晶体管可以构成一个电容结构，第一场效应晶体管与第一方面提供的场效应晶体管结构相似，主要包括叠层结构、沟道层、栅氧化层和栅极。叠层结构可以包括沿叠层方向依次层叠设置的第一极、介质层和第二极，且叠层结构上开设有沟槽，沟槽的开口位于第二极的上表面，沟槽贯穿第二极和介质层。在该场效应晶体管中，沟道层可以覆盖沟槽的侧壁和底部，栅氧化层可以覆盖沟道层，栅极填充于栅氧化层所限定的区域且从沟槽溢出。其中，第一极可以为源极，第二极可以为漏极，或者，第一极可以为漏极，第二极可以为源极。为实现电容结构，场效应晶体管的第一极和第二极需要短接作为MOS电容的一个金属层，场效应晶体管的栅极可以作为MOS电容的另一个金属层，在栅极和源漏极之间形成电容电场。电容结构具体可以作为去耦电容结构，去耦电容结构为防止电源线电压下降或地线电压升高，需要连接在电源线和地线之间，场效应晶体管的源漏极作为MOS电容的一个金属层可以与电源线或地线中的一个连接，场效应晶体管的栅极作为MOS电容的另一个金属层可以与电源线或地线中的另一个连接。具体地，各第一场效应晶体管的源漏极可以与电源线连接，各第一场效应晶体管的栅极可以与地线连接；或者，反之亦可。
在一些可能的实施方式中，每行第一场效应晶体管中的每一个第一场效应晶体管可以等间距排布，每列第一场效应晶体管中的每一个第一场效应晶体管也可以等间距排布。
在一些可能的实施方式中，为了提高电容阵列的电路密度，可以将每行第一场效应晶体管中的每一个第一场效应晶体管的第一极与沿着行方向延伸的第一连接部连接，每行第一场效应晶体管中的每一个第一场效应晶体管的第二极与沿着行方向延伸的第二连接部连接，同一行第一场效应晶体管连接的第一连接部和第二连接部通过第一过孔连接，实现同一行第一场效应晶体管中每一个第一场效应晶体管的源漏极短接。第一场效应晶体管的行数可以第一过孔的个数相同。示例性地，每列第一场效应晶体管中的 每一个第一场效应晶体管的栅极还可以通过沿列方向延伸的第四连接部连接，以便与电源线或地线中的一个连接。
在一些可能的实施方式中，为了提高电容阵列的电路密度，位于第一层存储阵列内且呈阵列排布的多个第一场效应晶体管中的相邻第一场效应晶体管之间可以不需要间隔设置，即多个第一场效应晶体管的第一极可以一体设置，多个第一场效应晶体管的第二极可以一体设置，多个第一场效应晶体管的栅极可以一体设置。这里提到的一体设置指的是部件位于同一平面内且相互连通构成一个整体。示例性地，可以在一行第一场效应晶体管的边缘将一体设置的第一极和第二极通过一个第一过孔短接。
在一些可能的实施方式中，为了在同等电容阵列的电路密度情况下提高阵列的电容值，电容阵列还可以包括在位于第一层存储阵列内的多个第一场效应晶体管上，堆叠设置的位于第二层存储阵列内且呈阵列排布的多个第二场效应晶体管。每一个第二场效应晶体管的结构与每一个第一场效应晶体管的结构相同，在此不做赘述。每一个第二场效应晶体管可以单独构成一个电容结构，也可以将多个第一场效应晶体管中的每一个第一场效应晶体管与多个第二场效应晶体管中的每一个第二场效应晶体管一一对应设置，使一一对应设置的一个第一场效应晶体管与一个第二场效应晶体管堆叠设置且构成一个电容结构。其中，多个第二场效应晶体管中的每一个第二场效应晶体管的第一极和第二极相互连接，且与每一个第一场效应晶体管的栅极连接；多个第二场效应晶体管中的每一个第二场效应晶体管的栅极相互连接，且与每一个第一场效应晶体管的第一极和第二极相互连接。
在一些可能的实施方式中，每行第二场效应晶体管中的每一个第二场效应晶体管可以等间距排布，每列第二场效应晶体管中的每一个第二场效应晶体管也可以等间距排布。
在一些可能的实施方式中，为了提高电容阵列的电路密度，可以将每列第二场效应晶体管中的每一个第二场效应晶体管的第一极与沿着列方向延伸的第四连接部连接，每列第二场效应晶体管中的每一个第二场效应晶体管的第二极与沿着列方向延伸的第五连接部连接，同一列第二场效应晶体管连接的第四连接部和第五连接部通过第二过孔连接，实现同一列第二场效应晶体管中每一个第二场效应晶体管的源漏极短接，且每列第一场效应晶体管中的每一个第一场效应晶体管的栅极可以与对应的第二场效应晶体管的第一极接触设置，以便与电源线或地线中的一个连接。并且，每行第二场效应晶体管中的每一个第二场效应晶体管的栅极可以与沿着行方向延伸的第三连接部连接，并且同一行的第一连接部、第二连接部和第三连接部通过一个第一过孔连接，实现同一行第一场效应晶体管的第一极和第二极与第二场效应晶体管的栅极连接，以便与电源线或地线中的另一个连接。
在一些可能的实施方式中，为了提高电容阵列的电路密度，位于第二层存储阵列内且呈阵列排布的多个第二场效应晶体管中的相邻第二场效应晶体管之间可以不需要间隔设置，即多个第二场效应晶体管的第一极可以一体设置，多个第二场效应晶体管的第二极可以一体设置，多个第二场效应晶体管的栅极可以一体设置。这里提到的一体设置指的是部件位于同一平面内且相互连通构成一个整体。示例性地，在一行第一场效应晶体管的一侧边缘将一体设置的第一极和第二极和第二场效应晶体管一体设置的栅极通过一个第一过孔短接，可以在一行第二场效应晶体管的另一侧边缘将一体设置的第一极和第二极通过一个第二过孔短接，第一场效应晶体管的一体设置的栅极和第二场效应晶体管的一体设置的第一极可以接触设置。在本申请实施例中，不限定第一过孔和第二过孔的数量和设置位置，第一过孔和第二过孔可以设置在每行的边缘处，也可以设置在每列的边缘处，还可以第一过孔设置在每行的边缘处，第二过孔设置在每列的边缘处。
在一些可能的实施方式中，还可以堆叠更多层的场效应晶体管，使电容阵列可以具有交替排布的多层第一层存储阵列和多层第二层存储阵列，且在一个第二层存储阵列与其上的一个第一层存储阵列之间可以设置有绝缘层。交替排布的多层第一层存储阵列和多层第二层存储阵列可以共用第一过孔和第二过孔。
第三方面，本申请提供了一种存储器，可以包括多个存储单元阵列(memory array)以及与多个存储单元阵列中的每个存储单元阵列连接的存储控制器，多个存储单元阵列中可以有部分存储单元阵列作为冗余阵列(dummy array)，可以将冗余阵列设计为本申请实施例提供的上述电容阵列，这样可以提高存储器芯片的存储效率。并且，电容阵列连接的电源线和地线的线宽会宽于正常的存储单元阵列中的信号线的线宽。利用本申请实施例提供的上述电容阵列作为存储器的冗余阵列后，通过仿真可以得到55nm pitch 25nm CD和90nm pitch 40nm CD两种电容阵列的总电容值分别为7.99E-16C和3.52E-16C，且电容密度为200fF/μm2。
第四方面，本申请提供了一种电子设备，该电子设备包括处理器以及与处理器耦合的存储器，存储器可以是本申请第三方面提供的存储器。具体地，处理器可以调用存储器中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
上述第二方面和第四方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到的技术效果说明，这里不再重复赘述。
附图说明
图1为本申请实施例提供的电容结构的一种电路示意图；
图2a为本申请实施例提供的电容结构的一种剖面示意图；
图2b为本申请实施例提供的电容结构的另一种剖面示意图；
图3为本申请实施例提供的电容结构的一种三维结构示意图；
图4为本申请实施例提供的电容结构的另一种电路示意图；
图5a为本申请实施例提供的电容结构的另一种剖面示意图；
图5b为本申请实施例提供的电容结构的又一种剖面示意图；
图5c为本申请实施例提供的电容结构的又一种剖面示意图；
图6为本申请实施例提供的电容结构的另一种三维结构示意图；
图7为本申请实施例提供的电容阵列的一种电路示意图；
图8为本申请实施例提供的电容阵列的一种剖面示意图；
图9为本申请实施例提供的电容阵列的一种三维结构示意图；
图10为本申请实施例提供的电容阵列的另一种电路示意图；
图11为本申请实施例提供的电容阵列的另一种剖面示意图；
图12为本申请实施例提供的电容阵列中一个电容结构的三维结构示意图；
图13为本申请实施例提供的电容阵列的又一种电路示意图；
图14为本申请实施例提供的电容阵列的又一种剖面示意图；
图15为本申请实施例提供的存储器的结构示意图；
图16为本申请实施例提供的电子设备的结构示意图。
附图标记说明：
1-场效应晶体管，1a-第一场效应晶体管，1b-第二场效应晶体管，10-叠层结构，11-沟道层，12-栅氧化层，13-栅极，13a-第一场效应晶体管的栅极，13b-第二场效应晶体管的栅极，14-过孔，14a-第一过孔，14b-第二过孔，15-绝缘层，V-沟槽，Z-叠层方向，VPP-电源线，VBB-地线，01-第一极，01a-第一场效应晶体管的第一极，01b-第二场效应晶体管的第一极，02-介质层，03-第二极，03a-第一场效应晶体管的第二极，03b-第二场效应晶体管的第二极，21-第一连接部，22-第二连接部，23-第三连接部，24-第四连接部，25-第五连接部，100-存储器，200处理器。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
应注意的是，在本说明书中，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本申请的描述中，需要说明的是，术语“中”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本发明保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
为了方便理解本申请实施例提供的技术方案，下面首先介绍其应用场景。本申请实施例提供的DeCAP电路可以应用于DRAM等存储器中。在存储器的电源线与地线之间放置DeCAP电路，它可以在瞬态电流增大和电压下降时向电路补充电流，以防止电源线电压下降或地线电压升高。该存储器可用于手机、平板电脑、笔记本电脑、可穿戴设备、车载设备等电子设备中的数据存储。当然，本申请提供 的DeCAP电路和存储器也可以应用于其他电子设备中，在此不作限定。
当前的DeCAP电路可以分为采用金属-绝缘体-金属(metal-insulator-metal，MIM)电容的DeCAP电路、采用金属-氧化物-金属(metal-oxide-metal，MOM)电容的DeCAP电路，和采用金属氧化物半导体(metal oxide semiconductor，MOS)电容的DeCAP电路。其中，MIM电容由两个平行金属层形成，它们之间具有高k值的电介质。MOM电容与MIM电容类似，区别在于将高k值的电介质替换为氧化物，并且金属层与氧化物是交织在一起。MOS电容是将MOS晶体管的源漏极短接形成的，MOS晶体管的栅氧化层作为氧化物，短接的源漏极和栅极分别作为MOS电容的两个金属层。
目前，在基于1T1C的DRAM芯片中，采用基于MIM电容、MOM电容或MOS电容的DeCAP电路会占据存储芯片资源，增大面积开销，降低存储芯片的存储密度。而在基于2T0C的DRAM芯片中，芯片自身并没有电容用作DeCAP电路，需要设置DeCAP电路提高电源线电压的稳定性，但如果采用基于MIM电容或MOS电容的DeCAP电路，实现类似基于1T1C的DRAM芯片中的DeCAP电路工艺开销巨大，DeCAP电路会占据芯片资源，降低芯片的存储单元面积效率。因此，对于DRAM芯片亟需一种面积开销较小且密度较高的DeCAP电路。
本申请利用沟道层呈垂直分布的场效应晶体管实现DeCAP电路，可以降低DeCAP电路带来的面积开销。并利用沟道层呈垂直分布的场效应晶体管阵列排布，将其设置在存储器中可以增加DeCAP电路密度和存储芯片的存储密度。
下面结合附图来说明本申请技术方案中提供的电容结构、电容阵列、存储器及电子设备。
图1示意出了本申请实施例提供的电容结构的一种电路示意图，图2a示意出了本申请实施例提供的电容结构的一种剖面示意图，图2b示意出了本申请实施例提供的电容结构的另一种剖面示意图，图3示意出了本申请实施例提供的电容结构的一种三维结构示意图。
参照图1至图3，本申请实施例提供的电容结构，可以包括至少一个场效应晶体管1；至少一个场效应晶体管1主要包括叠层结构10、沟道层11、栅氧化层12和栅极13。叠层结构10可以包括沿叠层方向Z依次层叠设置的第一极01、介质层02和第二极03，其中，第一极01可以为源极，第二极03可以为漏极，或者，第一极01可以为漏极，第二极03可以为源极。叠层结构10上开设有沟槽V，沟槽V的开口位于第二极03的上表面，沟槽V贯穿第二极03和介质层02。参照图2a，沟槽V可以仅贯穿至第一极01的表面，使沟槽V的底部位于第一极01的表面，或者，参照图2b，沟槽V还可以进一步贯穿至第一极01的里面，使沟槽V的底部位于第一极01的内部。在场效应晶体管1中，沟道层11可以覆盖沟槽V的侧壁和底部，并且沟道层11不会填满沟槽V，使沟槽V内保留足够的空间以容纳栅氧化层12和栅极13。在场效应晶体管1中，栅氧化层12可以覆盖沟道层11且中间留有空间，即栅氧化层12不会填满沟槽V，使沟槽V内保留足够的空间以容纳栅极13，即栅氧化层12会限定出用于容纳栅极的区域。在场效应晶体管1中，栅极13填充于栅氧化层12所限定的区域且从沟槽V中溢出，延伸至叠层结构10的上方。为实现电容结构，场效应晶体管1的第一极01和第二极03需要短接作为MOS电容的一个金属层，场效应晶体管1的栅极13可以作为MOS电容的另一个金属层，在栅极13和源漏极之间形成电容电场。示例性地，第一极01和第二极03可以通过过孔14连接，过孔14具体可以是连接孔(connect via)或其他垂直互联结构。电容结构具体可以作为应用于存储芯片中的去耦电容结构，去耦电容结构为防止电源线电压下降或地线电压升高，需要连接在电源线和地线之间，场效应晶体管1的源漏极作为MOS电容的一个金属层可以与电源线或地线中的一个连接，场效应晶体管1的栅极13作为MOS电容的另一个金属层可以与电源线或地线中的另一个连接。具体地，场效应晶体管1的源漏极可以与电源线VPP连接，场效应晶体管1的栅极13可以与地线VBB连接；或者反之亦可。
在本申请实施例中，由于场效应晶体管1的沟道层11呈垂直分布，因此相比平面型的场效应晶体管可以减小水平投影面积。并且，由于形成电容结构的两个金属层呈垂直分布，因此相比平面型的电容结构可以减小水平投影面积，以降低电容的面积开销。并且，在不增加场效应晶体管水平投影面积的情况下，通过调节沟槽V的槽深(即在层叠方向Z的沟槽V长度)，可以调节电容结构的电容值。
参照图2b，在本申请一些实施例中，场效应晶体管1中的沟槽V可以没入部分第一极01，即沟槽V可以没入至第一极01的里面，这样可以增大沟道层11与第一极01的接触面积，从而增大电容结构的电容值。
参照图2b，在本申请一些实施例中，栅极13在延伸至叠层结构10的上方之外，栅极13还可以在 垂直于叠层方向Z的平面延伸，可以增大栅极13与第二极03的正对面积，从而可以增大电容结构的电容值。
参照图2b，在本申请一些实施例中，沟道层11和栅氧化层12均还可以延伸至叠层结构10的上方，且沟道层11和栅氧化层12均还可以在垂直于叠层方向Z的平面延伸，从而可以增加第二极03与沟道层11的接触面积，从而可以增大电容结构的电容值。
需要说明的是，在具体实施中，场效应晶体管1的第一极01和第二极03可以互换，不做具体区分。
示例性地，第一极01和第二极03可以采用例如TiN、Ti、Au、W、Mo、In-Ti-O(ITO)、Al、Cu、Ru、Ag等导电材料或者它们的任意组合形成，在此不作限定。
示例性地，栅极13可以采用金属等导电性材料形成，例如TiN、Ti、Au、W、Mo、ITO、Al、Cu、Ru、Ag等导电材料或者它们的任意组合。
示例性地，栅氧化层12可以采用SiO2、Al2O3、HfO2、ZrO2、TiO2、Y2O3、Si3N4等绝缘材料或者它们的任意组合材料、叠层结构以及组合材料的叠层结构形成，在此不作限定。
示例性地，沟道层11可以采用半导体材料形成，例如Si、多晶Si、非晶Si、In-Ga-Zn-O(IGZO)多元化合物、ZnO、ITO、TiO2、MoS2等半导体材料或者它们的任意组合。
示例性地，介质层02可以采用绝缘材料形成，例如SiO2、Si3N4、Al2O3等绝缘材料，在此不作限定。
图4示意出了本申请实施例提供的电容结构的另一种电路示意图，图5a示意出了本申请实施例提供的电容结构的另一种剖面示意图，图5b示意出了本申请实施例提供的电容结构的又一种剖面示意图，图5c示意出了本申请实施例提供的电容结构的又一种剖面示意图，图6示意出了本申请实施例提供的电容结构的另一种三维结构示意图。
在本申请一些实施例中，为了增大电容值，电容结构可以包括多个堆叠设置的场效应晶体管。示例性地，参照图4至图6，电容结构可以包括堆叠设置的第一场效应晶体管1a和第二场效应晶体管1b，示例性地，第二场效应晶体管1b可以堆叠于第一场效应晶体管1a之上。第一场效应晶体管1a和第二场效应晶体管1b堆叠设置可以减小电容结构的面积开销，并且，第一场效应晶体管1a和第二场效应晶体管1b可以并联设置，以增大电容值。具体地，第一场效应晶体管1a的第一极01a和第二极03a短接后可以与第二场效应晶体管1b的栅极13b连接，作为电容结构的一个金属层例如可以与电源线VPP连接。示例性地，第一场效应晶体管1a的第一极01a和第二极03a可以与第二场效应晶体管1b的栅极13b可以通过同一个第一过孔14a电连接，通过同一个第一过孔14a连接可以减小连接区域的面积开销。具体地，第二场效应晶体管1b的第一极01b和第二极03b短接后可以与第一场效应晶体管1a的栅极13a连接，作为电容结构的另一个金属层例如可以与地线VBB连接。示例性地，第二场效应晶体管1b的第一极01b和第二极03b可以通过第二过孔14b电连接，第一场效应晶体管1a的栅极13a与第二场效应晶体管1b的第一极01b可以堆叠设置，使两者相互接触，达到两者导通可以传递电信号的关系，区别于通过第一过孔14a和第二过孔14b导通的连接方式。其中，第一过孔14a和第二过孔14b位置不交叠，且可以设置在任何位置，在此不做限定。
参照图5a，在本申请一些实施例中，为了减小堆叠设置的多个场效应晶体管的水平投影面积，第一场效应晶体管1a的沟槽中心位置和第二场效应晶体管1b的沟槽中心位置相互重合。参照图5b，在本申请另一些实施例中，堆叠设置的多个场效应晶体管的沟槽中心位置也可以错开设置，在此不做限定。
在本申请一些实施例中，为了便于制作，场效应晶体管的沟槽水平截面形状可以为圆形或其他便于形成的形状，下述均以沟槽的水平截面形状为圆形为例进行说明。参照图5a，在本申请一些实施例中，为了减小堆叠设置的多个场效应晶体管的水平投影面积，第一场效应晶体管1a的沟槽孔径和第二场效应晶体管1b的沟槽孔径可以相互重合。参照图5c，在本申请另一些实施例中，堆叠设置的多个场效应晶体管的沟槽孔径也可以设置为不同，例如第一场效应晶体管1a的沟槽孔径可以大于且覆盖第二场效应晶体管1b的沟槽孔径。在此基础上，可以通过调节沟槽的槽深控制电容值。
相应地，本申请实施例还提供了一种电容阵列。图7示意出了本申请实施例提供的电容阵列的一种电路示意图，图8示意出了本申请实施例提供的电容阵列的一种剖面示意图，图9示意出了本申请实施例提供的电容阵列的一种三维结构示意图。参照图7至图9，本申请实施例提供的电容阵列，可以包括位于第一层存储阵列内且呈阵列排布的多个第一场效应晶体管1a，图7中示意出了位于第一层存储阵列中呈三行四列分布的12个第一场效应晶体管1a。其中，每一个第一场效应晶体管1a可以构成一个 电容结构，第一场效应晶体管1a与图2a所示的场效应晶体管结构相似，主要包括叠层结构10、沟道层11、栅氧化层12和栅极13。叠层结构10可以包括沿叠层方向Z依次层叠设置的第一极01、介质层02和第二极03，且叠层结构10上开设有沟槽，沟槽的开口位于第二极03的上表面，沟槽贯穿第二极03和介质层02。在该场效应晶体管1中，沟道层11可以覆盖沟槽V的侧壁和底部，栅氧化层12可以覆盖沟道层11，栅极13填充于栅氧化层12所限定的区域且从沟槽溢出。其中，第一极01可以为源极，第二极03可以为漏极，或者，第一极01可以为漏极，第二极03可以为源极。为实现电容结构，场效应晶体管1的第一极01和第二极03需要短接作为MOS电容的一个金属层，场效应晶体管1的栅极13可以作为MOS电容的另一个金属层，在栅极13和源漏极之间形成电容电场。电容结构具体可以作为去耦电容结构，去耦电容结构为防止电源线电压下降或地线电压升高，需要连接在电源线和地线之间，场效应晶体管1的源漏极作为MOS电容的一个金属层可以与电源线或地线中的一个连接，场效应晶体管1的栅极13作为MOS电容的另一个金属层可以与电源线或地线中的另一个连接。具体地，各第一场效应晶体管1a的源漏极可以与电源线VPP连接，各第一场效应晶体管1a的栅极13a可以与地线VBB连接；或者，反之亦可。
在本申请一些实施例中，每行第一场效应晶体管1a中的每一个第一场效应晶体管1a可以等间距排布，每列第一场效应晶体管1a中的每一个第一场效应晶体管1a也可以等间距排布。图8示意出了一行第一场效应晶体管1a中包括四个等间距排列的第一场效应晶体管1a的情况。
在本申请一些实施例中，为了提高电容阵列的电路密度，可以将每行第一场效应晶体管1a中的每一个第一场效应晶体管1a的第一极01a与沿着行方向延伸的第一连接部21连接，每行第一场效应晶体管1a中的每一个第一场效应晶体管1a的第二极03a与沿着行方向延伸的第二连接部22连接，同一行第一场效应晶体管1a连接的第一连接部21和第二连接部22通过第一过孔14a连接，实现同一行第一场效应晶体管1a中每一个第一场效应晶体管1a的源漏极短接。图9示意出了两行第一场效应晶体管1a且每行第一场效应晶体管1a包括两个第一场效应晶体管1a的情况，第一场效应晶体管1a的行数可以第一过孔14a的个数相同。示例性地，每列第一场效应晶体管1a中的每一个第一场效应晶体管1a的栅极13a还可以通过沿列方向延伸的第四连接部24连接，以便与电源线或地线中的一个连接。
在本申请另一些实施例中，为了提高电容阵列的电路密度，位于第一层存储阵列内且呈阵列排布的多个第一场效应晶体管1a中的相邻第一场效应晶体管1a之间可以不需要间隔设置，即多个第一场效应晶体管1a的第一极01a可以一体设置，多个第一场效应晶体管1a的第二极03a可以一体设置，多个第一场效应晶体管01的栅极13a可以一体设置。这里提到的一体设置指的是部件位于同一平面内且相互连通构成一个整体。例如参照图8，也可以认为图8中一行第一场效应晶体管1a的四个第一场效应晶体管1a的栅极13a一体设置，第一极01a一体设置，第二极03a一体设置，可以在一行第一场效应晶体管1a的边缘将一体设置的第一极01a和第二极03a通过一个第一过孔14a短接。
图10示意出了本申请实施例提供的电容阵列的另一种电路示意图，图11示意出了本申请实施例提供的电容阵列的另一种剖面示意图，图12示意出了本申请实施例提供的电容阵列中一个电容结构的三维结构示意图。
参照图10至图12，在本申请一些实施例中，为了在同等电容阵列的电路密度情况下提高阵列的电容值，电容阵列还可以包括在位于第一层存储阵列内的多个第一场效应晶体管1a上，堆叠设置的位于第二层存储阵列内且呈阵列排布的多个第二场效应晶体管1b，图10中示意出了位于第一层存储阵列中呈三行两列分布的6个第一场效应晶体管1a，以及位于第二层存储阵列中呈三行两列分布的6个第二场效应晶体管1b。每一个第二场效应晶体管1b的结构与每一个第一场效应晶体管1a的结构相同，在此不做赘述。每一个第二场效应晶体管1b可以单独构成一个电容结构，也可以将多个第一场效应晶体管1a中的每一个第一场效应晶体管1a与多个第二场效应晶体管1b中的每一个第二场效应晶体管1b一一对应设置，使一一对应设置的一个第一场效应晶体管1a与一个第二场效应晶体管1b堆叠设置且构成一个电容结构。其中，多个第二场效应晶体管1b中的每一个第二场效应晶体管1b的第一极01b和第二极03b相互连接，且与每一个第一场效应晶体管1a的栅极13a连接；多个第二场效应晶体管1b中的每一个第二场效应晶体管1b的栅极13b相互连接，且与每一个第一场效应晶体管1a的第一极01a和第二极03a相互连接。参照图11，一行四个第一场效应晶体管1a与堆叠在其上的一行四个第二场效应晶体管1b的情况，图11中构成了四个电容结构。
在本申请一些实施例中，每行第二场效应晶体管1b中的每一个第二场效应晶体管1b可以等间距排 布，每列第二场效应晶体管1b中的每一个第二场效应晶体管1b也可以等间距排布。图11示意出了一行第二场效应晶体管1b中包括四个等间距排列的第二场效应晶体管1b的情况。
在本申请一些实施例中，为了提高电容阵列的电路密度，可以将每列第二场效应晶体管1b中的每一个第二场效应晶体管1b的第一极01b与沿着列方向延伸的第四连接部24连接，每列第二场效应晶体管1b中的每一个第二场效应晶体管1b的第二极03b与沿着列方向延伸的第五连接部25连接，同一列第二场效应晶体管1b连接的第四连接部24和第五连接部25通过第二过孔14b连接，实现同一列第二场效应晶体管1b中每一个第二场效应晶体管1b的源漏极短接，且每列第一场效应晶体管1a中的每一个第一场效应晶体管1a的栅极13a可以与对应的第二场效应晶体管1b的第一极01b接触设置，以便与电源线或地线中的一个连接。并且，每行第二场效应晶体管1b中的每一个第二场效应晶体管1b的栅极13b可以与沿着行方向延伸的第三连接部23连接，并且同一行的第一连接部21、第二连接部22和第三连接部23通过一个第一过孔14a连接，实现同一行第一场效应晶体管1a的第一极01a和第二极03a与第二场效应晶体管1b的栅极连接，以便与电源线或地线中的另一个连接。
在本申请另一些实施例中，为了提高电容阵列的电路密度，位于第二层存储阵列内且呈阵列排布的多个第二场效应晶体管1b中的相邻第二场效应晶体管1b之间可以不需要间隔设置，即多个第二场效应晶体管1b的第一极01b可以一体设置，多个第二场效应晶体管1b的第二极03b可以一体设置，多个第二场效应晶体管1b的栅极13b可以一体设置。这里提到的一体设置指的是部件位于同一平面内且相互连通构成一个整体。例如参照图11，也可以认为图11中一行第一场效应晶体管1a的四个第一场效应晶体管1a的栅极13a一体设置，第一极01a一体设置，第二极03a一体设置，且一行第二场效应晶体管1b的四个第一场效应晶体管1b的栅极13b一体设置，第一极01b一体设置，第二极03b一体设置。在一行第一场效应晶体管1a的一侧边缘将一体设置的第一极01a和第二极03a和第二场效应晶体管一体设置的栅极13b通过一个第一过孔14a短接，可以在一行第二场效应晶体管1b的另一侧边缘将一体设置的第一极01b和第二极03b通过一个第二过孔14b短接，第一场效应晶体管1a的一体设置的栅极13a和第二场效应晶体管1b的一体设置的第一极01b可以接触设置。在本申请实施例中，不限定第一过孔14a和第二过孔14b的数量和设置位置，第一过孔14a和第二过孔14b可以设置在每行的边缘处，也可以设置在每列的边缘处，还可以第一过孔14a设置在每行的边缘处，第二过孔设置在每列的边缘处。
图13示意出了本申请实施例提供的电容阵列的又一种电路示意图，图14示意出了本申请实施例提供的电容阵列的又一种剖面示意图。
参照图13和图14，在本申请一些实施例中，还可以堆叠更多层的场效应晶体管，使电容阵列可以具有交替排布的多层第一层存储阵列和多层第二层存储阵列，且在一个第二层存储阵列与其上的一个第一层存储阵列之间可以设置有绝缘层15。交替排布的多层第一层存储阵列和多层第二层存储阵列可以共用第一过孔14a和第二过孔14b。图13和图14中示意出了两层第一层存储阵列和两层第二层存储阵列的情况。
相应地，本申请实施例还提供了一种存储器。图15示意出了本申请实施例提供的存储器的结构示意图。参照图15，本实施例提供的存储器可以包括多个存储单元阵列(memory array)以及与多个存储单元阵列中的每个存储单元阵列连接的存储控制器(图中未示出)，多个存储单元阵列中可以有部分存储单元阵列作为冗余阵列(dummy array)，可以将冗余阵列设计为本申请实施例提供的上述电容阵列，这样可以提高存储器芯片的存储效率。并且，电容阵列连接的电源线和地线的线宽会宽于正常的存储单元阵列中的信号线的线宽。利用本申请实施例提供的上述电容阵列作为存储器的冗余阵列后，通过仿真可以得到55nm pitch 25nm CD和90nm pitch 40nm CD两种电容阵列的总电容值分别为7.99E-16C和3.52E-16C，且电容密度为200fF/μm2。
相应地，本申请实施例还提供了一种电子设备。图16示意出了本申请实施例提供的电子设备的结构示意图。参照图16，该电子设备包括处理器200以及与处理器耦合的存储器100，存储器100可以是本申请上述实施例提供的任一种存储器。具体地，处理器200可以调用存储器100中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (16)

  1. 一种电容结构，其特征在于，包括：至少一个场效应晶体管；所述至少一个场效应晶体管包括：叠层结构、沟道层、栅氧化层和栅极；
    所述叠层结构包括依次层叠设置的第一极、介质层和第二极，所述叠层结构上开设有沟槽，所述沟槽的开口位于所述第二极的上表面，所述沟槽贯穿所述第二极和所述介质层；所述第一极为源极，所述第二极为漏极，或，所述第一极为漏极，所述第二极为源极；
    所述沟道层覆盖所述沟槽的侧壁和底部；
    所述栅氧化层覆盖所述沟道层；
    所述栅极填充于所述栅氧化层在所述沟槽中限定的区域且从所述沟槽中溢出；
    所述第一极和第二极通过过孔连接。
  2. 如权利要求1所述的电容结构，其特征在于，所述电容结构为去耦电容结构；
    所述第一极和所述第二极用于连接电源线或地线中的一个，所述栅极用于连接所述电源线或所述地线中的另一个。
  3. 如权利要求2所述的电容结构，其特征在于，所述至少一个场效应晶体管包括堆叠设置的第一场效应晶体管和第二场效应晶体管；
    所述第一场效应晶体管的第一极和第二极与所述第二场效应晶体管的栅极连接，且用于连接所述电源线；
    所述第二场效应晶体管的第一极和第二极与所述第一场效应晶体管的栅极连接，且用于连接所述地线。
  4. 如权利要求3所述的电容结构，其特征在于，所述第二场效应晶体管堆叠于所述第一场效应晶体管之上，所述过孔包括第一过孔和第二过孔；
    所述第一场效应晶体管的第一极和第二极与所述第二场效应晶体管的栅极通过所述第一过孔电连接；
    所述第二场效应晶体管的第一极和第二极通过所述第二过孔电连接，所述第一场效应晶体管的栅极与所述第二场效应晶体管的第一极接触。
  5. 如权利要求3或4所述的电容结构，其特征在于，所述第一场效应晶体管的沟槽中心位置和所述第二场效应晶体管的沟槽中心位置在水平方向的投影相互重合。
  6. 如权利要求5所述的电容结构，其特征在于，所述第一场效应晶体管的沟槽孔径和所述第二场效应晶体管的沟槽孔径在水平方向的投影相互重合。
  7. 一种电容阵列，其特征在于，包括：位于第一层存储阵列内且呈阵列排布的多个第一场效应晶体管；所述多个第一场效应晶体管中的每一个第一场效应晶体管包括：叠层结构、沟道层、栅极和栅氧化层；所述叠层结构包括依次层叠设置的第一极、介质层和第二极，所述叠层结构上开设有沟槽，所述沟槽的开口位于所述第二极的上表面，所述沟槽贯穿所述第二极和所述介质层；所述第一极为源极，所述第二极为漏极，或，所述第一极为漏极，所述第二极为源极；所述沟道层覆盖所述沟槽的侧壁和底部；所述栅氧化层覆盖所述沟道层且中间留有空间；所述栅极填充于所述栅氧化层所限定的区域且从所述沟槽中溢出。
  8. 如权利要求7所述的电容阵列，其特征在于，所述电容阵列为去耦电容阵列；
    每一个第一场效应晶体管的第一极和第二极相互连接，且用于连接电源线或地线中的一个；每一个第一场效应晶体管的栅极相互连接，用于连接所述电源线或所述地线中的另一个。
  9. 如权利要求8所述的电容阵列，其特征在于，还包括：在位于所述第一层存储阵列内的所述多个第一场效应晶体管上，堆叠设置的位于第二层存储阵列内且呈阵列排布的多个第二场效应晶体管；
    所述多个第二场效应晶体管中的每一个第二场效应晶体管的第一极和第二极相互连接，且与每一个所述第一场效应晶体管的栅极连接；所述多个第二场效应晶体管中的每一个第二场效应晶体管的栅极相互连接，且与每一个所述第一场效应晶体管的第一极和第二极相互连接；
    每一个所述第二场效应晶体管的结构与每一个所述第一场效应晶体管的结构相同。
  10. 如权利要求9所述的电容阵列，其特征在于，所述多个第一场效应晶体管中的每一个第一场效应晶体管与所述多个第二场效应晶体管中的每一个第二场效应晶体管一一对应设置。
  11. 如权利要求10所述的电容阵列，其特征在于，每行所述第一场效应晶体管中的每一个所述第一场效应晶体管等间距排布，每列所述第一场效应晶体管中的每一个所述第一场效应晶体管等间距排布。
  12. 如权利要求10或11所述的电容阵列，其特征在于，每行所述第一场效应晶体管中的每一个所述第一场效应晶体管的第一极与沿着行方向延伸的第一连接部连接，每行所述第一场效应晶体管中的每一个所述第一场效应晶体管的第二极与沿着行方向延伸的第二连接部连接，每列所述第一场效应晶体管中的每一个所述第一场效应晶体管的栅极与对应的所述第二场效应晶体管的第一极接触设置；
    每行所述第二场效应晶体管中的每一个所述第二场效应晶体管的栅极与沿着行方向延伸的第三连接部连接，每列所述第二场效应晶体管中的每一个所述第二场效应晶体管的第一极与沿着列方向延伸的第四连接部连接，每列所述第二场效应晶体管中的每一个所述第二场效应晶体管的第二极与沿着列方向延伸的第五连接部连接；
    同一行的所述第一连接部、所述第二连接部和所述第三连接部通过一个第一过孔连接，同一列的所述第四连接部和所述第五连接部通过一个第二过孔连接。
  13. 如权利要求9或10所述的电容阵列，其特征在于，所述多个第一场效应晶体管的第一极一体设置，所述多个第一场效应晶体管的第二极一体设置，所述多个第一场效应晶体管的栅极一体设置；
    所述多个第二场效应晶体管的栅极一体设置，所述多个第二场效应晶体管的第一极一体设置，所述多个第二场效应晶体管的第二极一体设置；
    所述多个第一场效应晶体管的一体设置的第一极和第二极与所述多个第二场效应晶体管的一体设置的栅极通过至少一个第一过孔连接，所述多个第一场效应晶体管的一体设置的栅极和所述多个第二场效应晶体管的一体设置的第一极接触设置，所述多个第二场效应晶体管的一体设置的第二极与第一极通过至少一个第二过孔连接。
  14. 如权利要求9-13任一项所述的电容阵列，其特征在于，具有交替排布的多层所述第一层存储阵列和多层所述第二层存储阵列，且在一个所述第二层存储阵列与其上的一个所述第一层存储阵列之间设置有绝缘层。
  15. 一种存储器，其特征在于，包括多个存储单元阵列以及与所述多个存储单元阵列中的每个存储单元阵列连接的存储控制器，所述多个存储单元阵列中的至少一个存储单元阵列为如权利要求7-14任一项所述的电容阵列。
  16. 一种电子设备，其特征在于，包括处理器和与所述处理器耦合的、如权利要求15所述的存储器。
PCT/CN2023/101624 2022-09-15 2023-06-21 一种电容结构、电容阵列、存储器及电子设备 WO2024055667A1 (zh)

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