WO2024055160A1 - 超声指纹装置和电子设备 - Google Patents

超声指纹装置和电子设备 Download PDF

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Publication number
WO2024055160A1
WO2024055160A1 PCT/CN2022/118481 CN2022118481W WO2024055160A1 WO 2024055160 A1 WO2024055160 A1 WO 2024055160A1 CN 2022118481 W CN2022118481 W CN 2022118481W WO 2024055160 A1 WO2024055160 A1 WO 2024055160A1
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WIPO (PCT)
Prior art keywords
ultrasonic fingerprint
traces
driving
layer
metal layer
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PCT/CN2022/118481
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English (en)
French (fr)
Inventor
杜灿鸿
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2022/118481 priority Critical patent/WO2024055160A1/zh
Priority to US18/455,509 priority patent/US20240087355A1/en
Publication of WO2024055160A1 publication Critical patent/WO2024055160A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/1365—Matching; Classification

Definitions

  • Embodiments of the present application relate to the field of fingerprint identification, and more specifically, to an ultrasonic fingerprint device and electronic equipment.
  • Ultrasonic fingerprint recognition can not only identify the surface morphology of fingerprints, but also identify signals from the dermal layer of the finger, thereby achieving natural 3D anti-counterfeiting. Compared with optical fingerprint recognition, ultrasonic fingerprint recognition has a higher impact on the cleanliness of the finger surface. Tolerance. Therefore, ultrasonic fingerprint recognition has gradually become a new generation of fingerprint recognition method.
  • Ultrasonic fingerprint devices usually include piezoelectric transducers and ultrasonic fingerprint chips. How to achieve integration between piezoelectric transducers and ultrasonic fingerprint chips has become a problem that needs to be solved.
  • Embodiments of the present application provide an ultrasonic fingerprint device and electronic equipment, which can realize integration between a piezoelectric transducer and an ultrasonic fingerprint chip.
  • an ultrasonic fingerprint device which is disposed under a display screen of an electronic device to realize under-screen ultrasonic fingerprint recognition.
  • the ultrasonic fingerprint device includes an ultrasonic fingerprint chip and a pressure sensor disposed above the ultrasonic fingerprint chip. electrical transducer;
  • the piezoelectric transducer includes a piezoelectric layer, an upper electrode located above the piezoelectric layer, and a lower electrode located below the piezoelectric layer;
  • the ultrasonic fingerprint chip is a CMOS chip.
  • the upper electrode is led from the upper surface of the piezoelectric layer to the surface of the CMOS chip and is connected to one end of a lead through a pad on the surface of the COMS chip.
  • the lead The other end is connected to the circuit board below the ultrasonic fingerprint chip to realize the electrical connection between the piezoelectric transducer and the circuit board.
  • the ultrasonic fingerprint device includes a CMOS chip and an ultrasonic transducer.
  • the base of the CMOS chip is a silicon base, so wiring can be realized.
  • the interconnection between the upper electrode and the lead can be realized on the ultrasonic fingerprint chip through the bonding process, that is, the upper electrode and one end of the lead are connected by using the pad on the surface of the ultrasonic fingerprint chip.
  • the other end of the lead is connected to the circuit board under the ultrasonic fingerprint chip, thereby realizing the interconnection between the upper electrode and the circuit board, which is easy to implement in terms of technology and has high reliability.
  • the ultrasonic fingerprint chip includes a substrate and a plurality of metal layers disposed in a first region of the substrate.
  • the substrate is a silicon substrate, and the lower electrode is located in a second region of the substrate.
  • the density of the silver paste material of the upper electrode is very low and cannot support the bonding process.
  • the upper electrode can be led out to the ultrasonic fingerprint through the driving traces. surface of the chip.
  • the bonding process can be implemented on the chip surface to connect the drive traces to the circuit board through leads. In this way, the interconnection between the upper electrode and the circuit board is achieved.
  • a passivation layer is provided above the top metal layer, and a first opening corresponding to the N driving traces is provided on the passivation layer, and the upper electrode is connected from the The upper surface of the piezoelectric layer extends into the first opening to connect the first connection areas of each of the N driving traces located in the first opening.
  • the electrical connection between the upper electrode and the N driving traces is achieved.
  • the first window includes N sub-windows corresponding to the N driving traces, and the first connection area of each driving trace is located in its corresponding sub-window.
  • the passivation layer is also provided with N second openings corresponding to the N driving traces, wherein each driving trace is located in its corresponding second opening.
  • the second connection area is connected to its corresponding lead through its corresponding pad.
  • the bonding process can be implemented on the substrate. Therefore, by setting the second window, the bonding process can be used to realize the connection between the driving traces and the leads, and the driving wires are connected through the leads. Make connections between the traces and the circuit board.
  • the piezoelectric layer extends above the plurality of metal layers, the N driving traces extend into the piezoelectric layer, and the Nth driving traces extend into the piezoelectric layer.
  • a connection area is adjacent to the piezoelectric layer.
  • the first connection area of the driving traces can be made close to the edge of the piezoelectric layer, that is, the piezoelectric layer and The distance between the first connection areas is minimal, making the structure of the ultrasonic fingerprint device more compact.
  • the size of the first opening is larger than the size of the first connection area of the N driving traces, and the upper electrode extends from the upper surface of the piezoelectric layer to the The first part of the first opening is to cover the first connection area of the N driving traces, and the second part of the first opening is located under the piezoelectric layer.
  • the upper electrode When the size of the first opening is larger than the size of the first connection area of the N driving traces, the upper electrode extends to the first part of the first opening to cover the first connection area of the driving traces located in the first part.
  • the second part of a window extends into the piezoelectric layer and is located below the piezoelectric layer, thereby improving the connection reliability between the upper electrode and the driving trace.
  • the size of the first part in the direction of the N driving traces is greater than or equal to 150um; and/or, the size of the second part in the direction of the N driving traces The size is greater than or equal to 20um.
  • the distance between other traces in the top metal layer adjacent to the N driving traces and the N driving traces is greater than or equal to 10um.
  • the voltage of the driving signal of the upper electrode is usually high, which is significantly higher than the working voltage of the circuit in the ultrasonic fingerprint chip, it is not only easy to cause interference to the circuit in the ultrasonic fingerprint chip, but also easily cause electrical breakdown damage to the ultrasonic fingerprint chip. Therefore, other traces on the top metal layer adjacent to the driving traces should be kept at a distance from the driving traces to avoid same-layer breakdown, ensure the safety of the ultrasonic fingerprint device, and avoid driving traces. Interference with other traces on the top metal layer.
  • the top metal layer has a shielding effect on the N driving traces, which can prevent the N driving traces from interfering with other traces on the top metal layer.
  • holes are dug in the area corresponding to the N driving traces on a first metal layer among the plurality of metal layers, and the first metal layer is a phase located below the top metal layer. adjacent metal layer.
  • the first metal layer is an adjacent metal layer located below the top metal layer, by digging holes in its corresponding area below the N driving traces, the N driving traces are added to the other traces of the first metal layer. The electrical gap between them increases the voltage resistance strength of the first metal layer and avoids interlayer breakdown between the top metal layer and the first metal layer.
  • holes are dug in a region corresponding to the N driving traces on the first metal layer and in a region extending greater than or equal to 12 ⁇ m along the region.
  • the electrical gap between the drive traces and other traces on the first metal layer is further increased, and the top metal layer is avoided to the greatest extent. Interlayer breakdown occurs between the layer and the first metal layer.
  • an area on a second metal layer among the plurality of metal layers corresponding to the N driving traces is grounded, and the second metal layer is an adjacent metal layer located below the first metal layer. layer.
  • the second metal layer is an adjacent metal layer located below the first metal layer, by grounding its corresponding area located below the driving traces, the second metal layer has a shielding effect on the N driving traces, which can avoid Other traces on the second metal layer interfere with traces on the third metal layer below them.
  • a region on the second metal layer corresponding to the N driving traces and a region extending greater than or equal to 12 ⁇ m along the region are grounded.
  • the shielding effect of the second metal layer on the driving traces is further enhanced and the second metal layer is minimized. Interference caused by other traces on the layer to traces on the third metal layer below it.
  • a bonding pad for grounding is provided on the top metal layer, and the bonding pad is disposed beside the second connection area of the N driving traces.
  • a grounded pad is provided next to the second connection area of the driving traces between the pad and the second connection area. With a certain distance, it can avoid the interference of the driving signal to other surrounding signals.
  • the distance between the lower electrode and the passivation layer around the lower electrode is greater than or equal to 100um; and/or other traces in the top metal layer adjacent to the lower electrode wire to ground.
  • the distance between the edge of the upper electrode and the edge of the piezoelectric layer is greater than or equal to 50um. This prevents the upper electrode from overflowing to the surface of the ultrasonic fingerprint chip and avoids the risk of breakdown.
  • N 1
  • the area of the first window close to the piezoelectric layer is larger than the area of the part far away from the piezoelectric layer.
  • the shape of the first window is a trapezoid, and the lower bottom of the trapezoid is closer to the piezoelectric layer than the upper bottom thereof.
  • the shape of the first window is L-shaped, and the L-shape consists of a first part parallel to the direction of the driving traces, and a second part perpendicular to the direction of the driving traces. It consists of two parts, and the second part is closer to the piezoelectric layer than the first part.
  • an electronic device including: a display screen; and, according to the ultrasonic fingerprint device described in the first aspect or any implementation of the first aspect, the ultrasonic fingerprint device is provided on the display screen Below, to achieve under-screen ultrasonic fingerprint recognition.
  • Figure 1 is an integration method between the piezoelectric transducer and the ultrasonic fingerprint chip in the ultrasonic fingerprint device.
  • FIG. 2 is a schematic block diagram of an ultrasonic fingerprint device according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a possible structure of the ultrasonic fingerprint device shown in FIG. 2 .
  • FIG. 4 is a schematic diagram of another possible structure of the ultrasonic fingerprint device shown in FIG. 2 .
  • FIG. 5 is a schematic top view of a possible structure of the ultrasonic fingerprint device shown in FIG. 4 .
  • FIG. 6 is a schematic top view of another possible structure of the ultrasonic fingerprint device shown in FIG. 4 .
  • FIG. 7 is an equivalent circuit diagram between the driving trace and the upper electrode when the oxide layer formed on the first connection region is not broken down.
  • FIG. 8 is an equivalent circuit diagram between the driving trace and the upper electrode when the oxide layer formed on the first connection region is broken down.
  • FIG. 9 is a schematic top view of a partial area of the ultrasonic fingerprint device shown in FIG. 4 .
  • Figure 10 is a cross-sectional view of area A in Figure 5 along a direction perpendicular to the edge of the piezoelectric transducer.
  • Figure 11 is a schematic diagram of the shape of the first window in an embodiment of the present application.
  • Figure 12 is a schematic diagram of the shape of the first window in another embodiment of the present application.
  • Figure 13 is a schematic illustration of some possible dimensions of the L-shape of Figure 12.
  • Figure 14 is a schematic block of an electronic device according to an embodiment of the present application.
  • the ultrasonic fingerprint device 1 includes an ultrasonic fingerprint chip 101 and a piezoelectric transducer 102.
  • the piezoelectric transducer 102 includes a piezoelectric layer 1021 and an upper electrode located above the piezoelectric layer 1021. 1022, and a lower electrode 1023 located below the piezoelectric layer 1021.
  • the piezoelectric layer 1021 is formed of a piezoelectric material such as PVDF or PVDF-TrFE.
  • the piezoelectric transducer 102 is also called an ultrasonic transducer, which is arranged on the ultrasonic fingerprint chip 101.
  • Passivation layer 1024 plays a protective role.
  • the ultrasonic fingerprint chip 101 is a thin film transistor (Thin Film Transistor, TFT).
  • the material of the upper electrode 1022 is usually metal or metal paste, such as silver paste (Ag).
  • the density of silver paste is very low and does not support the bonding process (or wire bonding process), and it needs to be led out through leads.
  • the circuit board (not shown in Figure 1) below the ultrasonic fingerprint chip 101, thereby realizing the interconnection between the upper electrode 1022 and the circuit board, so that the driving signal output by the circuit board can be transmitted to the voltage through the lead.
  • the electrical transducer 10 is used to excite the piezoelectric transducer 10 to generate ultrasonic signals for fingerprint recognition.
  • the signal from the upper electrode 120 can also be led out to the circuit board through the lead wire.
  • the ultrasonic fingerprint chip 101 shown in Figure 1 is a TFT.
  • the wiring on the surface of the TFT due to its process characteristics, the wiring density is low and cannot meet the requirements of the bonding process. Therefore, the upper electrode 1022 cannot be placed on the ultrasonic fingerprint chip.
  • the surface of 101 is connected to the circuit board through leads, and the upper electrode 1022 can only be led out through other processes.
  • the ultrasonic fingerprint chip 101 is provided with a TVS through hole 103, and the TVS through hole 103 is filled with conductive material. In this way, the upper electrode 1022 can be led out to the circuit board through the TVS through hole 103; or, The upper electrode 1022 can be led out to the circuit board using methods such as pressing.
  • embodiments of the present application propose an ultrasonic fingerprint device that can use a bonding process to extract the upper electrode on the surface of the ultrasonic fingerprint chip, so that the upper electrode and the circuit board below the ultrasonic fingerprint chip have higher connection reliability.
  • FIG. 2 shows a schematic structural diagram of an ultrasonic fingerprint device according to an embodiment of the present application.
  • the ultrasonic fingerprint device 2 includes a piezoelectric transducer 10 and an ultrasonic fingerprint chip 20 .
  • FIG 3 is a schematic diagram of a possible structure of the ultrasonic fingerprint device 2 shown in Figure 2.
  • the piezoelectric transducer 10 is disposed above the ultrasonic fingerprint chip 20.
  • the piezoelectric transducer 10 includes a piezoelectric transducer.
  • the ultrasonic fingerprint chip 20 may be, for example, a Complementary Metal-Oxide-Semiconductor Transistor (CMOS) chip.
  • CMOS Complementary Metal-Oxide-Semiconductor Transistor
  • the upper electrode 120 is led from the upper surface of the piezoelectric layer 110 to the surface of the CMOS chip 20 and passes through the surface of the COMS chip 20
  • the pad 241 is connected to one end of the lead 310, and the other end of the lead 310 is connected to the circuit board 30 below the ultrasonic fingerprint chip to achieve electrical connection between the piezoelectric transducer 10 and the circuit board 30.
  • the ultrasonic fingerprint chip 20 is an application specific integrated circuit (ASIC) for ultrasonic fingerprint recognition.
  • the embodiment of the present application adopts a CMOS chip.
  • the ultrasonic fingerprint chip 20 can output a driving signal and load it to the upper electrode 120 and the lower electrode 130 of the piezoelectric layer 110.
  • the piezoelectric layer 110 vibrates, thereby transmitting an ultrasonic signal to the finger above the display screen.
  • the ultrasonic signal is transmitted to the surface of the finger, and is emitted or scattered at the fingerprint valley and fingerprint ridge to return an ultrasonic detection signal.
  • the ultrasonic detection signal is transmitted to the piezoelectric layer 110.
  • Based on the inverse piezoelectric effect a potential difference is generated between the electrodes on both sides of the piezoelectric layer 110, and a corresponding electrical signal is obtained. By subsequently processing the electrical signal, the fingerprint information of the finger can be obtained.
  • the piezoelectric layer 110 may be made of piezoelectric materials such as PVDF or PVDF-TrFE. Since the ultrasonic fingerprint device 2 in the embodiment of the present application uses the CMOS chip 20 and the substrate 210 of the CMOS chip 20 is a silicon substrate, it can be implemented on the silicon substrate. Hitting the line. After the upper electrode 120 is led to the substrate 210, the interconnection between the upper electrode 120 and the leads 310 can be realized on the substrate 210 through a bonding process, that is, the upper electrode 120 and the leads 310 are connected by using the pads 241 on the surface of the ultrasonic fingerprint chip 20.
  • a bonding process that is, the upper electrode 120 and the leads 310 are connected by using the pads 241 on the surface of the ultrasonic fingerprint chip 20.
  • One end of the lead 310 is fixed and connected, and the other end of the lead 310 is connected to the circuit board 30 below the ultrasonic fingerprint chip 20, thereby realizing the interconnection between the upper electrode 120 and the circuit board 30, which is easy to implement in terms of technology and has high performance. reliability.
  • the ultrasonic fingerprint device 2 shown in FIG. 3 has the following problems: First, the upper electrode 120 needs leads, that is, it is necessary to realize an electrical connection between the upper electrode 120 and the circuit board 30 below the ultrasonic fingerprint chip 20 in order to transmit the driving signal. applied to the ultrasonic transducer 10; secondly, the driving signal of the upper electrode 120 usually requires a high voltage of tens of volts.
  • the driving signal of the upper electrode 120 is led to the surface of the ultrasonic fingerprint chip 20, due to the driving voltage of the upper electrode 120 Being significantly higher than the working voltage of the circuits in the ultrasonic fingerprint chip 20 , the driving signal of the upper electrode 120 can easily interfere with the circuits in the ultrasonic fingerprint chip 20 , and can easily cause electrical breakdown damage to the ultrasonic fingerprint chip 20 .
  • a driving trace 230 can be provided on the ultrasonic fingerprint chip 20, and the upper electrode 120 and the bonding pad 241 are connected through the driving trace 230.
  • the bonding pad 241 is also referred to as a binding pad. (bonding pad)241.
  • the ultrasonic fingerprint chip 20 includes a substrate 210 and a plurality of metal layers disposed in the first region 201 of the substrate 210 .
  • the substrate 210 is a silicon substrate, and the lower electrode 130 is located in the second region of the substrate 210 .
  • the upper electrode 120 is respectively connected to the N pads 241 through the N drive wires 230, and the N pads 241 respectively connect the N drive wires 230 to the corresponding leads 310.
  • the density of the silver paste material of the upper electrode 120 is very low and cannot support the bonding process.
  • the upper electrode can be connected to the upper electrode 120 through the driving traces 230. 120 is led to the surface of the ultrasonic fingerprint chip 20 .
  • a bonding process can be implemented on the chip surface to connect the driving traces 230 to the circuit board 30 through the leads 310 . In this way, the interconnection between the upper electrode 120 and the circuit board 30 is achieved.
  • a passivation layer 220 is provided above the top metal layer TM, and the passivation layer 220 plays a protective role.
  • the passivation layer 220 is provided with a first opening 221 corresponding to the N driving traces 230 , and the portion of each driving trace 230 located within the first opening 221 is the first connection area of the driving trace 230 231.
  • the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first opening 221 to connect the first connection areas 231 of each of the N driving wires 230 located in the first opening 221 .
  • the top metal layer TM of the ultrasonic fingerprint chip 20 includes N driving traces 230 for connecting the upper electrode 120.
  • the passivation layer 220 above the top metal layer TM is provided with a first opening 221.
  • the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 and its edge into the first window 221, and covers the first connection areas 231 of the N drive wires 230 located in the first window 221, thereby achieving the above Electrical connections between the electrode 120 and the N driving traces 230 .
  • the ultrasonic fingerprint device 2 in the embodiment of the present application can be arranged under the display screen of the electronic device to realize under-screen ultrasonic fingerprint recognition.
  • the ultrasonic fingerprint device 2 includes a piezoelectric transducer 10 and an ultrasonic fingerprint chip 20.
  • the piezoelectric transducer 10 is disposed above the ultrasonic fingerprint chip 20.
  • the piezoelectric transducer 10 includes a piezoelectric layer 110,
  • the upper electrode 120 is located above the piezoelectric layer 110
  • the lower electrode 130 is located below the piezoelectric layer 110 .
  • the ultrasonic fingerprint chip 20 includes a base 210 and a plurality of metal layers disposed in the first region 201 of the base 210.
  • the plurality of metal layers include a first metal layer M1, a second metal layer M2, and a third metal layer. M3, the fourth metal layer M4 and the top metal layer TM.
  • the ultrasonic fingerprint chip 20 also includes a protective layer 220 located above the plurality of metal layers, such as a passivation layer 220.
  • the passivation layer 220 is used for protection.
  • the lower electrode 130 is located above the second region 202 of the substrate 210 .
  • the top metal layer TM includes the driving traces 230 , that is, the driving traces 230 are formed on the top metal layer TM.
  • the top metal layer TM may also include other traces.
  • One end of the driving trace 230 is close to the piezoelectric layer 110 , and the other end is close to the edge of the ultrasonic fingerprint chip 20 .
  • the passivation layer 220 is provided with a first opening 221, and the upper electrode 120 covers the upper surface of the piezoelectric layer 110 and is filled in the first opening 221, so that the upper electrode 120 and the driving trace 230 are located in the first opening. 221 are in contact with each other within the first connection area 231 .
  • the upper electrode 120 is formed as a silver paste pad 121 on the first connection area 231 of the driving trace 230, thereby achieving direct interconnection between the top metal layer TM and the upper electrode 120.
  • the uncured silver paste has fluidity and can extend from the upper surface of the piezoelectric layer 110 along its edge into the first window 221 to simultaneously form the upper surface of the piezoelectric layer 110 and the first window 221 . 221, so that the upper electrode 120 is in contact with the portion of the driving trace 230 located in the first window 221.
  • the silver paste can span the three-dimensional structure of the piezoelectric layer 110, and through the first opening 221, the silver paste pad 121 can be formed on the first connection area 231 of the driving trace 230.
  • the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first opening 221, which means that the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first opening 221 and covers the first opening. Part or all of the space within window 221. Generally, in order to prevent the silver paste of the upper electrode 120 from overflowing from the first window 221, the silver paste only needs to cover part of the space in the first window 221, as long as the silver paste can contact the driving traces 230 without filling it. The entire first opening window is 221.
  • the first window 221 includes N sub-windows corresponding to N driving traces 230, and the first connection area 231 of each driving trace 230 is located in its corresponding sub-window.
  • the first window 221 may be a complete window, and the first connection areas 231 of the N driving traces 230 are all located in the first window 221.
  • the upper electrode 120 is formed from the upper surface of the piezoelectric layer 110.
  • the first connection area 231 extends into the first window 221 and connects the N driving traces in the first window 221 .
  • the first window 221 may include M sub-windows, where M is a positive integer less than or equal to N.
  • M is a positive integer less than or equal to N.
  • the first window 221 includes N sub-windows corresponding to N driving wires 230, and the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the N sub-windows to connect N respectively.
  • the driving traces 230 are located in the first connection areas 231 in respective corresponding sub-windows.
  • N driving traces are divided based on the number of independent signals.
  • a driving trace that transmits an independent signal is called a driving trace, and the N driving traces each transmit N independent signals.
  • the number of metal lines used to transmit its corresponding independent signal in each driving line can be one or multiple metal lines connected in parallel.
  • the passivation layer 220 is also provided with N second openings 222 corresponding to the N driving traces 230 , wherein each driving trace 230 is located within its corresponding second opening 222 .
  • the second connection area 232 is connected to its corresponding lead 310 through its corresponding pad 241 .
  • the second connection areas 232 of the N driving traces 230 are respectively connected to the corresponding N leads 310 through the N pads 241 . Since the base of the CMOS chip 20 is a silicon base, the bonding process can be implemented on the base 210. Therefore, by setting the second window 222, the bonding process can be used to realize the connection between the driving trace 230 and the lead 310, so that the bonding process can be realized through the lead 310. Connect the driving traces 230 to the circuit board 30 .
  • N first connection areas 231 of the N driving lines are connected through the silver paste of the upper electrode 120, and the N second connection areas 232 of the N driving lines need to be connected to each other through independent N bonding pads 241.
  • the corresponding N leads are connected respectively.
  • the number N of the driving traces 230 mentioned above may be a positive integer.
  • Two independent driving traces 230 are respectively used to transmit two independent signals; or a larger number of independent driving traces 230 can be made on the top metal layer TM.
  • FIG. 5 is a top view of a possible structure of the ultrasonic fingerprint device 2 shown in Figure 4.
  • the number of driving traces 230 included in the top metal layer TM is 1.
  • the passivation layer 220 is provided with a first opening 221 corresponding to the driving trace 230.
  • the upper electrode 120 extends from the upper surface of the piezoelectric layer 110 into the first opening 221 to connect the driving trace 230 on the first opening. First connection area 231 within window 221 .
  • FIG. 6 is a top view of another possible structure of the ultrasonic fingerprint device 2 shown in Figure 4.
  • the number of driving traces included in the top metal layer TM is 2, respectively.
  • the passivation layer 220 is provided with a sub-window 221A corresponding to the driving wiring 230A and a sub-window 221B corresponding to the driving wiring 230B.
  • the upper electrode 120 is formed from the piezoelectric layer.
  • the upper surface of 110 extends into the sub-window 221A and the sub-window 221B to respectively connect the portion of the driving wire 230A located in the sub-window 221A and the portion of the driving wire 230B located in the first window 221B.
  • the driving traces 230 are usually made of metals such as aluminum (Al).
  • Aluminum is highly chemically active and will form aluminum oxide (Al 2 O 3 ) in the air.
  • Al 2 O 3 aluminum oxide
  • the driving traces 230 are The aluminum in the first connection area 231 of the line 230 located in the first window 221 will be exposed to the air, and an aluminum oxide film will form on its surface.
  • Aluminum oxide is non-conductive, and this layer of aluminum oxide film will prevent the interaction between the silver paste and the aluminum. interconnection between them, resulting in poor contact between the upper electrode 120 and the driving trace 230 .
  • an anti-oxidation protective layer can be plated on the surface of the first connection area 231, or a high voltage can be applied to the driving trace 230 to breakdown the oxide layer with high voltage.
  • the coating process will greatly increase the cost
  • the equivalent circuit of the piezoelectric layer 110 is a capacitor, the capacitor is equivalent to an open circuit for DC voltage, and it is impossible to judge whether the oxide layer is by measuring the resistance. Breakdown can only be measured through AC signals, which is not accurate enough and cannot be judged intuitively.
  • the applied high voltage is applied to both ends of the oxide layer through the equivalent capacitance of the piezoelectric layer 110, resulting in the actual drop. The voltage across the oxide layer is much smaller than the externally applied voltage, which requires a higher voltage to breakdown the oxide layer, which is not conducive to the realization of mass production.
  • Figure 7 is an equivalent circuit diagram without breakdown of the oxide layer
  • Figure 8 is an equivalent circuit diagram after breakdown of the oxide layer.
  • bonding pad 241A connected to the driving trace 230A, and bonding pad 241B connected to the driving trace 230B are respectively connected to external voltages, for example, bonding pad 241A is connected to 5V, bonding pad 241B is connected to GND, or bonding Pad 241A is connected to GND, bonding pad 241B is connected to 5V.
  • the 5V here is just an example, other voltage values can also be used.
  • the oxide layer 2313 can be equivalent to the capacitor C1 and the capacitor C2 shown in Figure 7. In this way, a 5V voltage will be directly applied to both ends of the oxide layer 2313, thereby directly breaking down the oxide layer 2313. It is not blocked by the capacitance C1 and the capacitance C2 of the piezoelectric layer 110 . Detect the current of the external 5V voltage.
  • the current passing through the 5V voltage will increase significantly, so that it can be accurately determined whether the oxide layer 2313 is broken down.
  • the DC resistance R1 and R2 between the bonding pad 241A and the bonding pad 241B can be measured to directly judge the effect of the breakdown and the interconnection impedance, thereby accurately judging the breakdown.
  • the connection between the rear upper electrode 120 and the driving trace 230 can be measured to directly judge the effect of the breakdown and the interconnection impedance, thereby accurately judging the breakdown.
  • testing process only needs to use DC voltage for testing throughout the whole process, and does not require AC voltage to measure the capacitance. Moreover, the testing voltage is relatively much lower, and the interconnection resistance can be accurately measured and monitored without increasing the size of the ultrasonic fingerprint chip 20. It reduces costs, improves testing efficiency, and is conducive to mass production.
  • bonding pad 241A and bonding pad 241B can remain disconnected or short-circuited. That is, the second connection area 232 of the driving line 230A and the second connection area 232 of the driving line 230B can be disconnected or connected to each other. When connected, the driving line 230A and the driving line 230B are merged into One driver trace 230.
  • the top metal layer TM includes one driving trace
  • the positional relationship and size between the driving trace 230 and each metal sum will be described.
  • the piezoelectric layer 110 extends over multiple metal layers, the N driving traces 230 extend into the piezoelectric layer 110 , and the N driving traces 230 extend into the piezoelectric layer 110 .
  • a connection area 231 is adjacent to the piezoelectric layer 110 .
  • the first connection area 231 of the driving traces 230 can be made close to the edge of the piezoelectric layer 110, that is, , the distance between the piezoelectric layer 110 and the first connection area 231 is minimized, so that the structure of the ultrasonic fingerprint device 2 is more compact.
  • the size of the first opening 221 is greater than or equal to the size of the first connection area 231 of the N driving traces, and the upper electrode 120 extends from the upper surface of the piezoelectric layer to the first A first part 221a of the window 221 is used to cover the first connection areas 231 of the N driving traces 230, and a second part 221b of the first window 221 is located under the piezoelectric layer 110.
  • the upper electrode 120 extends to the first part 221a of the first opening 221 to cover the first connection of the driving trace 230 located in the first part 221a.
  • the second portion 221b of the first window 221 extends into the piezoelectric layer 110 and is located below the piezoelectric layer 110 , thereby improving the connection reliability between the upper electrode 120 and the driving trace 230 .
  • the size S of the first portion 221a in the direction along the driving trace 230 is greater than or equal to 150 um, for example.
  • the size g of the second portion 221b in the direction along the driving trace 230 is, for example, greater than or equal to 20 um.
  • the voltage of the driving signal of the upper electrode 120 is usually high, which is significantly higher than the working voltage of the circuits in the ultrasonic fingerprint chip 20 , it not only easily causes interference to the circuits in the ultrasonic fingerprint chip 20 , but also easily causes electrical breakdown of the ultrasonic fingerprint chip 20 of damage. Therefore, in one implementation, a distance should be maintained between other traces on the top metal layer TM that are adjacent to the N driving traces 230 and the N driving traces 230 .
  • the distance between other adjacent traces of the driving trace 230 and the driving trace 230 is greater than or equal to 10um, thereby avoiding the occurrence of same-layer breakdown, ensuring the safety of the ultrasonic fingerprint device 2, and avoiding the pairing of the driving trace 230.
  • Other traces on the top metal layer TM create interference.
  • FIG. 9 is a schematic top view of a partial area of the ultrasonic fingerprint device 2 shown in FIG. 4 .
  • FIG. 9 only shows one driving trace.
  • the distance between any of the metal layers described and the driving traces 230 refers to the distance between the metal layer and the silver paste pad 121.
  • the silver paste pad 121 is rectangular and has a size of 240um ⁇ 200um as an example.
  • the size of the first connection area 231 of the driving trace 230 in the Y direction can be considered as the corresponding size of the silver paste pad 121.
  • the size of the driving trace 230 in the Y direction is 200um as shown by the dotted line in Figure 9, marked
  • the distance between each metal layer and the driving trace 230 is the distance between it and the dotted line shown, that is, the distance between it and the edge of the silver paste pad 121.
  • top metal layer TM has a shielding effect on the N driving traces 230, which can prevent the N driving traces 230 from interfering with other traces on the top metal layer TM.
  • Figure 9 only shows other traces of the top metal layer TM located on the right side of the driving trace 230, and other traces adjacent to the driving trace 230 on the top metal layer TM are grounded.
  • the portions (not shown) of the top metal layer TM located on the upper and left sides of the driving traces 230 are also grounded.
  • holes are dug in the first metal layer M1 among the multiple metal layers in an area corresponding to the N driving traces 230 .
  • the first metal layer M1 is located on the top metal layer.
  • the first metal layer M1 is an adjacent metal layer located below the top metal layer TM, by digging holes in its corresponding area below the N driving traces 230, N driving traces 230 and the first metal layer M1 are added. electrical gaps between other traces, thereby increasing the voltage resistance strength of the first metal layer M1 and preventing interlayer breakdown between the top metal layer TM and the first metal layer M1.
  • the area corresponding to the driving trace 230 on the second metal layer M2 among the multiple metal layers is grounded, and the second metal layer M2 is located on the first metal layer M1 adjacent metal layer below.
  • the second metal layer M2 is an adjacent metal layer located under the first metal layer M1, by grounding its corresponding area located under the N driving traces 230, the second metal layer M2 generates a disturbance to the driving traces 230.
  • the shielding function can prevent other traces of the second metal layer M2 from interfering with the traces of the third metal layer M3 located below it. In this way, the routing of the third metal layer M3 and the fourth metal layer M4 can be freely selected.
  • the area on the second metal layer M2 corresponding to the N driving traces 230 and the area extending around the area by greater than or equal to 12 ⁇ m are grounded.
  • the second metal layer M2 is located below the driving trace 230 and is grounded in an area formed by a distance a extending to all sides, so as to reduce the impact of other traces on the second metal layer M2 on the third layer below it.
  • the traces on the three metal layers M3 cause interference.
  • the lower electrode 130 is an electrode array composed of multiple electrodes, and each electrode in the electrode array corresponds to a pixel in the fingerprint image. Therefore, the electrode array below the piezoelectric layer 110 can be regarded as a pixel array.
  • the top metal layer TM is provided with a grounding
  • the pad is GND pad 242, and GND pad 242 is located next to the second connection area 232 of the N drive traces 230.
  • a GND pad 242 is provided next to the bonding pad 241 of the N driving traces 230. There is a certain distance between the GND pad 242 and the bonding pad 241, which can avoid the interference of the driving signals transmitted on the driving traces 230 to other surrounding signals. .
  • FIG. 10 is a cross-sectional view of area A in FIG. 5 along a direction perpendicular to the edge of the piezoelectric transducer 10 .
  • the distance e between the lower electrode 130 and the passivation layer 220 around the lower electrode 130 is greater than or equal to 100um.
  • other traces on the top metal layer TM adjacent to the lower electrode 130 are grounded.
  • the distance c1 between the edge of the upper electrode 120 and the edge of the piezoelectric layer 110 is greater than or equal to 50um. This prevents the upper electrode 120 from overflowing to the surface of the ultrasonic fingerprint chip 20 and avoids the risk of breakdown.
  • the edge of the passivation layer 220 exceeds the edge distance c2 of the piezoelectric layer 110 , c2 is, for example, greater than or equal to 20 ⁇ m; and/or the edge of the substrate 210 exceeds the edge c3 of the passivation layer 220 , c2 is, for example, Greater than or equal to 10um.
  • N 1
  • the area of the first window 221 close to the piezoelectric layer 110 is larger than the area of the part far away from the piezoelectric layer 110, thereby improving the distance between the upper electrode 120 and the driving traces. connection reliability.
  • Figures 11 to 13 illustrate the shape and size of the first window 221 in some implementations of the present application.
  • the shape of the first window 221 is a trapezoid, in which the lower bottom of the trapezoid is closer to the piezoelectric layer 110 than the upper bottom thereof; for another example, as shown in FIGS. 12 and 13 , the first window 221 is trapezoidal in shape.
  • the shape of a window 221 is L-shaped.
  • the L-shape is composed of a first part 2311 parallel to the direction of the driving traces 230 and a second part 2312 perpendicular to the direction of the driving traces 230.
  • the second part 2312 is compared with The first portion 2311 is closer to the piezoelectric layer 110 .
  • Figure 13 shows some possible sizes of the L-shaped first opening 221 in Figure 12.
  • the size of the part of the L-shape close to the piezoelectric layer 110 in the Y direction is larger than the size of the part of the L-shape away from the piezoelectric layer 110.
  • the size in the Y direction is used to improve the connection reliability between the upper electrode 120 and the first connection area 231 of the driving trace 230 without occupying additional area.
  • L1, L2 and L3 respectively represent the edge of the piezoelectric layer 110, the edge of the insulating protective layer (over coating) on the surface of the upper electrode 120, and the edge (die edge) of the ultrasonic fingerprint chip 20.
  • the silver paste pad 121 fills part of the L-shaped first window 221 and covers the first connection area 231 of the driving trace 230.
  • this application also provides an electronic device 3.
  • the electronic device 3 includes a display screen 4; and the above-mentioned ultrasonic fingerprint device 2.
  • the ultrasonic fingerprint chip 20 and the display screen 4 are bonded through an adhesive film 301 so that the ultrasonic fingerprint device 2 is located below the display screen 4, thereby realizing under-screen ultrasonic fingerprint recognition.
  • the electronic device in the embodiment of the present application may be a portable or mobile computing device such as a terminal device, a mobile phone, a tablet computer, a notebook computer, a desktop computer, a gaming device, a vehicle-mounted electronic device or a wearable smart device, and Electronic databases, cars, bank automated teller machines (Automated Teller Machine, ATM) and other electronic equipment.
  • the wearable smart devices include devices that are full-featured, large in size, and can realize complete or partial functions without relying on smartphones, such as smart watches or smart glasses, as well as devices that only focus on a certain type of application function and require integration with other devices such as smartphones.
  • Equipment used in conjunction with it such as various smart bracelets, smart jewelry and other equipment for physical sign monitoring.
  • the systems, devices and methods disclosed in the embodiments of this application can be implemented in other ways. For example, some features of the method embodiments described above may be omitted or not performed.
  • the device embodiments described above are only illustrative, and the division of units is only a logical function division. In actual implementation, there may be other divisions, and multiple units or components may be combined or integrated into another system.
  • the coupling between units or the coupling between components may be direct coupling or indirect coupling, and the above-mentioned coupling includes electrical, mechanical or other forms of connection.

Abstract

一种超声指纹装置（1）和电子设备，超声指纹装置（1）设置在电子设备的显示屏下方，以实现屏下超声指纹识别，超声指纹装置（1）包括超声指纹芯片（20）以及设置在超声指纹芯片（20）上方的压电换能器（10）；压电换能器（10）包括压电层（110）、位于压电层（110）上方的上电极（120）、以及位于压电层（110）下方的下电极（130）；超声指纹芯片（20）为CMOS芯片，上电极（120）引出至CMOS芯片的表面，并通过COMS芯片表面的焊盘（241）与引线（310）的一端连接，引线（310）的另一端连接至超声指纹芯片（20）下方的电路板（30），以实现压电换能器（10）与电路板（30）之间的电连接。

Description

超声指纹装置和电子设备 技术领域
本申请实施例涉及指纹识别领域，并且更具体地，涉及一种超声指纹装置和电子设备。
背景技术
随着社会进步，手机已成为现代生活必不可少的电子设备之一。目前市场上的手机都具有一种或多种身份认证方式，包括数字密码、手势图形、面部识别、指纹识别等。其中，指纹识别由于其应用方便、识别速度快和稳定可靠等特点，已经成为大多数手机的标配。指纹识别也发展出不同的技术路线，包括电容指纹识别、光学指纹识别和超声指纹识别等。
超声指纹识别不仅可以识别指纹的表层形貌，还可以识别到手指真皮层的信号，从而实现天然的3D防伪，并且相比于光学指纹识别，超声指纹识别对手指表面的洁净状态具有更高的容忍度。因此，超声指纹识别逐渐成为新一代的指纹识别方式。超声指纹装置通常包括压电换能器和超声指纹芯片，如何实现压电换能器和超声指纹芯片之间的集成，成为需要解决的问题。
发明内容
本申请实施例提供一种超声指纹装置和电子设备，能够实现压电换能器和超声指纹芯片之间的集成。
第一方面，提供了一种超声指纹装置，设置在电子设备的显示屏下方，以实现屏下超声指纹识别，所述超声指纹装置包括超声指纹芯片、以及设置在所述超声指纹芯片上方的压电换能器；
所述压电换能器包括压电层、位于所述压电层上方的上电极、以及位于所述压电层下方的下电极；
所述超声指纹芯片为CMOS芯片，所述上电极从所述压电层的上表面引出至所述CMOS芯片的表面，并通过所述COMS芯片表面的焊盘与引线的一端连接，所述引线的另一端连接至所述超声指纹芯片下方的电路板，以实现压电换能器与所述电路板之间的电连接。
本申请实施例中，超声指纹装置包括CMOS芯片和超声换能器，CMOS 芯片的基底为硅基底，因此能够实现打线。在将上电极引出至超声指纹芯片表面后，能够通过bonding工艺，在超声指纹芯片上实现上电极与引线之间的互连，即利用超声指纹芯片表面的焊盘将上电极与引线的一端之间固定和连接，引线的另一端连接至超声指纹芯片下方的电路板，从而实现上电极与电路板之间的互连，工艺上易于实现，且具有较高的可靠性。
在一种实现方式中，所述超声指纹芯片包括基底、以及设置在所述基底的第一区域的多个金属层，所述基底为硅基底，所述下电极位于所述基底的第二区域的上方，所述多个金属层中的顶层金属层包括N个驱动走线，N＝1或者N为大于1的正整数，所述上电极通过所述N个驱动走线分别连接至N个焊盘，所述N个焊盘分别将所述N个驱动走线与各自对应的引线相连。
一方面，上电极的银浆材料的致密度很低，不能支持bonding工艺，而该实施例中，通过在超声指纹芯片上设置驱动走线，便可以通过驱动走线将上电极引出至超声指纹芯片的表面。另一方面，由于采用CMOS芯片，便可以在芯片表面实现bonding工艺，以通过引线将驱动走线与电路板之间进行连接。这样，就实现了上电极与电路板之间的互连。
在一种实现方式中，所述顶层金属层的上方设置有钝化层，所述钝化层上设置有与所述N个驱动走线对应的第一开窗，所述上电极从所述压电层的上表面延伸至所述第一开窗内，以连接所述N个驱动走线各自的位于所述第一开窗内的第一连接区域。从而实现上电极与N个驱动走线之间的电连接。
在一种实现方式中，所述第一开窗包括与所述N个驱动走线对应的N个子开窗，每个驱动走线的所述第一连接区域位于其对应的子开窗内。
在一种实现方式中，所述钝化层上还设置有与所述N个驱动走线对应的N个第二开窗，其中每个驱动走线位于其对应的所述第二开窗内的第二连接区域，通过其对应的焊盘与其对应的引线连接。
该实施例中，由于CMOS芯片的基底为硅基底，能够在基底上实现bonding工艺，因此通过设置第二开窗，便可以利用bonding工艺实现驱动走线和引线之间的连接，通过引线将驱动走线与电路板之间进行连接。
在一种实现方式中，所述压电层延伸至所述多个金属层的上方，所述N个驱动走线延伸至所述压电层内，所述N个驱动走线的所述第一连接区域与所述压电层相邻。
当压电层延伸至多个金属层的上方，且驱动走线延伸至压电层内时，能 够使驱动走线的第一连接区域紧靠在压电层的边缘，即，使压电层与第一连接区域之间的距离最小，使超声指纹装置的结构更加紧凑。
在一种实现方式中，所述第一开窗的尺寸大于所述N个驱动走线的所述第一连接区域的尺寸，所述上电极从所述压电层的上表面延伸至所述第一开窗的第一部分，以覆盖所述N个驱动走线的所述第一连接区域，所述第一开窗的第二部分位于所述压电层的下方。
当第一开窗的尺寸大于N个驱动走线的第一连接区域的尺寸时，上电极延伸至第一开窗的第一部分，以覆盖驱动走线位于第一部分内的第一连接区域，第一开窗的第二部分延伸至压电层内并位于压电层下方，从而提高上电极与驱动走线之间的连接可靠性。
在一种实现方式中，所述第一部分在所述N个驱动走线的方向上的尺寸大于或等于150um；和/或，所述第二部分在所述N个驱动走线的方向上的尺寸大于或等于20um。
在一种实现方式中，所述顶层金属层中与所述N个驱动走线相邻的其他走线，与所述N个驱动走线之间的距离大于或等于10um。
由于上电极的驱动信号的电压通常较高，显著高于超声指纹芯片内线路的工作电压，不仅容易对超声指纹芯片内的线路产生干扰，还容易导致超声指纹芯片产生电击穿的损伤。因此，顶层金属层上与驱动走线相邻的其他走线，与驱动走线之间应保持一段距离，能够避免发生同层击穿，保证超声指纹装置的安全性，同时能够避免驱动走线对顶层金属层上的其他走线产生干扰。
在一种实现方式中，所述顶层金属层上与所述N个驱动走线相邻的其他走线接地。从而使顶层金属层产生对N个驱动走线的屏蔽作用，能够避免N个驱动走线对顶层金属层上的其他走线产生干扰。
在一种实现方式中，所述多个金属层中的第一金属层上与所述N个驱动走线对应的区域挖孔，所述第一金属层是位于所述顶层金属层下方的相邻金属层。
由于第一金属层是位于顶层金属层下方的相邻金属层，通过在其位于N个驱动走线下方的对应区域挖孔，增加了N个驱动走线与第一金属层的其他走线之间的电器间隙，从而增大了第一金属层的耐压强度，避免顶层金属层与第一金属层之间发生层间击穿。
在一种实现方式中，所述第一金属层上与所述N个驱动走线对应的区域、以及沿所述区域向四周延伸大于或等于12um的区域挖孔。
通过将挖孔区域从与N个驱动走线对应的区域向四周延伸一定距离，更进一步增加了驱动走线与第一金属层的其他走线之间的电器间隙，最大限度地避免了顶层金属层与第一金属层之间发生层间击穿。
在一种实现方式中，所述多个金属层中的第二金属层上与所述N个驱动走线对应的区域接地，所述第二金属层是位于第一金属层下方的相邻金属层。
由于第二金属层是位于第一金属层下方的相邻金属层，通过将其位于驱动走线下方的对应区域接地，使第二金属层产生了对N个驱动走线的屏蔽作用，能够避免第二金属层上的其他走线对位于其下方的第三金属层上的走线产生干扰。
在一种实现方式中，所述第二金属层上与所述N个驱动走线对应的区域、以及沿所述区域向四周延伸大于或等于12um的区域接地。
通过将第二金属层上的接地区域从与N个驱动走线对应的区域向四周延伸一定距离，更进一步增强了第二金属层对驱动走线的屏蔽作用，最大限度地降低了第二金属层的其他走线对位于其下方的第三金属层上的走线产生的干扰。
在一种实现方式中，所述顶层金属层上设置有用于接地的焊盘，所述焊盘设置在所述N个驱动走线的所述第二连接区域的旁侧。
为了避免驱动走线的高压对超声指纹芯片中的金属层造成电击穿以及干扰，在驱动走线的第二连接区域的旁侧设置接地的焊盘，该焊盘与第二连接区域之间具有一定的距离，能够避免驱动信号对周围其他信号的干扰。
在一种实现方式中，所述下电极与所述下电极周围的钝化层之间的距离大于或等于100um；和/或，所述顶层金属层中与所述下电极相邻的其他走线接地。
下电极和下电极周围的钝化层之间具有一定间距，和/或顶层金属层上与下电极相邻的其他走线接地，能够起到屏蔽作用，避免外部干扰影响下电极的阵列中靠近边缘的像素，同时减少边缘像素的边缘效应，提高边缘效应与中心像素之间的一致性。
在一种实现方式中，所述上电极的边缘与所述压电层的边缘之间的距离 大于或等于50um。从而防止上电极外溢至超声指纹芯片的表面，避免产生击穿风险。
在一种实现方式中，N＝1，所述第一开窗在其靠近所述压电层的部分的面积，大于其远离所述压电层的部分的面积。从而提高上电极与驱动走线之间的连接可靠性。
在一种实现方式中，所述第一开窗的形状为梯形，所述梯形的下底相比于其上底更靠近所述压电层。
在一种实现方式中，所述第一开窗的形状为L形，所述L形由平行于所述驱动走线的方向的第一部分、以及垂直于所述驱动走线的方向的第二部分组成，所述第二部分相比于所述第一部分更靠近所述压电层。
第二方面，提供了一种电子设备，包括：显示屏；以及，根据第一方面或第一方面的任一实现方式中所述的超声指纹装置，所述超声指纹装置设置在所述显示屏下方，以实现屏下超声指纹识别。
附图说明
图1是超声指纹装置中压电换能器和超声指纹芯片之间的一种集成方式。
图2是本申请实施例的超声指纹装置的示意性框图。
图3是图2所示的超声指纹装置的一种可能的结构的示意图。
图4是图2所示的超声指纹装置的另一种可能的结构的示意图。
图5是图4所示的超声指纹装置的一种可能的结构的俯视示意图。
图6是图4所示的超声指纹装置的另一种可能的结构的俯视示意图。
图7是第一连接区域上形成的氧化层未被击穿时驱动走线和上电极之间的等效电路图。
图8是第一连接区域上形成的氧化层被击穿时驱动走线和上电极之间的等效电路图。
图9是图4所示的超声指纹装置的局部区域的俯视示意图。
图10是图5中区域A沿垂直于压电换能器边缘方向的剖视图。
图11是本申请一实施例中的第一开窗的形状的示意图。
图12是本申请另一实施例中的第一开窗的形状的示意图。
图13是图12中的L形的一些可能的尺寸的示意图。
图14是本申请实施例的电子设备的示意性框。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
图1示出了传统的超声指纹装置1，超声指纹装置1包括超声指纹芯片101和压电换能器102，压电换成器102包括压电层1021、位于压电层1021上方的上电极1022、以及位于压电层1021下方的下电极1023。压电层1021由压电材料例如PVDF或者PVDF-TrFE等形成。压电换能器102也称为超声换能器，其设置在超声指纹芯片101上放。钝化层1024起保护作用。超声指纹芯片101为薄膜晶体管(Thin Film Transistor，TFT)。
上电极1022的材质通常为金属或者金属混浆，例如银浆(Ag)，银浆的致密度很低，不支持绑定(bonding)工艺(或者称打线工艺)，需要通过引线将其引出，并连接至超声指纹芯片101下方的电路板(图1中未示出)，从而实现上电极1022与电路板之间的互连，这样，电路板输出的驱动信号能够通过该引线传输至压电换能器10，以激励压电换能器10产生超声波信号用于指纹识别。此外，还可以通过该引线将上电极120的信号引出至电路板。
图1所示的超声指纹芯片101为TFT，而对于TFT表面的走线，由于其工艺特点决定了走线的致密度较低，不能满足bonding工艺的要求，因此上电极1022无法在超声指纹芯片101的表面上通过引线连接至电路板，只能通过其他工艺来将上电极1022引出。例如，如图1所示，超声指纹芯片101上设置有TVS通孔103，TVS通孔103内填充有导电材料，这样，通过TVS通孔103可以将上电极1022引出至电路板；或者，还可以采用压合等方式将将上电极1022引出至电路板。
若想要在TFT表面进行bonding工艺，以利用TFT表面的bonding pad实现上电极1022和引线之间的连接，则需要对TFT进行一些特殊处理，比如在TFT表面镀金等，否则会引起可靠性不足等问题，易出现老化和脱开等现象。但镀金等方式又增加了超声指纹装置1的工艺复杂度和成本。
为此，本申请实施例提出一种超声指纹装置，能够在超声指纹芯片的表面采用bonding工艺实现上电极的引出，使上电极与超声指纹芯片下方的电路板之间具有较高的连接可靠性。
图2示出了本申请实施例的超声指纹装置的示意性结构图。如图2所示， 超声指纹装置2包括压电换能器10和超声指纹芯片20。
图3为图2所示的超声指纹装置2的一种可能的结构的示意图，如图3所示，压电换能器10设置在超声指纹芯片20的上方，压电换能器10包括压电层110、位于压电层110上方的上电极120、以及位于压电层110下方的下电极130。
超声指纹芯片20例如可以是互补金属氧化物半导体(Complementary Metal-Oxide-Semiconductor Transistor，CMOS)芯片，上电极120从压电层110的上表面引出至CMOS芯片20的表面，并通过COMS芯片20表面的焊盘241与引线310的一端连接，引线310的另一端连接至超声指纹芯片下方的电路板30，以实现压电换能器10与电路板30之间的电连接。
超声指纹芯片20是用于超声指纹识别的专用集成电路(Application Specific Integrated Circuit，ASIC)，本申请实施例采用CMOS芯片。超声指纹芯片20可以输出驱动信号并加载至压电层110的上电极120和下电极130，在该驱动信号的作用下，基于压电效应，压电层110产生振动，从而向显示屏上方的手指发射超声信号，该超声信号传输至该手指的表面，在指纹谷和指纹脊处发生发射或散射而返回超声检测信号。超声检测信号传输至压电层110，基于逆压电效应，压电层110两侧的电极之间产生电势差，得到相应的电信号，通过后续对该电信号进行处理，可以获得该手指的指纹信息。
压电层110例如可以是PVDF或者PVDF-TrFE等压电材料形成，由于本申请实施例的超声指纹装置2中采用了CMOS芯片20，CMOS芯片20的基底210为硅基底，硅基底上能够实现打线。在将上电极120引出至基底210后，能够通过bonding工艺，在基底210上实现上电极120与引线310之间的互连，即利用超声指纹芯片20表面的焊盘241将上电极120与引线310的一端之间固定和连接，引线310的另一端连接至超声指纹芯片20下方的电路板30，从而实现上电极120与电路板30之间的互连，工艺上易于实现，且具有较高的可靠性。
但是，图3所示的超声指纹装置2存在以下问题：首先，上电极120需要引线，即，需要实现上电极120与超声指纹芯片20下方的电路板30之间的电连接，以便将驱动信号施加至超声换能器10；其次，上电极的120的驱动信号通常需要数十伏的高电压，若将上电极120的驱动信号引出至超声指 纹芯片20的表面，由于上电极120的驱动电压显著高于超声指纹芯片20中的线路的工作电压，上电极120的驱动信号容易对超声指纹芯片20内的线路产生干扰，还容易导致超声指纹芯片20产生电击穿的损伤。
为此，在一种实现方式中，可以在超声指纹芯片20上设置驱动走线230，通过驱动走线230连接上电极120与焊盘241，以下，也将焊盘241称为绑定焊盘(bonding pad)241。例如，一并参见图4至图6，超声指纹芯片20包括基底210、以及设置在基底210的第一区域201的多个金属层，基底210为硅基底，下电极130位于基底210的第二区域202的上方，多个金属层中的顶层金属层TM包括N个驱动走线，其中N＝1或者N为大于1的正整数。上电极120通过N个驱动走线230分别连接至N个焊盘241，N个焊盘241分别将N个驱动走线230与各自对应的引线310相连。
一方面，上电极120的银浆材料的致密度很低，不能支持bonding工艺，而在该实施例中，通过在超声指纹芯片上设置驱动走线230，便可以通过驱动走线230将上电极120引出至超声指纹芯片20的表面。另一方面，由于采用CMOS芯片，便可以在芯片表面实现bonding工艺，以通过引线310将驱动走线230与电路板30之间进行连接。这样，就实现了上电极120与电路板30之间的互连。
在一种实现方式中，如图4至图6所示，顶层金属层TM上方设置有钝化层220，钝化层220起保护作用。钝化层220上设置有与N个驱动走线230对应的第一开窗221，每个驱动走线230各自的位于第一开窗221内的部分为该驱动走线230的第一连接区域231。上电极120从压电层110的上表面延伸至第一开窗221内，以连接N个驱动走线230各自的位于该第一开窗221内的第一连接区域231。
该实施例中，超声指纹芯片20的顶层金属层TM包括用于连接上电极120的N个驱动走线230，顶层金属层TM上方的钝化层220上设置有第一开窗221，上电极120从压电层110的上表面及其边沿，延伸进入该第一开窗221内，并覆盖N个驱动走线230各自的位于第一开窗221内的第一连接区域231，从而实现上电极120与N个驱动走线230之间的电连接。
以下，作为示例，结合图4至图13对本申请实施例的超声指纹装置2进行详细描述。本申请实施例中的超声指纹装置2可以设置在电子设备的显示屏下方，以实现屏下超声指纹识别。
如图4所示，超声指纹装置2包括压电换能器10和超声指纹芯片20，压电换能器10设置在超声指纹芯片20的上方，压电换能器10包括压电层110、位于压电层110上方的上电极120、以及位于压电层110下方的下电极130。超声指纹芯片20包括基底210、以及设置在基底210的第一区域201的多个金属层，图4中是以多个金属层包括第一金属层M1、第二金属层M2、第三金属层M3、第四金属层M4和顶层金属层TM作为示例，超声指纹芯片20还包括位于多个金属层上方的保护层220，例如钝化层220，钝化层220用于起保护作用。下电极130位于基底210的第二区域202的上方。
其中，顶层金属层TM包括驱动走线230，也即，在顶层金属层TM上制作驱动走线230。此外，顶层金属层TM还可以包括其他走线。驱动走线230的一端靠近压电层110，另一端靠近超声指纹芯片20的边缘。钝化层220上设置有第一开窗221，上电极120覆盖在压电层110的上表面并填充在第一开窗221内，从而使上电极120与驱动走线230位于第一开窗221内的第一连接区域231之间接触。
以上电极120采用银浆材料为例，上电极120在驱动走线230的第一连接区域231上形成为银浆pad 121，从而实现顶层金属层TM和上电极120之间的直接互连。具体地，未固化前的银浆具有流动性，能够从压电层110的上表面沿其边沿延伸至第一开窗221内，以同时形成在压电层110的上表面和第一开窗221内，从而使上电极120与驱动走线230位于第一开窗221内的部分接触。银浆可以跨越压电层110的立体结构，通过第一开窗221，便可以在驱动走线230的第一连接区域231上形成银浆pad 121。
应理解，上电极120从压电层110的上表面延伸至第一开窗221内，是指上电极120从压电层110的上表面延伸至第一开窗221内，并覆盖第一开窗221内的部分或者全部空间。通常，为了避免上电极120的银浆从第一开窗221内溢出，银浆覆盖第一开窗221内的部分空间即可，只要银浆能够与驱动走线230接触即可，而无需填满整个第一开窗221。
在一种实现方式中，第一开窗221包括与N个驱动走线230对应的N个子开窗，每个驱动走线230的第一连接区域231位于其对应的子开窗内。
也就是说，第一开窗221可以是一个整的开窗，N个驱动走线230的第一连接区域231均位于该第一开窗221内，上电极120从压电层110的上表面延伸至第一开窗221内，并连接第一开窗221内N个驱动走线的第一连接 区域231。
或者，第一开窗221可以包括M个子开窗，M为小于或等于N的正整数。例如，M＝N时，第一开窗221包括与N个驱动走线230对应的N个子开窗，上电极120从压电层110的上表面延伸至N个子开窗内，以分别连接N个驱动走线230位于各自对应的子开窗内的第一连接区域231。
应理解，N个驱动走线是基于独立信号的数量进行划分的，传输一个独立信号的驱动走线称为一个驱动走线，N个驱动走线分别传输N个独立信号。但是每个驱动走线中用于传输其对应的独立信号的金属线的数量可以是1个也可以是并联的多个金属线。
在一种实现方式中，钝化层220上还设置有与N个驱动走线230对应的N个第二开窗222，其中每个驱动走线230位于其对应的第二开窗222内的第二连接区域232，通过其对应的焊盘241与其对应的引线310连接。
该实施例中，在N个第二开窗222内，N个驱动走线230的第二连接区域232分别通过N个焊盘241与对应的N个引线310连接。由于CMOS芯片20的基底为硅基底，能够在基底210上实现bonding工艺，因此通过设置第二开窗222，便可以利用bonding工艺实现驱动走线230和引线310之间的连接，从而通过引线310将驱动走线230与电路板30之间进行连接。
应当注意的是，N个驱动走线的N第一连接区域231通过上电极120的银浆连接，N个驱动走线的N个第二连接区域232需要分别通过独立的N个bonding pad 241与相应的N个引线分别连接。
本申请实施例中，上述的驱动走线230的数量N可以是正整数，例如，N＝1表示仅在顶层金属层TM上制作一个驱动走线；或者N＝2表示在顶层金属层TM上制作两个独立的驱动走线230，分别用于传输两路独立的信号；或者可以在顶层金属层TM上制作更多数量的独立的驱动走线230。
举例来说，N＝1，如图5所示，图5为图4所示的超声指纹装置2的一种可能的结构的俯视图，顶层金属层TM包括的驱动走线230的数量为1，钝化层220上设置有与驱动走线230对应的第一开窗221，上电极120从压电层110的上表面，延伸进入第一开窗221内，以连接驱动走线230位于第一开窗221内的第一连接区域231。
又例如，N＝2，如图6所示，图6为图4所示的超声指纹装置2的另一种可能的结构的俯视图，顶层金属层TM包括的驱动走线的数量为2，分别 为驱动走线230A和驱动走线230B，钝化层220上设置有与驱动走线230A对应的子开窗221A、以及与驱动走线230B对应的子开窗221B，上电极120从压电层110的上表面，延伸进入子开窗221A和子开窗221B内，以分别连接驱动走线230A位于子开窗221A内的部分、以及连接驱动走线230B位于第一开窗221B内的部分。
驱动走线230的材质通常为铝(Al)等金属，铝的化学活泼性很高，在空气中会形成氧化铝(Al 2O 3)，当在钝化层220上开窗之后，驱动走线230位于第一开窗221内的第一连接区域231的铝会暴露在空气中，其表面会形成氧化铝薄膜，氧化铝是不导电的，这层氧化铝薄膜会阻止银浆和铝之间的互连，导致上电极120和驱动走线230之间接触不良。为了消除第一连接区域231上的氧化层的影响，可以在第一连接区域231的表面镀抗氧化的保护层，或者向驱动走线230施加高电压以利用高压击穿氧化层。但是，对于前者，镀膜工序会极大地增加成本，而对于后者，由于压电层110的等效电路是一电容器，电容器对于直流电压来说相当于开路，无法通过测量电阻来判断氧化层是否已击穿，只能通过交流信号来测量，准确性不够且无法直观判断，另外，所施加的高压是隔着压电层110的等效电容再施加到氧化层的两端，导致实际上落在氧化层两端的电压要比外部施加的电压小很多，这就需要更高的电压来击穿氧化层，不利于量产的实现。
而对于图6所示的驱动走线230的数量为2的情况，其能够明显改善对氧化层击穿的效率，同时可以准确检测击穿后的直流电阻。下面结合图7和图8进行具体说明。图7是氧化层未被击穿的等效电路图，图8是氧化层击穿后的等效电路图。
如图7所示，与驱动走线230A连接的bonding pad 241A，以及与驱动走线230B连接的bonding pad 241B分别连接至外部电压，例如，bonding pad 241A连接5V，bonding pad 241B连接GND，或者bonding pad 241A连接GND，bonding pad 241B连接5V。这里的5V仅为示例，也可以采用其他电压值。
假设驱动走线230A在子开窗221A内的部分与上电极120的银浆pad 121A之间存在氧化层，驱动走线230B在子开窗221B内的部分与上电极120的银浆pad 121B之间存在氧化层2313，氧化层2313可以等效为图7所示的电容C1和电容C2，这样，5V电压将会直接施加在该氧化层2313的两端， 从而直接将氧化层2313击穿，不会被压电层110的电容C1和电容C2所隔断。检测外部的5V电压的电流，当氧化层2313被击穿时，通过5V电压的电流会显著增大，从而能够准确地判断氧化层2313是否被击穿。当判断氧化层2313被击穿时，如图8所示，可以测量bonding pad 241A和bonding pad 241B之间的直流电阻R1和R2，直接判断击穿的效果和互联阻抗，从而准确地判断击穿后上电极120与驱动走线230之间的连接情况。
上述的测试过程，全程只需要用直流电压进行测试，不需要交流电压测量电容，而且测试的电压相对要低得多，能够准确测量和监控互连电阻，不会增加超声指纹芯片20的尺寸，降低了成本，提升了测试效率，有利于量产。
应理解，在测试之后，应用于实际产品时，bonding pad 241A和bonding pad 241B之间可以继续保持断开，也可以进行短接。也即，驱动走线230A的第二连接区域232和驱动走线230B的第二连接区域232之间可以断开，也可以彼此相连，其中相连时，驱动走线230A和驱动走线230B合并为一个驱动走线230。
图7和图8是以顶层金属层TM具有两个驱动走线，即N＝2为例，当N为其他数值时，需要两两一组分别测试。例如N＝3时，可以先对第一个驱动走线和第二个驱动走线进行测试，其中一个接地，另一个加电压；然后再对第二个驱动走线和第三个驱动走线进行测试，其中一个接地，另一个加电压。
以下，为了简洁，以N＝1为例，即顶层金属层TM包括1个驱动走线为例，对驱动走线230和各个金属和之间的位置关系及其尺寸进行描述。
在一种实现方式中，如图4至图6所示，压电层110延伸至多个金属层的上方，N个驱动走线230延伸至压电层110内，N个驱动走线230的第一连接区域231与压电层110相邻。当压电层110延伸至多个金属层的上方，且驱动走线230延伸至压电层110内时，能够使驱动走线230的第一连接区域231紧靠在压电层110的边缘，即，使压电层110与第一连接区域231之间的距离最小，使超声指纹装置2的结构更加紧凑。
在一种实现方式中，如图4所示，第一开窗221的尺寸大于或者等于N个驱动走线的第一连接区域231的尺寸，上电极120从压电层的上表面延伸至第一开窗221的第一部分221a，以覆盖N个驱动走线230的第一连接区域231，该第一开窗221的第二部分221b位于压电层110下方。
可见，当第一开窗221的尺寸大于第一连接区域231的尺寸时，上电极120延伸至第一开窗221的第一部分221a，以覆盖驱动走线230位于第一部分221a内的第一连接区域231，第一开窗221的第二部分221b延伸至压电层110内并位于压电层110下方，从而提高了上电极120与驱动走线230之间的连接可靠性。
在一种实现方式中，第一部分221a在沿驱动走线230的方向即X方向上的尺寸S例如大于或等于150um，图4中是以第一开窗221的尺寸S＝240um作为示例。第二部分221b在沿驱动走线230的方向上的尺寸g例如大于或等于20um。
由于上电极120的驱动信号的电压通常较高，显著高于超声指纹芯片20内线路的工作电压，不仅容易对超声指纹芯片20内的线路产生干扰，还容易导致超声指纹芯片20产生电击穿的损伤。因此，在一种实现方式中，顶层金属层TM上与N个驱动走线230相邻的其他走线，与N个驱动走线230之间应保持一段距离，例如，顶层金属层TM上与驱动走线230相邻的其他走线，与驱动走线230之间的距离大于或等于10um，从而避免发生同层击穿，保证超声指纹装置2的安全性，同时能够避免驱动走线230对顶层金属层TM上的其他走线产生干扰。
图9为图4所示的超声指纹装置2的局部区域的俯视的示意图，图9作为示例，仅示出了1个驱动走线，顶层金属层TM上其他走线与该驱动走线230之间的距离f＝10um。
本申请实施例中，由于驱动走线230与银浆pad 121之间电连接，因此所描述的任一金属层与驱动走线230之间的距离，是指该金属层与银浆pad 121的边缘之间的距离。图9中以银浆pad 121为矩形且尺寸为240um×200um作为示例。驱动走线230的第一连接区域231在Y方向上的尺寸可以认为是银浆pad 121对应的尺寸，驱动走线230在Y方向上的尺寸为图9中的虚线所示的200um，所标识出的各金属层与驱动走线230之间的距离，指其与所示虚线之间的距离，即与银浆pad 121的边缘之间的距离。
在一种实现方式中，顶层金属层TM上与N个驱动走线230相邻的其他走线接地。从而使顶层金属层TM产生对N个驱动走线230的屏蔽作用，能够避免N个驱动走线230对顶层金属层TM上的其他走线产生干扰。例如，如图9所示，图9仅示出了顶层金属层TM位于驱动走线230右侧部分的其 他走线，顶层金属层TM上与驱动走线230相邻的其他走线接地。类似的，顶层金属层TM位于驱动走线230上侧和左侧的部分(未示出)也接地。
在一种实现方式中，如图4至图9所示，多个金属层中的第一金属层M1上与N个驱动走线230对应的区域挖孔，第一金属层M1是位于顶层金属层TM下方的相邻金属层。
由于第一金属层M1是位于顶层金属层TM下方的相邻金属层，通过在其位于N个驱动走线230下方的对应区域挖孔，增加了N个驱动走线230与第一金属层M1的其他走线之间的电器间隙，从而增大了第一金属层M1的耐压强度，避免顶层金属层TM与第一金属层M1之间发生层间击穿。
为了进一步增加了驱动走线230与第一金属层M1的其他走线之间的电器间隙，最大限度地避免顶层金属层TM与第一金属层M1之间发生层间击穿，在一种实现方式中，如图4至图9所示，第一金属层M1上与N个驱动走线230对应的区域、以及沿区域向四周延伸大于或等于a＝12um的区域挖孔。也就是说，将挖孔区域从与N个驱动走线230对应的区域向四周延伸一定距离a。
在一种实现方式中，如图4至图9所示，多个金属层中的第二金属层M2上与驱动走线230对应的区域接地，第二金属层M2是位于第一金属层M1下方的相邻金属层。
由于第二金属层M2是位于第一金属层M1下方的相邻金属层，通过将其位于N个驱动走线230下方的对应区域接地，使第二金属层M2产生了对驱动走线230的屏蔽作用，能够避免第二金属层M2的其他走线对位于其下方的第三金属层M3的走线产生干扰。这样，第三金属层M3和第四金属层M4的走线可以自由选择。
为了更进一步增强第二金属层M2对驱动走线230的屏蔽作用，最大限度地降低第二金属层M2的其他走线对位于其下方的第三金属层M3的走线产生的干扰，在一种实现方式中，第二金属层M2上与N个驱动走线230对应的区域、以及沿区域向四周延伸大于或等于12um的区域接地。例如，如图4至图9所示，第二金属层M2位于驱动走线230下方且向四周延伸距离a形成的区域接地，以减少第二金属层M2上的其他走线对其下方的第三金属层M3上的走线产生干扰。
通常，下电极130是由多个电极组成的电极阵列，电极阵列中的每个电 极对应指纹图像中的一个像素，因此压电层110下方的电极阵列可以看作是像素阵列。
为了避免驱动走线230的高压对超声指纹芯片20中的金属层造成电击穿以及干扰，在一种实现方式中，如图4至图6所示，顶层金属层TM上设置有用于接地的焊盘即GND pad 242，GND pad 242位于N个驱动走线230的第二连接区域232的旁侧。在N个驱动走线230的bonding pad 241的旁侧设置GND pad 242，GND pad 242与bonding pad 241之间具有一定的距离，能够避免驱动走线230上传输的驱动信号对周围其他信号的干扰。
图10是图5中的区域A沿垂直于压电换能器10边缘方向的剖视图。在一种实现方式中，如图10所示，下电极130与下电极130周围的钝化层220之间的距离e大于或等于100um。在另一种实现方式中，如图10所示，顶层金属层TM上与下电极130相邻的其他走线接地。
下电极130和下电极130周围的钝化层220之间具有一定间距，和/或顶层金属层TM上与下电极130相邻的其他走线接地，能够起到屏蔽作用，避免外部干扰影响下电极130的阵列中靠近边缘的像素。
同时，如图10所示，对于左侧边缘的像素，由于预留距离e做钝化层220开窗，边缘像素的左侧也存在金属线路，左侧的金属线路与其右侧电极之间平衡，仿佛这些边缘像素也像中心像素一般，从而减少了边缘像素的边缘效应，提高了边缘像素与中心像素之间的一致性。
在一种实现方式中，如图10所示，上电极120的边缘与压电层110的边缘之间的距离c1大于或等于50um。从而防止上电极120外溢至超声指纹芯片20的表面，避免产生击穿风险。
此外，如图10所示，钝化层220的边缘超出压电层110的边缘距离c2，c2例如大于或等于20um；和/或，基底210的边缘超出钝化层220的边缘c3，c2例如大于或等于10um。
在一种实现方式中，N＝1，第一开窗221在其靠近压电层110的部分的面积，大于其远离压电层110的部分的面积，从而提高上电极120与驱动走线之间的连接可靠性。
例如，图11至图13示出了本申请一些实现方式中的第一开窗221的形状和尺寸。例如，如图11所示，第一开窗221的形状为梯形，其中该梯形的下底相比于其上底更靠近压电层110；又例如，如图12和图13所示，第 一开窗221的形状为L形，该L形由平行于驱动走线230的方向的第一部分2311、以及垂直于驱动走线230的方向的第二部分2312组成，第二部分2312相比于第一部分2311更靠近压电层110。
图13示出了图12中的L形的第一开窗221的一些可能的尺寸，L形靠近压电层110的部分在Y方向上的尺寸，大于L形远离压电层110的部分在Y方向上的尺寸，以提高上电极120与驱动走线230的第一连接区域231之间的连接可靠性，且不占用额外的面积。其中，L1、L2和L3分别表示压电层110的边缘、上电极120表面的绝缘保护层(over coating)的边缘、以及超声指纹芯片20的边缘(die edge)。银浆pad 121填充在L形的第一开窗221内的部分区域，并覆盖驱动走线230的第一连接区域231，其中，图13仅作为示例，k1为银浆pad 121的尺寸，k1＝204um，L形的尺寸分别为：k2＝100um，k3＝404um，k4＝20um，k5＝244.5um，k6＝100um，k7＝215um，k8＝100um，k9根据k7来确定，这里可以为1000um。
应理解，图4至图13中未进行具体说明的各种参数，其范围可以认为是所示数值±50％。
如图14所示，本申请还提供了一种电子设备3，电子设备3包括显示屏4；以及上述的超声指纹装置2。超声指纹芯片20与显示屏4之间通过胶膜301粘接，以使超声指纹装置2位于显示屏4的下方，从而实现屏下超声指纹识别。
作为示例而非限定，本申请实施例中的电子设备可以为终端设备、手机、平板电脑、笔记本电脑、台式机电脑、游戏设备、车载电子设备或穿戴式智能设备等便携式或移动计算设备，以及电子数据库、汽车、银行自动柜员机(Automated Teller Machine，ATM)等其他电子设备。该穿戴式智能设备包括功能全、尺寸大、可不依赖智能手机实现完整或部分功能的设备，例如智能手表或智能眼镜等，以及包括只专注于某一类应用功能并且需要和其它设备如智能手机配合使用的设备，例如各类进行体征监测的智能手环、智能首饰等设备。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
本申请实施例中所揭露的系统、装置和方法，可以通过其它的方式实现。 例如，以上所描述的方法实施例的一些特征可以忽略或者不执行。以上所描述的装置实施例仅仅是示意性的，单元的划分仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，多个单元或组件可以结合或者可以集成到另一个系统。另外，各单元之间的耦合或各个组件之间的耦合可以是直接耦合，也可以是间接耦合，上述耦合包括电的、机械的或其它形式的连接。
本领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的装置和设备的具体工作过程以及产生的技术效果，可以参考前述方法实施例中对应的过程和技术效果，在此不再赘述。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围，本领域技术人员可以在上述实施例的基础上进行各种改进和变形，而这些改进或者变形均落在本申请的保护范围内。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种超声指纹装置，其特征在于，设置在电子设备的显示屏下方，以实现屏下超声指纹识别，所述超声指纹装置包括超声指纹芯片、以及设置在所述超声指纹芯片上方的压电换能器；
    所述压电换能器包括压电层、位于所述压电层上方的上电极、以及位于所述压电层下方的下电极；
    所述超声指纹芯片为互补金属氧化物半导体CMOS芯片，所述上电极从所述压电层的上表面引出至所述CMOS芯片的表面，并通过所述COMS芯片表面的焊盘与引线的一端连接，所述引线的另一端连接至所述超声指纹芯片下方的电路板，以实现压电换能器与所述电路板之间的电连接。
  2. 根据权利要求1所述的超声指纹装置，其特征在于，所述超声指纹芯片包括基底、以及设置在所述基底的第一区域的多个金属层，所述基底为硅基底，所述下电极位于所述基底的第二区域的上方，所述多个金属层中的顶层金属层包括N个驱动走线，N＝1或者N为大于1的正整数，所述上电极通过所述N个驱动走线分别连接至N个焊盘，所述N个焊盘分别将所述N个驱动走线与各自对应的引线相连。
  3. 根据权利要求2所述的超声指纹装置，其特征在于，所述顶层金属层的上方设置有钝化层，所述钝化层上设置有与所述N个驱动走线对应的第一开窗，所述上电极从所述压电层的上表面延伸至所述第一开窗内，以连接所述N个驱动走线各自的位于所述第一开窗内的第一连接区域。
  4. 根据权利要求3所述的超声指纹装置，其特征在于，所述第一开窗包括与所述N个驱动走线对应的N个子开窗，每个驱动走线的所述第一连接区域位于其对应的子开窗内。
  5. 根据权利要求3或4所述的超声指纹装置，其特征在于，所述钝化层上还设置有与所述N个驱动走线对应的N个第二开窗，其中每个驱动走线位于其对应的所述第二开窗内的第二连接区域，通过其对应的焊盘与其对应的引线连接。
  6. 根据权利要求3至5中任一项所述的超声指纹装置，其特征在于，所述压电层延伸至所述多个金属层的上方，所述N个驱动走线延伸至所述压电层内，所述N个驱动走线的所述第一连接区域与所述压电层相邻。
  7. 根据权利要求6所述的超声指纹装置，其特征在于，所述第一开窗 的尺寸大于所述N个驱动走线的所述第一连接区域的尺寸，所述上电极从所述压电层的上表面延伸至所述第一开窗的第一部分，以覆盖所述N个驱动走线的所述第一连接区域，所述第一开窗的第二部分位于所述压电层的下方。
  8. 根据权利要求7所述的超声指纹装置，其特征在于，所述第一部分在所述N个驱动走线的方向上的尺寸大于或等于150um；和/或，所述第二部分在所述N个驱动走线的方向上的尺寸大于或等于20um。
  9. 根据权利要求2至8中任一项所述的超声指纹装置，其特征在于，所述顶层金属层中与所述N个驱动走线相邻的其他走线，与所述N个驱动走线之间的距离大于或等于10um；和/或，所述顶层金属层上与所述N个驱动走线相邻的其他走线接地。
  10. 根据权利要求2至9中任一项所述的超声指纹装置，其特征在于，所述多个金属层中的第一金属层上与所述N个驱动走线对应的区域挖孔，所述第一金属层是位于所述顶层金属层下方的相邻金属层。
  11. 根据权利要求10所述的超声指纹装置，其特征在于，所述第一金属层上与所述N个驱动走线对应的区域、以及沿所述区域向四周延伸大于或等于12um的区域挖孔。
  12. 根据权利要求2至11中任一项所述的超声指纹装置，其特征在于，所述多个金属层中的第二金属层上与所述N个驱动走线对应的区域接地，所述第二金属层是位于第一金属层下方的相邻金属层。
  13. 根据权利要求12所述的超声指纹装置，其特征在于，所述第二金属层上与所述N个驱动走线对应的区域、以及沿所述区域向四周延伸大于或等于12um的区域接地。
  14. 根据权利要求5所述的超声指纹装置，其特征在于，所述顶层金属层上设置有用于接地的焊盘，所述焊盘设置在所述N个驱动走线的所述第二连接区域的旁侧。
  15. 根据权利要求2至14中任一项所述的超声指纹装置，其特征在于，所述下电极与所述下电极周围的钝化层之间的距离大于或等于100um；和/或，所述顶层金属层中与所述下电极相邻的其他走线接地。
  16. 根据权利要求2至15中任一项所述的超声指纹装置，其特征在于，所述上电极的边缘与所述压电层的边缘之间的距离大于或等于50um。
  17. 根据权利要求3至8中任一项所述的超声指纹装置，其特征在于， N＝1，所述第一开窗在其靠近所述压电层的部分的面积，大于其远离所述压电层的部分的面积。
  18. 根据权利要求17所述的超声指纹装置，其特征在于，所述第一开窗的形状为梯形，所述梯形的下底相比于其上底更靠近所述压电层。
  19. 根据权利要求17所述的超声指纹装置，其特征在于，所述第一开窗的形状为L形，所述L形由平行于所述驱动走线的方向的第一部分、以及垂直于所述驱动走线的方向的第二部分组成，所述第二部分相比于所述第一部分更靠近所述压电层。
  20. 一种电子设备，其特征在于，包括：
    显示屏；以及，
    根据权利要求1至19中任一项所述的超声指纹装置，所述超声指纹装置设置在所述显示屏下方，以实现屏下超声指纹识别。
PCT/CN2022/118481 2022-09-13 2022-09-13 超声指纹装置和电子设备 WO2024055160A1 (zh)

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