WO2024052774A1 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

Info

Publication number
WO2024052774A1
WO2024052774A1 PCT/IB2023/058644 IB2023058644W WO2024052774A1 WO 2024052774 A1 WO2024052774 A1 WO 2024052774A1 IB 2023058644 W IB2023058644 W IB 2023058644W WO 2024052774 A1 WO2024052774 A1 WO 2024052774A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulator
conductor
opening
oxide
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2023/058644
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
宮入秀和
山崎舜平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2024545077A priority Critical patent/JPWO2024052774A1/ja
Publication of WO2024052774A1 publication Critical patent/WO2024052774A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Further, one embodiment of the present invention relates to a storage device and a method for manufacturing the storage device. Further, one embodiment of the present invention relates to a transistor and a method for manufacturing the transistor. Further, one embodiment of the present invention relates to a capacitor and a method for manufacturing the capacitor.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (for example, touch sensors), input/output devices (for example, touch panels), An example of such a driving method or a manufacturing method thereof can be mentioned.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component containing a chip in a package are examples of semiconductor devices. Further, a storage device, a display device, a light emitting device, a lighting device, and an electronic device may themselves be semiconductor devices, and each may include a semiconductor device.
  • a CPU is an assembly of semiconductor elements, including a semiconductor integrated circuit (at least a transistor and a memory) formed into a chip by processing a semiconductor wafer, and on which electrodes serving as connection terminals are formed.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.
  • transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices.
  • ICs integrated circuits
  • display devices Although silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are attracting attention as other materials.
  • Patent Document 1 discloses a CPU with low power consumption that takes advantage of the low leakage current of a transistor using an oxide semiconductor.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by applying the characteristic that a transistor using an oxide semiconductor has a small leakage current.
  • Patent Document 3 and Non-Patent Document 1 a plurality of memory cells are provided in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film. discloses a technique for increasing the density of integrated circuits.
  • Patent Document 4 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.
  • JP2012-257187A JP2011-151383A International Publication No. 2021/053473 JP2013-211537A
  • An object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device. Alternatively, an object of one embodiment of the present invention is to provide a transistor with large on-state current. Alternatively, an object of one embodiment of the present invention is to provide a transistor with good electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption. Alternatively, it is an object of one embodiment of the present invention to provide a storage device that operates at high speed. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing the above transistor, semiconductor device, or memory device.
  • a second layer is formed over the first layer, a mask is formed over the second layer, a first resist mask is formed over the mask, and a first resist mask is formed over the first layer.
  • forming a first opening in a resist mask reducing the size of the first opening in plan view, and forming a second opening in a position of the mask overlapping with the first opening;
  • the first resist mask is removed, a second resist mask is formed on the mask provided with the second opening, and a third opening is formed in the second resist mask.
  • the size of the third opening is reduced, a fourth opening is formed in the mask at a position that overlaps with the third opening but does not overlap with the second opening, and the second resist mask is formed.
  • a second layer is formed over the first layer, a first mask is formed over the second layer, and a second mask is formed over the first mask.
  • forming a first resist mask on the second mask forming a first opening in the first resist mask, and reducing the size of the first opening in plan view.
  • forming a second opening in the second mask at a position overlapping with the first opening, removing the first resist mask, and replacing the second mask with the second opening.
  • forming a second resist mask forming a third opening in the second resist mask, reducing the size of the third opening in plan view, and reducing the size of the third opening in the second resist mask.
  • a fourth opening is formed at a position that overlaps with the opening and does not overlap with the second opening, the second resist mask is removed, and a position of the first mask that overlaps with the second opening is formed.
  • a fifth opening is formed in the second layer at a position overlapping with the fifth opening, the second mask is removed, and a sixth opening is formed in the second layer at a position overlapping with the fifth opening.
  • the step of reducing the size of the third opening and the step of forming the fourth opening are performed simultaneously.
  • the second mask has the same material as at least a portion of the second layer, and the second resist mask is removed during the step of forming the sixth opening.
  • the first layer is a conductor.
  • ALD atomic layer deposition
  • a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated can be provided.
  • a highly reliable transistor, semiconductor device, or memory device can be provided.
  • a transistor with large on-state current can be provided.
  • a transistor with good electrical characteristics can be provided.
  • a semiconductor device or a memory device with low power consumption can be provided.
  • a storage device with high operating speed can be provided.
  • a method for manufacturing the above transistor, semiconductor device, or memory device can be provided.
  • FIG. 1A to 1C are plan layouts showing an example of a storage device.
  • 2A to 2C are plan layouts showing an example of a storage device.
  • FIG. 3A1, FIG. 3B1, and FIG. 3C1 are plan views showing an example of a processing method.
  • FIG. 3A2, FIG. 3B2, and FIG. 3C2 are cross-sectional views showing an example of a processing method.
  • FIG. 4A1, FIG. 4B1, and FIG. 4C1 are plan views showing an example of a processing method.
  • FIG. 4A2, FIG. 4B2, and FIG. 4C2 are cross-sectional views showing an example of a processing method.
  • 5A to 5C are cross-sectional views showing an example of a processing method.
  • 6A to 6F are plan views showing an example of a processing method.
  • FIG. 7A is a plan view showing an example of a storage device.
  • 7B and 7C are cross-sectional views showing an example of a storage device.
  • FIG. 7D is a circuit diagram for explaining an example of the configuration of a storage device.
  • 8A and 8B are plan views showing an example of a storage device.
  • 9A to 9D are cross-sectional views showing an example of a storage device.
  • 10A to 10D are cross-sectional views showing an example of a storage device.
  • FIG. 11A is a cross-sectional view showing an example of a storage device.
  • FIG. 11B is a cross-sectional view showing an example of a storage device.
  • 12A to 12D are cross-sectional views showing an example of a storage device.
  • FIG. 13A is a plan view showing an example of a storage device.
  • 13B and 13C are cross-sectional views showing an example of a storage device.
  • 14A and 14B are cross-sectional views showing an example of a storage device.
  • 15A to 15D are cross-sectional views showing an example of a storage device.
  • 16A and 16B are cross-sectional views showing an example of a storage device.
  • FIG. 17A is a plan view showing an example of a storage device.
  • 17B and 17C are cross-sectional views showing an example of a storage device.
  • FIG. 18A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 18B and 18C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • 19A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 19B and 19C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 20A is a plan view showing an example of a method for manufacturing a storage device.
  • 20B and 20C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 21A is a plan view showing an example of a method for manufacturing a storage device.
  • 21B and 21C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 22A is a plan view illustrating an example of a method for manufacturing a storage device.
  • FIG. 22B and 22C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 23A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 23B and 23C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 24A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 24B and 24C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 25A is a plan view showing an example of a method for manufacturing a storage device.
  • 25B and 25C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • 26A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 26B and 26C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 27A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 28A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 28B and 28C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 29A is a plan view showing an example of a storage device.
  • FIG. 29B is a cross-sectional view showing an example of a storage device.
  • FIG. 29A is a plan view showing an example of a storage device.
  • FIG. 29B is a cross-sectional view showing an example of a storage device.
  • FIG. 29A is a plan
  • FIG. 30A is a plan view showing an example of a storage device.
  • FIG. 30B is a cross-sectional view showing an example of a storage device.
  • FIG. 31A is a plan view showing an example of a storage device.
  • FIG. 31B is a cross-sectional view showing an example of a storage device.
  • FIG. 32 is a cross-sectional view showing an example of a storage device.
  • FIG. 33 is a block diagram showing an example of a storage device.
  • 34A and 34B are schematic diagrams showing an example of a storage device.
  • 35A to 35D are circuit diagrams showing an example of a storage device.
  • FIG. 36 is a circuit diagram showing an example of a storage device.
  • 37A and 37B are diagrams showing an example of an electronic component.
  • FIGS. 38A and 38B are diagrams illustrating an example of an electronic device.
  • FIGS. 38C to 38E are diagrams showing an example of a large-sized computer.
  • FIG. 39 is a diagram showing an example of space equipment.
  • FIG. 40 is a diagram illustrating an example of a storage system applicable to a data center.
  • the position, size, range, etc. of each structure shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.
  • a layer or a resist mask may be unintentionally reduced due to a process such as etching, but this may not be reflected in the diagram for ease of understanding.
  • ordinal numbers such as “first” and “second” are used for convenience, and do not limit the number of components or the order of the components (for example, the order of steps or the order of lamination). It's not something you do. Further, the ordinal number attached to a constituent element in a certain part of this specification may not match the ordinal number attached to the constituent element in another part of this specification or in the claims.
  • a transistor is a type of semiconductor element, and can realize a function of amplifying current or voltage, a switching operation of controlling conduction or non-conduction, and the like.
  • Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a region where a channel is formed (also referred to as a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode). A current can be passed between the source and the drain through the source and drain.
  • a channel formation region refers to a region through which current mainly flows.
  • source and drain may be interchanged when transistors with different polarities are used, or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.
  • impurity of a semiconductor refers to, for example, something other than the main components constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be considered an impurity.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and the oxide semiconductor.
  • transition metals other than the main components include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as VO
  • oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • a nitrided oxide refers to a material whose composition contains more nitrogen than oxygen.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectroscopy
  • Ray Photoelectron Spectroscopy can be used.
  • SIMS is suitable when the content of the target element is high (for example, 0.5 atomic % or more, or 1 atomic % or more).
  • SIMS is suitable when the content of the target element is low (for example, 0.5 atomic % or less, or 1 atomic % or less.
  • SIMS When comparing the contents of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis techniques.
  • the term “insulator” can be replaced with an insulating film or an insulating layer.
  • the term “conductor” can be translated as a conductive film or a conductive layer.
  • the term “semiconductor” can be translated as a semiconductor film or a semiconductor layer.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case where the temperature is greater than or equal to -5 degrees and less than or equal to 5 degrees is also included.
  • substantially parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • perpendicular refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees are also included.
  • substantially perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • electrically connected includes a case where the two are connected via "something that has some kind of electrical effect.”
  • something that has some kind of electrical effect is not particularly limited as long as it enables transmission and reception of electrical signals between connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, switching elements such as transistors, resistance elements, coils, capacitance elements, and other elements with various functions.
  • off-state current refers to leakage current between a source and a drain when a transistor is in an off state (also referred to as a non-conducting state or a cutoff state).
  • an off state is a state in which the voltage between the gate and source, V gs , is lower than the threshold voltage V th for n-channel transistors (higher than V th for p-channel transistors). means.
  • top shape of a certain component refers to the outline shape of the component in plan view.
  • planar view refers to viewing from the normal direction of the surface on which the component is formed or the surface of the support (for example, a substrate) on which the component is formed.
  • a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • a region where the angle between the inclined side surface and the substrate surface or the surface to be formed also referred to as a taper angle
  • the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be completely flat, and may be substantially planar with a minute curvature or substantially planar with minute irregularities.
  • A is located on B, at least a portion of A is located on B. Therefore, for example, it can be said that A has a region located on B.
  • A covers B, at least a portion of A covers B. Therefore, for example, it can be said that A has a region that covers B.
  • arrows indicating the X direction, Y direction, and Z direction may be attached.
  • the "X direction” refers to the direction along the X axis, and the forward direction and reverse direction may not be distinguished unless explicitly stated.
  • the X direction, the Y direction, and the Z direction are directions that intersect with each other.
  • the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other.
  • one of the X direction, the Y direction, or the Z direction may be referred to as a "first direction” or a “first direction.” Further, the other direction may be referred to as a “second direction” or “second direction”. Further, the remaining one may be referred to as a "third direction” or "third direction.”
  • Embodiment 1 a semiconductor device of one embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1 to 32.
  • a memory device will be mainly described as an example of a semiconductor device of one embodiment of the present invention.
  • the storage device has memory cells. Further, the memory cell includes a transistor and a capacitor.
  • FIG. 1A shows a planar layout of a storage device according to one embodiment of the present invention.
  • the planar layout of FIG. 1A shows a region including 4 ⁇ 4 memory cells 150.
  • a conductor 260 functioning as a word line, a conductor 240 functioning as a bit line, and an opening 290 are illustrated.
  • the memory cell 150 is provided in a region where the conductor 260, the conductor 240, and the opening 290 overlap.
  • the opening 290 is provided in a region of the conductor 240 where the conductor 240 and the conductor 260 intersect.
  • FIG. 1A shows a configuration in which memory cells 150 are arranged in a matrix. Further, a configuration is shown in which the openings 290 are arranged in a matrix. Further, a configuration is shown in which the conductor 260 is provided extending in the Y direction (also referred to as the column direction), and the conductor 240 is provided extending in the X direction (also referred to as the row direction). In other words, a configuration is shown in which the conductor 260 and the conductor 240 are perpendicular to each other.
  • the width of the conductor 260 in the direction (X direction) perpendicular to the direction in which the conductor 260 extends is uniform
  • the width of the conductor 260 in the direction (Y direction) perpendicular to the direction in which the conductor 240 extends is uniform. This shows a configuration in which the width of the area is uniform. Note that the present invention is not limited to this.
  • FIG. 1B is another example of a planar layout of a storage device.
  • the planar layout of FIG. 1B illustrates a conductor 260, a conductor 240, a memory cell 150, and an opening 290, similar to FIG. 1A.
  • the memory device shown in FIG. 1B differs from the memory device shown in FIG. 1A mainly in the arrangement of memory cells 150, the arrangement of openings 290, the shape of conductors 240, and the direction in which conductors 260 extend.
  • the memory cells 150 are arranged such that the odd-numbered rows and the even-numbered rows are shifted by half of the repeating unit of the memory cells 150. Furthermore, the memory cells 150 are arranged with an offset of half of the repeating unit between the odd-numbered columns and the even-numbered columns. Similarly, the openings 290 shown in FIG. 1B are arranged with an offset of half the repeating unit of the openings 290 between odd and even rows. Furthermore, the openings 290 are arranged to be shifted by half of the repeating unit between the odd-numbered columns and the even-numbered columns.
  • a memory cell adjacent to the first memory cell in the X direction is a second memory cell
  • a second memory cell is a memory cell adjacent to the first memory cell in the extending direction of the conductor 260.
  • the memory cell closest to is defined as the third memory cell.
  • the center of the third memory cell be located on a straight line that passes between the first memory cell and the second memory cell and is parallel to the Y direction.
  • the third memory cell is located at a location shifted by half of the repeating unit in the X direction with respect to each of the first memory cell and the second memory cell.
  • the extending direction of the conductor 260 is arranged at an angle with respect to the Y direction.
  • the conductor 240 is provided extending in the X direction. That is, depending on the arrangement of memory cells 150 (or openings 290), the extending direction of conductor 260 may not be orthogonal to the extending direction of conductor 240. In other words, the conductor 260 does not need to be orthogonal to the conductor 240, and the conductor 260 and the conductor 240 are arranged so as to intersect with each other.
  • the conductor 240 has a first region and a second region.
  • the first region is the opening 290 and its vicinity, and the width of the first region in the Y direction is defined as the first width.
  • the first region can be said to have a shape of a quadrilateral with rounded corners.
  • the second region is a region between adjacent openings 290 in one conductor 240 (also referred to as a region between two adjacent first regions), and is a region in the Y direction in the second region. Let the width be the second width. At this time, the second width is preferably smaller than the first width.
  • the physical distance between the conductors 240 can be reduced when the memory cells 150 (or the openings 290) are arranged in rows and columns shifted by half the repeating unit. . Therefore, miniaturization and high integration of the memory device can be achieved.
  • FIG. 1C is another example of a planar layout of a storage device.
  • the planar layout of FIG. 1C illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 1B.
  • the memory device shown in FIG. 1C differs from the memory device shown in FIG. 1B mainly in the shape of the first region of the conductor 240.
  • the first region of the conductor 240 shown in FIG. 1B has a rectangular shape with rounded corners in a plan view, and one side of the rectangle is parallel to the X direction or the Y direction.
  • the first region of the conductor 240 shown in FIG. 1C has a rectangular shape with rounded corners in a plan view, and the diagonal of the rectangle is parallel to the X direction or the Y direction.
  • FIGS. 1B and 1C show an example in which the first region of the conductor 240 has a rectangular shape with rounded corners in plan view, the present invention is not limited to this.
  • FIG. 2A is another example of a planar layout of a storage device.
  • the planar layout of FIG. 2A illustrates a conductor 260, a conductor 240, a memory cell 150, and an opening 290, similar to FIG. 1B.
  • the memory device shown in FIG. 2A differs from the memory device shown in FIG. 1B or 1C mainly in the shape of the first region of the conductor 240.
  • the first region of the conductor 240 shown in FIG. 2A has a circular shape in plan view. Even with this configuration, the physical distance between the conductors 240 can be reduced when the memory cells 150 (or the openings 290) are arranged with rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved.
  • the first region of the conductor 240 in plan view is not limited to the shape described above.
  • the first region of the conductor 240 in plan view may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
  • FIG. 2A shows a configuration in which the width of the conductor 260 in the direction perpendicular to the direction in which the conductor 260 extends is uniform, the present invention is not limited to this.
  • FIG. 2B is another example of the planar layout of the storage device.
  • the planar layout of FIG. 2B illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, similar to FIG. 2A.
  • the memory device shown in FIG. 2B differs from the memory device shown in FIG. 2A mainly in the shape of the conductor 260.
  • the conductor 260 shown in FIG. 2B has a first region and a second region.
  • the first region is the opening 290 and its vicinity, and is circular in plan view.
  • the second region is a region between adjacent openings 290 in one conductor 260 (also referred to as a region between two adjacent first regions). Note that the first region of the conductor 260 overlaps with the first region of the conductor 240. With this configuration, the physical distance between the conductors 260 can be reduced when the memory cells 150 (or the openings 290) are arranged with rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved.
  • FIG. 2C is another example of the planar layout of the storage device.
  • the planar layout of FIG. 2C illustrates the conductor 260, the conductor 240, the memory cell 150, and the opening 290, as in FIG. 2A.
  • the memory device shown in FIG. 2C differs from the memory device shown in FIG. 2A mainly in the shape and stretching direction of the conductor 260.
  • the conductor 260 shown in FIG. 2C has a meandering shape like a triangular wave when viewed from above, and is provided extending in the Y direction. With this configuration, the physical distance between the conductors 260 can be reduced when the memory cells 150 (or the openings 290) are arranged with rows and columns shifted by half the repeating unit. Therefore, miniaturization and high integration of the memory device can be achieved.
  • the conductor 260 in plan view is not limited to the above, and may have a meander shape or the like.
  • one or both of the physical distance between the conductors 260 and the physical distance between the conductors 240 can be reduced, and the storage device can be miniaturized and highly integrated.
  • a first resist mask is formed over a hard mask, a first opening is formed in the first resist mask, and then a first opening in a plan view is formed. After (or while reducing) the size of the opening in the hard mask, a second opening is provided in the hard mask. Then, after removing the first resist mask on the hard mask, forming a second resist mask on the hard mask, and forming a third opening in the second resist mask, a third opening in a plan view is formed. After (or while) reducing the size of the opening, a fourth opening is provided in the hard mask.
  • the first opening provided in the first resist mask and the third opening provided in the second resist mask are The openings are arranged so as to be shifted from each other. In this way, by reducing the opening of the resist mask formed using an exposure apparatus, a minute opening can be formed in the resist mask. By performing the process of creating openings in the hard mask multiple times using a resist mask with minute openings, it is possible to form extremely minute openings that exceed the resolution limits of the exposure equipment. .
  • FIGS. 3 to 5 First, an example of forming the opening 290 having the planar layout shown in FIG. 1A will be described using FIGS. 3 to 5.
  • FIG. 3A1, FIG. 3B1, FIG. 3C1, FIG. 4A1, FIG. 4B1, and FIG. 4C1 show plan views of semiconductor devices.
  • 3A2, FIG. 3B2, FIG. 3C2, FIG. 4A2, FIG. 4B2, and FIG. 4C2 are cross-sectional views taken along dashed-dotted line A-B shown in FIG. 3A1, FIG. 3B1, FIG. 3C1, FIG. 4A1, FIG. 4B1, and FIG. 4C1, respectively. It is. Note that some elements are omitted in the plan view for clarity. Further, FIGS. 5A to 5C are cross-sectional views illustrating the steps after FIG. 4C2.
  • a second layer 401 is provided on the first layer 400, a mask 403 is provided on the second layer 401, a mask 405 is provided on the mask 403, and a resist mask 407a is provided on the mask 405. is provided.
  • the first layer 400 and the second layer 401 may each have a single layer structure or a laminated structure.
  • the first layer 400 and the second layer 401 can each include one or more of a conductor, a semiconductor, and an insulator.
  • a method for manufacturing a semiconductor device according to one embodiment of the present invention can be applied to, for example, manufacturing a transistor 200 illustrated in FIGS. 7A to 7C, which will be described later.
  • the first layer 400 corresponds to the conductor 120
  • the second layer 401 corresponds to a stacked structure of the insulator 280 and the conductor 240.
  • a method for manufacturing a semiconductor device according to one embodiment of the present invention can be applied to, for example, manufacturing a capacitor 100 illustrated in FIGS. 7A to 7C, which will be described later.
  • the first layer 400 corresponds to the conductor 110 and the second layer 401 corresponds to the insulator 180.
  • a very fine opening 190 can be formed in the insulator 180.
  • an opening 417a is formed in the resist mask 407a.
  • the minimum size of the opening 417a in plan view depends on the resolution limit of the exposure apparatus.
  • the light used to expose the resist mask 407a can be, for example, i-line (wavelength: 365 nm), g-line (wavelength: 436 nm), h-line (wavelength: 405 nm), or a mixture of these.
  • ultraviolet rays, KrF laser light, ArF laser light, etc. can also be used.
  • exposure may be performed using immersion exposure technology.
  • extreme ultraviolet (EUV) light or X-rays may be used.
  • an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or electron beams because extremely fine processing becomes possible. Note that when exposure is performed by scanning a beam such as an electron beam, a photomask is not necessary.
  • the shape of the opening provided in each component in plan view is circular, but is not particularly limited.
  • the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
  • the opening 417a provided in the resist mask 407a is reduced.
  • the reduced opening is shown as opening 418a.
  • the diameter of the opening 418a is smaller than the diameter of the opening 417a.
  • the length of the diagonal of the opening 418a is smaller than the length of the diagonal of the opening 417a.
  • the opening of the resist mask can be reduced by a chemical method.
  • the opening of the resist mask can be reduced by applying a shrink agent onto the resist mask and performing a predetermined process.
  • the opening of the resist mask may be reduced by applying a material that has a heat-shrinking effect and performing heat treatment.
  • the reduction of the opening of the resist mask 407a and the etching of the mask 405 are performed at the same time.
  • the reaction product 408a adheres to the side surface of the opening 417a, so that the opening 417a of the resist mask 407a is reduced to an opening 418a. Then, an opening 419a is formed in the mask 405 at a position overlapping with the opening 418a (FIGS. 3C1 and 3C2).
  • the reaction product 408a includes a reaction product between the supplied gas and the resist mask 407a, and a reaction product between the gas and the mask 405. After that, the resist mask 407a is removed.
  • an etching gas used for dry etching an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used.
  • an etching gas C 4 F 6 gas, C 5 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, NF 3 gas, CHF 3 gas, Cl 2 gas, BCl 3 gas, SiCl 4 Gas, CCl 4 gas, BBr 3 gas, etc. can be used alone or in combination of two or more gases.
  • oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, hydrocarbon gas, or the like can be added as appropriate to the above etching gas.
  • Etching conditions can be set as appropriate depending on the object to be etched.
  • a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as the dry etching device.
  • a capacitively coupled plasma etching apparatus having parallel plate electrodes may have a configuration in which a high frequency voltage is applied to one electrode of the parallel plate electrodes.
  • a configuration may be adopted in which a plurality of different high frequency voltages are applied to one electrode of a parallel plate type electrode.
  • a configuration may be adopted in which a high frequency voltage of the same frequency is applied to each of the parallel plate type electrodes.
  • a configuration may be adopted in which high frequency voltages having different frequencies are applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • the dry etching device having a high-density plasma source for example, an inductively coupled plasma (ICP) etching device or the like can be used.
  • ICP inductively coupled plasma
  • a resist mask 407b is formed on the mask 403 and the mask 405.
  • An opening 417b is provided in the resist mask 407b.
  • the minimum size of the opening 417b in plan view depends on the resolution limit of the exposure apparatus.
  • the opening 417b is provided so as not to overlap the opening 419a.
  • the opening provided in the resist mask 407b is reduced.
  • the reduced opening is shown as opening 418b.
  • the diameter of the opening 418b is smaller than the diameter of the opening 417b.
  • the length of the diagonal of the opening 418b is smaller than the length of the diagonal of the opening 417b.
  • the reduction of the opening of the resist mask 407b and the etching of the mask 405 are performed at the same time.
  • the reaction product 408b adheres to the side surface of the opening 417b in a dry etching apparatus, so that the opening 417b of the resist mask 407b is reduced to the opening 418b.
  • an opening 419b is formed in the mask 405 at a position overlapping with the opening 418b (FIGS. 4C1 and 4C2).
  • the reaction product 408b includes a reaction product between the supplied gas and the resist mask 407b, and a reaction product between the gas and the mask 405. After that, the resist mask 407b is removed.
  • the mask 405 is provided with an opening 419a and an opening 419b. Due to the resolution of the exposure apparatus, it is difficult to form openings corresponding to the openings 419a and 419b in the resist mask at the same time. On the other hand, as described above, by using the method for manufacturing a semiconductor device of one embodiment of the present invention, a very fine opening can be formed in the mask 405.
  • mask 403 is opened using mask 405 as a hard mask (FIG. 5A). Then, using the mask 403 as a hard mask, an opening reaching the first layer 400 is formed in the second layer 401 (FIG. 5B). At this time or after that, the mask 405 is removed. Furthermore, the mask 403 is removed. Through the above steps, the second layer 401 having minute openings can be formed on the first layer 400 (FIG. 5C).
  • a material for the mask 403 that has a high selectivity with respect to the mask 405 in etching it is preferable to use a material for the mask 403 that has a high selectivity with at least the uppermost layer of the second layer 401 in etching. This can suppress etching of the mask 403 in the etching process of the mask 405 and etching of the second layer 401 in the etching process of the mask 403, respectively.
  • the mask 405 is preferably made of a material that has a low selectivity with respect to at least a portion of the second layer 401 in etching.
  • the mask 405 preferably has the same material as at least a portion of the second layer 401. Thereby, as shown in FIG. 5B, the mask 405 can be removed when opening the second layer 401. This allows the manufacturing process to be simplified.
  • silicon oxide for the mask 405 it is preferable to use silicon oxide for the mask 405, use silicon for the mask 403, and use silicon oxide for at least a portion of the second layer 401.
  • the mask 403 using silicon can be removed using a chlorine-based gas, and the removal of the mask 405 using silicon oxide and the processing of silicon oxide included in the second layer 401 can be performed simultaneously using a fluorine-based gas. .
  • an insulator, a semiconductor, or a conductor can be further formed over the second layer 401 illustrated in FIG. 5C.
  • the inside of the opening of the second layer 401 is in contact with the side surface of the second layer 401 and the top surface of the first layer 400. Then, an oxide semiconductor 230 is formed.
  • the oxide semiconductor 230 is preferably formed using an ALD method, which allows formation of a film with excellent coverage.
  • a conductor 115 is formed so as to be in contact with.
  • the conductor 115 is preferably formed using an ALD method, which allows formation of a film with excellent coverage.
  • 3 to 5 show an example in which a resist mask is formed twice and the process of opening the mask 405 is performed twice, that is, an example including a process of forming an opening 419a and a process of forming an opening 419b. Ta.
  • the number of openings in the mask 405 is not limited to two times, but may be three or more times.
  • FIGS. 2A to 2C there are six memory cells 150 (or openings 290) adjacent to one memory cell 150 (or opening 290) at the shortest distance.
  • 6A to 6F an example will be described in which a resist mask is formed three times and the process of opening the mask 405 is performed three times.
  • an opening 417a is formed in the resist mask 407a.
  • the opening 417a provided in the resist mask 407a is reduced and the mask 405 is etched to form an opening 419a in the mask 405 (FIG. 6B). After that, the resist mask 407a is removed.
  • a resist mask 407b is formed on the mask 405, and an opening 417b is provided in the resist mask 407b.
  • the opening provided in the resist mask 407b is reduced and the mask 405 is etched to form an opening 419b in the mask 405 (FIG. 6D. After that, the resist mask 407b is removed.
  • a resist mask 407c is formed on the mask 405, and an opening 417c is provided in the resist mask 407c.
  • the opening provided in the resist mask 407c is reduced and the mask 405 is etched to form an opening 419c in the mask 405 (FIG. 6F). After that, the resist mask 407c is removed.
  • the mask 405 is provided with an opening 419a, an opening 419b, and an opening 419c. It is difficult to form openings corresponding to the openings 419a to 419c in a resist mask all at once. On the other hand, as described above, by using the method for manufacturing a semiconductor device of one embodiment of the present invention, a very fine opening can be formed in the mask 405.
  • fine openings can be formed in the resist mask by reducing the openings in the resist mask formed using an exposure apparatus.
  • FIG. 7A to 7C are a plan view and a cross-sectional view of a memory device including a transistor 200 and a capacitor 100.
  • FIG. 7A is a plan view of the storage device.
  • FIGS. 7B and 7C are cross-sectional views of the storage device.
  • FIG. 7B is a sectional view of a portion indicated by a dashed line A1-A2 in FIG. 7A.
  • FIG. 7C is a cross-sectional view of the portion shown by the dashed line A3-A4 in FIG. 7A. Note that in the plan view of FIG. 7A, some elements are omitted for clarity.
  • the memory device shown in FIGS. 7A to 7C includes an insulator 140 on a substrate (not shown), a conductor 110 on the insulator 140, a memory cell 150 on the conductor 110, and an insulator on the conductor 110. It has a body 180, an insulator 280, and an insulator 283 on the memory cell 150. Insulator 140, insulator 180, insulator 280, and insulator 283 function as interlayer films.
  • the conductor 110 functions as a wiring.
  • the memory cell 150 includes a capacitor 100 on a conductor 110 and a transistor 200 on the capacitor 100.
  • the capacitive element 100 includes a conductor 115 on the conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130.
  • the conductor 120 functions as one of a pair of electrodes (sometimes called an upper electrode)
  • the conductor 115 functions as the other of a pair of electrodes (sometimes called a lower electrode)
  • the insulator 130 functions as a dielectric. functions as In other words, the capacitive element 100 constitutes an MIM (Metal-Insulator-Metal) capacitor.
  • the insulator 180 is provided with an opening 190 that reaches the conductor 110. At least a portion of the conductor 115 is disposed in the opening 190. Note that the conductor 115 has a region in contact with the top surface of the conductor 110 at the opening 190, a region in contact with the side surface of the insulator 180 in the opening 190, and a region in contact with at least a part of the top surface of the insulator 180. have The insulator 130 is arranged such that at least a portion thereof is located in the opening 190. The conductor 120 is arranged such that at least a portion thereof is located in the opening 190.
  • the conductor 120 is preferably provided so as to fill the opening 190, as shown in FIGS. 7B and 7C.
  • each film provided inside the opening 190 is preferably formed using an ALD method. This improves the coverage of the film.
  • the conductor 115, the insulator 130, and the conductor 120 are each formed using an ALD method.
  • the opening 190 it is preferable to use the method for forming the opening described above. Thereby, fine openings can be formed.
  • FIG. 8A is a plan view showing an excerpt of the conductor 110, the conductor 115, the conductor 120, and the opening 190. Note that the opening 190 provided in the insulator 180 is shown by a broken line. As shown in FIG. 8A, the conductor 115 has an opening 190 in a region overlapping with the conductor 110. As shown in FIG. 8A, the conductor 115 has an opening 190 in a region overlapping with the conductor 110. As shown in FIG.
  • the capacitive element 100 has a structure in which the upper electrode and the lower electrode face each other with a dielectric interposed not only on the bottom surface but also on the side surface of the opening 190, and the capacitance per unit area can be increased. can. Therefore, as the depth of the opening 190 is increased, the capacitance of the capacitive element 100 can be increased. By increasing the capacitance per unit area of the capacitive element 100 in this manner, the read operation of the storage device can be stabilized. Further, it is possible to promote miniaturization or higher integration of storage devices.
  • the side walls of the opening 190 are perpendicular to the top surface of the conductor 110.
  • the opening 190 has a cylindrical shape. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
  • a conductor 115 and an insulator 130 are laminated along the side wall of the opening 190 and the top surface of the conductor 110 . Further, a conductor 120 is provided on the insulator 130 so as to fill the opening 190.
  • the capacitive element 100 having such a configuration may be called a trench-type capacitor or a trench capacitor.
  • An insulator 280 is arranged on the capacitive element 100. That is, the insulator 280 is placed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is placed under the insulator 280.
  • the transistor 200 includes a conductor 120, a conductor 240 over an insulator 280, an oxide semiconductor 230, an insulator 250 over the oxide semiconductor 230, and a conductor 260 over the insulator 250.
  • the oxide semiconductor 230 functions as a semiconductor layer
  • the conductor 260 functions as a gate electrode
  • the insulator 250 functions as a gate insulator
  • the conductor 120 functions as one of a source electrode and a drain electrode
  • the conductor 240 functions as a source electrode and a drain electrode. functions as the other of the source electrode and the drain electrode.
  • the insulator 280 and the conductor 240 are provided with an opening 290 that reaches the conductor 120. At least a portion of the oxide semiconductor 230 is arranged in the opening 290. Note that the oxide semiconductor 230 has a region in contact with the top surface of the conductor 120 at the opening 290, a region in contact with the side surface of the conductor 240 in the opening 290, and a region in contact with at least a part of the top surface of the conductor 240. has. Insulator 250 is arranged such that at least a portion thereof is located in opening 290 . The conductor 260 is arranged so that at least a portion thereof is located in the opening 290.
  • the conductor 260 is preferably provided so as to fill the opening 290, as shown in FIGS. 7B and 7C.
  • each film provided inside the opening 290 is preferably formed using an ALD method. This improves the coverage of the film.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are each preferably formed using an ALD method.
  • the opening 290 it is preferable to use the method for forming the opening described above. Thereby, fine openings can be formed.
  • FIG. 8B is a plan view showing excerpts of the conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290.
  • the opening 290 provided in the insulator 280 is shown by a broken line.
  • the conductor 240 has an opening 290 in a region overlapping with the conductor 120. Further, it is preferable that the conductor 240 is not provided inside the opening 290. In other words, the conductor 240 preferably does not have a region in contact with the side surface of the insulator 280 on the opening 290 side.
  • the oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the upper surface of the conductor 240. In this way, since the oxide semiconductor 230 is in contact with not only the side surface but also the top surface of the conductor 240, the area in which the oxide semiconductor 230 and the conductor 240 are in contact can be increased.
  • the transistor 200 is provided to overlap the capacitive element 100. Further, the opening 290 in which a part of the structure of the transistor 200 is provided has a region that overlaps with the opening 190 in which a part of the structure of the capacitor 100 is provided.
  • the conductor 120 has a function as one of the source electrode and drain electrode of the transistor 200 and a function as an upper electrode of the capacitor 100
  • the transistor 200 and the capacitor 100 share a part of the structure. I will do it.
  • the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in plan view. As a result, the area occupied by the memory cells 150 can be reduced, so the memory cells 150 can be arranged with high density and the storage capacity of the memory device can be increased. In other words, the storage device can be highly integrated.
  • FIG. 7D A circuit diagram of the memory device shown in this embodiment is shown in FIG. 7D.
  • the configuration shown in FIGS. 7A to 7C functions as a memory cell of a storage device.
  • the memory cell includes a transistor Tr and a capacitive element C.
  • the transistor Tr corresponds to the transistor 200
  • the capacitive element C corresponds to the capacitive element 100.
  • One of the source and drain of the transistor Tr is connected to one of a pair of electrodes of the capacitive element C.
  • the other of the source and drain of the transistor Tr is connected to the wiring BL.
  • the gate of the transistor Tr is connected to the wiring WL.
  • the other of the pair of electrodes of the capacitive element C is connected to the wiring PL.
  • the wiring BL corresponds to the conductor 240
  • the wiring WL corresponds to the conductor 260
  • the wiring PL corresponds to the conductor 110.
  • the conductor 260 is preferably provided extending in the Y direction
  • the conductor 240 is preferably provided extending in the X direction.
  • the wiring BL and the wiring WL are provided to intersect with each other.
  • the wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited to this.
  • the wiring PL may be provided parallel to the wiring WL (conductor 260) or may be provided parallel to the wiring BL (conductor 240).
  • Capacitive element 100 includes a conductor 115, an insulator 130, and a conductor 120. Furthermore, a conductor 110 is provided below the conductor 115 . The conductor 115 has a region in contact with the conductor 110.
  • the conductor 110 is provided on the insulator 140.
  • the conductor 110 functions as a wiring PL, and can be provided in a planar shape, for example.
  • the conductor 110 the conductors described in the section [Conductor] described below can be used in a single layer or a laminated structure.
  • a highly conductive material such as tungsten can be used as the conductor 110. By using such a conductive material with high conductivity, the conductivity of the conductor 110 can be improved and the conductor 110 can sufficiently function as the wiring PL.
  • the conductor 115 is preferably made of a conductive material that is not easily oxidized, a conductive material that has a function of suppressing oxygen diffusion, or the like in a single layer or a stacked layer.
  • a conductive material that is not easily oxidized titanium nitride or indium tin oxide added with silicon may be used.
  • a structure in which titanium nitride is laminated on tungsten may be used.
  • a structure may be used in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten.
  • Insulator 130 is provided on conductor 115 .
  • the insulator 130 is provided so as to be in contact with the top and side surfaces of the conductor 115. That is, it is preferable that the insulator 130 has a structure that covers the side end portions of the conductor 110. This can prevent short-circuiting between the conductor 115 and the conductor 120.
  • a structure may be adopted in which the side ends of the insulator 130 and the side ends of the conductor 115 coincide.
  • the insulator 130 and the conductor 115 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.
  • the insulator 130 it is preferable to use a material with a high dielectric constant, a so-called high-k material, described in the section [Insulator] described later.
  • a high-k material as the insulator 130, the insulator 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently secured.
  • the insulator 130 is used by laminating insulators made of a high-k material, and is made of a material having a high dielectric constant (high-k) and a material having a dielectric strength higher than that of the high-k material.
  • a laminated structure is used.
  • the insulator 130 an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
  • an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulator having a relatively high dielectric strength, such as aluminum oxide the dielectric strength is improved and electrostatic breakdown of the capacitive element 100 can be suppressed.
  • a material that can have ferroelectricity may be used as the insulator 130.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • element J1 here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.
  • hafnium oxide examples include added materials.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set as appropriate.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 is set to 1:1 or around 1:1.
  • element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Added materials, etc.
  • the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set as appropriate. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 is set to 1:1 or around 1:1.
  • lead titanate PbTiO x
  • barium strontium titanate BST
  • strontium titanate PZT
  • strontium bismuthate tantalate SBT
  • Piezoelectric ceramics having a perovskite structure such as bismuth ferrite (BFO) and barium titanate, may also be used.
  • examples of materials that can have ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen.
  • the element M1 is one or more selected from aluminum, gallium, indium, and the like.
  • the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Note that the ratio between the number of atoms of element M1 and the number of atoms of element M2 can be set as appropriate.
  • a metal oxide containing element M1 and nitrogen may have ferroelectricity even if it does not contain element M2.
  • materials that can have ferroelectricity include materials in which element M3 is added to the metal nitride described above.
  • the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.
  • examples of materials that can have ferroelectricity include perovskite oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 having a ⁇ alumina structure.
  • metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto.
  • a metal oxynitride obtained by adding nitrogen to the above-mentioned metal oxide, or a metal nitride obtained by adding oxygen to the above-mentioned metal nitride, etc. may be used.
  • the material that can have ferroelectricity for example, a mixture or compound consisting of a plurality of materials selected from the materials listed above can be used.
  • the insulator 130 can have a laminated structure made of a plurality of materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above may change not only due to film formation conditions but also due to various processes, so in this specification, only materials that exhibit ferroelectricity will be referred to. It is not only called a ferroelectric material, but also a material that can have ferroelectric properties.
  • a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even when processed into a thin film of several nanometers.
  • the film thickness of the insulator 130 can be set to 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less).
  • the film thickness is preferably 8 nm or more and 12 nm or less.
  • a layered material that can have ferroelectric properties is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification and the like.
  • a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a small area.
  • the area (occupied area) of the ferroelectric layer in plan view is 100 ⁇ m 2 or less, 10 ⁇ m 2 or less, 1 ⁇ m 2 or less, or 0.1 ⁇ m 2 or less, it can have ferroelectricity.
  • the thickness is 10000 nm 2 or less, or 1000 nm 2 or less, it may have ferroelectricity.
  • a ferroelectric material is an insulator, and has the property that polarization occurs internally when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. Therefore, a nonvolatile memory element can be formed using a capacitive element using this material as a dielectric (hereinafter sometimes referred to as a ferroelectric capacitor).
  • a nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like.
  • a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitive element 100, the storage device described in this embodiment functions as a ferroelectric memory.
  • ferroelectricity is said to be developed when oxygen or nitrogen in the crystal contained in the ferroelectric layer is displaced by an external electric field. Furthermore, the expression of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain crystals. In particular, it is preferable for the insulator 130 to include a crystal having a rectangular crystal structure because ferroelectricity is exhibited. Note that the crystal structure of the crystal contained in the insulator 130 may be one or more selected from cubic, tetragonal, rectangular, monoclinic, and hexagonal. good. Further, the insulator 130 may have an amorphous structure. At this time, the insulator 130 may have a composite structure having an amorphous structure and a crystal structure.
  • the conductor 120 is provided in contact with a part of the upper surface of the insulator 130. Further, as shown in FIG. 8A, the side end portion of the conductor 120 is preferably located inside the side end portion of the conductor 115 in both the X direction and the Y direction. Note that in a structure in which the insulator 130 covers the side end portion of the conductor 115, the side end portion of the conductor 120 may be located outside the side end portion of the conductor 115.
  • the conductors described in the section [Conductor] described later can be used in a single layer or in a laminated manner.
  • the conductor 120 it is preferable to use a conductive material that is not easily oxidized, a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • a conductive material that is not easily oxidized a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • titanium nitride or tantalum nitride can be used.
  • a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, titanium nitride is in contact with the insulator 130 and tantalum nitride is in contact with the oxide semiconductor 230.
  • the conductor 120 may have a structure in which tungsten is laminated on titanium nitride, for example.
  • the conductor 120 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in the section [Conductor] described below.
  • a conductive material containing oxygen as the conductor 120, conductivity can be maintained even if the conductor 120 absorbs oxygen.
  • an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 is suitable because it can maintain conductivity.
  • the conductor 120 for example, a single layer or a stack of indium tin oxide (also referred to as ITO), indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), etc. It can be used indium tin oxide (also referred to as ITO), indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), etc. It can be used indium tin
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant described in the section [Insulator] described later can be used in a single layer or a laminated form. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. At this time, the insulator 180b includes at least silicon and oxygen.
  • the insulator 180 is shown as a single layer in FIGS. 7B and 7C, the present invention is not limited to this.
  • the insulator 180 may have a laminated structure.
  • the insulator 180 may have a stacked structure of an insulator 180a and an insulator 180b on the insulator 180a.
  • an insulating material applicable to the insulator 180 described above may be used.
  • the insulator 180a it is preferable to use an insulator having barrier properties against oxygen, which is described in the section [Insulator] described later. Oxygen contained in the insulator 180b may oxidize the conductor 110, resulting in increased resistance. By providing the insulator 180a between the insulator 180b and the conductor 110, it is possible to prevent the conductor 110 from being oxidized and increasing its resistance.
  • impurities such as hydrogen When impurities such as hydrogen are mixed into the insulator 130, leakage current generated between the upper electrode and the lower electrode may increase. Furthermore, when a material that can have ferroelectricity is used as the insulator 130, impurities such as hydrogen may be mixed into the material that can have ferroelectricity, which may reduce the crystallinity of the material that can have ferroelectricity. There is a risk of deterioration. Therefore, it is preferable to prevent impurities such as hydrogen from entering the insulator 130.
  • the insulator 180a it is preferable to use an insulator having barrier properties against hydrogen, which is described in the "Insulator" section below. This can suppress hydrogen from diffusing into the insulator 130 via the insulator 180b and the conductor 115. Silicon nitride and silicon nitride oxide can be suitably used for the insulator 180a because they each release less impurities (for example, water and hydrogen) from themselves and are less permeable to oxygen and hydrogen. At this time, the insulator 180a includes at least silicon and nitrogen.
  • the insulator 180a it is preferable to use an insulator having a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced.
  • the insulator 180a magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 180a.
  • FIGS. 9A and 9B illustrate a structure in which the insulator 180 has a two-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulator 180 may have a laminated structure of three or more layers.
  • an insulator may be provided between the conductor 115 and the insulator 130 and the insulator 180b in addition to the insulator 180a and the insulator 180b.
  • an insulator applicable to the insulator 180a can be used. This can suppress hydrogen from diffusing into the insulator 130 via the insulator 180b.
  • the insulator 185 is provided between the conductor 115 and the insulator 180. Further, it is preferable that the insulator 185 is provided so as to be in contact with the side surface of the insulator 180 in the opening 190. That is, the insulator 185 is preferably provided between the side surface of the insulator 180 in the opening 190 and the conductor 115. Since the insulator 185 is provided along the opening 190, it is preferably formed using an ALD method.
  • the insulator 185 it is preferable to use an insulator having barrier properties against hydrogen, which is described in the section [Insulator] described later. This can suppress hydrogen from diffusing into the insulator 130 from outside the capacitive element 100 via the insulator 180.
  • silicon nitride or silicon nitride oxide can be used as the insulator 185.
  • the insulator 185 includes at least silicon and nitrogen.
  • the insulator 185 it is preferable to use an insulator having a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced.
  • the insulator 185 magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 185.
  • the insulator 185 is provided so as to be in contact with the side surface of the insulator 180a in the opening 190 and the side surface of the insulator 180b in the opening 190, but the present invention is not limited to this. It's not something you can do.
  • the insulator 185 may be provided so as to be in contact with a part of the upper surface of the insulator 180a and the side surface of the insulator 180b at the opening 190.
  • the conductor 120 is located inside the conductor 115 with the insulator 130 in between, but the present invention is not limited to this.
  • the conductor 120 may be located outside the conductor 115 with the insulator 130 in between.
  • the insulator 130 is provided on the outer side surface of the conductor 115 in addition to a region in contact with the inside of the recess of the conductor 115 and a region in contact with the upper surface of the conductor 115. It has an area located in .
  • the conductor 120 is provided so as to fill the recessed portion of the conductor 115 with an insulator 130 interposed therebetween. Furthermore, the conductor 120 has a region that faces a part of the outer side surface of the conductor 115 with the insulator 130 in between.
  • the capacitance per unit area can be increased.
  • an insulator 135 may be provided between the outer side surface of the conductor 115 and the insulators 130 and 180.
  • an insulator 182 may be provided over the conductor 120 and the insulator 130. Further, it is preferable that the insulator 182 is subjected to a planarization treatment so that the upper surface of the conductor 120 is exposed. By performing planarization treatment on the insulator 182, the transistor 200 can be suitably formed over the capacitor 100.
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator applicable to the insulator 180 can be used as the insulator 182 .
  • the insulator 180 may be omitted.
  • the storage device shown in FIGS. 10C and 10D differs from the storage device shown in FIGS. 10A and 10B in that an insulator 180 is not provided. By not providing the insulator 180, the manufacturing process of the memory device can be simplified.
  • the transistor 200 includes the conductor 120, the conductor 240 on the insulator 280, the upper surface of the conductor 120 exposed in the opening 290, and the insulator 280 in the opening 290. , the side surface of the conductor 240 in the opening 290, and the oxide semiconductor 230 provided in contact with at least a portion of the top surface of the conductor 240; and the insulator 250 provided in contact with the top surface of the oxide semiconductor 230. and a conductor 260 provided in contact with the upper surface of the insulator 250.
  • opening 290 At least some of the components of transistor 200 are disposed in opening 290.
  • the bottom of the opening 290 is the top surface of the conductor 120
  • the sidewalls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240.
  • the sidewalls of opening 290 are perpendicular to the top surface of conductor 110.
  • the opening 290 has a cylindrical shape. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
  • the opening 290 is circular in plan view, but the present invention is not limited to this.
  • the opening 290 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
  • the maximum width of the opening 290 may be calculated as appropriate depending on the shape of the top of the opening 290.
  • the maximum width of the opening 290 may be the length of the diagonal line at the top of the opening 290.
  • Portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290. Therefore, the oxide semiconductor 230 is provided to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided to cover the oxide semiconductor 230, and a recessed portion of the insulator 250 that reflects the shape of the opening 290 is formed. A conductor 260 is provided so as to be buried therein.
  • FIG. 11A an enlarged view of the oxide semiconductor 230 and its vicinity in FIG. 7B is shown in FIG. 11A. Further, a cross-sectional view in the XY plane including the conductor 240 is shown in FIG. 11B.
  • the oxide semiconductor 230 includes a region 230i, and a region 230na and a region 230nb that are provided to sandwich the region 230i.
  • the region 230na is a region of the oxide semiconductor 230 that is in contact with the conductor 120. At least a portion of the region 230na functions as one of a source region and a drain region of the transistor 200.
  • the region 230nb is a region of the oxide semiconductor 230 that is in contact with the conductor 240. At least a portion of the region 230nb functions as the other of the source region and the drain region of the transistor 200.
  • the conductor 240 is in contact with the entire outer periphery of the oxide semiconductor 230. Therefore, the other of the source region and the drain region of the transistor 200 can be formed over the entire outer periphery of a portion of the oxide semiconductor 230 that is formed in the same layer as the conductor 240.
  • the region 230i is a region of the oxide semiconductor 230 between the region 230na and the region 230nb. At least a portion of the region 230i functions as a channel formation region of the transistor 200.
  • the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 between the conductor 120 and the conductor 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or a region near the region.
  • the channel length of transistor 200 is the distance between the source and drain regions. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120.
  • FIG. 11A shows the channel length L of the transistor 200 with a dashed double-headed arrow.
  • the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 are in contact with each other and the end of the region where the oxide semiconductor 230 and the conductor 240 are in contact in a cross-sectional view.
  • the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in cross-sectional view.
  • the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the thickness of the insulator 280. Therefore, the channel length of the transistor 200 is set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more). As a result, the on-state current of the transistor 200 increases, and the frequency characteristics can be improved. Therefore, the read speed and write speed of the memory cell 150 can be improved, so that a memory device with high operating speed can be provided.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290.
  • the area occupied by the transistor 200 can be reduced compared to a conventional transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane. This allows the storage device to be highly integrated, thereby increasing the storage capacity per unit area.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided concentrically, as in FIG. 11B. Therefore, the side surface of the conductor 260 provided at the center faces the side surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. That is, in plan view, the entire circumference of the oxide semiconductor 230 becomes a channel formation region.
  • the channel width of the transistor 200 is determined by the length of the outer circumference of the oxide semiconductor 230. In other words, the channel width of the transistor 200 can be said to be determined by the maximum width of the opening 290 (the maximum diameter when the opening 290 is circular in plan view). In FIGS.
  • the maximum width D of the opening 290 is indicated by a two-dot chain double-headed arrow.
  • the channel width W of the transistor 200 is indicated by a dot-dash double-headed arrow.
  • the maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D ⁇ ". By applying the method for forming an opening according to one embodiment of the present invention described above, the maximum width D of the opening 290 can be easily reduced.
  • the channel length L of the transistor 200 is preferably smaller than at least the channel width W of the transistor 200.
  • the channel length L of the transistor 200 according to one embodiment of the present invention is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, with respect to the channel width W of the transistor 200. With such a configuration, a transistor having good electrical characteristics and high reliability can be realized.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided concentrically. Accordingly, the distance between the conductor 260 and the oxide semiconductor 230 becomes approximately uniform, so that a gate electric field can be applied to the oxide semiconductor 230 approximately uniformly.
  • a channel formation region of a transistor using an oxide semiconductor for a semiconductor layer preferably has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or a metal element than the source and drain regions.
  • hydrogen near oxygen vacancies may form defects in which hydrogen is present in oxygen vacancies (hereinafter sometimes referred to as V O H), and generate electrons that become carriers.
  • V O H oxygen vacancies
  • V OH are also preferably reduced.
  • the channel formation region of the transistor is a high resistance region with low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.
  • the source region and drain region of a transistor using an oxide semiconductor for the semiconductor layer have more oxygen vacancies, more V O H, or a higher concentration of impurities such as hydrogen, nitrogen, and metal elements than the channel formation region.
  • the opening 290 is provided so that the side wall of the opening 290 is perpendicular to the upper surface of the conductor 110, but the present invention is not limited to this.
  • the sidewalls of opening 290 may be tapered.
  • the storage device shown in FIGS. 12A and 12B has a configuration in which the side wall of the opening 290 is tapered. Note that FIG. 7A can be referred to for a plan view of the storage device shown in FIGS. 12A and 12B.
  • the angle between the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 110 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
  • the shape of the opening 290 shown in FIGS. 12A and 12B is a truncated cone shape.
  • the opening 290 is circular in plan view, and trapezoidal in cross-section.
  • the area of the truncated cone-shaped upper base (for example, the opening provided in the conductor 240) is larger than the area of the truncated conical lower base (the upper surface of the conductor 120 exposed in the opening 290). small.
  • the maximum diameter of the opening 290 may be calculated based on the upper base surface of the truncated cone shape.
  • the channel length can be set by the thickness of the insulator 280 and the angle ⁇ 1 between the side surface of the insulator 280 and the top surface of the conductor 110 in the opening 290. Further, the length of the outer periphery of the oxide semiconductor 230 is determined, for example, at a region facing the conductor 240 or at a position half the thickness of the insulator 280. Note that the length of the circumference at any position of the opening 290 may be used as the channel width of the transistor 200, if necessary. For example, the length of the circumference at the bottom of the opening 290 may be set as the channel width, or the length of the circumference at the top of the opening 290 may be set as the channel width.
  • FIGS. 12A and 12B show a configuration in which the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 match
  • the present invention is not limited to this.
  • the side surface of the conductor 240 at the opening 290 and the side surface of the insulator 280 at the opening 290 may be discontinuous.
  • the slope of the side surface of the conductor 240 at the opening 290 and the slope of the side surface of the insulator 280 at the opening 290 may be different from each other.
  • it is preferable that the angle between the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 110 is smaller than the angle ⁇ 1.
  • the bottom of the conductor 260 located in the opening 290 has a flat area.
  • the maximum width of the opening 290 the maximum diameter when the opening 290 is circular in plan view
  • the thickness of the insulator 280 corresponding to the depth of the opening 290
  • the thickness of the oxide semiconductor 230 Depending on the film thickness and the film thickness of the insulator 250, the bottom of the conductor 260 located in the opening 290 may not have a flat region.
  • the bottom of the conductor 260 located in the opening 290 may have a needle-like shape.
  • FIG. 7A can be referred to for a plan view of the storage device shown in FIGS. 12C and 12D.
  • the term acicular refers to a shape that becomes thinner toward the tip (closer to the bottom of the conductor 260 located in the opening 290).
  • the needle-like tip may have an acute angle or may have a downwardly convex curved shape.
  • a shape having an acute angle at the tip may be referred to as a V-shape.
  • a region of the conductor 260 located in the opening 290 that faces the oxide semiconductor 230 with the insulator 250 interposed therebetween functions as a gate electrode. Therefore, the conductor 260 that fills the opening 290 and has a needle-like bottom shape may be referred to as a needle-shaped gate. Further, as shown in FIGS. 12A and 12B, even if the conductor 260 has a flat bottom region, it may be called a needle-shaped gate.
  • the opening 190 is provided so that the side wall of the opening 190 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this.
  • the sidewall of opening 190 may be tapered or reverse tapered.
  • the angle between the side surface of the insulator 180 in the opening 190 and the top surface of the conductor 110 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
  • the bottom of the conductor 120 located in the opening 190 has a flat region.
  • the maximum width of the opening 190 the maximum diameter when the opening 190 is circular in plan view
  • the film thickness of the insulator 180 corresponding to the depth of the opening 190
  • the film of the conductor 115 the film of the conductor 115
  • the bottom of the conductor 120 located in the opening 190 may not have a flat area.
  • the bottom of the conductor 120 located in the opening 190 may have a needle-like shape.
  • FIG. 7A can be referred to for a plan view of the storage device shown in FIGS. 12C and 12D.
  • the angle ⁇ 1 and the angle ⁇ 2 match or approximately match.
  • the angle ⁇ 1 and the angle ⁇ 2 may be different depending on the materials used for the insulator 180 and the insulator 280, the method for forming the opening 190 and the opening 290, and the like.
  • the angle ⁇ 1 may be larger than the angle ⁇ 2, or may be smaller than the angle ⁇ 2.
  • one of the angle ⁇ 1 and the angle ⁇ 2 may be 90 degrees or a value close to 90 degrees.
  • the side wall of the opening 290 may have an inverted tapered shape.
  • the inverted tapered shape is a shape having a side portion or an upper portion that protrudes from the bottom portion in a direction parallel to the substrate.
  • the shape of the opening 290 is a truncated cone shape.
  • the opening 290 is circular in plan view, and trapezoidal in cross-section.
  • the area of the truncated cone-shaped upper base (for example, the opening provided in the conductor 240) is larger than the area of the truncated conical lower base (the upper surface of the conductor 120 exposed in the opening 290). big. With such a structure, the area in which the oxide semiconductor 230 and the conductor 120 are in contact can be increased.
  • FIGS. 7B and 7C a portion of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240.
  • FIG. 7B shows a configuration in which the oxide semiconductor 230 is divided in the X direction
  • the present invention is not limited to this.
  • the oxide semiconductor 230 may be provided extending in the X direction.
  • the oxide semiconductor 230 is divided in the Y direction (see FIG. 13C).
  • FIG. 7C shows a configuration in which the side end portion of the oxide semiconductor 230 is located inside the side end portion of the conductor 240.
  • the present invention is not limited to this.
  • a structure may be adopted in which the side edges of the oxide semiconductor 230 and the side edges of the conductor 240 coincide in the Y direction.
  • a structure may be adopted in which the side end portion of the oxide semiconductor 230 is located outside the side end portion of the conductor 240.
  • the band gap of the metal oxide used as the oxide semiconductor 230 is preferably 2 eV or more, and more preferably 2.5 eV or more.
  • a metal oxide with a large band gap as the oxide semiconductor 230 off-state current of the transistor can be reduced.
  • a transistor with a small off-state current in a memory cell it is possible to retain stored contents for a long period of time. In other words, since no refresh operation is required or the frequency of refresh operations is extremely low, power consumption of the storage device can be sufficiently reduced.
  • the refresh operation frequency needs to be approximately 1 time/60 msec, but in the storage device of one embodiment of the present invention, the refresh operation frequency is approximately 1 time/10 sec, and 10 msec.
  • the refresh operation frequency can be set to be twice or more or 100 times or more. Note that with the storage device of one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and 100 sec or less, preferably once every 5 sec or more and 50 sec or less.
  • oxide semiconductor 230 a metal oxide described in the section [Metal oxide] described below can be used in a single layer or in a stacked layer.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the element M it is preferable to use gallium.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but also the atomic ratio of the sputtering target used for forming the metal oxide film. It may be.
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS Inductively Coupled Plasma-Mass Spectrometry
  • ICP-AES Inductively Coupled Plasma-Atomi c Emission Spectrometry
  • analysis may be performed by combining two or more of these methods. Note that for elements with low content rates, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • ALD method can be suitably used to form the metal oxide.
  • a sputtering method or a CVD method may be used to form the metal oxide.
  • the composition of the formed metal oxide may be different from the composition of the sputtering target.
  • the content of zinc in the metal oxide after formation may be reduced to about 50% compared to the sputtering target.
  • the oxide semiconductor 230 preferably has crystallinity.
  • oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), and polycrystalline oxide semiconductors. Examples include semiconductors, single crystal oxide semiconductors, and the like.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • nc-OS nanocrystalline oxide semiconductor
  • polycrystalline oxide semiconductors examples include semiconductors, single crystal oxide semiconductors, and the like.
  • the CAAC-OS preferably has a plurality of layered crystal regions, and the c-axis is oriented in the normal direction of the surface on which it is formed.
  • the oxide semiconductor 230 preferably has a layered crystal that is approximately parallel to the sidewall of the opening 290, particularly the sidewall of the insulator 280. With this structure, the layered crystal of the oxide semiconductor 230 is formed approximately parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (eg, oxygen vacancies).
  • heat treatment at a temperature that does not polycrystallize the metal oxide (e.g., 400°C or higher and 600°C or lower) allows CAAC-OS to have a more highly crystalline and dense structure. It can be done. In this way, by further increasing the density of the CAAC-OS, it is possible to further reduce the diffusion of impurities or oxygen in the CAAC-OS.
  • CAAC-OS it is difficult to confirm clear grain boundaries, so it can be said that reduction in electron mobility due to grain boundaries is less likely to occur. Therefore, the metal oxide with CAAC-OS has stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and have high reliability.
  • the oxide semiconductor 230 by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode can be suppressed. As a result, even if heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, so the transistor 200 is stable against high temperatures (so-called thermal budget) during the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the crystallinity of the oxide semiconductor 230 is analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). I can. Alternatively, analysis may be performed by combining two or more of these methods.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor 230 may have a stacked structure of a plurality of oxide layers having different chemical compositions. For example, a structure may be adopted in which a plurality of metal oxides selected from the above metal oxides are laminated as appropriate.
  • the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b over the oxide semiconductor 230a.
  • the conductivity of the material used for the oxide semiconductor 230a is preferably different from the conductivity of the material used for the oxide semiconductor 230b.
  • a material with higher conductivity than the oxide semiconductor 230b can be used for the oxide semiconductor 230a.
  • a material with high conductivity for the oxide semiconductor 230a that is in contact with the conductor 120 and the conductor 240 that function as a source electrode or a drain electrode the contact resistance between the oxide semiconductor 230 and the conductor 120 and the oxide semiconductor 230 can be reduced.
  • the contact resistance between the conductor 240 and the conductor 240 can be reduced, and a transistor with a large on-state current can be obtained.
  • the threshold voltage of the transistor shifts, and the drain current (hereinafter referred to as (also referred to as cut-off current) may become large.
  • the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b.
  • the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current is sometimes referred to as normally off.
  • the oxide semiconductor 230 in a stacked structure and using a material with higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a transistor that is normally off and has a large on-state current can be obtained. Therefore, it is possible to provide a storage device that has both low power consumption and high performance.
  • the carrier concentration of the oxide semiconductor 230a is preferably higher than that of the oxide semiconductor 230b.
  • the conductivity increases, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
  • the transistor can have a large on-current.
  • the carrier concentration of the oxide semiconductor 230b By lowering the carrier concentration of the oxide semiconductor 230b, the conductivity is lowered, and a normally-off transistor can be obtained.
  • a material having higher conductivity than the oxide semiconductor 230b is used for the oxide semiconductor 230a is shown here, one embodiment of the present invention is not limited to this.
  • a material having lower conductivity than the oxide semiconductor 230b may be used for the oxide semiconductor 230a.
  • the carrier concentration of the oxide semiconductor 230a can be lower than the carrier concentration of the oxide semiconductor 230b.
  • the band gap of the first metal oxide used for the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used for the oxide semiconductor 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b. Accordingly, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with high on-state current can be obtained. Further, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor 200 can be a normally-off transistor.
  • the band gap of the first metal oxide is smaller than the band gap of the second metal oxide
  • one embodiment of the present invention is not limited to this.
  • the first metal oxide may have a larger band gap than the second metal oxide.
  • the band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b.
  • the composition of the first metal oxide is different from the composition of the second metal oxide.
  • the band gap can be controlled.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide and the second metal oxide are In-M-Zn oxide
  • the first metal oxide may not contain the element M.
  • the first metal oxide used for the oxide semiconductor 230a can be an In-Zn oxide
  • the second metal oxide used for the oxide semiconductor 230b can be an In-M-Zn oxide.
  • the first metal oxide can be an In-Zn oxide
  • the second metal oxide can be an In-Ga-Zn oxide.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide
  • one embodiment of the present invention is not limited to this.
  • the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide. Note that it is sufficient that the first metal oxide and the second metal oxide have different compositions, and the content rates of elements other than element M may be different.
  • the thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • each layer (here, the oxide semiconductor 230a and the oxide semiconductor 230b) constituting the oxide semiconductor 230 is determined so that the thickness of the oxide semiconductor 230 falls within the above range.
  • the thickness of the oxide semiconductor 230a can be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 are within required ranges.
  • the thickness of the oxide semiconductor 230b can be determined so that the threshold voltage of the transistor is within a desired range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.
  • FIGS. 14A and 14B show a structure in which the oxide semiconductor 230 has a two-layer stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b, the present invention is not limited to this.
  • the oxide semiconductor 230 may have a stacked structure of three or more layers.
  • the on-state current of the transistor 200 can be increased, and a highly reliable transistor structure with little variation can be achieved.
  • the insulators described in the section [Insulator] described later can be used in a single layer or in a laminated manner.
  • silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 250 a material having a high dielectric constant described in the section [Insulator] described later, a so-called high-k material, may be used.
  • hafnium oxide or aluminum oxide may be used.
  • the thickness of the insulator 250 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is preferable that the insulator 250 has a region having the thickness described above at least in part.
  • the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. This can suppress impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
  • a portion of the insulator 250 is located outside the opening 290, that is, above the conductor 240 and the insulator 280. At this time, it is preferable that the insulator 250 cover the side edges of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented. Further, it is preferable that the insulator 250 covers the side end portions of the conductor 240. This can prevent short-circuiting between the conductor 260 and the conductor 240.
  • the insulator 250 is shown as a single layer in FIGS. 7B and 7C, the present invention is not limited to this.
  • the insulator 250 may have a laminated structure.
  • the insulator 250 may have a laminated structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. .
  • the insulator 250b it is preferable to use a material with a low dielectric constant described in the section [Insulator] described later.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 250b includes at least oxygen and silicon. With such a configuration, the parasitic capacitance generated between the conductor 260 and the conductor 240 can be reduced. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250b is reduced.
  • the insulator 250a it is preferable to use an insulator having barrier properties against oxygen described in the section [Insulator] described later.
  • the insulator 250a has a region in contact with the oxide semiconductor 230. Since the insulator 250a has barrier properties against oxygen, desorption of oxygen from the oxide semiconductor 230 can be suppressed when heat treatment or the like is performed. Therefore, formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. Thereby, the electrical characteristics of the transistor 200 can be improved and reliability can be improved.
  • aluminum oxide may be used as the insulator 250a. In this case, the insulator 250a contains at least oxygen and aluminum.
  • the insulator 250c it is preferable to use an insulator having barrier properties against hydrogen as described in the section [Insulator] described later. Thereby, diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230 can be suppressed. Silicon nitride has high hydrogen barrier properties and is therefore suitable as the insulator 250c. In this case, the insulator 250c includes at least nitrogen and silicon.
  • the insulator 250c may further have barrier properties against oxygen. Insulator 250c is provided between insulator 250b and conductor 260. Therefore, oxygen contained in the insulator 250b can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Further, a decrease in the amount of oxygen supplied to the region 230i can be suppressed.
  • an insulator may be provided between the insulator 250b and the insulator 250c.
  • the insulator it is preferable to use an insulator having a function of capturing or fixing hydrogen as described in the section [Insulator] described below.
  • the insulator hydrogen contained in the oxide semiconductor 230 can be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • hafnium oxide may be used as the insulator.
  • the insulator contains at least oxygen and hafnium.
  • the insulator may have an amorphous structure.
  • the film thicknesses of the insulators 250a to 250c are preferably thin, and preferably within the above range.
  • the film thicknesses of the insulator 250a, the insulator 250b, the insulator having a function of capturing or fixing hydrogen, and the insulator 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • FIGS. 14A and 14B show a configuration in which the insulator 250 has a three-layer stacked structure of insulators 250a to 250c, the present invention is not limited to this.
  • the insulator 250 may have a laminated structure of two layers, or four or more layers. At this time, each layer included in the insulator 250 may be appropriately selected from the insulators 250a to 250c and an insulator having a function of capturing or fixing hydrogen.
  • the conductor 260 the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a highly conductive material such as tungsten can be used as the conductor 260.
  • the conductor 260 it is preferable to use a conductive material that is not easily oxidized, a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • the conductive material include a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride), a conductive material containing oxygen (for example, ruthenium oxide, etc.), and the like. Thereby, it is possible to suppress the conductivity of the conductor 260 from decreasing.
  • the conductor 260 may have a laminated structure.
  • the conductor 260 may have a stacked structure of a conductor 260a and a conductor 260b on the conductor 260a.
  • titanium nitride may be used as the conductor 260a
  • tungsten may be used as the conductor 260b.
  • FIGS. 14A and 14B show a configuration in which the conductor 260 has a two-layer stacked structure of a conductor 260a and a conductor 260b, the present invention is not limited to this.
  • the conductor 260 may have a laminated structure of three or more layers.
  • the conductor 260 is provided to fill the opening 290 in FIGS. 7B and 7C, the present invention is not limited thereto.
  • a recess reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a portion of the recess may be located in the opening 290.
  • the recess may be filled with an inorganic insulating material or the like.
  • a portion of the conductor 260 is located outside the opening 290, that is, above the conductor 240 and the insulator 280.
  • the side end portion of the conductor 260 is preferably located inside the side end portion of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented.
  • the side end portion of the conductor 260 may coincide with the side end portion of the oxide semiconductor 230, or may be located outside the side end portion of the oxide semiconductor 230.
  • the conductor 120 is provided as described in the section [Capacitive element 100].
  • FIGS. 7B and 7C show a configuration in which the upper surface of the conductor 120 is flat
  • the present invention is not limited to this.
  • a configuration may be adopted in which a recessed portion overlapping the opening 290 is formed on the upper surface of the conductor 120.
  • the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a highly conductive material such as tungsten can be used as the conductor 240.
  • the conductor 240 is also preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion.
  • a conductive material that is not easily oxidized for example, titanium nitride or tantalum nitride can be used. With such a structure, excessive oxidation of the conductor 240 by the oxide semiconductor 230 can be suppressed.
  • a structure in which tungsten is laminated on titanium nitride may be used. By layering tungsten in this way, the conductivity of the conductor 240 can be improved and it can function sufficiently as the wiring BL.
  • the conductor 240 has a structure in which a first conductor and a second conductor are laminated
  • the first conductor is formed using a conductive material with high conductivity
  • the second conductor is formed using a conductive material with high conductivity.
  • the conductor may be formed using a conductive material containing oxygen.
  • a conductive material containing oxygen as the second conductor of the conductor 240 in contact with the insulator 250, it is possible to suppress oxygen in the insulator 250 from diffusing into the first conductor of the conductor 240.
  • tungsten may be used as the first conductor of the conductor 240
  • indium tin oxide added with silicon may be used as the second conductor of the conductor 240.
  • the oxide semiconductor 230 and the conductor 120 come into contact with each other, a metal compound or an oxygen vacancy is formed, and the resistance of the region 230na of the oxide semiconductor 230 is reduced.
  • the contact resistance between the oxide semiconductor 230 and the conductor 120 can be reduced.
  • the oxide semiconductor 230 and the conductor 240 are in contact with each other, the resistance of the region 230nb of the oxide semiconductor 230 is reduced. Therefore, contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant which is described in the section [Insulator] described later, can be used in a single layer or a laminated form. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the concentration of impurities such as water and hydrogen in the insulator 140 and the insulator 280 is reduced. This can suppress impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
  • the insulator 280 disposed near the channel formation region it is preferable to use an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen).
  • excess oxygen an insulator containing oxygen that is released by heating
  • the insulator 280 an insulator having a function of capturing hydrogen or fixing hydrogen, which is described in the section [Insulator] described later, may be used. With such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed, and the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • the insulator 280 magnesium oxide, aluminum oxide, or the like can be used.
  • the insulator 280 is shown as a single layer in FIGS. 7B and 7C, the present invention is not limited to this.
  • the insulator 280 may have a laminated structure.
  • the insulator 280 may have a laminated structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b. .
  • the insulator 280b preferably has a region containing more oxygen than at least one of the insulators 280a and 280c. In particular, it is preferable that the insulator 280b has a region with a higher oxygen content than each of the insulators 280a and 280c. By increasing the oxygen content of the insulator 280b, an i-type region can be easily formed in a region of the oxide semiconductor 230 that is in contact with the insulator 280b and in the vicinity thereof.
  • the insulator 280b releases oxygen due to heat applied during the manufacturing process of the transistor 200, so that oxygen can be supplied to the oxide semiconductor 230.
  • oxygen vacancies and V O H in the oxide semiconductor 230 can be reduced, and good electrical characteristics can be achieved. A highly reliable transistor can be obtained.
  • oxygen can be supplied to the insulator 280b by performing heat treatment in an atmosphere containing oxygen or plasma treatment in an atmosphere containing oxygen.
  • oxygen may be supplied by forming an oxide film on the upper surface of the insulator 280b in an oxygen atmosphere by a sputtering method. After that, the oxide film may be removed.
  • the insulator 280b is preferably formed by a film forming method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a film forming method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • oxygen vacancies in the channel formation region and V OH have a particularly large influence on the electrical characteristics and reliability.
  • oxygen vacancies in the channel formation region and V OH have a particularly large influence on the electrical characteristics and reliability.
  • the insulator 280a and the insulator 280c it is preferable to use an insulator having barrier properties against oxygen, which is described in the section [Insulator] described later.
  • oxygen contained in the insulator 280b can be prevented from diffusing to the substrate side via the insulator 280a and to the insulator 250 side via the insulator 280c due to heating.
  • oxygen contained in the insulator 280b can be confined. Thereby, oxygen can be effectively supplied to the oxide semiconductor 230.
  • the conductor 120 and the conductor 240 may be oxidized by oxygen contained in the insulator 280b, resulting in increased resistance.
  • the insulator 280a between the insulator 280b and the conductor 120 it is possible to prevent the conductor 120 from being oxidized and increasing its resistance.
  • the insulator 280c between the insulator 280b and the conductor 240 it is possible to suppress the conductor 240 from being oxidized and increasing its resistance.
  • the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, and oxygen vacancies in the oxide semiconductor 230 can be reduced.
  • the amount of oxygen supplied to the region of the oxide semiconductor 230 in contact with the insulator 280a and the region in contact with the insulator 280c is smaller than that in the region in contact with the insulator 280b. Therefore, a region of the oxide semiconductor 230 in contact with the insulator 280a and a region in contact with the insulator 280c may have low resistance. That is, by adjusting the film thickness of the insulator 280a, the range of the region 230na that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb functioning as the other of the source region and the drain region can be controlled.
  • the source region and the drain region can be controlled by the film thicknesses of the insulator 280a and the insulator 280c, so the film thicknesses of the insulator 280a and the insulator 280c can be adjusted according to the characteristics required for the transistor 200. Can be set as appropriate.
  • the thickness of the insulator 280c and the thickness of the insulator 280a may be approximately the same.
  • the thickness of the insulator 280c may be smaller than the thickness of the insulator 280a.
  • FIGS. 15C and 15D show a configuration in which an insulator 280c is provided on a flattened insulator 280b
  • the present invention is not limited to this.
  • the insulator 280c may be formed without performing planarization treatment on the insulator 280b. By not performing planarization treatment, manufacturing costs can be lowered and production yields can be increased. Further, the insulator 280a, the insulator 280b, and the insulator 280c can be continuously formed without being exposed to the atmospheric environment.
  • the film By forming the film without exposing it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 280a to 280c, and it is possible to prevent impurities or moisture from adhering to the insulators 280a to 280c.
  • the vicinity of the interface between the insulator 280b and the insulator 280c can be kept clean.
  • an insulator having barrier properties against hydrogen as described in the "Insulator” section below, respectively, for the insulator 280a and the insulator 280c.
  • hydrogen can be suppressed from diffusing into the oxide semiconductor 230 from outside the transistor through the insulator 280a or the insulator 280c.
  • a silicon nitride film and a silicon nitride oxide film are suitable for the insulator 280a and the insulator 280c because they release little impurity (for example, water and hydrogen) from themselves and are difficult for oxygen and hydrogen to pass through. It can be used for.
  • the insulator 280a and the insulator 280c may be made of the same material or different materials.
  • the insulator 280a it is preferable to use an insulator having a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later.
  • Such a structure suppresses hydrogen from diffusing into the oxide semiconductor 230 from below the insulator 280a, and further captures or fixes hydrogen in the oxide semiconductor 230 to reduce the hydrogen concentration in the oxide semiconductor 230. Can be reduced. Further, it is possible to suppress hydrogen from diffusing into the insulator 130 from above the insulator 280a, and further capture or fix hydrogen in the insulator 130, thereby reducing the hydrogen concentration in the insulator 130.
  • the insulator 280a magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 280a.
  • the thickness of the insulator 280a is preferably smaller than the thickness of the insulator 280b. Further, the thickness of the insulator 280c is preferably smaller than the thickness of the insulator 280b.
  • the thickness of the insulator 280a and the insulator 280c is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and even more preferably 3 nm or more and 5 nm or less.
  • the thickness of the insulator 280b is preferably 3 nm or more and 30 nm or less, more preferably 5 nm or more and 20 nm or less, and more preferably 7 nm or more and 15 nm or less.
  • each of the insulator 280a and the insulator 280c includes at least silicon and nitrogen.
  • the insulator 280b includes at least silicon and oxygen.
  • FIGS. 16A and 16B illustrate a structure in which the insulator 280 has a three-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulator 280 may have a laminated structure of two layers or four or more layers.
  • the insulator 283 it is preferable to use an insulator having barrier properties against hydrogen, which is described in the section [Insulator] described later. Thereby, hydrogen can be suppressed from diffusing into the oxide semiconductor 230 from outside the transistor through the insulator 250.
  • a silicon nitride film and a silicon nitride oxide film are suitable for use as the insulator 283 because they release little impurity (for example, water and hydrogen) from themselves and are difficult for oxygen and hydrogen to pass through. can.
  • the insulator 283 it is preferable to use an insulator having a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With this structure, hydrogen is prevented from diffusing into the oxide semiconductor 230 from above the insulator 283, and hydrogen in the oxide semiconductor 230 is captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor 230. Can be reduced.
  • magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 283.
  • an insulator 283 (or an insulator having the same function or material as the insulator 283) may be formed on the side and bottom surfaces of the transistor 200, and the transistor 200 may be surrounded by the insulator 283.
  • an insulator 283 may be formed on the top, side, and bottom surfaces of the transistor 200 and the capacitor 100, and the transistor 200 and the capacitor 100 may be surrounded by the insulator 283.
  • FIGS. 7B and 7C show a structure in which the upper surface of the conductor 120 and the lower surface of the oxide semiconductor 230 are in contact with each other, the present invention is not limited to this.
  • a conductor may be provided between the conductor 120 and the oxide semiconductor 230.
  • a conductor 125 may be provided between the conductor 120 and the oxide semiconductor 230.
  • the conductor 125 it is preferable to use an oxygen-containing conductive material described in the "Conductor" section below.
  • a conductive material containing oxygen as the conductor 125, conductivity can be maintained even if the conductor 125 absorbs oxygen. Furthermore, diffusion of oxygen in the oxide semiconductor 230 into the conductor 120 can be suppressed.
  • the conductor 125 for example, indium tin oxide, silicon-added indium tin oxide, indium zinc oxide, or the like can be used in a single layer or in a stacked layer.
  • FIGS. 7B and 7C show a configuration in which the conductor 240 is provided on an insulator 280. Further, a configuration is shown in which a region of the insulator 250 that does not overlap with the conductor 240 has a region in contact with the upper surface of the insulator 280. Note that the present invention is not limited to this.
  • the conductor 240 may be embedded in an insulator 281.
  • the height of the top surface of the conductor 240 preferably matches the height of the top surface of the insulator 281.
  • FIG. 17A is a plan view of the storage device shown in FIGS. 17B and 17C.
  • the insulator 281 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant described in the section [Insulator] described later can be used in a single layer or a laminated form.
  • an insulating substrate for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulator region inside the semiconductor substrate described above such as an SOI (Silicon On Insulator) substrate.
  • the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • substrates containing metal nitrides, substrates containing metal oxides, and the like there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a semiconductor substrate in which a conductor or an insulator is provided, and a conductor substrate in which a semiconductor or an insulator is provided.
  • these substrates provided with elements may be used.
  • Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.
  • high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, and oxides containing aluminum and hafnium.
  • examples include nitride, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, and nitride containing silicon and hafnium.
  • materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and resins such as acrylic. Can be mentioned.
  • inorganic insulating materials having a low dielectric constant include, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen. Further, for example, silicon oxide having pores may be used. Note that these silicon oxides may contain nitrogen. Further, silicon oxide may be formed using, for example, organic silane such as tetraethoxysilane (TEOS).
  • TEOS tetraethoxysilane
  • insulators having the function of suppressing permeation of impurities and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, Insulators including neodymium, hafnium, or tantalum can be used in single layers or in stacks.
  • insulators that have the function of suppressing the permeation of impurities and oxygen include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc.
  • Metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • an insulator such as a gate insulator that is in contact with the semiconductor or an insulator provided near the semiconductor layer is preferably an insulator that has a region containing excess oxygen.
  • oxygen vacancies in the semiconductor layer can be reduced by providing a structure in which an insulator having a region containing excess oxygen is in contact with the semiconductor layer or in the vicinity of the semiconductor layer.
  • Examples of insulators that can easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
  • Insulators with barrier properties against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, and silicon nitride. , silicon nitride oxide, and the like.
  • oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulators having barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.
  • examples of the insulator having the function of capturing or fixing hydrogen include an oxide containing magnesium, or an oxide containing one or both of aluminum and hafnium. Moreover, it is more preferable that these oxides have an amorphous structure. In an oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may capture or fix hydrogen. Note that these metal oxides preferably have an amorphous structure, but a crystalline region may be formed in part.
  • barrier insulating film refers to an insulating film having barrier properties.
  • barrier property refers to the property that the corresponding substance is difficult to diffuse (also referred to as the property that the corresponding substance is difficult to permeate, the property that the corresponding substance has low permeability, or the ability to suppress the diffusion of the corresponding substance). do.
  • the function of capturing or fixing a corresponding substance can be referred to as barrier property.
  • hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities described as corresponding substances refer to impurities in the channel forming region or semiconductor layer, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, oxidation Refers to at least one of nitrogen molecules ( N2O , NO, NO2, etc.), copper atoms, etc.
  • oxygen refers to at least one of, for example, an oxygen atom or an oxygen molecule.
  • the barrier property against oxygen refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is difficult to diffuse.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal elements as a component, an alloy containing a combination of the above-mentioned metal elements, or the like. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used.
  • tantalum nitride titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. It is preferable. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • nitrides containing tantalum nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, etc.
  • a conductive material that is not easily oxidized, a conductive material that has a function of suppressing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen is preferable.
  • conductive materials containing oxygen indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium Examples include zinc oxide and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.
  • conductive materials mainly composed of tungsten, copper, or aluminum are preferable because they have high conductivity.
  • a plurality of conductors made of the above materials may be stacked and used.
  • a layered structure may be used in which a material containing the metal element described above and a conductive material containing oxygen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • the conductor that functions as the gate electrode has a stacked structure that combines a material containing the aforementioned metal element and a conductive material containing oxygen. It is preferable. In this case, it is preferable to provide a conductive material containing oxygen on the channel forming region side. By providing a conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as the conductor functioning as the gate electrode.
  • a conductive material containing the aforementioned metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • one or more of the added indium tin oxides may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal oxides may have lattice defects.
  • Lattice defects include atomic vacancies, point defects such as foreign atoms, line defects such as dislocations, planar defects such as crystal grain boundaries, and volume defects such as voids.
  • factors for the generation of lattice defects include a deviation in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms), impurities, and the like.
  • the metal oxide used for the semiconductor layer of the transistor preferably has few lattice defects.
  • the types of lattice defects that are likely to exist in a metal oxide and the amount of lattice defects that exist vary depending on the structure of the metal oxide, the method for forming a metal oxide film, and the like.
  • the structures of metal oxides are divided into single crystal structures and other structures (non-single crystal structures).
  • non-single crystal structures include a CAAC structure, a polycrystalline structure, a nc structure, an amorphous-like (a-like) structure, and an amorphous structure.
  • the a-like structure has a structure between an nc structure and an amorphous structure.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have cavities or low density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Further, a metal oxide having an a-like structure has a higher hydrogen concentration than a metal oxide having an nc structure and a metal oxide having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a highly crystalline metal oxide for the semiconductor layer of the transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using the metal oxide in a transistor, a transistor with good electrical characteristics can be realized. Furthermore, a highly reliable transistor can be realized.
  • a metal oxide that increases the on-state current of the transistor for the channel formation region of the transistor.
  • the crystal has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). At this time, the c-axis of the crystal is oriented in the direction in which a plurality of layers are stacked.
  • metal oxides having such crystals include single crystal oxide semiconductors, CAAC-OS (c-axis aligned crystalline oxide semiconductors), and the like.
  • the c-axis of the crystal is oriented in the normal direction to the surface on which the metal oxide is formed or the surface of the film.
  • the plurality of layers are arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. That is, the multiple layers extend in the channel length direction.
  • the three-layer crystal structure described above has the following structure.
  • the first layer has an octahedral atomic coordination structure of oxygen in which the metal of the first layer is located at the center.
  • the second layer has a trigonal bipyramidal or tetrahedral atomic coordination structure of oxygen in which the metal of the second layer exists at the center.
  • the third layer has a trigonal bipyramidal or tetrahedral atomic coordination structure of oxygen in which the metal of the third layer exists at the center.
  • Examples of the crystal structure of the above crystal include a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first to third layers is preferably composed of one metal element or a plurality of metal elements having the same valence and oxygen.
  • the valence of one or more metal elements forming the first layer is the same as the valence of one or more metal elements forming the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of one or more metal elements forming the first layer is different from the valence of one or more metal elements forming the third layer.
  • the crystallinity of the metal oxide can be improved and the mobility of the metal oxide can be increased. Therefore, by using the metal oxide in a channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide has two or three selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium.
  • the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony.
  • the element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable.
  • the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements” described in this specification and the like may include semimetal elements.
  • Examples of the metal oxide of one embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), and indium Gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide) aluminum zinc oxide (also written as Al-Zn oxide, also written as AZO), indium aluminum zinc oxide (also written as In-Al-Zn oxide, IAZO), indium tin zinc oxide (In- Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In- Ga-Sn-Zn oxide (also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may include one or more metal elements having a large periodic number in the periodic table of elements instead of indium.
  • the metal oxide may contain one or more metal elements having a large periodic number in the periodic table of elements. The greater the overlap between the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large periodic number in the periodic table of elements, it may be possible to increase the field effect mobility of the transistor. Examples of metal elements with large period numbers in the periodic table of elements include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal element examples include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more types of nonmetallic elements.
  • the metal oxide contains a nonmetal element, the field effect mobility of the transistor can be increased in some cases.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. . Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • an In-Ga-Zn oxide may be described as an example of a metal oxide.
  • a metal oxide having the above layered crystal structure In order to form a metal oxide having the above layered crystal structure, it is preferable to deposit atoms one layer at a time. Using the ALD method, it is easy to form a metal oxide having the above-described layered crystal structure.
  • Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.
  • a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy
  • PEALD plasma enhanced ALD
  • the ALD method can deposit atoms one layer at a time, it is possible to form extremely thin films, to form structures with high aspect ratios, to form films with few defects such as pinholes, and to improve coverage. It has advantages such as being able to form an excellent film and being able to form a film at a low temperature. Further, the PEALD method may be preferable because it can form a film at a lower temperature by using plasma. Note that some precursors used in the ALD method include elements such as carbon or chlorine. For this reason, a film formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that these elements can be quantified using XPS or SIMS.
  • the ALD method As a method for forming metal oxide films, it is possible to perform ALD without applying either or both of the conditions of high substrate temperature during film formation and the implementation of impurity removal treatment.
  • the amount of carbon and chlorine contained in the film can be reduced compared to when using the method.
  • impurity removal treatment intermittently in an atmosphere containing oxygen during the formation of a metal oxide film. Further, after forming the metal oxide film, it is preferable to perform impurity removal treatment in an atmosphere containing oxygen. Impurities in the film can be removed by performing impurity removal treatment during and/or after the metal oxide film is formed. This can suppress impurities (hydrogen, carbon, nitrogen, etc.) contained in raw materials such as precursors from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. Further, the crystallinity of the metal oxide can be improved.
  • Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment.
  • the temperature of the substrate should be at least room temperature (for example, 25 degrees Celsius), at least 100 degrees Celsius, at least 200 degrees Celsius, at least 300 degrees Celsius, or at least 400 degrees Celsius, and at most 500 degrees Celsius, respectively. , or 450°C or less. Further, the temperature of the heat treatment is preferably 100°C or higher, 200°C or higher, 300°C or higher, or 400°C or higher, and 500°C or lower, or 450°C or lower.
  • the temperature during impurity removal treatment to a temperature below the maximum temperature in the manufacturing process of transistors or semiconductor devices, the content of impurities in the metal oxide can be reduced without reducing productivity. ,preferable.
  • the productivity of the semiconductor device or memory device can be increased.
  • microwave processing refers to processing using, for example, a device having a power source that generates high-density plasma using microwaves.
  • microwave refers to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • the microwave processing it is preferable to use, for example, a microwave processing apparatus having a power source that generates high-density plasma using microwaves.
  • the frequency of the microwave processing device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be set to 2.45 GHz, for example.
  • the power of the power source for applying microwaves of the microwave processing device is preferably 1000 W or more and 10000 W or less, and preferably 2000 W or more and 5000 W or less.
  • the microwave processing apparatus may have a power source for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the film.
  • the microwave treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 300 Pa or more and 700 Pa or less. Further, the treatment temperature is preferably at least room temperature (25°C) and at most 750°C, more preferably at least 300°C and at most 500°C, and can be at least 400°C and at most 450°C.
  • heat treatment may be performed continuously without exposing to the outside air.
  • the temperature of the heat treatment is, for example, preferably 100°C or more and 750°C or less, more preferably 300°C or more and 500°C or less, and even more preferably 400°C or more and 450°C or less.
  • Microwave treatment can be performed using oxygen gas and argon gas, for example.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than or equal to 100%.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is greater than 0% and less than or equal to 50%.
  • the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 10% or more and 40% or less. More preferably, the oxygen flow rate ratio (O 2 /(O 2 +Ar)) is 10% or more and 30% or less.
  • the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas.
  • the oxygen gas content be about 20%.
  • the heat treatment may be performed under reduced pressure.
  • heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • the heat treatment may be performed in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less).
  • impurities such as hydrogen and carbon contained in the metal oxide can be removed.
  • carbon in a metal oxide can be released as CO2 and CO
  • hydrogen in a metal oxide can be released as H2O .
  • metal atoms and oxygen atoms are rearranged, and crystallinity can be improved. Therefore, a highly crystalline metal oxide having a layered crystal structure, particularly a metal oxide having the CAAC structure described above, can be formed.
  • the ALD method is a film forming method in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as sputtering or CVD, which have a high film formation rate.
  • a method may be used in which a first metal oxide is formed into a film using a sputtering method, and a second metal oxide is formed into a film using an ALD method on the first metal oxide.
  • the second metal oxide may grow crystals using the crystal part as a nucleus.
  • the composition of the resulting film can be controlled by the amount of raw material gas introduced.
  • the amount of raw material gas introduced it is possible to form a film of any composition by adjusting the amount of raw material gas introduced, the number of times it is introduced (also called the number of pulses), the time required for one pulse (also called pulse time), etc. can.
  • the ALD method by changing the raw material gas during film formation, it is possible to form a film whose composition changes continuously.
  • a transistor with high field-effect mobility can be achieved. Furthermore, a highly reliable transistor can be realized. Further, it is possible to realize miniaturized or highly integrated transistors. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.
  • the carrier concentration in the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ It is 1013 cm -3 or less, more preferably 1x1011 cm -3 or less, even more preferably less than 1x1010 cm- 3 , and 1x10-9 cm- 3 or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, it is preferable to lower the impurity concentration in the oxide semiconductor film and lower the defect level density.
  • low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic.
  • an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.
  • the impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. It is.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • Si transistors As transistors become smaller, a short channel effect (also referred to as SCE) occurs. Therefore, it is difficult to miniaturize Si transistors.
  • SCE short channel effect
  • silicon has a small band gap.
  • an OS transistor uses an oxide semiconductor, which is a semiconductor material with a large band gap, short channel effects can be suppressed. In other words, an OS transistor is a transistor that has no short channel effect or has very little short channel effect.
  • the short channel effect is a deterioration in electrical characteristics that becomes apparent as transistors become smaller (reduction in channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in a subthreshold region that causes a drain current to change by one order of magnitude with a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • the characteristic length is an index of the bendability of the potential in the channel forming region. The smaller the characteristic length, the more steeply the potential rises, so it can be said to be resistant to short channel effects.
  • the OS transistor is an accumulation type transistor, and the Si transistor is an inversion type transistor. Therefore, compared to a Si transistor, an OS transistor has a smaller characteristic length between the source region and the channel forming region and a smaller characteristic length between the drain region and the channel forming region. Therefore, OS transistors are more resistant to short channel effects than Si transistors. That is, when it is desired to manufacture a transistor with a short channel length, an OS transistor is more suitable than a Si transistor.
  • the carrier concentration of the oxide semiconductor is lowered until the channel formation region becomes i-type or substantially i-type, conduction in the channel formation region decreases due to the conduction-band-lowering (CBL) effect in short-channel transistors. Since the lower end of the conduction band is lowered, the energy difference at the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to 0.1 eV or more and 0.2 eV or less.
  • the OS transistor has an n + /n- / n + accumulation type junction-less transistor structure, in which the channel forming region becomes an n - type region and the source and drain regions become n + -type regions, or , n + /n ⁇ /n + storage type non-junction transistor structure.
  • the OS transistor By making the OS transistor have the above structure, it is possible to have good electrical characteristics even if the memory device is miniaturized or highly integrated. For example, even if the channel length or gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and is 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. Obtainable. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation.
  • the high frequency characteristics of the transistor can be improved.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to 50 GHz or more, preferably 100 GHz or more, more preferably 150 GHz or more, for example in a room temperature environment.
  • OS transistors have excellent effects compared to Si transistors, such as a smaller off-state current and the ability to manufacture a transistor with a short channel length.
  • the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms /cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 3 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 1 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, still more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , even more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor 230 can be referred to as a semiconductor layer including a channel formation region of a transistor.
  • Semiconductor materials that can be used for the semiconductor layer are not limited to the metal oxides mentioned above.
  • a semiconductor material having a band gap semiconductor material that is not a zero-gap semiconductor may be used as the semiconductor.
  • a layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of single element semiconductors that can be used as semiconductor materials include silicon and germanium.
  • Examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • Examples of polycrystalline silicon include low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • Boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • Boron arsenide that can be used in the semiconductor layer preferably contains crystals with a cubic crystal structure.
  • Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride as a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • a chalcogenide is a compound containing chalcogen.
  • chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • examples of chalcogenides include transition metal chalcogenides, group 13 chalcogenides, and the like.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as a semiconductor layer include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), Tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically Examples include HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ).
  • a in each figure shows a plan view.
  • B in each figure is a sectional view corresponding to the portion indicated by the dashed line A1-A2 in A in each figure.
  • C in each figure is a sectional view corresponding to the portion indicated by the dashed line A3-A4 in A in each figure.
  • some elements are omitted for clarity of the figure.
  • an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is used by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the film can be formed using a method such as the following.
  • sputtering methods include an RF sputtering method using a high frequency power source as a sputtering power source, a DC sputtering method using a DC power source, and a pulsed DC sputtering method in which the voltage applied to the electrodes is changed in a pulsed manner.
  • the RF sputtering method is mainly used when forming an insulating film
  • the DC sputtering method is mainly used when forming a metal conductive film.
  • the pulsed DC sputtering method is mainly used when forming a film of a compound such as an oxide, nitride, or carbide by a reactive sputtering method.
  • the CVD method can be classified into a plasma CVD (PECVD) method that uses plasma, a thermal CVD (TCVD) method that uses heat, a photo CVD (Photo CVD) method that uses light, and the like. Furthermore, depending on the raw material gas used, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method.
  • PECVD plasma CVD
  • TCVD thermal CVD
  • Photo CVD Photo CVD
  • MCVD metal CVD
  • MOCVD metal organic CVD
  • the plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a memory device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the memory device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of memory devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.
  • the ALD method a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.
  • the CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.
  • a film having an arbitrary composition can be formed by changing the flow rate ratio of source gases.
  • the flow rate ratio of source gases by changing the flow rate ratio of source gases during film formation, it is possible to form a film whose composition changes continuously.
  • the time required for film formation is reduced because it does not require time for transport or pressure adjustment. can do. Therefore, it may be possible to increase the productivity of the storage device.
  • a film having an arbitrary composition can be formed by simultaneously introducing a plurality of different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles for each precursor.
  • a substrate (not shown) is prepared, and an insulator 140 is formed on the substrate (FIGS. 18A to 18C).
  • the insulating material described above can be used as appropriate for the insulator 140.
  • the insulator 140 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductor 110 is formed on the insulator 140.
  • the conductive material described above can be used as appropriate for the conductor 110.
  • the conductor 110 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a stacked film in which tungsten and titanium nitride are deposited in this order can be formed using a CVD method.
  • the conductor 110 may be processed to have a shape extending in the X direction or the Y direction.
  • the conductor 110 can be processed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for microfabrication. By performing this processing, the side end portions of the conductor 110 are covered with an insulator 130 that will be formed later.
  • the resist is first exposed to light through a mask.
  • a resist mask is formed by removing or leaving the exposed area using a developer.
  • a conductor, semiconductor, insulator, or the like can be processed into a desired shape.
  • a resist mask is formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the resist mask can be removed by performing dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment.
  • an insulator 180 is formed on the conductor 110 (FIGS. 18A to 18C).
  • the insulating material described above can be used as appropriate for the insulator 180.
  • the insulator 180 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film is formed using a sputtering method.
  • the insulator 180 is preferably subjected to CMP (Chemical Mechanical Polishing) treatment after film formation to flatten the upper surface. Note that there are cases where it is not necessary to perform CMP processing. At this time, the upper surface of the insulator 180 has an upwardly convex curved shape. By not performing planarization treatment, manufacturing costs can be lowered and production yields can be increased.
  • the film thickness of the insulator 180 corresponds to the capacitance of the capacitive element 100
  • the film thickness of the insulator 180 can be appropriately set according to the design value of the capacitance of the capacitive element 100.
  • the hydrogen concentration in the insulator 180 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas.
  • the opening 190 can be formed using a lithography method.
  • the shape of the opening 190 is circular in plan view, it is not limited to this.
  • the shape of the opening 190 may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners when viewed from above.
  • the opening 190 is preferably formed using the above-mentioned ⁇ Method for Forming an Opening>. Thereby, it is possible to achieve miniaturization or high integration of the memory device.
  • the sidewall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
  • the side wall of the opening 190 may have a tapered shape. By tapering the side wall of the opening 190, the coverage of a conductive film, which will be described later as a conductor 115, can be improved, and defects such as holes can be reduced.
  • the maximum width (maximum diameter when the opening 190 is circular in plan view) of the opening 190 is preferably minute.
  • the maximum width of the opening 190 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and preferably 1 nm or more, or 5 nm or more.
  • the opening 190 has a large aspect ratio, it is preferable to process a portion of the insulator 180 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing.
  • a conductive film that will become the conductor 115 is formed in contact with the bottom and sidewalls of the opening 190 and at least a portion of the top surface of the insulator 180.
  • a conductor that can be used as the conductor 115 described above can be used as appropriate.
  • the conductive film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductive film is preferably formed in contact with the bottom and sidewalls of the opening 190 having a large aspect ratio.
  • a film forming method with good coverage it is preferable to use a CVD method, an ALD method, or the like.
  • a titanium nitride film is formed as the conductive film using a CVD method.
  • the conductive film that will become the conductor 115 is processed using a lithography method to form the conductor 115 (FIGS. 20A to 20C). As a result, a portion of the conductor 115 is formed in the opening 190. Further, the conductor 115 is in contact with a portion of the side surface and the top surface of the insulator 180.
  • an insulator 130 is formed over the conductor 115 and the insulator 180 (FIGS. 21A to 21C).
  • the above-mentioned high-k material or a material that can have ferroelectricity can be used as appropriate.
  • the insulator 130 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a laminated film of zirconium oxide, aluminum oxide, and zirconium oxide is formed in this order using an ALD method.
  • a conductive film 120A is formed on the insulator 130 (FIGS. 21A to 21C).
  • the above-mentioned conductive material can be used for the conductive film 120A.
  • the conductive film 120A can be formed by sputtering, This can be carried out using a CVD method, an MBE method, a PLD method, an ALD method, etc. as appropriate.
  • a stacked film in which titanium nitride and tantalum nitride are deposited in this order is formed using a CVD method.
  • a laminated film in which titanium nitride and tungsten are deposited in this order is formed using a CVD method.
  • the conductive film 120A is processed to form the conductor 120 (FIGS. 22A to 22C).
  • the conductor 120 can be formed using a lithography method.
  • a dry etching method or a wet etching method can be used to process the conductive film 120A. Processing by dry etching is suitable for microfabrication.
  • the capacitive element 100 including the conductor 115, the insulator 130, and the conductor 120 can be formed.
  • an insulator 280 is formed on the insulator 130 and the conductor 120 (FIGS. 23A to 23C).
  • the insulating material described above can be used as appropriate for the insulator 280.
  • the insulator 280 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film is formed using a sputtering method.
  • the insulator 280 is preferably subjected to CMP (Chemical Mechanical Polishing) treatment after film formation to flatten the upper surface. By performing planarization treatment on the insulator 280, the conductor 240 functioning as a wiring can be suitably formed.
  • CMP Chemical Mechanical Polishing
  • CMP treatment may be performed until the insulator 280 is reached.
  • the surface of the insulator 280 can be flattened and smoothed.
  • the upper surface of the insulator 280 has an upwardly convex curved shape.
  • the film thickness of the insulator 280 on the conductor 120 corresponds to the channel length of the transistor 200
  • the film thickness of the insulator 280 can be appropriately set according to the designed value of the channel length of the transistor 200.
  • the insulator 280 by forming the insulator 280 by a sputtering method in an atmosphere containing oxygen, the insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the film-forming gas, the hydrogen concentration in the insulator 280 can be reduced. By forming the insulator 280 in this manner, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and VoH can be reduced.
  • a conductive film 240A is formed on the insulator 280 (FIGS. 23A to 23C).
  • the above-mentioned conductive materials can be used as appropriate for the conductive film 240A.
  • the conductive film 240A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the opening 290 can be formed using a lithography method.
  • the shape of the opening 290 shown in FIG. 24A is circular in plan view, it is not limited to this.
  • the shape of the opening 290 may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners when viewed from above.
  • the opening 290 is preferably formed using the above-mentioned ⁇ Method for Forming an Opening>. Thereby, it is possible to achieve miniaturization or high integration of the memory device.
  • the sidewall of the opening 290 is preferably perpendicular to the top surface of the conductor 110.
  • the side wall of the opening 290 may have a tapered shape. By tapering the sidewall of the opening 290, coverage with an oxide semiconductor film or the like that becomes the oxide semiconductor 230 (described later) can be improved, and defects such as holes can be reduced.
  • the maximum width (maximum diameter when the opening 290 is circular in plan view) of the opening 290 is preferably minute.
  • the maximum width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and preferably 1 nm or more, or 5 nm or more.
  • the opening 290 has a large aspect ratio, it is preferable to process a portion of the conductive film 240A and a portion of the insulator 280 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing. Further, the processing may be performed under different conditions depending on the layer. Note that depending on the conditions for processing a portion of the conductive film 240A and a portion of the insulator 280, as described above, the slope of the side surface of the conductor 240 at the opening 290 and the slope of the insulator 280 at the opening 290 may vary. The slopes of the sides may differ from each other.
  • heat treatment may be performed.
  • the heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas.
  • the oxygen gas content is about 20%.
  • the heat treatment may be performed under reduced pressure.
  • heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • impurities such as water contained in the insulator 280 and the like can be reduced before forming an oxide semiconductor film that will become the oxide semiconductor 230 described later.
  • the gas used in the heat treatment is highly purified.
  • the amount of water contained in the gas used in the heat treatment is set to be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • an oxide semiconductor film that will become the oxide semiconductor 230 is formed in contact with the bottom and sidewalls of the opening 290 and at least a portion of the top surface of the conductive film 240A.
  • a metal oxide that can be used for the above-described oxide semiconductor 230 can be used as appropriate.
  • the oxide semiconductor film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the oxide semiconductor film is preferably formed in contact with the bottom and sidewalls of the opening 290 having a large aspect ratio.
  • the oxide semiconductor film it is preferable to use a film forming method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.
  • a CVD method an ALD method, or the like.
  • an In-Ga-Zn oxide is formed using an ALD method.
  • the oxide semiconductor film that becomes the oxide semiconductor 230 is not limited to the case where a CVD method or an ALD method is used.
  • a sputtering method may be used.
  • the deposition methods for each layer included in the oxide semiconductor 230 may be the same or different.
  • the lower layer of the oxide semiconductor film may be formed by a sputtering method
  • the upper layer of the oxide semiconductor film may be formed by an ALD method.
  • An oxide semiconductor film formed using a sputtering method tends to have crystallinity. Therefore, by providing an oxide semiconductor film having crystallinity as a lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved.
  • the oxide semiconductor film formed by the ALD method which has good coverage, can cover the overlapping portions. It can be closed with the upper layer of
  • the oxide semiconductor film serving as the oxide semiconductor 230 covers the top surface of the conductor 120 in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and the side surface of the conductor 240 in the opening 290. Preferably, it is formed in contact with the upper surface.
  • the oxide semiconductor film in contact with the conductor 120 the conductor 120 functions as one of a source electrode and a drain electrode of the transistor 200.
  • the conductor 240 functions as the other of the source electrode and the drain electrode of the transistor 200.
  • the heat treatment may be performed at a temperature range in which the oxide semiconductor film does not become polycrystalline, and may be performed at a temperature of 250° C. or more and 650° C. or less, preferably 400° C. or more and 600° C. or less.
  • the above description can be referred to.
  • the heat treatment is preferably performed while the insulator 280 containing excess oxygen is provided in contact with the oxide semiconductor film.
  • oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and VoH can be reduced.
  • heat treatment was performed after the oxide semiconductor film was formed, but the present invention is not limited to this.
  • a configuration may also be adopted in which heat treatment is performed in a later step.
  • the oxide semiconductor film that will become the oxide semiconductor 230 is processed using a lithography method to form the oxide semiconductor 230 (FIGS. 25A to 25C). As a result, part of the oxide semiconductor 230 is formed in the opening 290. Further, the oxide semiconductor 230 is in contact with a part of the side surface and the top surface of the conductor 240. Therefore, the area of the region where the oxide semiconductor 230 and the conductor 240 are in contact can be increased.
  • the conductive film 240A is processed to form a conductor 240 (FIGS. 26A to 26C).
  • the conductor 240 can be formed using a lithography method.
  • a dry etching method or a wet etching method can be used to process the conductive film 240A. Processing by dry etching is suitable for microfabrication.
  • the method is similar to that described above until the conductive film 240A shown in FIGS. 23A to 23C is formed.
  • the conductive film 240A is processed to form the conductor 240.
  • the above description can be referred to.
  • a portion of the conductor 240 and a portion of the insulator 280 are processed to form an opening 290 that reaches the conductor 120.
  • the above description can be referred to.
  • heat treatment may be performed.
  • the conditions of the heat treatment, etc. the above explanation can be referred to.
  • an oxide semiconductor film that will become the oxide semiconductor 230 is formed in contact with the bottom and sidewalls of the opening 290 and at least a portion of the top surface of the conductor 240. At this time, the oxide semiconductor film has a region in contact with the upper surface of the insulator 280.
  • the above description can be referred to.
  • the oxide semiconductor film that will become the oxide semiconductor 230 is processed using a lithography method to form the oxide semiconductor 230 (FIGS. 26A to 26C).
  • an insulator 250 is formed over the oxide semiconductor 230, the conductor 240, and the insulator 280 (FIGS. 27A to 27C).
  • the insulating material described above can be used as appropriate for the insulator 250.
  • the insulator 250 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the insulator 250 is preferably formed in contact with the oxide semiconductor 230 provided in the opening 290 with a large aspect ratio. Therefore, for forming the insulator 250, it is preferable to use a film forming method that provides good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.
  • a silicon oxide film is formed using an ALD method.
  • the film formation of the insulator 250 is not limited to the case where the CVD method or the ALD method is used.
  • a sputtering method may be used.
  • the side end portions of the oxide semiconductor 230 are covered with the insulator 250. Therefore, short circuit between the oxide semiconductor 230 and the conductor 260 can be prevented. Furthermore, with the above configuration, the side end portions of the conductor 240 are covered with the insulator 250. Therefore, short circuit between the conductor 240 and the conductor 260 can be prevented.
  • a conductive film 260A is formed so as to fill the recesses of the insulator 250 (FIGS. 27A to 27C).
  • the conductive material described above can be used as appropriate for the conductive film 260A.
  • the conductive film 260A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductive film 260A is preferably formed in contact with the insulator 250 provided in the opening 290 having a large aspect ratio.
  • the conductive film 260A it is preferable to use a film forming method that provides good coverage or embeddability, and it is more preferable to use a CVD method, an ALD method, or the like.
  • a CVD method an ALD method, or the like.
  • titanium nitride is formed as the conductive film 260A using a CVD method or an ALD method.
  • the conductive film 260A is formed using the CVD method, the average surface roughness of the upper surface of the conductive film 260A may become large. In this case, it is preferable to planarize the conductive film 260A using a CMP method. At this time, before performing the CMP treatment, a silicon oxide film or a silicon oxynitride film may be formed over the conductive film 260A, and the CMP treatment may be performed until the silicon oxide film or silicon oxynitride film is removed.
  • the conductive film 260A is provided so as to fill the opening 290, but the present invention is not limited to this.
  • a recess reflecting the shape of the opening 290 may be formed in the center of the conductive film 260A.
  • the recess may be filled with an inorganic insulating material or the like.
  • the conductor 260 is processed to form a conductor 260 (FIGS. 28A to 28C).
  • the conductor 260 can be formed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for microfabrication.
  • the side end portion of the conductor 260 is preferably located inside the side end portion of the oxide semiconductor 230 in plan view. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented.
  • the transistor 200 including the conductor 120, the conductor 240, the oxide semiconductor 230, the insulator 250, and the conductor 260 can be formed.
  • an insulator 283 is formed to cover the conductor 260 and the insulator 250.
  • the above-mentioned insulating materials can be used as appropriate.
  • the insulator 283 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a memory device having the memory cell 150 shown in FIGS. 7A to 7D can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 shown in FIGS. 7A to 7D can be manufactured.
  • Example 2 of manufacturing method of storage device> Next, a method for manufacturing a memory device shown in FIGS. 17A to 17C, which is one embodiment of the present invention, will be described. Note that for the steps up to forming the insulator 280, the description in ⁇ Example 1 of manufacturing method of memory device> described above can be referred to.
  • An insulator 281 is formed on the insulator 280.
  • the above-mentioned insulating materials can be used as appropriate.
  • the insulator 281 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film is formed using a sputtering method.
  • the insulator 281 is preferably subjected to CMP treatment after film formation to flatten the upper surface.
  • an opening reaching the insulator 280 is formed in the insulator 281. Since the conductor 240 functioning as a wiring is formed inside the opening, it is preferable that the opening extends in the X direction.
  • the opening can be formed using a lithography method. Further, a dry etching method or a wet etching method can be used for etching the opening. Processing by dry etching is suitable for microfabrication.
  • the insulator 280 may have a laminated structure, and an insulator functioning as an etching stopper film may be provided on the uppermost surface of the insulator 280.
  • the insulator corresponds to the insulator 280c in the configuration shown in FIG. 15.
  • silicon oxide or silicon oxynitride is used for the insulator 281 forming the opening
  • silicon nitride, aluminum oxide, hafnium oxide, or the like may be used as the etching stopper film.
  • a conductive film that will become the conductor 240 is formed so as to fill the opening formed in the insulator 281.
  • the above-mentioned conductive materials can be used as appropriate for the conductive film.
  • the conductive film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a stacked film of tantalum nitride and tungsten is formed in this order using a sputtering method.
  • the conductor 240 may be formed by performing CMP treatment on the conductive film until the upper surface of the insulator 281 is exposed.
  • a memory device having the memory cell 150 shown in FIGS. 17A to 17C can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 shown in FIGS. 17A to 17C can be manufactured.
  • a new transistor, a new semiconductor device, and a new memory device can be provided.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a storage device with good frequency characteristics can be provided.
  • a storage device with high operating speed can be provided.
  • a highly reliable storage device can be provided.
  • a storage device with low power consumption can be provided.
  • a memory device including a transistor with a large on-state current can be provided.
  • a memory device with less variation in transistor characteristics can be provided.
  • a storage device with good electrical characteristics can be provided.
  • the memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a small off-state current, it is possible to retain stored contents for a long period of time by using the transistor 200 in a memory device. In other words, since no refresh operation is required or the frequency of refresh operations is extremely low, power consumption of the storage device can be sufficiently reduced. Further, since the transistor 200 has high frequency characteristics, reading and writing to the memory device can be performed at high speed.
  • FIG. 29A is a plan view of the storage device.
  • FIG. 29B is a cross-sectional view of a portion shown by a dashed line A1-A2 in FIG. 29A. Note that in the plan view of FIG. 29A, some elements are omitted for clarity.
  • each of the memory cell 150a and the memory cell 150b shown in FIGS. 29A and 29B has the same configuration as the memory cell 150.
  • the memory cell 150a includes a capacitor 100a and a transistor 200a
  • the memory cell 150b includes a capacitor 100b and a transistor 200b. Therefore, in the storage devices shown in FIGS. 29A and 29B, structures having the same functions as the structures configuring the storage device shown in FIG. 7 are given the same reference numerals. Note that also in this item, the materials described in detail in ⁇ Example of configuration of storage device> can be used as the constituent materials of the storage device.
  • the conductor 260 functioning as the wiring WL is provided in the memory cell 150a and the memory cell 150b, respectively. Further, a conductor 240 that functions as a part of the wiring BL is provided in common to the memory cell 150a and the memory cell 150b. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.
  • the memory device shown in FIGS. 29A and 29B includes a conductor 245 and a conductor 246 that are electrically connected to the memory cell 150a and the memory cell 150b and function as a plug (also referred to as a connection electrode).
  • the conductor 245 is disposed within the openings formed in the insulator 180, the insulator 280, and the insulator 140, and is in contact with the lower surface of the conductor 240.
  • the conductor 246 is disposed within the openings formed in the insulator 287, the insulator 283, and the insulator 250, and is in contact with the upper surface of the conductor 240. Note that for the conductor 245 and the conductor 246, a conductive material that can be used for the conductor 240 can be used.
  • the dielectric constant is low.
  • an insulator containing a material with a low dielectric constant described in the above-mentioned [Insulator] item can be used in a single layer or a laminated form.
  • the concentration of impurities such as water and hydrogen in the insulator 287 is reduced. Thereby, impurities such as water and hydrogen can be suppressed from entering the channel formation region of the oxide semiconductor 230.
  • the conductor 245 and the conductor 246 electrically connect the memory cell 150a and the memory cell 150b to circuit elements, wiring, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistance elements, and diodes. Acts as a plug or wiring for.
  • a conductor 245 is electrically connected to a sense amplifier (not shown) provided below the storage device shown in FIG. 29, and a conductor 246 is provided above the storage device shown in FIG. It can be configured to be electrically connected to a similar storage device (not shown).
  • the conductor 245 and the conductor 246 function as part of the wiring BL. In this way, by providing a storage device or the like above or below the storage device shown in FIG. 29, the storage capacity per unit area can be increased.
  • the memory cell 150a and the memory cell 150b have a line-symmetrical configuration with a perpendicular bisector of the dashed-dotted line A1-A2 as an axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged at symmetrical positions with the conductor 245 and the conductor 246 in between.
  • the conductor 240 has a function as the other of the source electrode and the drain electrode of the transistor 200a, and a function as the other of the source electrode and the drain electrode of the transistor 200b.
  • the transistor 200a and the transistor 200b share a conductor 245 and a conductor 246 that function as a plug. In this way, by connecting the two transistors and the plug to the above-described configuration, it is possible to provide a memory device that can be miniaturized or highly integrated.
  • the conductor 110 functioning as the wiring PL may be provided in each of the memory cell 150a and the memory cell 150b, or may be provided in common in the memory cell 150a and the memory cell 150b. However, as shown in FIG. 29B, the conductor 110 is provided apart from the conductor 245 to prevent short circuit between the conductor 110 and the conductor 245.
  • FIGS. 30A and 30B show an example of a memory device in which 4 ⁇ 2 ⁇ 4 memory cells 150 are arranged in the X direction, Y direction, and Z direction.
  • FIG. 30A is a plan view of the storage device.
  • FIG. 30B is a cross-sectional view of the portion shown by the dashed line A1-A2 in FIG. 30A. Note that in the plan view of FIG. 30A, some elements are omitted for clarity.
  • each of the memory cells 150a to 150d shown in FIGS. 30A and 30B has the same configuration as the memory cell 150.
  • the memory cell 150a includes a capacitor 100a and a transistor 200a
  • the memory cell 150b includes a capacitor 100b and a transistor 200b
  • the memory cell 150c includes a capacitor 100c and a transistor 200c
  • the memory cell 150d includes: It has a capacitive element 100d and a transistor 200d. Therefore, in the storage devices shown in FIGS. 30A and 30B, structures having the same functions as the structures configuring the storage device shown in FIG. 7 are given the same reference numerals. Note that also in this item, the materials described in detail in ⁇ Example of configuration of storage device> can be used as the constituent materials of the storage device.
  • a storage device made up of memory cells 150a to 150d will be referred to as a memory unit.
  • the storage device shown in FIGS. 30A and 30B includes memory units 160[1,1] to 160[2,4]. Note that hereinafter, the memory units 160[1,1] to 160[2,4] may be collectively referred to as the memory unit 160.
  • Memory unit 160[1,2] is provided on memory unit 160[1,1]
  • memory unit 160[1,3] is provided on memory unit 160[1,2]
  • memory unit 160[1,3] is provided on memory unit 160[1,2].
  • 1,4] are provided on the memory unit 160[1,3].
  • Memory unit 160[2,1] is provided adjacent to memory unit 160[1,1] in the Y direction.
  • Memory unit 160[2,2] is provided on memory unit 160[2,1]
  • memory unit 160[2,3] is provided on memory unit 160[2,2]
  • memory unit 160[2,2] is provided on memory unit 160[2,2].
  • 160[2,4] is provided above memory unit 160[2,3].
  • a memory cell 150c is arranged outside the memory cell 150a, and a memory cell 150d is arranged outside the memory cell 150b, with the conductor 245 at the center.
  • the memory device shown in FIG. 29 can be said to be a memory device in which a memory cell 150c is provided adjacent to a memory cell 150a, and a memory cell 150d is provided adjacent to a memory cell 150b.
  • the conductor 260 functioning as the wiring WL is shared by memory cells 150 adjacent to each other in the Y direction. Furthermore, the conductor 240 that functions as part of the wiring BL is shared within the same memory unit. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of each of the memory cells 150a to 150d.
  • a conductor 245 is provided between conductors 240 of memory units adjacent in the Z direction.
  • the conductor 245 is provided in contact with the upper surface of the conductor 240 of the memory unit 160[1,1] and the lower surface of the conductor 240 of the memory unit 160[1,2].
  • the wiring BL is formed by the conductor 240 and the conductor 245 provided in each memory unit 160.
  • the conductor 245 is electrically connected to a sense amplifier (not shown) provided below the memory device shown in FIG. In this way, in the storage device shown in FIG. 30, by stacking a plurality of memory units, the storage capacity per unit area can be increased.
  • the memory cell 150a and the memory cell 150c, and the memory cell 150b and the memory cell 150d have a line-symmetric configuration with the perpendicular bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200c, and the transistor 200b and the transistor 200d are also arranged at symmetrical positions with the conductor 245 in between.
  • the conductor 240 functions as the other of the source electrode and drain electrode of each of the transistors 200a to 200d.
  • the transistors 200a to 200d share a conductor 245 that functions as a plug. In this way, by connecting the four transistors and the plugs in the above-described configuration, it is possible to provide a memory device that can be miniaturized or highly integrated.
  • the cells can be arranged in an integrated manner without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be configured. Note that although FIG. 30 illustrates a configuration in which four layers each having two memory units are stacked, the present invention is not limited to this.
  • the memory device may have one layer having at least one memory cell 150, or may have two or more layers stacked.
  • FIG. 30 shows a configuration in which a conductor 245 functioning as a plug is arranged between memory cells 150.
  • a configuration is shown in which the conductor 245 functioning as a plug is arranged inside the memory unit 160.
  • Electrical conductor 245 may be placed outside the memory unit.
  • FIGS. 31A and 31B show an example of a memory device in which 3 ⁇ 3 ⁇ 4 memory cells 150 are arranged in the X direction, Y direction, and Z direction.
  • FIG. 31A is a plan view of the storage device.
  • FIG. 31B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 31A. Note that in the plan view of FIG. 31A, some elements are omitted for clarity.
  • the memory device shown in FIGS. 31A and 31B has a structure in which m (m is an integer of 2 or more) layers including the memory cell 150 are laminated.
  • m is an integer of 2 or more
  • the above layer provided as the first layer (bottom) is referred to as layer 170[1]
  • the above layer provided as the second layer is referred to as layer 170[2]
  • the (m-1) layer is referred to as layer 170[1].
  • FIG. 31B shows the provided layer as a layer 170 [m-1], and the m-th (top) layer as a layer 170 [m].
  • the memory device of one embodiment of the present invention may have a plurality of layers including the memory cell 150, and may have a structure in which the plurality of layers are stacked.
  • the conductor 245 may be provided outside the memory unit. Further, the conductor 245 may be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in layer 170[1] is electrically connected to the wiring provided in layer 170[2]. Note that the wiring provided in layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of memory cell 150 included in layer 170[2]. In other words, the wiring can be formed in the same process as the conductor 110.
  • FIG. 31 shows a configuration in which the conductor 245 is electrically connected to a wiring provided in a layer above the layer including the conductor 245, the present invention is not limited to this.
  • the conductor 245 may be electrically connected to wiring provided in a layer including the conductor 245.
  • the conductor 245 provided in the layer 170[1] may be electrically connected to the wiring provided in the layer 170[1].
  • the wiring provided in layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of memory cell 150 included in layer 170[1]. In other words, the wiring can be formed in the same process as the conductor 110.
  • FIG. 32 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked on a layer in which a drive circuit including a sense amplifier is provided.
  • the capacitor 100 is provided above the transistor 300, and the transistor 200 is provided above the transistor 300 and the capacitor 100.
  • the transistor 300 is one of the transistors included in the sense amplifier.
  • the configuration of the memory cell 150 (transistor 200 and capacitor 100) shown in FIG. 32 is as described above.
  • the bit line can be shortened. This reduces the bit line capacitance and reduces the storage capacitance of the memory cell.
  • the transistor 200 is not subjected to thermal history during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as fluctuation in threshold voltage and increase in parasitic resistance, and increase in variation in electrical characteristics due to deterioration of electrical characteristics can be suppressed.
  • the storage device shown in FIG. 32 can correspond to the storage device 80 described in Embodiment 2.
  • transistor 300 corresponds to a transistor included in sense amplifier 46 in memory device 80.
  • the memory cell 150 corresponds to the memory cell 32
  • the transistor 200 corresponds to the transistor 37
  • the capacitor 100 corresponds to the capacitor 38.
  • the transistor 300 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311, and functions as a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b. Transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween.
  • the conductor 316 may be made of a material that adjusts the work function.
  • Such a transistor 300 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate.
  • an insulator may be provided in contact with the upper portion of the convex portion to function as a mask for forming the convex portion.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 300 illustrated in FIG. 32 is an example, and the structure is not limited, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer including an interlayer film, wiring, plug, etc. may be provided between each structure. Further, a plurality of wiring layers can be provided depending on the design. Here, a plurality of structures of a conductor functioning as a plug or a wiring may be given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided as interlayer films over the transistor 300. Further, a conductor 328 is embedded in the insulator 320 and the insulator 322, and a conductor 330 is embedded in the insulator 324 and the insulator 326. Note that the conductor 328 and the conductor 330 function as a plug or wiring.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below it.
  • the upper surface of the insulator 322 may be flattened by a flattening process using a CMP method or the like to improve flatness.
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are stacked in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or wiring.
  • the above-mentioned insulators that can be used in memory devices can be used.
  • the conductor that functions as a plug or a wiring for example, the conductor 328, the conductor 330, the conductor 356, etc., the conductors described in the above [Conductor] can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to use a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
  • the conductor 240 of the transistor 200 connects to the source of the transistor 300 via a conductor 643, a conductor 642, a conductor 644, a conductor 645, a conductor 646, a conductor 356, a conductor 330, and a conductor 328. It is electrically connected to a low resistance region 314b that functions as a region or a drain region.
  • the conductor 643 is embedded in the insulator 280.
  • the conductor 642 is provided on the insulator 130 and embedded in the insulator 641.
  • the conductor 642 can be manufactured using the same material and the same process as the conductor 120.
  • the conductor 644 is embedded in the insulator 180 and the insulator 130.
  • the conductor 645 is embedded in the insulator 647.
  • the conductor 645 can be manufactured using the same material and the same process as the conductor 110.
  • a conductor 646 is embedded in an insulator 648.
  • the transistor 300 and the conductor 110 are electrically insulated by the insulator 648.
  • Embodiment 2 a storage device according to one embodiment of the present invention will be described with reference to FIGS. 33 to 36.
  • a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a drive circuit including a sense amplifier is provided will be described.
  • FIG. 33 shows a block diagram illustrating a configuration example of a storage device 80 according to one aspect of the present invention.
  • a storage device 80 shown in FIG. 33 includes a layer 20 and a stacked layer 70.
  • Layer 20 is a layer containing Si transistors.
  • element layers 30[1] to 30[m] (m is an integer of 2 or more) are stacked.
  • the element layers 30[1] to 30[m] are layers including OS transistors.
  • the layer 70 in which layers having OS transistors are stacked can be provided in a stack on the layer 20 .
  • FIG. 33 shows an example in which the element layers 30[1] to 30[m] have a plurality of memory cells 32 arranged in a matrix of m rows and n columns (n is an integer of 2 or more).
  • the memory cell 32 in the first row and first column is shown as a memory cell 32[1,1] and the memory cell 32 in the mth row and nth column is shown as a memory cell 32[m,n].
  • the memory cell 32 in the mth row and nth column is shown as a memory cell 32[m,n].
  • i line when indicating an arbitrary line, it may be written as i line.
  • column j when indicating an arbitrary column, it may be written as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.
  • the memory cell 32 in the i-th row and j-th column is referred to as a memory cell 32[i,j].
  • m wires WL extending in the row direction m wires PL extending in the row direction, m wires PL extending in the row direction, and n wires BL extending in the column direction are illustrated. ing.
  • the wiring WL provided in the first (first row) is referred to as wiring WL[1]
  • the wiring WL provided in m-th (m-th row) is referred to as wiring WL[m].
  • the first wiring PL (first row) is designated as wiring PL[1]
  • the mth wiring PL (mth row) is designated as wiring PL[m].
  • wiring BL provided in the first (first column) is referred to as wiring BL[1]
  • wiring BL provided in the nth (nth column) is referred to as wiring BL[n].
  • the number of element layers 30[1] to 30[m] and the number of wirings WL (and wirings PL) may not be the same.
  • the plurality of memory cells 32 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]).
  • the plurality of memory cells 32 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling on or off (conductive state or non-conductive state) of an access transistor functioning as a switch.
  • the wiring PL has a function as a constant potential line connected to the capacitor. Note that a wiring CL (not shown) can be provided separately as a wiring for transmitting the back gate potential.
  • the memory cells 32 included in each of the element layers 30[1] to 30[m] are connected to a sense amplifier 46 via a wiring BL.
  • the wiring BL can be arranged horizontally and vertically on the surface of the substrate on which the layer 20 is provided.
  • the length of the wiring between the element layer 30 and the sense amplifier 46 can be shortened. Since the signal propagation distance between the memory cell and the sense amplifier can be shortened, and the bit line resistance and parasitic capacitance can be significantly reduced, power consumption and signal delay can be reduced. Therefore, the power consumption and signal delay of the storage device 80 can be reduced. Furthermore, it is possible to operate the memory cell 32 even if the capacitance of the capacitor is reduced. Therefore, the storage device 80 can be made smaller.
  • Layer 20 includes a power switch 71 (PSW), a power switch 72, and a peripheral circuit 22.
  • the peripheral circuit 22 includes a drive circuit 40, a control circuit 73, and a voltage generation circuit 74. Note that each circuit included in the layer 20 is a circuit including a Si transistor.
  • each circuit, each signal, and each voltage can be removed or discarded as necessary. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signal BW, the signal CE, and the signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signal PON1 and signal PON2 are power gating control signals. Note that the signal PON1 and the signal PON2 may be generated by the control circuit 73.
  • the control circuit 73 is a logic circuit that has a function of controlling the overall operation of the storage device 80. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 80. Alternatively, the control circuit 73 generates a control signal for the drive circuit 40 so that this operation mode is executed.
  • the control circuit 73 performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 80.
  • the control circuit 73 generates a control signal for the drive circuit 40 so that this operation mode is executed.
  • the voltage generation circuit 74 has a function of generating a negative voltage.
  • Signal WAKE has a function of controlling input of signal CLK to voltage generation circuit 74. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 74, and the voltage generation circuit 74 generates a negative voltage.
  • the drive circuit 40 is a circuit for writing and reading data to and from the memory cells 32.
  • the drive circuit 40 includes a row decoder 42, a column decoder 44, a row driver 43), a column driver 45, an input circuit 47, an output circuit 48, and the sense amplifier 46 described above.
  • Row decoder 42 and column decoder 44 have the function of decoding signal ADDR.
  • the row decoder 42 is a circuit for specifying a row to be accessed
  • the column decoder 44 is a circuit for specifying a column to be accessed.
  • the row driver 43 has a function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has a function of writing data into the memory cell 32, a function of reading data from the memory cell 32, a function of holding the read data, and the like.
  • Input circuit 47 has a function of holding signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written into the memory cell 32.
  • the data (Dout) read from the memory cell 32 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout. Further, the output circuit 48 has a function of outputting Dout to the outside of the storage device 80.
  • the data output from the output circuit 48 is the signal RDA.
  • the power switch 71 has a function of controlling the supply of VDD to the peripheral circuit 22.
  • the power switch 72 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the memory device 80 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to bring the word line to a high level, and is higher than VDD.
  • the signal PON1 controls on/off of the power switch 71
  • the signal PON2 controls the on/off of the power switch 72.
  • the number of power domains to which VDD is supplied is one, but it may be plural. In this case, a power switch may be provided for each power domain.
  • the element layer 30 provided as the first layer is shown as an element layer 30[1]
  • the element layer 30 provided as the second layer is shown as an element layer 30[2]
  • the element layer 30 provided as the fifth layer is shown as an element layer 30[2].
  • the element layer 30 is shown as an element layer 30[5].
  • a wiring WL and a wiring PL extending in the X direction, a wiring BL and a wiring BLB extending in the Y direction and the Z direction (direction perpendicular to the surface of the substrate on which the drive circuit is provided), is illustrated.
  • the wiring BLB is an inverted bit line. Note that, in order to make the drawing easier to read, some descriptions of the wiring WL and the wiring PL included in each of the element layers 30 are omitted.
  • FIG. 34B shows the configuration of the sense amplifier 46 connected to the wiring BL and the wiring BLB illustrated in FIG. 34A, and the memory cell 32 included in the element layers 30[1] to 30[5] connected to the wiring BL and the wiring BLB.
  • a schematic diagram illustrating an example is shown. Note that a configuration in which a plurality of memory cells (memory cells 32) are electrically connected to one wiring BL and one wiring BLB is also referred to as a "memory string.”
  • FIG. 34B illustrates an example of the circuit configuration of the memory cell 32 connected to the wiring BLB.
  • the memory cell 32 includes a transistor 37 and a capacitor 38.
  • the transistor 37, the capacitor 38, and each wiring (BL, WL, etc.) for example, the wiring BL[1] and the wiring WL[1] may be referred to as the wiring BL and the wiring WL.
  • the memory cell 150 illustrated in the previous embodiment can be applied to the memory cell 32. That is, the transistor 200 can be used as the transistor 37, and the capacitor 100 can be used as the capacitor 38. Further, as the transistor included in the sense amplifier 46, a transistor 300 (see FIG. 32) can be used.
  • one of the source and drain of the transistor 37 is connected to the wiring BL.
  • the other of the source and drain of the transistor 37 is connected to one electrode of the capacitive element 38.
  • the other electrode of the capacitive element 38 is connected to the wiring PL.
  • the gate of the transistor 37 is connected to the wiring WL.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitive element 38.
  • the number of wires can be reduced by connecting the plurality of wires PL as one wire.
  • the OS transistors are provided in a stacked manner, and a wiring functioning as a bit line is arranged in a direction perpendicular to the surface of the substrate on which layer 20 is provided.
  • the transistor 37 and the capacitive element 38 included in the memory cell 32 are arranged side by side in the direction perpendicular to the substrate surface on which the layer 20 is provided.
  • FIGS. 35A and 35B show a circuit diagram corresponding to the above-described memory cell 32 and a diagram illustrating a circuit block corresponding to the circuit diagram.
  • the memory cells 32 may be represented as blocks in drawings and the like. Note that the wiring BL illustrated in FIGS. 35A and 35B can be similarly expressed when replaced with the wiring BLB.
  • FIGS. 35C and 35D show a circuit diagram corresponding to the above-described sense amplifier 46 and a diagram illustrating a circuit block corresponding to the circuit diagram.
  • the sense amplifier 46 includes a switch circuit 82, a precharge circuit 83, a precharge circuit 84, and an amplifier circuit 85.
  • a wiring SA_OUT and a wiring SA_OUTB that output signals to be read are also illustrated.
  • the switch circuit 82 includes, for example, n-channel transistors 82_1 and 82_2, as shown in FIG. 35C.
  • the transistors 82_1 and 82_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.
  • the precharge circuit 83 is composed of n-channel transistors 83_1 to 83_3, as shown in FIG. 35C.
  • the precharge circuit 83 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD/2 in response to the signal EQ.
  • the precharge circuit 84 is composed of p-channel type transistors 84_1 to 84_3, as shown in FIG. 35C.
  • the precharge circuit 84 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD/2 in response to the signal EQB.
  • the amplifier circuit 85 includes p-channel transistors 85_1 and 85_2 and n-channel transistors 85_3 and 85_4, which are connected to the wiring SAP or the wiring SAN.
  • the wiring SAP or the wiring SAN is a wiring that has a function of providing VDD or VSS.
  • Transistors 85_1 to 85_4 are transistors forming an inverter loop.
  • FIG. 35D shows a diagram illustrating a circuit block corresponding to the sense amplifier 46 described in FIG. 35C and the like. As illustrated in FIG. 35D, the sense amplifier 46 may be represented as a block in drawings, etc.
  • FIG. 36 is a circuit diagram of the storage device 80 of FIG. 33.
  • FIG. 36 is illustrated using the circuit blocks described in FIGS. 35A to 35D.
  • the layer 70 including the element layer 30[m] has memory cells 32.
  • the memory cell 32 illustrated in FIG. 36 is connected to a pair of wiring BL[1] and wiring BLB[1], or wiring BL[2] and wiring BLB[2], as an example.
  • the memory cell 32 connected to the wiring BL is a memory cell into which data is written or read.
  • the wiring BL[1] and the wiring BLB[1] are connected to the sense amplifier 46[1], and the wiring BL[2] and the wiring BLB[2] are connected to the sense amplifier 46[2].
  • the sense amplifier 46[1] and the sense amplifier 46[2] can read data according to the various signals described with reference to FIG. 35C.
  • This embodiment mode can be combined with other embodiment modes and examples as appropriate.
  • a semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic equipment, large computers, space equipment, and data centers (also referred to as DCs). Electronic components, electronic equipment, large computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving higher performance such as lower power consumption.
  • FIG. 37A A perspective view of a board (mounted board 704) on which electronic component 700 is mounted is shown in FIG. 37A.
  • An electronic component 700 shown in FIG. 37A includes a semiconductor device 710 within a mold 711. In FIG. 37A, some descriptions are omitted to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. Land 712 is electrically connected to electrode pad 713, and electrode pad 713 is electrically connected to semiconductor device 710 via wire 714.
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702.
  • the semiconductor device 710 includes a drive circuit layer 715 and a memory layer 716.
  • the storage layer 716 has a structure in which a plurality of memory cell arrays are stacked.
  • the structure in which the drive circuit layer 715 and the memory layer 716 are stacked can be monolithically stacked. In a monolithically laminated structure, each layer can be connected without using a through electrode technology such as TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • Cu-Cu direct bonding By monolithically stacking the drive circuit layer 715 and the storage layer 716, it is possible to have a so-called on-chip memory structure in which memory is formed directly on the processor, for example. By using an on-chip memory configuration, it is possible to speed up the operation of the interface between the processor and the memory.
  • connection wiring etc. can be made smaller compared to a technology using through silicon vias such as TSV, so it is also possible to increase the number of connection pins.
  • TSV through silicon vias
  • connection pins By increasing the number of connection pins, parallel operation becomes possible, thereby making it possible to improve the memory bandwidth (also referred to as memory bandwidth).
  • a plurality of memory cell arrays included in the storage layer 716 be formed using OS transistors, and the plurality of memory cell arrays are monolithically stacked.
  • OS transistors By monolithically stacking a plurality of memory cell arrays, one or both of memory bandwidth and memory access latency can be improved.
  • bandwidth is the amount of data transferred per unit time
  • access latency is the time from access to the start of data exchange.
  • the semiconductor device 710 may be referred to as a die.
  • a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also referred to as a wafer) and cutting it into dice in the semiconductor chip manufacturing process.
  • semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also referred to as a silicon wafer
  • a silicon die is sometimes referred to as a silicon die.
  • the electronic component 730 is an example of SiP (System in Package) or MCM (Multi Chip Module).
  • an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.
  • the semiconductor device 710 is used as a high bandwidth memory (HBM).
  • the semiconductor device 735 is an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array). Can be used.
  • a CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • FPGA Field Programmable Gate Array
  • a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732.
  • the interposer 731 for example, a silicon interposer or a resin interposer can be used.
  • the interposer 731 has a plurality of wiring lines and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or in multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732.
  • interposers are sometimes called "rewiring boards” or “intermediate boards.”
  • a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode.
  • TSV can also be used as the through electrode.
  • HBM In HBM, it is necessary to connect many wires to realize a wide memory bandwidth. For this reason, an interposer mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.
  • a decrease in reliability due to a difference in expansion coefficient between the integrated circuit and the interposer is less likely to occur.
  • the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur.
  • a space corresponding to the width of the terminal pitch is required. Therefore, when trying to reduce the size of the electronic component 730, the above-mentioned terminal pitch width becomes a problem, and it may become difficult to provide the many wirings necessary to achieve a wide memory bandwidth. . Therefore, as described above, a configuration in which OS transistors are monolithically stacked is preferable. It may also be a composite structure in which a memory cell array stacked using TSVs and a memory cell array stacked monolithically are combined.
  • a heat sink may be provided to overlap the electronic component 730.
  • a heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the heights of the semiconductor device 710 and the semiconductor device 735 are the same.
  • an electrode 733 may be provided at the bottom of the package substrate 732.
  • FIG. 37B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of implementation methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), and QFJ (Quad Flat J-lead). package), and QFN (Quad Flat Non-leaded package) can be mentioned.
  • FIG. 38A a perspective view of electronic device 6500 is shown in FIG. 38A.
  • Electronic device 6500 shown in FIG. 38A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • Electronic device 6600 shown in FIG. 38B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like.
  • the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that it is preferable to use the semiconductor device of one embodiment of the present invention for the above-described control device 6509 and control device 6616 because power consumption can be reduced.
  • FIG. 38C a perspective view of large computer 5600 is shown in FIG. 38C.
  • a plurality of rack-mount computers 5620 are stored in a rack 5610.
  • the large computer 5600 may be called a supercomputer.
  • the computer 5620 can have, for example, the configuration shown in the perspective view shown in FIG. 38D.
  • a computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
  • a PC card 5621 shown in FIG. 38E is an example of a processing board that includes a CPU, a GPU, a storage device, and the like.
  • PC card 5621 has a board 5622.
  • the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • semiconductor devices other than the semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 are illustrated in FIG. The description of the semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • Examples of the standard of the connection terminal 5629 include PCIe.
  • connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as an interface for supplying power, inputting signals, etc. to the PC card 5621, for example. Further, for example, it can be used as an interface for outputting a signal calculated by the PC card 5621.
  • the respective standards of the connection terminal 5623, connection terminal 5624, and connection terminal 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Can be mentioned.
  • the respective standards include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and by inserting the terminal into a socket (not shown) provided on the board 5622, the semiconductor device 5626 and the board 5622 are electrically connected. can be connected to.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • an electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5628 include a storage device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • Large computer 5600 can also function as a parallel computer. By using the large-scale computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence learning and inference.
  • a semiconductor device of one embodiment of the present invention can be suitably used for space equipment.
  • a semiconductor device of one embodiment of the present invention includes an OS transistor.
  • OS transistors have small variations in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it can be suitably used in environments where radiation may be incident.
  • OS transistors can be suitably used when used in outer space.
  • the OS transistor can be used as a transistor configuring a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe.
  • Examples of radiation include X-rays and neutron beams.
  • outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include one or more of the thermosphere, mesosphere, and stratosphere.
  • FIG. 39 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that in FIG. 39, a planet 6804 is illustrated in outer space.
  • the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit. It is preferable to use an OS transistor in the battery management system or battery control circuit described above because it has low power consumption and high reliability even in outer space.
  • BMS battery management system
  • OS transistor it is preferable to use an OS transistor in the battery management system or battery control circuit described above because it has low power consumption and high reliability even in outer space.
  • outer space is an environment with more than 100 times higher radiation levels than on the ground.
  • radiation include electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays, and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. It will be done.
  • the solar panel 6802 By irradiating the solar panel 6802 with sunlight, electric power necessary for the operation of the artificial satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or in a situation where the amount of sunlight irradiated onto the solar panel is small, less electric power is generated. Therefore, the power necessary for satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even in a situation where generated power is small, it is preferable to provide the artificial satellite 6800 with a secondary battery 6805. Note that the solar panel is sometimes called a solar cell module.
  • Satellite 6800 can generate signals.
  • the signal is transmitted via antenna 6803 and can be received by a ground-based receiver or other satellite, for example.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • OS transistors Compared to Si transistors, OS transistors have smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, it is highly reliable and can be suitably used even in environments where radiation may be incident.
  • the artificial satellite 6800 can be configured to include a sensor.
  • the artificial satellite 6800 can have a function of detecting sunlight reflected by hitting an object provided on the ground.
  • the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface.
  • the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.
  • OS transistors have superior effects compared to Si transistors, such as being able to realize a wide memory bandwidth and having high radiation resistance.
  • a semiconductor device can be suitably used in, for example, a storage system applied to a data center or the like.
  • Data centers are required to perform long-term data management, including ensuring data immutability.
  • it is necessary to install storage and servers to store huge amounts of data, secure a stable power supply to retain data, or secure cooling equipment required to retain data, etc. due to the large size of the building. ization is required.
  • the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, the power required to hold data can be reduced and the semiconductor device that holds data can be made smaller. Therefore, it is possible to downsize the storage system, downsize the power supply for holding data, and downsize the cooling equipment. Therefore, it is possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, heat generated from the circuit can be reduced. Therefore, the adverse effect of the heat generation on the circuit itself, peripheral circuits, and module can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • FIG. 40 shows a storage system applicable to data centers.
  • the storage system 7000 shown in FIG. 40 has a plurality of servers 7001sb as hosts 7001 (shown as Host Computer). It also includes a plurality of storage devices 7003md as storage 7003 (shown as Storage).
  • a host 7001 and a storage 7003 are shown connected via a storage area network 7004 (SAN: Storage Area Network) and a storage control circuit 7002 (Storage Controller).
  • SAN Storage Area Network
  • Storage Controller Storage Controller
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • the storage 7003 uses flash memory to shorten the data access speed, that is, the time required to store and output data, this time is the same as the time required by DRAM, which can be used as a cache memory in the storage. It is much longer than .
  • a cache memory is usually provided in the storage to shorten the time required to store and output data.
  • the cache memory described above is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the storage control circuit 7002 and the cache memory in the storage 7003, and then output to the host 7001 or the storage 7003.
  • an OS transistor as a transistor for storing data in the cache memory described above and maintaining a potential according to the data, the frequency of refreshing can be reduced and power consumption can be reduced. Further, size reduction is possible by using a structure in which memory cell arrays are stacked.
  • the semiconductor device of one embodiment of the present invention by applying the semiconductor device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, power consumption can be reduced. There is expected. Therefore, as energy demand is expected to increase due to higher performance or higher integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention will reduce the greenhouse effect typified by carbon dioxide (CO 2 ). It also becomes possible to reduce the amount of gas discharged. Further, since the semiconductor device of one embodiment of the present invention has low power consumption, it is effective as a countermeasure against global warming.
  • CO 2 carbon dioxide
  • ADDR signal, BL[1]: wiring, BL[2]: wiring, BL[j]: wiring, BL[n]: wiring, BL: wiring, BLB[1]: wiring, BLB[2]: wiring, BLB: wiring, BW: signal, CE: signal, CL: wiring, CLK: signal, CSEL: signal, EQ: signal, EQB: signal, GW: signal, PL[1]: wiring, PL[i]: wiring, PL [m]: wiring, PL: wiring, RDA: signal, SA_OUT: wiring, SA_OUTB: wiring, SAN: wiring, SAP: wiring, Tr: transistor, VPRE: intermediate potential, WAKE: signal, WDA: signal, WL [ 1]: wiring, WL[i]: wiring, WL[m]: wiring, WL: wiring, 20: layer, 22: peripheral circuit, 30[1]: element layer, 30[2]: element layer, 30[ 5]: element layer, 30 [m]: element layer, 30: element layer, 32

Landscapes

  • Semiconductor Memories (AREA)
PCT/IB2023/058644 2022-09-08 2023-09-01 半導体装置の作製方法 Ceased WO2024052774A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024545077A JPWO2024052774A1 (https=) 2022-09-08 2023-09-01

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022142989 2022-09-08
JP2022-142989 2022-09-08

Publications (1)

Publication Number Publication Date
WO2024052774A1 true WO2024052774A1 (ja) 2024-03-14

Family

ID=90192115

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2023/058644 Ceased WO2024052774A1 (ja) 2022-09-08 2023-09-01 半導体装置の作製方法

Country Status (2)

Country Link
JP (1) JPWO2024052774A1 (https=)
WO (1) WO2024052774A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025219846A1 (ja) * 2024-04-19 2025-10-23 株式会社半導体エネルギー研究所 半導体装置
WO2025233772A1 (ja) * 2024-05-10 2025-11-13 株式会社半導体エネルギー研究所 半導体装置
WO2025243155A1 (ja) * 2024-05-23 2025-11-27 株式会社半導体エネルギー研究所 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349301A (ja) * 1999-04-01 2000-12-15 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2005150494A (ja) * 2003-11-18 2005-06-09 Sony Corp 半導体装置の製造方法
JP2010192825A (ja) * 2009-02-20 2010-09-02 Tokyo Electron Ltd 基板処理方法
JP2017168764A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
JP2018149552A (ja) * 2017-03-10 2018-09-27 株式会社ナノマテックス はんだ接合工法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349301A (ja) * 1999-04-01 2000-12-15 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2005150494A (ja) * 2003-11-18 2005-06-09 Sony Corp 半導体装置の製造方法
JP2010192825A (ja) * 2009-02-20 2010-09-02 Tokyo Electron Ltd 基板処理方法
JP2017168764A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
JP2018149552A (ja) * 2017-03-10 2018-09-27 株式会社ナノマテックス はんだ接合工法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025219846A1 (ja) * 2024-04-19 2025-10-23 株式会社半導体エネルギー研究所 半導体装置
WO2025233772A1 (ja) * 2024-05-10 2025-11-13 株式会社半導体エネルギー研究所 半導体装置
WO2025243155A1 (ja) * 2024-05-23 2025-11-27 株式会社半導体エネルギー研究所 半導体装置

Also Published As

Publication number Publication date
JPWO2024052774A1 (https=) 2024-03-14

Similar Documents

Publication Publication Date Title
WO2024052774A1 (ja) 半導体装置の作製方法
US20240113138A1 (en) Semiconductor device, method for manufacturing semiconductor device, and electronic apparatus
WO2024079586A1 (ja) 半導体装置、及び記憶装置
WO2024057166A1 (ja) 半導体装置
WO2024084366A1 (ja) 半導体装置、及び、記憶装置
JP2024000519A (ja) 半導体装置の作製方法
US20260052673A1 (en) Memory device and method for manufacturing the memory device
WO2023237961A1 (ja) 半導体装置、記憶装置、及び半導体装置の作製方法
WO2024057165A1 (ja) 記憶装置
KR20250154423A (ko) 반도체 장치 및 반도체 장치의 제작 방법
WO2024047486A1 (ja) 記憶装置
KR20260020398A (ko) 반도체 장치, 반도체 장치의 제작 방법, 및 전자 기기
KR20250126619A (ko) 반도체 장치
WO2024028681A1 (ja) 半導体装置、及び記憶装置
WO2025163448A1 (ja) 半導体装置
WO2025052212A1 (ja) 半導体装置
KR20250107184A (ko) 반도체 장치 및 반도체 장치의 제작 방법
WO2024095108A1 (ja) 半導体装置、及び記憶装置
WO2025163447A1 (ja) 半導体装置
WO2023209486A1 (ja) 半導体装置、及び記憶装置
KR20260057631A (ko) 반도체 장치 및 반도체 장치의 제작 방법
WO2025046390A1 (ja) 半導体装置、及び半導体装置の作製方法
WO2024194726A1 (ja) 半導体装置、及び、半導体装置の作製方法
KR20260013188A (ko) 반도체 장치 및 반도체 장치의 제작 방법
WO2025202852A1 (ja) 記憶素子、記憶装置及び電子機器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23862594

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2024545077

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23862594

Country of ref document: EP

Kind code of ref document: A1