WO2024050866A1 - 基于高温退火技术的氧化镓器件制备方法及氧化镓器件 - Google Patents

基于高温退火技术的氧化镓器件制备方法及氧化镓器件 Download PDF

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WO2024050866A1
WO2024050866A1 PCT/CN2022/119588 CN2022119588W WO2024050866A1 WO 2024050866 A1 WO2024050866 A1 WO 2024050866A1 CN 2022119588 W CN2022119588 W CN 2022119588W WO 2024050866 A1 WO2024050866 A1 WO 2024050866A1
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gallium oxide
barrier layer
layer
wafer
annealing
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PCT/CN2022/119588
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English (en)
French (fr)
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徐光伟
何启鸣
周选择
李秋艳
赵晓龙
龙世兵
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中国科学技术大学
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Priority to US18/344,625 priority Critical patent/US20240079478A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22

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  • the invention relates to semiconductor material processing technology, and in particular to a method for preparing a gallium oxide device based on high-temperature annealing technology and a gallium oxide device.
  • gallium oxide materials whether it is ion implantation technology or high-temperature oxygen annealing technology, there are currently large technical barriers that need to be broken through in order to better meet the needs of future based on Development of semiconductor devices using gallium oxide materials.
  • the present invention mainly solves the problem that the high-temperature annealing technology in the prior art cannot only process local areas of the gallium oxide material, and cannot regulate the net carrier concentration of the selective area of the gallium oxide material.
  • a method for preparing gallium oxide devices based on high-temperature annealing technology including the following steps:
  • a barrier layer is prepared on the surface of the gallium oxide wafer, and the barrier layer plays a role in blocking the oxygen atmosphere environment during the high-temperature oxygen annealing process;
  • the surface layer of the gallium oxide wafer from which the barrier layer has been stripped is removed.
  • a method for preparing a barrier layer on the surface of a gallium oxide wafer includes the steps:
  • a first barrier layer and a second barrier layer are prepared on the surface of the gallium oxide wafer, the first barrier layer is grown on the surface of the second barrier layer, and the second barrier layer isolates the surface of the gallium oxide wafer from the first barrier layer.
  • Barrier layer, the second barrier layer is a peeling layer.
  • a method for preparing a barrier layer on the surface of a gallium oxide wafer includes the following steps:
  • a first barrier layer and a second barrier layer are prepared on the surface of the gallium oxide wafer; the second barrier layer is located between the surface of the gallium oxide wafer and the first barrier layer, and the patterning rate of the second barrier layer is less than
  • the materials of the first barrier layer and the second barrier layer are selected according to the temperature of the high-temperature oxygen annealing treatment.
  • photolithography or etching is used to pattern the barrier layer.
  • the net carrier concentration is adjusted by adjusting the respective thicknesses or the total thickness of the first barrier layer and the second barrier layer;
  • the net carrier concentration is controlled in the area not covered by the first barrier layer after patterning.
  • the barrier layer is prepared on all surfaces of the gallium oxide wafer.
  • the net carrier concentration is controlled by one or more parameters including annealing temperature, oxygen concentration, and chamber pressure of the annealing equipment.
  • a dry etching method is used to perform a patterning process on the barrier layer, and the etching rate of the second barrier layer is smaller than the etching rate of the second barrier layer.
  • the material of the barrier layer is selected according to the following requirements:
  • the melting point is higher than the annealing temperature
  • a gallium oxide device including a gallium oxide epitaxial layer and/or a gallium oxide substrate that has been regionally controlled through a gallium oxide device preparation method based on high-temperature annealing technology.
  • a method for preparing a gallium oxide device which adopts the above-mentioned method for preparing a gallium oxide device based on high-temperature annealing technology. After the step of removing the surface layer of the gallium oxide wafer from which the barrier layer has been peeled off, it also includes the following steps:
  • An ohmic contact electrode is grown on the back side of the gallium oxide wafer, that is, the gallium oxide substrate layer;
  • Another method for preparing a gallium oxide device is further provided, which adopts a method for preparing a gallium oxide device based on high-temperature annealing technology, and further includes the steps:
  • Another method for preparing a gallium oxide device is further provided, which adopts a method for preparing a gallium oxide device based on high-temperature annealing technology. After removing the barrier layer of the patterned part, the method includes the following steps:
  • the required ions are injected into the gallium oxide epitaxial layer through ion implantation technology to form an ion implantation area, and the injected ions are acceptor impurities or donor impurities;
  • the gallium oxide wafer after the above treatment is annealed in an oxygen atmosphere. Under the high-temperature annealing environment, the ion implantation region forms an implantation region after the implanted impurities are activated, and the gallium oxide substrate and gallium oxide epitaxial layer are formed due to the influence of oxygen annealing. High resistance zone;
  • the surface layer of the gallium oxide wafer from which the barrier layer has been stripped is removed.
  • the damage to the crystal lattice of materials treated by high-temperature oxygen annealing is greatly reduced, which can ensure the quality of the materials and facilitate the subsequent use of the materials in device preparation.
  • high-temperature oxygen annealing technology does not have problems such as ion activation, ion diffusion, and ion distribution patterns, it has fewer technical barriers than ion implantation technology.
  • the process flow of high-temperature oxygen annealing technology is simpler, which reduces costs compared with ion implantation.
  • the annealing technology proposed by the present invention theoretically has a direct correlation between the number of wafers processed at a time and the size of the cavity, and the wafers can be placed vertically during the processing, which greatly improves space utilization and device processing efficiency. .
  • Figure 1 is a flow chart of the method for regulating net carrier concentration disclosed in Embodiment 2;
  • Figure 2 is a flow chart of another method for controlling net carrier concentration disclosed in Embodiment 4.
  • Figure 3 is a flow chart of the anode edge terminal preparation method disclosed in Example 6;
  • FIG. 4 is a flow chart of the method for preparing isolation between devices disclosed in Embodiment 7.
  • Figure 5 is a flow chart of the method for regulating the regional net carrier concentration based on ion implantation technology disclosed in Embodiment 8;
  • a method for preparing a gallium oxide device based on high-temperature annealing technology is a method for controlling the net carrier concentration in a selective region on the gallium oxide material, including process steps:
  • Step 1 Prepare a first barrier layer on the surface of the gallium oxide wafer.
  • the first barrier layer functions to block the high-temperature oxygen atmosphere environment during the high-temperature oxygen annealing process;
  • Step 2 Perform a patterning process on the first barrier layer for the purpose of controlling impurities in the gallium oxide wafer, and the process depth of the patterning process does not exceed the thickness of the first barrier layer;
  • Step 3 anneal the gallium oxide wafer after the above treatment in an oxygen atmosphere
  • Step 4 Remove the first barrier layer of the annealed gallium oxide wafer
  • Step 5 Remove the surface layer of the gallium oxide wafer from which the first barrier layer has been peeled off.
  • the first barrier layer needs to cover the entire gallium oxide wafer surface.
  • the material selection of the first barrier layer includes all high-temperature resistant materials (the reference temperature can be a melting point of not less than 900°C), and elements or compounds that react with oxygen to form new compounds, and the thermal expansion coefficient is not higher than 1 ⁇ 10 -4 /K.
  • Step 2 Specifically, photolithography or etching can be used to pattern the barrier layer; the corresponding area range is designed for the area that needs to be controlled, and the designed area range is oxidized by photolithography or etching.
  • the first barrier layer on the surface of the gallium wafer implements a patterning process for the purpose of controlling impurities in the gallium oxide wafer. To adjust the thickness of the first barrier layer and control the net carrier concentration, it is necessary to ensure that the process depth of the patterning process does not exceed the thickness of the first barrier layer.
  • Step 3 anneal the gallium oxide wafer after the above treatment in an oxygen atmosphere.
  • the material of the first barrier layer is a high-temperature resistant material that meets the melting point not lower than the annealing temperature.
  • the melting point is not lower than the annealing temperature. Lower than annealed material.
  • the selection of the melting point of the high-temperature-resistant material is adaptively adjusted according to the actual requirements during the annealing process. On the basis of this solution, the net carrier concentration control in the gallium oxide selective region can be realized through patterning process + annealing treatment.
  • the prepared gallium oxide wafer sample is placed in a high-temperature equipment for oxygen atmosphere annealing.
  • the reference temperature can be 600-1700°C.
  • even very short annealing times will have an impact on the net carrier concentration of the sample, but the extent of the impact will change with time and temperature.
  • oxygen should be continuously introduced, and the oxygen content in the cavity should not be lower than the oxygen content in the air (21%).
  • Optional additional methods include regulating the net carrier concentration by adjusting the oxygen atmosphere.
  • the oxygen concentration of the general annealing treatment is not lower than the oxygen content in the air, but the net carrier concentration can also be controlled by controlling the oxygen concentration. concentration.
  • the pressure in the cavity of the high-temperature equipment in the above-mentioned annealing process usually uses a standard atmospheric pressure, but the net carrier concentration can also be adjusted by adjusting the air pressure parameters.
  • the annealing time includes the temperature rising and cooling time.
  • the appropriate stop point for oxygen supply can be effectively achieved by selecting an appropriate oxygen supply stop point within the range from 400°C (reference temperature) to the actual annealing temperature. Regulation of net carrier concentration.
  • Step 4 Place the sample that has completed the annealing process into a solution capable of corroding the first barrier layer and perform ultrasound to remove the first barrier layer. Since the first barrier layer will have an oxidized part after being annealed in an oxygen atmosphere, the first barrier layer after step 3 is an element or compound formed by oxygen reaction to form a new compound. Therefore, it is preferable to choose relevant solutions that can dissolve raw materials and oxidizing substances.
  • Step 5 According to the application scenario, remove and repair the front and back surfaces of the gallium oxide material after removing the first barrier layer in sequence.
  • the etching depth of the side with the epitaxial material or the side that has undergone the barrier layer patterning process is within the range. 0-1 ⁇ m, the etching depth range of the surface without epitaxial material is 0-10 ⁇ m.
  • the range of surface removal thickness can be adjusted according to different application scenarios.
  • the surface layer can also be removed by uniformly thinning the material such as chemical mechanical polishing, with a thickness similar to that of etching.
  • the treated material surface is repaired through wet etching technology.
  • the reaction rate between the repair solution and the gallium oxide material is not higher than 100nm/min.
  • the thickness of the first barrier layer does not exceed 100 microns to prevent the barrier layer from experiencing large vertical deformation due to thermal expansion during the subsequent high-temperature annealing process, causing the barrier layer to fall off.
  • the thickness requirement of the first barrier layer is the current test requirement for gallium oxide samples, and other parameters are not excluded.
  • the material of the first barrier layer selected in Embodiment 1 generally needs to be removable by a certain solution, and the reaction rate between this solution and the gallium oxide material does not exceed 10 nm/min.
  • the reaction rate between this solution and the gallium oxide material does not exceed 10 nm/min.
  • this embodiment discloses a method for preparing a gallium oxide device. Referring to Figure 1, it includes process steps:
  • Step 1' prepare a first barrier layer 10 and a second barrier layer 20 on the surface of the gallium oxide wafer.
  • the first barrier layer 10 plays a role in blocking the high-temperature oxygen atmosphere environment during the high-temperature oxygen annealing process.
  • the second barrier layer 20 is a peeling layer, which plays the role of peeling off the first barrier layer 10 after annealing; wherein the gallium oxide wafer includes a gallium oxide substrate layer 40 and a gallium oxide epitaxial layer 30;
  • Step 2' perform a patterning process for the purpose of controlling gallium oxide impurities on the first barrier layer 10 and the second barrier layer 20.
  • the process depth of the patterning process does not exceed the first barrier layer. 10 plus the thickness of the second barrier layer 20; specifically, it cannot exceed the depth of the second barrier layer 20, that is, the process depth is greater than or equal to the thickness of the first barrier layer 10, but less than the total thickness of the first barrier layer 10 and the second barrier layer 20 .
  • the first barrier layer in the patterning process area 10-1 may not be completely removed to adjust the net carrier concentration in this area.
  • Step 3' as shown in Figure 1-c, the gallium oxide after the above treatment is annealed in an oxygen atmosphere to form an annealed net carrier concentration control layer 30-1; as shown in Figure 1-c after the patterning process Partial areas of the first barrier layer are etched.
  • the gallium oxide epitaxial layer that retains the first barrier layer and the gallium oxide epitaxial layer that removes the first barrier layer are affected by the annealing process to different depths.
  • the gallium oxide epitaxial layer that retains the first barrier layer The depth of influence of the gallium oxide epitaxial layer is shallower;
  • Step 4' peel off the first barrier layer 10 and the second barrier layer 20 of the annealed gallium oxide; then remove the gallium oxide crystal after peeling off the first barrier layer 10 and the second barrier layer 20. Round surface layer.
  • the first barrier layer 10 is made of a high-temperature-resistant material whose melting point is not lower than the annealing temperature.
  • a material whose melting point is not lower than the annealing temperature is used.
  • the selection of the melting point of the high-temperature-resistant material is adaptively adjusted according to the actual requirements during the annealing process.
  • the material of the second barrier layer 20 has a melting point higher than the annealing temperature, and is easily removed by solutions such as hydrofluoric acid, concentrated sulfuric acid, hydrochloric acid, and nitric acid that have minimal impact on the surface quality of the gallium oxide material.
  • the material of the second barrier layer 20 also has a low thermal expansion coefficient to avoid falling off during the annealing process.
  • the small impact on the surface of the gallium oxide material can be referenced as the corrosion rate is less than 10nm/min, and the low thermal expansion coefficient can be referenced as not higher than 1 ⁇ 10 -4 /K.
  • the parameters in this solution are only for implementation reference and are not specific limitations.
  • the total thickness of the first barrier layer 10 and the second barrier layer 20 does not exceed 100 microns. Preferably it is no more than 10 microns.
  • Step 5' as shown in Figure 1-e, according to the application scenario, the gallium oxide material after removing the first barrier layer 10 is sequentially removed and repaired on the front and back surfaces of the material, with the epitaxial material surface or barrier layer patterning process
  • the etching depth of the side is in the range of 0-1 ⁇ m, and the etching depth of the side without the epitaxial material is in the range of 0-10 ⁇ m.
  • the part of the gallium oxide epitaxial portion of the first barrier layer that is retained before the annealing treatment in the previous step and is affected by the annealing treatment is removed.
  • This embodiment provides a method for preparing a gallium oxide device based on high-temperature annealing technology.
  • the barrier layer it is different from Embodiment 1 and Embodiment 2.
  • a first barrier layer and a second barrier layer are prepared on the surface of the gallium oxide wafer;
  • the second barrier layer is located between the surface of the gallium oxide wafer and the first barrier layer.
  • the patterning rate of the second barrier layer is smaller than that of the first barrier layer.
  • the second barrier layer is selected according to the temperature of the high-temperature oxygen annealing process.
  • a barrier layer and the material of the second barrier layer is selected according to the temperature of the high-temperature oxygen annealing process.
  • this embodiment adds a second barrier layer as an etching stop layer
  • this embodiment adds a second barrier layer.
  • the material of the second barrier layer it must satisfy the functions of the stripping layer and the etching stop layer at the same time.
  • this embodiment discloses a method for preparing a gallium oxide device, which specifically includes a net carrier concentration control method, including process steps:
  • Step 1 prepare a first barrier layer and a second barrier layer on the surface of the gallium oxide wafer.
  • the first barrier layer plays a role in blocking the high-temperature oxygen atmosphere environment during the high-temperature oxygen annealing process;
  • the second barrier layer is peeled off layer and etching stop layer, please refer to Embodiment 2 for the technical solution as the peeling layer.
  • This embodiment mainly discloses the technical solution as the etching stop layer.
  • Step 2 perform a patterning process for the purpose of controlling gallium oxide impurities on the first barrier layer and the second barrier layer, and the process depth of the patterning process does not exceed the thickness of the first barrier layer plus the second barrier layer; Specifically, the depth of the second barrier layer cannot be exceeded, that is, the process depth is greater than or equal to the thickness of the first barrier layer and less than the total thickness of the first barrier layer and the second barrier layer.
  • the dry etching process as the patterning process is specifically described as follows: the first barrier layer is on the surface of the second barrier layer, and the first barrier layer is etched through the dry etching process.
  • the etching rate will decrease depending on the material. Therefore, the etching process can set a large etching time redundancy to ensure that this etching step will not affect the surface of the gallium oxide material.
  • Embodiment 3 it can be known that the technology regarding the etching stop layer disclosed in Embodiment 3 can be combined with Embodiment 1 and Embodiment 2 respectively to form two technical solutions.
  • This embodiment provides a material example of the first barrier layer and the second barrier layer.
  • SiO 2 is used as the second barrier layer and the Si layer is used as the first barrier layer.
  • SiO 2 is a substance that is easy to remove through hydrofluoric acid, concentrated sulfuric acid, hydrochloric acid, nitric acid and other solutions that have minimal impact on the surface quality of gallium oxide materials. . It can be used to peel off the Si layer after oxidation. At the same time, it has a low expansion coefficient to avoid falling off during the annealing process.
  • the Si layer is grown on the SiO 2 film, and the Si layer is etched by dry etching.
  • the rate is slower than the rate of etching the Si layer, thus achieving a larger etching process.
  • the etching time is redundant to ensure that this etching step will not affect the surface of the gallium oxide material.
  • the thickness of the SiO 2 layer should not be less than 5nm.
  • a method for preparing gallium oxide devices based on high-temperature annealing technology includes the following steps:
  • Step 100 as shown in Figure 2-a:
  • the material of the first barrier layer 10 is preferably Si
  • the material of the second barrier layer 20 is preferably SiO 2 .
  • the PECVD process and the LPCVD process are used to grow the SiO 2 layer and the Si layer respectively on the surface of the gallium oxide wafer.
  • the Si layer plays the role of blocking the oxygen atmosphere, and the SiO 2 layer plays the role of peeling off the Si layer.
  • the total thickness of the SiO 2 layer and the Si layer does not exceed 100 microns, preferably no more than 10 microns, to prevent the barrier layer from experiencing large vertical deformation due to thermal expansion during the subsequent high-temperature annealing process, causing the barrier layer to fall off.
  • the Si layer needs to cover all surfaces of the gallium oxide wafer, it is preferable to choose a growth method such as the LPCVD process that can cover the entire gallium oxide wafer sample surface with a single growth.
  • the depth of the patterning process is greater than the thickness of the Si layer and less than the total thickness of the two layers of materials, that is, for the preset patterned area 10-1 , remove the Si layer in the patterned area and retain some or all of the SiO 2 .
  • the Si layer in the patterning process area may not be completely removed to adjust the net carrier concentration in this area.
  • the SiO 2 layer can also function as a layer to adjust the net carrier concentration of the material. Further, the thickness of the SiO 2 layer can be adjusted to achieve regulation of the net carrier concentration of the material in the area without the Si barrier layer within a certain range.
  • etching technology includes dry etching and wet etching, that is, using etching plasma or etching solution to perform patterning process operations on gallium oxide wafers.
  • the pattern accuracy of dry etching is higher than that of wet etching. High, in order to ensure pattern accuracy, dry etching is preferred.
  • Step 300 as shown in Figure 2-c:
  • the gallium oxide wafer sample prepared according to the method of steps 100 to 200 in a high-temperature equipment (such as an annealing furnace) for oxygen atmosphere annealing at 600-1700°C.
  • a high-temperature equipment such as an annealing furnace
  • oxygen should be continuously introduced, and the oxygen content in the cavity should not be lower than the oxygen content in the air (21%).
  • the pressure in the high-temperature equipment cavity uses a standard atmospheric pressure.
  • the annealing time includes the heating and cooling time. During cooling, the net load can be effectively controlled by selecting an appropriate stop oxygen supply point within the range of 400°C to the actual annealing temperature. Control of current concentration. A region of low net carrier concentration 30-1 appears that is regulated regionally;
  • Control of the net carrier concentration is achieved by intermittently stopping the oxygen supply during annealing and introducing other gases to assist adjustment;
  • the net carrier concentration of the gallium oxide wafer sample is controlled
  • the net carrier concentration of the gallium oxide wafer sample can be controlled by adjusting the air pressure parameters
  • the gallium oxide wafer sample that has completed the annealing process is placed in a solution that can corrode SiO 2 and ultrasonicated to remove the barrier layer.
  • the second barrier layer is a peeling layer; because the alkaline solution used to remove the Si material will react with gallium oxide, causing damage to the surface quality of the gallium oxide material; therefore, it is necessary to choose a non-alkaline solution, and a non-alkaline solution is required for annealing
  • the removal effect of the Si/SiO 2 mixed layer after treatment is not ideal, so as a preference of Embodiment 1, a second barrier layer is added in this solution to function as a peeling layer. This ensures that the second barrier layer can quickly react and dissolve in a non-alkaline solution, solving the problem that the first barrier layer is not easy to peel off, or the peeling solution easily damages the gallium oxide material.
  • Step 500 is shown in Figure 2-e:
  • the gallium oxide material after removing the Si/SiO 2 barrier layer is sequentially removed and repaired on the front and back surfaces of the material.
  • the etching depth of the side with the epitaxial material or the side that has been patterned with the barrier layer is in the range 0- 1 ⁇ m, the etching depth range of the surface without epitaxial material is 0-10 ⁇ m.
  • the surface layer can also be removed by uniformly thinning the material such as chemical mechanical polishing, with a thickness similar to that of etching.
  • the treated material surface is repaired through wet etching technology.
  • the reaction rate between the repair solution and the gallium oxide material should not be higher than 100nm/min.
  • the wafer used in this case is a single-crystal (001) ⁇ -phase gallium oxide.
  • the wafer includes a high doping concentration ( ⁇ 10 18 cm -3 ) gallium oxide substrate in the (001) crystal orientation, and a A 9 ⁇ m single-crystal ⁇ -phase gallium oxide epitaxial film with low doping concentration ( ⁇ 10 16 cm -3 ) grown on it by halide vapor phase epitaxy (HVPE).
  • HVPE halide vapor phase epitaxy
  • Figure 2-a 150nm SiO 2 is grown on a gallium oxide film through PECVD, where SiO 2 simultaneously serves as an etching stop layer, a stripping layer, and a net carrier concentration control layer. Subsequently, 400 nm polycrystalline Si was continued to grow through LPCVD as an oxygen atmosphere barrier layer. Due to the growth characteristics of LPCVD, polycrystalline Si will cover the entire gallium oxide wafer material surface.
  • the barrier layer with epitaxial gallium oxide surface is patterned through photolithography technology and reactive ion etching (RIE) technology.
  • RIE reactive ion etching
  • the so-called patterning process is to select the area where the net carrier concentration needs to be changed. This part of the area removes the Si barrier layer and can also remove part of the SiO 2 group as an error range, which can also be used as a magazine concentration control requirement.
  • the patterned gallium oxide wafer is placed in an annealing furnace for annealing.
  • the oxygen flow rate is 3000 sccm
  • the pressure in the cavity is one standard atmospheric pressure
  • the temperature of the cavity is controlled at 1100°C
  • the heating time is 2 hours
  • the cooling time is 2.5 hours to 500°C. Keep oxygen flowing during the annealing process, and stop feeding oxygen when the temperature drops to 500°C.
  • Figure 2-d shows the gallium oxide wafer after annealing, which was ultrasonically cleaned in HF acid for 20 minutes to remove the SiO 2 /Si barrier material. And wash it with acetone, isopropyl alcohol, and deionized water in sequence.
  • an inductively coupled plasma etching machine is used to etch the back and front sides (with epitaxial layers) of the wafer in sequence.
  • the front etching is 600nm and the back etching is 1 ⁇ m.
  • An alternative to chemical mechanical polishing (CMP) can be used.
  • CMP chemical mechanical polishing
  • the etching process needs to be selectively implemented according to the actual application scenario, and there is no restriction. The description of this solution is only for reference implementation.
  • This embodiment further enumerates a method for preparing a gallium oxide device, specifically a method for preparing a gallium oxide device.
  • An anode edge terminal preparation method refer to Figure 3, using photoresist as the etching cover layer of the patterning process, the specific steps are as follows:
  • Step 3-a prepare a gallium oxide wafer, which includes a gallium oxide substrate 40 and a gallium oxide epitaxial layer 30;
  • Step 3-b grow a SiO 2 layer 20 on the surface of the gallium oxide epitaxial layer, which is used to peel off the Si layer and/or serve as an etching stop layer;
  • Step 3-c grow a Si layer 10 (polysilicon layer) on the surface of the SiO 2 layer and all surfaces of the gallium oxide wafer to block the high-temperature oxygen atmosphere.
  • the LPCVD process can be used;
  • Step 3-d spin-coat photoresist 50 on the Si layer surface at one end of the gallium oxide epitaxial layer for patterning process
  • Step 3-e expose and develop the area where the net carrier concentration needs to be changed to pattern the photoresist
  • Step 3-f use an etching process to remove the Si layer of the barrier layer in the patterned part, and wash away the photoresist 50;
  • Step 3-g annealing treatment for 8 hours, annealing atmosphere: 1100°C, one standard atmospheric pressure, oxygen flow rate 3000sccm, cavity space of annealing equipment is 0.04m 3 ; at this time, the original Si layer becomes Si/SiO due to oxygen atmosphere annealing 2 mixture layer; in the gallium oxide epitaxial region, low net carrier concentration regions 30-1 appear in different regions;
  • Step 3-h use BOE solution to remove the barrier layer by wet method.
  • the barrier layer here refers to the Si/SiO 2 mixture layer and SiO 2 layer after the return process;
  • Step 3-i use ICP etching to etch 1 ⁇ m on the back of the gallium oxide wafer;
  • Step 3-j use ICP etching to etch 600nm on the back of the gallium oxide wafer, and then soak it in piranha solution for 10-20 minutes
  • Step 3-k use physical vapor deposition technology to grow the ohmic contact electrode Ti/Au 60 on the back side of the gallium oxide wafer, that is, the gallium oxide substrate layer;
  • Step 3-l spin-coat photoresist on the front side of the gallium oxide wafer, that is, the surface of the gallium oxide epitaxial layer;
  • Step 3-m expose and develop the photoresist to pattern the photoresist, which is different from the patterning of step 3-e.
  • This step is used to grow the electrode, based on the low net carrier concentration formed in step 3-g.
  • Area 30-1 is the graphical area for this step of area design;
  • Step 3-n using physical vapor deposition technology to grow the Schottky electrode 70;
  • Step 3-o remove excess metal from the Schottky electrode and clean the photoresist.
  • the gallium oxide wafer with epitaxial film can also be replaced by a gallium oxide substrate without epitaxial film, or on other substrates (such as sapphire, Si, GaN, SiC, etc.), or on a substrate with epitaxial layer Amorphous, polycrystalline or single crystal gallium oxide material grown on a GaN substrate with AlGaN on the bottom), and the rest of the process remains unchanged.
  • the above-mentioned physical vapor deposition technology is, for example, electron beam evaporation technology.
  • this embodiment further provides a new gallium oxide device preparation method, specifically an isolation method between semiconductor devices.
  • photoresist is used as the etching cover layer in the patterning process. (Other materials can also be used), the specific steps are as follows:
  • Step 4-a prepare a gallium oxide wafer, which includes a gallium oxide substrate 40 and a gallium oxide epitaxial layer 30;
  • Step 4-b grow a SiO 2 layer 20 on the surface of the gallium oxide epitaxial layer, which is used to peel off the Si layer and/or serve as an etching stop layer;
  • Step 4-c grow a Si layer 10 (polysilicon layer) on the surface of the SiO 2 layer and all surfaces of the gallium oxide wafer to block the high-temperature oxygen atmosphere.
  • the LPCVD process can be used;
  • Step 4-d spin-coat photoresist on the Si layer surface at one end of the gallium oxide epitaxial layer for patterning process
  • Step 4-e expose and develop the area on the front of the wafer where the net carrier concentration needs to be changed to pattern the photoresist;
  • Step 4-f use an etching process to remove the Si layer of the barrier layer in the patterned part, specifically the area on the wafer used for device preparation, as shown in the figure in the middle part of the gallium oxide wafer, and wash away the photoresist;
  • Step 4-g spin-coat photoresist on the Si layer surface at one end of the gallium oxide substrate for patterning process
  • Step 4-h similar to step 4-e, expose and develop the area on the back of the wafer where the net carrier concentration needs to be changed to pattern the photoresist, and the area on the wafer used for device preparation;
  • Step 4-i use etching technology to remove the Si layer of the back barrier layer, and wash away the photoresist; now the Si layer has been patterned on both the front and back of the gallium oxide wafer, that is, the middle area is used as a selective control position ;
  • Step 4-j annealing treatment for 8 hours, annealing atmosphere: 1150°C, one standard atmospheric pressure, oxygen flow rate 3000sccm, cavity space of annealing equipment is 0.04m 3 ; at this time, the original Si layer becomes Si/SiO due to oxygen atmosphere annealing 2.
  • Step 4-k use BOE solution to remove the barrier layer by wet method.
  • the barrier layer here refers to the Si/SiO 2 mixture layer after the return process, and the SiO 2 layer;
  • Step 4-i use ICP etching to etch 1 ⁇ m on the back of the gallium oxide wafer; use ICP etching to etch 600 nm on the back of the gallium oxide wafer, and then soak it in piranha solution for 10-20 minutes to repair the wafer Surface etching damage.
  • Example 6 Before the second annealing, the last step of surface layer removal treatment in Example 6 is a necessary process.
  • Others such as local area passivation and conductivity control on the semiconductor surface, design of the internal current blocking layer of the vertical structure MOSFET device, etc. can all be derived based on the above embodiments.
  • the annealing time of each application needs to be adjusted according to the needs, and there are differences.
  • Others include changing the thickness of the SiO 2 layer, changing the thickness of the polycrystalline Si layer, changing the annealing temperature, and oxygen as mentioned above. Concentration, chamber pressure and other parameters to match the design method. For example: If you need to obtain a lower net carrier concentration and a deeper low net carrier concentration area, you can increase the annealing time, increase the oxygen concentration, increase the pressure, and reduce the thickness of SiO 2 . or multiple controls. On the contrary, the trend of using control methods is opposite.
  • This embodiment provides a process in which the barrier layer structure functions when high-temperature impurities are activated by ion implantation technology. Discloses a net carrier concentration control process based on ion implantation technology, as shown in Figure 5,
  • Step 5-a prepare a gallium oxide wafer, which includes a gallium oxide substrate 40 and a gallium oxide epitaxial layer 30;
  • Step 5-b complete the following process: 1) grow a SiO 2 layer 20 on the surface of the gallium oxide epitaxial layer, which is used to peel off the Si layer and/or serve as an etching stop layer; 2) grow a SiO 2 layer 20 on the surface of the SiO 2 layer and the gallium oxide crystal A Si layer 10 (polycrystalline silicon layer) is grown on all surfaces of the circle to block the high-temperature oxygen atmosphere. Specifically, the LPCVD process can be used; 3) Photoresist 50 is spin-coated on the surface of the Si layer at one end of the gallium oxide epitaxial layer for patterning process;
  • Step 5-c expose and develop the area where the net carrier concentration needs to be changed to pattern the photoresist
  • Step 5-d use an etching process to remove the patterned portion of the barrier layer Si layer and SiO 2 layer 20;
  • Step 5-e Inject the required ions into the gallium oxide epitaxial layer 30 through ion implantation technology to form the ion implantation region 60.
  • the injected ions are acceptor impurities (Mg or N); they can also be donor impurities;
  • Step 5-f remove photoresist
  • Step 5-g annealing treatment for 8 hours, annealing atmosphere: 1100°C, one standard atmospheric pressure, oxygen flow rate 3000sccm, cavity space of the annealing equipment is 0.04m 3 ; in a high-temperature annealing environment, the ion implantation area 60 forms an implantation after activation of impurities region 70, and is affected by oxygen annealing so that the gallium oxide substrate 40 and the gallium oxide epitaxial layer 30 form a high-resistance region 80;
  • Step 5-h remove the barrier layer, where the barrier layer refers to the annealed Si/SiO 2 mixture layer and the SiO 2 layer;
  • Step 5-i use ICP etching to remove the affected surface layer of the gallium oxide wafer.
  • annealing in a nitrogen or argon atmosphere is usually used for impurity activation treatment and lattice repair.
  • Oxygen atmosphere annealing itself will affect the net carrier concentration of the material, so it has not been suitable as an annealing atmosphere activated by injected impurities.
  • the oxygen atmosphere barrier layer structure proposed in the present invention can effectively isolate the influence of oxygen on the net carrier concentration of the gallium oxide material, making it possible for oxygen atmosphere annealing to be used to activate implanted impurities.

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Abstract

一种基于高温退火技术的氧化镓器件制备方法及氧化镓器件，所述方法包括：在氧化镓晶圆表面制备阻挡层，所述阻挡层起在高温氧退火过程中阻挡高温氧氛围环境的作用；对阻挡层实施以氧化镓晶圆杂质调控目的的图形化工艺，所述图形化工艺的工艺深度不超过阻挡层厚度；对经上述处理的氧化镓晶圆在氧氛围退火处理；去除退火处理后的氧化镓晶圆的阻挡层；去除已剥离所述阻挡层的氧化镓晶圆的表面层。

Description

基于高温退火技术的氧化镓器件制备方法及氧化镓器件 技术领域
本发明涉及半导体材料加工技术，尤其涉及一种基于高温退火技术的氧化镓器件制备方法及氧化镓器件。
背景技术
当前针对于氧化镓材料的选择性区域净载流子浓度调控主要是通过离子注入来实现。如掺入Si，Sn，Ge等施主杂质提高净载流子浓度，掺入Fe、Mg、N等受主杂质以补偿自由电子从而降低净载流子浓度。但是无论是从经济上还是技术特点上，氧化镓材料的离子注入技术都存在较多的挑战。首先，经济上而言，离子注入技术的成本很高。除了需要使用功率极高的发射高能量离子的设备外，还需要进行进一步高温退火处理，以激活注入离子和修复高能离子对材料所带来的损伤，这两步工艺都存在极大的能源消耗。就氧化镓材料离子注入的技术特点而言，注入离子的激活效率当前不明确；材料中较深位置的注入难以实现；注入离子存在扩散，精确的剂量难以控制，并且注入后的离子的分布规律目前没有准确的结论；注入后引起材料的缺陷类型和分布规律不明确；以及缺陷的修复技术还不成熟等技术壁垒都极大地阻碍着离子注入技术的应用。
除了离子注入以外，另一种改变氧化镓材料电导率的方式是高温氧退火处理。但是高温氧退火处理会影响到材料整体的电导率，并不能对材料上的选择性地处理某一个区域，这限制了这种技术地应用范围。
因此针对于氧化镓材料的选择性区域净载流子浓度调控技术，无论是离子注入技术还是高温氧退火技术在当前都还存在较大的技术壁垒需要突破，才能更好地满足于未来的基于氧化镓材料的半导体器件发展。
发明内容
本发明主要解决现有技术下高温退火技术下无法只针对氧化镓材料局部区域处理，无法对氧化镓材料选择性区域净载流子浓度调控的问题。
为了解决上述技术问题，本发明通过下述技术方案得以解决：
一种基于高温退火技术的氧化镓器件制备方法，包括以下步骤：
在氧化镓晶圆表面制备阻挡层，所述阻挡层起到在高温氧退火过程中阻挡氧氛围环境的作用；
对阻挡层实施以氧化镓晶圆杂质调控为目的的图形化工艺，所述图形化工艺的工艺深度不超过所述阻挡层厚度；
对经上述处理后的氧化镓晶圆在氧氛围退火处理；
去除退火处理后的氧化镓晶圆的阻挡层；
去除已剥离所述阻挡层的氧化镓晶圆的表面层。
作为一种优选方案，在氧化镓晶圆表面制备阻挡层的方法包括步骤：
在氧化镓晶圆表面制备第一阻挡层和第二阻挡层，在所述第二阻挡层表面生长第一阻挡层，所述第二阻挡层隔离所述氧化镓晶圆表面和所述第一阻挡层，所述第二阻挡层为剥离层。
作为一种优选方案，在氧化镓晶圆表面制备阻挡层的方法包括步骤：
在氧化镓晶圆表面制备第一阻挡层和第二阻挡层；所述第二阻挡层位于氧化镓晶圆表面和所述第一阻挡层之间，所述第二阻挡层的图形化速率小于所述第一阻挡层，根据高温氧退火处理的温度选择所述第一阻挡层和所述第二阻挡层的材料。
作为一种优选方案，采用光刻或刻蚀的方法对阻挡层进行图形化工艺。
作为一种优选方案，通过调整第一阻挡层和第二阻挡层的各自厚度或总厚度，调控净载流子浓度；
或，通过调整第二阻挡层的厚度，对图形化后没有所述第一阻挡层覆盖的区域做净载流子浓度的调控。
作为一种优选方案，所述阻挡层被制备在氧化镓晶圆的所有表面。
作为一种优选方案，通过退火温度、氧气浓度、退火设备腔体压强中的一种或多种参数调控净载流子浓度。
作为一种优选方案，采用干法刻蚀的方法对所述阻挡层实施图形化工艺，所述第二阻挡层的刻蚀速率小于所述第二阻挡层的刻蚀速率。
作为一种优选方案，所述阻挡层的材质根据以下要求进行选择：
熔点高于退火温度；
能够被与氧化镓材料表面反应速率慢溶液去除。
进一步的，基于上述方法，提供一种氧化镓器件，包括经过如基于高温退火技术的氧化镓器件制备方法实施过区域性调控的氧化镓外延层和/或氧化镓衬底。
一种氧化镓器件制备方法，采用上述基于高温退火技术的氧化镓器件制备方法，在去除已剥离所述阻挡层的氧化镓晶圆的表面层的步骤之后，还包括步骤：
在所述氧化镓晶圆背面，即氧化镓衬底层生长欧姆接触电极；
在所述氧化镓晶圆正面，即氧化镓外延层表面旋涂光刻胶；
对光刻胶曝光、显影使光刻胶图形化，用于生长电极，在低净载流子浓度区设计本步骤的图形化区域；
采用物理气相沉积技术发生长肖特基电极；
去除肖特基电极的多余金属，并清洗光刻胶。
进一步提供另一种氧化镓器件制备方法，采用基于高温退火技术的氧化镓器件制备方法，还包括步骤：
将晶圆正面和晶圆背面需要改变净载流子浓度的区域图形化，具体为晶圆上的用于器件制备区域。
进一步提供另一种氧化镓器件制备方法，采用基于高温退火技术的氧化镓器件制备方法，在去除图形化部分的阻挡层之后，包括步骤：
通过离子注技术在氧化镓外延层注入所需的离子，形成离子注入区，注入离子为受主杂质或施主杂质；
对经上述处理后的氧化镓晶圆在氧氛围退火处理，高温退火环境下，离子注入区形成所注入杂质激活后的注入区，以及受氧退火影响使得氧化镓衬底和氧化镓外延层形成高阻区；
去除退火处理后的氧化镓晶圆的阻挡层；
去除已剥离所述阻挡层的氧化镓晶圆的表面层。
本发明的有益效果：
1)首先，氧退火技术对氧化镓净载流子浓度的影响几乎可以深入到材料内部1mm以上，因此，以氧氛围退火技术结合图形化工艺可以解决离子注入技术在氧化镓中深区注入的困难。
其次，高温氧退火处理后的材料相较于离子注入而言，对晶格的损伤程度极大降低，可以保证材料的质量，有利于材料后续用于器件制备。此外，由于高温氧退火技术不存在离子激活，离子扩散，离子分布规律等问题，相较于离子注入技术而言技术壁垒更少。最后，高温氧退火技术的工艺流程更简单，相较于离子注入而言缩减了成本。
2)高温氧退火技术的技术壁垒是没有合适的阻挡层，使得其无法只针对于某个区域材料的净载流子浓度进行调控，这极大地限制了这种特殊处理方式的应用场景。本发明解决了这个问题。
3)对于不需要高度精确的净载流子浓度调控应用场景，如高阻终端，电流阻挡层，器件隔离等。该方法相较于离子注入技术有极大的成本优势。其一是因为本所发明方法中所使用的设备相较于离子注入机而言成本更低；其二是离子注入只能单片进行，并且其效率受限于设备所能处理的最大晶圆数量，晶圆必须水平放置，空间利用率很低。而本发明提出的退火 技术理论上单次处理晶片的数量和腔体的大小直接相关，且处理过程中晶圆可以垂直放置，这就极大提高了空间利用率，器件加工效率得到极大提升。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是实施例2披露的净载流子浓度调控的方法的流程图；
图2是实施例4披露的另一种净载流子浓度调控的方法的流程图；
图3是实施例6披露的阳极边缘终端制备方法的流程图；
图4是实施例7披露的器件间隔离制备方法的流程图。
图5是实施例8披露的基于离子注入技术的区域净载流子浓度调控的方法的流程图；
10-第一阻挡层，20-第二阻挡层，30-氧化镓外延层，40氧化镓，50光刻胶层，30-1，退火处理后的净载流子浓度调控层，60-欧姆接触电极，70-肖特基接触电极。
具体实施方式
除非另作定义，本申请使用的技术术语或者科学术语应当为本领域技术人员所理解的
通常意义。本申请说明书以及权利要求书中使用的术语“第一”、“第二”、“第三”、“第四”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。
由此，限定有“第一”、“第二”、“第三”、“第四”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。“左”、“右”、“上”以及“下”等方位术语是相对于附图中的示意放置的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据方位的变化而相应地发生变化。下面结合本申请实施例中的附图对本申请实施例进行描述。以下描述中，参考形成本申请一部分并以说明之方式示出本申请实施例的具体方面或可使用本申请实施例的具体方面的附图。应理解，本申请实施例可在其它方面中使用，并可包括附图中未描绘的结构或逻辑变化。因此，以下详细描述不应以限制性的意义来理解，且本申请的范围由所附权利要求书界定。另外，还应理解的是，除非另外明确提出，本文中所描述的各示例性实施例和/或方面的特征可以相互组合。
实施例1：
一种基于高温退火技术的氧化镓器件制备方法，是在氧化镓材料上选择性区域的净载流子浓度调控的方法，包括工艺步骤：
步骤1，在氧化镓晶圆表面制备第一阻挡层，所述第一阻挡层起在高温氧退火过程中阻挡高温氧氛围环境的作用；
步骤2，对第一阻挡层实施以氧化镓晶圆杂质调控目的的图形化工艺，所述图形化工艺的工艺深度不超过所述第一阻挡层厚度；
步骤3，对经上述处理后的氧化镓晶圆在氧化镓晶圆在氧氛围退火处理；
步骤4，去除退火处理后的氧化镓晶圆的第一阻挡层；
步骤5，去除已剥离所述第一阻挡层的氧化镓晶圆的表面层。
其中，步骤1，在实际操作过程中，由于退火氛围对材料的影响是360度全方位的，因此第一阻挡层需要覆盖到整个氧化镓晶圆表面。除了通过多次生长的工艺方法以外，优选的采用如LPCVD工艺，通过一次生长而使薄膜覆盖到整个氧化镓晶圆表面的生长方式，有利于缩减成本。在第一阻挡层的材料选择上包括所有耐高温材料(参考温度可以是熔点不低于900℃)，且与氧气反应形成新的化合物的单质或化合物，热膨胀系数不高于1×10 -4/K。
步骤2，具体的可采用光刻或刻蚀的方法对阻挡层进行图形化工艺；对需要进行调控的区域设计相应的区域范围，对设计好的区域范围通过光刻或刻蚀的方法将氧化镓晶圆表面的第一阻挡层实施以氧化镓晶圆杂质调控目的的图形化工艺。调整第一阻挡层厚度，调控净载流子浓度，需要保证图形化工艺的工艺深度不超过第一阻挡层的厚度。
步骤3，对经上述处理后的氧化镓晶圆在氧化镓晶圆在氧氛围退火处理，第一阻挡层的选材为耐高温材料，满足熔点不低于退火温度，本实施例中采用熔点不低于退火的材料。耐高温材料的熔点的选择根据退火处理过程中的实际要求做适应性调整。在本方案的基础上，可以实现通过图形化工艺+退火处理实现氧化镓选择性区域的净载流子浓度调控。
具体的，将准备好的氧化镓晶圆样品置于高温设备中氧氛围退火处理。参考温度可以为进行600-1700℃。理论上即使非常短的退火时间都会对样品的净载流子浓度产生影响，但是影响的程度会随着时间和温度而改变。退火过程中，保持持续通入氧气，且腔体内的氧气含量应该不低于空气中氧气含量(21％)。
可选的其他的附加方法还包括通过调整氧氛围调控净载流子浓度，例如1)一般退火处理的氧气浓度不低于空气中氧气含量，但也可以通过控制氧气的浓度调控净载流子浓度。
又例如2)上述退火处理中高温设备的腔体内的压强通常使用一个标准大气压，但也可通过调节气压参数来对净载流子浓度进行调控。3)另一方面退火处理中还需要注意的是退火时间包括升降温时间，其中降温时，通过在400℃(参考温度)到实际退火温度这个范围内 选择合适的停止供氧点可以有效实现对净载流子浓度的调控。4)还可以考虑退火处理中途间断性停止供氧，以及通入其他气体辅助调节的工艺手段。在此不一一例举。
步骤4，将完成退火处理工艺的样品置入能够腐蚀第一阻挡层的溶液中超声以去除该第一阻挡层。由于第一阻挡层在经过氧氛围退火处理之后会有氧化部分，经过第3步的第一阻挡层是氧气反应形成新的化合物的单质或化合物。故优选的，选择能溶解原材料和氧化物质的相关溶液。
步骤5，根据应用场景，对去除第一阻挡层后的氧化镓材料依次进行材料正反面表面的去除和修复处理，带外延材料面或进行过阻挡层图形化工艺的一面的刻蚀深度为范围0-1μm，不带外延材料面刻蚀深度范围为0-10μm。根据不同的应用场景又可以调整表面去除厚度的范围。除刻蚀外，还可通过化学机械抛光等均匀减薄材料的方式去除表面层，厚度和刻蚀类似。最后通过湿法腐蚀技术对处理完的材料表面进行修复，修复溶液和氧化镓材料的反应速率不高于100nm/min。
本实施例中，第一阻挡层的厚度不超过100微米，以防止阻挡层在后续高温退火过程中因热膨胀产生较大的垂直形变，致使阻挡层脱落。该第一阻挡层的厚度要求是当下氧化镓样品的试验要求，不排除其他参数。
实施例2：
在实施例1中选择的第一阻挡层的材料一般需要满足其可以通过某种溶液去除，且这种溶液和氧化镓材料的反应速率不超10nm/min。当存在剥离第一阻挡层出现困难，如第一阻挡层在退火工艺过程中产生杂质导致采用溶液剥离困难，会有杂质残留，或存在剥离第一阻挡层出现所用溶液与氧化镓材料会产生反应，或存在该种溶液成本过高，则提供了一种新的实施方式，通过增加剥离层保证氧化镓材料表面质量的情况下有效去除第一阻挡层。
基于上述原因，本实施例披露一种氧化镓器件制备方法，参照图1，包括工艺步骤：
步骤1’，如图1-a，在氧化镓晶圆表面制备第一阻挡层10和第二阻挡层20，所述第一阻挡层10起在高温氧退火过程中阻挡高温氧氛围环境的作用；所述第二阻挡层20为剥离层，起退火处理后剥离所述第一阻挡层10的作用；其中氧化镓晶圆包括氧化镓衬底层40和氧化镓外延层30；
步骤2’，如图1-b，对第一阻挡层10和第二阻挡层20实施以氧化镓杂质调控目的的图形化工艺，所述图形化工艺的工艺深度不超过所述第一阻挡层10加第二阻挡层20的厚度；具体的，不能超过第二阻挡层20的深度，即工艺深度大于等于第一阻挡层10厚度，小于第一阻挡层10和第二阻挡层20的总厚度。
可选的方案还有，进行图形化工艺区域10-1的第一阻挡层可以不完全去除，以用于调节该区域的净载流子浓度。
步骤3’，如图1-c，对经上述处理后的氧化镓在氧氛围退火处理，形成退火处理后的净载流子浓度调控层30-1；如图1-c图形化工艺后的第一阻挡层部分区域被刻蚀，退火处理后，保留第一阻挡层的氧化镓外延层和去除第一阻挡层的氧化镓外延层收到退火处理的影响深度不同，保留第一阻挡层的氧化镓外延层的影响深度更浅；
步骤4’，如图1-d，将退火处理后的氧化镓的第一阻挡层10和第二阻挡层20剥离；再去除剥离第一阻挡层10和第二阻挡层20后的氧化镓晶圆的表面层。
其中，第一阻挡层10的选材为耐高温材料，满足熔点不低于退火温度，本实施例中采用熔点不低于退火的材料。耐高温材料的熔点的选择根据退火处理过程中的实际要求做适应性调整。第二阻挡层20的材质的熔点高于退火温度，且易于通过氢氟酸、浓硫酸、盐酸、硝酸等对氧化镓材料表面质量影响极小的溶液去除。此外，第二阻挡层20(剥离层)材料还具有较低的热膨胀系数，以避免退火过程中脱落。这里的对于氧化镓材料表面影响较小可以参考为腐蚀速率小于10nm/min，具有较低的热膨胀系数可以参考为不高于1×10 -4/K。本方案中的参数仅作为实施参考，并非具体限定。
进一步的优化本实施方案，为了防止阻挡层在高温退火过程中因热膨胀产生较大的垂直形变，致使阻挡层脱落，所述第一阻挡层10和第二阻挡层20总厚度不超过100微米，优选为不超过10微米。
步骤5’，如图1-e，根据应用场景，对去除第一阻挡层10后的氧化镓材料依次进行材料正反面表面的去除和修复处理，带外延材料面或进行过阻挡层图形化工艺的一面的刻蚀深度为范围0-1μm，不带外延材料面刻蚀深度范围为0-10μm，去除前步骤退火处理前保留第一阻挡层的氧化镓外延部分区域被退火处理影响的部分。
基于上述步骤，即可得到一经过区域性调控净载流子浓度的氧化镓晶圆。
实施例3：
本实施例提供一种基于高温退火技术的氧化镓器件制备方法，关于阻挡层，其区别于实施例1和实施例2，在氧化镓晶圆表面制备第一阻挡层和第二阻挡层；所述第二阻挡层位于氧化镓晶圆表面和所述第一阻挡层之间，所述第二阻挡层的图形化速率小于所述第一阻挡层，根据高温氧退火处理的温度选择所述第一阻挡层和所述第二阻挡层的材料。
基于实施例1，本实施例增加第二阻挡层，作为刻蚀终止层；
基于实施例2，本实施例增加第二阻挡层，在选择所述第二阻挡层的材质时，须同时满足剥离层的功能和刻蚀终止层的功能。
由此，本实施例披露一种氧化镓器件制备方法，具体包括有净载流子浓度调控方法，包括工艺步骤：
步骤1”，在氧化镓晶圆表面制备第一阻挡层和第二阻挡层，所述第一阻挡层起在高温氧退火过程中阻挡高温氧氛围环境的作用；所述第二阻挡层为剥离层和刻蚀终止层，作为剥离层的技术方案请参照实施例2，在本实施例主要披露关于作为刻蚀终止层的技术方案。
步骤2”，对第一阻挡层和第二阻挡层实施以氧化镓杂质调控目的的图形化工艺，所述图形化工艺的工艺深度不超过所述第一阻挡层加第二阻挡层的厚度；具体的，不能超过第二阻挡层的深度，即工艺深度大于等于第一阻挡层厚度，小于第一阻挡层和第二阻挡层的总厚度。
以干法刻蚀工艺作为图形化工艺具体描述为，第一阻挡层在第二阻挡层的表面，通过干法刻蚀工艺刻蚀第一阻挡层，当用于刻蚀第二阻挡层时，其刻蚀速率会因为材料的不同而降低。因此刻蚀工艺就可以设置较大的刻蚀时间冗余，以确保该刻蚀步骤不会对氧化镓材料表面造成影响。
根据上文可以知道实施例3披露的关于刻蚀终止层的技术可以分别和实施例1以及实施例2结合，形成两种技术方案。
实施例4：
本实施例提供一种第一阻挡层和第二阻挡层的材质范例，以SiO 2为第二阻挡层，以Si层为第一阻挡层为例，在选材时发现Si的耐高温性能较优，可以用以起到在高温退火处理过程中阻挡氧氛围的作用，SiO 2是一种易于通过氢氟酸、浓硫酸、盐酸、硝酸等对氧化镓材料表面质量影响极小的溶液去除的物质。可以用以作为氧化后剥离Si层的功能，同时其具有较低的膨胀系数避免退火过程中脱落。Si层生长在SiO 2薄膜上，通过干法刻蚀刻蚀Si层，但是Si层刻蚀工艺用于刻蚀SiO 2时速率相对于刻蚀Si层的速率更慢，从而实现了较大的刻蚀时间冗余，以确保该刻蚀步骤不会对氧化镓材料表面造成影响。
关于刻蚀终止层，需要说明的是，采用干法刻蚀工艺去除阻挡层时，SiO 2层厚度不小于5nm。
一种基于高温退火技术的氧化镓器件制备方法，如图2，包括以下步骤：
步骤100，如图2-a：
第一阻挡层10的材料优选为Si，第二阻挡层20优选为SiO 2。在氧化镓晶圆表面使用PECVD工艺和LPCVD工艺先后分别生长SiO 2层和Si层。其中Si层起到阻挡氧氛围的作用，SiO 2层起到剥离Si层的作用。SiO 2层和Si层总厚度不超过100微米，优选的，不超过10微米，以防止阻挡层在后续高温退火过程中因热膨胀产生较大的垂直形变，致使阻挡层脱落。
考虑到Si层需要覆盖在氧化镓晶圆的各个表面，优选的选取如LPCVD工艺能通过一次生 长而使薄膜覆盖到整个氧化镓晶圆样品表面的生长方式。
步骤200，如图2-b：
通过光刻或刻蚀技术对Si层和SiO 2层实施图形化工艺，其图形化工艺的深度大于Si层厚度且小于两层材料的总厚度，也就是对于预设的图形化区域10-1，去除图形化区域的Si层并保留部分或全部的SiO 2。
进行图形化工艺区域的Si层可以不完全去除，以用于调节该区域的净载流子浓度。
SiO 2层也可作用为调节材料的净载流子浓度层，进一步可以通过调节SiO 2层的厚度以实现在一定范围内对没有Si阻挡层区域的材料净载流子浓度的调控。
其中，刻蚀技术包括干法刻蚀和湿法刻蚀，即采用刻蚀等离子或刻蚀溶液对氧化镓晶圆实施图形化工艺操作，其中干法刻蚀的图形精度比湿法刻蚀更高，为了保证图形精度目的，可优选干法刻蚀。
步骤300，如图2-c：
将根据步骤100-步骤200的方法准备好的氧化镓晶圆样品置于高温设备(如退火炉)中进行600-1700℃的氧氛围退火处理。退火过程中，保持持续通入氧气，且腔体内的氧气含量应该不低于空气中氧气含量(21％)。除了以上参数外，高温设备腔体内的压强使用一个标准大气压，退火时间包含升降温时间，其中降温时，通过在400℃到实际退火温度范围内选择合适的停止供氧点可以有效实现对净载流子浓度的调控。出现被区域化调控的低净载流子浓度区域30-1；
进一步的，在实际操作中还可以采用以下方式实现净载流子浓度的调控：
通过退火中途间断性停止供氧，以及通入其他气体辅助调节的工艺手段实现对净载流子浓度的控制；
通过改变氧气的浓度，实现调控氧化镓晶圆样品的净载流子浓度；
通过调节气压参数实现对氧化镓晶圆样品净载流子浓度的调控；
一般情况，即使非常短的退火时间都会对氧化镓晶圆样品的净载流子浓度产生影响，但是影响的程度会随着时间和温度而改变，故，进一步可以通过调整时间和温度的关系来实现对氧化镓晶圆样品净载流子浓度的调控。
步骤400，如图2-d：
将完成退火处理工艺的氧化镓晶圆样品置入能够腐蚀SiO 2的溶液中超声以去除阻挡层。其中，第二阻挡层为剥离层；由于去除Si材料使用的碱性溶液会与氧化镓发生反应，引起氧化镓材料表面质量受损；因此需要选择非碱性溶液，而非碱性溶液对于退火处理之后的Si/SiO 2混合层的去除作用并不理想，因此作为一种实施例1的优选，本方案中增加第二阻挡层， 作用为剥离层的功能。保证第二阻挡层可以在非碱性溶液中快速反应溶解，解决了第一阻挡层不易剥离，或剥离溶液易损坏氧化镓材料的问题。
步骤500如图2-e：，
根据应用场景，对去除Si/SiO 2阻挡层后的氧化镓材料依次进行材料正反面表面的去除和修复处理，带外延材料面或进行过阻挡层图形化的一面的刻蚀深度为范围0-1μm，不带外延材料面刻蚀深度范围为0-10μm。
除刻蚀外，还可通过化学机械抛光等均匀减薄材料的方式去除表面层，厚度和刻蚀类似。最后通过湿法腐蚀技术对处理完的材料表面进行修复，修复溶液和氧化镓材料的反应速率应该不高于100nm/min。
实施例5：
基于实施例4的Si/SiO 2阻挡层实例。参照图2，具体实施步骤如下：
此案例使用的晶圆为单晶(001)晶向的β相氧化镓，其中晶圆包括(001)晶向的高掺杂浓度(～10 18cm -3)的氧化镓衬底，以及通过卤化物气相外延技术(HVPE)在其上方生长的9μm低掺杂浓度(～10 16cm -3)的单晶β相氧化镓外延薄膜。
图2-a，通过PECVD在氧化镓薄膜上生长150nm的SiO 2，在此SiO 2同时起到刻蚀终止层、剥离层、净载流子浓度调控层的作用。随后通过LPCVD继续生长400nm的多晶Si作为氧氛围阻挡层。由于LPCVD的生长特点，多晶Si将覆盖到整个氧化镓晶圆材料表面。
图2-b，通过光刻技术和反应离子刻蚀技术(RIE)对带有外延氧化镓面的阻挡层进行图形化工艺，所谓图形化工艺即选择需要改变净载流子浓度的区域，对这部分的区域去除Si阻挡层，也可以去除部分SiO 2组为一种误差范围，也可以作为杂志浓度调控需求。
图2-c，将图形化完成后的氧化镓晶圆置于退火炉中进行退火。氧气流量为3000sccm，腔内压强为一个标准大气压，腔体的温度控制在1100℃，升温时间2小时，降温时间2.5小时降至500℃。退火过程中保持氧气持续通入，在温度降至500℃时停止通入氧气。
图2-d，退完火后的氧化镓晶圆，至于HF酸中超声清洗20min，去除SiO 2/Si阻挡层材料。并依次用丙酮、异丙醇、去离子水洗净。
图2-e，使用电感耦合等离子体刻蚀机依次对晶圆的背面和正面(带外延层面)进行刻蚀。其中正面刻蚀600nm，背面刻蚀1μm。可以使用化学机械抛光方法替代(CMP)。刻蚀工艺完成后，将晶圆置于食人鱼溶液中(H 2SO 4：H 2O 2＝3：1)浸泡15min以修复刻蚀缺陷。，其中刻蚀工艺需要根据实际的应用场景选择性实施，不做限制，本方案的描述仅做参照实施。
实施例6：
基于上述实施例1-实施例5所述，可以清楚的知道本方案的核心思路，以及基于该核心 思路下的具体实施方式，本实施例进一步的列举一种氧化镓器件制备方法，具体是一种阳极边缘终端制备方法，参照图3，以光刻胶作为图形化工艺的刻蚀覆盖层，具体步骤如下：
步骤3-a，准备氧化镓晶圆，其包括氧化镓衬底40和氧化镓外延层30；
步骤3-b，在氧化镓外延层表面生长SiO 2层20，用于剥离Si层和/或用于刻蚀终止层作用；
步骤3-c，在SiO 2层表面以及氧化镓晶圆所有表面生长Si层10(多晶硅层)，用于阻挡高温氧氛围，具体可以采用LPCVD工艺；
步骤3-d，在氧化镓外延层一端的Si层表面旋涂光刻胶50，用于图形化工艺；
步骤3-e，将需要改变净载流子浓度的区域曝光、显影使光刻胶图形化；
步骤3-f，采用刻蚀工艺去除图形化部分的阻挡层Si层，并洗去光刻胶50；
步骤3-g，退火处理8小时，退火氛围：1100℃，一个标准大气压，氧流量3000sccm，退火设备的腔体空间为0.04m 3；此时，原Si层因氧氛围退火变成Si/SiO 2混合物层；其中氧化镓外延区出现了不同区域的低净载流子浓度区30-1；
步骤3-h，采用BOE溶液，湿法去除阻挡层，这里的阻挡层指的是退货处理后的Si/SiO 2混合物层，以及SiO 2层；
步骤3-i，采用ICP刻蚀对氧化镓晶圆的背面刻蚀1μm；
步骤3-j，采用ICP刻蚀对氧化镓晶圆的背面刻蚀600nm，后将其置于食人鱼溶液浸泡10-20min
步骤3-k，在氧化镓晶圆背面，即氧化镓衬底层采用物理气相沉积技术生长欧姆接触电极Ti/Au 60；
步骤3-l，在氧化镓晶圆正面，即氧化镓外延层表面旋涂光刻胶；
步骤3-m，对光刻胶曝光、显影使光刻胶图形化，区别于步骤3-e的图形化，本步骤是用于生长电极，根据步骤3-g形成的低净载流子浓度区30-1区域设计本步骤的图形化区域；
步骤3-n，采用物理气相沉积技术发生长肖特基电极70；
步骤3-o，去除肖特基电极的多余金属，并清洗光刻胶。
同时也可以带有外延薄膜的氧化镓晶圆替换为不带外延薄膜的氧化镓衬底，或者是在其他衬底上(如蓝宝石，Si，GaN，SiC，等，或者带有外延层的衬底如长有AlGaN的GaN衬底)生长的非晶、多晶或单晶氧化镓材料，其余工艺不变。上述物理气相沉积技术，例举如电子束蒸发技术。
实施例7:
基于上述实施例1-实施例5，本实施例再提供一种新的氧化镓器件制备方法，具体是半 导体器件间隔离方法，参照图4，以光刻胶作为图形化工艺的刻蚀覆盖层(也可以采用其他材料)，具体步骤如下：
步骤4-a，准备氧化镓晶圆，其包括氧化镓衬底40和氧化镓外延层30；
步骤4-b，在氧化镓外延层表面生长SiO 2层20，用于剥离Si层和/或用于刻蚀终止层作用；
步骤4-c，在SiO 2层表面以及氧化镓晶圆所有表面生长Si层10(多晶硅层)，用于阻挡高温氧氛围，具体可以采用LPCVD工艺；
步骤4-d，在氧化镓外延层一端的Si层表面旋涂光刻胶，用于图形化工艺；
步骤4-e，将晶圆正面需要改变净载流子浓度的区域曝光、显影使光刻胶图形化；
步骤4-f，采用刻蚀工艺去除图形化部分的阻挡层Si层，具体为晶圆上的用于器件制备区域，如图为氧化镓晶圆中间部分，并洗去光刻胶；
步骤4-g，在氧化镓衬底一端的Si层表面旋涂光刻胶，用于图形化工艺；
步骤4-h，与步骤4-e相似的，将晶圆背面需要改变净载流子浓度的区域曝光、显影使光刻胶图形化，晶圆上的用于器件制备区域；
步骤4-i，采用刻蚀技术去除背面阻挡层Si层，并洗去光刻胶；至此氧化镓晶圆正面和背面均对Si层做了图形化，即以将中间区域作为选择性调控位置；
步骤4-j，退火处理8小时，退火氛围：1150℃，一个标准大气压，氧流量3000sccm，退火设备的腔体空间为0.04m 3；此时，原Si层因氧氛围退火变成Si/SiO 2混合物层；其中氧化镓外延区和衬底区均出现了不同区域的低净载流子浓度区30-1；
步骤4-k，采用BOE溶液，湿法去除阻挡层，这里的阻挡层指的是退货处理后的Si/SiO 2混合物层，以及SiO 2层；
步骤4-i，采用ICP刻蚀对氧化镓晶圆的背面刻蚀1μm；采用ICP刻蚀对氧化镓晶圆的背面刻蚀600nm，后将其置于食人鱼溶液浸泡10-20min修复晶圆表面刻蚀损伤。
其中，一次退火处理会存在其调控极限，若是需要获得大尺度的净载流子浓度调控范围，需要将实施例6中最终获得的晶圆再次进行重复操作，退火区域为同一位置。第二次退火之前，实施例6中的最后一步表面层去除处理为必要工艺。
其他的例如半导体表面局部区域钝化以及导电率调控，垂直结构MOSFET器件内部电流阻挡层设计等均可以根据以上实施例推导得到。其中，需要注意的是每一种应用的退火时间需要根据需求调整，具有区别，其他的还包括如前文所述的改变SiO 2层的厚度，改变多晶Si层的厚度，改变退火温度，氧气浓度，腔体压强等参数来配合设计方法。例如：若需获得更低的净载流子浓度，以及更深的低净载流子浓度区，则可以增加退火时间，提升氧气浓度， 增加压强，以及减薄SiO 2的厚度等方式的一种或多种来调控。反之则运用调控方法的趋势相反。
实施例8：
本实施例提供一种阻挡层结构在离子注入技术的高温杂质激活时发挥作用的工艺。公开一种基于离子注入技术的净载流子浓度控制工艺，如图5，
步骤5-a，准备氧化镓晶圆，其包括氧化镓衬底40和氧化镓外延层30；
步骤5-b，完成以下工艺：1)在氧化镓外延层表面生长SiO 2层20，用于剥离Si层和/或用于刻蚀终止层作用；2)在SiO 2层表面以及氧化镓晶圆所有表面生长Si层10(多晶硅层)，用于阻挡高温氧氛围，具体可以采用LPCVD工艺；3)在氧化镓外延层一端的Si层表面旋涂光刻胶50，用于图形化工艺；
步骤5-c，将需要改变净载流子浓度的区域曝光、显影使光刻胶图形化；
步骤5-d，采用刻蚀工艺去除图形化部分的阻挡层Si层和SiO 2层20；
步骤5-e，通过离子注技术在氧化镓外延层30注入所需的离子，形成离子注入区60，注入离子为受主杂质(Mg或N)；也可以是施主杂质；
步骤5-f，去除光刻胶；
步骤5-g，退火处理8小时，退火氛围：1100℃，一个标准大气压，氧流量3000sccm，退火设备的腔体空间为0.04m 3；高温退火环境下，离子注入区60形成杂质激活后的注入区70，以及受氧退火影响使得氧化镓衬底40和氧化镓外延层30形成高阻区80；
步骤5-h，去除阻挡层，这里的阻挡层指的是退火处理后的Si/SiO 2混合物层，以及SiO 2层；
步骤5-i，采用ICP刻蚀去除受到影响的氧化镓晶圆表面层。
本实施例中，当前对氧化镓材料离子注入后，其杂质激活处理和晶格修复通常使用氮气或氩气氛围的退火。氧氛围退火本身会影响材料的净载流子浓度，所以此前并不适合作为注入杂质激活的退火氛围。本发明中的所提出的氧氛围阻挡层结构可以有效隔绝氧气对氧化镓材料净载流子浓度的影响，使得氧氛围退火用于激活注入杂质成为可能。通过在氧化镓晶圆的局部区域注入受主杂质或施主杂质，并用阻挡层覆盖晶圆上的非注入区，有望在修复因高能粒子造成缺陷的同时，更为精确地对氧化镓晶圆的净载流子浓度进行调控，充分发挥两种技术的优势。
在上述实施例中，对各个实施例的描述各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。本申请在上述部分实施例中所讨论的工艺步骤，仅仅是一些优选实现方法，用于阐述本申请所述结构的可行性，不对发明的范围进行限制。通过其它工 艺方法或顺序实现本发明浓度调控方法的，亦在本发明保护范围之内。以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种基于高温退火技术的氧化镓器件制备方法，其特征在于，包括以下步骤：
    在氧化镓晶圆表面制备阻挡层，所述阻挡层起到在高温氧退火过程中阻挡氧氛围环境的作用；
    对阻挡层实施以氧化镓晶圆杂质调控为目的的图形化工艺，所述图形化工艺的工艺深度不超过所述阻挡层厚度；
    对经上述处理后的氧化镓晶圆在氧氛围退火处理；
    去除退火处理后的氧化镓晶圆的阻挡层；
    去除已剥离所述阻挡层的氧化镓晶圆的表面层。
  2. 根据权利要求1所述的基于高温退火技术的氧化镓器件制备方法，其特征在于，在氧化镓晶圆表面制备阻挡层的方法包括步骤：
    在氧化镓晶圆表面制备第一阻挡层和第二阻挡层，在所述第二阻挡层表面生长第一阻挡层，所述第二阻挡层隔离所述氧化镓晶圆表面和所述第一阻挡层，所述第二阻挡层为剥离层。
  3. 根据权利要求1所述的基于高温退火技术的氧化镓器件制备方法，其特征在于，在氧化镓晶圆表面制备阻挡层的方法包括步骤：
    在氧化镓晶圆表面制备第一阻挡层和第二阻挡层；所述第二阻挡层位于氧化镓晶圆表面和所述第一阻挡层之间，所述第二阻挡层的图形化速率小于所述第一阻挡层，根据高温氧退火处理的温度选择所述第一阻挡层和所述第二阻挡层的材料。
  4. 根据权利要求1所述的基于高温退火技术的氧化镓器件制备方法，其特征在于，采用光刻或刻蚀的方法对阻挡层进行图形化工艺。
  5. 根据权利要求2或3所述的基于高温退火技术的氧化镓器件制备方法，其特征在于，通过调整第一阻挡层和第二阻挡层的各自厚度或总厚度，调控净载流子浓度；
    或，通过调整第二阻挡层的厚度，对图形化后没有所述第一阻挡层覆盖的区域做净载流子浓度的调控。
  6. 根据权利要求1所述的基于高温退火技术的氧化镓器件制备方法，其特征在于，所述阻挡层被制备在氧化镓晶圆的所有表面。
  7. 根据权利要求1-3任意一项所述的基于高温退火技术的氧化镓器件制备方法，其特征在于，通过退火温度、氧气浓度、退火设备腔体压强中的一种或多种参数调控净载流子浓度。
  8. 根据权利要求2所述的基于高温退火技术的氧化镓器件制备方法，其特征在于，采用干法刻蚀的方法对所述阻挡层实施图形化工艺，所述第二阻挡层的刻蚀速率小于所述第二阻挡层的刻蚀速率。
  9. 根据权利要求1所述的基于高温退火技术的氧化镓器件制备方法，其特征在于，所述阻挡层的材质根据以下要求进行选择：
    熔点高于退火温度；
    能够被与氧化镓材料表面反应速率慢溶液去除。
  10. 一种氧化镓器件，其特征在于，包括经过如权利要求1-9所述的任意一种基于高温退火技术的氧化镓器件制备方法实施过区域性调控的氧化镓外延层和/或氧化镓衬底。
  11. 一种氧化镓器件制备方法，其特征在于，采用权利要求1-9任意一项所述的基于高温退火技术的氧化镓器件制备方法，在去除已剥离所述阻挡层的氧化镓晶圆的表面层的步骤之后，还包括步骤：
    在所述氧化镓晶圆背面，即氧化镓衬底层生长欧姆接触电极；
    在所述氧化镓晶圆正面，即氧化镓外延层表面旋涂光刻胶；
    对光刻胶曝光、显影使光刻胶图形化，用于生长电极，在低净载流子浓度区设计本步骤的图形化区域；
    采用物理气相沉积技术发生长肖特基电极；
    去除肖特基电极的多余金属，并清洗光刻胶。
  12. 一种氧化镓器件制备方法，其特征在于，采用权利要求1-9任意一项所述的基于高温退火技术的氧化镓器件制备方法，还包括步骤：
    将晶圆正面和晶圆背面需要改变净载流子浓度的区域图形化，具体为晶圆上的用于器件制备区域。
  13. 一种氧化镓器件制备方法，其特征在于，采用权利要求1-9任意一项所述的基于高温退火技术的氧化镓器件制备方法，在去除图形化部分的阻挡层之后，包括步骤：
    通过离子注技术在氧化镓外延层注入所需的离子，形成离子注入区，注入离子为受主杂质或施主杂质；
    对经上述处理后的氧化镓晶圆在氧氛围退火处理，高温退火环境下，离子注入区形成所注入杂质激活后的注入区，以及受氧退火影响使得氧化镓衬底和氧化镓外延层形成高阻区；
    去除退火处理后的氧化镓晶圆的阻挡层；
    去除已剥离所述阻挡层的氧化镓晶圆的表面层。
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