WO2024048394A1 - 積層構造体、積層構造体の製造方法、及び半導体デバイス - Google Patents

積層構造体、積層構造体の製造方法、及び半導体デバイス Download PDF

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WO2024048394A1
WO2024048394A1 PCT/JP2023/030337 JP2023030337W WO2024048394A1 WO 2024048394 A1 WO2024048394 A1 WO 2024048394A1 JP 2023030337 W JP2023030337 W JP 2023030337W WO 2024048394 A1 WO2024048394 A1 WO 2024048394A1
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pattern
layer
semiconductor
alignment
region
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French (fr)
Japanese (ja)
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逸 青木
眞澄 西村
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Japan Display Inc
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Japan Display Inc
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Priority to US19/062,500 priority patent/US20250220999A1/en
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
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Definitions

  • One embodiment of the present invention relates to a stacked structure including a semiconductor layer containing gallium nitride formed on an amorphous substrate, a method for manufacturing the stacked structure, and a semiconductor device using the stacked structure.
  • gallium nitride-based semiconductor layers As semiconductor devices using gallium nitride-based semiconductor layers, for example, transistor elements such as HEMT (High Electron Mobility Transistor) and light emitting elements such as LED (Light Emitting Diode) are known. In particular, there is a high demand for light emitting devices using light emitting diodes (LEDs) in each pixel, and there is an urgent need to develop a technology for forming a highly crystalline gallium nitride semiconductor layer on a substrate other than a silicon substrate.
  • HEMT High Electron Mobility Transistor
  • LED Light Emitting Diode
  • Patent Document 1 discloses that a buffer layer is formed on an insulating substrate such as a sapphire substrate or a quartz glass substrate, an insulating pattern is formed on the buffer layer, and a gallium nitride-based semiconductor is formed on the buffer layer and the insulating pattern. Techniques for forming layers are disclosed.
  • a gallium nitride-based semiconductor layer is generally formed by epitaxial growth at a temperature exceeding 1000°C using a sapphire substrate, a quartz glass substrate, or the like having heat resistance of 1000°C or higher.
  • a temperature exceeding 1000°C using a sapphire substrate, a quartz glass substrate, or the like having heat resistance of 1000°C or higher.
  • the use of expensive sapphire substrates or quartz glass substrates hinders the increase in the area of the display screen.
  • One of the objects of an embodiment of the present invention is to form a stacked structure using a highly crystalline gallium nitride semiconductor layer on an inexpensive amorphous substrate.
  • a laminated structure includes an amorphous substrate having an insulating surface, an alignment pattern on the amorphous substrate, an insulating layer that is in contact with the side surface of the alignment pattern and surrounding the peripheral edge of the alignment pattern, and an upper semiconductor pattern containing gallium nitride, and the insulating layer has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.
  • a method for manufacturing a laminated structure includes an amorphous substrate having an insulating surface, an alignment pattern on the amorphous substrate, and an insulating layer that is in contact with the outer circumferential side of the alignment pattern but not in contact with the top surface of the alignment pattern. and a semiconductor pattern containing gallium nitride on the alignment pattern, the alignment pattern having a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.
  • a method for manufacturing a laminated structure according to an embodiment of the present invention includes forming an alignment layer on an amorphous substrate having an insulating surface, etching the alignment layer to form an alignment pattern on the insulating surface, By forming an insulating layer on the insulating surface and the alignment pattern and etching the insulating layer, the insulating layer is formed so as to be in contact with the side surface of the alignment pattern and surrounding the periphery of the alignment pattern.
  • the method includes forming a semiconductor layer containing gallium nitride on the alignment pattern and etching the semiconductor layer containing gallium nitride to form a semiconductor pattern on the upper surface of the alignment layer,
  • the insulating layer surrounding the semiconductor pattern has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern.
  • a method for manufacturing a laminated structure according to an embodiment of the present invention includes forming an alignment layer on an amorphous substrate having an insulating surface, etching the alignment layer to form an alignment pattern on the insulating surface, By forming an insulating layer on the insulating surface and the alignment pattern and etching the insulating layer, the insulating layer is formed so as to be in contact with the outer peripheral side of the alignment pattern but not with the top surface of the alignment pattern.
  • forming a semiconductor pattern on the upper surface of the alignment layer by forming a semiconductor layer containing gallium nitride on the layer and the alignment pattern and etching the semiconductor layer containing gallium nitride, the alignment pattern , has a first region that overlaps with the semiconductor pattern, and a second region that does not overlap with the semiconductor pattern.
  • FIG. 2 is an end view showing a method for manufacturing a laminated structure according to an embodiment of the present invention.
  • FIG. 2 is an end view showing a method for manufacturing a laminated structure according to an embodiment of the present invention.
  • FIG. 2 is an end view showing a method for manufacturing a laminated structure according to an embodiment of the present invention.
  • FIG. 2 is an end view showing a method for manufacturing a laminated structure according to an embodiment of the present invention.
  • FIG. 2 is an end view showing a method for manufacturing a laminated structure according to an embodiment of the present invention.
  • FIG. 2 is an end view showing a method for manufacturing a laminated structure according to an embodiment of the present invention.
  • FIG. 1 is a plan view showing a laminated structure according to an embodiment of the present invention.
  • FIG. 1 is a plan view showing a laminated structure according to an embodiment of the present invention.
  • FIG. 1 is an end view showing a laminated structure according to an embodiment of the present invention.
  • FIG. 1 is an end view showing a laminated structure according to an embodiment of the present invention.
  • FIG. 1 is an end view showing a method for manufacturing a laminated structure according to an embodiment of the present invention.
  • FIG. 1 is an end view showing a semiconductor device using a stacked structure according to an embodiment of the present invention.
  • FIG. 1 is a plan view showing a light emitting device using a semiconductor device using a stacked structure according to an embodiment of the present invention.
  • FIG. 1 is an end view showing a semiconductor device using a stacked structure according to an embodiment of the present invention.
  • the direction from the substrate toward the semiconductor layer will be referred to as "up”, and the opposite direction will be referred to as “down”.
  • the expressions “above” and “below” merely explain the vertical relationship of each element.
  • the expressions “above” or “below” include not only the case where the third element is interposed between the first element and the second element, but also the case where the third element is not interposed.
  • the expressions “above” or “below” include not only cases in which each element overlaps in plan view, but also cases in which they do not overlap.
  • elements having the same functions as the elements already described may be given the same reference numerals or the same reference numerals and symbols such as alphabets, and the explanation thereof may be omitted.
  • a symbol such as an alphabet may be added to the code indicating the element to distinguish the parts.
  • the reference numeral indicating the element will be used in the description.
  • ⁇ includes A, B, or C
  • ⁇ includes any of A, B, and C
  • ⁇ is selected from the group consisting of A, B, and C.
  • expressions such as “including one of the combinations A to C” do not exclude the case where ⁇ includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where ⁇ includes other elements.
  • FIGS. 1 to 8 are end views showing a method for manufacturing a laminated structure including a semiconductor pattern containing gallium nitride in the first embodiment.
  • FIGS. 1 to 6 show an example in which a semiconductor pattern containing gallium nitride is formed on an amorphous substrate.
  • FIG. 7 is a plan view of the laminated structure when viewed from above, and
  • FIG. 8 is a cross-sectional view of the laminated structure shown in FIG. 7 taken along line A1-A2. Note that although FIGS. 1 to 8 show an example in which a single semiconductor pattern is formed, in reality, a plurality of semiconductor patterns are formed on a substrate.
  • a base layer 102 is formed on an amorphous substrate 101.
  • a glass substrate can be used as the amorphous substrate 101. It is preferable that the glass substrate has a low content of alkali components, a low coefficient of thermal expansion, a high strain point, and a high surface flatness. For example, it is preferable that the content of alkali metals (such as sodium) is 0.1% or less, the thermal expansion coefficient is lower than 50 ⁇ 10 ⁇ 7 /°C, and the strain point is 600°C or higher.
  • a gallium nitride semiconductor layer is formed by a sputtering method, so a glass substrate having lower heat resistance than a sapphire substrate or a quartz substrate can be used.
  • a glass substrate is cheaper than a sapphire substrate or a quartz substrate, and is suitable for increasing the area of mother glass.
  • the amorphous substrate 101 of this embodiment is not limited to a glass substrate, and may be a resin substrate such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate.
  • a base layer 102 is provided on the amorphous substrate 101.
  • the material of the underlayer 102 also affects the crystallinity of gallium nitride that will be formed later.
  • the base layer 102 has a role as a protective layer that prevents impurities from being mixed in from the amorphous substrate 101.
  • the base layer 102 is composed of one or more insulating layers selected from, for example, a silicon nitride layer, a silicon oxide layer, an aluminum nitride layer, and an aluminum oxide layer. In this embodiment, an aluminum nitride layer is used as the base layer 102. Further, the thickness of the base layer 102 is greater than or equal to 5 nm and less than or equal to 50 nm.
  • the base layer 102 is formed by a sputtering method, a CVD method, a vacuum evaporation method, an electron beam evaporation method, an ALD (Atomic Layer Deposition) method, or the like.
  • planarization treatment may be performed.
  • the planarization treatment refers to, for example, reverse sputtering treatment or etching treatment.
  • the orientation layer 103 has a function of improving the crystal orientation of the semiconductor layer 108 when forming the semiconductor layer 108 (see FIG. 2) containing gallium nitride, which will be described later.
  • the orientation layer 103 may be conductive or insulative, but preferably has crystallinity oriented along a specific axis (for example, the c-axis).
  • the orientation layer 103 is preferably a crystal with rotational symmetry.
  • the crystal surface has six-fold rotational symmetry.
  • the orientation layer 103 preferably has a hexagonal close-packed structure, a face-centered cubic structure, or a structure similar thereto.
  • a structure similar to a hexagonal close-packed structure or a face-centered cubic structure includes a crystal structure in which the c-axis does not form 90 degrees with respect to the a-axis and the b-axis.
  • the alignment layer 103 having a hexagonal close-packed structure or a structure similar thereto is preferably oriented in the (0001) direction with respect to the amorphous substrate 101, that is, in the c-axis direction.
  • the orientation layer 103 having a face-centered cubic structure or a similar structure is preferably oriented in the (111) direction with respect to the amorphous substrate 101.
  • the above-mentioned alignment layer 103 is, for example, a conductive alignment layer such as titanium (Ti), titanium nitride (TiNx), titanium oxide (TiOx), graphene, zinc oxide (ZnO), magnesium diboride (MgB 2 ).
  • a conductive alignment layer such as titanium (Ti), titanium nitride (TiNx), titanium oxide (TiOx), graphene, zinc oxide (ZnO), magnesium diboride (MgB 2 ).
  • aluminum (Al), silver (Ag), calcium (Ca), nickel (Ni), copper (Cu), strontium (Sr), rhodium (Rh), palladium (Pd), cerium (Ce), ytterbium (Yb) , iridium (Ir), platinum (Pt), gold (Au), lead (Pb), actinium (Ac), thorium (Th), and the like can be used.
  • the above-mentioned alignment layer 103 is, for example, an insulating alignment layer such as aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), lithium niobate (LiNbO), BiLaTiO, SrFeO, BiFeO, BaFeO, ZnFeO. , PMnN-PZT, biological apatite (BAp), or the like can be used.
  • AlN aluminum nitride
  • Al 2 O 3 aluminum oxide
  • LiNbO lithium niobate
  • BiLaTiO LiNbO
  • SrFeO BiFeO
  • BaFeO BaFeO
  • ZnFeO. boronO
  • PMnN-PZT biological apatite
  • BAp biological apatite
  • the alignment layer 103 may be a conductive alignment layer or an insulating alignment layer. When there is no need to distinguish between the conductive alignment layer and the insulating alignment layer, they are expressed as an alignment layer 103.
  • the surface state of the orientation layer 103 affects the crystallinity of the semiconductor layer 108, which will be described later. Therefore, it is desirable that the surface of the alignment layer 103 be flat.
  • the arithmetic mean roughness (Ra) of the surface of the alignment layer 103 is smaller than 2.3 nm.
  • the semiconductor layer 108 having c-axis orientation can be formed.
  • the surface of the alignment layer 103 may also be subjected to the planarization treatment described for the base layer 102 before forming the semiconductor layer 108.
  • an aluminum nitride layer is used as the base layer 102 and a titanium layer is used as the alignment layer 103.
  • a titanium layer is used as the alignment layer 103.
  • the thickness of the alignment layer 103 is, for example, 50 nm or more (preferably 50 nm or more and 100 nm or less).
  • the alignment layer 103 may be formed by any method.
  • the alignment layer 103 is formed by a sputtering method, a CVD method, a vacuum evaporation method, an electron beam evaporation method, an ALD method, or the like.
  • a resist mask 104 is formed on the alignment layer 103, and the alignment layer 103 is etched using the resist mask, thereby forming an alignment pattern 105. After that, the resist mask 104 is removed.
  • the orientation pattern 105 has a slope (hereinafter referred to as "taper") in which the angle of the side surface with respect to the bottom surface is ⁇ 1.
  • the taper angle ⁇ 1 of the alignment pattern 105 can be set to 20° or more and 50° or less (preferably 30° or more and 40° or less).
  • the alignment layer 103 is etched using a dry etching method, so that the taper angle ⁇ 1 of the alignment pattern 105 is set to 60° or more.
  • an insulating layer 106 is formed to cover the alignment pattern 105.
  • an inorganic insulating material such as silicon oxide or silicon nitride is used.
  • silicon nitride is formed as the insulating layer 106 by CVD.
  • the shape of the insulating layer 106 has an uneven shape that reflects the shape of the alignment pattern 105. Note that when the material of the base layer 102 and the material of the insulating layer 106 are the same, the sealing performance can be improved. Furthermore, when the materials of the base layer 102 and the materials of the insulating layer 106 are different, a material that does not affect the alignment pattern 105 can be selected.
  • a resist mask 107 is formed on the insulating layer 106, and the insulating layer 106 is etched using the resist mask 107 to open an opening that exposes the upper surface 105a of the alignment pattern 105.
  • a portion 106a is formed.
  • the insulating layer 106 comes into contact with the side surface 105b of the alignment pattern 105 and has a shape that surrounds the periphery of the alignment pattern 105.
  • the peripheral portion of the orientation pattern 105 refers to a portion including a portion of the side surface 105b and the top surface 105a of the orientation pattern.
  • the thickness of the insulating layer 106 is, for example, in a range of 50 nm or more and 100 nm or less.
  • the thickness of the insulating layer 106 is preferably approximately the same as that of the orientation pattern 105. Further, the thickness of the insulating layer 106 may be thicker than the thickness of the alignment pattern 105, but it is preferably twice the thickness of the alignment pattern 105 or less. If the thickness of the insulating layer 106 exceeds, for example, twice the thickness of the alignment pattern 105, a step will be formed between the upper surface 105a of the alignment pattern 105 and the upper surface of the insulating layer 106. The level difference caused by the insulating layer 106 may reduce the crystallinity of a semiconductor layer to be formed later.
  • the insulating layer 106 on the orientation pattern 105 may disappear when the insulating layer 106 is etched.
  • the thickness of the insulating layer 106 provided on the alignment pattern 105 substantially the same as the thickness of the alignment pattern, it covers the side surface 105b of the alignment pattern 105 and also covers the top surface 105a of the alignment pattern 105. can be protected. After etching, the resist mask 107 is removed to obtain the alignment pattern 105.
  • the crystal orientation axis of the semiconductor layer 108 that will be formed later is influenced by the surface of the insulating layer 106 and the surface of the orientation pattern 105. Therefore, the surfaces of the insulating layer 106 and the alignment pattern preferably have flat surfaces.
  • the thickness of the insulating layer 106 is made larger than the thickness of the alignment pattern 105, and before forming the resist mask 107, the surface of the insulating layer 106 is subjected to planarization treatment so that the surface of the alignment pattern 105 is not exposed. You may do so.
  • the surface of the insulating layer 106 may be subjected to polishing treatment.
  • a process may be performed to make the thickness of the region overlapping with the orientation pattern 105 smaller than the thickness of the region not overlapping with the orientation pattern 105. Thereby, a flat surface with reduced unevenness can be formed on the surface of the insulating layer 106.
  • gallium nitride is formed as the semiconductor layer 108 by a sputtering method. Specifically, gallium nitride is produced by heating an amorphous substrate 101 having an insulating surface (here, an amorphous substrate 101 provided with a base layer 102) to 25° C. to 600° C., preferably 25° C. to 400° C. It is formed by a sputtering method in this state. That is, gallium nitride is formed at a temperature below the strain point of the amorphous substrate 101.
  • Gallium nitride is usually formed by MOCVD (metal-organic chemical vapor deposition), but MOCVD requires a high process temperature, so it is not appropriate in consideration of the heat resistance of the amorphous substrate 101.
  • MOCVD metal-organic chemical vapor deposition
  • the semiconductor layer 108 can be formed on the inexpensive amorphous substrate 101 at a lower temperature than the MOCVD method. Furthermore, a semiconductor layer 108 is formed on an orientation pattern 105 having crystallinity oriented along a specific axis (for example, the c-axis). Furthermore, by relaxing the surface unevenness of the amorphous substrate 101 with the base layer 102, the surface unevenness of the alignment pattern 105 formed on the base layer 102 is alleviated. Thereby, even when the semiconductor layer 108 is formed at a lower temperature than the MOCVD method, the semiconductor layer 108 can be formed with high crystallinity. Further, since the amorphous substrate 101 can be made larger in area than the sapphire substrate, it is possible to form the laminated structure 100 with a large area.
  • the semiconductor layer 108 is formed, for example, by sputtering using a sintered body of gallium nitride as a sputtering target and using argon (Ar) or a mixed gas of argon (Ar) and nitrogen (N 2 ) as a sputtering gas.
  • argon Ar
  • Ar argon
  • N 2 nitrogen
  • Ru a mixed gas of argon
  • Ru a mixed gas of argon
  • Ru nitrogen
  • sputtering method for example, a bipolar sputtering method, a magnetron sputtering method, a dual magnetron sputtering method, a facing target sputtering method, an ion beam sputtering method, and an inductively coupled plasma (ICP) sputtering method can be applied.
  • ICP inductively coupled plasma
  • the conductivity type of the semiconductor layer 108 may be substantially intrinsic, or may have n-type conductivity or p-type conductivity.
  • the semiconductor layer 108 having n-type conductivity may not contain a dopant for controlling valence electrons, or may be doped with silicon (Si) or germanium (Ge) as an n-type dopant. good.
  • the semiconductor layer 108 having p-type conductivity may be doped with an element selected from magnesium (Mg), zinc (Zn), cadmium (Cd), and beryllium (Be) as a p-type dopant. .
  • the carrier concentration is preferably 1 ⁇ 10 18 /cm 3 or more.
  • the carrier concentration is preferably 5 ⁇ 10 16 /cm 3 or more.
  • zinc (Zn) may be included as a dopant.
  • the semiconductor layer 108 may contain one or more elements selected from indium (In), aluminum (Al), and arsenic (As).
  • the band gap of the semiconductor layer 108 can be adjusted by these elements.
  • the semiconductor layer 108 containing gallium nitride is formed on the amorphous substrate 101 on which the alignment pattern 105 is formed.
  • the crystallinity of the semiconductor layer 108 formed on the orientation pattern 105 is influenced by the orientation axis of the orientation pattern 105.
  • the semiconductor layer 108 also has c-axis orientation or (111) orientation crystallinity.
  • the crystallinity of the semiconductor layer 108 is preferably single crystal, but may be polycrystalline, microcrystalline, or nanocrystalline.
  • the crystal structure of the semiconductor layer 108 may have a wurtzite structure.
  • the orientation of the semiconductor layer 108 is preferably c-axis orientation or (111) orientation.
  • the semiconductor layer 108 may include an amorphous structure near the interface where it contacts the alignment pattern 105, it is preferable that the semiconductor layer 108 has crystallinity in the bulk.
  • the film thickness of the semiconductor layer 108 is 100 nm or more and 1 ⁇ m or less. However, the thickness of the semiconductor layer 108 is not limited and can be set as appropriate depending on the structure of the device.
  • the semiconductor layer 108 may have a single layer structure or a stacked structure including a plurality of layers having different conductivity types and/or compositions.
  • a resist mask 109 is formed on the semiconductor layer 108.
  • a semiconductor pattern 111 is formed.
  • a dry etching method using a halogenated gas is used as a method for etching the semiconductor layer 108.
  • the halogenated gas is not particularly limited as long as it contains one or more halogen atoms such as a chlorine atom, a fluorine atom, and a bromine atom and is in a gas state at room temperature, but examples include CF 4 , C 2 F 6 , Examples include C 3 F 8 , C 2 F 4 , C 4 F 8 , C 4 F 6 , C 5 F 8 , CHF 3 , CCl 4 , CClF 3 , AlF 3 and AlCl 3 . Further, a plurality of halogenated gases may be mixed and used.
  • the taper angle ⁇ 2 of the semiconductor pattern 111 can be set to 60° or more.
  • the present invention is not limited to this example, and the semiconductor pattern 111 may be formed using a wet etching method. As shown in FIG. 6, the semiconductor pattern 111 has a slope (hereinafter referred to as "taper") in which the angle of the side surface with respect to the bottom surface is ⁇ 2.
  • the taper angle ⁇ 2 of the semiconductor pattern 111 can be set to 20° or more and 50° or less (preferably 30° or more and 40° or less). After etching, the resist mask 109 is removed to obtain a semiconductor pattern 111 containing gallium nitride.
  • the insulating layer 106 has a first region 110 (see FIG. 8) that overlaps with the semiconductor pattern 111 and a second region 120 (see FIG. 8) that does not overlap with the semiconductor pattern 111. Further, the upper surface of the second region 120 in the insulating layer 106 is located below the upper surface of the first region 110.
  • the first region 110 is a region that overlaps with the orientation pattern 105
  • the second region 120 is a region that does not overlap with the orientation pattern 105.
  • the film thickness in the second region 120 is thicker than the film thickness in the first region 110.
  • the insulating layer 106 has a side surface in the second region 120 that is continuous with the upper surface of the first region 110 .
  • FIG. 7 is a plan view of a stacked structure 100 having a semiconductor pattern 111 containing gallium nitride. Further, FIG. 8 is an end view of the laminated structure 100 when the laminated structure 100 is cut along the line A1-A2.
  • an alignment layer 103 is formed on an amorphous substrate 101 having an insulating surface, and an alignment pattern 105 is formed on the insulating surface by etching the alignment layer 103.
  • An insulating layer 106 is formed on the surface and the alignment pattern 105 and etched, so that the insulating layer 106 is in contact with the side surface 105b of the alignment pattern 105 and surrounds the periphery of the alignment pattern 105.
  • a semiconductor layer 108 containing gallium nitride is formed on the insulating layer 106 and the alignment pattern 105, and the semiconductor layer 108 containing gallium nitride is etched, thereby forming a semiconductor pattern on the upper surface 105a of the alignment pattern 105.
  • the insulating layer 106 surrounding the peripheral portion of the alignment pattern 105 has a first region 110 that overlaps with the semiconductor pattern 111 and a second region 120 that does not overlap with the semiconductor pattern 111.
  • the stacked structure 100 in one embodiment of the present invention includes a semiconductor pattern 111 that has high crystallinity and has c-axis orientation. Furthermore, the laminated structure 100 includes an amorphous substrate 101 that can be made to have a large area. Therefore, by using the stacked structure 100, it is possible to increase the productivity of LEDs containing gallium nitride or to manufacture a backplane in which a transistor containing gallium nitride is formed.
  • the semiconductor pattern 111 of this embodiment has crystallinity aligned with a specific orientation axis, reflecting the orientation of the orientation pattern 105 and the insulating layer 106. Therefore, by processing the semiconductor pattern 111 of this embodiment and using it in a semiconductor device, a semiconductor device with excellent characteristics can be realized.
  • the alignment layer 103 by patterning the alignment layer 103 to form the alignment pattern 105, a high-definition semiconductor device can be formed compared to a case where the alignment layer is not patterned. Furthermore, by using a conductive material as the orientation pattern 105, the orientation pattern 105 can be used as wiring and electrodes.
  • the crystallinity of the semiconductor layer 108 may be reduced due to the influence of the uneven shape. Therefore, in the insulating layer 106 , a process may be performed to make the thickness of the first region 110 that overlaps with the alignment pattern 105 smaller than the thickness of the second region 120 that does not overlap with the alignment pattern 105 . By performing such treatment, when the semiconductor layer 108 is formed over the alignment pattern 105 and the insulating layer 106, the uneven shape of the insulating layer 106 can be reduced. Since the semiconductor layer 108 can be formed over a surface that is as flat as possible, the crystallinity of the semiconductor layer 108 can be improved.
  • the taper angle ⁇ 1 of the alignment pattern 105 tends to become large, and depending on the conditions, the taper angle ⁇ 1 becomes 60° or more.
  • etching residue the gallium nitride layer (residue) may occur.
  • adjacent alignment patterns 105 are also close to each other. Therefore, if gallium nitride residue is generated, there is a risk that adjacent alignment patterns 105 may be electrically connected to each other due to the etching residue.
  • an insulating layer 106 is provided so as to surround the periphery of the alignment pattern 105.
  • a semiconductor layer 108 is deposited on the alignment pattern 105 and the insulating layer 106 and etched on the insulating layer 106. Therefore, irrespective of the taper angle ⁇ 1 of the alignment pattern 105, it is possible to suppress the formation of etched residues of the semiconductor layer 108 near the lower end of the tapered portion of the alignment pattern 105. Thereby, conduction due to etching residue can be suppressed.
  • a laminated structure 100A having a partially different structure from the laminated structure 100 in the first embodiment will be described with reference to FIGS. 9 and 10.
  • the shape of the insulating layer 106 in contact with the orientation pattern 105 is different from the shape of the insulating layer 106 included in the laminated structure 100.
  • the method for manufacturing the layered structure 100A in this embodiment is the same as the method for manufacturing the layered structure 100 from FIGS. 1 to 5.
  • the laminated structure 100A differs from the manufacturing method of the laminated structure 100 in the region where a resist mask 112 is formed on the deposited semiconductor layer 108.
  • the resist mask 112 is formed inside the opening 106a of the insulating layer 106.
  • the insulating layer 106 is etched using the resist mask 112 to form a semiconductor pattern 111.
  • a dry etching method using a halogenated gas is used as a method for etching the semiconductor layer 108.
  • the taper angle ⁇ 2 refer to the description regarding FIG. 6.
  • the resist mask 112 is provided inside the opening 106a of the insulating layer 106. Therefore, when forming the semiconductor pattern 111 by etching, the upper surface of the insulating layer 106 and the upper surface 105a of the alignment pattern 105 are removed. At this time, the insulating layer 106 is in contact with the side surface 105b (also referred to as the outer peripheral side surface) of the alignment pattern 105, but not with the upper surface 105a of the alignment pattern 105. Further, the alignment pattern 105 has a first region 130 that overlaps with the semiconductor pattern 111 and a second region 140 that does not overlap with the semiconductor pattern 111. Furthermore, the alignment pattern 105 has a groove portion 105c near the lower end of the semiconductor pattern 111 in the second region 140.
  • the semiconductor pattern 111 does not overlap the insulating layer 106. Therefore, even if there is a region with low crystallinity in a region overlapping with the insulating layer 106 when forming the semiconductor layer 108, it can be removed when forming the semiconductor pattern 111. Thereby, a semiconductor device can be manufactured using a semiconductor pattern with high crystallinity.
  • a semiconductor device 500 using the stacked structure 100 in the first embodiment will be described with reference to FIGS. 11 and 12.
  • FIG. 11 is an end view showing a semiconductor device 500 including the stacked structure 100 in the first embodiment.
  • the semiconductor device 500 shown in FIG. 11 is an example of an LED element manufactured using the semiconductor pattern 111 shown in FIG. 4.
  • the same elements as those in the laminated structure 100 shown in the first embodiment are given the same reference numerals and redundant explanations will be omitted.
  • a semiconductor device 500 includes a stacked structure 100 in the first embodiment, an n-type gallium nitride layer 501 provided on the semiconductor pattern of the stacked structure 100, and an n-type gallium nitride layer 501.
  • an n-type electrode 504 provided on the n-type electrode 504; a light-emitting layer 502 provided on the n-type gallium nitride layer 501; It has a p-type gallium nitride layer 503 and a p-type electrode 505 provided on the p-type gallium nitride layer 503.
  • the semiconductor device 500 is formed by the process described below. After the semiconductor pattern 111 shown in FIG. 4 is formed, an n-type gallium nitride layer 501, a light-emitting layer 502, and a p-type gallium nitride layer 503 are sequentially grown on the semiconductor pattern 111. Thereafter, parts of the n-type gallium nitride layer 501, the light emitting layer 502, and the p-type gallium nitride layer 503 are removed so that the n-type gallium nitride layer 501 is exposed.
  • an n-type electrode 504 and a p-type electrode 505 are formed in contact with the n-type gallium nitride layer 501 and the p-type gallium nitride layer 503, respectively.
  • the formation method of the n-type gallium nitride layer 501 and the p-type gallium nitride layer 503 please refer to the description of the semiconductor layer 108 having n-type conductivity and the semiconductor layer 108 having p-type conductivity in the first embodiment. Bye.
  • the semiconductor device 500 shown in FIG. 11 is completed.
  • the semiconductor device 500 of this embodiment is formed using a highly crystalline semiconductor pattern 111 formed on an amorphous substrate 101. Therefore, according to this embodiment, the semiconductor device 500 can be manufactured on the inexpensive amorphous substrate 101. Furthermore, since the semiconductor device 500 can be manufactured on the large-area amorphous substrate 101, productivity is improved. Further, according to this embodiment, since a highly crystalline gallium nitride layer can be formed by sputtering, the semiconductor device 500 can be manufactured with high throughput without being exposed to high temperatures throughout the process. Further, according to this embodiment, by using the stacked structure 100 having the fine semiconductor pattern 111, a high-definition semiconductor device can be formed.
  • the semiconductor device 500 shown in FIG. 11 is merely an example of an LED element, and an LED element with another structure may be used.
  • the light emitting layer 502 may have a quantum well structure in which gallium nitride layers and indium gallium nitride layers are alternately stacked.
  • the semiconductor device 500 is manufactured using the stacked structure 100, but the semiconductor device 500 may be manufactured using the stacked structure 100A.
  • FIG. 12 is a plan view showing a light emitting device 600 using a semiconductor device 500 including the stacked structure 100 in the first embodiment.
  • a display section 601 and a peripheral circuit section 602 are provided on the amorphous substrate 101.
  • a terminal section 603 for inputting various signals (video signals and control signals) to the light emitting device 600 is provided in a part of the peripheral circuit section 602.
  • a plurality of pixels 604 are arranged in a matrix.
  • the semiconductor device 500 shown in FIG. 11 is arranged in each pixel 604.
  • each pixel 604 may be provided with a semiconductor chip for controlling light emission and non-light emission of the semiconductor device 500.
  • ⁇ Fourth embodiment> an example in which a semiconductor device having a structure different from that in the second embodiment is formed will be described. Specifically, in this embodiment, an example will be described in which a HEMT (High Electron Mobility Transistor) is formed as a semiconductor device.
  • HEMT High Electron Mobility Transistor
  • the same elements as those in the laminated structure 100 shown in the first embodiment are given the same reference numerals and redundant explanations will be omitted.
  • FIG. 13 is an end view showing a semiconductor device 700 including a gallium nitride-based semiconductor layer in the fourth embodiment.
  • the semiconductor device 700 shown in FIG. 13 is an example of a HEMT manufactured using the semiconductor pattern 111 shown in FIG. 4 in the first embodiment.
  • a semiconductor device 700 includes the stacked structure 100 in the first embodiment, an n-type aluminum gallium nitride layer 701 provided on the semiconductor pattern of the stacked structure, and an n-type aluminum gallium nitride layer.
  • silicon nitride may be provided as a protective layer on the source electrode 703, the drain electrode 704, and the gate electrode 705.
  • the semiconductor device 700 is formed by the process described below.
  • An n-type aluminum gallium nitride layer 701 and an n-type gallium nitride layer 702 are sequentially formed on the semiconductor pattern 111 made of a gallium nitride-based semiconductor layer.
  • a sputtering method can be used to form these gallium nitride semiconductor layers.
  • a trench reaching the n-type aluminum gallium nitride layer 701 is provided in the n-type aluminum gallium nitride layer 701 and the n-type gallium nitride layer 702, and a source electrode 703 and a drain electrode 704 are arranged inside the trench.
  • a gate electrode 705 in contact with the n-type gallium nitride layer 702 is arranged between the source electrode 703 and the drain electrode 704. Finally, a silicon nitride layer 706 is formed as a protective layer, thereby completing the HEMT shown in FIG. 13.
  • the semiconductor device 700 of this embodiment is formed using a highly crystalline gallium nitride layer (semiconductor pattern 111) formed on an amorphous substrate 101. Therefore, according to this embodiment, the semiconductor device 700 can be manufactured on the inexpensive amorphous substrate 101. Furthermore, since the semiconductor device 500 can be manufactured on the large-area amorphous substrate 101, productivity is improved. Further, according to the present embodiment, since the plurality of gallium nitride-based semiconductor layers are formed by sputtering, the semiconductor device 700 can be manufactured with high throughput without being exposed to high temperatures throughout the process. Further, according to this embodiment, by using the stacked structure 100 having the fine semiconductor pattern 111, a high-definition semiconductor device can be formed. Note that the semiconductor device 700 shown in FIG. 13 is only an example of a HEMT, and a HEMT of another structure may be used.
  • N-type electrode 505... P-type electrode, 600... Light-emitting device, 601... Display Part, 602... Peripheral circuit part, 603... Terminal part, 604... Pixel, 700... Semiconductor device, 701... N-type aluminum gallium nitride layer, 702... N-type gallium nitride layer, 703... Source electrode, 704... Drain electrode, 705 ...Gate electrode, 706...Silicon nitride layer

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11243229A (ja) * 1997-12-02 1999-09-07 Murata Mfg Co Ltd 半導体発光素子、およびその製造方法
JP2004137135A (ja) * 2002-10-21 2004-05-13 Sumitomo Metal Ind Ltd 薄膜付き石英基板
WO2020188851A1 (ja) * 2019-03-15 2020-09-24 三菱電機株式会社 Ｌｅｄディスプレイ
WO2021187077A1 (ja) * 2020-03-19 2021-09-23 日東電工株式会社 窒化物積層体、及び窒化物積層体の製造方法
WO2022113949A1 (ja) * 2020-11-25 2022-06-02 日亜化学工業株式会社 画像表示装置の製造方法および画像表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11243229A (ja) * 1997-12-02 1999-09-07 Murata Mfg Co Ltd 半導体発光素子、およびその製造方法
JP2004137135A (ja) * 2002-10-21 2004-05-13 Sumitomo Metal Ind Ltd 薄膜付き石英基板
WO2020188851A1 (ja) * 2019-03-15 2020-09-24 三菱電機株式会社 Ｌｅｄディスプレイ
WO2021187077A1 (ja) * 2020-03-19 2021-09-23 日東電工株式会社 窒化物積層体、及び窒化物積層体の製造方法
WO2022113949A1 (ja) * 2020-11-25 2022-06-02 日亜化学工業株式会社 画像表示装置の製造方法および画像表示装置

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