WO2024046021A1 - Structure semi-conductrice et son procédé de fabrication - Google Patents

Structure semi-conductrice et son procédé de fabrication Download PDF

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Publication number
WO2024046021A1
WO2024046021A1 PCT/CN2023/110794 CN2023110794W WO2024046021A1 WO 2024046021 A1 WO2024046021 A1 WO 2024046021A1 CN 2023110794 W CN2023110794 W CN 2023110794W WO 2024046021 A1 WO2024046021 A1 WO 2024046021A1
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Prior art keywords
semiconductor
word line
along
pillars
layer
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PCT/CN2023/110794
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English (en)
Chinese (zh)
Inventor
唐怡
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长鑫存储技术有限公司
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Publication of WO2024046021A1 publication Critical patent/WO2024046021A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • a three-dimensional semiconductor structure refers to a three-dimensional stacked semiconductor structure, that is, the arrangement of transistors in the semiconductor structure is a stacked arrangement.
  • the three-dimensional stacked semiconductor structure has the characteristics of high density, large capacity and high speed.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to reduce parasitic capacitance in the semiconductor structure.
  • an embodiment of the present disclosure provides a semiconductor structure, including: a substrate and a plurality of semiconductor pillars formed on the substrate.
  • the semiconductor pillars extend along a first direction, and extend along a second direction and a third direction.
  • the semiconductor pillar includes a channel area, a source electrode and a drain electrode, the source electrode and the drain electrode are located on opposite sides of the channel area;
  • the word line covers at least part of the channel area of the semiconductor pillar, and the word line extends along the second direction, And along the second direction, multiple semiconductor pillars are connected to the same word line;
  • the bit line is connected to one of the source electrode or the drain electrode of the semiconductor pillar, the bit line extends along the third direction, and along the third direction, multiple semiconductor pillars are connected to the same word line.
  • the pillars are connected to the same bit line; the charge storage unit is connected to the other one of the source electrode or the drain electrode of the semiconductor pillar, and the charge storage unit extends along the first direction; wherein at least two bit lines are connected to different numbers of semiconductor pillars .
  • the maximum number of semiconductor pillars arranged is A
  • the maximum number of semiconductor pillars arranged is B, where A ⁇ B>1.
  • the number of semiconductor pillars connected to some bit lines increases sequentially.
  • the maximum number A of semiconductor pillars arranged along the second direction is at least twice the maximum number B of semiconductor pillars arranged along the third direction, that is, A ⁇ 2B>1, wherein, along the third direction, some positions The number of semiconductor pillars connected by the lines first increases and then decreases.
  • the semiconductor structure further includes: word line extension lines, the word line extension lines extend along the third direction and are arranged along the second direction, and along the second direction, the bottoms of different word line extension lines are connected to different word lines. , wherein the word line extension lines connected to at least two adjacent word lines are located at opposite ends of the word line.
  • the charge storage unit includes a capacitor
  • the capacitor includes a columnar capacitor or a cup-shaped capacitor.
  • the projections of adjacent bit lines on the plane where the first direction and the third direction are located only partially overlap or do not overlap.
  • another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a substrate, and forming a plurality of semiconductor pillars on the substrate, the semiconductor pillars extending along a first direction and along a second direction.
  • the semiconductor pillar includes a channel area, a source electrode and a drain electrode.
  • the source electrode and the drain electrode are located on opposite sides of the channel area; a word line is formed, and the word line covers at least part of the channel area of the semiconductor pillar.
  • the word line extends along the second direction, and along the second direction, multiple semiconductor pillars are connected to the same word line; forming a bit line, the bit line is connected to one of the source or drain of the semiconductor pillar, and the bit line is connected along the third direction. direction extending, and along the third direction, multiple semiconductor pillars are connected to the same bit line, wherein at least two bit lines are connected to different numbers of semiconductor pillars; a charge storage unit is formed, connected to the source or drain of the semiconductor pillar On the other hand, the charge storage unit extends along the first direction.
  • forming a plurality of semiconductor pillars includes: forming alternately stacked sacrificial layers and semiconductor layers on a substrate; forming a plurality of first insulating layers within the sacrificial layer and the semiconductor layer, the first insulating layers extending along a first direction. Extend and be arranged at intervals along the second direction; remove part of the sacrificial layer and the semiconductor layer, and at least part of the remaining sacrificial layer and semiconductor layer have a ladder structure; form a second insulating layer, and the second insulating layer covers and fills the spaces between the first insulating layers. gap, the remaining semiconductor layer serves as a semiconductor pillar.
  • the maximum number of semiconductor pillars arranged is A
  • the maximum number of semiconductor pillars arranged is B, where A ⁇ B>1.
  • forming the word line includes: forming a first isolation layer along the second direction, the semiconductor pillar penetrating the first isolation layer, and the channel region of the semiconductor pillar being located between the first isolation layer; The semiconductor pillar surfaces between them form word lines.
  • forming the word lines further includes: forming a second isolation layer between the first isolation layers along the second direction, the second isolation layer being located between adjacent word lines.
  • the method further includes: forming a filling layer, filling a gap between the source of the semiconductor pillar and the first isolation layer, and filling a gap between the source of the semiconductor pillar and the first isolation layer. The gap between the drain electrode and the first isolation layer.
  • the method further includes: forming word line extension lines, the word line extension lines extend along the third direction, and are arranged along the second direction, and along the second direction, the bottoms of different word line extension lines Connect different word lines.
  • the width of the word line extension line is smaller than the width of the word line.
  • forming the bit line includes: removing one end of the source electrode or the drain electrode of part of the semiconductor pillar along a third direction, and filling the conductive material to form the bit line.
  • Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • 3 to 11 are structural schematic diagrams of various steps corresponding to a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • DRAM dynamic random access memory
  • Some DRAM capacitor structures include cup-shaped capacitors or barrel-shaped capacitors.
  • One of the electrodes in the capacitor structure is formed into a container shape, and the dielectric material and the other electrode are formed inside the container-shaped electrode (for example, a single-side hole capacitor structure ); or only outside the container-shaped electrode (for example, a single-sided columnar capacitive structure); or both inside and outside the container-shaped electrode (for example, a double-sided capacitive structure).
  • the transistors are arranged in a stacked arrangement, and the stacking density between corresponding capacitor structures increases, resulting in a decrease in the distance between adjacent capacitor structures and an increase in parasitic capacitance.
  • an embodiment of the present disclosure provides a semiconductor structure to reduce parasitic capacitance in the semiconductor structure.
  • FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings. ,details as follows:
  • the semiconductor structure includes: a substrate (not shown in the figure) and a plurality of semiconductor pillars 100 formed on the substrate.
  • the semiconductor pillars 100 extend along the first direction X, and extend along the second direction Y and the third direction Z.
  • the semiconductor pillar 100 includes a channel area, a source electrode and a drain electrode.
  • the source electrode and the drain electrode are located on opposite sides of the channel area;
  • the word line 101 covers at least part of the channel area of the semiconductor pillar 100.
  • the word line 101 is arranged along the channel area.
  • the two directions Y extend, and along the second direction Y, multiple semiconductor pillars 100 are connected to the same word line 101; the bit line 102 is connected to one of the source or drain of the semiconductor pillar 100, and the bit line 102 is along the third direction.
  • Z extends, and along the third direction Z, multiple semiconductor pillars 100 are connected to the same bit line 102; the charge storage unit 103 is connected to the other one of the source electrode or the drain electrode of the semiconductor pillar 100, and the charge storage unit 103 is connected along the first
  • the direction X extends; wherein, at least two bit lines 102 are connected to different numbers of semiconductor pillars 100 .
  • the semiconductor pillars 100 along the first direction Z-arrangement By extending the semiconductor pillars 100 along the first direction Z-arrangement in three directions to increase the density of transistors. Among them, multiple semiconductor pillars 100 along the second direction Y are connected to the same word line 101, and multiple semiconductor pillars 100 along the third direction Z are connected to the same bit line 102, which can reduce the control terminals of the word line 101 and the bit line 102 in the semiconductor structure. .
  • the charge storage unit 103 connected to the source or drain of the semiconductor pillar 100 extends along the first direction X, and may have It is beneficial to increase the aspect ratio of the charge storage unit 103, that is, the ratio of length to width or diameter, thereby increasing the distance between the charge storage units 103 between adjacent transistors and avoiding parasitic capacitance between the charge storage units 103.
  • the number of semiconductor pillars 100 connected to at least two bit lines 102 is different.
  • the number of semiconductor pillars 100 can be appropriately reduced.
  • the spacing between the charge storage units 103 corresponding to the transistor structure formed by the semiconductor pillars 100 can be increased, thereby avoiding high cost. Parasitic capacitance generated in densely packed structures affects the performance of semiconductor structures.
  • the angle between the first direction X and the second direction Y is 90°
  • the plane where the first direction X and the second direction Y are located is parallel to the surface of the substrate
  • the third direction Z It is perpendicular to the surface of the substrate, that is, the angle between the plane where the first direction and the second direction are located and the third direction is 90°; in other embodiments, the angle between the first direction X and the second direction Y can be 30°.
  • the angle between the plane where the first direction and the second direction are located and the surface of the substrate can be 30°, 45° or 90°, where the angle between the third direction and the surface of the substrate can be 30°, 45° or 60°, and the angle between the plane where the first direction and the second direction are located and the third direction may be 30°, 45° or 60°.
  • This embodiment does not constitute a modification of the first direction, the second direction and the third direction.
  • the definition of the angle between the second direction and the third direction is not constitute a modification of the first direction, the second direction and the third direction.
  • the material of the semiconductor pillar 100 includes elemental semiconductor material or crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material may be one of silicon or germanium; the crystalline inorganic compound semiconductor material may be one of silicon carbide, silicon germanium, gallium arsenide or indium gallium.
  • the material of the semiconductor pillar 100 may also be one of IGZO (Indium Gallium Zinc Oxide), IZO (Indium Zinc Oxide) or ITO (Indium Tin Oxide).
  • the semiconductor pillar 100 is a quadrangular prism; in other embodiments, the semiconductor pillar can also be a polygonal prism, a cylinder or an elliptical prism.
  • This embodiment does not limit the shape of the semiconductor pillar. It can be understood that when the semiconductor pillar is a cylinder or an elliptical cylinder, the surface of the semiconductor pillar can be smoothly transitioned to avoid tip discharge or leakage during operation of the transistor structure formed by the semiconductor pillar; when the semiconductor pillar is a square prism. When it is a solid or polygonal prism, the edges and corners of the semiconductor pillars can be chamfered to make the edges and corners of the semiconductor pillars transition smoothly, and to avoid leakage or discharge caused by the tips.
  • the source electrode of the semiconductor pillar is used to connect the bit line
  • the drain electrode of the semiconductor pillar is used to connect the charge storage unit.
  • the specific connection method of "source electrode” and “drain electrode” defined above is , does not constitute a limitation to the embodiments of the present application. In other embodiments, a connection method in which "drain” replaces “source” and “source” replaces “drain” may be used.
  • the drawings provided in this embodiment only represent parts of the semiconductor structure. The schematic diagram of the arrangement structure of semiconductor pillars does not constitute a limit to the number of semiconductor pillar arrangements.
  • the maximum number of semiconductor pillars arranged is A
  • the maximum number of semiconductor pillars arranged is B, where A ⁇ B>1. Since the number of semiconductor pillars connected to at least two bit lines is different, by setting the maximum number of semiconductor pillars arranged along the second direction to A and the maximum number of semiconductor pillars arranged along the third direction to B, where A ⁇ B>1, That is, the number of semiconductor pillars arranged laterally is greater than the number stacked vertically.
  • This arrangement of semiconductor pillars can form a ladder structure, thereby appropriately reducing the arrangement density of semiconductor pillars, thereby increasing the spacing between corresponding charge storage units of the transistors formed by semiconductor pillars. Reduce parasitic capacitance between transistor structures.
  • the number of semiconductor pillars 100 connected to some bit lines 102 increases in sequence.
  • the corresponding transistor structures can be arranged in a ladder structure, thereby appropriately reducing the arrangement density of the transistor structures and reducing the parasitic capacitance between the transistor structures.
  • the maximum number A of semiconductor pillars arranged along the second direction is at least twice the maximum number B of semiconductor pillars arranged along the third direction, that is, A ⁇ 2B>1, wherein, along the third direction, part of The number of semiconductor pillars connected to the bit lines first increases and then decreases.
  • the corresponding transistor structures can be arranged in a pyramid structure, thereby appropriately reducing the arrangement density of the transistor structure and reducing the transistor structure. parasitic capacitance between them.
  • the charge storage units connected to the other one of the source electrode or the drain electrode of the semiconductor pillar are arranged in a ladder shape. It can be understood that the charge storage units and the semiconductor pillars extend in the same direction. When the semiconductor pillars are arranged in a ladder or pyramid shape, correspondingly, the charge storage units connected to the drain electrodes of the semiconductor pillars are arranged in a ladder or pyramid shape. , thereby increasing the spacing between charge storage units, reducing the parasitic capacitance between charge storage units.
  • the material of the word line 101 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper or tungsten.
  • the word line 101 covers the entire surface of the channel region of the semiconductor pillar 100, that is, the word line 101 is arranged around the semiconductor pillar 100; in other embodiments, the word line can also be arranged through the interior of the semiconductor pillar, that is, the trench.
  • the word line may only cover the top surface of the semiconductor pillar channel region to A single-sided gate structure is formed; or, the word line covers the top surface and sidewalls of the semiconductor pillar channel region to form a fin gate structure.
  • the word line covering the surface of the semiconductor pillar may also include a dielectric layer.
  • the dielectric layer covers the surface of the channel region of the semiconductor pillar.
  • the word line covers the surface of the dielectric layer of the semiconductor pillar.
  • the dielectric layer can prevent the word line from being damaged during subsequent processes. Reacts with the semiconductor pillars to avoid damage to the semiconductor structure.
  • the semiconductor structure further includes: word line extension lines 111 , the word line extension lines 111 extend along the third direction Z, and are arranged along the second direction Y. Along the second direction Y, different The bottom of the word line extension line 111 is connected to different word lines 101 . It can be understood that when the number of stacked semiconductor pillars 100 is gradually increased in a sequential manner, the number of semiconductor pillars 100 connected to the word line 101 from bottom to top gradually decreases, and correspondingly, the length of the word line 101 increases from bottom to top.
  • the word line 101 can form a ladder structure, and then the extension direction of the word line 101 can be changed from the second direction Y to the third direction Z through the word line extension line 111.
  • the corresponding control end and bit of the word line 101 can be shortened gradually.
  • the control ends of line 102 may be located in the same direction to facilitate connection to the corresponding control port of word line 101.
  • the material of the word line extension line 111 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper or tungsten.
  • the word line extension line 111 is made of the same material as the word line 101 and is represented by the same characteristics, thereby reducing the contact resistance between the word line and the word line contact line; in other embodiments, the word line extension The material of the lines can be different from the material of the word lines.
  • the number of semiconductor pillars 100 connected to some bit lines 102 along the third direction Z when the number of semiconductor pillars 100 connected to some bit lines 102 along the third direction Z first increases and then decreases, the number of semiconductor pillars 100 connected to at least two adjacent word lines 101
  • the word line extension lines 111 may be located at opposite ends of the word line 101 .
  • the corresponding transistor structures formed are arranged in a pyramid structure, the length of the word line 101 gradually shortens from bottom to top, and both ends of the word line 101 can be formed
  • the corresponding word line extension lines 111 can be alternately distributed at both ends of the word line 101, thereby reducing the distance between the word line extension lines 111 and reducing the parasitic capacitance between the word line extension lines 111.
  • a part of the word line extension lines may be arranged in sequence at one end of the word line, and another part of the word line extension lines may be arranged in sequence at the other end of the word line.
  • the material of the bit line 102 may be a single metal, a metal compound or an alloy.
  • the single metal may be copper, aluminum, tungsten, gold or silver; the metal compound may be tantalum nitride or titanium nitride; and the alloy may be an alloy material composed of at least two of copper, aluminum, tungsten, gold or silver. Setting the material of the bit line 102 to a metal material can make the bit line 102 have a smaller resistivity, which is beneficial to the bit line 102.
  • the resistance of the line 102 increases the transmission rate of electrical signals in the bit line 102, reduces the parasitic capacitance of the bit line 102, and reduces heat loss to reduce power consumption.
  • the projections of adjacent bit lines on the plane where the first direction and the third direction are located only partially overlap or do not overlap. That is, in the second direction, adjacent bit lines can be distributed in a staggered manner, thereby increasing the distance between adjacent bit lines and reducing parasitic capacitance between adjacent bit lines.
  • the charge storage unit includes a capacitor, and the capacitor includes a columnar capacitor or a cup-shaped capacitor.
  • the structure of the columnar capacitor is simple, which facilitates the production of semiconductor structures; the cup-shaped capacitor can increase the relative area between the upper plate and the lower plate of the capacitor and improve the storage capacity of the capacitor.
  • the transistors formed corresponding to the semiconductor pillars 100 can extend along the first direction X. , and are arranged along the second direction Y and the third direction Z to increase the arrangement density of the transistors; wherein, multiple semiconductor pillars 100 along the second direction Y are connected to the same word line 101, and multiple semiconductor pillars along the third direction Z are connected.
  • the charge storage unit 103 connected to the source or drain of the semiconductor pillar 100 extends along the first direction X, which can be beneficial to increasing the charge.
  • the aspect ratio of the storage unit 103 is the ratio of length to width or diameter, thereby increasing the distance between charge storage units 103 between adjacent transistors and avoiding parasitic capacitance between the charge storage units 103.
  • It can avoid tilting when the aspect ratio of the charge storage unit 103 is large, and avoid damage to the semiconductor structure; among them, the number of semiconductor pillars 100 connected to at least two bit lines 102 is different, and the number of semiconductor pillars 100 can be appropriately reduced.
  • the spacing between the charge storage units 103 of the transistor structure formed by the semiconductor pillars 100 is increased, thereby avoiding parasitic capacitance generated in a high-density stacked structure that affects the performance of the semiconductor structure.
  • embodiments of the present disclosure also provide a method of manufacturing a semiconductor structure to reduce parasitic capacitance in the semiconductor structure. It should be noted that for parts that are the same as or corresponding to the above-mentioned embodiments, reference may be made to the corresponding descriptions of the foregoing embodiments and will not be described in detail below.
  • FIG. 3 to 11 are structural schematic diagrams of various steps corresponding to a method for manufacturing a semiconductor structure provided by yet another embodiment of the present disclosure.
  • Fig. 6 is a schematic cross-sectional structural diagram along the direction AA1 of Fig. 5
  • Fig. 8 is a schematic diagram of the cross-sectional structure along the AA1 direction of Fig. 7
  • Figures 9 to 11 are schematic cross-sectional structural diagrams along the BB1 direction in Figure 7.
  • a substrate is provided, and a plurality of semiconductor pillars are formed on the substrate, the semiconductor pillars extending along the first direction, And arranged along the second direction and the third direction, the semiconductor pillar includes a channel region, a source electrode and a drain electrode, and the source electrode and the drain electrode are located on opposite sides of the channel region.
  • a plurality of semiconductor pillars are formed, including: with reference to FIG. 3 , forming alternately stacked sacrificial layers 201 and semiconductor layers 202 on the substrate 200 ; with reference to FIG. 4 , forming within the sacrificial layers 201 and semiconductor layers 202 A plurality of first insulating layers 203 are formed.
  • the first insulating layers 203 extend along the first direction
  • the remaining sacrificial layer 201 and the semiconductor layer 202 have a ladder structure; referring to Figure 7, a second insulating layer 204 is formed, the second insulating layer 204 covers and fills the gap between the first insulating layers 203, and the remaining semiconductor layer 202 serves as the semiconductor pillar 212.
  • the maximum number of semiconductor pillars 212 arranged is A
  • the third direction Z the maximum number of semiconductor pillars 212 arranged is B, where A ⁇ B>1.
  • the arrangement of the semiconductor pillars can form a ladder structure, thereby appropriately reducing the arrangement density of the semiconductor pillars, thereby increasing the spacing between corresponding charge storage units of the transistors formed by the semiconductor pillars, and reducing the parasitic capacitance between the transistor structures.
  • the number of alternately stacked sacrificial layers 201 and semiconductor layers 202 is 3, that is, the number of sacrificial layers 201 is 3, and the number of semiconductor layers 202 is 3; in other implementations
  • the number of alternately stacked sacrificial layers 201 and semiconductor layers 202 can also be 4, 6, 10, or 20 layers. That is, the number of sacrificial layers 201 and the number of semiconductor layers 202 are both 4 or 6. , 10 layers or 20 layers.
  • This embodiment does not constitute a limitation on the number of alternately stacked sacrificial layers 201 and semiconductor layers 202 .
  • the material forming the substrate 200 includes elemental semiconductor materials or crystalline inorganic compound semiconductor materials.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or indium gallium, etc.
  • the material forming the semiconductor layer includes elemental semiconductor material or crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or indium gallium, etc.
  • the material forming the sacrificial layer 201 includes silicon germanium.
  • the materials forming the first insulating layer 203 and the second insulating layer 204 include silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the material forming the first insulating layer 203 is the same as the material forming the second insulating layer 204 and is represented by the same characteristics; in other embodiments, the material forming the first insulating layer may be the same as the material forming the second insulating layer 204 .
  • the insulation layer is made of different materials.
  • the sacrificial layer and the semiconductor layer both have a thickness of 20 nm to 60 nm.
  • the semiconductor layer is used to form semiconductor pillars. The greater the thickness of the semiconductor layer, the larger the diameter of the semiconductor pillars formed, and the number of stacked semiconductor pillars in the unit space is reduced. The thinner the thickness of the semiconductor layer, the corresponding formation of semiconductor pillars. The smaller the diameter of the semiconductor pillars, the arrangement density between the semiconductor pillars increases accordingly, and the distance between the charge storage units decreases. Parasitic capacitance is easily generated between the charge storage units, which affects the performance of the semiconductor structure.
  • the semiconductor layer The thickness needs to be adjusted within a certain range to maximize the arrangement density of semiconductor pillars while avoiding parasitic capacitance between charge storage units and improving the reliability of the semiconductor structure.
  • the sacrificial layer is located between the semiconductor layers.
  • the thickness of the sacrificial layer corresponds to the distance between the semiconductor pillars.
  • the corresponding distance between the semiconductor pillars needs to be adjusted within a certain range according to the arrangement requirements of the semiconductor pillars to avoid between semiconductor pillars. Too close a distance between them will affect the performance of the semiconductor structure, while avoiding too far a distance between the semiconductor pillars will reduce the integration density of the semiconductor structure.
  • a word line is formed, the word line covers at least part of the channel region of the semiconductor pillar, the word line extends along the second direction, and along the second direction, multiple semiconductor pillars are connected to the same word line.
  • forming the word line 206 includes: forming a first isolation layer 205 along the second direction Y, the semiconductor pillar 212 penetrating the first isolation layer 205 , and the channel region of the semiconductor pillar 212 is located between the first isolation layer 205 between; remove the sacrificial layer 201 between the first isolation layers 205, and form a word line 206 on the surface of the semiconductor pillar 212 between the first isolation layers 205.
  • a dielectric layer 216 is also formed before forming the word line 206.
  • the dielectric layer 216 covers the surface of the channel region of the semiconductor pillar 212.
  • the word line 206 covers the surface of the dielectric layer 216 of the semiconductor pillar 212.
  • the dielectric layer 216 may This prevents the word line 206 from reacting with the semiconductor pillar 212 during subsequent processes, thereby avoiding damage to the semiconductor structure.
  • the material forming the word line 206 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.
  • the material forming the first isolation layer 205 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the material forming the dielectric layer 216 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the material forming the dielectric layer 216 is the same as the material forming the first insulating layer 203 and is represented by the same characteristics; in other embodiments, the material forming the dielectric layer may be the same as the material forming the first insulating layer. different.
  • forming the word lines 206 further includes: forming a second isolation layer 207 between the first isolation layers 205 along the second direction Y, and the second isolation layer 207 is located between adjacent word lines 206 .
  • the first isolation layer 205 and the second isolation layer 207 can isolate different word lines 206, preventing adjacent word lines 206 from being connected to each other and causing the performance of the semiconductor structure to be affected, and improving the stability of the semiconductor structure.
  • the material forming the second isolation layer 207 includes silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the material 205 forming the first isolation layer is the same as the material forming the second isolation layer 207 and represented by the same characteristics; in other embodiments, the material forming the first isolation layer may be the same as the material forming the second isolation layer 207 .
  • the material of the isolation layer is different.
  • the step of forming the word line and the second isolation layer includes: after forming a dielectric layer on the surface of the semiconductor pillar, before forming the word line, between the lowest semiconductor pillars between the first isolation layer A first word line is formed first, and the first word line fills the gap between the semiconductor pillars at the bottom layer; a second isolation layer is formed on the surface of the first word line; a second isolation layer is formed between the semiconductor pillars on the second isolation layer.
  • the second word line fills the gap between the second layer of semiconductor pillars in the direction away from the substrate; forms a second isolation layer on the surface of the second word line; continues the semiconductor pillars on the second isolation layer A third word line is formed between them, and the third word line fills the gap between the third layer of semiconductor pillars in the direction away from the substrate; a second isolation layer is formed on the surface of the third word line, thereby repeatedly forming the word line and second isolation layer.
  • the step of forming the word line and the second isolation layer includes: after forming a dielectric layer on the surface of the semiconductor pillar, before forming the word line, forming an initial word line to fill all the semiconductor pillars between the first isolation layer gaps between them; forming a plurality of word line isolation trenches along the second direction, the word line isolation trenches being located within the initial word lines between the first isolation layers and between adjacent semiconductor pillars; using insulating material to fill the word lines The trench is isolated to form a second isolation layer, and the remaining initial word lines serve as word lines.
  • the method further includes: forming a word line extension line 226 .
  • the word line extension line 226 extends along the third direction Z and is arranged along the second direction Y. In the two directions Y, the bottoms of different word line extension lines 226 are connected to different word lines 206 . It can be understood that when the number of stacked semiconductor pillars is gradually increased in a sequential manner, the number of semiconductor pillars connected to the word line from bottom to top gradually decreases, and accordingly, the length of the word line can be gradually shortened from bottom to top.
  • the word line can form a ladder structure, and the extending direction of the word line can be changed from the second word line through the word line extension line.
  • the control end of the corresponding word line and the control end of the bit line can be located in the same direction, so as to facilitate the connection of the corresponding control port of the word line.
  • the material forming the word line extension line 226 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.
  • the width of the word line extension line is smaller than the width of the word line. It can be understood that the bottom of the word line extension line is in contact with the word line, so that the word line and the word line extension line are electrically connected.
  • the width of the word line extension line is smaller than the width of the word line, which facilitates the production of the semiconductor structure, and The smaller diameter of the word line extension line can avoid taking up too much space and affecting other devices in the semiconductor structure.
  • the material forming the word line extension 226 is the same as the material forming the word line 206 and is represented by the same characteristics; in other embodiments, the material of the word line extension 226 may be different from the material of the word line.
  • the method further includes: forming a filling layer 208 , and the filling layer 208 fills the source of the semiconductor pillar 212 to the first isolation layer 205 and fill the gap between the drain electrode of the semiconductor pillar 212 and the first isolation layer 205 .
  • the filling layer fills the gaps between the semiconductor pillars, which can isolate the transistor structures formed by different semiconductor pillars, prevent adjacent transistor structures from being connected to each other, and improve the reliability of the semiconductor structure.
  • the material of the filling layer 208 includes silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • bit line 209 is formed.
  • the bit line 209 is connected to one of the source or drain electrodes of the semiconductor pillars 212 .
  • the bit line 209 extends along the third direction Z, and along the third direction Z, a plurality of semiconductor pillars 212 The same bit line 209 is connected, wherein at least two bit lines 209 are connected to different numbers of semiconductor pillars 212 .
  • forming the bit line 209 includes: removing one end of the source electrode or the drain electrode of part of the semiconductor pillar 212 and part of the filling layer 208 along the third direction Z, and filling the conductive material to form the bit line 209 .
  • a charge storage unit 300 is formed, the charge storage unit 300 is connected to the other one of the source electrode or the drain electrode of the semiconductor pillar 212 , and the charge storage unit 300 extends along the first direction X.
  • the charge storage unit 300 includes: a lower electrode layer 301, a capacitive dielectric layer 302, and an upper electrode layer 303.
  • the lower electrode layer 301 covers the surface of the source or drain of the semiconductor pillar 212
  • the capacitive dielectric layer 301 covers the source or drain surface of the semiconductor pillar 212.
  • the layer 302 covers the surface of the lower electrode layer 301
  • the upper electrode layer 303 covers the surface of the capacitive dielectric layer 302 .
  • the materials forming the lower electrode layer 301 and the upper electrode layer 303 can be platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or At least one of ruthenium.
  • the material forming the capacitive dielectric layer 302 includes silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or strontium titanate. High dielectric constant materials such as barium.
  • the material forming the upper electrode layer 303 is the same as the material forming the lower electrode layer 301 and is represented by the same characteristics; in other embodiments, the material forming the upper electrode layer and the material forming the lower electrode layer may be different.
  • the semiconductor structure manufacturing method provided by the embodiment of the disclosure can form semiconductor pillars 212 extending along the first direction X and arranged along the second direction Y and the third direction Z, so that the transistors formed corresponding to the semiconductor pillars 212 can be formed along the first direction.
  • Two semiconductor pillars 212 are connected to the same bit line 209, which can reduce the control terminals of the word line 206 and the bit line 209 in the semiconductor structure; the charge storage unit 300 connected to the source or drain of the semiconductor pillar 212 extends along the first direction X, and can have It is beneficial to increase the aspect ratio of the charge storage unit 300, that is, the ratio of length to width or diameter, thereby increasing the distance between the charge storage units 300 between adjacent transistors, avoiding parasitic capacitance between the charge storage units 300, and compared with the vertical
  • the transistor structure can avoid tilting when the aspect ratio of the charge storage unit 300 is large, and avoid damage to the semiconductor structure; among them, the number of semiconductor pillars 212 connected to at least two bit lines 209 is different, and the number of semiconductor pillars 212 can be appropriately reduced. , correspondingly, the spacing between the charge storage units 103 of the transistor structure formed by the semiconductor pillars 212 is increased, thereby preventing parasitic capacitance from affecting the performance of the semiconductor structure

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Abstract

Sont divulgués une structure semi-conductrice et son procédé de fabrication. La structure comprend : un substrat, des colonnes semi-conductrices, des lignes de mots, des lignes de bits et des unités de stockage de charge. La pluralité de colonnes semi-conductrices sont placées sur le substrat dans une deuxième direction et une troisième direction, et les colonnes semi-conductrices comprennent chacune une source, une région de canal et un drain qui sont agencés dans une première direction. Les lignes de mots s'étendent dans la deuxième direction et recouvrent au moins les régions de canal de certaines des colonnes semi-conductrices. Les lignes de bits s'étendent dans la troisième direction et sont chacune connectées à l'un parmi la source et le drain de chacune de la pluralité de colonnes semi-conductrices. Les unités de stockage de charge s'étendent dans la première direction et sont chacune connectées à l'autre parmi la source et le drain de chacune des colonnes semi-conductrices. Le nombre de colonnes semi-conductrices connectées à au moins deux lignes de bits est différent.
PCT/CN2023/110794 2022-08-29 2023-08-02 Structure semi-conductrice et son procédé de fabrication WO2024046021A1 (fr)

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Citations (5)

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US10043855B1 (en) * 2017-05-31 2018-08-07 National Technology & Engineering Solutions Of Sandia, Llc Compensating for parasitic voltage drops in circuit arrays
US20200279601A1 (en) * 2019-02-28 2020-09-03 SK Hynix Inc. Vertical memory device
US11282548B1 (en) * 2021-05-04 2022-03-22 Micron Technology, Inc. Integrated assemblies and methods forming integrated assemblies
CN114783481A (zh) * 2021-01-05 2022-07-22 美光科技公司 集成组合件
CN115425025A (zh) * 2022-08-29 2022-12-02 长鑫存储技术有限公司 半导体结构及其制作方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10043855B1 (en) * 2017-05-31 2018-08-07 National Technology & Engineering Solutions Of Sandia, Llc Compensating for parasitic voltage drops in circuit arrays
US20200279601A1 (en) * 2019-02-28 2020-09-03 SK Hynix Inc. Vertical memory device
CN114783481A (zh) * 2021-01-05 2022-07-22 美光科技公司 集成组合件
US11282548B1 (en) * 2021-05-04 2022-03-22 Micron Technology, Inc. Integrated assemblies and methods forming integrated assemblies
CN115425025A (zh) * 2022-08-29 2022-12-02 长鑫存储技术有限公司 半导体结构及其制作方法

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