WO2024045820A1 - 功率放大器、功率放大器组件和信号处理设备 - Google Patents

功率放大器、功率放大器组件和信号处理设备 Download PDF

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Publication number
WO2024045820A1
WO2024045820A1 PCT/CN2023/102633 CN2023102633W WO2024045820A1 WO 2024045820 A1 WO2024045820 A1 WO 2024045820A1 CN 2023102633 W CN2023102633 W CN 2023102633W WO 2024045820 A1 WO2024045820 A1 WO 2024045820A1
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Prior art keywords
electrically connected
transistor
power amplifier
transformer
power
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PCT/CN2023/102633
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English (en)
French (fr)
Inventor
陈志林
马宵宵
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深圳市中兴微电子技术有限公司
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Publication of WO2024045820A1 publication Critical patent/WO2024045820A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Definitions

  • the present disclosure relates to the field of communication equipment, and in particular to power amplifiers, power amplifier components, and signal processing equipment.
  • the transceiver may need to integrate large-scale front-end array channels, so the PA module It may need to be integrated into the transceiver chip and implemented using a silicon-based process, but it cannot be used like the fourth generation mobile communication technology (4G) and the third generation mobile communication technology (3G), that is, the PA alone uses the III-V family process to achieve high output power. , but it still requires the PA to have larger output power.
  • 4G fourth generation mobile communication technology
  • 3G third generation mobile communication technology
  • 5G communications require high-order modulation methods, which require a larger peak-to-average power ratio (PAPR) and higher linear output power. Therefore, higher requirements are also put forward for the linearity of the PA. .
  • a power amplifier includes a first transistor and a second transistor.
  • the gate of the first transistor is electrically connected to the gate of the second transistor.
  • the first transistor is The first pole of the transistor is electrically connected to the positive output terminal of the power amplifier, the first pole of the second transistor is electrically connected to the negative output terminal of the power amplifier, the power amplifier further includes a peaking inductor, the The first end of the peaking inductor is electrically connected to the second pole of the first transistor, and the second end of the peaking inductor is electrically connected to the second pole of the second transistor.
  • a power amplifier assembly includes a driver stage amplifier and at least one power stage amplifier.
  • the driver stage amplifier is an embodiment of the first aspect of the present disclosure.
  • the power amplifier described above, the power stage amplifier is the power amplifier described in another implementation manner of the first aspect of the present disclosure.
  • a signal processing device includes a power amplifier component, and the power amplifier component includes the power amplifier component described in the second aspect of the present disclosure.
  • Figure 1 is a schematic diagram of an embodiment of a power amplifier provided by the present disclosure
  • Figure 2 is a schematic diagram of an implementation of a power amplifier provided by the present disclosure
  • Figure 3 is a circuit schematic diagram of a power amplifier assembly provided by the present disclosure.
  • Figure 4 is a schematic diagram of two third transformers provided by the present disclosure.
  • the main structures include the following: differential common source structure, differential cascode structure, Differential stacking structure.
  • the differential common source structure has high linearity, but the output power is low.
  • the common source structure works in a high output power state, there is a risk of breakdown and is reliable.
  • the performance is low; the differential cascode structure has moderate linearity and output power, but for 5G communications, the single-stage differential cascode structure still cannot meet the requirements of 5G communications.
  • a differential stacked transistor structure has been proposed in recent years.
  • a power amplifier is provided. As shown in FIG. 1 , the power amplifier includes a first transistor M1 and a second transistor M2. The gate electrode of the first transistor M1 is in contact with the gate electrode of the second transistor M2. connection, the first pole of the first transistor M1 is electrically connected to the positive output terminal Out+ of the power amplifier, and the first pole of the second transistor M2 is electrically connected to the negative output terminal Out- of the power amplifier.
  • the power amplifier further includes a peaking inductor L2, a first end of the peaking inductor L2 is electrically connected to the second pole of the first transistor M1, and a second end of the peaking inductor L2 is electrically connected to the second pole of the second transistor M2. connect.
  • the peaking inductor L2 connected in parallel between the positive output terminal Out+ and the negative output terminal Out- can resonate out the influence of the parasitic capacitance, thereby improving the output power of the power amplifier.
  • both the first transistor M1 and the second transistor M2 are N-type transistors, and the size of the first transistor M1 is the same as the size of the second transistor M2.
  • the gate of the first transistor M1 and the gate of the second transistor M2 need to be electrically connected to the bias input terminal Bias to maintain the normal operation of the power amplifier.
  • the "first transistor M1" and the “second transistor M2” may be transistors or field effect transistors.
  • the "gate” mentioned in this disclosure is the base region of the transistor. of electrodes. "Gate”, “base”, “gating electrode”, etc. are all equivalent to the "gate” shown in this disclosure.
  • the first pole of the first transistor M1 when powered on, the first pole of the first transistor M1 is the drain of the first transistor M1, the second pole of the first transistor M1 is the source of the first transistor M1, and the second pole of the first transistor M1 is the source of the first transistor M1.
  • the first pole of the transistor M2 is the drain of the second transistor M2, and the second pole of the second transistor M2 is the source of the second transistor M2.
  • the power amplifier further includes a first auxiliary capacitor C1, a second auxiliary capacitor C2 and a resonant inductor L1.
  • the first end of the first auxiliary capacitor C1 is electrically connected to the first pole of the first transistor M1.
  • the second end of an auxiliary capacitor C1 is electrically connected to the first end of the second auxiliary capacitor C2, the second end of the second auxiliary capacitor C2 is electrically connected to the first pole of the second transistor M2, and the first end of the resonant inductor L1 is electrically connected to
  • the second terminal of the first auxiliary capacitor C1 is electrically connected, and the second terminal of the resonant inductor L1 is electrically connected to the reference signal terminal.
  • Providing the first auxiliary capacitor C1 and the second auxiliary capacitor C2 can adjust the output impedance of the power amplifier, so that the power amplifier has sufficient output power to drive a subsequent-stage power amplifier.
  • the first auxiliary capacitor C1, the second auxiliary capacitor C2 and the resonant inductor L1 can form an LC network.
  • the LC network resonates at the second harmonic. Combined with the LC network of the input stage matching circuit (this circuit will be introduced below), it can Further improve the linearity of the power amplifier.
  • the reference signal terminal electrically connected to the second terminal of the resonant inductor L1 may be a virtual ground node.
  • the size of the first auxiliary capacitor C1 may be the same as the size of the second auxiliary capacitor C2.
  • the power amplifier may be a power amplifier having a cascode structure. That is to say, the power amplifier further includes a third transistor M3 and a fourth transistor M4.
  • the first pole of the third transistor M3 is electrically connected to the first pole of the fourth transistor M4 and is electrically connected to the reference signal terminal.
  • the gate of the transistor M3 is electrically connected to the positive input terminal In+ of the input signal
  • the gate of the fourth transistor M4 is electrically connected to the negative input terminal In- of the input signal
  • the second electrode of the third transistor M3 is connected to the second electrode of the first transistor M1 electrically connected, the second pole of the fourth transistor M4 and the The second poles of the two transistors M2 are electrically connected.
  • both the third transistor M3 and the fourth transistor M4 are N-type transistors, and the size of the third transistor M3 may be the same as the size of the fourth transistor M4.
  • the second pole of the third transistor M3 when powered on, the second pole of the third transistor M3 is the drain of the third transistor, the first pole of the third transistor M3 is the source of the third transistor, and the fourth transistor M4 The second pole of M4 is the drain of the fourth transistor, and the first pole of the fourth transistor M4 is the source of the fourth transistor.
  • the power amplifier may further include a first neutralizing capacitor C3 and a second neutralizing capacitor C4.
  • One end of the first neutralizing capacitor C3 is electrically connected to the second electrode of the third transistor M3, the other end of the first neutralizing capacitor C3 is electrically connected to the input signal negative input terminal In-, and one end of the second neutralizing capacitor C4 is electrically connected to the second electrode of the third transistor M3.
  • the second pole of the four-transistor M4 is electrically connected, and the other end of the second neutralizing capacitor C4 is electrically connected to the input signal positive input terminal In+. Setting the first neutralizing capacitor C3 and the second neutralizing capacitor C4 can neutralize the parasitic capacitances of the third transistor M3 and the fourth transistor M4, thereby improving the stability and gain of the power amplifier.
  • the first neutralizing capacitor C3 and the second neutralizing capacitor C4 have the same size.
  • the power amplifier further includes a variable capacitor.
  • the variable capacitor includes a first P-type transistor M5 and a second P-type transistor M6.
  • the first P-type transistor M5 has a One pole is electrically connected to the second pole of the first P-type transistor M5, the first pole of the second P-type transistor M6 is electrically connected to the second pole of the second P-type transistor M6, and the first pole of the first P-type transistor M5
  • the gate electrode of the first P-type transistor M5 is electrically connected to the positive input terminal In+ of the input signal
  • the gate electrode of the second P-type transistor M6 is electrically connected to the negative input terminal In of the input signal. -Electrical connection.
  • the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 in the power amplifier are all N-type transistors. After setting a variable capacitor composed of a P-type transistor, the variable capacitor will change accordingly.
  • the power change characteristics are opposite to the power variation characteristics of the parasitic capacitance formed by the N-type transistor, which can compensate for the amplitude modulation-phase modulation (AM-PM) characteristics of the power amplifier and improve the linearity of the power amplifier.
  • AM-PM amplitude modulation-phase modulation
  • the first P-type transistor M5 and the second P-type transistor M6 have the same size.
  • a power amplifier assembly As a second aspect of the present disclosure, a power amplifier assembly is provided. As shown in Figure 3, the power amplifier assembly includes a driver stage amplifier A1 and at least one power stage amplifier.
  • the driver stage amplifier A1 is the first aspect of the present disclosure.
  • a power amplifier provided by an embodiment of the disclosure, and the power stage amplifier is a power amplifier provided by another embodiment of the first aspect of the present disclosure.
  • the driving stage amplifier A1 may be the power amplifier shown in Figure 1.
  • the peaking inductor L2 connected in parallel between the positive output terminal Out+ and the negative output terminal Out- can resonate out The influence of parasitic capacitance can improve the output power of the power amplifier.
  • Setting the first auxiliary capacitor C1 and the second auxiliary capacitor C2 can adjust the output impedance of the power amplifier, so that the power amplifier has enough output power to drive the subsequent power amplifier (ie, power stage amplifier).
  • the power stage amplifier may be the power amplifier shown in FIG. 2 .
  • the power stage amplifier also has better linearity.
  • the number of power stage amplifiers is not particularly limited.
  • the amplifier assembly may include two power stage amplifiers, namely power stage amplifier A2 and power stage amplifier A3. Two power stage amplifiers are combined, and the two power stage amplifiers have the same structure.
  • the power amplifier assembly also includes an input stage matching circuit 100.
  • the input stage matching circuit 100 includes a first transformer TF1, a first matching capacitor C5, a second matching capacitor C7 and a third auxiliary capacitor C6.
  • a matching capacitor C5 is connected across both ends of the primary coil of the first transformer TF1
  • a second matching capacitor C7 is connected across both ends of the secondary coil of the first transformer TF1
  • the first end of the third auxiliary capacitor C6 is connected to the first end of the secondary coil of the first transformer TF1.
  • the tap of the secondary coil of the first transformer TF1 is electrically connected, the second end of the third auxiliary capacitor C6 is electrically connected to the reference signal end, and both ends of the secondary coil of the first transformer TF1 are respectively connected to the positive input end of the driver stage amplifier A1 and The negative input terminal of the driver stage amplifier A1 is electrically connected.
  • the first matching capacitor C5 and the second matching capacitor C7 can tune the impedance to achieve impedance matching of the driver stage amplifier A1, and the third auxiliary capacitor C6 forms a second harmonic with the inductance of the secondary coil of the first transformer TF1 LC network can further increase power Linearity of amplifier components.
  • the middle tap of the secondary coil of the first transformer TF1 is electrically connected to the bias signal terminal Bias1.
  • the input terminal of the first transformer TF1 is the input terminal PA_IN of the power amplifier component.
  • the power amplifier assembly further includes an inter-stage matching circuit 200.
  • the inter-stage matching circuit 200 includes a second transformer TF2, a third matching capacitor C9 and a fourth auxiliary capacitor C8.
  • the primary coil of the second transformer TF2 Both ends of are electrically connected to the positive output terminal and the negative output terminal of the drive stage amplifier A1 respectively.
  • the two ends of the third matching capacitor C9 are connected across the two ends of the secondary coil of the second transformer TF2.
  • the fourth auxiliary capacitor C8 is One end is electrically connected to the middle tap of the secondary coil of the second transformer TF2, the second end of the fourth auxiliary capacitor C8 is electrically connected to the reference signal terminal, and both ends of the secondary coil of the second transformer TF2 are respectively connected to the power stage.
  • the positive input terminal and the negative input terminal of the amplifier are electrically connected.
  • the center tap of the primary coil of the second transformer TF2 is electrically connected to the high-level signal terminal VDD1.
  • the middle tap of the secondary coil of the second transformer TF2 is grounded through the fourth auxiliary capacitor C8, and at the same time, the middle tap of the secondary coil of the second transformer TF2 is electrically connected to the bias voltage signal terminal Bias3.
  • Both ends of the third matching capacitor C9 are connected across the two ends of the secondary coil of the second transformer TF2 to achieve impedance adjustment, achieve impedance matching between the driver stage amplifier A1 and the power stage power amplifier, and achieve the maximum output of the driver stage amplifier. Power transfer.
  • the fourth auxiliary capacitor C8 and the inductance of the secondary coil of the second transformer TF2 form a second harmonic LC network to improve linearity.
  • the second transformer TF2 is electrically connected to the power stage amplifier.
  • the power amplifier assembly includes multiple power stage amplifiers, both ends of the secondary coil of the second transformer TF2 are electrically connected to the power divider PD1.
  • the power divider PD1 can adopt a zero-degree power division structure and a fully symmetrical layout to ensure the balance of amplitude and phase of the multi-channel power stage amplifier.
  • the power amplifier assembly further includes a power combiner PC1 and at least one output stage matching circuit 300.
  • the at least one output stage matching circuit 300 corresponds to at least one of the power stage amplifiers.
  • the output stage matching circuit 300 includes a third transformer TF3 and the fourth matching capacitor C10. Both ends of the primary coil of the third transformer TF3 are electrically connected to the positive output terminal and the negative output terminal of the corresponding power stage amplifier respectively.
  • the first terminal of the secondary coil of the third transformer TF3 is connected to the reference signal. terminals are electrically connected, the second terminal of the secondary coil of the third transformer TF3 is electrically connected to the input terminal of the power combiner PC1, and the fourth matching capacitor C10 is connected across both ends of the secondary coil of the third transformer TF3.
  • the middle tap of the primary coil of the third transformer TF3 is electrically connected to the high-level signal terminal VDD2.
  • the fourth matching capacitor C10 can adjust the output matching impedance so that the output impedance is at the maximum output load impedance point of the power stage amplifier.
  • the power amplifier assembly includes two power stage amplifiers, namely power stage amplifier A2 and power stage amplifier A3.
  • the power stage amplifier adopts two-way synthesis.
  • the power stage amplifier A2 and the power stage amplifier A3 are also biased in the class AB working state, which compromises the performance of efficiency, linearity and output power.
  • the power stage amplifier includes a variable capacitor composed of P-type transistors, it can compensate for AM-PM distortion and improve linearity.
  • a ground shielding layer is provided around the third transformer TF3.
  • the distance between the two third transformers TF3 is relatively close, and the electromagnetic coupling will significantly deteriorate the balance. Therefore, a ground shielding layer is added around each third transformer. Reduce electromagnetic coupling.
  • the main reason that affects the synthetic power and efficiency of the output matching network is the imbalance of amplitude and phase.
  • the amplitude imbalance is mainly due to the fact that the two third transformers are essentially differential to single-ended baluns. One end of the secondary coil is grounded, and the other end is connected to the load output by the power amplifier component.
  • Capacitors Cp1 and Cp2 will cause leakage currents Ip1 and Ip2, and the difference in load at both ends of the secondary coil may cause a difference in leakage current at both ends (Ip1 ⁇ Ip2), resulting in an unbalanced amplitude of the differential port, which is also extremely The earth deteriorates the power and efficiency of the synthesis.
  • phase imbalance it can be achieved by changing the position of the middle tap of the primary coil of the two third transformers TF3, that is, s in Figure 4; the other side Symmetrically connecting large-value decoupling capacitors to the connection line between the middle taps of the two transformers can also effectively improve the phase imbalance.
  • the amplitude and phase balance of the output matching network can be significantly improved, thereby improving the power and efficiency of the power stage amplifier synthesis and reducing losses.
  • Table 1 Shown in Table 1 is the performance comparison of different power amplifiers under the same power consumption.
  • a signal processing device includes a power amplifier component, and the power amplifier component is the power amplifier component provided in the second aspect of the present disclosure.
  • the signal processing device may be a signal transmitter or a signal receiver in a millimeter wave communication system or a radar system, or the signal processing device may be any one of LNA, VGA, DA, etc.
  • Example embodiments have been disclosed, and although specific terms are employed, they are used and should be interpreted in a general illustrative sense only and not for purpose of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may stand alone unless expressly stated otherwise. used, or may be used in combination with features, characteristics and/or elements described in connection with other embodiments. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the appended claims.

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Abstract

本公开提供一种功率放大器，包括：第一晶体管（M1）和第二晶体管（M2），所述第一晶体管（M1）的栅极与所述第二晶体管（M2）的栅极电连接，所述第一晶体管（M1）的第一极与所述功率放大器的正输出端（Out+）电连接，所述第二晶体管（M2）的第一极与所述功率放大器的负输出端（Out-）电连接，所述功率放大器还包括峰化电感（L2），所述峰化电感（L2）的第一端与所述第一晶体管（M1）的第二极电连接，所述峰化电感（L2）的第二端与所述第二晶体管（M2）的第二极电连接。本公开还提供一种功率放大器组件和一种信号处理设备。

Description

功率放大器、功率放大器组件和信号处理设备
相关申请的交叉引用
本申请要求于2022年8月29日提交的中国专利申请NO.202211040833.1的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本公开涉及通信设备领域，具体地，涉及功率放大器、功率放大器组件、和信号处理设备。
背景技术
随着第五代移动通信时代的到来，通信领域对传输速率、时延、可靠性等性能的要求不断提高，除了通信频段的提升(提升到毫米波频段)，大规模相控阵技术和大规模多输入多输出(Massive MIMO)技术、高阶调制方式如256正交振幅调制(QAM)、甚至1024QAM也得到了发展。
以上的改变对于收发机中最核心的功率放大器(Power amplifier，PA)影响巨大，由于大规模相控阵技术和Massive MIMO技术的应用，收发机可能需要集成大规模的前端阵列通道，因此PA模块可能需要集成到收发机芯片中采用硅基工艺实现，而无法像第四代移动通信技术(4G)、第三代移动通信技术(3G)一样，即PA单独采用三五族工艺实现大输出功率，但是却依然要求PA具有较大的输出功率。此外，5G通信要求高阶调制方式，这需要更大的峰均比(peak-to-average power ratio，PAPR)和更高的线性输出功率，因此对于PA的线性度也提出了更高的要求。
公开内容
作为本公开的一个方面，提供一种功率放大器，所述功率放大器包括第一晶体管和第二晶体管，所述第一晶体管的栅极与所述第二晶体管的栅极电连接，所述第一晶体管的第一极与所述功率放大器的正输出端电连接，所述第二晶体管的第一极与所述功率放大器的负输出端电连接，所述功率放大器还包括峰化电感，所述峰化电感的第一端与所述第一晶体管的第二极电连接，所述峰化电感的第二端与所述第二晶体管的第二极电连接。
作为本公开的第二个方面，提供一种功率放大器组件，所述功率放大器组件包括驱动级放大器、至少一个功率级放大器，所述驱动级放大器为本公开第一个方面的一种实施方式所述的功率放大器，所述功率级放大器为本公开第一个方面的另一种实施方式所述的功率放大器。
作为本公开的第三个方面，提供一种信号处理设备，所述信号处理设备包括功率放大器组件，所述功率放大器组件包括本公开第二个方面所述的功率放大器组件。
附图说明
图1是本公开所提供的功率放大器的一种实施方式的示意图；
图2是本公开所提供的功率放大器的一种实施方式的示意图；
图3是本公开所提供的功率放大器组件的电路示意图；以及
图4是本公开所提供的两个第三变压器的示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的功率放大器、功率放大器组件、和信号处理设备进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现，且本公开不应当被解释为限于本文阐述的实施例。提供这些实施例的目的在于使本公开更加透彻和完整，并使本领域技术人员充分理解本公开的范围。
在不冲突的情况下，本公开各实施例及实施例中的各特征可相互组合。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不限制本公开。如本文所使用的，单数形式“一个”和“该”也包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在特定特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本文所用的所有术语(包括技术术语和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
经研究发现，导致功率放大器输出功率不高的原因包括功率放大器为集成电路，不同器件的导电元件位于集成电路不同层中，会形成寄生电容，而寄生电容的存在会导致功率放大器的输出功率下降。
例如，当工作频率到达毫米波频段，考虑到工艺本身的性能，需要选择特征频率(ft)大于200吉赫兹(GHz)的工艺，通常这种工艺制程都小于65纳米(nm)，而这些先进工艺的击穿电压都较低，因此导致PA很难实现大输出功率，此外，在毫米波频段，寄生效应和电磁耦合更加严重，将会进一步恶化PA的输出功率。基于以上背景，设计一款高输出功率高线性度PA具有广泛的市场前景和应用价值。
相关PA电路通常采用单路架构。由于差分结构比单端结构有更好的线性度、输出功率以及抗干扰能力，因此目前PA大部分都采用差分结构，主要结构包括以下几种：差分共源结构、差分共源共栅结构、差分堆叠结构。差分共源结构具有较高的线性度，但是输出功率较低，此外当共源结构工作在高输出功率状态下有被击穿风险，可靠 性较低；差分共源共栅结构具有适中的线性度和输出功率，但是对于5G通信来说，单级差分共源共栅结构依然无法达到5G通信要求。为了进一步提升单级放大器的输出功率，近些年提出了差分堆叠晶体管结构，该结构输出功率可以满足5G通信要求，但是由于其堆叠晶体管越多，寄生效应越严重，并且每一个晶体管都会压缩电压裕度，因此该结构线性度较差，无法满足5G通信需求。为了折中输出功率和线性度的矛盾，有人提出了功率合成架构。理论上，每多一路合成，输出功率多(10logN)dB，N为合成路数，但是随着N增大，合成网络的损耗也越大，合成收益显著降低，因此在实际设计中，N一般不超过4。此外，由于5G通信采用大规模阵列集成，其通道尺寸较小，PA尺寸要求小型化，也限制了功率合成的规模，并且，在尺寸限制下采用功率合成架构时，往往遭受严重的电磁耦合，极大的恶化合成网络的平衡性，从而加大合成网络的损耗，降低功率合成的收益。因此在折中尺寸和功耗的前提下，高输出功率高线性度PA很难实现。
作为本公开的一个方面，提供一种功率放大器，如图1所示，所述功率放大器包括第一晶体管M1和第二晶体管M2，第一晶体管M1的栅极与第二晶体管M2的栅极电连接，第一晶体管M1的第一极与所述功率放大器的正输出端Out+电连接，第二晶体管M2的第一极与所述功率放大器的负输出端Out-电连接。所述功率放大器还包括峰化电感L2，该峰化电感L2的第一端与第一晶体管M1的第二极电连接，峰化电感L2的第二端与第二晶体管M2的第二极电连接。
本公开所提供的功率放大器中，在正输出端Out+和负输出端Out-之间跨接并联的峰化电感L2可以谐振掉寄生电容的影响，从而可以提高功率放大器的输出功率。
在一些实施方式中，第一晶体管M1和第二晶体管M2均为N型晶体管，且第一晶体管M1的尺寸与第二晶体管M2的尺寸相同。
需要指出的是，第一晶体管M1的栅极、以及第二晶体管M2的栅极需要和偏压输入端Bias电连接，以维持功率放大器的正常工作。
在本公开中，“第一晶体管M1”和“第二晶体管M2”可以为三极管，或者场效应管。本公开中所述的“栅极”是晶体管的基区引出 的电极。“栅极”、“基极”、“门控电极”等均等同于本公开中所示的“栅极”。
需要指出的是，在本公开中，上电的情况下，第一晶体管M1的第一极为第一晶体管M1的漏极，第一晶体管M1的第二极为第一晶体管M1的源极，第二晶体管M2的第一极为第二晶体管M2的漏极，第二晶体管M2的第二极为第二晶体管M2的源极。
在一些实施方式中，所述功率放大器还包括第一辅助电容C1、第二辅助电容C2和谐振电感L1，第一辅助电容C1的第一端与第一晶体管M1的第一极电连接，第一辅助电容C1的第二端与第二辅助电容C2的第一端电连接，第二辅助电容C2的第二端与第二晶体管M2的第一极电连接，谐振电感L1的第一端与第一辅助电容C1的第二端电连接，谐振电感L1的第二端与参考信号端电连接。
设置第一辅助电容C1、以及第二辅助电容C2可以调节所述功率放大器的输出阻抗，从而使得所述功率放大器具有足够的输出功率可以驱动后级的功率放大器。
第一辅助电容C1、第二辅助电容C2与谐振电感L1可以构成LC网络，该LC网络谐振在二次谐波处，结合输入级匹配电路(该电路将在下文中进行介绍)的LC网络，可以进一步提高功率放大器的线性度。在本公开中，与谐振电感L1的第二端电连接的参考信号端可以是虚地节点，通过引入谐振电感L1可以将第一辅助电容C1和第二辅助电容C2接地，从而避免恶化功率放大器的其他功能。
在本公开中，第一辅助电容C1的尺寸可以与第二辅助电容C2的尺寸相同。
在本公开中，对功率放大器的其他结构不做特殊的限定。例如，所述功率放大器可以是具有共源共栅结构的功率放大器。也就是说，所述功率放大器还包括第三晶体管M3和第四晶体管M4，第三晶体管M3的第一极与第四晶体管M4的第一极电连接，且与参考信号端电连接，第三晶体管M3的栅极与输入信号正输入端In+电连接，第四晶体管M4的栅极与输入信号负输入端In-电连接，第三晶体管M3的第二极与第一晶体管M1的第二极电连接，第四晶体管M4的第二极与第 二晶体管M2的第二极电连接。
在本公开中，第三晶体管M3和第四晶体管M4均为N型晶体管，且第三晶体管M3的尺寸可以与第四晶体管M4的尺寸相同。
需要指出的是，在本公开中，上电的情况下，第三晶体管M3的第二极为第三晶体管的漏极，第三晶体管M3的第一极为第三晶体管的源极，第四晶体管M4的第二极为第四晶体管的漏极，第四晶体管M4的第一极为第四晶体管的源极。
在一些实施方式中，所述功率放大器还可以包括第一中和电容C3和第二中和电容C4。第一中和电容C3的一端与第三晶体管M3的第二极电连接，第一中和电容C3的另一端与输入信号负输入端In-电连接，第二中和电容C4的一端与第四晶体管M4的第二极电连接，第二中和电容C4的另一端与输入信号正输入端In+电连接。设置第一中和电容C3和第二中和电容C4可以中和第三晶体管M3、以及第四晶体管M4的寄生电容，从而提高所述功率放大器的稳定性和增益。
在一些实施方式中，第一中和电容C3和第二中和电容C4的尺寸相同。
在一些实施方式中，如图2所示，所述功率放大器还包括可变电容器，所述可变电容器包括第一P型晶体管M5和第二P型晶体管M6，第一P型晶体管M5的第一极与第一P型晶体管M5的第二极电连接，第二P型晶体管M6的第一极与第二P型晶体管M6的第二极电连接，且第一P型晶体管M5的第一极与第二P型晶体管M6的第一极电连接，第一P型晶体管M5的栅极与输入信号正输入端In+电连接，第二P型晶体管M6的栅极与输入信号负输入端In-电连接。
如上文中所述，功率放大器中的第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4均为N型晶体管，设置P型晶体管构成的可变电容后，该可变电容随功率变化的特性与N型晶体管形成的寄生电容随功率变化的特性相反，从而可以补偿功率放大器的调幅-调相(AM-PM)特性，提升功率放大器的线性度。
在一些实施方式中，第一P型晶体管M5和第二P型晶体管M6尺寸相同。
作为本公开的第二个方面，提供一种功率放大器组件，如图3所示，所述功率放大器组件包括驱动级放大器A1、至少一个功率级放大器，驱动级放大器A1为本公开第一个方面的一种实施方式所提供的功率放大器，所述功率级放大器为本公开第一个方面的另一种实施方式所提供的功率放大器。
在一些实施方式中，驱动级放大器A1可以是图1中所示的功率放大器，如上文中所述，在正输出端Out+和负输出端Out-之间跨接并联的峰化电感L2可以谐振掉寄生电容的影响，从而可以提高功率放大器的输出功率。
设置第一辅助电容C1、以及第二辅助电容C2可以调节所述功率放大器的输出阻抗，从而使得所述功率放大器具有足够的输出功率可以驱动后级的功率放大器(即，功率级放大器)。
所述功率级放大器可以是图2中所示的功率放大器。除了具有图1中所示的功率放大器的优点之外，所述功率级放大器还具有更好的线性度。
在本公开中，对功率级放大器的数量不做特殊的限定。在一些实施方式中，所述放大器组件可以包括两个功率级放大器，分别为功率级放大器A2和功率级放大器A3。两路功率级放大器合路，且两路功率级放大器的结构相同。
如图3所示，所述功率放大器组件还包括输入级匹配电路100，该输入级匹配电路100包括第一变压器TF1、第一匹配电容C5、第二匹配电容C7和第三辅助电容C6，第一匹配电容C5跨接在第一变压器TF1的初级线圈的两端，第二匹配电容C7跨接在第一变压器TF1的次级线圈的两端，且第三辅助电容C6的第一端与第一变压器TF1次级线圈的抽头电连接，第三辅助电容C6的第二端与参考信号端电连接，第一变压器TF1的次级线圈的两端分别与驱动级放大器A1的正输入端、以及驱动级放大器A1的负输入端电连接。
在本公开中，第一匹配电容C5、第二匹配电容C7可以调谐阻抗，实现驱动级放大器A1的阻抗匹配，第三辅助电容C6与第一变压器TF1的次级线圈的电感形成二次谐波LC网络，可以进一步提升功率 放大器组件的线性度。
由于第一变压器TF1的中间抽头对于需要的信号来说是虚地点，因此，增设第三辅助电容C6不会影响功率放大器组件的其他性能。在本实施方式中，第一变压器TF1次级线圈的中间抽头与偏压信号端Bias1电连接。第一变压器TF1的输入端为所述功率放大器组件的输入端PA_IN。
在一些实施方式中，所述功率放大器组件还包括级间匹配电路200，该级间匹配电路200包括第二变压器TF2、第三匹配电容C9和第四辅助电容C8，第二变压器TF2的初级线圈的两端分别与驱动级放大器A1的正输出端和负输出端电连接，第三匹配电容C9的两端跨接在第二变压器TF2的次级线圈的两端，第四辅助电容C8的第一端与第二变压器TF2的次级线圈的中间抽头电连接，第四辅助电容C8的第二端与参考信号端电连接，第二变压器TF2的次级线圈的两端分别与所述功率级放大器的正输入端以及负输入端电连接。
第二变压器TF2的初级线圈的中间抽头与高电平信号端VDD1电连接。第二变压器TF2的次级线圈的中间抽头通过第四辅助电容C8接地，同时第二变压器TF2的次级线圈中间抽头与偏置电压信号端Bias3电连接。第三匹配电容C9的两端跨接在第二变压器TF2的次级线圈的两端，可以实现阻抗调节，实现驱动级放大器A1与功率级功率放大器之间的阻抗匹配，并实现驱动级放大器最大功率传输。第四辅助电容C8与第二变压器TF2的次级线圈的电感构成二次谐波LC网络，改善线性度。
在本公开中，对第二变压器TF2如何与功率级放大器电连接不做特殊的限定。当所述功率放大器组件包括多个功率级放大器时，第二变压器TF2的次级线圈的两端与功分器PD1电连接。在一些实施方式中，该功分器PD1可以采用零度功分结构，采用全对称布局，保证多路功率级放大器的幅度以及相位的平衡。
在本公开中，所述功率放大器组件还包括功合器PC1和至少一个输出级匹配电路300，至少一个输出级匹配电路300与至少一个所述功率级放大器一一对应。输出级匹配电路300包括第三变压器TF3 和第四匹配电容C10，第三变压器TF3的初级线圈的两端分别与相应的功率级放大器的正输出端以及负输出端电连接，第三变压器TF3的次级线圈的第一端与参考信号端电连接，第三变压器TF3的次级线圈的第二端与功合器PC1的输入端电连接，第四匹配电容C10跨接在第三变压器TF3的次级线圈的两端。
第三变压器TF3的初级线圈的中间抽头与高电平信号端VDD2电连接。第四匹配电容C10可以调节输出匹配的阻抗，使输出阻抗在功率级放大器的最大输出负载阻抗点上。
在图3中所示的实施方式中，功率放大器组件包括两路功率级放大器，分别为功率级放大器A2和功率级放大器A3。也就是说，功率级放大器采用两路合成，功率级放大器A2和功率级放大器A3同样偏置在AB类工作状态，折中了效率、线性度和输出功率的性能。由于功率级放大器包括P型晶体管构成的可变电容，可以补偿AM-PM失真，提升了线性度。
在一些实施方式中，如图4所示，第三变压器TF3的外围设置有地屏蔽层。
由于在有限的尺寸内，如图4所示，两路第三变压器TF3之间距离较近，其电磁耦合将会显著恶化平衡性，因此在每一个第三变压器周围都加了地屏蔽层以降低电磁耦合。另外，影响输出匹配网络合成功率和效率的主要原因是幅度和相位的不平衡性。幅度不平衡主要由于两路第三变压器本质上都是差分转单端的巴伦，其次级线圈一端接地，另一端接所述功率放大器组件输出的负载，而由于变压器初级线圈和次级线圈的寄生电容Cp1和Cp2将会导致泄露电流Ip1和Ip2，以及次级线圈两端负载的差异，可能会导致两端泄露电流的差异(Ip1≠Ip2)，从而导致了差分端口的幅度不平衡，也极大地恶化了合成的功率和效率。为了改善这一问题，本公开中通过调节初级线圈和次级线圈的交叠的偏移位置，即图4中的(d±Δ)，来改善初级线圈和次级线圈两端的寄生电容，从而使泄露电流一致(Ip1＝Ip2)，最后保证了幅度的平衡性。针对相位不平衡，可以通过改变两个第三变压器TF3的初级线圈中间抽头的位置，即图4中的s来实现；另一方 面在两个变压器中间抽头的连线上对称地接上大容值的去耦电容也可以有效的改善相位不平衡。基于以上改善方法，可以显著提高输出匹配网络的幅度和相位平衡性，从而提高功率级放大器合成的功率和效率，降低损耗。
表1中所示的是相同功耗下，不同功率放大器的性能对比。
表1
通过表1可以看出，本公开所提供的功率放大器组件具有更好的性能。
作为本公开的第三个方面，提供一种信号处理设备，所述信号处理设备包括功率放大器组件，所述功率放大器组件为本公开第二个方面所提供的功率放大器组件。
所述信号处理设备可以是毫米波通信系统或雷达系统的中的信号发射器、信号接收器，或者，所述信号处理设备也可以是LNA、VGA、DA等中的任意一者。
本公开已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则与特定实施例相结合描述的特征、特性和/或元素可单独 使用，或可与结合其它实施例描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种功率放大器，包括：第一晶体管和第二晶体管，所述第一晶体管的栅极与所述第二晶体管的栅极电连接，所述第一晶体管的第一极与所述功率放大器的正输出端电连接，所述第二晶体管的第一极与所述功率放大器的负输出端电连接，其中，所述功率放大器还包括峰化电感，所述峰化电感的第一端与所述第一晶体管的第二极电连接，所述峰化电感的第二端与所述第二晶体管的第二极电连接。
  2. 根据权利要求1所述的功率放大器，还包括：第一辅助电容、第二辅助电容和谐振电感，所述第一辅助电容的第一端与所述第一晶体管的第一极电连接，所述第一辅助电容的第二端与所述第二辅助电容的第一端电连接，所述第二辅助电容的第二端与所述第二晶体管的第一极电连接，所述谐振电感的第一端与所述第一辅助电容的第二端电连接，所述谐振电感的第二端与参考信号端电连接。
  3. 根据权利要求1或2所述的功率放大器，还包括：第三晶体管和第四晶体管，所述第三晶体管的第一极与所述第四晶体管的第一极电连接，且与参考信号端电连接，所述第三晶体管的栅极与输入信号正输入端电连接，所述第四晶体管的栅极与输入信号负输入端电连接，所述第三晶体管的第二极与所述第一晶体管的第二极电连接，所述第四晶体管的第二极与所述第二晶体管的第二极电连接。
  4. 根据权利要求3所述的功率放大器，还包括：可变电容器，所述可变电容器包括第一P型晶体管和第二P型晶体管，所述第一P型晶体管的第一极与所述第一P型晶体管的第二极电连接，所述第二P型晶体管的第一极与所述第二P型晶体管的第二极电连接，且所述第一P型晶体管的第一极与所述第二P型晶体管的第一极电连接，所述第一P型晶体管的栅极与所述输入信号正输入端电连接，所述第二P型晶体管的栅极与所述输入信号负输入端电连接。
  5. 一种功率放大器组件，包括：驱动级放大器、至少一个功率级放大器，其中，所述驱动级放大器为权利要求1至3中任意一项所述的功率放大器，所述功率级放大器为权利要求4所述的功率放大器。
  6. 根据权利要求5所述的功率放大器组件，还包括：输入级匹配电路，所述输入级匹配电路包括第一变压器、第一匹配电容、第二匹配电容和第三辅助电容，第一匹配电容跨接在所述第一变压器的初级线圈的两端，所述第二匹配电容跨接在所述第一变压器的次级线圈的两端，且所述第三辅助电容的第一端与所述次级线圈的抽头电连接，所述第三辅助电容的第二端与参考信号端电连接，第一变压器的次级线圈的两端分别与所述驱动级放大器的正输入端以及所述驱动级放大器的负输入端电连接。
  7. 根据权利要求5所述的功率放大器组件，还包括：级间匹配电路，所述级间匹配电路包括第二变压器、第三匹配电容和第四辅助电容，所述第二变压器的初级线圈的两端分别与所述驱动级放大器的正输出端和负输出端电连接，所述第三匹配电容的两端跨接在所述第二变压器的次级线圈的两端，所述第四辅助电容的第一端与所述第二变压器的次级线圈的中间抽头电连接，所述第四辅助电容的第二端与参考信号端电连接，所述第二变压器的次级线圈的两端分别与所述功率级放大器的正输入端以及负输入端电连接。
  8. 根据权利要求5至7中任意一项所述的功率放大器组件，还包括：功合器和至少一个输出级匹配电路，至少一个所述输出级匹配电路与至少一个所述功率级放大器一一对应，所述输出级匹配电路包括第三变压器和第四匹配电容，所述第三变压器的初级线圈的两端分别与相应的功率级放大器的正输出端以及负输出端电连接，所述第三变压器的次级线圈的第一端与参考信号端电连接，所述第三变压器的次级线圈的第二端与所述功合器的输入端电连接，所述第四匹配电容 跨接在所述第三变压器的次级线圈的两端。
  9. 根据权利要求8所述的功率放大器组件，其中，所述第三变压器的外围设置有地屏蔽层。
  10. 一种信号处理设备，包括：权利要求5至9中任意一项所述的功率放大器组件。
PCT/CN2023/102633 2022-08-29 2023-06-27 功率放大器、功率放大器组件和信号处理设备 WO2024045820A1 (zh)

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CN114844473A (zh) * 2022-04-11 2022-08-02 电子科技大学 一种采用补偿电容技术的双控制位型可变增益放大器

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