WO2023045543A1 - 基于变压器匹配的三级功率放大器及射频前端架构 - Google Patents

基于变压器匹配的三级功率放大器及射频前端架构 Download PDF

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WO2023045543A1
WO2023045543A1 PCT/CN2022/108109 CN2022108109W WO2023045543A1 WO 2023045543 A1 WO2023045543 A1 WO 2023045543A1 CN 2022108109 W CN2022108109 W CN 2022108109W WO 2023045543 A1 WO2023045543 A1 WO 2023045543A1
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stage
transformer
capacitor
input
matching
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PCT/CN2022/108109
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English (en)
French (fr)
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谢志远
赵宇霆
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2023045543A1 publication Critical patent/WO2023045543A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only

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  • the utility model relates to the technical field of power amplifiers, in particular to a three-stage power amplifier based on transformer matching and a radio frequency front-end architecture.
  • the key module is the RF Power Amplifier (RF Power Amplifier) located at the final stage of the transmitter, which is used to amplify the output signal and send out the amplified signal by the antenna.
  • the RF power amplifier directly affects and determines various performance indicators such as output power, efficiency, gain, linearity, operating bandwidth, and reflection coefficient of the transmitter system, thereby affecting and determining various performance indicators of the entire 5G wireless communication system.
  • the output power of the RF power amplifier in 5G mobile communication is required to be greater, so more transistors are required to design and realize high power, which increases the difficulty of matching; and the capacitance, inductance, and resistance at high frequencies will generate large parasitic Effect, resulting in a certain gap between the actual value of the device and the ideal value; it can be seen that impedance matching at high frequencies will be more difficult.
  • the embodiment of the utility model provides a three-stage power amplifier and a radio frequency front-end architecture based on transformer matching, which can reduce matching difficulty and have higher gain and output power.
  • the utility model provides a three-stage power amplifier based on transformer matching on the one hand, including an input matching network, a first-stage single-channel amplifier circuit, a first-stage inter-stage matching network, and a second-stage dual-channel amplifier circuit. , a second-stage inter-stage matching network, a third-stage dual-channel amplifier circuit, and an output matching network;
  • the first interstage matching network includes a first transformer T1
  • the second interstage matching network includes two ⁇ -type matching units and two choke inductors L
  • the output matching network includes a second transformer T2;
  • the input end and output end of the input matching network are respectively connected to the single-ended radio frequency input signal RFin and the input end of the first-stage single-channel amplifier circuit, and the two input ends of the first transformer T1 are respectively connected to the first-stage single-channel amplifier circuit.
  • the output terminal of the two-way amplifier circuit and the supply voltage Vcc1, the two output terminals of the first transformer T1 are respectively connected to the two input terminals of the second-stage dual-channel amplifier circuit, and the two input terminals of the second-stage dual-channel amplifier circuit
  • the output ends are respectively connected to the input ends of the two T-type matching units, the output ends of the two T-type matching units are respectively connected to the two input ends of the third-stage dual amplifying circuit, and the two input ends of the two T-type matching units are connected respectively.
  • One end of the choke inductance L is respectively connected to the two output ends of the second stage dual amplifier circuit, the other ends of the two choke inductors L are connected to the power supply voltage Vcc2, and the third stage dual amplifier circuit
  • the two output terminals of the second transformer T2 are respectively connected to the two input terminals of the second transformer T2, one output terminal of the second transformer T2 is used to output the radio frequency signal RFout, and the other output terminal of the second transformer T2 is grounded.
  • the first-stage single-channel amplifier circuit includes a first transistor Q1
  • the second-stage dual-channel amplifier circuit includes two second transistors Q2
  • the third-stage dual-channel amplifier circuit includes two second transistors Q2.
  • the base and the collector of the first transistor Q1 are respectively the input terminal and the output terminal of the first stage single amplifier circuit, the emitter of the first transistor Q1 is grounded; the two second transistors Q2 The bases are respectively the two input terminals of the second stage dual amplifier circuit, the collectors of the two second transistors Q2 are respectively the two output terminals of the second stage dual amplifier circuit, and the two The emitters of the second transistor Q2 are grounded; the bases of the two third transistors Q3 are respectively the two input terminals of the third-stage dual amplifier circuit, and the collectors of the two third transistors Q3 are respectively The emitters of the two third transistors Q3 are grounded.
  • the negative feedback network also includes a negative feedback network connected between the collector and the base of the first transistor Q1, the negative feedback network includes a first resistor R1 and a first capacitor C1 connected in series;
  • the first-stage single-channel amplifier circuit further includes a second resistor R2, the second resistor R2 is connected in series between the input matching network and the base of the first transistor Q1, and connected in parallel with the negative feedback network .
  • the first inter-stage matching network further includes a second capacitor C2, a third capacitor C3, two fourth capacitors C4, and a first inductor L1;
  • One end of the second capacitor C2 is connected to the input end of the first transformer T1 connected to the collector of the first transistor Q1, the other end of the second capacitor C2 is grounded, and one end of the third capacitor C3
  • the first inductor L1 is connected in series with the input end of the first transformer T1 connected to the power supply voltage Vcc1 and the power supply voltage Vcc1.
  • the T-shaped matching unit includes a fifth capacitor C5, a sixth capacitor C6, and a second inductor L2;
  • One end of the fifth capacitor C5 is the input end of the T-shaped matching unit, and the other end of the fifth capacitor C5 is connected to one end of the second inductor L2 and one end of the sixth capacitor C6.
  • the other end of the sixth capacitor C6 is the output end of the T-shaped matching unit, and the other end of the second inductor L2 is grounded.
  • the output matching network further includes a seventh capacitor C7, a third inductor L3, and two eighth capacitors C8;
  • One end of the seventh capacitor C7 is connected to the other output end of the second transformer T2, the other end of the seventh capacitor C7 is grounded, and the other output end of the second transformer T2 passes through the The third inductor L3 is grounded, one end of the two eighth capacitors C8 is respectively connected to the two input ends of the second transformer T2, and the other end of the two eighth capacitors C8 is grounded.
  • the input matching network includes a ninth capacitor C9, a tenth capacitor C10, a fourth inductor L4, and a fifth inductor L5;
  • One end of the ninth capacitor C9 is connected to one end of the fourth inductor L4, and the connection node is used to input the single-ended radio frequency input signal RFin, the other end of the fourth inductor L4 is grounded, and the ninth capacitor C9 The other end is connected to one end of the tenth capacitor C10, the other end of the tenth capacitor C10 is connected to the input end of the first-stage single-channel amplifier circuit, and one end of the fifth inductor L5 is connected to the first Between the ninth capacitor C9 and the tenth capacitor C10, the other end of the fifth inductor L5 is grounded.
  • a third resistor R3 is connected in series between the output terminal of the T-shaped matching unit and the input terminal of the third-stage dual amplifier circuit.
  • both the first transformer T1 and the second transformer T2 are symmetrical interwound transformers.
  • the turns ratio of the symmetrical interwound transformer is between 2:1 and 1:1.
  • Another aspect of the present invention also provides a radio frequency front-end architecture, including the three-stage power amplifier based on transformer matching described in any one of the above.
  • the three-stage power amplifier based on transformer matching of the utility model includes an input matching network, a first-stage single-channel amplifier circuit, a first-stage inter-stage matching network, a second-stage dual-channel amplifier circuit, and a second-stage inter-stage matching network , a third-stage dual amplifier circuit and an output matching network;
  • the first inter-stage matching network includes a first transformer T1
  • the second inter-stage matching network includes two ⁇ -type matching units and two choke inductors L
  • the output matching network includes a second transformer T2; the input end and output end of the input matching network are respectively connected to the single-ended radio frequency input signal RFin and the input end of the first-stage single-channel amplifier circuit, and the two ends of the first transformer T1
  • the two input terminals are respectively connected to the output terminal of the first-stage single-channel amplifier circuit and the supply voltage Vcc1, and the two output terminals of the first transformer T1 are respectively connected to the two input terminals of the second-stage dual-channel amplifier circuit,
  • the two input ends of the circuit are connected, one end of the two choke inductors L is respectively connected to the two output ends of the second-stage dual amplifier circuit, and the other end of the two choke inductors L is connected to the power supply voltage Vcc2, the two output terminals of the third-stage dual amplifying circuit are respectively connected to the two input terminals of the second transformer T2, one output terminal of the second transformer T2 is used to output the radio frequency signal RFout, and the other The output terminal is grounded, so that the inter-stage matching network and the output matching network are realized by transformers, which can effectively reduce the difficulty of inter-stage matching, effectively optimize the input return loss and gain, and increase the output power.
  • Fig. 1 is the circuit diagram of the three-stage power amplifier based on transformer matching that the utility model embodiment provides;
  • Fig. 2 is a schematic diagram of a symmetrical interwinding transformer provided by an embodiment of the present invention
  • Fig. 3 is the layout of the symmetrical interwinding transformer provided by the embodiment of the present invention.
  • the differential power amplifier 100 of the embodiment of the present utility model comprise input matching network 11, the first-stage single-channel amplifier circuit 12, the first-stage inter-stage matching network 13, the second-stage dual-channel amplification circuit connected in series successively Circuit 14 , second interstage matching network 15 , third stage dual amplifier circuit 16 and output matching network 17 .
  • the first interstage matching network 13 includes a first transformer T1
  • the second interstage matching network 15 includes two ⁇ -type matching units and two choke inductors L
  • the output matching network 17 includes a second transformer T2 .
  • the input end and the output end of the input matching network 11 are respectively connected to the single-ended radio frequency input signal RFin and the input end of the first-stage single-channel amplifier circuit 12, and the two input ends of the first transformer T1 are respectively connected to the The output terminal of the first-stage single-channel amplifying circuit 12 and the supply voltage Vcc1, the two output terminals of the first transformer T1 are respectively connected to the two input terminals of the second-stage dual-channel amplifying circuit 14, the second-stage Two output ends of the dual-way amplifier circuit 14 are respectively connected with the input ends of the two T-type matching units, and the output ends of the two T-type matching units are respectively connected to the two ends of the third-stage dual-way amplifier circuit 16.
  • the two output terminals of the third-stage dual amplifier circuit 16 are respectively connected to the two input terminals of the second transformer T2, one output terminal of the second transformer T2 is used to output the radio frequency signal RFout, and the other output end grounded.
  • the power amplifier 100 is implemented by using a three-stage amplifying circuit, thereby obtaining high gain, and by using a transformer to realize the inter-stage matching network and the output matching network, the difficulty of inter-stage matching can be effectively reduced, and the Effectively optimize the input return loss and gain, which is beneficial to improve the output power.
  • the first-stage single-channel amplifier circuit 12, the second-stage dual-channel amplifier circuit 14, and the third-stage dual-channel amplifier circuit 16 can be implemented using HBT transistors.
  • HBT transistors HBT transistors
  • the amplification circuits of various levels can also be realized by using COMS tubes, HEMT tubes or pHEMT tubes.
  • the first-stage single-channel amplifier circuit 12 includes a first transistor Q1
  • the second-stage dual-channel amplifier circuit 14 includes two second transistors Q2
  • the third-stage dual-channel amplifier circuit 16 includes two third transistors Q3.
  • the base and the collector of the first transistor Q1 are respectively the input terminal and the output terminal of the first-stage single-channel amplifier circuit, and the emitter of the first transistor Q1 is grounded;
  • the two second transistors The bases of Q2 are respectively the two input terminals of the second-stage dual-channel amplifier circuit, and the collectors of the two second transistors Q2 are respectively the two output terminals of the second-stage dual-channel amplifier circuit, so The emitters of the two second transistors Q2 are grounded;
  • the bases of the two third transistors Q3 are respectively the two input terminals of the third-stage dual amplifier circuit, and the set of the two third transistors Q3
  • the electrodes are respectively the two output terminals of the third-stage dual amplifier circuit, and the emitters of the two third transistors Q3 are grounded.
  • the three-stage power amplifier 100 also includes a negative feedback network 18 connected between the collector and the base of the first transistor Q1, and the negative feedback network 18 includes a first resistor R1 and a first resistor R1 connected in series. Capacitor C1.
  • the first-stage single-channel amplifier circuit 12 also includes a second resistor R2, the second resistor R2 is connected in series between the input matching network 11 and the base of the first transistor Q1, and connected to the negative feedback
  • the networks 18 are connected in parallel.
  • the base of the first transistor Q1 is connected in series with the second resistor R2 with a smaller resistance, and a negative feedback network 18 is added between the collector and the base of the first transistor Q1, wherein the first resistor R1
  • the function of can adjust the feedback depth, thereby increasing the stability while reducing the gain and output power of the first-stage single-channel amplifier circuit 12 .
  • the frequency band where the feedback is located can be adjusted.
  • the first-stage single-channel amplifying circuit 12 adopts the first transistor Q1 to realize one-channel amplifying circuit.
  • the number of the first transistor Q1 is not limited to one, and can be
  • the first-stage single-channel amplifier circuit 12 is realized by using multiple first transistors Q1 connected in parallel.
  • the parallel connection of multiple first transistors Q1 is achieved by connecting the bases of multiple first transistors Q1 in series with a second resistor R2 and then connecting them in parallel.
  • the collectors of the first transistor Q1 are connected in parallel as the output end of the first-stage single-channel amplifier circuit 12, and the emitters of the first transistor Q1 are both grounded.
  • the second-stage dual-channel amplifier circuit 14 uses two second transistors Q2 to implement a two-channel amplifier circuit.
  • each of the second-stage dual-channel amplifier circuits 14 One amplifying circuit can also be implemented by multiple parallel second transistors Q2, the bases of multiple parallel second transistors Q2 in each amplifying circuit are connected in parallel, the collectors are connected in parallel, and the emitters are all grounded.
  • the third-stage dual-channel amplifier circuit 16 uses two third transistors Q3 to implement two-channel amplifier circuits respectively.
  • each amplifier circuit of the third-stage dual-channel amplifier circuit 16 can use multiple Three transistors Q3 are implemented, the bases of multiple parallel third transistors Q3 in each channel are connected in parallel, the collectors are connected in parallel, and the emitters are grounded.
  • the first inter-stage matching network 13 further includes a second capacitor C2, a third capacitor C3, two fourth capacitors C4 and a first inductor L1.
  • One end of the second capacitor C2 is connected to the input end of the first transformer T1 connected to the collector of the first transistor Q1, the other end of the second capacitor C2 is grounded, and one end of the third capacitor C3
  • the first inductor L1 is connected in series with the input end of the first transformer T1 connected to the power supply voltage Vcc1 and the power supply voltage Vcc1.
  • the two fourth capacitors C4 have the same size and are DC blocking capacitors, which can adjust the gain trend of the second-stage dual-channel amplifier circuit.
  • the second capacitor C2, the third capacitor C3 and the first inductor L1 can increase the matching bandwidth of the transformer T1, and Reduce the insertion loss of the matching network of transformer T1.
  • the T-shaped matching unit includes a fifth capacitor C5, a sixth capacitor C6 and a second inductor L2.
  • One end of the fifth capacitor C5 is the input end of the T-shaped matching unit, and the other end of the fifth capacitor C5 is connected to one end of the second inductor L2 and one end of the sixth capacitor C6.
  • the other end of the sixth capacitor C6 is the output end of the T-shaped matching unit, and the other end of the second inductor L2 is grounded.
  • the output matching network 17 further includes a seventh capacitor C7, a third inductor L3 and two eighth capacitors C8.
  • One end of the seventh capacitor C7 is connected to the other output end of the second transformer T2, the other end of the seventh capacitor C7 is grounded, and the other output end of the second transformer T2 passes through the
  • the third inductor L3 is grounded, one end of the two eighth capacitors C8 is respectively connected to the two input ends of the second transformer T2, and the other end of the two eighth capacitors C8 is grounded.
  • the dual-channel differential signal can be converted into a single-ended signal output. Specifically, the dual-channel differential signal with a phase difference of 180° will generate a phase difference of 180° again after passing through the second transformer T2.
  • the seventh capacitor C7, the eighth capacitor C8, the third inductor L3, and the transformer T2 together form a transformer matching network. Through the effects of the seventh capacitor C7, the eighth capacitor C8, and the third inductor L3, the matching bandwidth of the transformer T2 can be increased and the transformer T2 can be reduced. Transformer T2 matches the insertion loss of the network.
  • the input matching network 11 is realized by two-stage LC matching, that is, a high-pass matching structure formed by connecting the inductor in parallel to the ground and connecting the capacitor in series, which is beneficial to increase stability while The gain and output power of the first-stage single-channel amplifier circuit 12 are reduced.
  • the input matching network 11 includes the input matching network including a ninth capacitor C9, a tenth capacitor C10, a fourth inductor L4, and a fifth inductor L5.
  • One end of the ninth capacitor C9 is connected to one end of the fourth inductor L4, and the connection node is used to input the single-ended radio frequency input signal RFin, the other end of the fourth inductor L4 is grounded, and the ninth capacitor C9 The other end is connected to one end of the tenth capacitor C10, and the other end of the tenth capacitor C10 is connected to the input end of the first-stage single-channel amplifier circuit 12 (that is, the base of the first transistor Q1), wherein , the second resistor R2 is connected in series between the tenth capacitor C10 and the base of the first transistor Q1.
  • One end of the fifth inductor L5 is connected between the ninth capacitor C9 and the tenth capacitor C10, and the other end of the fifth inductor L5 is grounded.
  • the third-stage dual amplifying circuit 16 also includes a third resistor R3, that is, a third resistor R3 is connected in series between the output terminal of the T-shaped matching unit and the input terminal of the third-stage dual amplifying circuit 16. Resistor R3.
  • the power amplifier 100 further includes a base bias circuit connected to the bases of each of the transistors in the amplifier circuits of various stages in a one-to-one correspondence, for providing bias voltages to the bases of the transistors.
  • the power supply voltages Vcc1 and Vcc2 are used to supply power to corresponding devices, and their magnitudes can be the same or different, and can be selected according to actual needs.
  • the first transformer T1 and the second transformer T2 are mutually winding symmetrical transformers, and the grounding point is on the symmetrical axis, so that the phase can be guaranteed when the output signal phase is converted. It is accurate enough and has great advantages in transmitting differential signals.
  • the symmetrical interwound transformer has a large mutual inductance, so its coupling coefficient K value is 0.7 to 0.9. The larger the K value, the closer the transformer is to the ideal state, and its bandwidth is wider and the insertion loss is smaller.
  • the ports of the primary coil and the secondary coil of the transformer are at both ends of the transformer, so it is very suitable for the cascade connection of the front and rear circuits.
  • the E and F terminals of the transformer are respectively connected to the collector of the first transistor Q1 and the DC power supply terminal Vcc1
  • the E and F terminals and their connected coils are the primary coils
  • the M and N terminals are connected to the second
  • the two input ends of the first-stage dual-channel amplifier circuit, M, N and their connecting coils are secondary coils, and the turns ratio of the primary and secondary coils is between 2:1 and 1:1.
  • the three-stage power amplifier based on transformer matching of the utility model is beneficial to reduce the difficulty of matching, and can make the insertion return loss of inter-stage matching and overall matching better, and has higher gain, output power and efficiency.
  • Embodiments of the present invention also provide a radio frequency front-end architecture, including the three-stage power amplifier based on transformer matching described in any of the above embodiments.

Abstract

一种基于变压器匹配的三级功率放大器，包括输入匹配网络（11）、第一级单路放大电路（12）、第一级间匹配网络（13）、第二级双路放大电路（14）、第二级间匹配网络（15）、第三级双路放大电路（16）以及输出匹配网络（17）；所述第一级间匹配网络（13）包括第一变压器T1，所述第二级间匹配网络（15）包括两个π型匹配单元和两个扼流电感L，所述输出匹配网络（17）包括第二变压器T2；所述第一变压器T1用于将经过第一级单路放大电路（12）放大后的信号变为差分信号，该差分信号依次经过第二级、第三级双路放大电路（14、16）的放大后，经由所述第二变压器T2合成为一路信号输出，由此通过将级间匹配网络和输出匹配网络采用变压器来实现，可以有效降低级间匹配难度，且可以提高输出功率。

Description

基于变压器匹配的三级功率放大器及射频前端架构 技术领域
本实用新型涉及功率放大器技术领域，尤其涉及一种基于变压器匹配的三级功率放大器及射频前端架构。
背景技术
在5G无线通信系统中，关键模块是位于发射机末级的射频功率放大器(RF Power Amplifier)，其作用为将输出信号进行放大，由天线将被放大的信号发出。射频功率放大器直接影响和决定发射机系统的输出功率、效率、增益、线性度、工作带宽、反射系数等各项性能指标，从而影响和决定整个5G无线通信系统的各项性能指标。5G移动通信中的射频功率放大器的输出功率要求更大，因此设计和实现高功率需要更多的晶体管，增加了匹配的难度；并且在高频下的电容、电感、电阻将产生较大的寄生效应，导致器件的实际值与理想值有一定差距；由此可知高频下的阻抗匹配将更加困难。
实用新型内容
本实用新型实施例提供一种基于变压器匹配的三级功率放大器及射频前端架构，能够降低匹配难度，具有较高的增益和输出功率。
为了解决上述技术问题，本实用新型一方面提供一种基于变压器匹配的三级功率放大器，包括输入匹配网络、第一级单路放大电路、第一级间匹配网络、第二级双路放大电路、第二级间匹配网络、第三级双路放大电路以及输出匹配网络；
所述第一级间匹配网络包括第一变压器T1，所述第二级间匹配网络包括两个π型匹配单元和两个扼流电感L，所述输出匹配网络包括第二变压器T2；
所述输入匹配网络的输入端和输出端分别连接单端射频输入信号RFin和第一级单路放大电路的输入端，所述第一变压器T1的两个输入端分别连接所述第一级单路放大电路的输出端和供电电压Vcc1，所述第一变压器T1的两个输出端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别与所述两个T型匹配单元的输入端连接，所述两个T型 匹配单元的输出端分别与所述第三级双路放大电路的两个输入端连接，两个所述扼流电感L的一端分别与所述第二级双路放大电路的两个输出端连接，两个所述扼流电感L的另一端连接供电电压Vcc2，所述第三级双路放大电路的两个输出端分别与所述第二变压器T2的两个输入端连接，所述第二变压器T2的一个输出端用于输出射频信号RFout，另一个输出端接地。
更进一步地，所述第一级单路放大电路包括一个第一晶体管Q1，所述第二级双路放大电路包括两个第二晶体管Q2，所述第三级双路放大电路包括两个第三晶体管Q3；
所述第一晶体管Q1的基极和集电极分别为所述第一级单路放大电路的输入端和输出端，所述第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路的两个输出端，所述两个第二晶体管Q2的发射极接地；所述两个第三晶体管Q3的基极分别为所述第三级双路放大电路的两个输入端，所述两个第三晶体管Q3的集电极分别为所述第三级双路放大电路的两个输出端，所述两个第三晶体管Q3的发射极接地。
更进一步地，还包括连接在所述第一晶体管Q1的集电极和基极之间的负反馈网络，所述负反馈网络包括串联的第一电阻R1和第一电容C1；
所述第一级单路放大电路还包括第二电阻R2，所述第二电阻R2串联在所述输入匹配网络和所述第一晶体管Q1的基极之间，并与所述负反馈网络并联。
更进一步地，所述第一级间匹配网络还包括第二电容C2、第三电容C3、两个第四电容C4以及第一电感L1；
所述第二电容C2的一端与所述第一变压器T1中连接所述第一晶体管Q1的集电极的输入端连接，所述第二电容C2的另一端接地，所述第三电容C3的一端与所述第一变压器T1中连接供电电压Vcc1的输入端连接，所述第一电感L1串联在所述第一变压器T1的连接供电电压Vcc1的输入端和所述供电电压Vcc1之间。
更进一步地，所述T型匹配单元包括第五电容C5、第六电容C6以及第二电感L2；
所述第五电容C5的一端为所述T型匹配单元的输入端，所述第五电容C5 的另一端与所述第二电感L2的一端、所述第六电容C6的一端连接，所述第六电容C6的另一端为所述T型匹配单元的输出端，所述第二电感L2的另一端接地。
更进一步地，所述输出匹配网络还包括第七电容C7、第三电感L3以及两个第八电容C8；
所述第七电容C7的一端与所述第二变压器T2的所述另一个输出端连接，所说第七电容C7的另一端接地，所述第二变压器T2的所述另一个输出端通过所述第三电感L3接地，所述两个第八电容C8的一端分别与所述第二变压器T2的两个输入端连接，所述两个第八电容C8的另一端接地。
更进一步地，所述输入匹配网络包括第九电容C9、第十电容C10、第四电感L4以及第五电感L5；
所述第九电容C9的一端与第四电感L4的一端连接，且连接节点用于输入所述单端射频输入信号RFin，所述第四电感L4的另一端接地，所述第九电容C9的另一端与所述第十电容C10的一端连接，所述第十电容C10的另一端与所述第一级单路放大电路的输入端连接，所述第五电感L5的一端连接在所述第九电容C9和第十电容C10之间，所述第五电感L5的另一端接地。
更进一步地，在所述T型匹配单元的输出端和所述第三级双路放大电路的输入端之间还串联有第三电阻R3。
更进一步地，所述第一变压器T1和所述第二变压器T2均为对称互绕式变压器。
更进一步地，所述对称互绕式变压器的匝数比在2:1～1:1之间。
本实用新型另一方面还提供一种射频前端架构，包括上述任一项所述的基于变压器匹配的三级功率放大器。
有益效果：本实用新型的基于变压器匹配的三级功率放大器，包括输入匹配网络、第一级单路放大电路、第一级间匹配网络、第二级双路放大电路、第二级间匹配网络、第三级双路放大电路以及输出匹配网络；所述第一级间匹配网络包括第一变压器T1，所述第二级间匹配网络包括两个π型匹配单元和两个扼流电感L，所述输出匹配网络包括第二变压器T2；所述输入匹配网络的输入端和输出端分别连接单端射频输入信号RFin和第一级单路放大电路的输入端， 所述第一变压器T1的两个输入端分别连接所述第一级单路放大电路的输出端和供电电压Vcc1，所述第一变压器T1的两个输出端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别与所述两个T型匹配单元的输入端连接，所述两个T型匹配单元的输出端分别与所述第三级双路放大电路的两个输入端连接，两个所述扼流电感L的一端分别与所述第二级双路放大电路的两个输出端连接，两个所述扼流电感L的另一端连接供电电压Vcc2，所述第三级双路放大电路的两个输出端分别与所述第二变压器T2的两个输入端连接，所述第二变压器T2的一个输出端用于输出射频信号RFout，另一个输出端接地，由此通过将级间匹配网络和输出匹配网络采用变压器来实现，可以有效降低级间匹配难度，可有效优化输入回波损耗和增益，同时可以提高输出功率。
附图说明
下面结合附图，通过对本实用新型的具体实施方式详细描述，将使本实用新型的技术方案及其有益效果显而易见。
图1是本实用新型实施例提供的基于变压器匹配的三级功率放大器的电路图；
图2是本实用新型实施例提供的对称互绕变压器的原理图；
图3是本实用新型实施例提供的对称互绕变压器的版图。
具体实施方式
请参照图式，其中相同的组件符号代表相同的组件，本实用新型的原理是以实施在一适当的运算环境中来举例说明。以下的说明是基于所例示的本实用新型具体实施例，其不应被视为限制本实用新型未在此详述的其它具体实施例。
参阅图1，本实用新型实施例在的差分功率放大器100中，包括依次串联连接的输入匹配网络11、第一级单路放大电路12、第一级间匹配网络13、第二级双路放大电路14、第二级间匹配网络15、第三级双路放大电路16以及输出匹配网络17。所述第一级间匹配网络13包括第一变压器T1，所述第二级间匹配网络15包括两个π型匹配单元和两个扼流电感L，所述输出匹配网络17包括第二变压器T2。
其中，所述输入匹配网络11的输入端和输出端分别连接单端射频输入信号 RFin和第一级单路放大电路12的输入端，所述第一变压器T1的两个输入端分别连接所述第一级单路放大电路12的输出端和供电电压Vcc1，所述第一变压器T1的两个输出端分别连接所述第二级双路放大电路14的两个输入端，所述第二级双路放大电路14的两个输出端分别与所述两个T型匹配单元的输入端连接，所述两个T型匹配单元的输出端分别与所述第三级双路放大电路16的两个输入端连接，两个所述扼流电感L的一端分别与所述第二级双路放大电路14的两个输出端连接，两个所述扼流电感L的另一端连接供电电压Vcc2，所述第三级双路放大电路16的两个输出端分别与所述第二变压器T2的两个输入端连接，所述第二变压器T2的一个输出端用于输出射频信号RFout，另一个输出端接地。
本实用新型实施例中，通过采用三级放大电路实现功率放大器100，由此可获得高增益，并且通过将级间匹配网络和输出匹配网络采用变压器来实现，可以有效降低级间匹配难度，可有效优化输入回波损耗和增益，有利于提高输出功率。
在本实用新型的一些实现方式中，第一级单路放大电路12、第二级双路放大电路14以及第三级双路放大电路16可采用HBT晶体管实现，当然，在其他一些实现方式中，也可以采用其他工艺实现，例如各级放大电路还可以采用COMS管、HEMT管或pHEMT管来实现。
以HBT晶体管为例，所述第一级单路放大电路12包括一个第一晶体管Q1，所述第二级双路放大电路14包括两个第二晶体管Q2，所述第三级双路放大电路16包括两个第三晶体管Q3。
其中，所述第一晶体管Q1的基极和集电极分别为所述第一级单路放大电路的输入端和输出端，所述第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路的两个输出端，所述两个第二晶体管Q2的发射极接地；所述两个第三晶体管Q3的基极分别为所述第三级双路放大电路的两个输入端，所述两个第三晶体管Q3的集电极分别为所述第三级双路放大电路的两个输出端，所述两个第三晶体管Q3的发射极接地。
进一步地，所述三级功率放大器100还包括连接在所述第一晶体管Q1的 集电极和基极之间的负反馈网络18，所述负反馈网络18包括串联的第一电阻R1和第一电容C1。所述第一级单路放大电路12还包括第二电阻R2，所述第二电阻R2串联在所述输入匹配网络11和所述第一晶体管Q1的基极之间，并与所述负反馈网络18并联。由此，通过在第一晶体管Q1的基极串联阻值较小的第二电阻R2，并在第一晶体管Q1的集电极和基极之间增加负反馈网络18，其中，通过第一电阻R1的作用可调节反馈深度，从而增加稳定性的同时使第一级单路放大电路12的增益和输出功率有所降低。通过第一电容C1，可以调节反馈所在的频段位置。
从图1可以看出，本实用新型实施例中，第一级单路放大电路12采用第一晶体管Q1实现一路放大电路，在其他实施例中，第一晶体管Q1的数量不限于是一个，可以采用多个并联的第一晶体管Q1实现第一级单路放大电路12，多个第一晶体管Q1实现并联的方式为多个第一晶体管Q1的基极各自串联一个第二电阻R2后并联在一起，第一晶体管Q1的集电极并联在一起作为第一级单路放大电路12的输出端，第一晶体管Q1的发射极均接地。同理地，图1所示的实施例中，第二级双路放大电路14采用两个第二晶体管Q2实现两路放大电路，在其他实时方式中，第二级双路放大电路14的每一路放大电路也可以采用多个并联的第二晶体管Q2实现，每一路放大电路中的多个并联的第二晶体管Q2的基极并联在一起，集电极并联在一起，发射极均接地。此外，第三级双路放大电路16采用两个第三晶体管Q3分别实现两路放大电路，在其他实时方式中，第三级双路放大电路16的每一路放大电路可以采用多个并联的第三晶体管Q3实现，每一路中多个并联的第三晶体管Q3的基极并联在一起，集电极并联在一起，发射极接地。
其中，所述第一级间匹配网络13还包括第二电容C2、第三电容C3、两个第四电容C4以及第一电感L1。所述第二电容C2的一端与所述第一变压器T1中连接所述第一晶体管Q1的集电极的输入端连接，所述第二电容C2的另一端接地，所述第三电容C3的一端与所述第一变压器T1中连接供电电压Vcc1的输入端连接，所述第一电感L1串联在所述第一变压器T1的连接供电电压Vcc1的输入端和所述供电电压Vcc1之间。两个第四电容C4大小相同并且为隔直电容，可调节第二级双路放大电路增益的趋势，第二电容C2、第三电容C3以及 第一电感L1可增加变压器T1的匹配带宽，并且降低变压器T1的匹配网络的插损。
其中，所述T型匹配单元包括第五电容C5、第六电容C6以及第二电感L2。所述第五电容C5的一端为所述T型匹配单元的输入端，所述第五电容C5的另一端与所述第二电感L2的一端、所述第六电容C6的一端连接，所述第六电容C6的另一端为所述T型匹配单元的输出端，所述第二电感L2的另一端接地。
其中，所述输出匹配网络17还包括第七电容C7、第三电感L3以及两个第八电容C8。所述第七电容C7的一端与所述第二变压器T2的所述另一个输出端连接，所说第七电容C7的另一端接地，所述第二变压器T2的所述另一个输出端通过所述第三电感L3接地，所述两个第八电容C8的一端分别与所述第二变压器T2的两个输入端连接，所述两个第八电容C8的另一端接地。通过第二变压器T2作用，可以实现将双路差分信号转为单端信号输出，具体地，相位相差180°的双路差分信号经过该第二变压器T2后将再次产生180°的相位差，此时的相位差为360°即0°，由此完成功率合成，以此获得高输出功率。第七电容C7、第八电容C8以及第三电感L3和变压器T2共同组成变压器匹配网络，通过第七电容C7、第八电容C8以及第三电感L3的作用可增加变压器T2的匹配带宽，并且降低变压器T2匹配网络的插损。
本实用新型实施例中，为优化整体电路的插入回波损耗，所述输入匹配网络11采用两阶LC匹配实现，即电感并联接地和电容串联形成的高通匹配结构，有利于增加稳定性的同时使第一级单路放大电路12的增益和输出功率有所降低。具体地，输入匹配网络11包括所述输入匹配网络包括第九电容C9、第十电容C10、第四电感L4以及第五电感L5。所述第九电容C9的一端与第四电感L4的一端连接，且连接节点用于输入所述单端射频输入信号RFin，所述第四电感L4的另一端接地，所述第九电容C9的另一端与所述第十电容C10的一端连接，所述第十电容C10的另一端与所述第一级单路放大电路12的输入端(也即第一晶体管Q1的基极)连接，其中，第二电阻R2串联在所述第十电容C10和所述第一晶体管Q1的基极之间。所述第五电感L5的一端连接在所述第九电容C9和第十电容C10之间，所述第五电感L5的另一端接地。
进一步地，第三级双路放大电路16还包括第三电阻R3，即在所述T型匹 配单元的输出端和所述第三级双路放大电路16的输入端之间还串联有第三电阻R3。功率放大器100还包括与各级放大电路中的每个所述晶体管的基极一一对应连接的基极偏置电路，用于对晶体管的基极提供偏置电压。
其中，供电电压Vcc1和Vcc2用于对相应器件进行供电，其大小可以相同也可以不同，可以根据实际需要进行选择。
参阅图2和图3，本实用新型的实施例中，第一变压器T1和第二变压器T2均为互绕对称式变压器，接地点在对称轴上，由此在输出信号相位转换时可确保相位足够精确，在传输差分信号方面有较大优势。此外，对称互绕变压器有较大的互感，因此其耦合系数K值较大为0.7～0.9，K值越大，变压器越接近理想状态，其带宽较宽、插入损耗较小。并且该变压器的初级线圈和次级线圈的端口在变压器两端，因此十分适合用于前后级电路的级联。例如，以第一变压器T1为例，变压器的E、F端分别连接第一晶体管Q1的集电极与直流供电端Vcc1，E、F端及其连接线圈为初级线圈，M、N端连接第二级双路放大电路的两个输入端，M、N及其连接线圈为次级线圈，初、次级线圈匝数比在2:1与1:1之间。
通过本实用新型的基于变压器匹配的三级功率放大器，有利于降低匹配难度，且可以使得级间匹配和整体匹配的插入回波损耗较好，具有较高的增益、输出功率和效率。
本实用新型实施例还提供一种射频前端架构，包括上述任一实施例所描述的基于变压器匹配的三级功率放大器。
以上对本实用新型实施例所提供的一种基于变压器匹配的三级功率放大器及射频前端架构进行了详细介绍，本文中应用了具体个例对本实用新型的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本实用新型的方法及其核心思想；同时，对于本领域的技术人员，依据本实用新型的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本实用新型的限制。

Claims (10)

  1. 一种基于变压器匹配的三级功率放大器，其特征在于，包括输入匹配网络、第一级单路放大电路、第一级间匹配网络、第二级双路放大电路、第二级间匹配网络、第三级双路放大电路以及输出匹配网络；
    所述第一级间匹配网络包括第一变压器T1，所述第二级间匹配网络包括两个π型匹配单元和两个扼流电感L，所述输出匹配网络包括第二变压器T2；
    所述输入匹配网络的输入端和输出端分别连接单端射频输入信号RFin和第一级单路放大电路的输入端，所述第一变压器T1的两个输入端分别连接所述第一级单路放大电路的输出端和供电电压Vcc1，所述第一变压器T1的两个输出端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别与所述两个T型匹配单元的输入端连接，所述两个T型匹配单元的输出端分别与所述第三级双路放大电路的两个输入端连接，两个所述扼流电感L的一端分别与所述第二级双路放大电路的两个输出端连接，两个所述扼流电感L的另一端连接供电电压Vcc2，所述第三级双路放大电路的两个输出端分别与所述第二变压器T2的两个输入端连接，所述第二变压器T2的一个输出端用于输出射频信号RFout，另一个输出端接地。
  2. 根据权利要求1所述的基于变压器匹配的三级功率放大器，其特征在于，所述第一级单路放大电路包括一个第一晶体管Q1，所述第二级双路放大电路包括两个第二晶体管Q2，所述第三级双路放大电路包括两个第三晶体管Q3；
    所述第一晶体管Q1的基极和集电极分别为所述第一级单路放大电路的输入端和输出端，所述第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路的两个输出端，所述两个第二晶体管Q2的发射极接地；所述两个第三晶体管Q3的基极分别为所述第三级双路放大电路的两个输入端，所述两个第三晶体管Q3的集电极分别为所述第三级双路放大电路的两个输出端，所述两个第三晶体管Q3的发射极接地。
  3. 根据权利要求2所述的基于变压器匹配的三级功率放大器，其特征在于，还包括连接在所述第一晶体管Q1的集电极和基极之间的负反馈网络，所述负反馈网络包括串联的第一电阻R1和第一电容C1；
    所述第一级单路放大电路还包括第二电阻R2，所述第二电阻R2串联在所述输入匹配网络和所述第一晶体管Q1的基极之间，并与所述负反馈网络并联。
  4. 根据权利要求2所述的基于变压器匹配的三级功率放大器，其特征在于，所述第一级间匹配网络还包括第二电容C2、第三电容C3、两个第四电容C4以及第一电感L1；
    所述第二电容C2的一端与所述第一变压器T1中连接所述第一晶体管Q1的集电极的输入端连接，所述第二电容C2的另一端接地，所述第三电容C3的一端与所述第一变压器T1中连接供电电压Vcc1的输入端连接，所述第一电感L1串联在所述第一变压器T1的连接供电电压Vcc1的输入端和所述供电电压Vcc1之间。
  5. 根据权利要求1所述的基于变压器匹配的三级功率放大器，其特征在于，所述T型匹配单元包括第五电容C5、第六电容C6以及第二电感L2；
    所述第五电容C5的一端为所述T型匹配单元的输入端，所述第五电容C5的另一端与所述第二电感L2的一端、所述第六电容C6的一端连接，所述第六电容C6的另一端为所述T型匹配单元的输出端，所述第二电感L2的另一端接地。
  6. 根据权利要求1所述的基于变压器匹配的三级功率放大器，其特征在于，所述输出匹配网络还包括第七电容C7、第三电感L3以及两个第八电容C8；
    所述第七电容C7的一端与所述第二变压器T2的所述另一个输出端连接，所说第七电容C7的另一端接地，所述第二变压器T2的所述另一个输出端通过所述第三电感L3接地，所述两个第八电容C8的一端分别与所述第二变压器T2的两个输入端连接，所述两个第八电容C8的另一端接地。
  7. 根据权利要求1所述的基于变压器匹配的三级功率放大器，其特征在于，所述输入匹配网络包括第九电容C9、第十电容C10、第四电感L4以及第五电感L5；
    所述第九电容C9的一端与第四电感L4的一端连接，且连接节点用于输入所述单端射频输入信号RFin，所述第四电感L4的另一端接地，所述第九电容C9的另一端与所述第十电容C10的一端连接，所述第十电容C10的另一端与所述第一级单路放大电路的输入端连接，所述第五电感L5的一端连接在所述 第九电容C9和第十电容C10之间，所述第五电感L5的另一端接地；
    在所述T型匹配单元的输出端和所述第三级双路放大电路的输入端之间还串联有第三电阻R3。
  8. 根据权利要求1所述的基于变压器匹配的三级功率放大器，其特征在于，所述第一变压器T1和所述第二变压器T2均为对称互绕式变压器。
  9. 根据权利要求8所述的基于变压器匹配的三级功率放大器，其特征在于，所述对称互绕式变压器的匝数比在2:1～1:1之间。
  10. 一种射频前端架构，其特征在于，包括权利要求1-9任一项所述的基于变压器匹配的三级功率放大器。
PCT/CN2022/108109 2021-09-27 2022-07-27 基于变压器匹配的三级功率放大器及射频前端架构 WO2023045543A1 (zh)

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