WO2024045345A1 - 半导体器件及电子器件 - Google Patents

半导体器件及电子器件 Download PDF

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Publication number
WO2024045345A1
WO2024045345A1 PCT/CN2022/131460 CN2022131460W WO2024045345A1 WO 2024045345 A1 WO2024045345 A1 WO 2024045345A1 CN 2022131460 W CN2022131460 W CN 2022131460W WO 2024045345 A1 WO2024045345 A1 WO 2024045345A1
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Prior art keywords
layer
active layer
active
hole
insulating
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PCT/CN2022/131460
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English (en)
French (fr)
Inventor
李治福
刘广辉
戴超
艾飞
宋德伟
罗成志
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US17/926,189 priority Critical patent/US12532508B2/en
Publication of WO2024045345A1 publication Critical patent/WO2024045345A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the field of display technology, and in particular to a semiconductor device and an electronic device.
  • liquid crystal display panels Liquid Crystal Display, LCD
  • organic light emitting diode (OLED) mobile terminals are widely used due to their advantages such as high image quality, power saving, thin body and wide application range. It has become the mainstream in display devices in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers.
  • the minimum size of the mask pattern is generally larger than 2 ⁇ m.
  • Embodiments of the present application provide a semiconductor device and an electronic device to alleviate deficiencies in related technologies.
  • Embodiments of the present application provide a semiconductor device, including:
  • a thin film transistor layer is provided on the insulating base.
  • the thin film transistor layer includes a first active layer, an insulating layer and a second active layer that are stacked on the insulating base.
  • the insulating layer is provided on the insulating base. between the first active layer and the second active layer and covering the first active layer;
  • the insulating layer is formed with a through hole located on the first active layer
  • the thin film transistor layer further includes a third active layer located at least partially on the sidewall of the through hole, and the third One side of the active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer.
  • the thin film transistor layer further includes a first metal layer located in the insulating layer, the first metal layer is insulated from the first active layer, and the The first metal layer is located on at least one side of the through hole.
  • the first metal layer is disposed around the third active layer on the sidewall of the through hole.
  • the first active layer includes a first conductor part doped with ions
  • the second active layer includes a second conductor part doped with ions
  • the The orthographic projection of the first conductor part on the insulating substrate at least overlaps with the orthographic projection of part of the second conductor part on the insulating substrate; wherein one side of the third active layer and the first The conductor part is connected, and the other side of the third active layer is connected to the second conductor part.
  • the doping ion concentration of the second conductor part is smaller than the doping ion concentration of the first conductor part.
  • the thin film transistor layer includes a second metal layer located on a side of the second active layer away from the insulating layer, and the second metal layer includes a A first electrode connected to a conductor part, and a second electrode connected to the second conductor part;
  • the first conductor part includes a first conductor sub-part connected to the third active layer and a second conductor sub-part connected to the first electrode, and the second conductor sub-part is in the The orthographic projection on the insulating base does not overlap with the orthographic projection of the second conductor part on the insulating base.
  • the second conductor part includes a third conductor sub-part connected to the third active layer and a fourth conductor sub-part connected to the second electrode, wherein, the doping ion concentration of the first conductor sub-section is less than the doping ion concentration of the second conductor sub-section, and the doping ion concentration of the third conductor sub-section is less than the doping ion concentration of the fourth conductor sub-section. Impurity ion concentration.
  • the first conductor sub-portion is connected to one side of the third active layer, and the third conductor sub-portion is connected to another side of the third active layer. side connection.
  • the thin film transistor layer includes a channel between the first active layer and the second active layer, and the length of the channel is equal to the length of the channel.
  • the depth of the hole satisfies the following relationship:
  • L represents the length of the channel
  • H represents the depth of the through hole
  • ⁇ represents the angle between the third active layer on the side wall of the through hole and the bottom of the through hole.
  • the angle ⁇ between the third active layer on the sidewall of the through hole and the bottom of the through hole is greater than 90 degrees and less than or equal to 120 degrees.
  • the length of the channel in a direction perpendicular to the insulating substrate, is greater than or equal to 3,000 angstroms and less than or equal to 10,000 angstroms.
  • the third active layer includes a first active sub-portion and a second active sub-portion connected to each other, and the first active sub-portion is located in the insulating layer.
  • the first active sub-portion is connected to the second active layer, and the second active sub-portion passes through the side wall of the through hole and is connected to the first active layer. connect.
  • the thin film transistor layer further includes a barrier layer located between the insulating layer and the second active layer, and at least part of the barrier layer is located in the through hole. .
  • a side of the barrier layer close to the second active layer is flush with a side of the insulating layer close to the second active layer.
  • the third active layer is located on the sidewall and bottom of the through hole, and extends to a side of the insulating layer away from the insulating base.
  • the insulating layer includes a first insulating layer and a second insulating layer provided on the insulating base, and the first insulating layer is located on the first active layer. And covering the first active layer, the second active layer covers the first active layer;
  • the first insulating layer is formed with a first through hole located on the first active layer
  • the second insulating layer is formed with a first through hole located on the first active layer and connected to the first through hole.
  • the second through hole is connected, and the angle between the side wall of the second through hole and the first active layer is equal to the angle between the side wall of the first through hole and the first active layer. The angles are equal in size.
  • An embodiment of the present application provides an electronic device.
  • the electronic device includes a semiconductor device.
  • the semiconductor device includes:
  • a thin film transistor layer is provided on the insulating base.
  • the thin film transistor layer includes a first active layer, an insulating layer and a second active layer that are stacked on the insulating base.
  • the insulating layer is provided on the insulating base. between the first active layer and the second active layer and covering the first active layer;
  • the insulating layer is formed with a through hole located on the first active layer
  • the thin film transistor layer further includes a third active layer located at least partially on the sidewall of the through hole, and the third One side of the active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer.
  • the thin film transistor layer further includes a first metal layer located in the insulating layer, the first metal layer is insulated from the first active layer, and the The first metal layer is located on at least one side of the through hole.
  • the first active layer includes a first conductor part doped with ions
  • the second active layer includes a second conductor part doped with ions
  • the The orthographic projection of the first conductor part on the insulating substrate at least overlaps with the orthographic projection of part of the second conductor part on the insulating substrate; wherein one side of the third active layer and the first The conductor part is connected, and the other side of the third active layer is connected to the second conductor part.
  • the third active layer includes a first active sub-portion and a second active sub-portion connected to each other, and the first active sub-portion is located on the insulating layer.
  • the first active sub-portion is connected to the second active layer, and the second active sub-portion passes through the side wall of the through hole and is connected to the first active layer. connect.
  • Embodiments of the present application provide a semiconductor device and an electronic device.
  • the semiconductor device includes an insulating base and a thin film transistor layer disposed on the insulating base.
  • the thin film transistor layer includes a first thin film transistor layer disposed on the insulating base.
  • a through hole located on the first active layer is formed by arranging the insulating layer, and the thin film transistor layer further includes a third active layer located at least partially on the sidewall of the through hole, the One side of the third active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer, thereby reducing the channel length and reducing short channels.
  • the channel effect increases the on-state current and reduces the power consumption; and further reduces the area occupied by the semiconductor device and improves the integration of the semiconductor device, which is beneficial to the development of high PII and high refresh rate products and the implementation of some IC function.
  • Figure 1 is a top cross-sectional view of an existing thin film transistor
  • Figure 2 is a schematic cross-sectional structural diagram along the A-A' direction in Figure 1;
  • Figure 3 is a top cross-sectional view of a semiconductor device provided by an embodiment of the present application.
  • Figure 4 is a schematic diagram of the first cross-sectional structure along the A-A' direction in Figure 3;
  • Figure 5 is an enlarged view of B in Figure 4.
  • Figure 6 is a schematic diagram of the second cross-sectional structure along the A-A' direction in Figure 3;
  • Figure 7 is an enlarged view of B in Figure 6;
  • Figure 8 is a schematic diagram of the third cross-sectional structure along the A-A' direction in Figure 3;
  • Figure 9 is an enlarged view of B in Figure 8.
  • Figure 10 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • FIGS. 11A to 11G are structural process flow diagrams for manufacturing the semiconductor device in FIG. 10 .
  • Embodiments of the present application provide a display panel, a manufacturing method thereof, and a mobile terminal.
  • the present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.
  • Embodiments of the present application provide a semiconductor device and an electronic device. Each is explained in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.
  • inventions of the present application provide a semiconductor device and an electronic device.
  • the semiconductor device includes:
  • the thin film transistor layer 40 is provided on the insulating substrate 10.
  • the thin film transistor layer 40 includes a first active layer 41, an insulating layer 44 and a second active layer 42 that are stacked on the insulating substrate 10.
  • the insulating layer 44 is disposed between the first active layer 41 and the second active layer 42 and covers the first active layer 41;
  • the insulating layer 44 is formed with a through hole 44C located on the first active layer 41
  • the thin film transistor layer 40 further includes a third active layer located at least partially on the sidewall 44C1 of the through hole 44C.
  • Layer 43 one side of the third active layer 43 is connected to the first active layer 41
  • the other side of the third active layer 43 is connected to the second active layer 42 .
  • Figure 1 is a top cross-sectional view of an existing thin film transistor
  • Figure 2 is a schematic cross-sectional structural diagram along the A-A' direction in Figure 1.
  • the existing thin film transistor includes an insulating substrate 10, and a light-shielding layer 20, a first buffer layer 30, an active layer 410, a gate insulating layer 44, a gate electrode 45A, and an interlayer insulating layer that are sequentially stacked on the insulating substrate 10. 46.
  • the technical solution of the present application is illustrated by taking an existing display panel including a top-gate thin film transistor as an example.
  • TFT ThinFilmTransistor
  • a through hole located on the first active layer is formed by arranging the insulating layer, and the thin film transistor layer further includes a third active layer located at least partially on the sidewall of the through hole, One side of the third active layer is connected to the first active layer, and the other side of the third active layer is connected to the second active layer, thereby reducing the channel length and reducing the
  • the short channel effect increases the on-state current and reduces power consumption; and further reduces the area occupied by the semiconductor device, improves the integration of the semiconductor device, and is conducive to the development of high PII and high refresh rate products;
  • the semiconductor device provided in this embodiment has the characteristics of small size and high integration, it can also realize functions such as data storage and voltage conversion of the IC.
  • FIG. 3 is a top cross-sectional view of the semiconductor device provided by the embodiment of the present application
  • FIG. 4 is the first type along the A-A′ direction in FIG. 3.
  • Figure 5 is an enlarged view of B in Figure 4.
  • the semiconductor device includes an insulating substrate 10 and a thin film transistor layer 40 disposed on the insulating substrate 10.
  • the insulating substrate 10 may include a rigid substrate or a flexible substrate.
  • the insulating substrate 10 materials are not subject to specific restrictions.
  • the thin film transistor layer 40 includes a first active layer 41 , an insulating layer 44 and a second active layer 42 that are stacked on the insulating substrate 10 .
  • the insulating layer 44 is provided on the first active layer 41 and the second active layer 42 and covering the first active layer 41; wherein the insulating layer 44 is formed with a through hole 44C located on the first active layer 41, and the thin film transistor
  • the layer 40 also includes a third active layer 43 at least partially located on the sidewall 44C1 of the through hole 44C, one side of the third active layer 43 is connected to the first active layer 41, and the third active layer 43 is connected to the first active layer 41. The other side of the third active layer 43 is connected to the second active layer 42 .
  • the thin film transistor layer 40 includes at least one thin film transistor (not labeled in the figure).
  • the thin film transistor includes the first active layer 41 and the third active layer 41 stacked on the insulating substrate 10 .
  • the conductor portion 42, the third active layer 43 includes an active segment 43A located on the sidewall 44C1 of the through hole 44C, the orthographic projection of the first conductor portion 41 on the insulating substrate 10 is at least partially consistent with The orthographic projection of the second conductor part 42 on the insulating substrate 10 overlaps, one side of the active segment 43A is connected to the first conductor part 41, and the other side of the active segment 43A is connected to the first conductor part 41.
  • the second conductor portion 42 is connected.
  • the first active layer 41, the insulating layer 44 and the second active layer 42 are stacked on the insulating substrate 10, and the insulating layer 44 is provided on Between the first active layer 41 and the second active layer 42 and covering the first active layer 41 , the insulating layer 44 is formed with a through hole located on the first active layer 41 44C, the thin film transistor layer 40 further includes a third active layer 43 located at least partially on the sidewall 44C1 of the through hole 44C, one side of the third active layer 43 is in contact with the first active layer 41 is connected, and the other side of the third active layer 43 is connected to the second active layer 42, wherein the first active layer 41 is a first conductor part 41 doped with ions, and the The second active layer 42 is a second conductor portion 42 doped with ions, and the third active layer 43 includes an active section 43A located on the sidewall 44C1 of the through hole 44C, that is, in this embodiment , the channel P of the thin film transistor is located on the sidewall 44C
  • the channel P is located between the first active layer 41 and the second active layer 42 , and the length of the channel P is equal to the depth of the through hole 44C. Satisfy the following relationship:
  • L represents the length of the channel P
  • H represents the depth of the through hole 44C
  • ⁇ represents the angle between the side wall 44C1 of the through hole 44C and the bottom 44C4 of the through hole 44C.
  • the cross-section of the side wall 44C1 of the through hole 44C is linear, and the distance between the side wall 44C1 of the through hole 44C and the bottom 44C4 of the through hole 44C is
  • the included angle ⁇ is greater than 90 degrees and less than or equal to 120 degrees.
  • the included angle ⁇ is preferably 95 degrees, 100 degrees, 110 degrees or 120 degrees; the depth of the through hole 44C is greater than or equal to 0.3 microns and less than or equal to 0.3 microns.
  • the depth of the through hole 44C is preferably 0.03 micron, 0.5 micron or 1 micron; in the direction perpendicular to the insulating substrate 10, the length of the channel P is greater than or equal to 3000 angstroms, and Less than or equal to 10,000 Angstroms.
  • the length of the channel P of the thin film transistor can be determined by the depth of the through hole 44C. Therefore, compared with the traditional thin film transistor, which is limited by the exposure equipment during the manufacturing process, the channel P length of the thin film transistor can be determined by the depth of the through hole 44C.
  • the length of the channel P is usually greater than 2 microns.
  • the active section 43A is located on the sidewall 44C1 of the through hole 44C, where the depth of the through hole 44C is greater than or equal to 0.3 microns and less than or equal to 0.3 microns. It is equal to 1 micron, thereby reducing the length of the channel P, realizing the short channel P of the thin film transistor, and further reducing the area of the thin film transistor, which is beneficial to the production of micro thin film transistors.
  • the channel P of the thin film transistor is located on the sidewall 44C1 of the through hole 44C, compared with a traditional thin film transistor, which is limited by exposure equipment during the manufacturing process, its channel length is usually longer than 2 microns.
  • the active segment 43A on the side wall 44C1 of the through hole 44C, it is possible to control the depth of the through hole 44C, the distance between the side wall 44C1 of the through hole 44C and The angle ⁇ between the bottoms 44C4 of the through holes 44C controls the length of the channel P, that is, the length of the channel P can be controlled independently of the exposure equipment, thereby realizing the short-circuit length of the thin film transistor.
  • the channelization; and further reducing the area of the thin film transistor is conducive to the production of micro thin film transistors; in addition, since the width of the channel P is determined by the third active layer 43 on the insulating substrate 10 Therefore, under the condition that the width of the channel P is certain, shortening the length of the channel P can make the thin film transistor have a larger width-to-length ratio, and thus have a larger opening state current, reducing the power consumption of the thin film transistor.
  • the semiconductor device further includes a first buffer layer 30 and a light-shielding layer 20 located between the insulating base 10 and the insulating layer 44.
  • the first buffer layer 30 covers the Light-shielding layer 20, the orthographic projection of the light-shielding layer 20 on the insulating substrate 10 at least covers the orthographic projection of the third active layer 43 on the insulating substrate 10; wherein, the light-shielding layer 20 can be Blocking the light to the third active layer 43 , thereby reducing the increase in leakage current caused by the photogenerated carriers generated by the light irradiation of the third active layer 43 , thereby maintaining the stability of the thin film transistor during operation. .
  • the thin film transistor layer 40 further includes a first metal layer 45 located in the insulating layer 44.
  • the first metal layer 45 is insulated from the first active layer 41.
  • a metal layer 45 is located at least on one side of the through hole 44C; preferably, the first metal layer 45 includes but is not limited to a gate electrode 45A, and the gate electrode 45A is insulated from the first active layer 41.
  • the gate 45A is located at least on one side of the through hole 44C.
  • the orthographic projection of the gate 45A on the sidewall 44C1 of the third active layer 43 covers the active section 43A, so that The gate 45A is enabled to adjust the channel P current of the thin film transistor.
  • the first metal layer 45 is formed with an opening 45B located on the first active layer 41 , the opening 45B is provided corresponding to the through hole 44C, and the aperture of the opening 45B is larger than the through hole 44C.
  • the aperture of the through hole 44C is adjusted, so that the first metal layer 45 is disposed around the third active layer 43 on the sidewall 44C1 of the through hole 44C, that is, the gate 45A surrounds the through hole 44C.
  • the third active layer 43 is provided on the side wall 44C1.
  • the shape of the orthographic projection of the gate 45A on the insulating substrate 10 is an annular shape.
  • the orthographic projection of the gate 45A on the insulating substrate 10 is consistent with the The four sides of the orthographic projection of the active section 43A on the insulating substrate 10 overlap, that is, an annular channel P region is formed on the active section 43A, thereby controlling the width of the channel P region and further adjusting The channel P current of the thin film transistor.
  • the insulating layer 44 includes a first insulating layer 44B and a second insulating layer 44A disposed on the insulating substrate 10 , and the first insulating layer 44B is located on the first insulating layer 44B.
  • the second active layer 42 covers the first metal layer 45.
  • the first insulating layer 44B is the second buffer layer 44
  • the second insulating layer 44A is the gate insulating layer 44; wherein, the first insulating layer 44B is formed with a first through hole 44C2 located on the first active layer 41, and the second insulating layer 44A is formed with a first through hole 44C2 on the first active layer 41.
  • the through hole 44C includes the first through holes 44C2 that are connected with each other.
  • the materials of the first active layer 41 , the second active layer 42 and the third active layer 43 include but are not limited to amorphous silicon, polycrystalline silicon, or oxidized silicon.
  • Physical semiconductor material preferably, the first conductor part 41 and the second conductor part 42 are both made of silicide, polysilicon doped with n-type impurities at a high concentration, and the doped ions of the second conductor part 42 The concentration is smaller than the doping ion concentration of the first conductor part 41 .
  • the second conductor portion 42 with a lower doped ion concentration is formed on the active section 43A, so that the doped ions in the second conductor portion 42 are not easily Diffusion into the active section 43A is beneficial to improving the short channel effect in the thin film transistor structure, thereby optimizing the performance of the thin film transistor.
  • both the first conductor part 41 and the second conductor part 42 may be made of silicide, polysilicon doped with n-type impurities at a high concentration, for illustration only; for example, in another embodiment , the first conductor part 41 and the second conductor part 42 are both N-type heavily doped amorphous silicon layers, so when manufacturing the thin film transistor, no additional ion implantation is required, thereby avoiding the need for additional ion implantation when the second conductor part 41 is produced.
  • the conductor part 42 is made of polysilicon doped with n-type impurities at a high concentration, there is a risk that the plasma gas diffuses from the second conductor part 42 into the active section 43A.
  • the thin film transistor layer 40 further includes a barrier layer 48 located between the insulating layer 44 and the second active layer 42 , and at least part of the barrier layer 48 is located within the through hole 44C, thereby avoiding When the second conductor portion 42 is formed on the third active layer 43, the plasma gas diffuses in the direction of the active section 43A to achieve the effect of maintaining the operating stability of the thin film transistor.
  • the first metal layer 45 is located in the insulating layer 44 and the first metal layer 45 has a certain thickness. Therefore, in the insulating layer 44, The position of the first metal layer 45 forms a step; at the same time, since the third active layer 43 is located on the sidewall 44C1 of the through hole 44C and the bottom 44C4 of the through hole 44C, the position of the through hole 44C is The position will form a step difference.
  • the side of the barrier layer 48 close to the second active layer 42 is flush with the side of the insulating layer 44 close to the second active layer 42.
  • the barrier layer 48 includes a first barrier portion 48A located on the side of the insulating layer 44 away from the insulating substrate 10 and a second barrier portion 48B located in the through hole 44C.
  • the first barrier portion 48A is close to One side of the second active layer 42 is flush with the side of the insulating layer 44 close to the second active layer 42 , thereby improving the thickness of the first metal layer 45 causing the insulating layer to The upper surface of 44 is uneven at the position of the first metal layer 45.
  • the side of the second blocking portion 48B close to the second active layer 42 and the side of the insulating layer 44 close to the second active layer 44 are uneven.
  • One side of the source layer 42 is flush, thereby avoiding the risk of the second conductor portion 42 being broken at the step position when the second conductor portion 42 is formed on the third active layer 43 .
  • the thin film transistor layer 40 includes a second metal layer 47 located on a side of the second active layer 42 away from the insulating layer 44 , and the second metal layer 47 includes a layer similar to the first metal layer 47 .
  • the two electrodes include but are not limited to the other one of the source electrode 47A and the drain electrode 47B.
  • the first electrode is the drain electrode 47B and the second electrode is the source electrode 47A.
  • the semiconductor device includes an interlayer insulating layer 46 between the second active layer 42 and the second metal layer 47 , passing through the interlayer insulating layer 46 and on the second conductor portion 42
  • the first conductor part 41 includes a first conductor sub-part 41A1 connected to the third active layer 43, and a third conductor part 41A1 connected to the first electrode.
  • Two conductor sub-parts 41A2, the orthographic projection of the first conductor sub-part 41A1 on the insulating base 10 overlaps with at least part of the orthographic projection of the second conductor part 42 on the insulating base 10, and the second The orthographic projection of the conductor sub-portion 41A2 on the insulating substrate 10 does not overlap with the orthographic projection of the second conductor portion 42 on the insulating substrate 10 .
  • the length of the first conductor part 41 is greater than the length of the second conductor part 42, so as to facilitate
  • the drain electrode 47B is connected to the first conductor part 41, and compared with the existing thin film transistor, this embodiment increases the distance between the source electrode 47A and the drain electrode 47B, avoiding the need for the source electrode 47A.
  • a contact short circuit occurs between the drain electrode 47B and the drain electrode 47B, which is beneficial to improving the production yield of the product.
  • Figure 6 is a schematic diagram of the second cross-sectional structure along the A-A' direction in Figure 3;
  • Figure 7 is an enlarged view of B in Figure 6.
  • the structure of the display panel is similar/identical to the structure of the semiconductor device provided in the above embodiment.
  • the description of the semiconductor device in the above embodiment please refer to the description of the semiconductor device in the above embodiment, which will not be described again here. The difference between the two Just because:
  • the third active layer 43 is located on the sidewall 44C1 and the bottom 44C4 of the through hole 44C, and extends to the side of the insulating layer 44 away from the insulating substrate 10; specifically, the third active layer 43 has The active layer 43 includes a first active sub-portion 43A1 and a second active sub-portion 43A2 that are connected to each other. The first active sub-portion 43A1 is located on a side of the insulating layer 44 away from the insulating substrate 10 .
  • the active sub-portion 43A1 is connected to the second active layer 42, and the second active sub-portion 43A2 is connected to the first active layer 41 through the side wall 44C1 of the through hole 44C, wherein the The first active sub-part 43A1 is connected to the second conductor part 42, the second active sub-part 43A2 is connected to the first conductor part 41, and the first conductor part 41 is on the insulating base.
  • the orthographic projection on the insulating substrate 10 covers the orthographic projection of the second active sub-portion 43A2 on the insulating substrate 10 , and the orthographic projection of the second conductor portion 42 on the insulating substrate 10 covers the first active sub-portion 43A2 . Orthographic projection of sub-portion 43A1 on the insulating substrate 10 .
  • this embodiment increases the efficiency by arranging the orthographic projection of the second conductor part 42 on the insulating substrate 10 to cover the orthographic projection of the first active sub-part 43A1 on the insulating substrate 10 .
  • the contact area between the second conductor part 42 and the third active layer 43 improves the stability of signal transmission.
  • FIG. 8 is a third cross-sectional structural schematic diagram along the A-A′ direction in FIG. 3 ;
  • FIG. 9 is an enlarged view of B in FIG. 8 .
  • the structure of the display panel is similar/identical to the structure of the semiconductor device provided in the above embodiment.
  • the description of the semiconductor device in the above embodiment please refer to the description of the semiconductor device in the above embodiment, which will not be described again here. The difference between the two Just because:
  • the second conductor part 42 includes a third conductor sub-part 42A1 connected to the third active layer 43 and a fourth conductor sub-part 42A2 connected to the second electrode, wherein, The doping ion concentration of the first conductor sub-section 41A1 is less than that of the second conductor sub-section 41A2, and the doping ion concentration of the third conductor sub-section 42A1 is less than that of the fourth conductor sub-section 42A2. doping ion concentration.
  • the first conductor sub-portion 41A1 is connected to one side of the third active layer 43
  • the third conductor sub-portion 42A1 is connected to another side of the third active layer 43 .
  • One side is connected; it can be understood that in this embodiment, the first conductor sub-section 41A1 with a smaller doping ion concentration is connected to one side of the third active layer 43 and the doping ion concentration is smaller.
  • the third conductor sub-portion 42A1 is connected to the other side of the third active layer 43, thereby preventing the plasma gas in the first conductor portion 41 and the second conductor portion 42 from flowing toward the active layer 43.
  • the direction of the source segment 43A is diffused to achieve the effect of maintaining the operating stability of the thin film transistor.
  • Embodiments of the present application also provide a method for manufacturing a semiconductor device. Please refer to Figures 6, 7, 10, 11A to 11G; wherein, Figure 10 is a flow chart of a method of manufacturing a semiconductor device provided by an embodiment of the application. Figure; Figures 11A to 11G are structural process flow charts for manufacturing the semiconductor device in Figure 10.
  • the method for manufacturing a vertically structured semiconductor device includes the following steps:
  • Step S100 Provide an insulating substrate 10.
  • the material when the insulating substrate 10 is a rigid substrate, the material may be metal or glass; when the insulating substrate 10 is a flexible substrate, the material may include acrylic resin, methacrylic resin, polyisoprene, At least one of vinyl resin, epoxy resin, polyurethane resin, cellulose resin, silicone resin, polyimide-based resin, and polyamide-based resin.
  • Step S200 Form a thin film transistor layer 40 on the insulating substrate 10.
  • the thin film transistor layer 40 includes a first active layer 41, an insulating layer 44 and a second active layer 42 stacked on the insulating substrate 10.
  • the insulating layer 44 is disposed between the first active layer 41 and the second active layer 42 and covers the first active layer 41; wherein the insulating layer 44 is formed on the The through hole 44C on the first active layer 41
  • the thin film transistor layer 40 also includes a third active layer 43 located at least partially on the sidewall 44C1 of the through hole 44C, the third active layer 43 One side is connected to the first active layer 41 , and the other side of the third active layer 43 is connected to the second active layer 42 .
  • the manufacturing method of the semiconductor device further includes the following steps:
  • Step S110 Form a light-shielding layer 20 and a first buffer layer 30 sequentially on the insulating substrate 10, as shown in FIG. 11A;
  • the material of the light-shielding layer 20 includes but is not limited to metal materials, and the metal materials include but is not limited to molybdenum. (Mo), titanium (Ti), nickel (Ni);
  • the material of the first buffer layer 30 includes but is not limited to a single layer of silicon nitride (Si 3 N 4 ), a single layer of Si Silicon oxide (SiO 2 ), single layer silicon oxynitride (SiON x ), or a double-layer structure of the above film layers.
  • the first active layer 41 includes a first conductor part 41 doped with ions
  • the second active layer 42 includes a second conductor part 42 doped with ions
  • the third active layer 43 includes an active segment 43A located on the sidewall 44C1 of the through hole 44C
  • the orthographic projection of the first conductor portion 41 on the insulating substrate 10 is at least the same as part of the third
  • the orthographic projections of the two conductor parts 42 on the insulating substrate 10 overlap, one side of the active segment 43A is connected to the first conductor part 41, and the other side of the active segment 43A is connected to the second conductor part 41.
  • the conductor part 42 is connected.
  • step S200 includes the following steps:
  • Step S201 Form a first amorphous silicon layer on the buffer layer, and perform crystallization processing on the first amorphous silicon layer to form a first polysilicon film; specifically, deposit an amorphous silicon layer on the buffer layer.
  • An amorphous silicon material (a-si) is layered to form the first amorphous silicon layer, and the first amorphous silicon layer is subjected to an excimer laser annealing (ELA) process to form the first polysilicon film.
  • ELA excimer laser annealing
  • Step S202 Pattern the first polysilicon film to form a first polysilicon pattern. Specifically, use a photomask and use a positive photoresist to pattern the first polysilicon through a yellow light and etching process. The film is patterned to form the first polysilicon pattern on the buffer layer.
  • Step S203 Perform ion implantation on the first polysilicon pattern to form the first conductor portion 41, as shown in FIG. 11B; wherein the ions incorporated into the first polysilicon pattern are boron ions. Or phosphorus ions.
  • Step S204 Form a first insulating layer 44B on the first conductor part 41.
  • the second insulating layer 44A covers the first conductor part 41.
  • the material of the first insulating layer 44B includes but is not limited to a single layer. Silicon nitride (Si 3 N 4 ), single layer silicon dioxide (SiO 2 ), single layer silicon oxynitride (SiON x ), or a double-layer structure of the above film layers.
  • Step S205 Form a gate electrode 45A on the side of the second buffer layer 44 away from the first buffer layer 30, where the thickness of the gate electrode 45A is greater than or equal to 0.05 microns and less than or equal to 0.2 microns, so
  • the material of the gate 45A is a metal material, which includes but is not limited to molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold ( At least one metal from the group consisting of Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta) and tungsten (W).
  • Mo molybdenum
  • Al aluminum
  • platinum (Pt) palladium
  • silver Ag
  • Au At least one metal from the group consisting of Au
  • Ni nickel
  • Nd neodymium
  • Ir irid
  • the step S205 includes: forming a first metal layer 45 on a side of the second buffer layer 44 away from the first buffer layer 30, and patterning the first metal layer 45 to form the gate.
  • the gate electrode 45A is etched with an opening 45B located above the first conductor portion 41 , and the opening 45B passes through the gate electrode 45A, as shown in FIG. 11C .
  • Step S206 Form a second insulating layer 44A on the side of the gate 45A away from the second buffer layer 44, wherein the second insulating layer 44A covers the gate 45A, thereby protecting the gate 45A.
  • the material of the second insulating layer 44A includes but is not limited to a single layer of silicon nitride (Si 3 N 4 ), a single layer of silicon dioxide (SiO 2 ), a single layer of silicon oxynitride (SiON x ), or a double-layer structure of the above film layers.
  • Step S207 Through a photomask process, open the through hole 44C on the first conductor part 41 on the second insulating layer 44A and the first insulating layer 44B.
  • the through hole 44C is connected to the first insulating layer 44B.
  • the opening 45B is provided correspondingly, and the aperture of the through hole 44C is smaller than the aperture of the opening 45B, so that the gate 45A is arranged around the third active layer 43 on the sidewall 44C1 of the through hole 44C,
  • the through hole 44C includes a first through hole 44C2 passing through the first insulating layer 44B and a second through hole 44C3 passing through the second insulating layer 44A. Sides of the second through hole 44C3
  • the angle between the wall 44C1 and the first active layer 41 is equal to the angle between the side wall 44C1 of the first through hole 44C2 and the first active layer 41 , as shown in FIG. 11D .
  • Step S208 Form a third active layer 43 on the side of the second insulating layer 44A away from the first insulating layer 44B, and at least part of the third active layer 43 is located on the sidewall 44C1 of the through hole 44C. superior.
  • the third active layer 43 is located on the sidewall 44C1 and the bottom 44C4 of the through hole 44C, and extends to the side of the insulating layer 44 away from the insulating substrate 10; wherein the third active layer 43 includes The first active sub-portion 43A1 and the second active sub-portion 43A2 are connected to each other.
  • the first active sub-portion 43A1 is located on the side of the insulating layer 44 away from the insulating substrate 10 .
  • the second active sub-portion 43A2 is connected to each other.
  • Step S209 Form a barrier layer 48 on the side of the second insulating layer 44A away from the first insulating layer 44B, and at least part of the barrier layer 48 is located in the through hole 44C; specifically, the barrier layer 48 It includes a first blocking portion 48A located on the side of the insulating layer 44 away from the insulating substrate 10 and a second blocking portion 48B located in the through hole 44C. The first blocking portion 48A is close to the second blocking portion 48B.
  • One side of the source layer 42 is flush with the side of the insulating layer 44 close to the second active layer 42
  • the side of the second blocking portion 48B close to the second active layer 42 is flush with the side of the insulating layer 44 close to the second active layer 42 .
  • the side of the layer 44 close to the second active layer 42 is flush.
  • the material of the barrier layer 48 is silicon oxide (SiO x ), as shown in FIG. 11F .
  • Step S210 Form a second amorphous silicon layer on the side of the third active layer 43 away from the first conductor part 41, and perform a crystallization process on the second amorphous silicon layer to form a second polycrystalline silicon layer.
  • Silicon film specifically, deposit a layer of amorphous silicon material (a-si) on the third active layer 43 to form the second amorphous silicon layer, and calibrate the second amorphous silicon layer.
  • Molecular laser annealing (ELA) processing to form the second polysilicon film.
  • Step S211 Pattern the third polysilicon film to form a second polysilicon pattern. Specifically, use a photomask and use a positive photoresist to pattern the third polysilicon through a yellow light and etching process. The film is patterned to form the second polysilicon pattern on the third active layer 43 .
  • Step S212 Perform ion implantation on the second polysilicon pattern to form the second conductor part 42, wherein the first active sub-part 43A1 is connected to the second active layer 42, and the The orthographic projection of the second conductor portion 42 on the insulating substrate 10 covers the orthographic projection of the first active sub-portion 43A1 on the insulating substrate 10 .
  • the first conductor part 41 includes a first conductor sub-part 41A1 connected to the third active layer 43 and a second conductor sub-part 41A2 connected to the first conductor sub-part 41A1.
  • the orthographic projection of the first conductor sub-portion 41A1 on the insulating substrate 10 overlaps at least part of the orthographic projection of the second conductor sub-portion 42 on the insulating substrate 10
  • the second conductor sub-portion 41A2 is on the insulating substrate 10 .
  • the orthographic projection on the substrate 10 does not overlap with the orthographic projection of the second conductor portion 42 on the insulating substrate 10 , as shown in FIG. 11G .
  • Step S213 Form an interlayer insulating layer 46 on the side of the barrier layer 48 away from the second insulating layer 44A.
  • the interlayer insulating layer 46 covers the barrier layer 48, the second conductor portion 42 and the The second gate 45A.
  • Step S214 Through a photomask process, a first via hole 46A is opened on the interlayer insulating layer 46, and a first via hole 46A is formed on the interlayer insulating layer 46, the barrier layer 48, the second insulating layer 44A and the A second via hole 46B is opened in the first insulating layer 44B, wherein the first via hole 46A passes through the interlayer insulating layer 46 and is located on the second conductor part 42, and the second via hole 46B passes through Passing through the interlayer insulating layer 46 , the barrier layer 48 , the second insulating layer 44A and the first insulating layer 44B and located on the second conductor sub-portion 41A2 .
  • Step S215 Form a source electrode 47A and a drain electrode 47B on the side of the interlayer insulating layer 46 away from the barrier layer 48.
  • the source electrode 47A communicates with the second conductor part 42 through the first via hole 46A.
  • the drain electrode 47B is connected to the second conductor part 42 through the second via hole 46B, as shown in FIGS. 6 and 7 .
  • This embodiment provides an electronic device, which includes the semiconductor device described in any of the above embodiments.
  • the electronic device can be a display screen of a smartphone, tablet computer, notebook computer, smart bracelet, smart watch, smart glasses, smart helmet, desktop computer, smart TV or digital camera, or even Applied to electronic devices with flexible displays.

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Abstract

本申请提供一种半导体器件及电子器件，通过设置绝缘层形成有位于第一有源层上的通孔，薄膜晶体管层还包括至少部分位于通孔的侧壁上的第三有源层，第三有源层的一侧与第一有源层连接，第三有源层的另一侧与第二有源层连接，从而减小了沟道长度，降低短沟道效应，提升了开态电流，降低了功耗。

Description

半导体器件及电子器件 技术领域
本申请涉及显示技术领域，尤其涉及一种半导体器件及电子器件。
背景技术
目前液晶显示面板(Liquid Crystal Display，LCD)和有机发光二极管(OrganicLightEmittingDiode，OLED)移动终端等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
在现有技术中，已知将像素、驱动、多路复用、控制、逻辑等IC(Integrated Circuit)电路集成在玻璃基板(system on glass，SOG)上可以提高半导体器件集成度、降低对IC芯片的依赖性；而为了实现SOG需要提高现有薄膜晶体管(Thin Film Transistor，TFT)的集成度、最大工作频率和电流密度，其中，由于薄膜晶体管导通时的电性能与有源层对应于所述源极和所述漏极之间的部分(即所述有源层的沟道(channel)长度)有关，为了实现上述效果，需要使薄膜晶体管具有更短的沟道长度和更小的体积；然而，传统的薄膜晶体管通常为平面型，在基底上通过现有曝光设备制作“I”型有源层时，其掩模图案的最小尺寸一般大于2μm，在现有技术中，很难实现所述薄膜晶体管的短沟道化，因此，如何保证在薄膜晶体管器件正常工作的前提下，减小薄膜晶体管的沟道长度、及减小薄膜晶体管在整个显示面板中所占区域的面积，是本领域技术人员亟需解决的技术问题。
技术问题
本申请实施例提供一种半导体器件及电子器件，用以缓解相关技术中的不足。
技术解决方案
为实现上述功能，本申请实施例提供的技术方案如下：
本申请实施例提供一种半导体器件，包括：
绝缘基底；
薄膜晶体管层，设置于所述绝缘基底上，所述薄膜晶体管层包括层叠设置于所述绝缘基底上的第一有源层、绝缘层以及第二有源层，所述绝缘层设置于所述第一有源层和所述第二有源层之间且覆盖所述第一有源层；
其中，所述绝缘层形成有位于所述第一有源层上的通孔，所述薄膜晶体管层还包括至少部分位于所述通孔的侧壁上的第三有源层，所述第三有源层的一侧与所述第一有源层连接，所述第三有源层的另一侧与所述第二有源层连接。
在本申请实施例所提供的半导体器件中，所述薄膜晶体管层还包括位于所述绝缘层内的第一金属层，所述第一金属层与所述第一有源层绝缘设置，所述第一金属层至少位于所述通孔的一侧。
在本申请实施例所提供的半导体器件中，所述第一金属层围绕所述通孔的侧壁上的第三有源层设置。
在本申请实施例所提供的半导体器件中，所述第一有源层包括掺杂了离子的第一导体部，所述第二有源层包括掺杂了离子的第二导体部，所述第一导体部在所述绝缘基底上的正投影至少与部分所述第二导体部在所述绝缘基底上的正投影重叠；其中，所述第三有源层的一侧与所述第一导体部连接，所述第三有源层的另一侧与所述第二导体部连接。
在本申请实施例所提供的半导体器件中，所述第二导体部的掺杂离子浓度小于所述第一导体部的掺杂离子浓度。
在本申请实施例所提供的半导体器件中，所述薄膜晶体管层包括位于所述第二有源层远离所述绝缘层一侧的第二金属层，所述第二金属层包括与所述第一导体部连接的第一电极、及与所述第二导体部连接的第二电极；
其中，所述第一导体部包括与所述第三有源层连接的第一导体子部、及与所述第一电极连接的第二导体子部，所述第二导体子部在所述绝缘基底上的正投影与所述第二导体部在所述绝缘基底上的正投影不交叠。
在本申请实施例所提供的半导体器件中，所述第二导体部包括与所述第三有源层连接的第三导体子部、及与所述第二电极连接的第四导体子部，其中，所述第一导体子部的掺杂离子浓度小于所述第二导体子部的掺杂离子浓度，所述第三导体子部的掺杂离子浓度小于所述第四导体子部的掺杂离子浓度。
在本申请实施例所提供的半导体器件中，所述第一导体子部与所述第三有源层的一侧连接，所述第三导体子部与所述第三有源层的另一侧连接。
在本申请实施例所提供的半导体器件中，所述薄膜晶体管层包括位于所述第一有源层和所述第二有源层之间的沟道，所述沟道的长度与所述通孔的深度满足以下关系式：
Figure PCTCN2022131460-appb-000001
其中，L表示所述沟道的长度，H表示所述通孔的深度，α表示所述通孔的侧壁上的第三有源层与所述通孔底部之间的夹角。
在本申请实施例所提供的半导体器件中，所述通孔的侧壁上的第三有源层与所述通孔底部之间的夹角α大于90度，且小于或等于120度。
在本申请实施例所提供的半导体器件中，在垂直于所述绝缘基底的方向上，所述沟道的长度大于或等于3000埃，且小于或等于10000埃。
在本申请实施例所提供的半导体器件中，所述第三有源层包括相互连接的第一有源子部和第二有源子部，所述第一有源子部位于所述绝缘层远离绝缘基底的一侧，所述第一有源子部与所述第二有源层连接，所述第二有源子部穿过所述通孔的侧壁与所述第一有源层连接。
在本申请实施例所提供的半导体器件中，所述薄膜晶体管层还包括位于所述绝缘层和所述第二有源层之间的阻挡层，至少部分所述阻挡层位于所述通孔内。
在本申请实施例所提供的半导体器件中，所述阻挡层靠近所述第二有源层的一侧与所述绝缘层靠近所述第二有源层的一侧平齐。
在本申请实施例所提供的半导体器件中，所述第三有源层位于通孔的侧壁和底部，且延伸至所述绝缘层远离绝缘基底的一侧。
在本申请实施例所提供的半导体器件中，所述绝缘层包括设置于所述绝缘基底上的第一绝缘层和第二绝缘层，所述第一绝缘层位于所述第一有源层上且覆盖所述第一有源层，所述第二有源层覆盖所述第一有源层；
其中，所述第一绝缘层形成有位于所述第一有源层上的第一通孔，所述第二绝缘层形成有位于所述第一有源层上且与所述第一通孔连通的第二通孔，所 述第二通孔的侧壁与所述第一有源层之间的夹角与所述第一通孔的侧壁与所述第一有源层之间的夹角大小相等。
本申请实施例提供一种电子器件，所述电子器件包括一半导体器件，所述半导体器件包括：
绝缘基底；
薄膜晶体管层，设置于所述绝缘基底上，所述薄膜晶体管层包括层叠设置于所述绝缘基底上的第一有源层、绝缘层以及第二有源层，所述绝缘层设置于所述第一有源层和所述第二有源层之间且覆盖所述第一有源层；
其中，所述绝缘层形成有位于所述第一有源层上的通孔，所述薄膜晶体管层还包括至少部分位于所述通孔的侧壁上的第三有源层，所述第三有源层的一侧与所述第一有源层连接，所述第三有源层的另一侧与所述第二有源层连接。
在本申请实施例所提供的电子器件中，所述薄膜晶体管层还包括位于所述绝缘层内的第一金属层，所述第一金属层与所述第一有源层绝缘设置，所述第一金属层至少位于所述通孔的一侧。
在本申请实施例所提供的电子器件中，所述第一有源层包括掺杂了离子的第一导体部，所述第二有源层包括掺杂了离子的第二导体部，所述第一导体部在所述绝缘基底上的正投影至少与部分所述第二导体部在所述绝缘基底上的正投影重叠；其中，所述第三有源层的一侧与所述第一导体部连接，所述第三有源层的另一侧与所述第二导体部连接。
在本申请实施例所提供的电子器件中，所述第三有源层包括相互连接的第一有源子部和第二有源子部，所述第一有源子部位于所述绝缘层远离绝缘基底的一侧，所述第一有源子部与所述第二有源层连接，所述第二有源子部穿过所述通孔的侧壁与所述第一有源层连接。
有益效果
本申请实施例提供一种半导体器件及电子器件，所述半导体器件包括绝缘基底、及设置于所述绝缘基底上的薄膜晶体管层，所述薄膜晶体管层包括设置于所述绝缘基底上的第一有源层、绝缘层以及第二有源层，所述绝缘层设置于所述第一有源层和所述第二有源层之间且覆盖所述第一有源层；其中，本申请 实施例通过设置所述绝缘层形成有位于所述第一有源层上的通孔，所述薄膜晶体管层还包括至少部分位于所述通孔的侧壁上的第三有源层，所述第三有源层的一侧与所述第一有源层连接，所述第三有源层的另一侧与所述第二有源层连接，从而减小了沟道长度，降低短沟道效应，提升了开态电流，降低了功耗；并且进一步缩小所述半导体器件所占用面积减小，提高了所述半导体器件的集成度，有利于开发高PII、高刷新率产品以及实现部分IC功能。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有薄膜晶体管的俯视截面图；
图2为图1中沿A-A′方向的剖面结构示意图；
图3为本申请实施例所提供的半导体器件的俯视截面图；
图4为图3中沿A-A′方向的第一种剖面结构示意图；
图5为图4中B处的放大图；
图6为图3中沿A-A′方向的第二种剖面结构示意图；
图7为图6中B处的放大图；
图8为图3中沿A-A′方向的第三种剖面结构示意图；
图9为图8中B处的放大图；
图10为本申请实施例所提供的半导体器件的制作方法的流程图；
图11A至图11G为图10中半导体器件制作的结构工艺流程图。
本发明的实施方式
本申请实施例提供一种显示面板及其制作方法、移动终端，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例提供一种半导体器件及电子器件。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图3～图11G，本申请实施例提供一种半导体器件及电子器件，所述半导体器件包括：
绝缘基底10；
薄膜晶体管层40，设置于所述绝缘基底10上，所述薄膜晶体管层40包括层叠设置于所述绝缘基底10上的第一有源层41、绝缘层44以及第二有源层42，所述绝缘层44设置于所述第一有源层41和所述第二有源层42之间且覆盖所述第一有源层41；
其中，所述绝缘层44形成有位于所述第一有源层41上的通孔44C，所述薄膜晶体管层40还包括至少部分位于所述通孔44C的侧壁44C1上的第三有源层43，所述第三有源层43的一侧与所述第一有源层41连接，所述第三有源层43的另一侧与所述第二有源层42连接。
请结合图1和图2；其中，图1为现有薄膜晶体管的俯视截面图；图2为图1中沿A-A′方向的剖面结构示意图。
现有薄膜晶体管包括绝缘基底10、及依次层叠设置于所述绝缘基底10上的遮光层20、第一缓冲层30、有源层410、栅极绝缘层44、栅极45A、层间绝缘层46、源极47A、漏极47B、平坦层50、公共电极61、钝化层70以及像素电极62；需要说明的是，本实施例对现有薄膜晶体管的种类不做具体限制，本实施例仅以现有显示面板包括顶栅型薄膜晶体管为例对本申请的技术方案进行举例说明。
可以理解的是，随着显示面板行业的不断发展，消费者对显示面板有窄边框、高开口率、高亮度、高分辨率等参数提出了越来越高的要求，而为了实现上述效果，需要提高现有薄膜晶体管(ThinFilmTransistor，TFT)的集成度、最大工作频率和电流密度，其中，由于薄膜晶体管导通时的电性能与有源层对应于所述源极和所述漏极之间的部分(即所述有源层的沟道(channel)长度)有关，因此，需要使薄膜晶体管具有更短的沟道长度和更小的体积；但在传统的薄膜晶体管制作过程中，薄膜晶体管通常为平面型，在绝缘基底上通过现有曝光设备制作“I”型有源层时，其掩模图案的最小尺寸一般大于2μm，因此在现有技术中，很难实现所述薄膜晶体管的短沟道化。
本申请实施例通过设置所述绝缘层形成有位于所述第一有源层上的通孔， 所述薄膜晶体管层还包括至少部分位于所述通孔的侧壁上的第三有源层，所述第三有源层的一侧与所述第一有源层连接，所述第三有源层的另一侧与所述第二有源层连接，从而减小了沟道长度，降低短沟道效应，提升了开态电流，降低了功耗；并且进一步缩小所述半导体器件所占用面积减小，提高了所述半导体器件的集成度，有利于开发高PII、高刷新率产品；同时，由于本实施例所提供的半导体器件具有尺寸小、集成度高特点，因此还可以实现IC的数据存储，电压变换等功能。
现结合具体实施例对本申请的技术方案进行描述。
在一实施例中，请结合图3、图4和图5；其中，图3为本申请实施例所提供的半导体器件的俯视截面图；图4为图3中沿A-A′方向的第一种剖面结构示意图；图5为图4中B处的放大图。
在本实施例中，所述半导体器件包括绝缘基底10和设置于所述绝缘基底10上的薄膜晶体管层40，所述绝缘基底10可以包括刚性基底或柔性基底，本实施例对所述绝缘基底10的材料不做具体限制。
所述薄膜晶体管层40包括层叠设置于所述绝缘基底10上的第一有源层41、绝缘层44以及第二有源层42，所述绝缘层44设置于所述第一有源层41和所述第二有源层42之间且覆盖所述第一有源层41；其中，所述绝缘层44形成有位于所述第一有源层41上的通孔44C，所述薄膜晶体管层40还包括至少部分位于所述通孔44C的侧壁44C1上的第三有源层43，所述第三有源层43的一侧与所述第一有源层41连接，所述第三有源层43的另一侧与所述第二有源层42连接。
具体地，所述薄膜晶体管层40包括至少一薄膜晶体管(图中未标记)，所述薄膜晶体管包括层叠设置于所述绝缘基底10上的所述第一有源层41、所述第三有源层43以及第二有源层42；进一步地，所述第一有源层41为掺杂了离子的第一导体部41，所述第二有源层42为掺杂了离子的第二导体部42，所述第三有源层43包括位于所述通孔44C的侧壁44C1上的有源段43A，所述第一导体部41在所述绝缘基底10上的正投影至少与部分所述第二导体部42在所述绝缘基底10上的正投影重叠，所述有源段43A的一侧与所述第一导体 部41连接，所述有源段43A的另一侧与所述第二导体部42连接。
可以理解的是，本实施例通过将所述第一有源层41、所述绝缘层44以及所述第二有源层42层叠设置于所述绝缘基底10上，所述绝缘层44设置于所述第一有源层41和所述第二有源层42之间且覆盖所述第一有源层41，所述绝缘层44形成有位于所述第一有源层41上的通孔44C，所述薄膜晶体管层40还包括至少部分位于所述通孔44C的侧壁44C1上的第三有源层43，所述第三有源层43的一侧与所述第一有源层41连接，所述第三有源层43的另一侧与所述第二有源层42连接，其中，所述第一有源层41为掺杂了离子的第一导体部41，所述第二有源层42为掺杂了离子的第二导体部42，所述第三有源层43包括位于所述通孔44C的侧壁44C1上的有源段43A，即，在本实施例中，所述薄膜晶体管的沟道P位于所述通孔44C的侧壁44C1上。
具体地，在本实施例中，所述沟道P位于所述第一有源层41和所述第二有源层42之间，所述沟道P的长度与所述通孔44C的深度满足以下关系式：
Figure PCTCN2022131460-appb-000002
其中，L表示所述沟道P的长度，H表示所述通孔44C的深度，α表示所述通孔44C的侧壁44C1与所述通孔44C底部44C4之间的夹角。
进一步地，在垂直于所述绝缘基底10的方向上，所述通孔44C的侧壁44C1的截面呈直线型，所述通孔44C的侧壁44C1与所述通孔44C底部44C4之间的夹角α大于90度，且小于或等于120度，优选地，夹角α优选为95度、100度、110度或者120度；所述通孔44C的深度大于或等于0.3微米，且小于或等于1微米，其中，所述通孔44C的深度优选为0.03微米、0.5微米或1微米；在垂直于所述绝缘基底10的方向上，所述沟道P的长度大于或等于3000埃，且小于或等于10000埃。
可以理解的是，在本实施例中，所述薄膜晶体管的沟道P长度可以由所述通孔44C的深度决定，因此，相对于传统的薄膜晶体管在制作过程中受曝光设备的限制，其沟道P长度通常大于2微米，本实施例通过设置所述有源段43A位于所述通孔44C的侧壁44C1上，其中，所述通孔44C的深度大于或等于0.3微米，且小于或等于1微米，从而减小了所述沟道P长度，实现薄膜晶 体管的短沟道P化，并且进一步缩小所述薄膜晶体管的面积，有利于实现微型薄膜晶体管的制作。
需要说明的是，由于所述薄膜晶体管的沟道P位于所述通孔44C的侧壁44C1上，因此，相对于传统的薄膜晶体管在制作过程中受曝光设备的限制，其沟道长度通常大于2微米，本实施例通过将所述有源段43A设置于所述通孔44C的侧壁44C1上，因此可以通过控制所述通孔44C的深度、及所述通孔44C的侧壁44C1与所述通孔44C底部44C4之间的夹角α来控制所述沟道P的长度，即，所述沟道P的长度可以独立于所述曝光设备进行控制，从而实现所述薄膜晶体管的短沟道化；并且，进一步缩小所述薄膜晶体管的面积，有利于实现微型薄膜晶体管的制作；另外，由于，所述沟道P的宽度由所述第三有源层43在所述绝缘基底10上的正投影宽度决定，因此，在所述沟道P的宽度一定的条件下，缩短所述沟道P的长度能够使所述薄膜晶体管具有更大的宽长比，从而具有更大的开态电流，降低了所述薄膜晶体管的功耗。
需要说明的是，在本实施例中，所述半导体器件还包括位于所述绝缘基底10和绝缘层44之间的第一缓冲层30和遮光层20，所述第一缓冲层30覆盖所述遮光层20，所述遮光层20在所述绝缘基底10上的正投影至少覆盖所述第三有源层43在所述绝缘基底10上的正投影；其中，所述遮光层20可以对射向所述第三有源层43的光进行遮挡，从而减少因光照射所述第三有源层43产生的光生载流子导致的漏电流增加，进而保持所述薄膜晶体管工作时的稳定性。
在本实施例中，所述薄膜晶体管层40还包括位于所述绝缘层44内的第一金属层45，所述第一金属层45与所述第一有源层41绝缘设置，所述第一金属层45至少位于所述通孔44C的一侧；优选地，所述第一金属层45包括但不限于栅极45A，所述栅极45A与所述第一有源层41绝缘设置，所述栅极45A至少位于所述通孔44C的一侧，进一步地，所述栅极45A在所述第三有源层43的侧壁44C1上的正投影覆盖所述有源段43A，从而使所述栅极45A能够调节所述薄膜晶体管的沟道P电流。
具体地，所述第一金属层45形成有位于所述第一有源层41上的开孔45B，所述开孔45B与所述通孔44C对应设置，所述开孔45B的孔径大于所述通孔 44C的孔径，从而使所述第一金属层45围绕所述通孔44C的侧壁44C1上的第三有源层43设置，即，所述栅极45A围绕所述通孔44C的侧壁44C1上的第三有源层43设置，所述栅极45A在所述绝缘基底10上的正投影的形状为环形，所述栅极45A在所述绝缘基底10上的正投影与所述有源段43A在所述绝缘基底10上的正投影的四边重叠，即，在所述有源段43A上形成环形的沟道P区，从而控制所述沟道P区的宽度，进一步调节所述薄膜晶体管的沟道P电流。
需要说明的是，在本实施例中，所述绝缘层44包括设置于所述绝缘基底10上的第一绝缘层44B和第二绝缘层44A，所述第一绝缘层44B位于所述第一有源层41上且覆盖所述第一有源层41，所述第二有源层42覆盖所述第一金属层45，优选地，所述第一绝缘层44B为第二缓冲层44，所述第二绝缘层44A为栅极绝缘层44；其中，所述第一绝缘层44B形成有位于所述第一有源层41上的第一通孔44C2，所述第二绝缘层44A形成有位于所述第一有源层41上且与所述第一通孔44C2连通的第二通孔44C3，所述第二通孔44C3的侧壁44C1与所述第一有源层41之间的夹角与所述第一通孔44C2的侧壁44C1与所述第一有源层41之间的夹角大小相等，即，所述通孔44C包括相互连通的所述第一通孔44C2和所述第二通孔44C3，可以理解的是，本实施例通过设置所述绝缘层44包括设置于所述绝缘基底10上的第一绝缘层44B和第二绝缘层44A，从而便于控制所述通孔44C的深度，进而便于控制所述沟道P的长度。
在本申请中，所述第一有源层41的材料、所述第二有源层42的材料以及所述第三有源层43的材料均包括但不限于非晶硅、多晶硅、或者氧化物半导体材料，优选地，所述第一导体部41和所述第二导体部42均由硅化物制成以高浓度掺杂n型杂质的多晶硅，所述第二导体部42的掺杂离子浓度小于所述第一导体部41的掺杂离子浓度。
可以理解的是，在本实施例中，将掺杂离子浓度较低的所述第二导体部42形成在所述有源段43A上，使得所述第二导体部42中的掺杂离子不易扩散进入所述有源段43A中，利于改善薄膜晶体管结构中的短沟道效应，从而优化所述薄膜晶体管的性能。
可以理解的是，所述第一导体部41和所述第二导体部42均可以由硅化物制成以高浓度掺杂n型杂质的多晶硅仅用于举例说明；例如在另一实施例中，所述第一导体部41和所述第二导体部42均为N型重掺杂非晶硅层，从而在制作所述薄膜晶体管时，无需额外进行离子注入，进而避免当所述第二导体部42由硅化物制成以高浓度掺杂n型杂质的多晶硅时，等离子气体存在由所述第二导体部42扩散到所述有源段43A中的风险。
进一步地，所述薄膜晶体管层40还包括位于所述绝缘层44和所述第二有源层42之间的阻挡层48，至少部分所述阻挡层48位于所述通孔44C内，进而避免在所述有第三有源层43上形成第二导体部42时，等离子气体向所述有源段43A的方向扩散，以达到维持所述薄膜晶体管的工作稳定性的效果。
需要说明的是，由于在本实施例中，所述第一金属层45位于所述绝缘层44内，所述第一金属层45具有有一定厚度，因此，在所述绝缘层44中，所述第一金属层45的位置形成台阶；同时，由于所述第三有源层43位于所述通孔44C的侧壁44C1、及所述通孔44C的底部44C4，因此在所述通孔44C的位置会形成段差。
承上，在本实施例中，所述阻挡层48靠近所述第二有源层42的一侧与所述绝缘层44靠近所述第二有源层42的一侧平齐，具体地，所述阻挡层48包括位于所述绝缘层44远离所述绝缘基底10一侧的第一阻挡部48A、及位于所述通孔44C内的第二阻挡部48B，所述第一阻挡部48A靠近所述第二有源层42的一侧与所述绝缘层44靠近所述第二有源层42的一侧平齐，从而改善因所述第一金属层45的厚度，导致所述绝缘层44的上表面在所述第一金属层45位置处高低不平的问题，所述第二阻挡部48B靠近所述第二有源层42的一侧与所述绝缘层44靠近所述第二有源层42的一侧平齐，从而避免在所述有第三有源层43上形成第二导体部42时，所述第二导体部42在所述段差位置存在断裂的风险。
在本实施例中，所述薄膜晶体管层40包括位于所述第二有源层42远离所述绝缘层44一侧的第二金属层47，所述第二金属层47包括与所述第一导体部41连接的第一电极、及与所述第二导体部42连接的第二电极，其中，所述第一电极包括但不限于源极47A和漏极47B中的一者，所述第二电极包括但 不限于源极47A和漏极47B中的另一者，在本实施例以所述第一电极为漏极47B、所述第二电极为源极47A为例对本申请的技术方案进行举例说明，
所述半导体器件包括位于所述第二有源层42和所述第二金属层47之间的层间绝缘层46、穿过所述层间绝缘层46且位于所述第二导体部42上的第一过孔46A、及穿过所述层间绝缘层46、所述阻挡层48、所述第二绝缘层44A以及所述第一绝缘层44B且位于所述第一导体部41上的第二过孔46B，其中，所述第一过孔46A穿过所述层间绝缘层46，所述第二过孔46B穿过所述层间绝缘层46、所述阻挡层48、所述第二绝缘层44A以及所述第一绝缘层44B，所述源极47A通过所述第一过孔46A与所述第二导体部42连接，所述漏极47B穿过所述第二过孔46B与所述第二导体部42连接；具体地，所述第一导体部41包括与所述第三有源层43连接的第一导体子部41A1、及与所述第一电极连接的第二导体子部41A2，所述第一导体子部41A1在所述绝缘基底10上的正投影至少与部分所述第二导体部42在所述绝缘基底10上的正投影重叠，所述第二导体子部41A2在所述绝缘基底10上的正投影与所述第二导体部42在所述绝缘基底10上的正投影不交叠。
承上，可以理解的是，在本实施例中沿所述源极47A指向所述漏极47B的方向，所述第一导体部41的长度大于所述第二导体部42的长度，从而方便所述漏极47B与所述第一导体部41连接，且相对于现有薄膜晶体管，本实施例增大了所述源极47A和所述漏极47B之间的间距，避免了源极47A和漏极47B之间发生接触短路，有利于提高产品的生产良率。
在另一实施例中，请结合轻3、图6和图7；其中，图6为图3中沿A-A′方向的第二种剖面结构示意图；图7为图6中B处的放大图。
在本实施例中，所述显示面板的结构与上述实施例所提供的半导体器件的结构相似/相同，具体请参照上述实施例中的半导体器件的描述，此处不再赘述，两者的区别仅在于：
在本实施例中，所述第三有源层43位于通孔44C的侧壁44C1和底部44C4，且延伸至所述绝缘层44远离绝缘基底10的一侧；具体地，所述第三有源层43包括相互连接的第一有源子部43A1和第二有源子部43A2，所述第一有源子部43A1位于所述绝缘层44远离绝缘基底10的一侧，所述第一有源子部 43A1与所述第二有源层42连接，所述第二有源子部43A2穿过所述通孔44C的侧壁44C1与所述第一有源层41连接，其中，所述第一有源子部43A1与所述第二导体部42连接，所述第二有源子部43A2与所述第一导体部41连接，并且所述第一导体部41在所述绝缘基底10上的正投影覆盖所述第二有源子部43A2在所述绝缘基底10上的正投影，所述第二导体部42在所述绝缘基底10上的正投影覆盖所述第一有源子部43A1在所述绝缘基底10上的正投影。
可以立即的是，本实施例通过设置所述第二导体部42在所述绝缘基底10上的正投影覆盖所述第一有源子部43A1在所述绝缘基底10上的正投影，增加了所述第二导体部42与所述第三有源层43的接触面积，从而提高了信号传输的稳定性。
在另一实施例中，请结合轻3、图8；其中，图8为图3中沿A-A′方向的第三种剖面结构示意图；图9为图8中B处的放大图。
在本实施例中，所述显示面板的结构与上述实施例所提供的半导体器件的结构相似/相同，具体请参照上述实施例中的半导体器件的描述，此处不再赘述，两者的区别仅在于：
在本实施例中，所述第二导体部42包括与所述第三有源层43连接的第三导体子部42A1、及与所述第二电极连接的第四导体子部42A2，其中，所述第一导体子部41A1的掺杂离子浓度小于所述第二导体子部41A2的掺杂离子浓度，所述第三导体子部42A1的掺杂离子浓度小于所述第四导体子部42A2的掺杂离子浓度。
具体地，在本实施例中，所述第一导体子部41A1与所述第三有源层43的一侧连接，所述第三导体子部42A1与所述第三有源层43的另一侧连接；可以理解的是，本实施例通过设置掺杂离子浓度较小的所述第一导体子部41A1与所述第三有源层43的一侧连接、及掺杂离子浓度较小的所述第三导体子部42A1与所述第三有源层43的另一侧连接，从而可以避免所述第一导体部41和所述第二导体部42中的等离子气体向所述有源段43A的方向扩散，以达到维持所述薄膜晶体管的工作稳定性的效果。
本申请实施例还提供一种半导体器件的制作方法，请结合图6、图7、图10、图11A至图11G；其中，图10为本申请实施例所提供的半导体器件的制 作方法的流程图；图11A至图11G为图10中半导体器件制作的结构工艺流程图。
在本实施例中，所述垂直结构的半导体器件的制作方法包括以下步骤：
步骤S100：提供一绝缘基底10。
其中，当所述绝缘基底10为刚性衬底时，材料可以是金属或玻璃，当所述绝缘基底10为柔性衬底时，材料可以包括丙烯酸树脂、甲基丙烯酸树脂、聚异戊二烯、乙烯基树脂、环氧基树脂、聚氨酯基树脂、纤维素树脂、硅氧烷树脂、聚酰亚胺基树脂、聚酰胺基树脂中的至少一种。
步骤S200：在所述绝缘基底10上形成薄膜晶体管层40，所述薄膜晶体管层40包括层叠设置于所述绝缘基底10上的第一有源层41、绝缘层44以及第二有源层42，所述绝缘层44设置于所述第一有源层41和所述第二有源层42之间且覆盖所述第一有源层41；其中，所述绝缘层44形成有位于所述第一有源层41上的通孔44C，所述薄膜晶体管层40还包括至少部分位于所述通孔44C的侧壁44C1上的第三有源层43，所述第三有源层43的一侧与所述第一有源层41连接，所述第三有源层43的另一侧与所述第二有源层42连接。
具体地，在本实施例中，在所述步骤S200之前，所述半导体器件的制作方法还包括以下步骤：
步骤S110：在所述绝缘基底10上依次形成遮光层20和第一缓冲层30，如图11A所示；所述遮光层20的材料包括但不限于金属材料，所金属材料包括但不限于钼(Mo)、钛(Ti)、镍(Ni)其中的一种或多种合金；所述第一缓冲层30的材料包括但不限于单层氮化硅(Si 3N 4)、单层二氧化硅(SiO 2)、单层氮氧化硅(SiON x)，或是以上膜层的双层结构。
需要说明的是，在本实施例中，所述第一有源层41包括掺杂了离子的第一导体部41，所述第二有源层42包括掺杂了离子的第二导体部42，所述第三有源层43包括位于所述通孔44C的侧壁44C1上的有源段43A，所述第一导体部41在所述绝缘基底10上的正投影至少与部分所述第二导体部42在所述绝缘基底10上的正投影重叠，所述有源段43A的一侧与所述第一导体部41连接，所述有源段43A的另一侧与所述第二导体部42连接。
具体地，在本实施例中，所述步骤S200包括以下步骤：
步骤S201：在所述缓冲层上形成第一非晶硅层，并对所述第一非晶硅层进行结晶处理以形成第一多晶硅薄膜；具体的，在所述缓冲层上沉积一层非晶硅材料(a-si)以形成所述第一非晶硅层，对所述第一非晶硅层进行准分子激光退火(ELA)处理以形成所述第一多晶硅薄膜。
步骤S202：对所述第一多晶硅薄膜图案化处理形成第一多晶硅图案，具体地，利用一道光罩，采用正型光阻通过黄光、蚀刻制程对所述第一多晶硅薄膜进行图形化处理，从而在所述缓冲层上形成所述第一多晶硅图案。
步骤S203:对所述第一多晶硅图案进行离子注入，从而形成所述第一导体部41，如图11B所示；其中，所述第一多晶硅图案中掺入的离子为硼离子或者磷离子。
步骤S204：在所述第一导体部41上形成第一绝缘层44B，所述第二绝缘层44A覆盖所述第一导体部41，所述第一绝缘层44B的材料包括但不限于单层氮化硅(Si 3N 4)、单层二氧化硅(SiO 2)、单层氮氧化硅(SiON x)，或是以上膜层的双层结构。
步骤S205：在所述第二缓冲层44远离所述第一缓冲层30的一侧形成栅极45A，其中，所述栅极45A的厚度大于或等于0.05微米，且小于或等于0.2微米，所述栅极45A的材料为金属材料，所述金属材料包括但不限于钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)和钨(W)中的至少一种金属。
具体地，所述步骤S205包括：在所述第二缓冲层44远离所述第一缓冲层30的一侧形成第一金属层45，对所述第一金属层45图案化处理形成所述栅极45A，所述栅极45A上刻蚀有位于所述第一导体部41上方的开孔45B，所述开孔45B穿过所述栅极45A，如图11C所示。
步骤S206：在所述栅极45A远离所述第二缓冲层44的一侧形成第二绝缘层44A，其中，所述第二绝缘层44A覆盖所述栅极45A，从而对所述栅极45A起到阻隔水氧以及绝缘的作用，所述第二绝缘层44A的材料包括但不限于单层氮化硅(Si 3N 4)、单层二氧化硅(SiO 2)、单层氮氧化硅(SiON x)，或是以上膜层的双层结构。
步骤S207：通过一光罩制程，在所述第二绝缘层44A和所述第一绝缘层 44B上开设位于所述第一导体部41上的所述通孔44C，所述通孔44C与所述开孔45B对应设置，所述通孔44C的孔径小于所述开孔45B的孔径，从而使所述栅极45A围绕所述通孔44C的侧壁44C1上的第三有源层43设置，其中，所述通孔44C包括穿过所述第一绝缘层44B的第一通孔44C2、及穿过所述第二绝缘层44A的第二通孔44C3，所述第二通孔44C3的侧壁44C1与所述第一有源层41之间的夹角与所述第一通孔44C2的侧壁44C1与所述第一有源层41之间的夹角大小相等，如图11D所示。
步骤S208：在所述第二绝缘层44A远离所述第一绝缘层44B的一侧形成第三有源层43，至少部分所述第三有源层43位于所述通孔44C的侧壁44C1上。
具体地，所述第三有源层43位于通孔44C的侧壁44C1和底部44C4，且延伸至所述绝缘层44远离绝缘基底10的一侧；其中，所述第三有源层43包括相互连接的第一有源子部43A1和第二有源子部43A2，所述第一有源子部43A1位于所述绝缘层44远离绝缘基底10的一侧，所述第二有源子部43A2穿过所述通孔44C的侧壁44C1与所述第一导体部41连接，并且所述第一导体部41在所述绝缘基底10上的正投影覆盖所述第二有源子部43A2在所述绝缘基底10上的正投影，如图11E所示。
步骤S209：在所述第二绝缘层44A远离所述第一绝缘层44B的一侧形成阻挡层48，至少部分所述阻挡层48位于所述通孔44C内；具体地，所述阻挡层48包括位于所述绝缘层44远离所述绝缘基底10一侧的第一阻挡部48A、及位于所述通孔44C内的第二阻挡部48B，所述第一阻挡部48A靠近所述第二有源层42的一侧与所述绝缘层44靠近所述第二有源层42的一侧平齐，所述第二阻挡部48B靠近所述第二有源层42的一侧与所述绝缘层44靠近所述第二有源层42的一侧平齐，优选地，所述阻挡层48的材料为氧化硅(SiO X)，如图11F所示。
步骤S210：在所述第三有源层43远离所述第一导体部41的一侧形成第二非晶硅层，并对所述第二非晶硅层进行结晶处理以形成第二多晶硅薄膜；具体的，在所述第三有源层43上沉积一层非晶硅材料(a-si)以形成所述第二非晶硅层，对所述第二非晶硅层进行准分子激光退火(ELA)处理以形成所述第二 多晶硅薄膜。
步骤S211：对所述第三多晶硅薄膜图案化处理形成第二多晶硅图案，具体地，利用一道光罩，采用正型光阻通过黄光、蚀刻制程对所述第三多晶硅薄膜进行图形化处理，从而在所述第三有源层43上形成所述第二多晶硅图案。
步骤S212:对所述第二多晶硅图案进行离子注入，从而形成所述第二导体部42，其中，所述第一有源子部43A1与所述第二有源层42连接，所述第二导体部42在所述绝缘基底10上的正投影覆盖所述第一有源子部43A1在所述绝缘基底10上的正投影。
具体地，所述第一导体部41包括与所述第三有源层43连接的第一导体子部41A1、及与所述第一导体子部41A1连接的第二导体子部41A2，所述第一导体子部41A1在所述绝缘基底10上的正投影至少与部分所述第二导体部42在所述绝缘基底10上的正投影重叠，所述第二导体子部41A2在所述绝缘基底10上的正投影与所述第二导体部42在所述绝缘基底10上的正投影不交叠，如图11G所示。
步骤S213:在所述阻挡层48远离所述第二绝缘层44A的一侧形成层间绝缘层46，所述层间绝缘层46覆盖所述阻挡层48、所述第二导体部42以及所述第二栅极45A。
步骤S214:通过一光罩制程，在所述层间绝缘层46上开设第一过孔46A，在所述层间绝缘层46、所述阻挡层48、所述第二绝缘层44A以及所述第一绝缘层44B上开设第二过孔46B，其中，所述第一过孔46A穿过所述层间绝缘层46且位于所述第二导体部42上，所述第二过孔46B穿过所述层间绝缘层46、所述阻挡层48、所述第二绝缘层44A和所述第一绝缘层44B且位于所述第二导体子部41A2上。
步骤S215:在所述层间绝缘层46远离所述阻挡层48的一侧形成源极47A和漏极47B，所述源极47A通过所述第一过孔46A与所述第二导体部42连接，所述漏极47B穿过所述第二过孔46B与所述第二导体部42连接，如图6和图7所示。
本实施例提供一种电子器件，所述电子器件包括上述任一实施例中所述的半导体器件。
可以理解的是，所述半导体器件已经在上述实施例中进行了详细的说明，在此不在重复说明。
在具体应用时，所述电子器件可以为智能手机、平板电脑、笔记本电脑、智能手环、智能手表、智能眼镜、智能头盔、台式机电脑、智能电视或者数码相机等设备的显示屏，甚至可以应用在具有柔性显示屏的电子设备上。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种半导体器件，其中，包括：
    绝缘基底；
    薄膜晶体管层，设置于所述绝缘基底上，所述薄膜晶体管层包括层叠设置于所述绝缘基底上的第一有源层、绝缘层以及第二有源层，所述绝缘层设置于所述第一有源层和所述第二有源层之间且覆盖所述第一有源层；
    其中，所述绝缘层形成有位于所述第一有源层上的通孔，所述薄膜晶体管层还包括至少部分位于所述通孔的侧壁上的第三有源层，所述第三有源层的一侧与所述第一有源层连接，所述第三有源层的另一侧与所述第二有源层连接。
  2. 根据权利要求1所述的半导体器件，其中，所述薄膜晶体管层还包括位于所述绝缘层内的第一金属层，所述第一金属层与所述第一有源层绝缘设置，所述第一金属层至少位于所述通孔的一侧。
  3. 根据权利要求2所述的半导体器件，其中，所述第一金属层围绕所述通孔的侧壁上的第三有源层设置。
  4. 根据权利要求1所述的半导体器件，其中，所述第一有源层包括掺杂了离子的第一导体部，所述第二有源层包括掺杂了离子的第二导体部，所述第一导体部在所述绝缘基底上的正投影至少与部分所述第二导体部在所述绝缘基底上的正投影重叠；其中，所述第三有源层的一侧与所述第一导体部连接，所述第三有源层的另一侧与所述第二导体部连接。
  5. 根据权利要求4所述的半导体器件，其中，所述第二导体部的掺杂离子浓度小于所述第一导体部的掺杂离子浓度。
  6. 根据权利要求4所述的半导体器件，其中，所述薄膜晶体管层包括位于所述第二有源层远离所述绝缘层一侧的第二金属层，所述第二金属层包括与所述第一导体部连接的第一电极、及与所述第二导体部连接的第二电极；
    其中，所述第一导体部包括与所述第三有源层连接的第一导体子部、及与所述第一电极连接的第二导体子部，所述第二导体子部在所述绝缘基底上的正投影与所述第二导体部在所述绝缘基底上的正投影不交叠。
  7. 根据权利要求6所述的半导体器件，其中，所述第二导体部包括与所述第三有源层连接的第三导体子部、及与所述第二电极连接的第四导体子部， 其中，所述第一导体子部的掺杂离子浓度小于所述第二导体子部的掺杂离子浓度，所述第三导体子部的掺杂离子浓度小于所述第四导体子部的掺杂离子浓度。
  8. 根据权利要求7所述的半导体器件，其中，所述第一导体子部与所述第三有源层的一侧连接，所述第三导体子部与所述第三有源层的另一侧连接。
  9. 根据权利要求1所述的半导体器件，其中，所述薄膜晶体管层包括位于所述第一有源层和所述第二有源层之间的沟道，所述沟道的长度与所述通孔的深度满足以下关系式：
    Figure PCTCN2022131460-appb-100001
    其中，L表示所述沟道的长度，H表示所述通孔的深度，α表示所述通孔的侧壁上的第三有源层与所述通孔底部之间的夹角。
  10. 根据权利要求9所述的半导体器件，其中，所述通孔的侧壁上的第三有源层与所述通孔底部之间的夹角α大于90度，且小于或等于120度。
  11. 根据权利要求9所述的半导体器件，其中，在垂直于所述绝缘基底的方向上，所述沟道的长度大于或等于3000埃，且小于或等于10000埃。
  12. 根据权利要求1所述的半导体器件，其中，所述第三有源层包括相互连接的第一有源子部和第二有源子部，所述第一有源子部位于所述绝缘层远离绝缘基底的一侧，所述第一有源子部与所述第二有源层连接，所述第二有源子部穿过所述通孔的侧壁与所述第一有源层连接。
  13. 根据权利要求1所述的半导体器件，其中，所述薄膜晶体管层还包括位于所述绝缘层和所述第二有源层之间的阻挡层，至少部分所述阻挡层位于所述通孔内。
  14. 根据权利要求13所述的半导体器件，其中，所述阻挡层靠近所述第二有源层的一侧与所述绝缘层靠近所述第二有源层的一侧平齐。
  15. 根据权利要求13所述的半导体器件，其中，所述第三有源层位于通孔的侧壁和底部，且延伸至所述绝缘层远离绝缘基底的一侧。
  16. 根据权利要求1所述的半导体器件，其中，所述绝缘层包括设置于所述绝缘基底上的第一绝缘层和第二绝缘层，所述第一绝缘层位于所述第一有源层上且覆盖所述第一有源层，所述第二有源层覆盖所述第一有源层；
    其中，所述第一绝缘层形成有位于所述第一有源层上的第一通孔，所述第二绝缘层形成有位于所述第一有源层上且与所述第一通孔连通的第二通孔，所述第二通孔的侧壁与所述第一有源层之间的夹角与所述第一通孔的侧壁与所述第一有源层之间的夹角大小相等。
  17. 一种电子器件，其中，所述电子器件一半导体器件，所述半导体器件包括：
    绝缘基底；
    薄膜晶体管层，设置于所述绝缘基底上，所述薄膜晶体管层包括层叠设置于所述绝缘基底上的第一有源层、绝缘层以及第二有源层，所述绝缘层设置于所述第一有源层和所述第二有源层之间且覆盖所述第一有源层；
    其中，所述绝缘层形成有位于所述第一有源层上的通孔，所述薄膜晶体管层还包括至少部分位于所述通孔的侧壁上的第三有源层，所述第三有源层的一侧与所述第一有源层连接，所述第三有源层的另一侧与所述第二有源层连接。
  18. 根据权利要求17所述的电子器件，其中，所述薄膜晶体管层还包括位于所述绝缘层内的第一金属层，所述第一金属层与所述第一有源层绝缘设置，所述第一金属层至少位于所述通孔的一侧。
  19. 根据权利要求17所述的电子器件，其中，所述第一有源层包括掺杂了离子的第一导体部，所述第二有源层包括掺杂了离子的第二导体部，所述第一导体部在所述绝缘基底上的正投影至少与部分所述第二导体部在所述绝缘基底上的正投影重叠；其中，所述第三有源层的一侧与所述第一导体部连接，所述第三有源层的另一侧与所述第二导体部连接。
  20. 根据权利要求17所述的电子器件，其中，所述第三有源层包括相互连接的第一有源子部和第二有源子部，所述第一有源子部位于所述绝缘层远离绝缘基底的一侧，所述第一有源子部与所述第二有源层连接，所述第二有源子部穿过所述通孔的侧壁与所述第一有源层连接。
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