WO2024045296A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2024045296A1
WO2024045296A1 PCT/CN2022/127029 CN2022127029W WO2024045296A1 WO 2024045296 A1 WO2024045296 A1 WO 2024045296A1 CN 2022127029 W CN2022127029 W CN 2022127029W WO 2024045296 A1 WO2024045296 A1 WO 2024045296A1
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layer
trench isolation
shallow trench
isolation structure
insulating layer
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PCT/CN2022/127029
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English (en)
French (fr)
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王同辉
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors

Definitions

  • the present disclosure relates to the field of integrated circuits, and in particular, to a semiconductor structure and a preparation method thereof.
  • the lattice constant of Si is 0.543nm
  • the lattice constant of Ge is 0.567nm.
  • the difference between the two is 4.17%. Therefore, the introduction of Ge element into pure Si will form a SiGe material with stress.
  • the bandgap width of the silicon germanium (SiGe) material can change, making it easy to form heterostructures; at the same time, the electron and hole mobility of the silicon germanium (SiGe) material are both higher than that of Si. ) material as a channel helps improve the hole mobility of the device channel.
  • the silicon germanium (SiGe) layer formed using silicon germanium (SiGe) material has structural defects and cannot meet the requirements.
  • the technical problem to be solved by this disclosure is to provide a semiconductor structure and a preparation method thereof, which can overcome the structural defects of the channel layer and form a channel layer with uniform thickness.
  • Embodiments of the present disclosure provide a method for preparing a semiconductor structure, including: providing a substrate that includes a shallow trench isolation structure and an active area defined by the shallow trench isolation structure; forming a Channel layer; removing the channel layer in the interface area between the shallow trench isolation structure and the active area to expose part of the active area; forming an insulating layer on the exposed surface of the active area.
  • the method of forming a channel layer on the surface of the active area includes: depositing silicon germanium material to form a silicon germanium material layer on the surface of the shallow trench isolation structure and the surface of the active area; etching The silicon germanium material layer is etched until the surface of the shallow trench isolation structure is exposed.
  • the thickness of the silicon germanium material layer deposited on the surface of the shallow trench isolation structure is smaller than the thickness of the silicon germanium material layer deposited on the surface of the active region.
  • the silicon germanium material layer on the surface of the active area is thinned.
  • the steps of depositing the silicon germanium material and etching the silicon germanium material layer are cyclically performed until the silicon germanium material layer with a set thickness is formed on the surface of the active area. There is no silicon germanium material layer on the surface of the trench isolation structure.
  • a method for removing the channel layer in the interface area between the shallow trench isolation structure and the active region includes: forming a mask on the surface of the shallow trench isolation structure and the channel layer layer; patterning the mask layer to form a first window, the first window exposing the channel layer in the interface area; using the mask layer as a mask to remove the channel layer.
  • the step of forming an insulating layer on the exposed surface of the active region includes: using the first window as a process window, forming the insulating layer on the exposed surface of the active region; thinning the The mask layer and the insulating layer are exposed until the channel layer, and the remaining mask layer on the surface of the shallow trench isolation structure is retained as a supplementary layer.
  • the step of removing the channel layer in the interface area between the shallow trench isolation structure and the active region includes: over-etching the active region to form a groove; and forming the insulating layer In the step, the insulating layer is filled in the groove.
  • the surface of the insulating layer is lower than the surface of the channel layer
  • the method further includes the following steps: forming a supplementary layer, the supplementary layer covering the shallow trench isolation structure and the surface of the insulating layer , and be flush with the surface of the channel layer.
  • Embodiments of the present disclosure also provide a semiconductor structure, which includes: a substrate including a shallow trench isolation structure and an active region defined by the shallow trench isolation structure; a channel layer disposed on the active a surface in the middle of the region; an insulating layer, disposed between the shallow trench isolation structure and the channel layer, and covering the surface of the periphery of the active region.
  • the bottom surface of the insulating layer is lower than the top surface of the active area, the top surface of the insulating layer is flush with the top surface of the shallow trench isolation structure, and the insulating layer The top surface is lower than the top surface of the channel layer.
  • a supplementary layer is further included, the supplementary layer covering the shallow trench isolation structure and the top surface of the insulating layer.
  • the bottom surface of the insulating layer is lower than the top surface of the active region, and the top surface of the insulating layer is flush with the top surface of the channel layer.
  • a supplementary layer is further included, the supplementary layer covers the top surface of the shallow trench isolation structure, and the top surface of the supplementary layer is flush with the top surface of the insulating layer.
  • the material of the insulating layer is the same as the material of the shallow trench isolation structure, and the material of the supplementary layer is different from the material of the insulating layer.
  • the preparation method of the semiconductor structure provided by the embodiment of the present disclosure removes the thin edge portion of the channel layer after forming the channel layer, and fills it with the insulating layer to form a channel layer with uniform thickness and high quality, which greatly improves the efficiency of the semiconductor structure.
  • the performance expands the scope of application of semiconductor structures using silicon germanium materials as channels.
  • Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 3A to 3P are schematic diagrams of a semiconductor structure formed by the main steps of the preparation method provided by an embodiment of the present disclosure
  • 4A and 4B are schematic diagrams of a semiconductor structure formed by the main steps of a preparation method provided by another embodiment of the present disclosure.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, DRAM.
  • the silicon germanium layer formed of silicon germanium material as the channel layer has structural defects.
  • a silicon germanium layer 10 is formed on the active area (Active Area, AA) 11.
  • the silicon germanium layer 10 serves as a channel layer and is located between the active area 11 and the shallow trench isolation structure (Shallow The thickness of the silicon germanium layer 10 at the junction of Trench Isolation (STI) 12 (the area circled by the dotted box E in the figure) is smaller than the thickness of the silicon germanium layer 10 located in the center of the active area 11, even between the active area 11 and the shallow trench There is no silicon germanium layer 10 at the junction of the isolation structure 12, which has a great impact on the performance of the semiconductor structure.
  • STI Trench Isolation
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which can improve the structure of the channel layer, obtain a high-quality channel layer, and thereby improve the performance of the semiconductor structure.
  • FIG. 2 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • the preparation method includes: step S20, providing a substrate, the substrate including a shallow trench isolation structure and a shallow trench isolation structure. The active area defined by the trench isolation structure; step S21, form a channel layer on the surface of the active area; step S22, remove the channel layer in the interface area between the shallow trench isolation structure and the active area, Part of the active area is exposed; step S23, forming an insulating layer on the exposed surface of the active area.
  • 3A to 3P are schematic diagrams of semiconductor structures formed by the main steps of the preparation method provided by embodiments of the present disclosure.
  • FIG. 3A is a top view
  • FIG. 3B is a cross-sectional view along line A-A in FIG. 3A.
  • a substrate 300 is provided.
  • the substrate 300 includes a shallow trench isolation structure 301 and a Trench isolation structure 301 defines active area 302 .
  • the base 300 includes a substrate 303 in which the active region 302 and the shallow trench isolation structure 301 are formed.
  • the substrate 303 may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (for example, silicon (Si) substrate, germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, nitride Gallium (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductors known in the art Material.
  • This embodiment is explained by taking the substrate 303 as a silicon substrate as an example.
  • embodiments of the present disclosure provide a method of forming the substrate.
  • the method includes: using photolithography and etching processes to form shallow trenches in the substrate 303, the shallow trenches extending a set distance toward the inside of the substrate 303, and the shallow trenches connecting the substrate 303 and the substrate 303.
  • the bottom 303 is isolated into a plurality of active areas 302 arranged in an array; the shallow trenches are filled with dielectric to form the shallow trench isolation structure 301.
  • the shallow trench isolation structure 301 combines the plurality of active areas 302.
  • the source area 302 is separated.
  • chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic layer deposition, ALD) and other processes can be used to deposit an oxide layer, a nitride layer, or both in the shallow trench.
  • Composite layer For example, in this embodiment, a chemical vapor deposition process is used to deposit silicon oxide into a shallow trench, and the silicon nitride fills the shallow trench to form a shallow trench isolation structure 301 to isolate the active region 302 . In this embodiment, only one shallow trench isolation region 301 and one active region 302 are schematically illustrated.
  • FIG. 3E is a top view and FIG. 3F is a cross-sectional view along line A-A in FIG. 3E.
  • a channel layer 310 is formed on the surface of the active region 302.
  • the channel layer 310 covers the surface of the active region 302 but does not cover the surface of the shallow trench isolation structure 301 .
  • a silicon germanium layer serves as the channel layer 310 .
  • the electron and hole mobility of the silicon germanium material are both higher than that of silicon.
  • Using the silicon germanium layer as the channel layer helps to improve the hole mobility of the semiconductor structure channel, improves the electrical performance of the semiconductor structure, and expands the application scope of the semiconductor structure. .
  • the embodiment of the present disclosure provides a method of forming the channel layer 310 on the surface of the active area 302.
  • the method includes the following steps:
  • FIG. 3C is a top view
  • FIG. 3D is a cross-sectional view along line A-A in FIG. 3C.
  • Silicon germanium material is deposited to cover the surface of the shallow trench isolation structure 301 and the active area.
  • a silicon germanium material layer 390 is formed on the surface of 302.
  • the silicon germanium material layer 390 not only covers the surface of the active region 302 but also covers the surface of the shallow trench isolation structure 301 .
  • the material composition of the shallow trench isolation structure 301 is different from that of the active region 302 , for example, the material of the shallow trench isolation structure 301 is silicon oxide, and the active region 302 The material is silicon, and the deposition rate of silicon germanium material on the surface of the shallow trench isolation structure 301 is lower than the deposition rate on the surface of the active area 302, so that the silicon germanium material formed on the surface of the shallow trench isolation structure 301
  • the thickness of the layer 390 is smaller than the thickness of the silicon germanium material layer 390 formed on the surface of the active region 302 , that is, the silicon germanium material layer 390 formed on the surface of the shallow trench isolation structure 301 is different from the thickness of the silicon germanium material layer 390 formed on the surface of the active region 302 .
  • the silicon germanium material layer 390 formed on the surface of 302 has a height difference.
  • etching the silicon germanium material layer 390 until the surface of the shallow trench isolation structure 301 is exposed.
  • a dry etching process may be used to etch the silicon germanium material layer 390, and the etching substance includes but is not limited to HCL etching gas.
  • the silicon germanium material layer 390 on the surface of the shallow trench isolation structure 301 is completely removed, and because the thickness of the silicon germanium material layer 390 on the surface of the shallow trench isolation structure 301 is smaller than the active area 302
  • the silicon germanium material layer 390 on the surface of the active area 302 is only partially removed. That is, the silicon germanium material layer 390 on the surface of the active area 302 is only thinned but not completely removed, and a part of the silicon germanium material layer 390 remains on the surface of the active area 301 .
  • the steps of depositing the silicon germanium material and etching the silicon germanium material layer can be cyclically performed, that is, the deposition-etching process is cycled until a predetermined structure is formed on the surface of the active region 301 There is no silicon germanium material layer 390 on the surface of the shallow trench isolation structure 301, wherein the silicon germanium material layer 390 with a set thickness is formed on the surface of the active area 301.
  • the germanium material layer 390 serves as the channel layer 310 .
  • the formation of the silicon germanium material layer 390 is a dynamic growth process. During the growth process of the silicon germanium material layer 390, HCL etching gas is introduced, so that on the interface of the shallow trench isolation structure 301 The formed silicon germanium material layer 390 is dynamically removed, and finally the silicon germanium material layer 390 with a set thickness is only formed on the silicon interface of the active region 302 .
  • the exposed surface of the shallow trench isolation structure 301 and the Silicon germanium material is continued to be deposited on the surface of the thinned silicon germanium material layer 390 to form a new silicon germanium material layer; an etching process is then performed on the new silicon germanium material layer until the surface of the shallow trench isolation structure 301 is exposed again ; Perform the deposition-etching process in multiple cycles until the silicon germanium material layer 390 with a set thickness is formed on the surface of the active area 302.
  • the silicon germanium material layer 390 is composed of a stack of silicon germanium material layers remaining after performing an etching process on a new silicon germanium material layer in each cycle, and in each process of depositing silicon germanium material,
  • the thickness of the new silicon germanium material layer deposited on the surface of the shallow trench isolation structure 301 is smaller than the thickness of the new silicon germanium material layer deposited on the surface of the remaining silicon germanium material layer on the surface of the active area 301, thereby forming a layer on the surface of the active area 301.
  • the silicon germanium material layer 390 having a set thickness is formed on the surface of the active area 301 , and there is no semiconductor structure of the silicon germanium material layer 390 on the surface of the shallow trench isolation structure 301 .
  • the thickness of the silicon germanium material layer 390 on the surface of the shallow trench isolation structure 301 is less than the thickness of the silicon germanium material layer 390 on the surface of the active area 302, then in the shallow trench At the junction of the trench isolation structure 301 and the active area 302 (the area indicated by arrow D in Figure 3D), the sidewalls of the silicon germanium material layer 390 located on the surface of the active area 302 are partially exposed, please refer to Figure 3C and Figure 3D.
  • the etching gas will not only etch the silicon germanium material layer 390 downward, but also etch the silicon germanium material layer 390 laterally.
  • the silicon germanium material layer 390 has exposed sidewalls, while in other areas (such as the central area) of the active region 302, the silicon germanium material layer 390 does not have exposed sidewalls, which will only be etched downwards. This causes the etching degree of the silicon germanium material layer 390 at the interface between the shallow trench isolation structure 301 and the active region 302 to be greater than the etching degree of the silicon germanium material layer 390 in other areas of the active region 302 , resulting in The edge thickness of the finally formed channel layer 310 is smaller than the center thickness (the thickness of the channel layer 310 in the area circled by the dotted box E in Figure 3F is smaller than the thickness of other areas of the channel layer 310), which will have a negative impact on the performance of the semiconductor structure.
  • the thickness difference between the edge and the center of the channel layer 310 becomes more and more obvious, and there is even no channel layer at the interface between the shallow trench isolation structure 301 and the active area 302 310, which has a greater impact on the performance of semiconductor structures.
  • a mask layer may also be used to block the silicon germanium material layer 390 on the surface of the active area 302 before performing the step of etching the silicon germanium material layer 390 .
  • the step of forming the germanium material layer 390 due to the shielding of the mask layer, only the silicon germanium material layer 390 on the surface of the shallow trench isolation structure 301 is removed, and the silicon germanium material layer 390 on the surface of the active area 302 is not removed. Be thinned.
  • the sidewalls of the silicon germanium material layer 390 on the surface of the active area 302 are still exposed to the etching environment, and the etching gas still exists to laterally etch the exposed side walls of the silicon germanium material layer 390 situation, while in other areas of the active area 302 (such as the central area), protected by the mask layer, the silicon germanium material layer 390 has not been etched, which also results in the final formation of the channel layer 310
  • the edge thickness is less than the center thickness.
  • FIG. 3K is a top view
  • FIG. 3L is a cross-sectional view along line A-A in FIG.
  • the channel layer 310 exposes part of the active region 302.
  • the junction between the shallow trench isolation structure 301 and the active region 302 (the position indicated by arrow D in FIG. 3D) and the trench A gap C is formed between edges of the track layer 310 .
  • the boundary area between the shallow trench isolation structure 301 and the active area 302 extends from the boundary between the shallow trench isolation structure 301 and the active area 302 toward the active area 302
  • the interface area between the shallow trench isolation structure 301 and the active area 302 at least covers the edge area of the channel layer 310, so that areas with different edge thicknesses of the channel layer 310 can be completely removed. , improving the uniformity of the thickness of the channel layer 310.
  • the edge area may refer to an area where the edge thickness of the channel layer 310 is smaller than the center thickness of the channel layer 310 .
  • the remaining edge thickness of the channel layer 310 is consistent with the center thickness, which improves the performance of the semiconductor structure.
  • embodiments of the present disclosure provide a method for removing the channel layer 310 in the interface area between the shallow trench isolation structure 301 and the active region 302 .
  • the methods include:
  • FIG. 3G is a top view
  • FIG. 3H is a cross-sectional view along line A-A in FIG. 3G.
  • a mask layer 380 is formed on the surface of the shallow trench isolation structure 301 and the channel layer 310. . That is, in this step, the mask layer 380 covers the surface of the shallow trench isolation structure 301 and the channel layer 310 . If the active area 302 is not covered by the channel layer 310 at the interface between the shallow trench isolation structure 301 and the active area 302, then in this step, the mask layer 380 is also Cover the exposed surface of the active area 302 .
  • the mask layer 380 may be a hard mask layer composed of a nitride layer, or may be a hard mask composed of a composite layer of oxide and nitride.
  • FIG. 3I is a top view
  • FIG. 3J is a cross-sectional view along line A-A in FIG. 3I.
  • the mask layer 380 is patterned to form a first window 381, and the first window 381 is exposed.
  • the channel layer 310 in the interface area between the shallow trench isolation structure 301 and the active region 302 is exposed.
  • the boundary area between the shallow trench isolation structure 301 and the active area 302 corresponds to the first window 381, that is, the boundary area between the shallow trench isolation structure 301 and the active area 302 Overlaps with the orthographic projection of the first window 381 on the substrate 300; in other embodiments, the width of the first window 381 is greater than the boundary between the shallow trench isolation structure 301 and the active area 302
  • the width of the area, that is, the orthographic projection of the first window 381 on the substrate 300 covers the orthographic projection of the boundary area between the shallow trench isolation structure 301 and the active region 302 on the substrate 300, and the The orthographic projection area of the first window 381 on the substrate 300 is larger than the orthographic projection area of the interface between the shallow trench isolation structure 301 and the active region 302 on the substrate 300, thereby ensuring that the channel Areas with uneven thickness of layer 310 can be completely removed to improve the uniformity of the thickness of channel layer 310 .
  • a patterned photoresist layer can be formed on the surface of the mask layer 380, and the photoresist layer is used to define the position of the first window 381; and then the photoresist layer is Mask, use an etching process to etch the mask layer 380 to form the first window 381.
  • a bottom anti-reflection coating may also be formed on the surface of the mask layer 380, and the photoresist layer may be formed on the surface of the bottom anti-reflection coating, so as to Reduce light reflection during photolithography.
  • an etching process such as a dry etching process, is used along the first window 381 to remove the shallow trench isolation structure 301 and The channel layer 310 in the interface area of the active area 302 exposes the active area 302 covered by the channel layer 310 .
  • the etching gas in the dry etching process includes but is not limited to HCL.
  • the active region 302 when the channel layer 310 is removed, the active region 302 is over-etched to form a groove 304.
  • the top surface of the active region 302 ie, the bottom surface of the groove 304
  • the active area 302 in the interface area between the shallow trench isolation structure 301 and the active area 302 is also partially removed to form the groove 304. This ensures that the channel layer 310 is completely removed and prevents the channel layer 310 from remaining.
  • the active region 302 may not be over-etched, and the top surface of the active region 302 is flush with the top surface of the shallow trench isolation structure 301. and lower than the top surface of the channel layer 310 .
  • FIG. 3O is a top view and FIG. 3P is a cross-sectional view along line A-A in FIG. 3O.
  • An insulating layer 320 is formed on the exposed surface of the active region 302.
  • the insulating layer 320 is formed on the exposed surface of the active region 302 .
  • FIG. 3M and FIG. 3N are a top view
  • FIG. 3N is a cross-sectional view along line A-A in FIG. 3M.
  • Insulating material is deposited, and the insulating material fills the groove 304 and the third groove.
  • a window 381 covers the surface of the mask layer 380 , and the insulating material serves as the insulating layer 320 .
  • the insulating material may not cover the surface of the mask layer 380 , but only fills the groove 304 and the first window 381 .
  • the insulating material may be the same as the dielectric material of the shallow trench isolation structure 301.
  • the insulating material and the dielectric material of the shallow trench isolation structure 301 are both silicon oxide.
  • the insulating material may be different from the dielectric material of the shallow trench isolation structure 301.
  • the dielectric material of the shallow trench isolation structure 301 may be silicon oxide, and the insulating material may be nitride. silicon.
  • the mask layer 380 and the insulating layer 320 are thinned until the channel layer 310 is exposed.
  • the remaining mask layer 380 on the surface of the shallow trench isolation structure 301 is Reserved as supplementary layer 360.
  • CMP chemical mechanical polishing
  • the remaining mask layer 380 covers the surface of the shallow trench isolation structure 301 , and as the supplementary layer 360 , the remaining insulating layer 320 covers the surface of the active area 302 .
  • the material of the supplementary layer 360 is different from the material of the insulating layer 320 .
  • the material of the supplementary layer 360 is a hard mask material
  • the material of the insulating layer 320 is silicon oxide.
  • the top surface of the channel layer 310 is higher than the top surface of the shallow trench isolation structure 301, then the top surface of the insulating layer 320 formed in this step or It is flush with the top surface of the channel layer 310 or lower than the top surface of the channel layer 310 .
  • the top surface of the insulating layer 320 may be flush with the top surface of the channel layer 310 , that is, the top surface of the insulating layer 320 is higher than that of the shallow trench isolation structure 301 .
  • the top surface is flush with the top surface of the channel layer 310 .
  • the supplementary layer 360 is used to fill the surface of the shallow trench isolation structure 301 , and the top surface of the supplementary layer 360 is flush with the top surface of the channel layer 310 . That is, the top surface of the supplementary layer 360, the top surface of the insulating layer 320 and the top surface of the channel layer 310 are flush, so that the formed semiconductor structure has a flat surface.
  • the insulating layer 320 is thinned, such as etching back the insulating layer 320, so that the top surface of the insulating layer 320 is lower than the channel layer. 310 , and then remove the mask layer 380 to expose the shallow trench isolation structure 301 and the channel layer 310 .
  • FIGS. 4A and 4B where FIG. 4A is a top view and FIG. 4B is a cross-sectional view along line A-A in FIG. 4A , the top surface of the insulating layer 320 is planar with the top surface of the shallow trench isolation structure 301 . level and lower than the top surface of the channel layer 310 .
  • a step of forming the supplementary layer 360 is also included.
  • the supplementary layer 360 covers the top surface of the shallow trench isolation structure 301 and the insulating layer 320, and is flush with the surface of the channel layer 310, so that the formed semiconductor structure has a flat surface.
  • the supplementary layer 360 is also used to protect the sidewalls of the channel layer 310 to prevent them from being damaged in subsequent processes.
  • the material of the supplementary layer 360 may be the same as the material of the insulating layer 320 , for example, both materials are silicon oxide.
  • the step of forming the supplementary layer 360 includes: first forming a covering material covering the shallow trench isolation structure 301 , the insulating layer 320 and the top surface of the channel layer 310 ; Thin the covering material until the top surface of the channel layer 310 is exposed, and the remaining covering material serves as the supplementary layer 360 .
  • the surface of the insulating layer 320 is flush with the surface of the shallow trench isolation structure 301, and the supplementary layer 360 can also be used to fill the shallow trench isolation structure 301 and the insulation layer.
  • the top surface of the supplementary layer 360 is flush with the top surface of the channel layer 310 .
  • the supplementary layer 360 can be formed by the same method as described above, and will not be described again here.
  • the preparation method of the semiconductor structure provided by the embodiment of the present disclosure removes the thin edge portion of the channel layer after forming the channel layer, and fills it with the insulating layer to form a channel layer with uniform thickness and high quality, which greatly improves the efficiency of the semiconductor structure.
  • the performance expands the scope of application of semiconductor structures using silicon germanium materials as channels.
  • Embodiments of the present disclosure also provide a semiconductor structure formed using the above preparation method. Please refer to FIGS. 3A to 3P , which are schematic structural diagrams of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes a substrate 300 , a channel layer 310 , and an insulating layer 320 .
  • the substrate 300 includes a shallow trench isolation structure 301 and an active region 302 defined by the shallow trench isolation structure 301 .
  • the base 300 includes a substrate 303, and the active region 302 and the shallow trench isolation structure 301 are disposed in the substrate 303.
  • the shallow trench isolation structure 301 extends a set distance toward the inside of the substrate 303.
  • the shallow trench isolation structure 301 isolates the substrate 303 into a plurality of active areas 302 arranged in an array. In this implementation In the example, only a shallow trench isolation region 301 and an active region 302 are schematically illustrated.
  • the channel layer 310 is disposed on the surface of the middle part of the active area 302 . That is to say, the channel layer 310 does not cover the active area 302, and the periphery of the active area 302 is not covered by the channel layer 310. That is, the shallow trench isolation structure 301 and There is a gap C (please refer to FIG. 3L) between the junction of the active area 302 (the position indicated by arrow D in FIG. 3D) and the edge of the channel layer 310. The gap C is the channel The edge of the channel layer 310 is removed and formed. Since the channel layer 310 is partially removed during the preparation process, the thickness of the edge region of the channel layer 310 of the semiconductor structure is substantially consistent with the thickness of the central region.
  • the insulating layer 320 is disposed between the shallow trench isolation structure 301 and the channel layer 310, and covers the peripheral surface of the active area 302, that is, the insulating layer 320 covers the surface corresponding to the interval C.
  • the insulating layer 320 does not cover the top surface of the active region 302 and the sidewalls of the channel layer 310 . That is to say, the insulating layer 320 fills the gap C, thereby avoiding a gap between the shallow trench isolation structure 301 and the channel layer 310 .
  • the active area 302 has a groove 304, and the bottom surface of the groove 304 is lower than the top surface of the shallow trench isolation structure 301.
  • the insulating layer 320 is filled in the groove 304 . That is to say, in this embodiment, the bottom surface of the insulating layer 320 is lower than the top surface of the active region 302 , and the top surface of the insulating layer 320 is flush with the top surface of the channel layer 310 , the top surface of the shallow trench isolation structure 301 is lower than the top surface of the channel layer 310 .
  • the semiconductor structure also includes a supplementary layer 360.
  • the supplementary layer 360 covers the surface of the shallow trench isolation structure 301.
  • the surface of the supplementary layer 360 is flush with the surface of the channel layer 310, that is, the supplementary layer 360
  • the top surfaces of the insulating layer 320 and the channel layer 310 are flush with each other, so that the semiconductor structure has a flat surface.
  • the material of the insulating layer 320 and the shallow trench isolation structure 301 are the same, for example, both are silicon oxide; the material of the supplementary layer 360 is the same as the material of the insulating layer 320 Differently, for example, the material of the supplementary layer 360 is a hard mask material, such as silicon nitride, and the material of the insulating layer 320 is silicon oxide. It can be understood that in other embodiments, the material of the supplementary layer 360 can also be the same as the material of the insulating layer 320 and the shallow trench isolation structure 301, for example, all three are silicon oxide.
  • the supplementary layer 360 only covers the surface of the shallow trench isolation structure 301 .
  • the bottom surface of the insulating layer 320 is lower than the top surface of the active region 302
  • the top surface of the insulating layer 320 is lower than the top surface of the active region 302 .
  • the supplementary layer 360 not only covers the surface of the shallow trench isolation structure 301, but also covers the insulation
  • the surface of the layer 320, and the surface of the supplementary layer 360 is flush with the surface of the channel layer 310, is used to form a flat device surface, and is also used to protect the sidewalls of the channel layer 310 to avoid subsequent processes. suffered damage.
  • the bottom surface of the insulating layer 320 is lower than the top surface of the active region 302 , and the top surface of the insulating layer 320 is higher than the top surface of the shallow trench isolation structure 301 . surface, and is lower than the top surface of the channel layer 310, then the supplementary layer 360 covers the shallow trench isolation structure 301 and the surface of the insulating layer 320, and is flush with the surface of the channel layer 310, to form a flat device surface.
  • the bottom surface of the insulating layer 320 is flush with the top surface of the active region 302 and flush with the top surface of the shallow trench isolation structure 301 .
  • the top surface of the layer 320 is flush with the top surface of the channel layer 310, then the supplementary layer 360 covers the top surface of the shallow trench isolation structure 301 and is flush with the surface of the channel layer 310, so that Create a flat device surface.
  • the bottom surface of the insulating layer 320 is flush with the top surface of the active region 302 and flush with the top surface of the shallow trench isolation structure 301 .
  • the top surface of the layer 320 is lower than the top surface of the channel layer 310, then the supplementary layer 360 covers the shallow trench isolation structure 301 and the top surface of the insulating layer 320, and is in contact with the channel layer. 310 surface is flush to form a flat device surface.
  • the thickness of the edge region of the channel layer 310 of the semiconductor structure is basically consistent with the thickness of the central region.
  • the removed area of the channel layer 310 is filled with the insulating layer 320 to further prevent the sidewalls of the channel layer 310 from being exposed and to form a channel layer 310 with uniform thickness and high quality, which greatly improves the performance of the semiconductor structure and expands the use of silicon.
  • the germanium material is suitable for channel semiconductor structures.

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Abstract

本公开提供一种半导体结构及其制备方法，制备方法包括：提供基底，所述基底包括浅沟槽隔离结构及被所述浅沟槽隔离结构限定的有源区；在所述有源区表面形成沟道层；去除所述浅沟槽隔离结构与所述有源区交界区域的所述沟道层，暴露出部分所述有源区；在所述有源区暴露的表面形成绝缘层。本公开实施例提供的半导体结构的制备方法在形成沟道层后去除沟道层厚度较薄的边缘部分，并利用绝缘层进行填充，形成厚度均一高质量的沟道层，大大提高了半导体结构的性能，扩大了以硅锗材料为沟道的半导体结构的适用范围。

Description

半导体结构及其制备方法
相关申请引用说明
本申请要求于2022年08月30日递交的中国专利申请号202211046045.3、申请名为“半导体结构及其制备方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及集成电路领域，尤其涉及一种半导体结构及其制备方法。
背景技术
随着新兴技术的崛起，迫切的需要一种低耗能、体积小、高效率能满足电池供电的芯片技术，采用SiGe材料作为沟道(channel)，可助力新兴技术力量崛起。
Si的晶格常数为0.543nm，Ge的晶格常数为0.567nm，二者相差4.17％，因此，纯Si中引入Ge元素会形成带有应力的SiGe材料。硅锗(SiGe)材料随Ge元素的密度变化，禁带宽度可以改变，易于形成异质结构；同时，硅锗(SiGe)材料的电子和空穴迁移率均比Si高，采用硅锗(SiGe)材料作为沟道有助于提高器件沟道的空穴迁移率。
但是，在一些半导体工艺中，采用硅锗(SiGe)材料形成的硅锗(SiGe)层存在结构缺陷，无法满足要求。
发明内容
本公开所要解决的技术问题是，提供一种半导体结构及其制备方法，其能够克服沟道层的结构缺陷，形成厚度均一的沟道层。
本公开实施例提供一种半导体结构的制备方法，包括：提供基底，所述基底包括浅沟槽隔离结构及被所述浅沟槽隔离结构限定的有源区；在所述有源区表面形成沟道层；去除所述浅沟槽隔离结构与所述有源区交界区域的所述沟道层，暴露出部分所述有源区；在所述有源区暴露的表面形成绝缘层。
在一实施例中，在所述有源区表面形成沟道层的方法包括：沉积硅锗材料，以在所述浅沟槽隔离结构表面及所述有源区表面形成硅锗材料层；刻蚀所述硅锗材料层，直至所述浅沟槽隔离结构表面被暴露。
在一实施例中，在沉积硅锗材料步骤中，在所述浅沟槽隔离结构表面沉积的硅锗材料层厚度小于在所述有源区表面沉积的硅锗材料层厚度。
在一实施例中，在刻蚀所述硅锗材料层的步骤中，所述有源区表面的硅锗材料层被减薄。
在一实施例中，循环沉积所述硅锗材料及刻蚀所述硅锗材料层的步骤，直至在所述有 源区表面形成具有设定厚度的所述硅锗材料层，在所述浅沟槽隔离结构的表面无所述硅锗材料层。
在一实施例中，去除所述浅沟槽隔离结构与所述有源区交界区域的所述沟道层的方法包括：在所述浅沟槽隔离结构及所述沟道层表面形成掩膜层；图案化所述掩膜层，形成第一窗口，所述第一窗口暴露出所述交界区域的所述沟道层；以所述掩膜层作为掩膜去除所述沟道层。
在一实施例中，在所述有源区暴露的表面形成绝缘层的步骤包括：以所述第一窗口作为工艺窗口，在所述有源区暴露的表面形成所述绝缘层；减薄所述掩膜层及所述绝缘层，至所述沟道层被暴露，所述浅沟槽隔离结构表面剩余的掩膜层被保留作为补充层。
在一实施例中，去除所述浅沟槽隔离结构与所述有源区交界区域的所述沟道层的步骤包括：过刻蚀所述有源区形成凹槽；在形成所述绝缘层的步骤中，所述绝缘层填充在所述凹槽内。
在一实施例中，所述绝缘层表面低于所述沟道层表面，所述方法还包括如下步骤：形成补充层，所述补充层覆盖所述浅沟槽隔离结构及所述绝缘层表面，并与所述沟道层表面平齐。
本公开实施例还提供一种半导体结构，其包括：基底，所述基底包括浅沟槽隔离结构及被所述浅沟槽隔离结构限定的有源区；沟道层，设置在所述有源区中部的表面；绝缘层，设置在所述浅沟槽隔离结构与所述沟道层之间，且覆盖所述有源区外围的表面。
在一实施例中，所述绝缘层的底表面低于所述有源区的顶表面，所述绝缘层的顶表面与所述浅沟槽隔离结构的顶表面平齐，所述绝缘层的顶表面低于所述沟道层的顶表面。
在一实施例中，还包括补充层，所述补充层覆盖所述浅沟槽隔离结构及所述绝缘层的顶表面。
在一实施例中，所述绝缘层的底表面低于所述有源区的顶表面，所述绝缘层的顶表面与所述沟道层的顶表面平齐。
在一实施例中，还包括补充层，所述补充层覆盖所述浅沟槽隔离结构的顶表面，所述补充层的顶表面与所述绝缘层的顶表面平齐。
在一实施例中，所述绝缘层的材料与所述浅沟槽隔离结构的材料相同，所述补充层的材料与所述绝缘层的材料不同。
本公开实施例提供的半导体结构的制备方法在形成沟道层后去除沟道层厚度较薄的边缘部分，并利用绝缘层进行填充，形成厚度均一高质量的沟道层，大大提高了半导体结构 的性能，扩大了以硅锗材料为沟道的半导体结构的适用范围。
附图说明
图1是本公开一实施例提供的半导体结构的结构示意图；
图2是本公开一实施例提供的半导体结构的制备方法的步骤示意图；
图3A～图3P是本公开一实施例提供的制备方法的主要步骤形成的半导体结构示意图；
图4A及图4B是本公开另一实施例提供的制备方法的主要步骤形成的半导体结构示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其制备方法的具体实施方式做详细说明。本具体实施方式中所述的半导体结构可以是但不限于DRAM。
在一些半导体工艺中，采用硅锗材料形成的硅锗层作为沟道层存在结构缺陷。例如，请参阅图1，在有源区(Active Area，AA)11上形成硅锗层10，所述硅锗层10作为沟道层，而位于有源区11与浅沟槽隔离结构(Shallow Trench Isolation，STI)12交界处的硅锗层10(如图中虚线框E圈示区域)厚度小于位于有源区11中心的硅锗层10的厚度，甚至在有源区11与浅沟槽隔离结构12交界处不存在硅锗层10，对半导体结构的性能产生较大影响。
鉴于上述原因，本公开实施例提供一种半导体结构的制备方法，其能够改善沟道层的结构，获得高质量的沟道层，进而提高半导体结构的性能。
图2是本公开实施例提供的半导体结构的制备方法的步骤示意图，请参阅图2，所述制备方法包括：步骤S20，提供基底，所述基底包括浅沟槽隔离结构及被所述浅沟槽隔离结构限定的有源区；步骤S21，在所述有源区表面形成沟道层；步骤S22，去除所述浅沟槽隔离结构与所述有源区交界区域的所述沟道层，暴露出部分所述有源区；步骤S23，在所述有源区暴露的表面形成绝缘层。
图3A～图3P是本公开实施例提供的制备方法的主要步骤形成的半导体结构示意图。
请参阅步骤S20、图3A及图3B，其中，图3A为俯视图，图3B为沿图3A中A-A线截面图，提供基底300，所述基底300包括浅沟槽隔离结构301及被所述浅沟槽隔离结构301限定的有源区302。
所述基底300包括衬底303，所述有源区302及所述浅沟槽隔离结构301形成在所述衬底303内。所述衬底303可以为半导体衬底；具体包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底等)、至少一个III-V化合物半导体材料(例如为氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底等)、至少一个II-VI化合物半导体材料、至少一个有 机半导体材料或者在本领域已知的其他半导体材料。本实施例以所述衬底303为硅衬底为例进行说明。
作为示例，本公开实施例提供一种形成所述基底的方法。所述方法包括：采用光刻及刻蚀工艺在所述衬底303内形成浅沟槽，所述浅沟槽朝向所述衬底303内部延伸设定距离，所述浅沟槽将所述衬底303隔离成阵列排布的多个有源区302；在所述浅沟槽内填充介质，以形成所述浅沟槽隔离结构301，所述浅沟槽隔离结构301将多个所述有源区302隔开。其中，在一些实施例中，可采用化学气相沉积(Chemical Vapor Deposition，CVD)、原子层沉积(Atomic layer deposition，ALD)等工艺在浅沟槽内沉积氧化物层、氮化物层或者两者的复合层。例如，在本实施例中，采用化学气相沉积工艺向浅沟槽中沉积氧化硅，所述氮化硅填充所述浅沟槽形成浅沟槽隔离结构301，以隔离所述有源区302。在本实施例中，仅示意性绘示一个浅沟槽隔离区301及一个有源区302。
请参阅步骤S21、图3E及图3F，其中，图3E为俯视图，图3F为沿图3E中A-A线的截面图，在所述有源区302表面形成沟道层310。
在该步骤中，所述沟道层310覆盖所述有源区302的表面，并不覆盖所述浅沟槽隔离结构301的表面。
在一些实施例中，硅锗层作为所述沟道层310。硅锗材料的电子和空穴迁移率均比硅高，采用硅锗层作为沟道层有助于提高半导体结构沟道的空穴迁移率，提供半导体结构的电学性能，扩大半导体结构的应用范围。
作为示例，本公开实施例提供一种在所述有源区302表面形成沟道层310的方法，所述方法包括如下步骤：
请参阅图3C及图3D，其中，图3C为俯视图，图3D为沿图3C中A-A线的截面图，沉积硅锗材料，以在所述浅沟槽隔离结构301表面及所述有源区302表面形成硅锗材料层390。
在该步骤中，可采用化学气相沉积、原子层沉积等工艺在所述浅沟槽隔离结构301及所述有源区302的表面沉积硅锗材料，形成所述硅锗材料层390。在该步骤中，所述硅锗材料层390不仅覆盖所述有源区302的表面，还覆盖所述浅沟槽隔离结构301的表面。
在本实施例中，由于浅沟槽隔离结构301的材料组成与所述有源区302的材料组成不同，例如，所述浅沟槽隔离结构301的材料为氧化硅，所述有源区302的材料为硅，硅锗材料在所述浅沟槽隔离结构301表面的沉积速率小于在所述有源区302表面的沉积速率，使得在所述浅沟槽隔离结构301表面形成的硅锗材料层390的厚度小于在所述有源区302 表面形成的硅锗材料层390的厚度，即在所述浅沟槽隔离结构301表面形成的所述硅锗材料层390与在所述有源区302表面形成的所述硅锗材料层390具有高度差。
请继续参阅图3E及图3F，刻蚀所述硅锗材料层390，直至所述浅沟槽隔离结构301表面被暴露。其中，可采用干法刻蚀工艺刻蚀所述硅锗材料层390，所述刻蚀物质包括但不限于HCL刻蚀气体。
在该步骤中，所述浅沟槽隔离结构301表面的硅锗材料层390被完全去除，而由于所述浅沟槽隔离结构301表面的硅锗材料层390的厚度小于所述有源区302表面的硅锗材料层390的厚度，则所述有源区302表面的硅锗材料层390仅被部分去除。即所述有源区302表面的硅锗材料层390仅被减薄，而并未被完全去除，在所述有源区301表面还保留有部分所述硅锗材料层390。
在一些实施例中，为了提高膜层质量，可循环沉积硅锗材料及刻蚀所述硅锗材料层的步骤，即循环沉积-刻蚀工艺直至在所述有源区301表面形成具有设定厚度的所述硅锗材料层390，在所述浅沟槽隔离结构301的表面无所述硅锗材料层390，其中，在所述有源区301表面形成的具有设定厚度的所述硅锗材料层390作为所述沟道层310。
在一些实施例中，所述硅锗材料层390的形成是一个动态生长的过程，在所述硅锗材料层390生长过程中通入HCL刻蚀气体，使得在浅沟槽隔离结构301界面上形成的硅锗材料层390被动态去除，最终只在所述有源区302的硅界面上形成具有设定厚度的硅锗材料层390。
具体地说，在本实施例中，刻蚀所述硅锗材料层390，直至所述浅沟槽隔离结构301表面被暴露的步骤之后，在所述浅沟槽隔离结构301暴露的表面及减薄后的硅锗材料层390的表面继续沉积硅锗材料，形成新的硅锗材料层；再对新的硅锗材料层执行刻蚀工艺，直至所述浅沟槽隔离结构301表面被再次暴露；多次循环执行沉积-刻蚀工艺，直至在所述有源区302表面形成具有设定厚度的所述硅锗材料层390。可以理解的是，所述硅锗材料层390由每次循环中对新的硅锗材料层执行刻蚀工艺后剩余的硅锗材料层堆叠构成，并且在每次沉积硅锗材料的工艺中，沉积在浅沟槽隔离结构301表面的新的硅锗材料层的厚度小于沉积在所述有源区301表面剩余的硅锗材料层表面的新的硅锗材料层的厚度，从而形成在所述有源区301表面形成具有设定厚度的所述硅锗材料层390，在所述浅沟槽隔离结构301的表面无所述硅锗材料层390的半导体结构。
在执行沉积硅锗材料的步骤之后，所述浅沟槽隔离结构301表面的硅锗材料层390的厚度小于所述有源区302表面的硅锗材料层390的厚度，则在所述浅沟槽隔离结构301与 有源区302的交界处(如图3D中箭头D所指示区域)，位于所述有源区302表面的硅锗材料层390的侧壁被部分暴露，请参阅图3C及图3D。在执行刻蚀工艺时，在所述浅沟槽隔离结构301与有源区302的交界处，刻蚀气体不仅会向下刻蚀所述硅锗材料层390，还会侧向刻蚀所述硅锗材料层390暴露的侧壁，而在所述有源区302的其他区域(例如中心区域)，所述硅锗材料层390不存在暴露的侧壁，其仅会被向下刻蚀，这使得所述浅沟槽隔离结构301与有源区302的交界处的硅锗材料层390的刻蚀程度大于所述有源区302的其他区域的硅锗材料层390的刻蚀程度，导致最终形成的沟道层310的边缘厚度小于中心厚度(如图3F中虚线框E所圈示区域的沟道层310的厚度小于沟道层310其他区域的厚度)，对半导体结构的性能会产生较大影响。并且，随着沉积-刻蚀工艺循环次数的增加，沟道层310的边缘与中心的厚度差距越来越明显，甚至在浅沟槽隔离结构301与有源区302交界处不存在沟道层310，对半导体结构的性能产生较大影响。
在本公开其他实施例中，在执行刻蚀所述硅锗材料层390的步骤之前也可采用掩膜层遮挡所述有源区302表面的硅锗材料层390，在执行刻蚀所述硅锗材料层390的步骤中，由于所述掩膜层的遮挡，仅所述浅沟槽隔离结构301表面的硅锗材料层390被去除，所述有源区302表面的硅锗材料层390未被减薄。该种情况下，所述有源区302表面的硅锗材料层390的侧壁依然暴露在刻蚀环境中，则依然存在刻蚀气体侧向刻蚀所述硅锗材料层390暴露的侧壁的情况，而在所述有源区302的其他区域(例如中心区域)，受到掩膜层的保护，所述硅锗材料层390并未被刻蚀，这也导致最终形成的沟道层310的边缘厚度小于中心厚度。
请参阅步骤S22、图3K及图3L，其中，图3K为俯视图，图3L为沿图3K中A-A线的截面图，去除所述浅沟槽隔离结构301与所述有源区302交界区域的所述沟道层310，暴露出部分所述有源区302，所述浅沟槽隔离结构301与所述有源区302的交界处(如图3D中箭头D所指示位置)与所述沟道层310的边缘之间形成间隔C。
在该步骤中，所述浅沟槽隔离结构301与所述有源区302交界区域为自所述浅沟槽隔离结构301与所述有源区302交界处向所述有源区302方向延伸设定距离而形成的区域，例如所述间隔C对应的区域。在本实施例中，所述浅沟槽隔离结构301与所述有源区302交界区域至少覆盖所述沟道层310的边缘区域，以能够完全去除所述沟道层310边缘厚度不同的区域，提高沟道层310厚度的均一性。所述边缘区域可以指所述沟道层310边缘厚度小于所述沟道层310中心厚度的区域。在一些实施例中，在执行步骤S22之后，剩余的所述沟道层310边缘厚度与中心厚度一致，提高了半导体结构的性能。
作为示例，本公开实施例提供了一种去除所述浅沟槽隔离结构301与所述有源区302交界区域的所述沟道层310方法。所述方法包括：
请参阅图3G及图3H，其中，图3G为俯视图，图3H为沿图3G中A-A线的截面图，在所述浅沟槽隔离结构301及所述沟道层310表面形成掩膜层380。即在该步骤中，所述掩膜层380覆盖所述浅沟槽隔离结构301及所述沟道层310表面。若是在所述浅沟槽隔离结构301与所述有源区302的交界处所述有源区302并未被所述沟道层310覆盖，则在该步骤中，所述掩膜层380也覆盖所述有源区302暴露的表面。所述掩膜层380可为由氮化物层构成的硬掩膜层，也可由氧化物与氮化物复合层构成的硬掩膜。
请参阅图3I及图3J，其中，图3I为俯视图，图3J为沿图3I中A-A线的截面图，图案化所述掩膜层380，形成第一窗口381，所述第一窗口381暴露出所述浅沟槽隔离结构301与所述有源区302交界区域的所述沟道层310。
在本实施例中，所述浅沟槽隔离结构301与所述有源区302交界区域与所述第一窗口381对应，即所述浅沟槽隔离结构301与所述有源区302交界区域与所述第一窗口381在所述基底300上的正投影重叠；在另一些实施例中，所述第一窗口381的宽度大于所述浅沟槽隔离结构301与所述有源区302交界区域的宽度，即所述第一窗口381在所述基底300上的正投影覆盖所述浅沟槽隔离结构301与所述有源区302交界区域在所述基底300上的正投影，且所述第一窗口381在所述基底300上的正投影面积大于所述浅沟槽隔离结构301与所述有源区302交界区域在所述基底300上的正投影面积，从而保证所述沟道层310厚度不均匀的区域能够被完全去除，提高沟道层310厚度的均一性。
在该步骤中，可在所述掩膜层380表面形成图案化的光刻胶层，利用所述光刻胶层定义出所述第一窗口381的位置；再以所述光刻胶层为掩膜，采用刻蚀工艺刻蚀所述掩膜层380，形成所述第一窗口381。在一些实施例中，还可在所述掩膜层380表面形成底部抗反射涂层(Bottom Anti-Reflection Coating,BARC)，在所述底部抗反射涂层表面形成所述光刻胶层，以减少光刻时的光反射。
请继续参阅图3K及图3L，以所述掩膜层380作为掩膜去除所述沟道层310。具体地说，在该步骤中，以所述掩膜层380作为掩膜，沿所述第一窗口381，采用刻蚀工艺，例如干法刻蚀工艺，去除所述浅沟槽隔离结构301与所述有源区302交界区域的所述沟道层310，暴露出被所述沟道层310覆盖的有源区302。干法刻蚀工艺的刻蚀气体包括但不限于HCL。
在本实施例中，在去除所述沟道层310时，过刻蚀所述有源区302，形成凹槽304，所述有源区302的顶表面(即所述凹槽304的底表面)低于所述浅沟槽隔离结构301的顶表 面。具体地说，在去除所述沟道层310后，所述浅沟槽隔离结构301与所述有源区302交界区域的所述有源区302也被部分去除，形成所述凹槽304，从而能够保证所述沟道层310被完全去除，避免沟道层310残留。可以理解的是，在其他实施例中，也可不对所述有源区302进行过刻蚀，则所述有源区302的顶表面与所述浅沟槽隔离结构301的顶表面平齐，且低于所述沟道层310的顶表面。
请参阅步骤S23、图3O及图3P，其中，图3O为俯视图，图3P为沿图3O中A-A线的截面图，在所述有源区302暴露的表面形成绝缘层320。
在该步骤中，以所述第一窗口381作为工艺窗口，在所述有源区302暴露的表面形成所述绝缘层320。具体地说，请参阅图3M及图3N，其中，图3M为俯视图，图3N为沿图3M中A-A线的截面图，沉积绝缘材料，所述绝缘材料填充所述凹槽304及所述第一窗口381，并覆盖所述掩膜层380的表面，所述绝缘材料作为所述绝缘层320。在一些实施例中，所述绝缘材料也可不覆盖所述掩膜层380的表面，而是仅填充所述凹槽304及所述第一窗口381。
在一些实施例中，所述绝缘材料可与所述浅沟槽隔离结构301的介质材料相同，例如，所述绝缘材料与所述浅沟槽隔离结构301的介质材料均为氧化硅。在另一些实施例中，所述绝缘材料可与所述浅沟槽隔离结构301的介质材料可不同，例如所述浅沟槽隔离结构301的介质材料为氧化硅，所述绝缘材料为氮化硅。
请继续参阅图3O及图3P，减薄所述掩膜层380及所述绝缘层320，至所述沟道层310被暴露，所述浅沟槽隔离结构301表面剩余的掩膜层380被保留作为补充层360。具体地说，在该步骤中，采用化学机械研磨工艺(Chemical Mechanical Polish，CMP)去除所述掩膜层380表面的所述绝缘层320，并减薄所述掩膜层380及所述绝缘层320。保留的所述掩膜层380覆盖所述浅沟槽隔离结构301表面，作为补充层360，保留的所述绝缘层320覆盖所述有源区302的表面。在本实施例中，所述补充层360的材料与所述绝缘层320的材料不同，例如，所述补充层360的材料为硬掩膜材料，所述绝缘层320的材料为氧化硅。
在本公开实施例提供的制备方法中，所述沟道层310的顶表面高于所述浅沟槽隔离结构301的顶表面，则在该步骤中形成的所述绝缘层320的顶表面或与所述沟道层310的顶表面平齐，或低于所述沟道层310的顶表面。例如，在本实施例中，所述绝缘层320的顶表面或与所述沟道层310的顶表面平齐，即所述绝缘层320的顶表面高于所述浅沟槽隔离结构301的顶表面，且与所述沟道层310的顶表面平齐。所述补充层360用于填补所述浅沟槽隔离结构301的表面，所述补充层360的顶表面与所述沟道层310的顶表面平齐。即 所述补充层360的顶表面、所述绝缘层320的顶表面及所述沟道层310的顶表面平齐，使得形成的半导体结构具有平坦的表面。
在另一实施例中，在形成所述绝缘层320后，减薄所述绝缘层320，例如回刻蚀所述绝缘层320，使得所述绝缘层320的顶表面低于所述沟道层310的顶表面，再去除所述掩膜层380，暴露出所述浅沟槽隔离结构301及所述沟道层310。如图4A及图4B所示，其中，图4A为俯视图，图4B为沿图4A中A-A线的截面图，所述绝缘层320的顶表面与所述浅沟槽隔离结构301的顶表面平齐，并低于所述沟道层310的顶表面。
则在去除所述掩膜层380后，还包括形成补充层360的步骤。所述补充层360覆盖所述浅沟槽隔离结构301及所述绝缘层320的顶表面，并与所述沟道层310表面平齐，使得形成的半导体结构具有平坦的表面。所述补充层360还用于保护所述沟道层310的侧壁，避免其在后续工艺中受到损伤。在本实施例中，所述补充层360的材料可与所述绝缘层320的材料相同，例如两者的材料均为氧化硅。在一些实施例中，形成所述补充层360的步骤包括：先形成覆盖材料，所述覆盖材料覆盖所述浅沟槽隔离结构301、所述绝缘层320及所述沟道层310的顶表面；减薄所述覆盖材料至所述沟道层310的顶表面被暴露，剩余的所述覆盖材料作为所述补充层360。
同样地，在另一些实施例中，所述绝缘层320表面与所述浅沟槽隔离结构301的表面平齐，则也可利用补充层360填补所述浅沟槽隔离结构301及所述绝缘层320表面，所述补充层360顶表面与所述沟道层310的顶表面平齐。所述补充层360的形成方法可以上述方法相同，此处不再赘述。
本公开实施例提供的半导体结构的制备方法在形成沟道层后去除沟道层厚度较薄的边缘部分，并利用绝缘层进行填充，形成厚度均一高质量的沟道层，大大提高了半导体结构的性能，扩大了以硅锗材料为沟道的半导体结构的适用范围。
本公开实施例还提供一种采用上述制备方法形成的半导体结构。请参阅图3A～图3P，其为本公开实施例提供的半导体结构的结构示意图，所述半导体结构包括基底300、沟道层310、绝缘层320。
所述基底300包括浅沟槽隔离结构301及被所述浅沟槽隔离结构301限定的有源区302。在本实施例中，所述基底300包括衬底303，所述有源区302及所述浅沟槽隔离结构301设置在所述衬底303内。所述浅沟槽隔离结构301朝向所述衬底303内部延伸设定距离，所述浅沟槽隔离结构301将所述衬底303隔离成阵列排布的多个有源区302，在本实施例中，仅示意性绘示一个浅沟槽隔离区301及一个有源区302。
所述沟道层310设置在所述有源区302中部的表面。也就是说，所述沟道层310并未铺满所述有源区302，所述有源区302的外围并未被所述沟道层310覆盖，即所述浅沟槽隔离结构301与所述有源区302的交界处(如图3D中箭头D所指示位置)与所述沟道层310的边缘之间具有一间隔C(请参阅图3L)，所述间隔C是所述沟道层310边缘被去除而形成。由于所述沟道层310在制备过程中被部分去除，使得所述半导体结构的所述沟道层310边缘区域的厚度与中心区域的厚度基本一致。
所述绝缘层320设置在所述浅沟槽隔离结构301与所述沟道层310之间，且覆盖所述有源区302外围的表面，即所述绝缘层320覆盖所述间隔C对应的所述有源区302的顶表面及所述沟道层310的侧壁，所述绝缘层320并不覆盖所述沟道层310的顶表面。也就是说，所述绝缘层320填充所述间隔C，从而避免所述浅沟槽隔离结构301与所述沟道层310之间存在间隙。
在本实施例中，在所述间隔C对应的区域，所述有源区302具有一凹槽304，所述凹槽304的底面低于所述浅沟槽隔离结构301的顶表面，所述绝缘层320填充在所述凹槽304内。也就是说，在本实施例中，所述绝缘层320的底表面低于所述有源区302的顶表面，所述绝缘层320的顶表面与所述沟道层310的顶表面平齐，所述浅沟槽隔离结构301的顶表面低于所述沟道层310的顶表面。
所述半导体结构还包括补充层360，所述补充层360覆盖所述浅沟槽隔离结构301的表面，所述补充层360表面与所述沟道层310表面平齐，即所述补充层360的顶表面、所述绝缘层320的顶表面及所述沟道层310的顶表面平齐，使得所述半导体结构具有平坦的表面。
在本实施例中，所述绝缘层320的材料与所述浅沟槽隔离结构301的材料相同，例如，两者均为氧化硅；所述补充层360的材料与所述绝缘层320的材料不同，例如，所述补充层360的材料为硬掩膜材料，如氮化硅，所述绝缘层320的材料为氧化硅。可以理解的是，在其他实施例中，所述补充层360的材料也可与所述绝缘层320及所述浅沟槽隔离结构301的材料相同，例如三者均为氧化硅。
在本实施例中，由于所述绝缘层320的顶表面与所述沟道层310的顶表面平齐，则所述补充层360仅覆盖所述浅沟槽隔离结构301的表面。在本公开另一实施例提供的半导体结构中，请参阅图4A及图4B，所述绝缘层320的底表面低于所述有源区302的顶表面，所述绝缘层320的顶表面低于所述沟道层310的表面，且与所述浅沟槽隔离结构301的顶表面平齐，则所述补充层360不仅覆盖所述浅沟槽隔离结构301的表面，还覆盖所述绝缘 层320的表面，且所述补充层360表面与所述沟道层310表面平齐，用于形成平坦的器件表面，也用于保护所述沟道层310的侧壁，避免其在后续工艺中受到损伤。
同样地，在另一些实施例中，所述绝缘层320的底表面低于所述有源区302的顶表面，所述绝缘层320的顶表面高于所述浅沟槽隔离结构301的顶表面，且低于所述沟道层310的顶表面，则所述补充层360覆盖所述浅沟槽隔离结构301及所述绝缘层320表面，且与所述沟道层310表面平齐，以于形成平坦的器件表面。
同样地，在另一些实施例中，所述绝缘层320的底表面与所述有源区302的顶表面平齐，且与所述浅沟槽隔离结构301的顶表面平齐，所述绝缘层320的顶表面与所述沟道层310的顶表面平齐，则所述补充层360覆盖所述浅沟槽隔离结构301顶表面，且与所述沟道层310表面平齐，以于形成平坦的器件表面。
同样地，在另一些实施例中，所述绝缘层320的底表面与所述有源区302的顶表面平齐，且与所述浅沟槽隔离结构301的顶表面平齐，所述绝缘层320的顶表面低于与所述沟道层310的顶表面，则所述补充层360覆盖所述浅沟槽隔离结构301及所述绝缘层320的顶表面，且与所述沟道层310表面平齐，以于形成平坦的器件表面。
本公开实施例提供的半导体结构中，由于所述沟道层310在制备过程中被部分去除，使得所述半导体结构的所述沟道层310边缘区域的厚度与中心区域的厚度基本一致，所述沟道层310被去除的区域采用绝缘层320填充，进一步避免沟道层310侧壁被暴露，能够形成厚度均一高质量的沟道层310，大大提高了半导体结构的性能，扩大了以硅锗材料为沟道的半导体结构的适用范围。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (16)

  1. 一种半导体结构的制备方法，包括：
    提供基底，所述基底包括浅沟槽隔离结构及被所述浅沟槽隔离结构限定的有源区；
    在所述有源区表面形成沟道层；
    去除所述浅沟槽隔离结构与所述有源区交界区域的所述沟道层，暴露出部分所述有源区；
    在所述有源区暴露的表面形成绝缘层。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，在所述有源区表面形成沟道层的方法包括：
    沉积硅锗材料，以在所述浅沟槽隔离结构表面及所述有源区表面形成硅锗材料层；
    刻蚀所述硅锗材料层，直至所述浅沟槽隔离结构表面被暴露。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，在沉积硅锗材料步骤中，在所述浅沟槽隔离结构表面沉积的硅锗材料层厚度小于在所述有源区表面沉积的硅锗材料层厚度。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，在刻蚀所述硅锗材料层的步骤中，所述有源区表面的硅锗材料层被减薄。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，循环沉积所述硅锗材料及刻蚀所述硅锗材料层的步骤，直至在所述有源区表面形成具有设定厚度的所述硅锗材料层，在所述浅沟槽隔离结构的表面无所述硅锗材料层。
  6. 根据权利要求1所述的半导体结构的制备方法，其中，去除所述浅沟槽隔离结构与所述有源区交界区域的所述沟道层的方法包括：
    在所述浅沟槽隔离结构及所述沟道层表面形成掩膜层；
    图案化所述掩膜层，形成第一窗口，所述第一窗口暴露出所述交界区域的所述沟道层；
    以所述掩膜层作为掩膜去除所述沟道层。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，在所述有源区暴露的表面形成绝缘层的步骤包括：以所述第一窗口作为工艺窗口，在所述有源区暴露的表面形成所述绝缘层；
    减薄所述掩膜层及所述绝缘层，至所述沟道层被暴露，所述浅沟槽隔离结构表面剩余的掩膜层被保留作为补充层。
  8. 根据权利要求1所述的半导体结构的制备方法，其中，去除所述浅沟槽隔离结构与所述有源区交界区域的所述沟道层的步骤包括：过刻蚀所述有源区形成凹槽；在形成所述绝 缘层的步骤中，所述绝缘层填充在所述凹槽内。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，所述绝缘层表面低于所述沟道层表面，所述方法还包括如下步骤：
    形成补充层，所述补充层覆盖所述浅沟槽隔离结构及所述绝缘层表面，并与所述沟道层顶表面平齐。
  10. 一种半导体结构，包括：
    基底，所述基底包括浅沟槽隔离结构及被所述浅沟槽隔离结构限定的有源区；
    沟道层，设置在所述有源区中部的表面；
    绝缘层，设置在所述浅沟槽隔离结构与所述沟道层之间，且覆盖所述有源区外围的表面。
  11. 根据权利要求10所述的半导体结构，其中，所述绝缘层的底表面低于所述有源区的顶表面，所述绝缘层的顶表面与所述浅沟槽隔离结构的顶表面平齐，所述绝缘层的顶表面低于所述沟道层的顶表面。
  12. 根据权利要求11所述的半导体结构，进一步还包括补充层，所述补充层覆盖所述浅沟槽隔离结构及所述绝缘层的顶表面。
  13. 根据权利要求10所述的半导体结构，其中，所述绝缘层的底表面低于所述有源区的顶表面，所述绝缘层的顶表面与所述沟道层的顶表面平齐。
  14. 根据权利要求13所述的半导体结构，进一步还包括补充层，所述补充层覆盖所述浅沟槽隔离结构的顶表面，所述补充层的顶表面与所述绝缘层的顶表面平齐。
  15. 根据权利要求12所述的半导体结构，其中，所述绝缘层的材料与所述浅沟槽隔离结构的材料相同，所述补充层的材料与所述绝缘层的材料不同。
  16. 根据权利要求14所述的半导体结构，其中，所述绝缘层的材料与所述浅沟槽隔离结构的材料相同，所述补充层的材料与所述绝缘层的材料不同。
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