WO2024043105A1 - トランスチップ、信号伝達装置 - Google Patents

トランスチップ、信号伝達装置 Download PDF

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Publication number
WO2024043105A1
WO2024043105A1 PCT/JP2023/029140 JP2023029140W WO2024043105A1 WO 2024043105 A1 WO2024043105 A1 WO 2024043105A1 JP 2023029140 W JP2023029140 W JP 2023029140W WO 2024043105 A1 WO2024043105 A1 WO 2024043105A1
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Prior art keywords
chip
transformer
coil
insulating layer
electrode
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PCT/JP2023/029140
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English (en)
French (fr)
Japanese (ja)
Inventor
普之 井ノ口
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024542746A priority Critical patent/JPWO2024043105A1/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F19/00—Fixed transformers or mutual inductances of the signal type
    • H01F19/04—Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present disclosure relates to a transformer chip and a signal transmission device.
  • an insulated gate driver that applies a gate voltage to the gate of a switching element such as a transistor is known.
  • a structure is known that includes a first coil and a second coil that are arranged to face each other in the thickness direction of the element insulating layer in the element insulating layer (for example, (See Patent Document 1).
  • insulated chips such as those described above may be required to have improved dielectric strength.
  • a transformer chip that is one aspect of the present disclosure includes a conductive substrate, an insulator provided on the substrate and including a first insulating layer arranged parallel to the substrate, and sandwiching the first insulating layer.
  • a first transformer including a first coil and a second coil, which are arranged with the first insulating layer sandwiched therebetween, and which include a first coil and a second coil which are arranged so as to be magnetically coupled in the thickness direction of the first insulating layer;
  • a second transformer including a third coil and a fourth coil arranged so as to be magnetically coupled in the thickness direction of one insulating layer, and a second transformer electrically connected to the first transformer; and the insulation transformer.
  • first connection electrode and a second connection electrode that are electrically connected to and used for electrical connection with the outside; a first capacitor that is electrically connected to the first connection electrode; and a second connection electrode. and a second capacitor electrically connected in series with the first capacitor, and a connection portion that electrically connects the first capacitor and the second capacitor to the substrate.
  • a signal transmission device includes a first chip including a first circuit, a transformer chip, and at least one of transmitting and receiving a signal with the first circuit through the transformer chip.
  • the transformer includes a third coil and a fourth coil that are arranged to sandwich the first insulating layer and are arranged to be magnetically coupled in the thickness direction of the first insulating layer, and are electrically connected to the first transformer.
  • a second transformer a first connection electrode and a second connection electrode that are electrically connected to the insulation transformer and used for electrical connection with the outside; and a first connection electrode and a second connection electrode that are electrically connected to the first connection electrode.
  • a second capacitor electrically connected to the second connection electrode and electrically connected in series with the first capacitor; A connection part that electrically connects to the substrate.
  • transformer chip and signal transmission device that are one aspect of the present disclosure, it is possible to improve the dielectric strength.
  • FIG. 1 is a circuit diagram schematically showing a circuit configuration of a signal transmission device according to an embodiment.
  • FIG. 2 is a schematic cross-sectional view of a signal transmission device of one embodiment.
  • 3 is a schematic plan view of the transformer chip of FIG. 2.
  • FIG. 4 is a schematic plan view of the transformer chip of FIG. 2 in a different position from FIG. 3.
  • FIG. 5 is a schematic cross-sectional view of the transformer chip of FIG. 2.
  • FIG. 6 is a schematic cross-sectional view of a signal transmission device of a comparative example.
  • FIG. 7 is a schematic cross-sectional view of a signal transmission device according to a modification.
  • FIG. 8 is a schematic cross-sectional view of a modified example of the signal transmission device.
  • FIG. 9 is a circuit diagram schematically showing a circuit configuration of a signal transmission device according to a modified example.
  • the expression “at least one” as used herein means “one or more” of the desired options.
  • the expression “at least one” as used herein means “only one option” or “both of the two options” if the number of options is two.
  • the expression “at least one” as used herein means “only one option” or “any combination of two or more options” if there are three or more options. means.
  • FIG. 1 shows a simplified example of the circuit configuration of the signal transmission device 10.
  • FIG. 2 shows an example of a schematic cross-sectional structure showing the internal structure of a part of the signal transmission device 10.
  • the signal transmission device 10 is a device that transmits signals while electrically insulating between the primary terminal 11 and the secondary terminal 12.
  • Signal transmission device 10 is, for example, a digital isolator.
  • the signal transmission device 10 includes a primary circuit 13 electrically connected to a primary terminal 11, a secondary circuit 14 electrically connected to a secondary terminal 12, and a primary circuit 13.
  • the signal transmission circuit 10A includes a transformer 15 that electrically isolates the secondary circuit 14 from the signal transmission circuit 10A.
  • the primary side circuit 13 corresponds to a "first circuit”
  • the secondary side circuit 14 corresponds to a "second circuit”.
  • the transformer 15 corresponds to an "insulation transformer".
  • the primary side circuit 13 is a circuit configured to operate when the first voltage V1 is applied.
  • the secondary side circuit 14 is a circuit configured to operate when a second voltage V2 different from the first voltage V1 is applied.
  • the first voltage V1 and the second voltage V2 are different voltages.
  • the first voltage V1 is higher than, for example, the second voltage V2.
  • the first voltage V1 and the second voltage V2 are DC voltages.
  • the ground of the primary circuit 13 and the ground of the secondary circuit 14 are provided independently.
  • the primary side circuit 13 is electrically connected via the primary side terminal 11 to, for example, a drive circuit to be controlled by a control device.
  • An example of a drive circuit is a switching circuit.
  • the secondary circuit 14 is electrically connected to, for example, an external control device (not shown) via the secondary terminal 12.
  • a control signal from the control device is input to the secondary circuit 14 via the secondary terminal 12.
  • the output signal of the secondary circuit 14 is transmitted to the primary circuit 13 via the transformer 15.
  • the signal transmitted to the primary circuit 13 is output from the primary circuit 13 to the drive circuit via the primary terminal 11.
  • the primary side circuit 13 and the secondary side circuit 14 are electrically insulated by the transformer 15. More specifically, the transformer 15 is configured to regulate the transmission of DC voltage between the primary side circuit 13 and the secondary side circuit 14, while being able to transmit pulse signals.
  • the state where the primary side circuit 13 and the secondary side circuit 14 are insulated refers to the state where the transmission of DC voltage is cut off between the primary side circuit 13 and the secondary side circuit 14. This means that transmission of pulse signals from the primary circuit 13 to the secondary circuit 14 is permitted.
  • the primary side circuit 13 is configured to perform at least one of transmitting and receiving signals with the secondary side circuit 14.
  • the dielectric strength voltage of the signal transmission device 10 is, for example, 5000 Vrms or more and 15000 Vrms or less.
  • the dielectric strength voltage of the signal transmission device 10 of this embodiment is about 10,000 Vrms.
  • the specific numerical value of the dielectric strength voltage of the signal transmission device 10 is not limited to this and is arbitrary.
  • the signal transmission device 10 of this embodiment has one signal transmission path between the primary side circuit 13 and the secondary side circuit 14 by a transformer 15.
  • the signal transmission device 10 includes primary signal lines 16A, 16B that connect the primary circuit 13 and the transformer 15, secondary signal lines 17A, 17B that connect the transformer 15 and the secondary circuit 14, including.
  • the transformer 15 transmits the first signal from the primary circuit 13 to the secondary circuit 14 while electrically insulating the primary circuit 13 and the secondary circuit 14.
  • the transformer 15 includes a first transformer 21 and a second transformer 22 that are connected in series.
  • the first transformer 21 corresponds to a "first insulating element”
  • the second transformer 22 corresponds to a "second insulating element”.
  • the signal transmission device 10 includes a pair of connection signal lines 18A and 18B that connect the first transformer 21 and the second transformer 22.
  • the dielectric strength voltage of each transformer 21 and 22 in this embodiment is, for example, 2500 Vrms or more and 7500 Vrms or less. Note that the dielectric strength voltage of each transformer 21 and 22 may be 2500 Vrms or more and 5700 Vrms or less. However, the specific numerical value of the dielectric strength voltage of each transformer 21, 22 is not limited to this and is arbitrary.
  • the first transformer 21 has a first coil 23 and a second coil 24 that is electrically insulated from the first coil 23 and can be magnetically coupled.
  • the second transformer 22 includes a third coil 25 and a fourth coil 26 that is electrically insulated from the third coil 25 and can be magnetically coupled.
  • the first coil 23 is electrically connected to the primary circuit 13 by primary signal lines 16A and 16B.
  • the second coil 24 is connected to the fourth coil 26 by a pair of connection signal lines 18A and 18B.
  • the second coil 24 and the fourth coil 26 are connected to each other so as to be electrically floating.
  • the first end of the second coil 24 and the first end of the fourth coil 26 are connected by a connection signal line 18A
  • the second end of the second coil 24 and the second end of the fourth coil 26 are connected to each other by a connection signal line 18A. and is connected by a connection signal line 18B.
  • the second coil 24 and the fourth coil 26 serve as relay coils that relay the first signal between the first coil 23 and the third coil 25.
  • the third coil 25 is electrically connected to the secondary circuit 14 by secondary signal lines 17A and 17B.
  • FIG. 2 shows an example of a schematic cross-sectional structure showing the internal structure of a part of the signal transmission device 10.
  • the signal transmission device 10 is a semiconductor device in which a plurality of semiconductor chips are packaged into one package.
  • the package format of the signal transmission device 10 is, for example, an SO (Small Outline) system, and in this embodiment is an SOP (Small Outline Package). Note that the package format of the signal transmission device 10 can be changed arbitrarily.
  • the signal transmission device 10 includes a first chip 40, a second chip 50, and a transformer chip 60 as a plurality of semiconductor chips.
  • the signal transmission device 10 also includes a primary die pad 71 on which the first chip 40 is mounted, a secondary die pad 72 on which the second chip 50 is mounted, and an intermediate die pad 73 on which the transformer chip 60 is mounted.
  • the intermediate die pad 73 is insulated from both the primary die pad 71 and the secondary die pad 72.
  • the signal transmission device 10 includes a sealing resin 90 that seals each die pad 71 , 72 , 73 and each chip 40 , 50 , 60 .
  • the transformer chip 60 corresponds to an "insulating chip”.
  • the primary die pad 71 corresponds to a "first die pad”
  • the secondary die pad 72 corresponds to a "second die pad”
  • the intermediate die pad 73 corresponds to a "third die pad.”
  • the sealing resin 90 is made of an electrically insulating material, for example, black epoxy resin.
  • the sealing resin 90 is formed into a rectangular plate shape with the thickness direction in the z direction.
  • the primary die pad 71, the secondary die pad 72, and the intermediate die pad 73 are made of a conductive material.
  • each die pad 71, 72, 73 is formed of a material containing Cu (copper).
  • each die pad 71, 72, 73 may be formed of other metal materials such as Al (aluminum).
  • the material constituting each die pad 71, 72, 73 is not limited to a conductive material.
  • each die pad 71, 72, 73 may be made of ceramic such as alumina. That is, each die pad 71, 72, 73 may be formed of a material having electrical insulation properties.
  • the primary die pad 71, intermediate die pad 73, and secondary die pad 72 are arranged side by side and spaced apart from each other.
  • the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 are electrically insulated from each other. Therefore, the intermediate die pad 73 is in an electrically floating state with respect to the primary die pad 71 and the secondary die pad 72.
  • the arrangement direction of the primary die pad 71, intermediate die pad 73, and secondary die pad 72 is defined as the x direction.
  • the direction orthogonal to the x direction is defined as the y direction.
  • the x direction corresponds to the "first direction”
  • the y direction corresponds to the "second direction”.
  • the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 are formed into a flat plate shape.
  • the shape of each die pad 71, 72, 73 when viewed from the z direction is a rectangular shape with the short side in the x direction and the long side in the y direction.
  • the area of the secondary die pad 72 viewed from the z direction is larger than the area of the primary die pad 71 viewed from the z direction.
  • the shape of each die pad 71, 72, 73 viewed from the z direction can be changed arbitrarily.
  • the shape of each die pad 71, 72, 73 viewed from the z direction may be a rectangle with the long side in the x direction and the short side in the y direction.
  • the transformer chip 60 is mounted on the intermediate die pad 73. That is, the first chip 40, the transformer chip 60, and the second chip 50 are mounted on the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72, respectively, which are electrically insulated from each other. It can be said that the first chip 40, the transformer chip 60, and the second chip 50 are arranged apart from each other in the x direction. In this embodiment, the first chip 40, the transformer chip 60, and the second chip 50 are arranged in this order from the primary die pad 71 toward the secondary die pad 72 in the x direction. In other words, the transformer chip 60 is arranged between the first chip 40 and the second chip 50 in the x direction. In this embodiment, each die pad 71 , 72 , 73 is not exposed from the sealing resin 90 .
  • the distance between the primary die pad 71 and the intermediate die pad 73 in the x direction is equal to the distance between the intermediate die pad 73 and the secondary die pad 72 in the x direction. Therefore, when viewed from the z direction, the distance between the first chip 40 and the transformer chip 60 in the x direction is equal to the distance between the transformer chip 60 and the second chip 50 in the x direction. In other words, the transformer chip 60 is placed intermediate between the first chip 40 and the second chip 50.
  • the first chip 40 has a rectangular shape having short sides and long sides when viewed from the z direction. When viewed from the z direction, the first chip 40 is mounted on the primary die pad 71 so that the short side runs along the x direction and the long side runs along the y direction.
  • the first chip 40 includes a first substrate 43 on which the primary circuit 13 is formed.
  • the first substrate 43 is, for example, a semiconductor substrate.
  • An example of the semiconductor substrate is a substrate made of a material containing Si (silicon).
  • a wiring layer 44 is formed on the first substrate 43.
  • the wiring layer 44 includes a plurality of insulating films laminated in the z-direction, a metal layer provided between adjacent insulating films in the z-direction, and a via that penetrates the insulating film in the z-direction and is connected to the metal layer. It has The metal layer constitutes the wiring pattern of the first chip 40.
  • the first chip 40 has a chip main surface 40S and a chip back surface 40R facing oppositely to each other in the z direction.
  • the first substrate 43 constitutes the back surface 40R of the chip
  • the wiring layer 44 constitutes the main surface 40S of the chip.
  • the chip back surface 40R faces the primary die pad 71.
  • a plurality of first electrode pads 41 and a plurality of second electrode pads 42 are provided on the chip main surface 40S side of the first chip 40. More specifically, each electrode pad 41, 42 is provided so as to be exposed from the chip main surface 40S.
  • Each electrode pad 41 , 42 is electrically connected to the primary circuit 13 through a wiring layer 44 .
  • the plurality of first electrode pads 41 are arranged on the opposite side of the transformer chip 60 with respect to the center of the chip main surface 40S in the x direction of the chip main surface 40S. Although not shown, the plurality of first electrode pads 41 are arranged apart from each other in the y direction.
  • the plurality of second electrode pads 42 are arranged closer to the transformer chip 60 with respect to the center of the chip main surface 40S in the x direction of the chip main surface 40S. Although not shown, the plurality of second electrode pads 42 are arranged apart from each other in the y direction.
  • the first chip 40 is bonded to the primary die pad 71 by a first bonding material 81. More specifically, a first bonding material 81 is interposed between the chip back surface 40R and the primary die pad 71. The first bonding material 81 bonds the chip back surface 40R and the primary die pad 71.
  • the first bonding material 81 is a conductive bonding material such as solder or Ag (silver) paste.
  • the first bonding material 81 bonds the first substrate 43 of the first chip 40 and the primary die pad 71. Thereby, the first substrate 43 and the primary die pad 71 are electrically connected. Therefore, the primary circuit 13 is electrically connected to the primary die pad 71 via the first bonding material 81.
  • the primary die pad 71 constitutes a ground for the primary circuit 13.
  • the shape of the second chip 50 is a rectangle having short sides and long sides when viewed from the z direction. When viewed from the z direction, the second chip 50 is mounted on the secondary die pad 72 so that the short side runs along the x direction and the long side runs along the y direction.
  • the second chip 50 includes a second substrate 53 on which the secondary circuit 14 is formed.
  • the second substrate 53 is, for example, a semiconductor substrate.
  • An example of a semiconductor substrate is a Si substrate.
  • a wiring layer 54 is formed on the second substrate 53.
  • the wiring layer 54 includes a plurality of insulating films laminated in the z-direction, a metal layer provided between adjacent insulating films in the z-direction, and vias that penetrate the insulating films in the z-direction and are connected to the metal layer. It has .
  • the metal layer constitutes the wiring pattern of the second chip 50.
  • the second chip 50 has a chip main surface 50S and a chip back surface 50R facing oppositely to each other in the z direction.
  • the second substrate 53 constitutes the back surface 50R of the chip
  • the wiring layer 54 constitutes the main surface 50S of the chip.
  • the chip back surface 50R faces the secondary die pad 72.
  • the chip back surface 50R faces the same side as the chip back surface 40R of the first chip 40
  • the chip main surface 50S faces the same side as the chip main surface 40S of the first chip 40.
  • a plurality of first electrode pads 51 and a plurality of second electrode pads 52 are provided on the chip main surface 50S side of the second chip 50. More specifically, each electrode pad 51, 52 is provided so as to be exposed from the chip main surface 50S.
  • Each electrode pad 51, 52 is electrically connected to the secondary circuit 14 by, for example, a wiring layer 54.
  • the plurality of first electrode pads 51 are arranged closer to the transformer chip 60 with respect to the center of the chip main surface 50S in the x direction of the chip main surface 50S. Although not shown, the plurality of first electrode pads 51 are arranged apart from each other in the y direction.
  • the plurality of second electrode pads 52 are arranged on the opposite side of the transformer chip 60 with respect to the center of the chip main surface 50S in the x direction of the chip main surface 50S. Although not shown, the plurality of second electrode pads 52 are arranged apart from each other in the y direction.
  • the second chip 50 is bonded to the secondary die pad 72 by a second bonding material 82. More specifically, the second bonding material 82 is interposed between the chip back surface 50R and the secondary die pad 72. The second bonding material 82 bonds the chip back surface 50R and the secondary die pad 72.
  • the second bonding material 82 is a conductive bonding material such as solder or Ag paste. In this embodiment, the second bonding material 82 is made of the same material as the first bonding material 81, for example.
  • the second bonding material 82 bonds the second substrate 53 of the second chip 50 and the secondary die pad 72 . Thereby, the second substrate 53 and the secondary die pad 72 are electrically connected. Therefore, the secondary circuit 14 is electrically connected to the secondary die pad 72 via the second bonding material 82.
  • the secondary die pad 72 constitutes a ground for the secondary circuit 14.
  • the transformer chip 60 has a rectangular shape having short sides and long sides when viewed from the z direction. In this embodiment, when viewed from the z direction, the transformer chip 60 is mounted on the secondary die pad 72 so that the long side runs along the y direction and the short side runs along the x direction.
  • the transformer chip 60 includes a third substrate 63.
  • the third substrate 63 is, for example, a semiconductor substrate.
  • An example of a semiconductor substrate is a Si substrate.
  • the transformer chip 60 includes an insulator 64 on a third substrate 63.
  • the transformer chip 60 includes the transformer 15 (first transformer 21, second transformer 22). Further, the transformer chip 60 includes a first capacitor 31 and a second capacitor 32. The transformer 15, the first capacitor 31, and the second capacitor 32 are embedded in the insulator 64.
  • the transformer chip 60 has a chip main surface 60S and a chip back surface 60R facing oppositely to each other in the z direction.
  • the chip back surface 60R faces the secondary die pad 72. That is, the chip back surface 60R faces the same side as the chip back surface 50R of the second chip 50, and the chip main surface 60S faces the same side as the chip main surface 50S of the second chip 50.
  • the transformer chip 60 includes a plurality of first electrode pads 61 and a plurality of second electrode pads 62. Each first electrode pad 61 and each second electrode pad 62 are provided on the chip main surface 60S side. More specifically, when viewed from the z direction, each electrode pad 61, 62 is provided so as to be exposed from the chip main surface 60S.
  • the plurality of first electrode pads 61 are arranged closer to the first chip 40 with respect to the center of the chip main surface 60S in the x direction of the chip main surface 60S.
  • the plurality of second electrode pads 62 are arranged closer to the second chip 50 with respect to the center of the chip main surface 60S in the x direction of the chip main surface 60S.
  • the first transformer 21 and the second transformer 22 of the transformer 15 are connected in series between the first electrode pad 61 and the second electrode pad 62.
  • the first capacitor 31 and the second capacitor 32 are connected in series between the first electrode pad 61 and the second electrode pad 62. Further, the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63.
  • the first electrode pad 61 corresponds to a "first connection electrode.”
  • the second electrode pad 62 corresponds to a "second connection electrode.”
  • the transformer chip 60 is bonded to the intermediate die pad 73 by a third bonding material 83. More specifically, a third bonding material 83 is interposed between the chip back surface 60R and the intermediate die pad 73. The third bonding material 83 bonds the chip back surface 60R and the intermediate die pad 73.
  • the third bonding material 83 is a conductive bonding material such as solder or Ag (silver) paste. The third bonding material 83 bonds the third substrate 63 of the transformer chip 60 and the intermediate die pad 73. Thereby, the third substrate 63 and the intermediate die pad 73 are electrically connected.
  • wires W1 to W4 are connected to each of the first chip 40, transformer chip 60, and second chip 50.
  • Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor such as Au (gold), Al, or Cu.
  • the plurality of first electrode pads 41 of the first chip 40 are individually connected to a plurality of primary leads (not shown) by a plurality of wires W1.
  • the primary lead is a component that constitutes the primary terminal 11 in FIG. Thereby, the primary side circuit 13 and the primary side terminal 11 are electrically connected.
  • the primary lead is made of the same material as the primary die pad 71, for example.
  • the primary lead and the primary die pad 71 may be integrally formed.
  • the primary-side leads are arranged at a distance from the primary-side die pad 71 on the side opposite to the secondary-side die pad 72, and are formed across the sealing resin 90. That is, the primary lead has a portion that protrudes outward from the sealing resin 90. A portion of the primary lead that protrudes outward from the sealing resin 90 constitutes an external terminal of the signal transmission device 10.
  • the plurality of second electrode pads 42 of the first chip 40 are individually connected to the plurality of first electrode pads 61 of the transformer chip 60 by a plurality of wires W2. Thereby, the primary circuit 13 and the first transformer 21 are electrically connected. That is, the wiring layer 44 of the first chip 40, the plurality of second electrode pads 42, the plurality of wires W2, and the plurality of first electrode pads 61 are each connected to one of the primary signal lines 16A, 16B (see FIG. 1). It makes up the department.
  • the plurality of second electrode pads 62 of the transformer chip 60 are individually connected to the plurality of first electrode pads 51 of the second chip 50 by a plurality of wires W3. Thereby, the second transformer 22 and the secondary circuit 14 are electrically connected. That is, the plurality of second electrode pads 62, the plurality of wires W3, and the plurality of first electrode pads 51 of the second chip 50 each constitute a part of the secondary signal lines 17A, 17B (see FIG. 1). ing.
  • the plurality of second electrode pads 52 of the second chip 50 are individually connected to a plurality of secondary leads (not shown) by a plurality of wires W4.
  • the secondary lead is a component that constitutes the secondary terminal 12 in FIG. Thereby, the secondary side circuit 14 and the secondary side terminal 12 are electrically connected.
  • the secondary leads are made of the same material as the secondary die pad 72, for example.
  • the secondary lead and the secondary die pad 72 may be integrally formed.
  • the secondary leads are arranged at a distance from the secondary die pad 72 on the opposite side of the primary die pad 71 and are formed across the sealing resin 90 . That is, the secondary lead has a portion that protrudes outward from the sealing resin 90. A portion of the secondary lead that protrudes outward from the sealing resin 90 constitutes an external terminal of the signal transmission device 10.
  • FIG. 3 is a plan view schematically showing the planar structure of the transformer chip 60.
  • FIG. 4 is a cross-sectional view schematically showing the cross-sectional structure of the inside of the transformer chip 60 taken along the xy plane. In FIG. 4, hatching lines are omitted from the viewpoint of ease of viewing the drawing.
  • FIG. 5 is a cross-sectional view schematically showing the cross-sectional structure of the transformer chip 60. As shown in FIG. Further, since the coils 23, 24, 25, 26 shown in FIG. 5 are shown schematically, they are not consistent with the configurations of the coils 23, 24, 25, 26 shown in FIGS. 3 and 4. .
  • the transformer chip 60 is the transformer 15 integrated into one chip. That is, the transformer chip 60 is a chip dedicated to the transformer 15 that is provided separately from the first chip 40 and the second chip 50.
  • the transformer chip 60 includes a chip main surface 60S, a chip back surface 60R, and a plurality of chip side surfaces 601, 602, 603, and 604.
  • the chip side surfaces 601 to 604 are perpendicular to both the chip main surface 60S and the chip back surface 60R.
  • Chip side surfaces 601 and 602 constitute end surfaces of the transformer chip 60 in the x direction.
  • Chip side surfaces 603 and 604 constitute end surfaces of the transformer chip 60 in the y direction.
  • a chip side surface 601 of the transformer chip 60 faces the first chip 40 shown in FIG. 2
  • a chip side surface 602 of the transformer chip 60 faces the second chip 50 shown in FIG.
  • the direction from the chip back surface 60R of the transformer chip 60 to the chip main surface 60S will be referred to as the upper side
  • the direction from the chip main surface 60S to the chip rear surface 60R will be referred to as the lower side.
  • the transformer chip 60 includes a third substrate 63 and an insulator 64 disposed on the third substrate 63.
  • the third substrate 63 has a substrate front surface 63S and a substrate back surface 63R facing oppositely to each other in the z direction.
  • the third substrate 63 is formed of, for example, a semiconductor substrate.
  • the third substrate 63 is a semiconductor substrate made of a material containing Si.
  • the third substrate 63 may be made of a wide bandgap semiconductor or a compound semiconductor as a semiconductor substrate.
  • the third substrate 63 may be an insulating substrate formed of a material containing glass or an insulating substrate formed of a material containing ceramics such as alumina.
  • a wide band gap semiconductor is a semiconductor substrate having a band gap of 2.0 eV or more.
  • the wide bandgap semiconductor may be SiC (silicon carbide).
  • the compound semiconductor may be a III-V compound semiconductor.
  • the compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).
  • the insulator 64 includes a first insulating layer 641, a second insulating layer 642 provided on the first insulating layer 641, and a third insulating layer 643 provided below the first insulating layer 641. .
  • the first insulating layer 641 is arranged parallel to the third substrate 63.
  • the first insulating layer 641 and the second insulating layer 642 are in contact with each other.
  • the first insulating layer 641 and the third insulating layer 643 are in contact with each other.
  • the third insulating layer 643 is in contact with the substrate surface 63S of the third substrate 63.
  • the insulator 64 includes a third insulating layer 643, a first insulating layer 641, and a second insulating layer 642 stacked upward from the substrate surface 63S of the third substrate 63.
  • the upper surface of the second insulating layer 642 constitutes the main chip surface 60S of the transformer chip 60 described above.
  • the first insulating layer 641 is made of a material containing Si, for example. As the material containing Si, SiO 2 (silicon oxide), SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), etc. can be used.
  • the first insulating layer 641 of this embodiment is composed of a plurality of insulating films 641A. Each of the plurality of insulating films 641A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 .
  • the plurality of insulating films 641A may be formed as one insulating film without being distinguished from each other.
  • the second insulating layer 642 is made of, for example, a material containing Si. As the material containing Si, SiO 2 , SiN, SiC, SiCN, etc. can be used.
  • the second insulating layer 642 of this embodiment is composed of a plurality of insulating films 642A. Each of the plurality of insulating films 642A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 .
  • the plurality of insulating films 642A may be formed as one insulating film without being distinguished from each other.
  • the second insulating layer 642 may include a resin layer.
  • the resin layer may be formed from a material containing polyimide (PI), for example.
  • the third insulating layer 643 is made of a material containing Si, for example. As the material containing Si, SiO 2 , SiN, SiC, SiCN, etc. can be used.
  • the third insulating layer 643 of this embodiment is composed of a plurality of insulating films 643A. Each of the plurality of insulating films 643A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 .
  • the plurality of insulating films 643A may be formed as one insulating film without being distinguished from each other.
  • the transformer chip 60 includes a transformer 15, a first capacitor 31, and a second capacitor 32.
  • the transformer 15 includes a first transformer 21 and a second transformer 22.
  • the first transformer 21 and the second transformer 22 are arranged side by side in the x direction in the insulator 64. Both the first transformer 21 and the second transformer 22 are arranged along the chip side surface 604. That is, the first transformer 21 and the second transformer 22 are aligned in the y direction and spaced apart from each other in the x direction. It can also be said that the first transformer 21 and the second transformer 22 are arranged apart from each other in the arrangement direction of the die pads 71, 73, 72 shown in FIG.
  • the first capacitor 31 and the second capacitor 32 are arranged side by side in the x direction in the insulator 64. Both the first capacitor 31 and the second capacitor 32 are arranged along the chip side surface 603. That is, the first capacitor 31 and the second capacitor 32 are aligned in the y direction and spaced apart from each other in the x direction. It can also be said that the first capacitor 31 and the second capacitor 32 are arranged apart from each other in the arrangement direction of the die pads 71, 73, 72 shown in FIG.
  • the first transformer 21 includes a first coil 23 and a second coil 24.
  • the second transformer 22 includes a third coil 25 and a fourth coil 26.
  • the first coil 23 includes a spiral coil portion 23A, a first end portion 23B extending inward from the inner peripheral end of the coil portion 23A, and a first end portion 23B extending inward from the outer peripheral end of the coil portion 23A. and a second end 23C extending outward.
  • the first end 23B and the second end 23C of the first coil 23 are ends that are electrically connected to the primary circuit 13 shown in FIG.
  • the first coil 23 is electrically connected to the first electrode pad 61.
  • the first electrode pad 61 includes an electrode pad 61A electrically connected to the first end 23B of the first coil 23, and an electrode pad 61B electrically connected to the second end 23C of the first coil 23. including.
  • the third coil 25 includes a spiral coil portion 25A, a first end portion 25B extending inward from the inner peripheral end of the coil portion 25A, and a first end portion 25B extending inward from the outer peripheral end of the coil portion 25A. and a second end 25C extending outward.
  • the first end 25B and the second end 25C of the third coil 25 are ends that are electrically connected to the secondary circuit 14 shown in FIG.
  • the third coil 25 is electrically connected to the second electrode pad 62.
  • the second electrode pad 62 includes an electrode pad 62A electrically connected to the first end 25B of the third coil 25, and an electrode pad 62B electrically connected to the second end 25C of the third coil 25. including.
  • the second coil 24 and the fourth coil 26 each have spiral coil portions 24A and 26A.
  • the coil portion 24A of the second coil 24 and the coil portion 26A of the fourth coil 26 are electrically connected to each other by wirings 65C and 65D.
  • the first coil 23 and the second coil 24 are arranged with the first insulating layer 641 in between.
  • the first coil 23 and the second coil 24 are arranged so as to be magnetically coupled in the thickness direction (z direction) of the first insulating layer 641.
  • the first coil 23 is disposed within the second insulating layer 642 above the first insulating layer 641 .
  • the second coil 24 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, the first coil 23 and the second coil 24 are in contact with the first insulating layer 641.
  • the first coil 23 is electrically connected to the first electrode pad 61B by a wiring 65A.
  • the third coil 25 is electrically connected to the second electrode pad 62B by a wiring 65B.
  • the first coil 23 is electrically connected to the first electrode pad 61A shown in FIG. 3 by wiring not shown.
  • the fourth coil 26 is electrically connected to the second electrode pad 62A shown in FIG. 3 by wiring not shown.
  • the third coil 25 and the fourth coil 26 are arranged with the first insulating layer 641 in between.
  • the third coil 25 and the fourth coil 26 are arranged so as to be magnetically coupled in the thickness direction (z direction) of the first insulating layer 641.
  • the third coil 25 is disposed within the second insulating layer 642 above the first insulating layer 641 .
  • the fourth coil 26 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, both the third coil 25 and the fourth coil 26 are in contact with the first insulating layer 641.
  • the first coil 23, the second coil 24, the third coil 25, and the fourth coil 26 are made of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, Ag, Cu, One or more of Al and W (tungsten) is selected as appropriate.
  • each of the coils 23 to 26 is made of a material containing Cu.
  • the wirings 65A to 65D one or more of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, Ag, Cu, Al, and W (tungsten) is appropriately selected. be done.
  • each of the wirings 65A to 65D is formed of a material containing Cu.
  • the first capacitor 31 includes a first electrode plate 33 and a second electrode plate 34.
  • both the first electrode plate 33 and the second electrode plate 34 are formed into a rectangular shape when viewed from the z direction.
  • both the first electrode plate 33 and the second electrode plate 34 can have any shape when viewed from the z direction, such as a circular shape, an elliptical shape, and a polygonal shape.
  • the first electrode plate 33 and the second electrode plate 34 have the same size when viewed from the z direction, and are arranged to overlap with each other.
  • the second capacitor 32 includes a third electrode plate 35 and a fourth electrode plate 36.
  • both the third electrode plate 35 and the fourth electrode plate 36 are formed into a rectangular shape when viewed from the z direction.
  • both the third electrode plate 35 and the fourth electrode plate 36 can have any shape when viewed from the z direction, such as a circular shape, an elliptical shape, and a polygonal shape.
  • the third electrode plate 35 and the fourth electrode plate 36 have the same size when viewed from the z direction, and are arranged to overlap with each other. Further, both the third electrode plate 35 and the fourth electrode plate 36 have the same shape and size as the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction.
  • the first electrode plate 33 of the first capacitor 31 is electrically connected to the first electrode pad 61B by a wiring 66A.
  • the third electrode plate 35 of the second capacitor 32 is electrically connected to the second electrode pad 62B by a wiring 66B.
  • the second electrode plate 34 of the first capacitor 31 and the fourth electrode plate 36 of the second capacitor 32 are electrically connected to each other by a wiring 66C.
  • it is electrically connected to the third substrate 63 by wiring 66C and wiring 66D.
  • the first electrode plate 33, the second electrode plate 34, the third electrode plate 35, and the fourth electrode plate 36 are made of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, One or more of Ag, Cu, Al, and W (tungsten) is selected as appropriate.
  • each of the electrode plates 33 to 36 is made of a material containing Cu.
  • the wirings 66A to 66D one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W is appropriately selected.
  • each of the wirings 66A to 66D is formed of a material containing Cu.
  • the first electrode plate 33 and the second electrode plate 34 of the first capacitor 31 are arranged with the first insulating layer 641 in between.
  • the first electrode plate 33 and the second electrode plate 34 are arranged in the thickness direction of the first insulating layer 641 so as to be magnetically coupled.
  • the first electrode plate 33 is disposed within the second insulating layer 642 above the first insulating layer 641 .
  • the second electrode plate 34 is arranged in the third insulating layer 643 under the first insulating layer 641 .
  • the first electrode plate 33 and the second electrode plate 34 are in contact with the first insulating layer 641.
  • the first electrode plate 33 is electrically connected to the first electrode pad 61 by a wiring 66A.
  • the third electrode plate 35 and the fourth electrode plate 36 are arranged with the first insulating layer 641 in between.
  • the third electrode plate 35 and the fourth electrode plate 36 are arranged in the thickness direction of the first insulating layer 641 so as to be magnetically coupled.
  • the third electrode plate 35 is disposed within the second insulating layer 642 above the first insulating layer 641 .
  • the fourth electrode plate 36 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, both the third electrode plate 35 and the fourth electrode plate 36 are in contact with the first insulating layer 641.
  • the third electrode plate 35 is electrically connected to the second electrode pad 62 by a wiring 66B.
  • the first electrode plate 33 and the second electrode plate 34 have the same size when viewed from the z direction, and are arranged to overlap with each other. Therefore, the first capacitor 31 has the following characteristics: the area of each of the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction, and the distance between the first electrode plate 33 and the second electrode plate 34 (the first insulating It has a capacitance value depending on the thickness T1) of the layer 641.
  • the third electrode plate 35 and the fourth electrode plate 36 have the same size when viewed from the z direction, and are arranged so as to overlap each other. Therefore, the first capacitor 31 has the following characteristics: the area of each of the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction, and the distance between the first electrode plate 33 and the second electrode plate 34 (the first insulating It has a capacitance value depending on the thickness T1) of the layer 641.
  • both the third electrode plate 35 and the fourth electrode plate 36 have the same shape and size as the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction. Therefore, the first capacitor 31 and the second capacitor 32 have the same capacitance value.
  • the first coil 23 and the fourth coil 26 are arranged at the same position in the thickness direction of the insulator 64.
  • the second coil 24 and the third coil 25 are arranged at the same position in the thickness direction of the insulator 64.
  • the distance D1 between the first coil 23 of the first transformer 21 and the third coil 25 of the second transformer 22 is larger than the distance D2 between the first coil 23 and the second coil 24.
  • the distance D1 between the first coil 23 and the third coil 25 is larger than the distance D3 between the third coil 25 and the fourth coil 26.
  • the distance D1 between the first coil 23 and the third coil 25 is larger than the distance D4 between the third substrate 63 and the second coil 24.
  • the distance D1 between the first coil 23 and the third coil 25 is larger than the distance D5 between the third substrate 63 and the fourth coil 26.
  • the distance D6 between the second coil 24 and the second electrode plate 34 is greater than or equal to the distance D4 between the third substrate 63 and the second coil 24.
  • the distance D7 between the fourth coil 26 and the fourth electrode plate 36 is greater than or equal to the distance D5 between the third substrate 63 and the fourth coil 26.
  • FIG. 6 is a schematic cross-sectional view showing a signal transmission device 10X including a transformer chip 60X of a comparative example.
  • the same members as those of the transformer chip 60 and signal transmission device 10 of the above embodiment are given the same reference numerals.
  • the transformer chip 60X of the comparative example does not have the first capacitor 31 and the second capacitor 32, compared to the transformer chip 60 of the above embodiment.
  • the transformer chip 60X of the comparative example is mounted on the intermediate die pad 73, similar to the signal transmission device 10 of the above embodiment.
  • the intermediate die pad 73 and the third substrate 63 electrically connected to the intermediate die pad 73 are in a floating state with respect to the first chip 40 and the second chip 50, the primary die pad 71, and the secondary die pad 72.
  • the potential of the third substrate 63 becomes equal to the potential of the first substrate 43 of the first chip 40 mounted on the primary die pad 71. Therefore, in the transformer chip 60X of the comparative example, the distance between the third substrate 63 and the second transformer 22 (third coil 25) is equal to the potential difference between the primary circuit 13 and the secondary circuit 14; In other words, it is necessary depending on the dielectric strength voltage. In order to increase the dielectric strength of the transformer chip 60X, it is necessary to increase the distance between the third substrate 63 and the second transformer 22 (third coil 25), that is, to increase the thickness of the insulator 64. .
  • the thickness of the insulator 64 influences changes in the process for manufacturing the transformer chip 60X, warping of the third substrate 63 (semiconductor wafer) during manufacturing, and the like. As the insulator 64 becomes thicker, the number of steps increases and the warpage increases. Therefore, there is a limit to increasing the thickness of the insulator 64. A similar problem occurs when the comparative example transformer chip 60X is mounted on the secondary die pad 72.
  • the transformer chip 60X is mounted on an intermediate die pad 73 that is electrically separated from the primary die pad 71 and the secondary die pad 72.
  • the intermediate die pad 73 is in a floating state with respect to the primary die pad 71 and the secondary die pad 72. Therefore, the transformer chip 60X of the comparative example can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
  • the intermediate die pad 73 and the third substrate 63 are in an electrically floating state. Therefore, the potential of the intermediate die pad 73 may be affected by the potential of the primary die pad 71. In this case, it is the same as when the transformer chip 60X of the comparative example is mounted on the primary die pad 71. In other words, since the potential of the third substrate 63 is the same as that of the first chip, the dielectric breakdown voltage of the transformer chip 60X may be exceeded.
  • the transformer chip 60 of this embodiment is mounted on an intermediate die pad 73 electrically separated from the primary die pad 71 and the secondary die pad 72. Therefore, similarly to the comparative example transformer chip 60X shown in FIG. 6, the dielectric strength can be improved without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25. .
  • the transformer chip 60 of this embodiment has a first capacitor 31 electrically connected to a first electrode pad 61, a second electrode pad 62, and electrically connected in series with the first capacitor 31. and a second capacitor 32.
  • the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63 by wirings 66C and 66D as connection parts.
  • the first electrode pad 61 is electrically connected to the first chip 40.
  • the second electrode pad 62 is electrically connected to the second chip 50. Therefore, the potential of the third substrate 63 is between the potential of the first electrode pad 61 and the potential of the second electrode pad 62.
  • the capacitance value of the first capacitor 31 and the capacitance value of the second capacitor 32 are equal to each other. Therefore, the potential of the third substrate 63 becomes an intermediate potential (1/2) between the potential of the first electrode pad 61 and the potential of the second electrode pad 62. That is, in this embodiment, the third substrate 63 of the transformer chip 60 is not in a floating state, but has a potential between the voltages applied to the first electrode pad 61 and the second electrode pad 62.
  • the transformer chip 60 of this embodiment can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
  • the transformer chip 60 is mounted on an intermediate die pad 73 electrically separated from the primary die pad 71 and the secondary die pad 72. Therefore, the dielectric strength can be improved without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
  • the potentials of the third substrate 63 and the intermediate die pad 73 of the transformer chip 60 are the same as those of the first chip 40 (primary side circuit 13) and the second chip 50 connected to the first electrode pad 61. (secondary side circuit 14). Therefore, it becomes less susceptible to the influence of the potential of the primary die pad 71 on which the first chip 40, which is on the high voltage side, is mounted. Therefore, the transformer chip 60 can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
  • the configuration of the transformer chip 60 of the above embodiment can be changed as appropriate.
  • the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63 by wirings 67A and 67B, respectively.
  • the second electrode plate 34 of the first capacitor 31 is electrically connected to the third substrate 63 by a wiring 67A.
  • the fourth electrode plate 36 of the second capacitor 32 is electrically connected to the third substrate 63 by a wiring 67B. That is, the first capacitor 31 and the second capacitor 32 are connected to each other via the third substrate 63 and the wirings 67A and 67B.
  • the potential of the third substrate 63 can be set to an intermediate voltage between the voltages applied to the first electrode pad 61B and the second electrode pad 62B, respectively. Therefore, the dielectric strength of the transformer chip 60A can be improved.
  • the transformer chip 60B of the signal transmission device 112 shown in FIG. has been done.
  • the first electrode pad 61B and the second electrode pad 62B are in contact with the first insulating layer 641.
  • the transformer chip 60B also includes a first opposing electrode 68A that faces the first electrode pad 61B with the first insulating layer 641 in between, and a second opposing electrode that faces the second electrode pad 62B with the first insulating layer 641 in between. 68B.
  • the first opposing electrode 68A and the second opposing electrode 68B are electrically connected to each other by a wiring 66C.
  • the wiring 66C is connected to the third substrate 63 by a wiring 66D.
  • the first capacitor 31 includes a first electrode pad 61B and a first counter electrode 68A, which sandwich a first insulating layer 641 therebetween.
  • the second capacitor 32 is composed of a second electrode pad 62B and a second opposing electrode 68B, which sandwich the first insulating layer 641 therebetween. Also in the transformer chip 60B configured in this manner, the potential of the third substrate 63 can be set to an intermediate voltage between the voltages applied to the first electrode pad 61B and the second electrode pad 62B, respectively. Therefore, the dielectric strength of the transformer chip 60B can be improved.
  • the signal transmission device 114 (signal transmission circuit 114A) shown in FIG. 9 has two transformers 15A and 15B between the primary side circuit 13 and the secondary side circuit 14.
  • the two transformers 15A and 15B have the same configuration as the transformer 15 of the above embodiment, and each includes a first transformer 21 and a second transformer 22. These two transformers 15A and 15B are used, for example, to transmit a signal from the secondary circuit 14 to the primary circuit 13. Note that the two transformers 15A and 15B may be used to transmit signals from the primary circuit 13 to the secondary circuit 14.
  • the transformer 15A is used to transmit a signal from the secondary circuit 14 to the primary circuit 13, and the transformer 15B is used to transmit a signal from the primary circuit 13 to the secondary circuit 14. May be used for.
  • the two transformers 15A and 15B may use two transformer chips 60 of the above embodiment, or may be configured as one transformer chip. Note that three or more transformers may be provided between the primary circuit 13 and the secondary circuit 14.
  • the term “on” includes both “on” and “above” unless the context clearly indicates otherwise.
  • the phrase “the first layer is formed on the second layer” refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term “on” does not exclude structures in which other layers are formed between the first layer and the second layer.
  • the Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. Accordingly, various structures according to the present disclosure (e.g., the structure shown in FIG. 1) are different from each other in that "upper” and “lower” in the Z-axis direction described herein are “upper” and “lower” in the vertical direction. Not limited to one thing.
  • the X-axis direction may be a vertical direction
  • the Y-axis direction may be a vertical direction.
  • the first capacitor (31) includes a first electrode plate (33) provided within the insulator (64) and electrically connected to the first connection electrode (61B), and the insulator (64). a second electrode plate (34) provided therein and disposed opposite to the first electrode plate (33) with the first insulating layer (641) interposed therebetween;
  • the second capacitor (32) includes a third electrode plate (35) provided within the insulator (64) and electrically connected to the second connection electrode (62B), and the insulator (64).
  • a fourth electrode plate (36) provided therein and disposed opposite to the third electrode plate (35) with the first insulating layer (641) interposed therebetween;
  • the connecting portions (66C, 66D, 67A, 67B) connect the second electrode plate (34) and the fourth electrode plate (36) to the substrate (63).
  • the transformer chip according to appendix 1 or appendix 2.
  • the first capacitor (31) is located at a position opposite to the first connection electrode (61B) via the first insulating layer (641) in the insulator (64).
  • the second capacitor (32) is located at a position opposite to the second connection electrode (62B) through the first insulating layer (641) in the insulator (64).
  • a second opposing electrode (68B) provided in the The connection portion (66C, 66D) connects the first counter electrode (68A) and the second counter electrode (68B) to the substrate (63).
  • the transformer chip according to appendix 1 or appendix 2.
  • the first coil (23) is connected to the first connection electrode (61B),
  • the third coil (25) is connected to the second connection electrode (62B), the second coil (24) and the fourth coil (26) are connected to each other;
  • the transformer chip according to any one of Supplementary notes 1 to 4.
  • the insulator (64) includes a second insulating layer (642) above the first insulating layer (641) and a third insulating layer (643) below the first insulating layer (641),
  • the first coil (23) and the third coil (25) are arranged within the second insulating layer (642), the second coil (24) and the fourth coil (26) are arranged within the third insulating layer (643);
  • the transformer chip according to any one of Supplementary notes 1 to 5.
  • the transformer chip (60) is a conductive substrate (63); an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63); A first coil (23) and a second coil (24) are arranged to sandwich the first insulating layer (641) and are arranged to be magnetically coupled in the thickness direction of the first insulating layer (641).
  • the first capacitor (31) includes a first electrode plate (33) provided within the insulator (64) and electrically connected to the first connection electrode (61B), and the insulator (64). a second electrode plate (34) provided therein and disposed opposite to the first electrode plate (33) with the first insulating layer (641) interposed therebetween;
  • the second capacitor (32) includes a third electrode plate (35) provided within the insulator (64) and electrically connected to the second connection electrode (62B), and the insulator (64).
  • a fourth electrode plate (36) provided therein and disposed opposite to the third electrode plate (35) with the first insulating layer (641) interposed therebetween;
  • the connecting portion connects the second electrode plate (34) and the fourth electrode plate (36) to the substrate (63).
  • the first capacitor (31) is located at a position opposite to the first connection electrode (61B) via the first insulating layer (641) in the insulator (64).
  • the second capacitor (32) is located at a position opposite to the second connection electrode (62B) through the first insulating layer (641) in the insulator (64).
  • a second opposing electrode (68B) provided in the The connection portion connects the first counter electrode (68A) and the second counter electrode (68B) to the substrate (63).
  • the first coil (23) is connected to the first connection electrode (61B),
  • the third coil (25) is connected to the second connection electrode (62B), the second coil (24) and the fourth coil (26) are connected to each other;
  • the signal transmission device according to any one of Supplementary notes 7 to 11.
  • the insulator (64) includes a second insulating layer (642) above the first insulating layer (641) and a third insulating layer (643) below the first insulating layer (641),
  • the first coil (23) and the third coil (25) are arranged within the second insulating layer (642), the second coil (24) and the fourth coil (26) are arranged within the third insulating layer (643);
  • the signal transmission device according to any one of attachments 7 to 12.
  • the transformer chip (60) is a conductive substrate (63); an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63); A first coil (23) and a second coil (24) are arranged to sandwich the first insulating layer (641) and are arranged to be magnetically coupled in the thickness direction of the first insulating layer (641).

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Publication number Priority date Publication date Assignee Title
JP2022101068A (ja) * 2020-12-24 2022-07-06 ローム株式会社 ゲートドライバ
WO2022163347A1 (ja) * 2021-01-29 2022-08-04 ローム株式会社 トランスチップ、信号伝達装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022101068A (ja) * 2020-12-24 2022-07-06 ローム株式会社 ゲートドライバ
WO2022163347A1 (ja) * 2021-01-29 2022-08-04 ローム株式会社 トランスチップ、信号伝達装置

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