WO2024043105A1 - Transformer chip and signal transmission device - Google Patents

Transformer chip and signal transmission device Download PDF

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Publication number
WO2024043105A1
WO2024043105A1 PCT/JP2023/029140 JP2023029140W WO2024043105A1 WO 2024043105 A1 WO2024043105 A1 WO 2024043105A1 JP 2023029140 W JP2023029140 W JP 2023029140W WO 2024043105 A1 WO2024043105 A1 WO 2024043105A1
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Prior art keywords
chip
transformer
coil
insulating layer
electrode
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PCT/JP2023/029140
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French (fr)
Japanese (ja)
Inventor
普之 井ノ口
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ローム株式会社
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Publication of WO2024043105A1 publication Critical patent/WO2024043105A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F19/00—Fixed transformers or mutual inductances of the signal type
    • H01F19/04—Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

Definitions

  • the present disclosure relates to a transformer chip and a signal transmission device.
  • an insulated gate driver that applies a gate voltage to the gate of a switching element such as a transistor is known.
  • a structure is known that includes a first coil and a second coil that are arranged to face each other in the thickness direction of the element insulating layer in the element insulating layer (for example, (See Patent Document 1).
  • insulated chips such as those described above may be required to have improved dielectric strength.
  • a transformer chip that is one aspect of the present disclosure includes a conductive substrate, an insulator provided on the substrate and including a first insulating layer arranged parallel to the substrate, and sandwiching the first insulating layer.
  • a first transformer including a first coil and a second coil, which are arranged with the first insulating layer sandwiched therebetween, and which include a first coil and a second coil which are arranged so as to be magnetically coupled in the thickness direction of the first insulating layer;
  • a second transformer including a third coil and a fourth coil arranged so as to be magnetically coupled in the thickness direction of one insulating layer, and a second transformer electrically connected to the first transformer; and the insulation transformer.
  • first connection electrode and a second connection electrode that are electrically connected to and used for electrical connection with the outside; a first capacitor that is electrically connected to the first connection electrode; and a second connection electrode. and a second capacitor electrically connected in series with the first capacitor, and a connection portion that electrically connects the first capacitor and the second capacitor to the substrate.
  • a signal transmission device includes a first chip including a first circuit, a transformer chip, and at least one of transmitting and receiving a signal with the first circuit through the transformer chip.
  • the transformer includes a third coil and a fourth coil that are arranged to sandwich the first insulating layer and are arranged to be magnetically coupled in the thickness direction of the first insulating layer, and are electrically connected to the first transformer.
  • a second transformer a first connection electrode and a second connection electrode that are electrically connected to the insulation transformer and used for electrical connection with the outside; and a first connection electrode and a second connection electrode that are electrically connected to the first connection electrode.
  • a second capacitor electrically connected to the second connection electrode and electrically connected in series with the first capacitor; A connection part that electrically connects to the substrate.
  • transformer chip and signal transmission device that are one aspect of the present disclosure, it is possible to improve the dielectric strength.
  • FIG. 1 is a circuit diagram schematically showing a circuit configuration of a signal transmission device according to an embodiment.
  • FIG. 2 is a schematic cross-sectional view of a signal transmission device of one embodiment.
  • 3 is a schematic plan view of the transformer chip of FIG. 2.
  • FIG. 4 is a schematic plan view of the transformer chip of FIG. 2 in a different position from FIG. 3.
  • FIG. 5 is a schematic cross-sectional view of the transformer chip of FIG. 2.
  • FIG. 6 is a schematic cross-sectional view of a signal transmission device of a comparative example.
  • FIG. 7 is a schematic cross-sectional view of a signal transmission device according to a modification.
  • FIG. 8 is a schematic cross-sectional view of a modified example of the signal transmission device.
  • FIG. 9 is a circuit diagram schematically showing a circuit configuration of a signal transmission device according to a modified example.
  • the expression “at least one” as used herein means “one or more” of the desired options.
  • the expression “at least one” as used herein means “only one option” or “both of the two options” if the number of options is two.
  • the expression “at least one” as used herein means “only one option” or “any combination of two or more options” if there are three or more options. means.
  • FIG. 1 shows a simplified example of the circuit configuration of the signal transmission device 10.
  • FIG. 2 shows an example of a schematic cross-sectional structure showing the internal structure of a part of the signal transmission device 10.
  • the signal transmission device 10 is a device that transmits signals while electrically insulating between the primary terminal 11 and the secondary terminal 12.
  • Signal transmission device 10 is, for example, a digital isolator.
  • the signal transmission device 10 includes a primary circuit 13 electrically connected to a primary terminal 11, a secondary circuit 14 electrically connected to a secondary terminal 12, and a primary circuit 13.
  • the signal transmission circuit 10A includes a transformer 15 that electrically isolates the secondary circuit 14 from the signal transmission circuit 10A.
  • the primary side circuit 13 corresponds to a "first circuit”
  • the secondary side circuit 14 corresponds to a "second circuit”.
  • the transformer 15 corresponds to an "insulation transformer".
  • the primary side circuit 13 is a circuit configured to operate when the first voltage V1 is applied.
  • the secondary side circuit 14 is a circuit configured to operate when a second voltage V2 different from the first voltage V1 is applied.
  • the first voltage V1 and the second voltage V2 are different voltages.
  • the first voltage V1 is higher than, for example, the second voltage V2.
  • the first voltage V1 and the second voltage V2 are DC voltages.
  • the ground of the primary circuit 13 and the ground of the secondary circuit 14 are provided independently.
  • the primary side circuit 13 is electrically connected via the primary side terminal 11 to, for example, a drive circuit to be controlled by a control device.
  • An example of a drive circuit is a switching circuit.
  • the secondary circuit 14 is electrically connected to, for example, an external control device (not shown) via the secondary terminal 12.
  • a control signal from the control device is input to the secondary circuit 14 via the secondary terminal 12.
  • the output signal of the secondary circuit 14 is transmitted to the primary circuit 13 via the transformer 15.
  • the signal transmitted to the primary circuit 13 is output from the primary circuit 13 to the drive circuit via the primary terminal 11.
  • the primary side circuit 13 and the secondary side circuit 14 are electrically insulated by the transformer 15. More specifically, the transformer 15 is configured to regulate the transmission of DC voltage between the primary side circuit 13 and the secondary side circuit 14, while being able to transmit pulse signals.
  • the state where the primary side circuit 13 and the secondary side circuit 14 are insulated refers to the state where the transmission of DC voltage is cut off between the primary side circuit 13 and the secondary side circuit 14. This means that transmission of pulse signals from the primary circuit 13 to the secondary circuit 14 is permitted.
  • the primary side circuit 13 is configured to perform at least one of transmitting and receiving signals with the secondary side circuit 14.
  • the dielectric strength voltage of the signal transmission device 10 is, for example, 5000 Vrms or more and 15000 Vrms or less.
  • the dielectric strength voltage of the signal transmission device 10 of this embodiment is about 10,000 Vrms.
  • the specific numerical value of the dielectric strength voltage of the signal transmission device 10 is not limited to this and is arbitrary.
  • the signal transmission device 10 of this embodiment has one signal transmission path between the primary side circuit 13 and the secondary side circuit 14 by a transformer 15.
  • the signal transmission device 10 includes primary signal lines 16A, 16B that connect the primary circuit 13 and the transformer 15, secondary signal lines 17A, 17B that connect the transformer 15 and the secondary circuit 14, including.
  • the transformer 15 transmits the first signal from the primary circuit 13 to the secondary circuit 14 while electrically insulating the primary circuit 13 and the secondary circuit 14.
  • the transformer 15 includes a first transformer 21 and a second transformer 22 that are connected in series.
  • the first transformer 21 corresponds to a "first insulating element”
  • the second transformer 22 corresponds to a "second insulating element”.
  • the signal transmission device 10 includes a pair of connection signal lines 18A and 18B that connect the first transformer 21 and the second transformer 22.
  • the dielectric strength voltage of each transformer 21 and 22 in this embodiment is, for example, 2500 Vrms or more and 7500 Vrms or less. Note that the dielectric strength voltage of each transformer 21 and 22 may be 2500 Vrms or more and 5700 Vrms or less. However, the specific numerical value of the dielectric strength voltage of each transformer 21, 22 is not limited to this and is arbitrary.
  • the first transformer 21 has a first coil 23 and a second coil 24 that is electrically insulated from the first coil 23 and can be magnetically coupled.
  • the second transformer 22 includes a third coil 25 and a fourth coil 26 that is electrically insulated from the third coil 25 and can be magnetically coupled.
  • the first coil 23 is electrically connected to the primary circuit 13 by primary signal lines 16A and 16B.
  • the second coil 24 is connected to the fourth coil 26 by a pair of connection signal lines 18A and 18B.
  • the second coil 24 and the fourth coil 26 are connected to each other so as to be electrically floating.
  • the first end of the second coil 24 and the first end of the fourth coil 26 are connected by a connection signal line 18A
  • the second end of the second coil 24 and the second end of the fourth coil 26 are connected to each other by a connection signal line 18A. and is connected by a connection signal line 18B.
  • the second coil 24 and the fourth coil 26 serve as relay coils that relay the first signal between the first coil 23 and the third coil 25.
  • the third coil 25 is electrically connected to the secondary circuit 14 by secondary signal lines 17A and 17B.
  • FIG. 2 shows an example of a schematic cross-sectional structure showing the internal structure of a part of the signal transmission device 10.
  • the signal transmission device 10 is a semiconductor device in which a plurality of semiconductor chips are packaged into one package.
  • the package format of the signal transmission device 10 is, for example, an SO (Small Outline) system, and in this embodiment is an SOP (Small Outline Package). Note that the package format of the signal transmission device 10 can be changed arbitrarily.
  • the signal transmission device 10 includes a first chip 40, a second chip 50, and a transformer chip 60 as a plurality of semiconductor chips.
  • the signal transmission device 10 also includes a primary die pad 71 on which the first chip 40 is mounted, a secondary die pad 72 on which the second chip 50 is mounted, and an intermediate die pad 73 on which the transformer chip 60 is mounted.
  • the intermediate die pad 73 is insulated from both the primary die pad 71 and the secondary die pad 72.
  • the signal transmission device 10 includes a sealing resin 90 that seals each die pad 71 , 72 , 73 and each chip 40 , 50 , 60 .
  • the transformer chip 60 corresponds to an "insulating chip”.
  • the primary die pad 71 corresponds to a "first die pad”
  • the secondary die pad 72 corresponds to a "second die pad”
  • the intermediate die pad 73 corresponds to a "third die pad.”
  • the sealing resin 90 is made of an electrically insulating material, for example, black epoxy resin.
  • the sealing resin 90 is formed into a rectangular plate shape with the thickness direction in the z direction.
  • the primary die pad 71, the secondary die pad 72, and the intermediate die pad 73 are made of a conductive material.
  • each die pad 71, 72, 73 is formed of a material containing Cu (copper).
  • each die pad 71, 72, 73 may be formed of other metal materials such as Al (aluminum).
  • the material constituting each die pad 71, 72, 73 is not limited to a conductive material.
  • each die pad 71, 72, 73 may be made of ceramic such as alumina. That is, each die pad 71, 72, 73 may be formed of a material having electrical insulation properties.
  • the primary die pad 71, intermediate die pad 73, and secondary die pad 72 are arranged side by side and spaced apart from each other.
  • the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 are electrically insulated from each other. Therefore, the intermediate die pad 73 is in an electrically floating state with respect to the primary die pad 71 and the secondary die pad 72.
  • the arrangement direction of the primary die pad 71, intermediate die pad 73, and secondary die pad 72 is defined as the x direction.
  • the direction orthogonal to the x direction is defined as the y direction.
  • the x direction corresponds to the "first direction”
  • the y direction corresponds to the "second direction”.
  • the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 are formed into a flat plate shape.
  • the shape of each die pad 71, 72, 73 when viewed from the z direction is a rectangular shape with the short side in the x direction and the long side in the y direction.
  • the area of the secondary die pad 72 viewed from the z direction is larger than the area of the primary die pad 71 viewed from the z direction.
  • the shape of each die pad 71, 72, 73 viewed from the z direction can be changed arbitrarily.
  • the shape of each die pad 71, 72, 73 viewed from the z direction may be a rectangle with the long side in the x direction and the short side in the y direction.
  • the transformer chip 60 is mounted on the intermediate die pad 73. That is, the first chip 40, the transformer chip 60, and the second chip 50 are mounted on the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72, respectively, which are electrically insulated from each other. It can be said that the first chip 40, the transformer chip 60, and the second chip 50 are arranged apart from each other in the x direction. In this embodiment, the first chip 40, the transformer chip 60, and the second chip 50 are arranged in this order from the primary die pad 71 toward the secondary die pad 72 in the x direction. In other words, the transformer chip 60 is arranged between the first chip 40 and the second chip 50 in the x direction. In this embodiment, each die pad 71 , 72 , 73 is not exposed from the sealing resin 90 .
  • the distance between the primary die pad 71 and the intermediate die pad 73 in the x direction is equal to the distance between the intermediate die pad 73 and the secondary die pad 72 in the x direction. Therefore, when viewed from the z direction, the distance between the first chip 40 and the transformer chip 60 in the x direction is equal to the distance between the transformer chip 60 and the second chip 50 in the x direction. In other words, the transformer chip 60 is placed intermediate between the first chip 40 and the second chip 50.
  • the first chip 40 has a rectangular shape having short sides and long sides when viewed from the z direction. When viewed from the z direction, the first chip 40 is mounted on the primary die pad 71 so that the short side runs along the x direction and the long side runs along the y direction.
  • the first chip 40 includes a first substrate 43 on which the primary circuit 13 is formed.
  • the first substrate 43 is, for example, a semiconductor substrate.
  • An example of the semiconductor substrate is a substrate made of a material containing Si (silicon).
  • a wiring layer 44 is formed on the first substrate 43.
  • the wiring layer 44 includes a plurality of insulating films laminated in the z-direction, a metal layer provided between adjacent insulating films in the z-direction, and a via that penetrates the insulating film in the z-direction and is connected to the metal layer. It has The metal layer constitutes the wiring pattern of the first chip 40.
  • the first chip 40 has a chip main surface 40S and a chip back surface 40R facing oppositely to each other in the z direction.
  • the first substrate 43 constitutes the back surface 40R of the chip
  • the wiring layer 44 constitutes the main surface 40S of the chip.
  • the chip back surface 40R faces the primary die pad 71.
  • a plurality of first electrode pads 41 and a plurality of second electrode pads 42 are provided on the chip main surface 40S side of the first chip 40. More specifically, each electrode pad 41, 42 is provided so as to be exposed from the chip main surface 40S.
  • Each electrode pad 41 , 42 is electrically connected to the primary circuit 13 through a wiring layer 44 .
  • the plurality of first electrode pads 41 are arranged on the opposite side of the transformer chip 60 with respect to the center of the chip main surface 40S in the x direction of the chip main surface 40S. Although not shown, the plurality of first electrode pads 41 are arranged apart from each other in the y direction.
  • the plurality of second electrode pads 42 are arranged closer to the transformer chip 60 with respect to the center of the chip main surface 40S in the x direction of the chip main surface 40S. Although not shown, the plurality of second electrode pads 42 are arranged apart from each other in the y direction.
  • the first chip 40 is bonded to the primary die pad 71 by a first bonding material 81. More specifically, a first bonding material 81 is interposed between the chip back surface 40R and the primary die pad 71. The first bonding material 81 bonds the chip back surface 40R and the primary die pad 71.
  • the first bonding material 81 is a conductive bonding material such as solder or Ag (silver) paste.
  • the first bonding material 81 bonds the first substrate 43 of the first chip 40 and the primary die pad 71. Thereby, the first substrate 43 and the primary die pad 71 are electrically connected. Therefore, the primary circuit 13 is electrically connected to the primary die pad 71 via the first bonding material 81.
  • the primary die pad 71 constitutes a ground for the primary circuit 13.
  • the shape of the second chip 50 is a rectangle having short sides and long sides when viewed from the z direction. When viewed from the z direction, the second chip 50 is mounted on the secondary die pad 72 so that the short side runs along the x direction and the long side runs along the y direction.
  • the second chip 50 includes a second substrate 53 on which the secondary circuit 14 is formed.
  • the second substrate 53 is, for example, a semiconductor substrate.
  • An example of a semiconductor substrate is a Si substrate.
  • a wiring layer 54 is formed on the second substrate 53.
  • the wiring layer 54 includes a plurality of insulating films laminated in the z-direction, a metal layer provided between adjacent insulating films in the z-direction, and vias that penetrate the insulating films in the z-direction and are connected to the metal layer. It has .
  • the metal layer constitutes the wiring pattern of the second chip 50.
  • the second chip 50 has a chip main surface 50S and a chip back surface 50R facing oppositely to each other in the z direction.
  • the second substrate 53 constitutes the back surface 50R of the chip
  • the wiring layer 54 constitutes the main surface 50S of the chip.
  • the chip back surface 50R faces the secondary die pad 72.
  • the chip back surface 50R faces the same side as the chip back surface 40R of the first chip 40
  • the chip main surface 50S faces the same side as the chip main surface 40S of the first chip 40.
  • a plurality of first electrode pads 51 and a plurality of second electrode pads 52 are provided on the chip main surface 50S side of the second chip 50. More specifically, each electrode pad 51, 52 is provided so as to be exposed from the chip main surface 50S.
  • Each electrode pad 51, 52 is electrically connected to the secondary circuit 14 by, for example, a wiring layer 54.
  • the plurality of first electrode pads 51 are arranged closer to the transformer chip 60 with respect to the center of the chip main surface 50S in the x direction of the chip main surface 50S. Although not shown, the plurality of first electrode pads 51 are arranged apart from each other in the y direction.
  • the plurality of second electrode pads 52 are arranged on the opposite side of the transformer chip 60 with respect to the center of the chip main surface 50S in the x direction of the chip main surface 50S. Although not shown, the plurality of second electrode pads 52 are arranged apart from each other in the y direction.
  • the second chip 50 is bonded to the secondary die pad 72 by a second bonding material 82. More specifically, the second bonding material 82 is interposed between the chip back surface 50R and the secondary die pad 72. The second bonding material 82 bonds the chip back surface 50R and the secondary die pad 72.
  • the second bonding material 82 is a conductive bonding material such as solder or Ag paste. In this embodiment, the second bonding material 82 is made of the same material as the first bonding material 81, for example.
  • the second bonding material 82 bonds the second substrate 53 of the second chip 50 and the secondary die pad 72 . Thereby, the second substrate 53 and the secondary die pad 72 are electrically connected. Therefore, the secondary circuit 14 is electrically connected to the secondary die pad 72 via the second bonding material 82.
  • the secondary die pad 72 constitutes a ground for the secondary circuit 14.
  • the transformer chip 60 has a rectangular shape having short sides and long sides when viewed from the z direction. In this embodiment, when viewed from the z direction, the transformer chip 60 is mounted on the secondary die pad 72 so that the long side runs along the y direction and the short side runs along the x direction.
  • the transformer chip 60 includes a third substrate 63.
  • the third substrate 63 is, for example, a semiconductor substrate.
  • An example of a semiconductor substrate is a Si substrate.
  • the transformer chip 60 includes an insulator 64 on a third substrate 63.
  • the transformer chip 60 includes the transformer 15 (first transformer 21, second transformer 22). Further, the transformer chip 60 includes a first capacitor 31 and a second capacitor 32. The transformer 15, the first capacitor 31, and the second capacitor 32 are embedded in the insulator 64.
  • the transformer chip 60 has a chip main surface 60S and a chip back surface 60R facing oppositely to each other in the z direction.
  • the chip back surface 60R faces the secondary die pad 72. That is, the chip back surface 60R faces the same side as the chip back surface 50R of the second chip 50, and the chip main surface 60S faces the same side as the chip main surface 50S of the second chip 50.
  • the transformer chip 60 includes a plurality of first electrode pads 61 and a plurality of second electrode pads 62. Each first electrode pad 61 and each second electrode pad 62 are provided on the chip main surface 60S side. More specifically, when viewed from the z direction, each electrode pad 61, 62 is provided so as to be exposed from the chip main surface 60S.
  • the plurality of first electrode pads 61 are arranged closer to the first chip 40 with respect to the center of the chip main surface 60S in the x direction of the chip main surface 60S.
  • the plurality of second electrode pads 62 are arranged closer to the second chip 50 with respect to the center of the chip main surface 60S in the x direction of the chip main surface 60S.
  • the first transformer 21 and the second transformer 22 of the transformer 15 are connected in series between the first electrode pad 61 and the second electrode pad 62.
  • the first capacitor 31 and the second capacitor 32 are connected in series between the first electrode pad 61 and the second electrode pad 62. Further, the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63.
  • the first electrode pad 61 corresponds to a "first connection electrode.”
  • the second electrode pad 62 corresponds to a "second connection electrode.”
  • the transformer chip 60 is bonded to the intermediate die pad 73 by a third bonding material 83. More specifically, a third bonding material 83 is interposed between the chip back surface 60R and the intermediate die pad 73. The third bonding material 83 bonds the chip back surface 60R and the intermediate die pad 73.
  • the third bonding material 83 is a conductive bonding material such as solder or Ag (silver) paste. The third bonding material 83 bonds the third substrate 63 of the transformer chip 60 and the intermediate die pad 73. Thereby, the third substrate 63 and the intermediate die pad 73 are electrically connected.
  • wires W1 to W4 are connected to each of the first chip 40, transformer chip 60, and second chip 50.
  • Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor such as Au (gold), Al, or Cu.
  • the plurality of first electrode pads 41 of the first chip 40 are individually connected to a plurality of primary leads (not shown) by a plurality of wires W1.
  • the primary lead is a component that constitutes the primary terminal 11 in FIG. Thereby, the primary side circuit 13 and the primary side terminal 11 are electrically connected.
  • the primary lead is made of the same material as the primary die pad 71, for example.
  • the primary lead and the primary die pad 71 may be integrally formed.
  • the primary-side leads are arranged at a distance from the primary-side die pad 71 on the side opposite to the secondary-side die pad 72, and are formed across the sealing resin 90. That is, the primary lead has a portion that protrudes outward from the sealing resin 90. A portion of the primary lead that protrudes outward from the sealing resin 90 constitutes an external terminal of the signal transmission device 10.
  • the plurality of second electrode pads 42 of the first chip 40 are individually connected to the plurality of first electrode pads 61 of the transformer chip 60 by a plurality of wires W2. Thereby, the primary circuit 13 and the first transformer 21 are electrically connected. That is, the wiring layer 44 of the first chip 40, the plurality of second electrode pads 42, the plurality of wires W2, and the plurality of first electrode pads 61 are each connected to one of the primary signal lines 16A, 16B (see FIG. 1). It makes up the department.
  • the plurality of second electrode pads 62 of the transformer chip 60 are individually connected to the plurality of first electrode pads 51 of the second chip 50 by a plurality of wires W3. Thereby, the second transformer 22 and the secondary circuit 14 are electrically connected. That is, the plurality of second electrode pads 62, the plurality of wires W3, and the plurality of first electrode pads 51 of the second chip 50 each constitute a part of the secondary signal lines 17A, 17B (see FIG. 1). ing.
  • the plurality of second electrode pads 52 of the second chip 50 are individually connected to a plurality of secondary leads (not shown) by a plurality of wires W4.
  • the secondary lead is a component that constitutes the secondary terminal 12 in FIG. Thereby, the secondary side circuit 14 and the secondary side terminal 12 are electrically connected.
  • the secondary leads are made of the same material as the secondary die pad 72, for example.
  • the secondary lead and the secondary die pad 72 may be integrally formed.
  • the secondary leads are arranged at a distance from the secondary die pad 72 on the opposite side of the primary die pad 71 and are formed across the sealing resin 90 . That is, the secondary lead has a portion that protrudes outward from the sealing resin 90. A portion of the secondary lead that protrudes outward from the sealing resin 90 constitutes an external terminal of the signal transmission device 10.
  • FIG. 3 is a plan view schematically showing the planar structure of the transformer chip 60.
  • FIG. 4 is a cross-sectional view schematically showing the cross-sectional structure of the inside of the transformer chip 60 taken along the xy plane. In FIG. 4, hatching lines are omitted from the viewpoint of ease of viewing the drawing.
  • FIG. 5 is a cross-sectional view schematically showing the cross-sectional structure of the transformer chip 60. As shown in FIG. Further, since the coils 23, 24, 25, 26 shown in FIG. 5 are shown schematically, they are not consistent with the configurations of the coils 23, 24, 25, 26 shown in FIGS. 3 and 4. .
  • the transformer chip 60 is the transformer 15 integrated into one chip. That is, the transformer chip 60 is a chip dedicated to the transformer 15 that is provided separately from the first chip 40 and the second chip 50.
  • the transformer chip 60 includes a chip main surface 60S, a chip back surface 60R, and a plurality of chip side surfaces 601, 602, 603, and 604.
  • the chip side surfaces 601 to 604 are perpendicular to both the chip main surface 60S and the chip back surface 60R.
  • Chip side surfaces 601 and 602 constitute end surfaces of the transformer chip 60 in the x direction.
  • Chip side surfaces 603 and 604 constitute end surfaces of the transformer chip 60 in the y direction.
  • a chip side surface 601 of the transformer chip 60 faces the first chip 40 shown in FIG. 2
  • a chip side surface 602 of the transformer chip 60 faces the second chip 50 shown in FIG.
  • the direction from the chip back surface 60R of the transformer chip 60 to the chip main surface 60S will be referred to as the upper side
  • the direction from the chip main surface 60S to the chip rear surface 60R will be referred to as the lower side.
  • the transformer chip 60 includes a third substrate 63 and an insulator 64 disposed on the third substrate 63.
  • the third substrate 63 has a substrate front surface 63S and a substrate back surface 63R facing oppositely to each other in the z direction.
  • the third substrate 63 is formed of, for example, a semiconductor substrate.
  • the third substrate 63 is a semiconductor substrate made of a material containing Si.
  • the third substrate 63 may be made of a wide bandgap semiconductor or a compound semiconductor as a semiconductor substrate.
  • the third substrate 63 may be an insulating substrate formed of a material containing glass or an insulating substrate formed of a material containing ceramics such as alumina.
  • a wide band gap semiconductor is a semiconductor substrate having a band gap of 2.0 eV or more.
  • the wide bandgap semiconductor may be SiC (silicon carbide).
  • the compound semiconductor may be a III-V compound semiconductor.
  • the compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).
  • the insulator 64 includes a first insulating layer 641, a second insulating layer 642 provided on the first insulating layer 641, and a third insulating layer 643 provided below the first insulating layer 641. .
  • the first insulating layer 641 is arranged parallel to the third substrate 63.
  • the first insulating layer 641 and the second insulating layer 642 are in contact with each other.
  • the first insulating layer 641 and the third insulating layer 643 are in contact with each other.
  • the third insulating layer 643 is in contact with the substrate surface 63S of the third substrate 63.
  • the insulator 64 includes a third insulating layer 643, a first insulating layer 641, and a second insulating layer 642 stacked upward from the substrate surface 63S of the third substrate 63.
  • the upper surface of the second insulating layer 642 constitutes the main chip surface 60S of the transformer chip 60 described above.
  • the first insulating layer 641 is made of a material containing Si, for example. As the material containing Si, SiO 2 (silicon oxide), SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), etc. can be used.
  • the first insulating layer 641 of this embodiment is composed of a plurality of insulating films 641A. Each of the plurality of insulating films 641A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 .
  • the plurality of insulating films 641A may be formed as one insulating film without being distinguished from each other.
  • the second insulating layer 642 is made of, for example, a material containing Si. As the material containing Si, SiO 2 , SiN, SiC, SiCN, etc. can be used.
  • the second insulating layer 642 of this embodiment is composed of a plurality of insulating films 642A. Each of the plurality of insulating films 642A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 .
  • the plurality of insulating films 642A may be formed as one insulating film without being distinguished from each other.
  • the second insulating layer 642 may include a resin layer.
  • the resin layer may be formed from a material containing polyimide (PI), for example.
  • the third insulating layer 643 is made of a material containing Si, for example. As the material containing Si, SiO 2 , SiN, SiC, SiCN, etc. can be used.
  • the third insulating layer 643 of this embodiment is composed of a plurality of insulating films 643A. Each of the plurality of insulating films 643A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 .
  • the plurality of insulating films 643A may be formed as one insulating film without being distinguished from each other.
  • the transformer chip 60 includes a transformer 15, a first capacitor 31, and a second capacitor 32.
  • the transformer 15 includes a first transformer 21 and a second transformer 22.
  • the first transformer 21 and the second transformer 22 are arranged side by side in the x direction in the insulator 64. Both the first transformer 21 and the second transformer 22 are arranged along the chip side surface 604. That is, the first transformer 21 and the second transformer 22 are aligned in the y direction and spaced apart from each other in the x direction. It can also be said that the first transformer 21 and the second transformer 22 are arranged apart from each other in the arrangement direction of the die pads 71, 73, 72 shown in FIG.
  • the first capacitor 31 and the second capacitor 32 are arranged side by side in the x direction in the insulator 64. Both the first capacitor 31 and the second capacitor 32 are arranged along the chip side surface 603. That is, the first capacitor 31 and the second capacitor 32 are aligned in the y direction and spaced apart from each other in the x direction. It can also be said that the first capacitor 31 and the second capacitor 32 are arranged apart from each other in the arrangement direction of the die pads 71, 73, 72 shown in FIG.
  • the first transformer 21 includes a first coil 23 and a second coil 24.
  • the second transformer 22 includes a third coil 25 and a fourth coil 26.
  • the first coil 23 includes a spiral coil portion 23A, a first end portion 23B extending inward from the inner peripheral end of the coil portion 23A, and a first end portion 23B extending inward from the outer peripheral end of the coil portion 23A. and a second end 23C extending outward.
  • the first end 23B and the second end 23C of the first coil 23 are ends that are electrically connected to the primary circuit 13 shown in FIG.
  • the first coil 23 is electrically connected to the first electrode pad 61.
  • the first electrode pad 61 includes an electrode pad 61A electrically connected to the first end 23B of the first coil 23, and an electrode pad 61B electrically connected to the second end 23C of the first coil 23. including.
  • the third coil 25 includes a spiral coil portion 25A, a first end portion 25B extending inward from the inner peripheral end of the coil portion 25A, and a first end portion 25B extending inward from the outer peripheral end of the coil portion 25A. and a second end 25C extending outward.
  • the first end 25B and the second end 25C of the third coil 25 are ends that are electrically connected to the secondary circuit 14 shown in FIG.
  • the third coil 25 is electrically connected to the second electrode pad 62.
  • the second electrode pad 62 includes an electrode pad 62A electrically connected to the first end 25B of the third coil 25, and an electrode pad 62B electrically connected to the second end 25C of the third coil 25. including.
  • the second coil 24 and the fourth coil 26 each have spiral coil portions 24A and 26A.
  • the coil portion 24A of the second coil 24 and the coil portion 26A of the fourth coil 26 are electrically connected to each other by wirings 65C and 65D.
  • the first coil 23 and the second coil 24 are arranged with the first insulating layer 641 in between.
  • the first coil 23 and the second coil 24 are arranged so as to be magnetically coupled in the thickness direction (z direction) of the first insulating layer 641.
  • the first coil 23 is disposed within the second insulating layer 642 above the first insulating layer 641 .
  • the second coil 24 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, the first coil 23 and the second coil 24 are in contact with the first insulating layer 641.
  • the first coil 23 is electrically connected to the first electrode pad 61B by a wiring 65A.
  • the third coil 25 is electrically connected to the second electrode pad 62B by a wiring 65B.
  • the first coil 23 is electrically connected to the first electrode pad 61A shown in FIG. 3 by wiring not shown.
  • the fourth coil 26 is electrically connected to the second electrode pad 62A shown in FIG. 3 by wiring not shown.
  • the third coil 25 and the fourth coil 26 are arranged with the first insulating layer 641 in between.
  • the third coil 25 and the fourth coil 26 are arranged so as to be magnetically coupled in the thickness direction (z direction) of the first insulating layer 641.
  • the third coil 25 is disposed within the second insulating layer 642 above the first insulating layer 641 .
  • the fourth coil 26 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, both the third coil 25 and the fourth coil 26 are in contact with the first insulating layer 641.
  • the first coil 23, the second coil 24, the third coil 25, and the fourth coil 26 are made of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, Ag, Cu, One or more of Al and W (tungsten) is selected as appropriate.
  • each of the coils 23 to 26 is made of a material containing Cu.
  • the wirings 65A to 65D one or more of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, Ag, Cu, Al, and W (tungsten) is appropriately selected. be done.
  • each of the wirings 65A to 65D is formed of a material containing Cu.
  • the first capacitor 31 includes a first electrode plate 33 and a second electrode plate 34.
  • both the first electrode plate 33 and the second electrode plate 34 are formed into a rectangular shape when viewed from the z direction.
  • both the first electrode plate 33 and the second electrode plate 34 can have any shape when viewed from the z direction, such as a circular shape, an elliptical shape, and a polygonal shape.
  • the first electrode plate 33 and the second electrode plate 34 have the same size when viewed from the z direction, and are arranged to overlap with each other.
  • the second capacitor 32 includes a third electrode plate 35 and a fourth electrode plate 36.
  • both the third electrode plate 35 and the fourth electrode plate 36 are formed into a rectangular shape when viewed from the z direction.
  • both the third electrode plate 35 and the fourth electrode plate 36 can have any shape when viewed from the z direction, such as a circular shape, an elliptical shape, and a polygonal shape.
  • the third electrode plate 35 and the fourth electrode plate 36 have the same size when viewed from the z direction, and are arranged to overlap with each other. Further, both the third electrode plate 35 and the fourth electrode plate 36 have the same shape and size as the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction.
  • the first electrode plate 33 of the first capacitor 31 is electrically connected to the first electrode pad 61B by a wiring 66A.
  • the third electrode plate 35 of the second capacitor 32 is electrically connected to the second electrode pad 62B by a wiring 66B.
  • the second electrode plate 34 of the first capacitor 31 and the fourth electrode plate 36 of the second capacitor 32 are electrically connected to each other by a wiring 66C.
  • it is electrically connected to the third substrate 63 by wiring 66C and wiring 66D.
  • the first electrode plate 33, the second electrode plate 34, the third electrode plate 35, and the fourth electrode plate 36 are made of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, One or more of Ag, Cu, Al, and W (tungsten) is selected as appropriate.
  • each of the electrode plates 33 to 36 is made of a material containing Cu.
  • the wirings 66A to 66D one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W is appropriately selected.
  • each of the wirings 66A to 66D is formed of a material containing Cu.
  • the first electrode plate 33 and the second electrode plate 34 of the first capacitor 31 are arranged with the first insulating layer 641 in between.
  • the first electrode plate 33 and the second electrode plate 34 are arranged in the thickness direction of the first insulating layer 641 so as to be magnetically coupled.
  • the first electrode plate 33 is disposed within the second insulating layer 642 above the first insulating layer 641 .
  • the second electrode plate 34 is arranged in the third insulating layer 643 under the first insulating layer 641 .
  • the first electrode plate 33 and the second electrode plate 34 are in contact with the first insulating layer 641.
  • the first electrode plate 33 is electrically connected to the first electrode pad 61 by a wiring 66A.
  • the third electrode plate 35 and the fourth electrode plate 36 are arranged with the first insulating layer 641 in between.
  • the third electrode plate 35 and the fourth electrode plate 36 are arranged in the thickness direction of the first insulating layer 641 so as to be magnetically coupled.
  • the third electrode plate 35 is disposed within the second insulating layer 642 above the first insulating layer 641 .
  • the fourth electrode plate 36 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, both the third electrode plate 35 and the fourth electrode plate 36 are in contact with the first insulating layer 641.
  • the third electrode plate 35 is electrically connected to the second electrode pad 62 by a wiring 66B.
  • the first electrode plate 33 and the second electrode plate 34 have the same size when viewed from the z direction, and are arranged to overlap with each other. Therefore, the first capacitor 31 has the following characteristics: the area of each of the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction, and the distance between the first electrode plate 33 and the second electrode plate 34 (the first insulating It has a capacitance value depending on the thickness T1) of the layer 641.
  • the third electrode plate 35 and the fourth electrode plate 36 have the same size when viewed from the z direction, and are arranged so as to overlap each other. Therefore, the first capacitor 31 has the following characteristics: the area of each of the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction, and the distance between the first electrode plate 33 and the second electrode plate 34 (the first insulating It has a capacitance value depending on the thickness T1) of the layer 641.
  • both the third electrode plate 35 and the fourth electrode plate 36 have the same shape and size as the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction. Therefore, the first capacitor 31 and the second capacitor 32 have the same capacitance value.
  • the first coil 23 and the fourth coil 26 are arranged at the same position in the thickness direction of the insulator 64.
  • the second coil 24 and the third coil 25 are arranged at the same position in the thickness direction of the insulator 64.
  • the distance D1 between the first coil 23 of the first transformer 21 and the third coil 25 of the second transformer 22 is larger than the distance D2 between the first coil 23 and the second coil 24.
  • the distance D1 between the first coil 23 and the third coil 25 is larger than the distance D3 between the third coil 25 and the fourth coil 26.
  • the distance D1 between the first coil 23 and the third coil 25 is larger than the distance D4 between the third substrate 63 and the second coil 24.
  • the distance D1 between the first coil 23 and the third coil 25 is larger than the distance D5 between the third substrate 63 and the fourth coil 26.
  • the distance D6 between the second coil 24 and the second electrode plate 34 is greater than or equal to the distance D4 between the third substrate 63 and the second coil 24.
  • the distance D7 between the fourth coil 26 and the fourth electrode plate 36 is greater than or equal to the distance D5 between the third substrate 63 and the fourth coil 26.
  • FIG. 6 is a schematic cross-sectional view showing a signal transmission device 10X including a transformer chip 60X of a comparative example.
  • the same members as those of the transformer chip 60 and signal transmission device 10 of the above embodiment are given the same reference numerals.
  • the transformer chip 60X of the comparative example does not have the first capacitor 31 and the second capacitor 32, compared to the transformer chip 60 of the above embodiment.
  • the transformer chip 60X of the comparative example is mounted on the intermediate die pad 73, similar to the signal transmission device 10 of the above embodiment.
  • the intermediate die pad 73 and the third substrate 63 electrically connected to the intermediate die pad 73 are in a floating state with respect to the first chip 40 and the second chip 50, the primary die pad 71, and the secondary die pad 72.
  • the potential of the third substrate 63 becomes equal to the potential of the first substrate 43 of the first chip 40 mounted on the primary die pad 71. Therefore, in the transformer chip 60X of the comparative example, the distance between the third substrate 63 and the second transformer 22 (third coil 25) is equal to the potential difference between the primary circuit 13 and the secondary circuit 14; In other words, it is necessary depending on the dielectric strength voltage. In order to increase the dielectric strength of the transformer chip 60X, it is necessary to increase the distance between the third substrate 63 and the second transformer 22 (third coil 25), that is, to increase the thickness of the insulator 64. .
  • the thickness of the insulator 64 influences changes in the process for manufacturing the transformer chip 60X, warping of the third substrate 63 (semiconductor wafer) during manufacturing, and the like. As the insulator 64 becomes thicker, the number of steps increases and the warpage increases. Therefore, there is a limit to increasing the thickness of the insulator 64. A similar problem occurs when the comparative example transformer chip 60X is mounted on the secondary die pad 72.
  • the transformer chip 60X is mounted on an intermediate die pad 73 that is electrically separated from the primary die pad 71 and the secondary die pad 72.
  • the intermediate die pad 73 is in a floating state with respect to the primary die pad 71 and the secondary die pad 72. Therefore, the transformer chip 60X of the comparative example can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
  • the intermediate die pad 73 and the third substrate 63 are in an electrically floating state. Therefore, the potential of the intermediate die pad 73 may be affected by the potential of the primary die pad 71. In this case, it is the same as when the transformer chip 60X of the comparative example is mounted on the primary die pad 71. In other words, since the potential of the third substrate 63 is the same as that of the first chip, the dielectric breakdown voltage of the transformer chip 60X may be exceeded.
  • the transformer chip 60 of this embodiment is mounted on an intermediate die pad 73 electrically separated from the primary die pad 71 and the secondary die pad 72. Therefore, similarly to the comparative example transformer chip 60X shown in FIG. 6, the dielectric strength can be improved without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25. .
  • the transformer chip 60 of this embodiment has a first capacitor 31 electrically connected to a first electrode pad 61, a second electrode pad 62, and electrically connected in series with the first capacitor 31. and a second capacitor 32.
  • the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63 by wirings 66C and 66D as connection parts.
  • the first electrode pad 61 is electrically connected to the first chip 40.
  • the second electrode pad 62 is electrically connected to the second chip 50. Therefore, the potential of the third substrate 63 is between the potential of the first electrode pad 61 and the potential of the second electrode pad 62.
  • the capacitance value of the first capacitor 31 and the capacitance value of the second capacitor 32 are equal to each other. Therefore, the potential of the third substrate 63 becomes an intermediate potential (1/2) between the potential of the first electrode pad 61 and the potential of the second electrode pad 62. That is, in this embodiment, the third substrate 63 of the transformer chip 60 is not in a floating state, but has a potential between the voltages applied to the first electrode pad 61 and the second electrode pad 62.
  • the transformer chip 60 of this embodiment can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
  • the transformer chip 60 is mounted on an intermediate die pad 73 electrically separated from the primary die pad 71 and the secondary die pad 72. Therefore, the dielectric strength can be improved without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
  • the potentials of the third substrate 63 and the intermediate die pad 73 of the transformer chip 60 are the same as those of the first chip 40 (primary side circuit 13) and the second chip 50 connected to the first electrode pad 61. (secondary side circuit 14). Therefore, it becomes less susceptible to the influence of the potential of the primary die pad 71 on which the first chip 40, which is on the high voltage side, is mounted. Therefore, the transformer chip 60 can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
  • the configuration of the transformer chip 60 of the above embodiment can be changed as appropriate.
  • the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63 by wirings 67A and 67B, respectively.
  • the second electrode plate 34 of the first capacitor 31 is electrically connected to the third substrate 63 by a wiring 67A.
  • the fourth electrode plate 36 of the second capacitor 32 is electrically connected to the third substrate 63 by a wiring 67B. That is, the first capacitor 31 and the second capacitor 32 are connected to each other via the third substrate 63 and the wirings 67A and 67B.
  • the potential of the third substrate 63 can be set to an intermediate voltage between the voltages applied to the first electrode pad 61B and the second electrode pad 62B, respectively. Therefore, the dielectric strength of the transformer chip 60A can be improved.
  • the transformer chip 60B of the signal transmission device 112 shown in FIG. has been done.
  • the first electrode pad 61B and the second electrode pad 62B are in contact with the first insulating layer 641.
  • the transformer chip 60B also includes a first opposing electrode 68A that faces the first electrode pad 61B with the first insulating layer 641 in between, and a second opposing electrode that faces the second electrode pad 62B with the first insulating layer 641 in between. 68B.
  • the first opposing electrode 68A and the second opposing electrode 68B are electrically connected to each other by a wiring 66C.
  • the wiring 66C is connected to the third substrate 63 by a wiring 66D.
  • the first capacitor 31 includes a first electrode pad 61B and a first counter electrode 68A, which sandwich a first insulating layer 641 therebetween.
  • the second capacitor 32 is composed of a second electrode pad 62B and a second opposing electrode 68B, which sandwich the first insulating layer 641 therebetween. Also in the transformer chip 60B configured in this manner, the potential of the third substrate 63 can be set to an intermediate voltage between the voltages applied to the first electrode pad 61B and the second electrode pad 62B, respectively. Therefore, the dielectric strength of the transformer chip 60B can be improved.
  • the signal transmission device 114 (signal transmission circuit 114A) shown in FIG. 9 has two transformers 15A and 15B between the primary side circuit 13 and the secondary side circuit 14.
  • the two transformers 15A and 15B have the same configuration as the transformer 15 of the above embodiment, and each includes a first transformer 21 and a second transformer 22. These two transformers 15A and 15B are used, for example, to transmit a signal from the secondary circuit 14 to the primary circuit 13. Note that the two transformers 15A and 15B may be used to transmit signals from the primary circuit 13 to the secondary circuit 14.
  • the transformer 15A is used to transmit a signal from the secondary circuit 14 to the primary circuit 13, and the transformer 15B is used to transmit a signal from the primary circuit 13 to the secondary circuit 14. May be used for.
  • the two transformers 15A and 15B may use two transformer chips 60 of the above embodiment, or may be configured as one transformer chip. Note that three or more transformers may be provided between the primary circuit 13 and the secondary circuit 14.
  • the term “on” includes both “on” and “above” unless the context clearly indicates otherwise.
  • the phrase “the first layer is formed on the second layer” refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term “on” does not exclude structures in which other layers are formed between the first layer and the second layer.
  • the Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. Accordingly, various structures according to the present disclosure (e.g., the structure shown in FIG. 1) are different from each other in that "upper” and “lower” in the Z-axis direction described herein are “upper” and “lower” in the vertical direction. Not limited to one thing.
  • the X-axis direction may be a vertical direction
  • the Y-axis direction may be a vertical direction.
  • the first capacitor (31) includes a first electrode plate (33) provided within the insulator (64) and electrically connected to the first connection electrode (61B), and the insulator (64). a second electrode plate (34) provided therein and disposed opposite to the first electrode plate (33) with the first insulating layer (641) interposed therebetween;
  • the second capacitor (32) includes a third electrode plate (35) provided within the insulator (64) and electrically connected to the second connection electrode (62B), and the insulator (64).
  • a fourth electrode plate (36) provided therein and disposed opposite to the third electrode plate (35) with the first insulating layer (641) interposed therebetween;
  • the connecting portions (66C, 66D, 67A, 67B) connect the second electrode plate (34) and the fourth electrode plate (36) to the substrate (63).
  • the transformer chip according to appendix 1 or appendix 2.
  • the first capacitor (31) is located at a position opposite to the first connection electrode (61B) via the first insulating layer (641) in the insulator (64).
  • the second capacitor (32) is located at a position opposite to the second connection electrode (62B) through the first insulating layer (641) in the insulator (64).
  • a second opposing electrode (68B) provided in the The connection portion (66C, 66D) connects the first counter electrode (68A) and the second counter electrode (68B) to the substrate (63).
  • the transformer chip according to appendix 1 or appendix 2.
  • the first coil (23) is connected to the first connection electrode (61B),
  • the third coil (25) is connected to the second connection electrode (62B), the second coil (24) and the fourth coil (26) are connected to each other;
  • the transformer chip according to any one of Supplementary notes 1 to 4.
  • the insulator (64) includes a second insulating layer (642) above the first insulating layer (641) and a third insulating layer (643) below the first insulating layer (641),
  • the first coil (23) and the third coil (25) are arranged within the second insulating layer (642), the second coil (24) and the fourth coil (26) are arranged within the third insulating layer (643);
  • the transformer chip according to any one of Supplementary notes 1 to 5.
  • the transformer chip (60) is a conductive substrate (63); an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63); A first coil (23) and a second coil (24) are arranged to sandwich the first insulating layer (641) and are arranged to be magnetically coupled in the thickness direction of the first insulating layer (641).
  • the first capacitor (31) includes a first electrode plate (33) provided within the insulator (64) and electrically connected to the first connection electrode (61B), and the insulator (64). a second electrode plate (34) provided therein and disposed opposite to the first electrode plate (33) with the first insulating layer (641) interposed therebetween;
  • the second capacitor (32) includes a third electrode plate (35) provided within the insulator (64) and electrically connected to the second connection electrode (62B), and the insulator (64).
  • a fourth electrode plate (36) provided therein and disposed opposite to the third electrode plate (35) with the first insulating layer (641) interposed therebetween;
  • the connecting portion connects the second electrode plate (34) and the fourth electrode plate (36) to the substrate (63).
  • the first capacitor (31) is located at a position opposite to the first connection electrode (61B) via the first insulating layer (641) in the insulator (64).
  • the second capacitor (32) is located at a position opposite to the second connection electrode (62B) through the first insulating layer (641) in the insulator (64).
  • a second opposing electrode (68B) provided in the The connection portion connects the first counter electrode (68A) and the second counter electrode (68B) to the substrate (63).
  • the first coil (23) is connected to the first connection electrode (61B),
  • the third coil (25) is connected to the second connection electrode (62B), the second coil (24) and the fourth coil (26) are connected to each other;
  • the signal transmission device according to any one of Supplementary notes 7 to 11.
  • the insulator (64) includes a second insulating layer (642) above the first insulating layer (641) and a third insulating layer (643) below the first insulating layer (641),
  • the first coil (23) and the third coil (25) are arranged within the second insulating layer (642), the second coil (24) and the fourth coil (26) are arranged within the third insulating layer (643);
  • the signal transmission device according to any one of attachments 7 to 12.
  • the transformer chip (60) is a conductive substrate (63); an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63); A first coil (23) and a second coil (24) are arranged to sandwich the first insulating layer (641) and are arranged to be magnetically coupled in the thickness direction of the first insulating layer (641).

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Abstract

In the present invention, a transformer chip includes: an insulating body that is provided on a substrate; an isolation transformer; a first connection electrode and a second connection electrode; a first capacitor; a second capacitor; and a connection portion. The isolation transformer has a first transformer that includes a first coil and a second coil that are arranged with a first insulating layer of the insulating body interposed therebetween, and a second transformer that includes a third coil and a fourth coil that are arranged with the first insulating layer interposed therebetween. The first connection electrode and the second connection electrode are electrically connected to the isolation transformer. The first capacitor is electrically connected to the first connection electrode. The second capacitor is electrically connected to the second connection electrode. The connection portion electrically connects the first capacitor and the second capacitor to the substrate.

Description

トランスチップ、信号伝達装置Transformer chip, signal transmission device
　本開示は、トランスチップ、信号伝達装置に関するものである。 The present disclosure relates to a transformer chip and a signal transmission device.
　信号伝達装置の一例として、トランジスタ等のスイッチング素子のゲートにゲート電圧を印加する絶縁型のゲートドライバが知られている。このようなゲートドライバに用いられる絶縁チップの一例として、素子絶縁層内において、素子絶縁層の厚さ方向に互いに対向配置された第１コイルおよび第２コイルを含む構造が知られている（たとえば特許文献１参照）。 As an example of a signal transmission device, an insulated gate driver that applies a gate voltage to the gate of a switching element such as a transistor is known. As an example of an insulating chip used in such a gate driver, a structure is known that includes a first coil and a second coil that are arranged to face each other in the thickness direction of the element insulating layer in the element insulating layer (for example, (See Patent Document 1).
特開２０１８－７８１６９号公報JP 2018-78169 Publication
　ところで、上記のような絶縁チップでは、絶縁耐圧の向上が要求される場合がある。 Incidentally, insulated chips such as those described above may be required to have improved dielectric strength.
　本開示の一態様であるトランスチップは、導電性を有する基板と、前記基板上に設けられ、前記基板と平行に配置される第１絶縁層を含む絶縁体と、前記第１絶縁層を挟んで配置されるとともに前記第１絶縁層の厚さ方向に磁気結合可能に配置された第１コイルおよび第２コイルを含む第１トランスと、前記第１絶縁層を挟んで配置されるとともに前記第１絶縁層の厚さ方向に磁気結合可能に配置された第３コイルおよび第４コイルを含み且つ前記第１トランスと電気的に接続された第２トランスと、を有する絶縁トランスと、前記絶縁トランスに電気的に接続され、外部との電気的な接続に用いられる第１接続電極および第２接続電極と、前記第１接続電極と電気的に接続された第１キャパシタと、前記第２接続電極と電気的に接続され、前記第１キャパシタと電気的に直列に接続された第２キャパシタと、前記第１キャパシタおよび前記第２キャパシタを前記基板に電気的に接続する接続部と、を含む。 A transformer chip that is one aspect of the present disclosure includes a conductive substrate, an insulator provided on the substrate and including a first insulating layer arranged parallel to the substrate, and sandwiching the first insulating layer. a first transformer including a first coil and a second coil, which are arranged with the first insulating layer sandwiched therebetween, and which include a first coil and a second coil which are arranged so as to be magnetically coupled in the thickness direction of the first insulating layer; a second transformer including a third coil and a fourth coil arranged so as to be magnetically coupled in the thickness direction of one insulating layer, and a second transformer electrically connected to the first transformer; and the insulation transformer. a first connection electrode and a second connection electrode that are electrically connected to and used for electrical connection with the outside; a first capacitor that is electrically connected to the first connection electrode; and a second connection electrode. and a second capacitor electrically connected in series with the first capacitor, and a connection portion that electrically connects the first capacitor and the second capacitor to the substrate.
　また、本開示の別の一態様である信号伝達装置は、第１回路を含む第１チップと、トランスチップと、前記トランスチップを通して前記第１回路と信号の送信および受信の少なくとも一方を行うように構成された第２回路を含む第２チップと、前記第１チップが実装された第１ダイパッドと、前記第２チップが実装された第２ダイパッドと、前記第１ダイパッドおよび前記第２ダイパッドの双方と絶縁され、前記トランスチップが実装された第３ダイパッドと、を含み、前記トランスチップは、導電性を有する基板と、前記基板上に設けられ、前記基板と平行に配置される第１絶縁層を含む絶縁体と、前記第１絶縁層を挟んで配置されるとともに前記第１絶縁層の厚さ方向に磁気結合可能に配置された第１コイルおよび第２コイルを含む第１トランスと、前記第１絶縁層を挟んで配置されるとともに前記第１絶縁層の厚さ方向に磁気結合可能に配置された第３コイルおよび第４コイルを含み且つ前記第１トランスと電気的に接続された第２トランスと、を有する絶縁トランスと、前記絶縁トランスに電気的に接続され、外部との電気的な接続に用いられる第１接続電極および第２接続電極と、前記第１接続電極と電気的に接続された第１キャパシタと、前記第２接続電極と電気的に接続され、前記第１キャパシタと電気的に直列に接続された第２キャパシタと、前記第１キャパシタおよび前記第２キャパシタを前記基板に電気的に接続する接続部と、を含む。 Further, a signal transmission device according to another aspect of the present disclosure includes a first chip including a first circuit, a transformer chip, and at least one of transmitting and receiving a signal with the first circuit through the transformer chip. a second die pad on which the first chip is mounted; a second die pad on which the second chip is mounted; a third die pad on which the transformer chip is mounted and insulated from both of the die pads; a first transformer including a first coil and a second coil arranged to sandwich the first insulating layer and magnetically coupled in the thickness direction of the first insulating layer; The transformer includes a third coil and a fourth coil that are arranged to sandwich the first insulating layer and are arranged to be magnetically coupled in the thickness direction of the first insulating layer, and are electrically connected to the first transformer. a second transformer; a first connection electrode and a second connection electrode that are electrically connected to the insulation transformer and used for electrical connection with the outside; and a first connection electrode and a second connection electrode that are electrically connected to the first connection electrode. a second capacitor electrically connected to the second connection electrode and electrically connected in series with the first capacitor; A connection part that electrically connects to the substrate.
　本開示の一態様であるトランスチップ、信号伝達装置によれば、絶縁耐圧の向上を図ることができる。 According to the transformer chip and signal transmission device that are one aspect of the present disclosure, it is possible to improve the dielectric strength.
図１は、一実施形態の信号伝達装置の回路構成を模式的に示す回路図である。FIG. 1 is a circuit diagram schematically showing a circuit configuration of a signal transmission device according to an embodiment. 図２は、一実施形態の信号伝達装置の概略断面図である。FIG. 2 is a schematic cross-sectional view of a signal transmission device of one embodiment. 図３は、図２のトランスチップの概略平面図である。3 is a schematic plan view of the transformer chip of FIG. 2. FIG. 図４は、図３と異なる位置における図２のトランスチップの概略平面図である。4 is a schematic plan view of the transformer chip of FIG. 2 in a different position from FIG. 3. FIG. 図５は、図２のトランスチップの概略断面図である。FIG. 5 is a schematic cross-sectional view of the transformer chip of FIG. 2. 図６は、比較例の信号伝達装置の概略断面図である。FIG. 6 is a schematic cross-sectional view of a signal transmission device of a comparative example. 図７は、変更例の信号伝達装置の概略断面図である。FIG. 7 is a schematic cross-sectional view of a signal transmission device according to a modification. 図８は、変更例の信号伝達装置の概略断面図である。FIG. 8 is a schematic cross-sectional view of a modified example of the signal transmission device. 図９は、変更例の信号伝達装置の回路構成を模式的に示す回路図である。FIG. 9 is a circuit diagram schematically showing a circuit configuration of a signal transmission device according to a modified example.
　以下、添付図面を参照して本開示の半導体装置のいくつかの実施形態を説明する。なお、説明を簡単かつ明確にするために、図面に示される構成要素は必ずしも一定の縮尺で描かれていない。また、理解を容易にするために、断面図では、ハッチング線が省略されている場合がある。添付の図面は、本開示の実施形態を例示するに過ぎず、本開示を制限するものとみなされるべきではない。本開示における「第１」、「第２」、「第３」等の用語は、単に対象物を区別するために用いられており、対象物を順位づけするものではない。 Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. It should be noted that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Further, in order to facilitate understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the disclosure and should not be considered as limiting the disclosure. Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects, and are not intended to rank the objects.
　以下の詳細な記載は、本開示の例示的な実施形態を具体化する装置、システム、および方法を含む。この詳細な記載は本来説明のためのものに過ぎず、本開示の実施形態またはこのような実施形態の適用および使用を限定することを意図しない。 The following detailed description includes devices, systems, and methods that embody example embodiments of the present disclosure. This detailed description is illustrative in nature and is not intended to limit the embodiments of the disclosure or the application and uses of such embodiments.
　本明細書において使用される「少なくとも１つ」という表現は、所望の選択肢の「１つ以上」を意味する。一例として、本明細書において使用される「少なくとも１つ」という表現は、選択肢の数が２つであれば「１つの選択肢のみ」または「２つの選択肢の双方」を意味する。他の例として、本明細書において使用される「少なくとも１つ」という表現は、選択肢の数が３つ以上であれば「１つの選択肢のみ」または「２つ以上の任意の選択肢の組み合わせ」を意味する。 The expression "at least one" as used herein means "one or more" of the desired options. As an example, the expression "at least one" as used herein means "only one option" or "both of the two options" if the number of options is two. As another example, the expression "at least one" as used herein means "only one option" or "any combination of two or more options" if there are three or more options. means.
　（信号伝達装置の概略構成）
　図１および図２を参照して、一実施形態の信号伝達装置１０の概略構成について説明する。図１は、信号伝達装置１０の回路構成の一例を簡略化して示している。図２は、信号伝達装置１０の一部の内部構成を示す模式的な断面構造の一例を示している。なお、図２では、便宜上、ハッチング線を省略している。 (Schematic configuration of signal transmission device)
A schematic configuration of a signal transmission device 10 according to an embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 shows a simplified example of the circuit configuration of the signal transmission device 10. As shown in FIG. FIG. 2 shows an example of a schematic cross-sectional structure showing the internal structure of a part of the signal transmission device 10. As shown in FIG. Note that, in FIG. 2, hatching lines are omitted for convenience.
　図１に示されるように、信号伝達装置１０は、１次側端子１１と２次側端子１２との間を電気的に絶縁しつつ信号を伝達する装置である。信号伝達装置１０は、たとえばデジタルアイソレータである。信号伝達装置１０は、１次側端子１１に電気的に接続された１次側回路１３と、２次側端子１２に電気的に接続された２次側回路１４と、１次側回路１３と２次側回路１４とを電気的に絶縁するトランス１５と、を有する信号伝達回路１０Ａを含む。１次側回路１３は「第１回路」に対応し、２次側回路１４は「第２回路」に対応している。トランス１５は「絶縁トランス」に対応している。 As shown in FIG. 1, the signal transmission device 10 is a device that transmits signals while electrically insulating between the primary terminal 11 and the secondary terminal 12. Signal transmission device 10 is, for example, a digital isolator. The signal transmission device 10 includes a primary circuit 13 electrically connected to a primary terminal 11, a secondary circuit 14 electrically connected to a secondary terminal 12, and a primary circuit 13. The signal transmission circuit 10A includes a transformer 15 that electrically isolates the secondary circuit 14 from the signal transmission circuit 10A. The primary side circuit 13 corresponds to a "first circuit", and the secondary side circuit 14 corresponds to a "second circuit". The transformer 15 corresponds to an "insulation transformer".
　１次側回路１３は、第１電圧Ｖ１が印加されることによって動作するように構成された回路である。２次側回路１４は、第１電圧Ｖ１とは異なる第２電圧Ｖ２が印加されることによって動作するように構成された回路である。第１電圧Ｖ１と第２電圧Ｖ２は、互いに異なる電圧である。たとえば、第１電圧Ｖ１は、たとえば第２電圧Ｖ２よりも高い。第１電圧Ｖ１および第２電圧Ｖ２は直流電圧である。本実施形態では、１次側回路１３のグランドと２次側回路１４のグランドとのそれぞれが独立して設けられている。 The primary side circuit 13 is a circuit configured to operate when the first voltage V1 is applied. The secondary side circuit 14 is a circuit configured to operate when a second voltage V2 different from the first voltage V1 is applied. The first voltage V1 and the second voltage V2 are different voltages. For example, the first voltage V1 is higher than, for example, the second voltage V2. The first voltage V1 and the second voltage V2 are DC voltages. In this embodiment, the ground of the primary circuit 13 and the ground of the secondary circuit 14 are provided independently.
　１次側回路１３は、１次側端子１１を介して、たとえば制御装置の制御対象となる駆動回路に電気的に接続されている。駆動回路の一例は、スイッチング回路である。２次側回路１４は、２次側端子１２を介してたとえば外部の制御装置（図示略）に電気的に接続されている。 The primary side circuit 13 is electrically connected via the primary side terminal 11 to, for example, a drive circuit to be controlled by a control device. An example of a drive circuit is a switching circuit. The secondary circuit 14 is electrically connected to, for example, an external control device (not shown) via the secondary terminal 12.
　信号伝達回路１０Ａにおいては、制御装置からの制御信号が２次側端子１２を介して２次側回路１４に入力される。２次側回路１４の出力信号は、トランス１５を介して１次側回路１３に伝達される。そして、１次側回路１３に伝達された信号は、１次側回路１３から１次側端子１１を介して駆動回路に出力される。 In the signal transmission circuit 10A, a control signal from the control device is input to the secondary circuit 14 via the secondary terminal 12. The output signal of the secondary circuit 14 is transmitted to the primary circuit 13 via the transformer 15. The signal transmitted to the primary circuit 13 is output from the primary circuit 13 to the drive circuit via the primary terminal 11.
　上述のとおり、信号伝達回路１０Ａは、トランス１５によって１次側回路１３と２次側回路１４とが電気的に絶縁されている。より詳細には、トランス１５は、１次側回路１３と２次側回路１４との間における直流電圧の伝達を規制する一方、パルス信号の伝達を可能に構成されている。 As described above, in the signal transmission circuit 10A, the primary side circuit 13 and the secondary side circuit 14 are electrically insulated by the transformer 15. More specifically, the transformer 15 is configured to regulate the transmission of DC voltage between the primary side circuit 13 and the secondary side circuit 14, while being able to transmit pulse signals.
　すなわち、１次側回路１３と２次側回路１４とが絶縁されている状態とは、１次側回路１３と２次側回路１４との間において、直流電圧の伝達が遮断されている状態を意味し、１次側回路１３から２次側回路１４へのパルス信号の伝達については許容している。このように、１次側回路１３は、２次側回路１４と信号の送信および受信の少なくとも一方を行うように構成されている。 In other words, the state where the primary side circuit 13 and the secondary side circuit 14 are insulated refers to the state where the transmission of DC voltage is cut off between the primary side circuit 13 and the secondary side circuit 14. This means that transmission of pulse signals from the primary circuit 13 to the secondary circuit 14 is permitted. In this way, the primary side circuit 13 is configured to perform at least one of transmitting and receiving signals with the secondary side circuit 14.
　信号伝達装置１０の絶縁耐圧は、たとえば５０００Ｖｒｍｓ以上１５０００Ｖｒｍｓ以下である。本実施形態の信号伝達装置１０の絶縁耐圧は、１００００Ｖｒｍｓ程度である。ただし、信号伝達装置１０の絶縁耐圧の具体的な数値はこれに限られず任意である。 The dielectric strength voltage of the signal transmission device 10 is, for example, 5000 Vrms or more and 15000 Vrms or less. The dielectric strength voltage of the signal transmission device 10 of this embodiment is about 10,000 Vrms. However, the specific numerical value of the dielectric strength voltage of the signal transmission device 10 is not limited to this and is arbitrary.
　（信号伝達装置の詳細）
　本実施形態の信号伝達装置１０は、１次側回路１３と２次側回路１４との間に、トランス１５によって１つの信号伝達経路を有している。信号伝達装置１０は、１次側回路１３とトランス１５とを接続する１次側信号線１６Ａ，１６Ｂと、トランス１５と２次側回路１４とを接続する２次側信号線１７Ａ，１７Ｂと、を含む。トランス１５は、１次側回路１３から２次側回路１４に第１信号を伝達する一方、１次側回路１３と２次側回路１４とを電気的に絶縁している。 (Details of signal transmission device)
The signal transmission device 10 of this embodiment has one signal transmission path between the primary side circuit 13 and the secondary side circuit 14 by a transformer 15. The signal transmission device 10 includes primary signal lines 16A, 16B that connect the primary circuit 13 and the transformer 15, secondary signal lines 17A, 17B that connect the transformer 15 and the secondary circuit 14, including. The transformer 15 transmits the first signal from the primary circuit 13 to the secondary circuit 14 while electrically insulating the primary circuit 13 and the secondary circuit 14.
　トランス１５は、互いに直列に接続された第１トランス２１および第２トランス２２を有している。ここで、本実施形態では、第１トランス２１は「第１絶縁素子」に対応し、第２トランス２２は「第２絶縁素子」に対応している。信号伝達装置１０は、第１トランス２１と第２トランス２２とを接続する一対の接続信号線１８Ａ，１８Ｂを含む。 The transformer 15 includes a first transformer 21 and a second transformer 22 that are connected in series. Here, in this embodiment, the first transformer 21 corresponds to a "first insulating element" and the second transformer 22 corresponds to a "second insulating element". The signal transmission device 10 includes a pair of connection signal lines 18A and 18B that connect the first transformer 21 and the second transformer 22.
　本実施形態における各トランス２１，２２の絶縁耐圧は、たとえば２５００Ｖｒｍｓ以上７５００Ｖｒｍｓ以下である。なお、各トランス２１，２２の絶縁耐圧は、２５００Ｖｒｍｓ以上５７００Ｖｒｍｓ以下であってもよい。ただし、各トランス２１，２２の絶縁耐圧の具体的な数値はこれに限られず任意である。 The dielectric strength voltage of each transformer 21 and 22 in this embodiment is, for example, 2500 Vrms or more and 7500 Vrms or less. Note that the dielectric strength voltage of each transformer 21 and 22 may be 2500 Vrms or more and 5700 Vrms or less. However, the specific numerical value of the dielectric strength voltage of each transformer 21, 22 is not limited to this and is arbitrary.
　第１トランス２１は、第１コイル２３と、第１コイル２３と電気的に絶縁されておりかつ磁気結合可能な第２コイル２４と、を有している。第２トランス２２は、第３コイル２５と、第３コイル２５と電気的に絶縁されておりかつ磁気結合可能な第４コイル２６と、を有している。 The first transformer 21 has a first coil 23 and a second coil 24 that is electrically insulated from the first coil 23 and can be magnetically coupled. The second transformer 22 includes a third coil 25 and a fourth coil 26 that is electrically insulated from the third coil 25 and can be magnetically coupled.
　第１コイル２３は、１次側信号線１６Ａ，１６Ｂによって１次側回路１３と電気的に接続されている。第２コイル２４は、一対の接続信号線１８Ａ，１８Ｂによって第４コイル２６に接続されている。一例では、第２コイル２４および第４コイル２６は、電気的にフローティング状態となるように互いに接続されている。第２コイル２４の第１端部と第４コイル２６の第１端部とは接続信号線１８Ａによって接続されており、第２コイル２４の第２端部と第４コイル２６の第２端部とは接続信号線１８Ｂによって接続されている。この第２コイル２４および第４コイル２６は、第１コイル２３と第３コイル２５との間で第１信号を中継する中継コイルとなる。第３コイル２５は、２次側信号線１７Ａ，１７Ｂによって２次側回路１４と電気的に接続されている。 The first coil 23 is electrically connected to the primary circuit 13 by primary signal lines 16A and 16B. The second coil 24 is connected to the fourth coil 26 by a pair of connection signal lines 18A and 18B. In one example, the second coil 24 and the fourth coil 26 are connected to each other so as to be electrically floating. The first end of the second coil 24 and the first end of the fourth coil 26 are connected by a connection signal line 18A, and the second end of the second coil 24 and the second end of the fourth coil 26 are connected to each other by a connection signal line 18A. and is connected by a connection signal line 18B. The second coil 24 and the fourth coil 26 serve as relay coils that relay the first signal between the first coil 23 and the third coil 25. The third coil 25 is electrically connected to the secondary circuit 14 by secondary signal lines 17A and 17B.
　（信号伝達装置の内部構成）
　図２は、信号伝達装置１０の一部の内部構成を示す模式的な断面構造の一例を示している。図２に示されるように、信号伝達装置１０は、複数の半導体チップが１パッケージ化された半導体装置である。図示していないが、信号伝達装置１０のパッケージ形式はたとえばＳＯ（Small Outline）系であり、本実施形態ではＳＯＰ（Small Outline Package）である。なお、信号伝達装置１０のパッケージ形式は任意に変更可能である。 (Internal configuration of signal transmission device)
FIG. 2 shows an example of a schematic cross-sectional structure showing the internal structure of a part of the signal transmission device 10. As shown in FIG. As shown in FIG. 2, the signal transmission device 10 is a semiconductor device in which a plurality of semiconductor chips are packaged into one package. Although not shown, the package format of the signal transmission device 10 is, for example, an SO (Small Outline) system, and in this embodiment is an SOP (Small Outline Package). Note that the package format of the signal transmission device 10 can be changed arbitrarily.
　信号伝達装置１０は、複数の半導体チップとして、第１チップ４０と第２チップ５０とトランスチップ６０とを含む。また、信号伝達装置１０は、第１チップ４０が搭載された１次側ダイパッド７１と、第２チップ５０が搭載された２次側ダイパッド７２と、トランスチップ６０が実装された中間ダイパッド７３とを含む。中間ダイパッド７３は、１次側ダイパッド７１および２次側ダイパッド７２の双方と絶縁されている。また、信号伝達装置１０は、各ダイパッド７１，７２，７３および各チップ４０，５０，６０を封止する封止樹脂９０を含む。ここで、本実施形態では、トランスチップ６０は「絶縁チップ」に対応する。１次側ダイパッド７１は「第１ダイパッド」に対応し、２次側ダイパッド７２は「第２ダイパッド」に対応し、中間ダイパッド７３は「第３ダイパッド」に対応している。 The signal transmission device 10 includes a first chip 40, a second chip 50, and a transformer chip 60 as a plurality of semiconductor chips. The signal transmission device 10 also includes a primary die pad 71 on which the first chip 40 is mounted, a secondary die pad 72 on which the second chip 50 is mounted, and an intermediate die pad 73 on which the transformer chip 60 is mounted. include. The intermediate die pad 73 is insulated from both the primary die pad 71 and the secondary die pad 72. Further, the signal transmission device 10 includes a sealing resin 90 that seals each die pad 71 , 72 , 73 and each chip 40 , 50 , 60 . Here, in this embodiment, the transformer chip 60 corresponds to an "insulating chip". The primary die pad 71 corresponds to a "first die pad," the secondary die pad 72 corresponds to a "second die pad," and the intermediate die pad 73 corresponds to a "third die pad."
　封止樹脂９０は、電気絶縁性を有する材料によって形成されており、たとえば黒色のエポキシ樹脂によって形成されている。封止樹脂９０は、ｚ方向を厚さ方向とする矩形板状に形成されている。 The sealing resin 90 is made of an electrically insulating material, for example, black epoxy resin. The sealing resin 90 is formed into a rectangular plate shape with the thickness direction in the z direction.
　１次側ダイパッド７１、２次側ダイパッド７２、および中間ダイパッド７３は、導電性を有する材料によって形成されている。本実施形態では、各ダイパッド７１，７２，７３は、Ｃｕ（銅）を含む材料によって形成されている。なお、各ダイパッド７１，７２，７３は、Ａｌ（アルミニウム）等の他の金属材料によって形成されていてもよい。また、各ダイパッド７１，７２，７３を構成する材料は導電性を有する材料に限られない。たとえば、各ダイパッド７１，７２，７３はアルミナ等のセラミックスによって形成されていてもよい。つまり、各ダイパッド７１，７２，７３は電気絶縁性を有する材料によって形成されていてもよい。 The primary die pad 71, the secondary die pad 72, and the intermediate die pad 73 are made of a conductive material. In this embodiment, each die pad 71, 72, 73 is formed of a material containing Cu (copper). Note that each die pad 71, 72, 73 may be formed of other metal materials such as Al (aluminum). Moreover, the material constituting each die pad 71, 72, 73 is not limited to a conductive material. For example, each die pad 71, 72, 73 may be made of ceramic such as alumina. That is, each die pad 71, 72, 73 may be formed of a material having electrical insulation properties.
　ｚ方向から視て、１次側ダイパッド７１、中間ダイパッド７３、および２次側ダイパッド７２は、互いに離れた状態で並んで配列されている。１次側ダイパッド７１、中間ダイパッド７３、および２次側ダイパッド７２は、互いに電気的に絶縁されている。したがって、中間ダイパッド７３は、１次側ダイパッド７１および２次側ダイパッド７２に対して電気的にフローティング状態である。ｚ方向から視て、１次側ダイパッド７１、中間ダイパッド７３、および２次側ダイパッド７２の配列方向をｘ方向とする。ｚ方向から視て、ｘ方向と直交する方向をｙ方向とする。ここで、ｘ方向は「第１方向」に対応しており、ｙ方向は「第２方向」に対応している。 When viewed from the z direction, the primary die pad 71, intermediate die pad 73, and secondary die pad 72 are arranged side by side and spaced apart from each other. The primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 are electrically insulated from each other. Therefore, the intermediate die pad 73 is in an electrically floating state with respect to the primary die pad 71 and the secondary die pad 72. When viewed from the z direction, the arrangement direction of the primary die pad 71, intermediate die pad 73, and secondary die pad 72 is defined as the x direction. When viewed from the z direction, the direction orthogonal to the x direction is defined as the y direction. Here, the x direction corresponds to the "first direction" and the y direction corresponds to the "second direction".
　１次側ダイパッド７１、中間ダイパッド７３、および２次側ダイパッド７２は、平板状に形成されている。本実施形態では、ｚ方向から視た各ダイパッド７１，７２，７３の形状は、ｘ方向が短辺となり、ｙ方向が長辺となる矩形状である。本実施形態では、ｚ方向から視た２次側ダイパッド７２の面積は、ｚ方向から視た１次側ダイパッド７１の面積よりも大きい。なお、ｚ方向から視た各ダイパッド７１，７２，７３の形状は任意に変更可能である。一例では、ｚ方向から視た各ダイパッド７１，７２，７３の形状は、ｘ方向が長辺となり、ｙ方向が短辺となる矩形状であってもよい。 The primary die pad 71, the intermediate die pad 73, and the secondary die pad 72 are formed into a flat plate shape. In this embodiment, the shape of each die pad 71, 72, 73 when viewed from the z direction is a rectangular shape with the short side in the x direction and the long side in the y direction. In this embodiment, the area of the secondary die pad 72 viewed from the z direction is larger than the area of the primary die pad 71 viewed from the z direction. Note that the shape of each die pad 71, 72, 73 viewed from the z direction can be changed arbitrarily. In one example, the shape of each die pad 71, 72, 73 viewed from the z direction may be a rectangle with the long side in the x direction and the short side in the y direction.
　本実施形態では、トランスチップ６０は、中間ダイパッド７３に搭載されている。つまり、第１チップ４０、トランスチップ６０、および第２チップ５０はそれぞれ、互いに電気的に絶縁された１次側ダイパッド７１、中間ダイパッド７３、および２次側ダイパッド７２に搭載されている。そして、第１チップ４０、トランスチップ６０、および第２チップ５０は、ｘ方向において互いに離れて配列されているといえる。本実施形態では、第１チップ４０、トランスチップ６０、および第２チップ５０は、この順番で、ｘ方向において１次側ダイパッド７１から２次側ダイパッド７２に向かって配置されている。換言すると、トランスチップ６０は、ｘ方向において第１チップ４０と第２チップ５０との間に配置されている。本実施形態では、各ダイパッド７１，７２，７３は封止樹脂９０から露出していない。 In this embodiment, the transformer chip 60 is mounted on the intermediate die pad 73. That is, the first chip 40, the transformer chip 60, and the second chip 50 are mounted on the primary die pad 71, the intermediate die pad 73, and the secondary die pad 72, respectively, which are electrically insulated from each other. It can be said that the first chip 40, the transformer chip 60, and the second chip 50 are arranged apart from each other in the x direction. In this embodiment, the first chip 40, the transformer chip 60, and the second chip 50 are arranged in this order from the primary die pad 71 toward the secondary die pad 72 in the x direction. In other words, the transformer chip 60 is arranged between the first chip 40 and the second chip 50 in the x direction. In this embodiment, each die pad 71 , 72 , 73 is not exposed from the sealing resin 90 .
　信号伝達装置１０の絶縁耐圧を予め設定された絶縁耐圧とするため、各ダイパッド７１，７２，７３を互いに離す必要がある。本実施形態では、ｚ方向から視て、ｘ方向における１次側ダイパッド７１と中間ダイパッド７３との間の距離は、ｘ方向において中間ダイパッド７３と２次側ダイパッド７２との間の距離と等しい。このため、ｚ方向から視て、ｘ方向における第１チップ４０とトランスチップ６０との間の距離は、ｘ方向においてトランスチップ６０と第２チップ５０との間の距離と等しい。換言すると、トランスチップ６０は、第１チップ４０と第２チップ５０との間の中間に配置されている。 In order to set the dielectric strength voltage of the signal transmission device 10 to a preset dielectric strength voltage, it is necessary to separate the die pads 71, 72, and 73 from each other. In this embodiment, when viewed from the z direction, the distance between the primary die pad 71 and the intermediate die pad 73 in the x direction is equal to the distance between the intermediate die pad 73 and the secondary die pad 72 in the x direction. Therefore, when viewed from the z direction, the distance between the first chip 40 and the transformer chip 60 in the x direction is equal to the distance between the transformer chip 60 and the second chip 50 in the x direction. In other words, the transformer chip 60 is placed intermediate between the first chip 40 and the second chip 50.
　（第１チップ）
　第１チップ４０の形状は、ｚ方向から視て、短辺および長辺を有する矩形状である。ｚ方向から視て、第１チップ４０は、短辺がｘ方向に沿い、長辺がｙ方向に沿うように１次側ダイパッド７１に搭載されている。 (1st chip)
The first chip 40 has a rectangular shape having short sides and long sides when viewed from the z direction. When viewed from the z direction, the first chip 40 is mounted on the primary die pad 71 so that the short side runs along the x direction and the long side runs along the y direction.
　第１チップ４０は、１次側回路１３が形成された第１基板４３を含む。第１基板４３は、たとえば半導体基板である。半導体基板の一例は、Ｓｉ（シリコン）を含む材料によって形成された基板である。第１基板４３上には、配線層４４が形成されている。配線層４４は、ｚ方向に積層された複数の絶縁膜と、ｚ方向において隣り合う絶縁膜の間に設けられた金属層と、ｚ方向において絶縁膜を貫通して金属層に接続されるビアとを有している。金属層は、第１チップ４０の配線パターンを構成している。 The first chip 40 includes a first substrate 43 on which the primary circuit 13 is formed. The first substrate 43 is, for example, a semiconductor substrate. An example of the semiconductor substrate is a substrate made of a material containing Si (silicon). A wiring layer 44 is formed on the first substrate 43. The wiring layer 44 includes a plurality of insulating films laminated in the z-direction, a metal layer provided between adjacent insulating films in the z-direction, and a via that penetrates the insulating film in the z-direction and is connected to the metal layer. It has The metal layer constitutes the wiring pattern of the first chip 40.
　第１チップ４０は、ｚ方向において互いに反対側を向くチップ主面４０Ｓおよびチップ裏面４０Ｒを有している。第１基板４３はチップ裏面４０Ｒを構成し、配線層４４はチップ主面４０Ｓを構成している。チップ裏面４０Ｒは１次側ダイパッド７１と対面している。第１チップ４０のチップ主面４０Ｓの側には、複数の第１電極パッド４１および複数の第２電極パッド４２が設けられている。より詳細には、各電極パッド４１，４２は、チップ主面４０Ｓから露出するように設けられている。各電極パッド４１，４２は、配線層４４によって１次側回路１３と電気的に接続されている。 The first chip 40 has a chip main surface 40S and a chip back surface 40R facing oppositely to each other in the z direction. The first substrate 43 constitutes the back surface 40R of the chip, and the wiring layer 44 constitutes the main surface 40S of the chip. The chip back surface 40R faces the primary die pad 71. A plurality of first electrode pads 41 and a plurality of second electrode pads 42 are provided on the chip main surface 40S side of the first chip 40. More specifically, each electrode pad 41, 42 is provided so as to be exposed from the chip main surface 40S. Each electrode pad 41 , 42 is electrically connected to the primary circuit 13 through a wiring layer 44 .
　複数の第１電極パッド４１は、チップ主面４０Ｓのうちチップ主面４０Ｓのｘ方向の中央に対してトランスチップ６０とは反対側に配置されている。図示していないが、複数の第１電極パッド４１は、ｙ方向において互いに離れて配列されている。複数の第２電極パッド４２は、チップ主面４０Ｓのうちチップ主面４０Ｓのｘ方向の中央に対してトランスチップ６０寄りに配置されている。図示していないが、複数の第２電極パッド４２は、ｙ方向において互いに離れて配列されている。 The plurality of first electrode pads 41 are arranged on the opposite side of the transformer chip 60 with respect to the center of the chip main surface 40S in the x direction of the chip main surface 40S. Although not shown, the plurality of first electrode pads 41 are arranged apart from each other in the y direction. The plurality of second electrode pads 42 are arranged closer to the transformer chip 60 with respect to the center of the chip main surface 40S in the x direction of the chip main surface 40S. Although not shown, the plurality of second electrode pads 42 are arranged apart from each other in the y direction.
　第１チップ４０は、第１接合材８１によって１次側ダイパッド７１に接合されている。より詳細には、チップ裏面４０Ｒと１次側ダイパッド７１との間には第１接合材８１が介在している。第１接合材８１は、チップ裏面４０Ｒと１次側ダイパッド７１とを接合している。第１接合材８１は、はんだ、Ａｇ（銀）ペースト等の導電性接合材である。第１接合材８１は、第１チップ４０の第１基板４３と１次側ダイパッド７１とを接合している。これにより、第１基板４３と１次側ダイパッド７１とが電気的に接続されている。このため、１次側回路１３は、第１接合材８１を介して１次側ダイパッド７１に電気的に接続されている。１次側ダイパッド７１は１次側回路１３のグランドを構成している。 The first chip 40 is bonded to the primary die pad 71 by a first bonding material 81. More specifically, a first bonding material 81 is interposed between the chip back surface 40R and the primary die pad 71. The first bonding material 81 bonds the chip back surface 40R and the primary die pad 71. The first bonding material 81 is a conductive bonding material such as solder or Ag (silver) paste. The first bonding material 81 bonds the first substrate 43 of the first chip 40 and the primary die pad 71. Thereby, the first substrate 43 and the primary die pad 71 are electrically connected. Therefore, the primary circuit 13 is electrically connected to the primary die pad 71 via the first bonding material 81. The primary die pad 71 constitutes a ground for the primary circuit 13.
　（第２チップ）
　第２チップ５０の形状は、ｚ方向から視て、短辺および長辺を有する矩形状である。ｚ方向から視て、第２チップ５０は、短辺がｘ方向に沿い、長辺がｙ方向に沿うように２次側ダイパッド７２に搭載されている。 (2nd chip)
The shape of the second chip 50 is a rectangle having short sides and long sides when viewed from the z direction. When viewed from the z direction, the second chip 50 is mounted on the secondary die pad 72 so that the short side runs along the x direction and the long side runs along the y direction.
　第２チップ５０は、２次側回路１４が形成された第２基板５３を含む。第２基板５３は、たとえば半導体基板である。半導体基板の一例は、Ｓｉ基板である。第２基板５３上には、配線層５４が形成されている。配線層５４は、ｚ方向に積層された複数の絶縁膜と、ｚ方向において隣り合う絶縁膜の間に設けられた金属層と、ｚ方向に絶縁膜を貫通して金属層に接続されるビアと、を有している。金属層は、第２チップ５０の配線パターンを構成している。 The second chip 50 includes a second substrate 53 on which the secondary circuit 14 is formed. The second substrate 53 is, for example, a semiconductor substrate. An example of a semiconductor substrate is a Si substrate. A wiring layer 54 is formed on the second substrate 53. The wiring layer 54 includes a plurality of insulating films laminated in the z-direction, a metal layer provided between adjacent insulating films in the z-direction, and vias that penetrate the insulating films in the z-direction and are connected to the metal layer. It has . The metal layer constitutes the wiring pattern of the second chip 50.
　第２チップ５０は、ｚ方向において互いに反対側を向くチップ主面５０Ｓおよびチップ裏面５０Ｒを有している。第２基板５３はチップ裏面５０Ｒを構成し、配線層５４はチップ主面５０Ｓを構成している。チップ裏面５０Ｒは２次側ダイパッド７２と対面している。チップ裏面５０Ｒは第１チップ４０のチップ裏面４０Ｒと同じ側を向き、チップ主面５０Ｓは第１チップ４０のチップ主面４０Ｓと同じ側を向いている。第２チップ５０のチップ主面５０Ｓの側には、複数の第１電極パッド５１および複数の第２電極パッド５２が設けられている。より詳細には、各電極パッド５１，５２は、チップ主面５０Ｓから露出するように設けられている。各電極パッド５１，５２は、たとえば配線層５４によって２次側回路１４と電気的に接続されている。 The second chip 50 has a chip main surface 50S and a chip back surface 50R facing oppositely to each other in the z direction. The second substrate 53 constitutes the back surface 50R of the chip, and the wiring layer 54 constitutes the main surface 50S of the chip. The chip back surface 50R faces the secondary die pad 72. The chip back surface 50R faces the same side as the chip back surface 40R of the first chip 40, and the chip main surface 50S faces the same side as the chip main surface 40S of the first chip 40. A plurality of first electrode pads 51 and a plurality of second electrode pads 52 are provided on the chip main surface 50S side of the second chip 50. More specifically, each electrode pad 51, 52 is provided so as to be exposed from the chip main surface 50S. Each electrode pad 51, 52 is electrically connected to the secondary circuit 14 by, for example, a wiring layer 54.
　複数の第１電極パッド５１は、チップ主面５０Ｓのうちチップ主面５０Ｓのｘ方向の中央に対してトランスチップ６０寄りに配置されている。図示していないが、複数の第１電極パッド５１は、ｙ方向において互いに離れて配列されている。複数の第２電極パッド５２は、チップ主面５０Ｓのうちチップ主面５０Ｓのｘ方向の中央に対してトランスチップ６０とは反対側に配置されている。図示していないが、複数の第２電極パッド５２は、ｙ方向において互いに離れて配列されている。 The plurality of first electrode pads 51 are arranged closer to the transformer chip 60 with respect to the center of the chip main surface 50S in the x direction of the chip main surface 50S. Although not shown, the plurality of first electrode pads 51 are arranged apart from each other in the y direction. The plurality of second electrode pads 52 are arranged on the opposite side of the transformer chip 60 with respect to the center of the chip main surface 50S in the x direction of the chip main surface 50S. Although not shown, the plurality of second electrode pads 52 are arranged apart from each other in the y direction.
　第２チップ５０は、第２接合材８２によって２次側ダイパッド７２に接合されている。より詳細には、チップ裏面５０Ｒと２次側ダイパッド７２との間には第２接合材８２が介在している。第２接合材８２は、チップ裏面５０Ｒと２次側ダイパッド７２とを接合している。第２接合材８２は、はんだ、Ａｇペースト等の導電性接合材である。本実施形態では、第２接合材８２は、たとえば第１接合材８１と同じ材料の接合材が用いられている。第２接合材８２は、第２チップ５０の第２基板５３と２次側ダイパッド７２とを接合している。これにより、第２基板５３と２次側ダイパッド７２とが電気的に接続されている。このため、２次側回路１４は、第２接合材８２を介して２次側ダイパッド７２に電気的に接続されている。２次側ダイパッド７２は２次側回路１４のグランドを構成している。 The second chip 50 is bonded to the secondary die pad 72 by a second bonding material 82. More specifically, the second bonding material 82 is interposed between the chip back surface 50R and the secondary die pad 72. The second bonding material 82 bonds the chip back surface 50R and the secondary die pad 72. The second bonding material 82 is a conductive bonding material such as solder or Ag paste. In this embodiment, the second bonding material 82 is made of the same material as the first bonding material 81, for example. The second bonding material 82 bonds the second substrate 53 of the second chip 50 and the secondary die pad 72 . Thereby, the second substrate 53 and the secondary die pad 72 are electrically connected. Therefore, the secondary circuit 14 is electrically connected to the secondary die pad 72 via the second bonding material 82. The secondary die pad 72 constitutes a ground for the secondary circuit 14.
　（トランスチップ）
　トランスチップ６０の形状はｚ方向から視て、短辺および長辺を有する矩形状である。本実施形態では、ｚ方向から視て、トランスチップ６０は、長辺がｙ方向に沿い、短辺がｘ方向に沿うように２次側ダイパッド７２に搭載されている。 (trans chip)
The transformer chip 60 has a rectangular shape having short sides and long sides when viewed from the z direction. In this embodiment, when viewed from the z direction, the transformer chip 60 is mounted on the secondary die pad 72 so that the long side runs along the y direction and the short side runs along the x direction.
　トランスチップ６０は、第３基板６３を含む。第３基板６３は、たとえば半導体基板である。半導体基板の一例は、Ｓｉ基板である。トランスチップ６０は、第３基板６３上の絶縁体６４を含む。トランスチップ６０は、トランス１５（第１トランス２１，第２トランス２２）を含む。また、トランスチップ６０は、第１キャパシタ３１および第２キャパシタ３２を含む。トランス１５、第１キャパシタ３１、および第２キャパシタ３２は、絶縁体６４に埋め込まれている。 The transformer chip 60 includes a third substrate 63. The third substrate 63 is, for example, a semiconductor substrate. An example of a semiconductor substrate is a Si substrate. The transformer chip 60 includes an insulator 64 on a third substrate 63. The transformer chip 60 includes the transformer 15 (first transformer 21, second transformer 22). Further, the transformer chip 60 includes a first capacitor 31 and a second capacitor 32. The transformer 15, the first capacitor 31, and the second capacitor 32 are embedded in the insulator 64.
　トランスチップ６０は、ｚ方向において互いに反対側を向くチップ主面６０Ｓおよびチップ裏面６０Ｒを有している。チップ裏面６０Ｒは２次側ダイパッド７２と対面している。つまり、チップ裏面６０Ｒは第２チップ５０のチップ裏面５０Ｒと同じ側を向き、チップ主面６０Ｓは第２チップ５０のチップ主面５０Ｓと同じ側を向いている。 The transformer chip 60 has a chip main surface 60S and a chip back surface 60R facing oppositely to each other in the z direction. The chip back surface 60R faces the secondary die pad 72. That is, the chip back surface 60R faces the same side as the chip back surface 50R of the second chip 50, and the chip main surface 60S faces the same side as the chip main surface 50S of the second chip 50.
　トランスチップ６０は、複数の第１電極パッド６１および複数の第２電極パッド６２を含む。各第１電極パッド６１および各第２電極パッド６２は、チップ主面６０Ｓの側に設けられている。より詳細には、ｚ方向から視て、各電極パッド６１，６２は、チップ主面６０Ｓから露出するように設けられている。 The transformer chip 60 includes a plurality of first electrode pads 61 and a plurality of second electrode pads 62. Each first electrode pad 61 and each second electrode pad 62 are provided on the chip main surface 60S side. More specifically, when viewed from the z direction, each electrode pad 61, 62 is provided so as to be exposed from the chip main surface 60S.
　複数の第１電極パッド６１は、チップ主面６０Ｓのうちチップ主面６０Ｓのｘ方向の中央に対して第１チップ４０寄りに配置されている。複数の第２電極パッド６２は、チップ主面６０Ｓのうちチップ主面６０Ｓのｘ方向の中央に対して第２チップ５０寄りに配置されている。 The plurality of first electrode pads 61 are arranged closer to the first chip 40 with respect to the center of the chip main surface 60S in the x direction of the chip main surface 60S. The plurality of second electrode pads 62 are arranged closer to the second chip 50 with respect to the center of the chip main surface 60S in the x direction of the chip main surface 60S.
　トランス１５の第１トランス２１と第２トランス２２は、第１電極パッド６１と第２電極パッド６２との間に、直列に接続されている。第１キャパシタ３１と第２キャパシタ３２は、第１電極パッド６１と第２電極パッド６２との間に、直列に接続されている。また、第１キャパシタ３１および第２キャパシタ３２は、第３基板６３と電気的に接続されている。第１電極パッド６１は、「第１接続電極」に相当する。第２電極パッド６２は、「第２接続電極」に相当する。 The first transformer 21 and the second transformer 22 of the transformer 15 are connected in series between the first electrode pad 61 and the second electrode pad 62. The first capacitor 31 and the second capacitor 32 are connected in series between the first electrode pad 61 and the second electrode pad 62. Further, the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63. The first electrode pad 61 corresponds to a "first connection electrode." The second electrode pad 62 corresponds to a "second connection electrode."
　トランスチップ６０は、第３接合材８３によって中間ダイパッド７３に接合されている。より詳細には、チップ裏面６０Ｒと中間ダイパッド７３との間には第３接合材８３が介在している。第３接合材８３は、チップ裏面６０Ｒと中間ダイパッド７３とを接合している。第３接合材８３は、はんだ、Ａｇ（銀）ペースト等の導電性接合材である。第３接合材８３は、トランスチップ６０の第３基板６３と中間ダイパッド７３とを接合している。これにより、第３基板６３と中間ダイパッド７３とが電気的に接続されている。 The transformer chip 60 is bonded to the intermediate die pad 73 by a third bonding material 83. More specifically, a third bonding material 83 is interposed between the chip back surface 60R and the intermediate die pad 73. The third bonding material 83 bonds the chip back surface 60R and the intermediate die pad 73. The third bonding material 83 is a conductive bonding material such as solder or Ag (silver) paste. The third bonding material 83 bonds the third substrate 63 of the transformer chip 60 and the intermediate die pad 73. Thereby, the third substrate 63 and the intermediate die pad 73 are electrically connected.
　（ワイヤ）
　第１チップ４０、トランスチップ６０、および第２チップ５０のそれぞれには、複数のワイヤＷ１～Ｗ４が接続されている。各ワイヤＷ１～Ｗ４は、ワイヤボンディング装置によって形成されるボンディングワイヤであり、たとえばＡｕ（金），Ａｌ，Ｃｕ等の導体によって形成されている。 (wire)
A plurality of wires W1 to W4 are connected to each of the first chip 40, transformer chip 60, and second chip 50. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor such as Au (gold), Al, or Cu.
　第１チップ４０の複数の第１電極パッド４１は、図示していない複数の１次側リードに複数のワイヤＷ１によって個別に接続されている。１次側リードは、図１の１次側端子１１を構成する部品である。これにより、１次側回路１３と１次側端子１１とが電気的に接続されている。 The plurality of first electrode pads 41 of the first chip 40 are individually connected to a plurality of primary leads (not shown) by a plurality of wires W1. The primary lead is a component that constitutes the primary terminal 11 in FIG. Thereby, the primary side circuit 13 and the primary side terminal 11 are electrically connected.
　１次側リードは、たとえば１次側ダイパッド７１と同じ材料によって形成されている。１次側リードおよび１次側ダイパッド７１は、一体に形成されていてもよい。１次側リードは、１次側ダイパッド７１に対して２次側ダイパッド７２とは反対側に間隔をあけて配置されており、封止樹脂９０を跨いで形成されている。つまり、１次側リードは、封止樹脂９０から外部に向けて突出した部分を有している。１次側リードのうち封止樹脂９０から外部に向けて突出した部分は、信号伝達装置１０の外部端子を構成している。 The primary lead is made of the same material as the primary die pad 71, for example. The primary lead and the primary die pad 71 may be integrally formed. The primary-side leads are arranged at a distance from the primary-side die pad 71 on the side opposite to the secondary-side die pad 72, and are formed across the sealing resin 90. That is, the primary lead has a portion that protrudes outward from the sealing resin 90. A portion of the primary lead that protrudes outward from the sealing resin 90 constitutes an external terminal of the signal transmission device 10.
　第１チップ４０の複数の第２電極パッド４２は、複数のワイヤＷ２によってトランスチップ６０の複数の第１電極パッド６１と個別に接続されている。これにより、１次側回路１３と第１トランス２１とが電気的に接続されている。つまり、第１チップ４０の配線層４４、複数の第２電極パッド４２、複数のワイヤＷ２、および複数の第１電極パッド６１はそれぞれ、１次側信号線１６Ａ，１６Ｂ（図１参照）の一部を構成している。 The plurality of second electrode pads 42 of the first chip 40 are individually connected to the plurality of first electrode pads 61 of the transformer chip 60 by a plurality of wires W2. Thereby, the primary circuit 13 and the first transformer 21 are electrically connected. That is, the wiring layer 44 of the first chip 40, the plurality of second electrode pads 42, the plurality of wires W2, and the plurality of first electrode pads 61 are each connected to one of the primary signal lines 16A, 16B (see FIG. 1). It makes up the department.
　トランスチップ６０の複数の第２電極パッド６２は、複数のワイヤＷ３によって第２チップ５０の複数の第１電極パッド５１と個別に接続されている。これにより、第２トランス２２と２次側回路１４とが電気的に接続されている。つまり、複数の第２電極パッド６２、複数のワイヤＷ３、および第２チップ５０の複数の第１電極パッド５１はそれぞれ、２次側信号線１７Ａ，１７Ｂ（図１参照）の一部を構成している。 The plurality of second electrode pads 62 of the transformer chip 60 are individually connected to the plurality of first electrode pads 51 of the second chip 50 by a plurality of wires W3. Thereby, the second transformer 22 and the secondary circuit 14 are electrically connected. That is, the plurality of second electrode pads 62, the plurality of wires W3, and the plurality of first electrode pads 51 of the second chip 50 each constitute a part of the secondary signal lines 17A, 17B (see FIG. 1). ing.
　第２チップ５０の複数の第２電極パッド５２は、図示していない複数の２次側リードに複数のワイヤＷ４によって個別に接続されている。２次側リードは、図１の２次側端子１２を構成する部品である。これにより、２次側回路１４と２次側端子１２とが電気的に接続されている。 The plurality of second electrode pads 52 of the second chip 50 are individually connected to a plurality of secondary leads (not shown) by a plurality of wires W4. The secondary lead is a component that constitutes the secondary terminal 12 in FIG. Thereby, the secondary side circuit 14 and the secondary side terminal 12 are electrically connected.
　２次側リードは、たとえば２次側ダイパッド７２と同じ材料によって形成されている。２次側リードおよび２次側ダイパッド７２は、一体に形成されていてもよい。２次側リードは、２次側ダイパッド７２に対して１次側ダイパッド７１とは反対側に間隔をあけて配置されており、封止樹脂９０を跨いで形成されている。つまり、２次側リードは、封止樹脂９０から外部に向けて突出した部分を有している。２次側リードのうち封止樹脂９０から外部に向けて突出した部分は、信号伝達装置１０の外部端子を構成している。 The secondary leads are made of the same material as the secondary die pad 72, for example. The secondary lead and the secondary die pad 72 may be integrally formed. The secondary leads are arranged at a distance from the secondary die pad 72 on the opposite side of the primary die pad 71 and are formed across the sealing resin 90 . That is, the secondary lead has a portion that protrudes outward from the sealing resin 90. A portion of the secondary lead that protrudes outward from the sealing resin 90 constitutes an external terminal of the signal transmission device 10.
　（トランスチップの構成）
　図３～図５を参照して、トランスチップ６０の構成の一例を説明する。
　図３は、トランスチップ６０の平面構造を模式的に示した平面図である。図４は、トランスチップ６０の内部をｘｙ平面で切った断面構造を模式的に示した断面図である。図４では、図面の見やすさの観点からハッチング線を省略して示している。図５は、トランスチップ６０の断面構造を模式的に示した断面図である。また、図５に示されるコイル２３，２４，２５，２６は、模式的に示されているため、図３および図４に示されるコイル２３，２４，２５，２６の構成とは整合していない。 (Configuration of transformer chip)
An example of the configuration of the transformer chip 60 will be described with reference to FIGS. 3 to 5.
FIG. 3 is a plan view schematically showing the planar structure of the transformer chip 60. FIG. 4 is a cross-sectional view schematically showing the cross-sectional structure of the inside of the transformer chip 60 taken along the xy plane. In FIG. 4, hatching lines are omitted from the viewpoint of ease of viewing the drawing. FIG. 5 is a cross-sectional view schematically showing the cross-sectional structure of the transformer chip 60. As shown in FIG. Further, since the coils 23, 24, 25, 26 shown in FIG. 5 are shown schematically, they are not consistent with the configurations of the coils 23, 24, 25, 26 shown in FIGS. 3 and 4. .
　図３～図５に示されるように、トランスチップ６０は、トランス１５が１チップ化されたものである。つまり、トランスチップ６０は、第１チップ４０と第２チップ５０とは別に設けられたトランス１５専用のチップである。 As shown in FIGS. 3 to 5, the transformer chip 60 is the transformer 15 integrated into one chip. That is, the transformer chip 60 is a chip dedicated to the transformer 15 that is provided separately from the first chip 40 and the second chip 50.
　トランスチップ６０は、チップ主面６０Ｓ、チップ裏面６０Ｒ、複数のチップ側面６０１，６０２，６０３，６０４を含む。チップ側面６０１～６０４は、チップ主面６０Ｓおよびチップ裏面６０Ｒの双方と直交する。チップ側面６０１，６０２は、トランスチップ６０のｘ方向の端面を構成する。チップ側面６０３，６０４は、トランスチップ６０のｙ方向の端面を構成する。本実施形態において、トランスチップ６０のチップ側面６０１は図２に示される第１チップ４０と対向し、トランスチップ６０のチップ側面６０２は図２に示される第２チップ５０と対向する。以降の説明では、トランスチップ６０のチップ裏面６０Ｒからチップ主面６０Ｓに向かう方向を上方とし、チップ主面６０Ｓからチップ裏面６０Ｒに向かう方向を下方とする。 The transformer chip 60 includes a chip main surface 60S, a chip back surface 60R, and a plurality of chip side surfaces 601, 602, 603, and 604. The chip side surfaces 601 to 604 are perpendicular to both the chip main surface 60S and the chip back surface 60R. Chip side surfaces 601 and 602 constitute end surfaces of the transformer chip 60 in the x direction. Chip side surfaces 603 and 604 constitute end surfaces of the transformer chip 60 in the y direction. In this embodiment, a chip side surface 601 of the transformer chip 60 faces the first chip 40 shown in FIG. 2, and a chip side surface 602 of the transformer chip 60 faces the second chip 50 shown in FIG. In the following description, the direction from the chip back surface 60R of the transformer chip 60 to the chip main surface 60S will be referred to as the upper side, and the direction from the chip main surface 60S to the chip rear surface 60R will be referred to as the lower side.
　（基板、絶縁体）
　図５～図８に示すように、トランスチップ６０は、第３基板６３と、第３基板６３の上に配置された絶縁体６４と、を含む。 (substrate, insulator)
As shown in FIGS. 5 to 8, the transformer chip 60 includes a third substrate 63 and an insulator 64 disposed on the third substrate 63.
　第３基板６３は、ｚ方向において互いに反対側を向く基板表面６３Ｓおよび基板裏面６３Ｒを有している。第３基板６３は、たとえば半導体基板によって形成されている。本実施形態では、第３基板６３は、Ｓｉを含む材料によって形成された半導体基板である。なお、第３基板６３は、半導体基板として、ワイドバンドギャップ半導体または化合物半導体が用いられていてもよい。また、第３基板６３は、半導体基板に代えて、ガラスを含む材料によって形成された絶縁基板、またはアルミナ等のセラミックスを含む材料によって形成された絶縁基板が用いられていてもよい。 The third substrate 63 has a substrate front surface 63S and a substrate back surface 63R facing oppositely to each other in the z direction. The third substrate 63 is formed of, for example, a semiconductor substrate. In this embodiment, the third substrate 63 is a semiconductor substrate made of a material containing Si. Note that the third substrate 63 may be made of a wide bandgap semiconductor or a compound semiconductor as a semiconductor substrate. Furthermore, instead of the semiconductor substrate, the third substrate 63 may be an insulating substrate formed of a material containing glass or an insulating substrate formed of a material containing ceramics such as alumina.
　ワイドバンドギャップ半導体は、２．０ｅＶ以上のバンドギャップを有する半導体基板である。ワイドバンドギャップ半導体は、ＳｉＣ（炭化シリコン）であってもよい。化合物半導体は、ＩＩＩ－Ｖ族化合物半導体であってもよい。化合物半導体は、ＡｌＮ（窒化アルミニウム）、ＩｎＮ（窒化インジウム）、ＧａＮ（窒化ガリウム）、およびＧａＡｓ（ヒ化ガリウム）のうち少なくとも１つを含んでいてもよい。 A wide band gap semiconductor is a semiconductor substrate having a band gap of 2.0 eV or more. The wide bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).
　絶縁体６４は、第１絶縁層６４１と、第１絶縁層６４１の上に設けられた第２絶縁層６４２と、第１絶縁層６４１の下に設けられた第３絶縁層６４３と、を含む。第１絶縁層６４１は、第３基板６３と平行に配置されている。第１絶縁層６４１と第２絶縁層６４２は互いに接している。第１絶縁層６４１と第３絶縁層６４３は互いに接している。第３絶縁層６４３は、第３基板６３の基板表面６３Ｓと接する。つまり、絶縁体６４は、第３基板６３の基板表面６３Ｓから、上方にむけて積層された第３絶縁層６４３、第１絶縁層６４１、および第２絶縁層６４２を含む。第２絶縁層６４２の上面は、上記したトランスチップ６０のチップ主面６０Ｓを構成する。 The insulator 64 includes a first insulating layer 641, a second insulating layer 642 provided on the first insulating layer 641, and a third insulating layer 643 provided below the first insulating layer 641. . The first insulating layer 641 is arranged parallel to the third substrate 63. The first insulating layer 641 and the second insulating layer 642 are in contact with each other. The first insulating layer 641 and the third insulating layer 643 are in contact with each other. The third insulating layer 643 is in contact with the substrate surface 63S of the third substrate 63. That is, the insulator 64 includes a third insulating layer 643, a first insulating layer 641, and a second insulating layer 642 stacked upward from the substrate surface 63S of the third substrate 63. The upper surface of the second insulating layer 642 constitutes the main chip surface 60S of the transformer chip 60 described above.
　第１絶縁層６４１は、たとえばＳｉを含む材料により形成されている。Ｓｉを含む材料としては、ＳｉＯ２（酸化シリコン）、ＳｉＮ（窒化シリコン）、ＳｉＣ、ＳｉＣＮ（窒素添加炭化シリコン）等を用いることができる。本実施形態の第１絶縁層６４１は、複数の絶縁膜６４１Ａにより構成されている。複数の絶縁膜６４１Ａはそれぞれ、ＳｉＮ、ＳｉＣ、ＳｉＣＮ等を含む材料により形成された薄膜と、ＳｉＯ２を含む材料により形成された層間絶縁膜とにより構成され得る。複数の絶縁膜６４１Ａは、それぞれが区別されることなく、１つの絶縁膜として形成されていてもよい。 The first insulating layer 641 is made of a material containing Si, for example. As the material containing Si, SiO 2 (silicon oxide), SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), etc. can be used. The first insulating layer 641 of this embodiment is composed of a plurality of insulating films 641A. Each of the plurality of insulating films 641A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 . The plurality of insulating films 641A may be formed as one insulating film without being distinguished from each other.
　第２絶縁層６４２は、たとえばＳｉを含む材料により形成されている。Ｓｉを含む材料としては、ＳｉＯ２、ＳｉＮ、ＳｉＣ、ＳｉＣＮ等を用いることができる。本実施形態の第２絶縁層６４２は、複数の絶縁膜６４２Ａにより構成されている。複数の絶縁膜６４２Ａはそれぞれ、ＳｉＮ、ＳｉＣ、ＳｉＣＮ等を含む材料により形成された薄膜と、ＳｉＯ２を含む材料により形成された層間絶縁膜とにより構成され得る。複数の絶縁膜６４２Ａは、それぞれが区別されることなく、１つの絶縁膜として形成されていてもよい。第２絶縁層６４２は、樹脂層を含んでいてもよい。樹脂層は、たとえば、ポリイミド（ＰＩ）を含む材料から形成され得る。 The second insulating layer 642 is made of, for example, a material containing Si. As the material containing Si, SiO 2 , SiN, SiC, SiCN, etc. can be used. The second insulating layer 642 of this embodiment is composed of a plurality of insulating films 642A. Each of the plurality of insulating films 642A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 . The plurality of insulating films 642A may be formed as one insulating film without being distinguished from each other. The second insulating layer 642 may include a resin layer. The resin layer may be formed from a material containing polyimide (PI), for example.
　第３絶縁層６４３は、たとえばＳｉを含む材料により形成されている。Ｓｉを含む材料としては、ＳｉＯ２、ＳｉＮ、ＳｉＣ、ＳｉＣＮ等を用いることができる。本実施形態の第３絶縁層６４３は、複数の絶縁膜６４３Ａにより構成されている。複数の絶縁膜６４３Ａはそれぞれ、ＳｉＮ、ＳｉＣ、ＳｉＣＮ等を含む材料により形成された薄膜と、ＳｉＯ２を含む材料により形成された層間絶縁膜とにより構成され得る。複数の絶縁膜６４３Ａは、それぞれが区別されることなく、１つの絶縁膜として形成されていてもよい。 The third insulating layer 643 is made of a material containing Si, for example. As the material containing Si, SiO 2 , SiN, SiC, SiCN, etc. can be used. The third insulating layer 643 of this embodiment is composed of a plurality of insulating films 643A. Each of the plurality of insulating films 643A may be composed of a thin film formed of a material containing SiN, SiC, SiCN, etc., and an interlayer insulating film formed of a material containing SiO 2 . The plurality of insulating films 643A may be formed as one insulating film without being distinguished from each other.
　（トランス、第１キャパシタ、第２キャパシタ）
　図３～図５に示されるように、トランスチップ６０は、トランス１５、第１キャパシタ３１、および第２キャパシタ３２を含む。トランス１５は、第１トランス２１および第２トランス２２を含む。 (Transformer, first capacitor, second capacitor)
As shown in FIGS. 3 to 5, the transformer chip 60 includes a transformer 15, a first capacitor 31, and a second capacitor 32. The transformer 15 includes a first transformer 21 and a second transformer 22.
　図３、図４に示されるように、第１トランス２１と第２トランス２２は、絶縁体６４において、ｘ方向に並んで配置されている。第１トランス２１および第２トランス２２の双方は、チップ側面６０４に沿って配列されている。つまり、第１トランス２１および第２トランス２２は、ｙ方向において互いに揃った状態でｘ方向において互いに離間して配列されている。そして、第１トランス２１および第２トランス２２は、図２に示されるダイパッド７１，７３，７２の配列方向に離間して配列されているともいえる。 As shown in FIGS. 3 and 4, the first transformer 21 and the second transformer 22 are arranged side by side in the x direction in the insulator 64. Both the first transformer 21 and the second transformer 22 are arranged along the chip side surface 604. That is, the first transformer 21 and the second transformer 22 are aligned in the y direction and spaced apart from each other in the x direction. It can also be said that the first transformer 21 and the second transformer 22 are arranged apart from each other in the arrangement direction of the die pads 71, 73, 72 shown in FIG.
　第１キャパシタ３１と第２キャパシタ３２は、絶縁体６４において、ｘ方向に並んで配置されている。第１キャパシタ３１および第２キャパシタ３２の双方は、チップ側面６０３に沿って配列されている。つまり、第１キャパシタ３１および第２キャパシタ３２は、ｙ方向において互いに揃った状態でｘ方向において互いに離間して配列されている。そして、第１キャパシタ３１および第２キャパシタ３２は、図２に示されるダイパッド７１，７３，７２の配列方向に離間して配列されているともいえる。 The first capacitor 31 and the second capacitor 32 are arranged side by side in the x direction in the insulator 64. Both the first capacitor 31 and the second capacitor 32 are arranged along the chip side surface 603. That is, the first capacitor 31 and the second capacitor 32 are aligned in the y direction and spaced apart from each other in the x direction. It can also be said that the first capacitor 31 and the second capacitor 32 are arranged apart from each other in the arrangement direction of the die pads 71, 73, 72 shown in FIG.
　図３～図５に示されるように、第１トランス２１は、第１コイル２３と第２コイル２４とを含む。第２トランス２２は、第３コイル２５と第４コイル２６とを含む。
　図３に示されるように、第１コイル２３は、渦巻き状のコイル部２３Ａと、コイル部２３Ａの内周端から内方に向けて延びる第１端部２３Ｂと、コイル部２３Ａの外周端から外方に向けて延びる第２端部２３Ｃとを含む。第１コイル２３の第１端部２３Ｂおよび第２端部２３Ｃは、図１に示される１次側回路１３に電気的に接続される端部である。第１コイル２３は、第１電極パッド６１に電気的に接続されている。第１電極パッド６１は、第１コイル２３の第１端部２３Ｂに電気的に接続された電極パッド６１Ａと、第１コイル２３の第２端部２３Ｃに電気的に接続された電極パッド６１Ｂとを含む。 As shown in FIGS. 3 to 5, the first transformer 21 includes a first coil 23 and a second coil 24. The second transformer 22 includes a third coil 25 and a fourth coil 26.
As shown in FIG. 3, the first coil 23 includes a spiral coil portion 23A, a first end portion 23B extending inward from the inner peripheral end of the coil portion 23A, and a first end portion 23B extending inward from the outer peripheral end of the coil portion 23A. and a second end 23C extending outward. The first end 23B and the second end 23C of the first coil 23 are ends that are electrically connected to the primary circuit 13 shown in FIG. The first coil 23 is electrically connected to the first electrode pad 61. The first electrode pad 61 includes an electrode pad 61A electrically connected to the first end 23B of the first coil 23, and an electrode pad 61B electrically connected to the second end 23C of the first coil 23. including.
　図３に示されるように、第３コイル２５は、渦巻き状のコイル部２５Ａと、コイル部２５Ａの内周端から内方に向けて延びる第１端部２５Ｂと、コイル部２５Ａの外周端から外方に向けて延びる第２端部２５Ｃとを含む。第３コイル２５の第１端部２５Ｂおよび第２端部２５Ｃは、図１に示される２次側回路１４に電気的に接続される端部である。第３コイル２５は、第２電極パッド６２に電気的に接続されている。第２電極パッド６２は、第３コイル２５の第１端部２５Ｂに電気的に接続された電極パッド６２Ａと、第３コイル２５の第２端部２５Ｃに電気的に接続された電極パッド６２Ｂとを含む。 As shown in FIG. 3, the third coil 25 includes a spiral coil portion 25A, a first end portion 25B extending inward from the inner peripheral end of the coil portion 25A, and a first end portion 25B extending inward from the outer peripheral end of the coil portion 25A. and a second end 25C extending outward. The first end 25B and the second end 25C of the third coil 25 are ends that are electrically connected to the secondary circuit 14 shown in FIG. The third coil 25 is electrically connected to the second electrode pad 62. The second electrode pad 62 includes an electrode pad 62A electrically connected to the first end 25B of the third coil 25, and an electrode pad 62B electrically connected to the second end 25C of the third coil 25. including.
　図４に示されるように、第２コイル２４および第４コイル２６はそれぞれ、渦巻状のコイル部２４Ａ，２６Ａを有している。第２コイル２４のコイル部２４Ａと第４コイル２６のコイル部２６Ａは、配線６５Ｃ，６５Ｄにより互いに電気的に接続されている。 As shown in FIG. 4, the second coil 24 and the fourth coil 26 each have spiral coil portions 24A and 26A. The coil portion 24A of the second coil 24 and the coil portion 26A of the fourth coil 26 are electrically connected to each other by wirings 65C and 65D.
　図５に示されるように、第１コイル２３と第２コイル２４は、第１絶縁層６４１を挟んで配置されている。第１コイル２３および第２コイル２４は、第１絶縁層６４１の厚さ方向（ｚ方向）に磁気結合可能に配置されている。第１コイル２３は、第１絶縁層６４１の上の第２絶縁層６４２内に配置されている。第２コイル２４は、第１絶縁層６４１の下の第３絶縁層６４３内に配置されている。本実施形態において、第１コイル２３および第２コイル２４は、第１絶縁層６４１と接している。 As shown in FIG. 5, the first coil 23 and the second coil 24 are arranged with the first insulating layer 641 in between. The first coil 23 and the second coil 24 are arranged so as to be magnetically coupled in the thickness direction (z direction) of the first insulating layer 641. The first coil 23 is disposed within the second insulating layer 642 above the first insulating layer 641 . The second coil 24 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, the first coil 23 and the second coil 24 are in contact with the first insulating layer 641.
　第１コイル２３は、配線６５Ａにより第１電極パッド６１Ｂに電気的に接続されている。同様に、第３コイル２５は、配線６５Ｂにより第２電極パッド６２Ｂに電気的に接続されている。なお、第１コイル２３は、図示しない配線により図３に示される第１電極パッド６１Ａに電気的に接続されている。同様に、第４コイル２６は、図示しない配線により図３に示される第２電極パッド６２Ａに電気的に接続されている。 The first coil 23 is electrically connected to the first electrode pad 61B by a wiring 65A. Similarly, the third coil 25 is electrically connected to the second electrode pad 62B by a wiring 65B. Note that the first coil 23 is electrically connected to the first electrode pad 61A shown in FIG. 3 by wiring not shown. Similarly, the fourth coil 26 is electrically connected to the second electrode pad 62A shown in FIG. 3 by wiring not shown.
　第３コイル２５と第４コイル２６は、第１絶縁層６４１を挟んで配置されている。第３コイル２５および第４コイル２６は、第１絶縁層６４１の厚さ方向（ｚ方向）に磁気結合可能に配置されている。第３コイル２５は、第１絶縁層６４１の上の第２絶縁層６４２内に配置されている。第４コイル２６は、第１絶縁層６４１の下の第３絶縁層６４３内に配置されている。本実施形態において、第３コイル２５および第４コイル２６の双方は、第１絶縁層６４１と接している。 The third coil 25 and the fourth coil 26 are arranged with the first insulating layer 641 in between. The third coil 25 and the fourth coil 26 are arranged so as to be magnetically coupled in the thickness direction (z direction) of the first insulating layer 641. The third coil 25 is disposed within the second insulating layer 642 above the first insulating layer 641 . The fourth coil 26 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, both the third coil 25 and the fourth coil 26 are in contact with the first insulating layer 641.
　第１コイル２３、第２コイル２４、第３コイル２５、および第４コイル２６は、Ｔｉ（チタン）、ＴｉＮ（窒化チタン）、Ｔａ（タンタル）、ＴａＮ（窒化タンタル）、Ａｕ、Ａｇ、Ｃｕ、Ａｌ、およびＷ（タングステン）のうち１つまたは複数が適宜選択される。本実施形態では、各コイル２３～２６は、Ｃｕを含む材料によって形成されている。配線６５Ａ～６５Ｄは、Ｔｉ（チタン）、ＴｉＮ（窒化チタン）、Ｔａ（タンタル）、ＴａＮ（窒化タンタル）、Ａｕ、Ａｇ、Ｃｕ、Ａｌ、およびＷ（タングステン）のうち１つまたは複数が適宜選択される。本実施形態では、各配線６５Ａ～６５Ｄは、Ｃｕを含む材料によって形成されている。 The first coil 23, the second coil 24, the third coil 25, and the fourth coil 26 are made of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, Ag, Cu, One or more of Al and W (tungsten) is selected as appropriate. In this embodiment, each of the coils 23 to 26 is made of a material containing Cu. For the wirings 65A to 65D, one or more of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, Ag, Cu, Al, and W (tungsten) is appropriately selected. be done. In this embodiment, each of the wirings 65A to 65D is formed of a material containing Cu.
　図３～図５に示されるように、第１キャパシタ３１は、第１電極板３３および第２電極板３４を含む。本実施形態において、第１電極板３３および第２電極板３４の双方は、ｚ方向から視て、四角形状に形成されている。なお、第１電極板３３および第２電極板３４の双方は、ｚ方向から視た形状を、円形状、楕円形状、多角形状、等の任意の形状とすることができる。第１電極板３３および第２電極板３４は、ｚ方向から視て同じ大きさであり、互いに重なるように配置されている。 As shown in FIGS. 3 to 5, the first capacitor 31 includes a first electrode plate 33 and a second electrode plate 34. In this embodiment, both the first electrode plate 33 and the second electrode plate 34 are formed into a rectangular shape when viewed from the z direction. Note that both the first electrode plate 33 and the second electrode plate 34 can have any shape when viewed from the z direction, such as a circular shape, an elliptical shape, and a polygonal shape. The first electrode plate 33 and the second electrode plate 34 have the same size when viewed from the z direction, and are arranged to overlap with each other.
　第２キャパシタ３２は、第３電極板３５および第４電極板３６を含む。本実施形態において、第３電極板３５および第４電極板３６の双方は、ｚ方向から視て、四角形状に形成されている。なお、第３電極板３５および第４電極板３６の双方は、ｚ方向から視た形状を、円形状、楕円形状、多角形状、等の任意の形状とすることができる。第３電極板３５および第４電極板３６は、ｚ方向から視て同じ大きさであり、互いに重なるように配置されている。また、第３電極板３５および第４電極板３６の双方は、ｚ方向から視て、第１電極板３３および第２電極板３４と同一形状、同一サイズである。 The second capacitor 32 includes a third electrode plate 35 and a fourth electrode plate 36. In this embodiment, both the third electrode plate 35 and the fourth electrode plate 36 are formed into a rectangular shape when viewed from the z direction. Note that both the third electrode plate 35 and the fourth electrode plate 36 can have any shape when viewed from the z direction, such as a circular shape, an elliptical shape, and a polygonal shape. The third electrode plate 35 and the fourth electrode plate 36 have the same size when viewed from the z direction, and are arranged to overlap with each other. Further, both the third electrode plate 35 and the fourth electrode plate 36 have the same shape and size as the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction.
　図３、図５に示されるように、第１キャパシタ３１の第１電極板３３は、配線６６Ａにより第１電極パッド６１Ｂに電気的に接続されている。第２キャパシタ３２の第３電極板３５は、配線６６Ｂにより第２電極パッド６２Ｂに電気的に接続されている。図４に示されるように、第１キャパシタ３１の第２電極板３４と第２キャパシタ３２の第４電極板３６は、配線６６Ｃにより互いに電気的に接続されている。図５に示されるように、配線６６Ｃ、配線６６Ｄにより第３基板６３と電気的に接続されている。 As shown in FIGS. 3 and 5, the first electrode plate 33 of the first capacitor 31 is electrically connected to the first electrode pad 61B by a wiring 66A. The third electrode plate 35 of the second capacitor 32 is electrically connected to the second electrode pad 62B by a wiring 66B. As shown in FIG. 4, the second electrode plate 34 of the first capacitor 31 and the fourth electrode plate 36 of the second capacitor 32 are electrically connected to each other by a wiring 66C. As shown in FIG. 5, it is electrically connected to the third substrate 63 by wiring 66C and wiring 66D.
　第１電極板３３、第２電極板３４、第３電極板３５、および第４電極板３６は、Ｔｉ（チタン）、ＴｉＮ（窒化チタン）、Ｔａ（タンタル）、ＴａＮ（窒化タンタル）、Ａｕ、Ａｇ、Ｃｕ、Ａｌ、およびＷ（タングステン）のうち１つまたは複数が適宜選択される。本実施形態では、各電極板３３～３６は、Ｃｕを含む材料によって形成されている。配線６６Ａ～６６Ｄは、Ｔｉ、ＴｉＮ、Ｔａ、ＴａＮ、Ａｕ、Ａｇ、Ｃｕ、Ａｌ、およびＷのうち１つまたは複数が適宜選択される。本実施形態では、各配線６６Ａ～６６Ｄは、Ｃｕを含む材料によって形成されている。 The first electrode plate 33, the second electrode plate 34, the third electrode plate 35, and the fourth electrode plate 36 are made of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, One or more of Ag, Cu, Al, and W (tungsten) is selected as appropriate. In this embodiment, each of the electrode plates 33 to 36 is made of a material containing Cu. For the wirings 66A to 66D, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W is appropriately selected. In this embodiment, each of the wirings 66A to 66D is formed of a material containing Cu.
　図５に示されるように、第１キャパシタ３１の第１電極板３３と第２電極板３４は、第１絶縁層６４１を挟んで配置されている。第１電極板３３および第２電極板３４は、第１絶縁層６４１の厚さ方向に磁気結合可能に配置されている。第１電極板３３は、第１絶縁層６４１の上の第２絶縁層６４２内に配置されている。第２電極板３４は、第１絶縁層６４１の下の第３絶縁層６４３内に配置されている。本実施形態において、第１電極板３３および第２電極板３４は、第１絶縁層６４１と接している。第１電極板３３は、配線６６Ａにより第１電極パッド６１に電気的に接続されている。 As shown in FIG. 5, the first electrode plate 33 and the second electrode plate 34 of the first capacitor 31 are arranged with the first insulating layer 641 in between. The first electrode plate 33 and the second electrode plate 34 are arranged in the thickness direction of the first insulating layer 641 so as to be magnetically coupled. The first electrode plate 33 is disposed within the second insulating layer 642 above the first insulating layer 641 . The second electrode plate 34 is arranged in the third insulating layer 643 under the first insulating layer 641 . In this embodiment, the first electrode plate 33 and the second electrode plate 34 are in contact with the first insulating layer 641. The first electrode plate 33 is electrically connected to the first electrode pad 61 by a wiring 66A.
　第３電極板３５と第４電極板３６は、第１絶縁層６４１を挟んで配置されている。第３電極板３５および第４電極板３６は、第１絶縁層６４１の厚さ方向に磁気結合可能に配置されている。第３電極板３５は、第１絶縁層６４１の上の第２絶縁層６４２内に配置されている。第４電極板３６は、第１絶縁層６４１の下の第３絶縁層６４３内に配置されている。本実施形態において、第３電極板３５および第４電極板３６の双方は、第１絶縁層６４１と接している。第３電極板３５は、配線６６Ｂにより第２電極パッド６２に電気的に接続されている。 The third electrode plate 35 and the fourth electrode plate 36 are arranged with the first insulating layer 641 in between. The third electrode plate 35 and the fourth electrode plate 36 are arranged in the thickness direction of the first insulating layer 641 so as to be magnetically coupled. The third electrode plate 35 is disposed within the second insulating layer 642 above the first insulating layer 641 . The fourth electrode plate 36 is arranged in the third insulating layer 643 under the first insulating layer 641. In this embodiment, both the third electrode plate 35 and the fourth electrode plate 36 are in contact with the first insulating layer 641. The third electrode plate 35 is electrically connected to the second electrode pad 62 by a wiring 66B.
　第１電極板３３および第２電極板３４は、ｚ方向から視て同じ大きさであり、互いに重なるように配置されている。したがって、第１キャパシタ３１は、第１電極板３３および第２電極板３４のｚ方向から視たそれぞれの面積と、第１電極板３３と第２電極板３４との間の距離（第１絶縁層６４１の厚さＴ１）による容量値を持つ。 The first electrode plate 33 and the second electrode plate 34 have the same size when viewed from the z direction, and are arranged to overlap with each other. Therefore, the first capacitor 31 has the following characteristics: the area of each of the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction, and the distance between the first electrode plate 33 and the second electrode plate 34 (the first insulating It has a capacitance value depending on the thickness T1) of the layer 641.
　第３電極板３５および第４電極板３６は、ｚ方向から視て同じ大きさであり、互いに重なるように配置されている。したがって、第１キャパシタ３１は、第１電極板３３および第２電極板３４のｚ方向から視たそれぞれの面積と、第１電極板３３と第２電極板３４との間の距離（第１絶縁層６４１の厚さＴ１）による容量値を持つ。 The third electrode plate 35 and the fourth electrode plate 36 have the same size when viewed from the z direction, and are arranged so as to overlap each other. Therefore, the first capacitor 31 has the following characteristics: the area of each of the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction, and the distance between the first electrode plate 33 and the second electrode plate 34 (the first insulating It has a capacitance value depending on the thickness T1) of the layer 641.
　また、第３電極板３５および第４電極板３６の双方は、ｚ方向から視て、第１電極板３３および第２電極板３４と同一形状、同一サイズである。したがって、第１キャパシタ３１と第２キャパシタ３２は、同じ容量値を有する。 Further, both the third electrode plate 35 and the fourth electrode plate 36 have the same shape and size as the first electrode plate 33 and the second electrode plate 34 when viewed from the z direction. Therefore, the first capacitor 31 and the second capacitor 32 have the same capacitance value.
　次に、図５を参照して、トランスチップ６０における寸法関係の一例について説明する。
　第１コイル２３と第４コイル２６は、絶縁体６４の厚さ方向において同じ位置に配置されている。第２コイル２４と第３コイル２５は、絶縁体６４の厚さ方向において同じ位置に配置されている。第１トランス２１の第１コイル２３と第２トランス２２の第３コイル２５との間の距離Ｄ１は、第１コイル２３と第２コイル２４との間の距離Ｄ２よりも大きい。第１コイル２３と第３コイル２５との間の距離Ｄ１は、第３コイル２５と第４コイル２６との間の距離Ｄ３よりも大きい。第１コイル２３と第３コイル２５との間の距離Ｄ１は、第３基板６３と第２コイル２４との間の距離Ｄ４よりも大きい。第１コイル２３と第３コイル２５との間の距離Ｄ１は、第３基板６３と第４コイル２６との間の距離Ｄ５よりも大きい。第２コイル２４と第２電極板３４との間の距離Ｄ６は、第３基板６３と第２コイル２４との間の距離Ｄ４以上である。第４コイル２６と第４電極板３６との間の距離Ｄ７は、第３基板６３と第４コイル２６との間の距離Ｄ５以上である。 Next, an example of the dimensional relationship in the transformer chip 60 will be described with reference to FIG.
The first coil 23 and the fourth coil 26 are arranged at the same position in the thickness direction of the insulator 64. The second coil 24 and the third coil 25 are arranged at the same position in the thickness direction of the insulator 64. The distance D1 between the first coil 23 of the first transformer 21 and the third coil 25 of the second transformer 22 is larger than the distance D2 between the first coil 23 and the second coil 24. The distance D1 between the first coil 23 and the third coil 25 is larger than the distance D3 between the third coil 25 and the fourth coil 26. The distance D1 between the first coil 23 and the third coil 25 is larger than the distance D4 between the third substrate 63 and the second coil 24. The distance D1 between the first coil 23 and the third coil 25 is larger than the distance D5 between the third substrate 63 and the fourth coil 26. The distance D6 between the second coil 24 and the second electrode plate 34 is greater than or equal to the distance D4 between the third substrate 63 and the second coil 24. The distance D7 between the fourth coil 26 and the fourth electrode plate 36 is greater than or equal to the distance D5 between the third substrate 63 and the fourth coil 26.
　（作用）
　本実施形態の信号伝達装置１０の作用について説明する。
　図６は、比較例のトランスチップ６０Ｘを含む信号伝達装置１０Ｘを示す概略断面図である。比較例のトランスチップ６０Ｘおよび信号伝達装置１０Ｘについて、上記実施形態のトランスチップ６０および信号伝達装置１０と同じ部材については同じ符号を付す。 (effect)
The operation of the signal transmission device 10 of this embodiment will be explained.
FIG. 6 is a schematic cross-sectional view showing a signal transmission device 10X including a transformer chip 60X of a comparative example. Regarding the transformer chip 60X and signal transmission device 10X of the comparative example, the same members as those of the transformer chip 60 and signal transmission device 10 of the above embodiment are given the same reference numerals.
　比較例のトランスチップ６０Ｘは、上記実施形態のトランスチップ６０と比べ、第１キャパシタ３１および第２キャパシタ３２を有してないものである。
　図６に示される信号伝達装置１０Ｘでは、上記実施形態の信号伝達装置１０と同様に、比較例のトランスチップ６０Ｘは、中間ダイパッド７３に搭載されている。中間ダイパッド７３および中間ダイパッド７３に電気的に接続された第３基板６３は、第１チップ４０および第２チップ５０、１次側ダイパッド７１および２次側ダイパッド７２に対してフローティング状態にある。 The transformer chip 60X of the comparative example does not have the first capacitor 31 and the second capacitor 32, compared to the transformer chip 60 of the above embodiment.
In the signal transmission device 10X shown in FIG. 6, the transformer chip 60X of the comparative example is mounted on the intermediate die pad 73, similar to the signal transmission device 10 of the above embodiment. The intermediate die pad 73 and the third substrate 63 electrically connected to the intermediate die pad 73 are in a floating state with respect to the first chip 40 and the second chip 50, the primary die pad 71, and the secondary die pad 72.
　比較例のトランスチップ６０Ｘを１次側ダイパッド７１に搭載した場合、第３基板６３の電位は、１次側ダイパッド７１に搭載された第１チップ４０の第１基板４３の電位と等しくなる。このため、比較例のトランスチップ６０Ｘでは、第３基板６３と第２トランス２２（第３コイル２５）との間の距離が、１次側回路１３と２次側回路１４との間の電位差、つまり絶縁耐圧に応じて必要となる。トランスチップ６０Ｘの絶縁耐圧を高くするためには、第３基板６３と第２トランス２２（第３コイル２５）との間の距離を大きくする、つまり絶縁体６４の厚さを厚くする必要がある。絶縁体６４の厚さは、トランスチップ６０Ｘを製造するプロセス（工程）の変更や、製造時において第３基板６３（半導体ウエハ）の反り、等に影響する。絶縁体６４を厚くするほど、工程数が増加し、反りは大きくなる。このため、絶縁体６４の厚さを厚くすることには限界がある。比較例のトランスチップ６０Ｘを２次側ダイパッド７２に搭載する場合も同様の問題が生じる。 When the comparative example transformer chip 60X is mounted on the primary die pad 71, the potential of the third substrate 63 becomes equal to the potential of the first substrate 43 of the first chip 40 mounted on the primary die pad 71. Therefore, in the transformer chip 60X of the comparative example, the distance between the third substrate 63 and the second transformer 22 (third coil 25) is equal to the potential difference between the primary circuit 13 and the secondary circuit 14; In other words, it is necessary depending on the dielectric strength voltage. In order to increase the dielectric strength of the transformer chip 60X, it is necessary to increase the distance between the third substrate 63 and the second transformer 22 (third coil 25), that is, to increase the thickness of the insulator 64. . The thickness of the insulator 64 influences changes in the process for manufacturing the transformer chip 60X, warping of the third substrate 63 (semiconductor wafer) during manufacturing, and the like. As the insulator 64 becomes thicker, the number of steps increases and the warpage increases. Therefore, there is a limit to increasing the thickness of the insulator 64. A similar problem occurs when the comparative example transformer chip 60X is mounted on the secondary die pad 72.
　これに対し、図６に示される信号伝達装置１０では、１次側ダイパッド７１および２次側ダイパッド７２から電気的に離隔された中間ダイパッド７３にトランスチップ６０Ｘが搭載されている。中間ダイパッド７３は、１次側ダイパッド７１および２次側ダイパッド７２に対して、フローティング状態である。このため、比較例のトランスチップ６０Ｘは、第３基板６３と第１コイル２３および第３コイル２５との間の距離を大きくすることなく、絶縁耐圧の向上が可能である。 On the other hand, in the signal transmission device 10 shown in FIG. 6, the transformer chip 60X is mounted on an intermediate die pad 73 that is electrically separated from the primary die pad 71 and the secondary die pad 72. The intermediate die pad 73 is in a floating state with respect to the primary die pad 71 and the secondary die pad 72. Therefore, the transformer chip 60X of the comparative example can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
　しかしながら、比較例のトランスチップ６０Ｘおよび信号伝達装置１０Ｘでは、中間ダイパッド７３および第３基板６３が電気的にフローティング状態である。このため、中間ダイパッド７３の電位は、１次側ダイパッド７１の電位の影響を受ける場合がある。この場合、比較例のトランスチップ６０Ｘを１次側ダイパッド７１に搭載したときと同様となる。つまり、第３基板６３が第１チップの電位となるため、トランスチップ６０Ｘの絶縁耐圧を超える場合がある。 However, in the comparative example transformer chip 60X and signal transmission device 10X, the intermediate die pad 73 and the third substrate 63 are in an electrically floating state. Therefore, the potential of the intermediate die pad 73 may be affected by the potential of the primary die pad 71. In this case, it is the same as when the transformer chip 60X of the comparative example is mounted on the primary die pad 71. In other words, since the potential of the third substrate 63 is the same as that of the first chip, the dielectric breakdown voltage of the transformer chip 60X may be exceeded.
　本実施形態のトランスチップ６０は、１次側ダイパッド７１および２次側ダイパッド７２から電気的に離隔された中間ダイパッド７３に搭載されている。したがって、図６に示される比較例のトランスチップ６０Ｘと同様に、第３基板６３と第１コイル２３および第３コイル２５との間の距離を大きくすることなく、絶縁耐圧を向上することができる。 The transformer chip 60 of this embodiment is mounted on an intermediate die pad 73 electrically separated from the primary die pad 71 and the secondary die pad 72. Therefore, similarly to the comparative example transformer chip 60X shown in FIG. 6, the dielectric strength can be improved without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25. .
　本実施形態のトランスチップ６０は、第１電極パッド６１と電気的に接続された第１キャパシタ３１と、第２電極パッド６２と電気的に接続され、第１キャパシタ３１と電気的に直列に接続された第２キャパシタ３２とを含む。第１キャパシタ３１と第２キャパシタ３２は、接続部としての配線６６Ｃ，６６Ｄにより第３基板６３と電気的に接続される。 The transformer chip 60 of this embodiment has a first capacitor 31 electrically connected to a first electrode pad 61, a second electrode pad 62, and electrically connected in series with the first capacitor 31. and a second capacitor 32. The first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63 by wirings 66C and 66D as connection parts.
　第１電極パッド６１は、第１チップ４０に電気的接続される。第２電極パッド６２は、第２チップ５０に電気的に接続される。したがって、第３基板６３の電位は、第１電極パッド６１の電位と、第２電極パッド６２の電位との間の電位となる。上記実施形態では、第１キャパシタ３１の容量値と、第２キャパシタ３２の容量値は、互いに等しい。したがって、第３基板６３の電位は、第１電極パッド６１の電位と、第２電極パッド６２の電位との間の中間の電位（１／２）となる。つまり、本実施形態において、トランスチップ６０の第３基板６３は、フローティング状態ではなく、第１電極パッド６１と第２電極パッド６２とに加わる電圧の間の電位となる。 The first electrode pad 61 is electrically connected to the first chip 40. The second electrode pad 62 is electrically connected to the second chip 50. Therefore, the potential of the third substrate 63 is between the potential of the first electrode pad 61 and the potential of the second electrode pad 62. In the embodiment described above, the capacitance value of the first capacitor 31 and the capacitance value of the second capacitor 32 are equal to each other. Therefore, the potential of the third substrate 63 becomes an intermediate potential (1/2) between the potential of the first electrode pad 61 and the potential of the second electrode pad 62. That is, in this embodiment, the third substrate 63 of the transformer chip 60 is not in a floating state, but has a potential between the voltages applied to the first electrode pad 61 and the second electrode pad 62.
　図２に示される信号伝達装置１０において、トランスチップ６０の第３基板６３および中間ダイパッド７３の電位は、第１電極パッド６１と接続される第１チップ４０（１次側回路１３）と第２チップ５０（２次側回路１４）の間の電位となる。このため、高圧側となる第１チップ４０が搭載された１次側ダイパッド７１の電位の影響を受け難くなる。このため、本実施形態のトランスチップ６０は、第３基板６３と第１コイル２３および第３コイル２５との間の距離を大きくすることなく、絶縁耐圧を向上することができる。 In the signal transmission device 10 shown in FIG. This is the potential between the chips 50 (secondary side circuits 14). Therefore, it becomes less susceptible to the influence of the potential of the primary die pad 71 on which the first chip 40, which is on the high voltage side, is mounted. Therefore, the transformer chip 60 of this embodiment can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
　以上記述したように、本実施形態によれば、以下の効果を奏する。
　（１）トランスチップ６０は、１次側ダイパッド７１および２次側ダイパッド７２から電気的に離隔された中間ダイパッド７３に搭載されている。したがって、第３基板６３と第１コイル２３および第３コイル２５との間の距離を大きくすることなく、絶縁耐圧を向上することができる。 As described above, according to this embodiment, the following effects are achieved.
(1) The transformer chip 60 is mounted on an intermediate die pad 73 electrically separated from the primary die pad 71 and the secondary die pad 72. Therefore, the dielectric strength can be improved without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
　（２）信号伝達装置１０において、トランスチップ６０の第３基板６３および中間ダイパッド７３の電位は、第１電極パッド６１と接続される第１チップ４０（１次側回路１３）と第２チップ５０（２次側回路１４）との間の電位となる。このため、高圧側となる第１チップ４０が搭載された１次側ダイパッド７１の電位の影響を受け難くなる。このため、トランスチップ６０は、第３基板６３と第１コイル２３および第３コイル２５との間の距離を大きくすることなく、絶縁耐圧を向上することができる。 (2) In the signal transmission device 10, the potentials of the third substrate 63 and the intermediate die pad 73 of the transformer chip 60 are the same as those of the first chip 40 (primary side circuit 13) and the second chip 50 connected to the first electrode pad 61. (secondary side circuit 14). Therefore, it becomes less susceptible to the influence of the potential of the primary die pad 71 on which the first chip 40, which is on the high voltage side, is mounted. Therefore, the transformer chip 60 can improve the dielectric strength without increasing the distance between the third substrate 63 and the first coil 23 and the third coil 25.
　（変更例）
　上記実施形態は例えば以下のように変更できる。上記実施形態と以下の各変更例は、技術的な矛盾が生じない限り、互いに組み合せることができる。なお、以下の変更例において、上記実施形態と共通する部分については、上記実施形態と同一の符号を付してその説明を省略する。 (Example of change)
The above embodiment can be modified as follows, for example. The above embodiment and each modification example below can be combined with each other as long as no technical contradiction occurs. In addition, in the following modified examples, parts common to the above embodiment are given the same reference numerals as in the above embodiment, and the explanation thereof will be omitted.
　・上記実施形態のトランスチップ６０の構成は適宜変更することができる。
　図７に示される信号伝達装置１１０のトランスチップ６０Ａにおいて、第１キャパシタ３１と第２キャパシタ３２はそれぞれ、配線６７Ａ，６７Ｂにより第３基板６３に電気的に接続されている。詳しくは、第１キャパシタ３１の第２電極板３４は、配線６７Ａにより第３基板６３に電気的に接続されている。第２キャパシタ３２の第４電極板３６は、配線６７Ｂにより第３基板６３に電気的に接続されている。つまり、第１キャパシタ３１と第２キャパシタ３２は、第３基板６３および配線６７Ａ，６７Ｂを介して互いに接続されている。このように構成されるトランスチップ６０Ａにおいても、第３基板６３の電位を第１電極パッド６１Ｂと第２電極パッド６２Ｂとにそれぞれ加わる電圧の中間電圧とすることができる。このため、トランスチップ６０Ａの絶縁耐圧を向上することができる。 - The configuration of the transformer chip 60 of the above embodiment can be changed as appropriate.
In the transformer chip 60A of the signal transmission device 110 shown in FIG. 7, the first capacitor 31 and the second capacitor 32 are electrically connected to the third substrate 63 by wirings 67A and 67B, respectively. Specifically, the second electrode plate 34 of the first capacitor 31 is electrically connected to the third substrate 63 by a wiring 67A. The fourth electrode plate 36 of the second capacitor 32 is electrically connected to the third substrate 63 by a wiring 67B. That is, the first capacitor 31 and the second capacitor 32 are connected to each other via the third substrate 63 and the wirings 67A and 67B. Also in the transformer chip 60A configured in this manner, the potential of the third substrate 63 can be set to an intermediate voltage between the voltages applied to the first electrode pad 61B and the second electrode pad 62B, respectively. Therefore, the dielectric strength of the transformer chip 60A can be improved.
　図８に示される信号伝達装置１１２のトランスチップ６０Ｂは、第１接続電極および第２接続電極に相当する第１電極パッド６１Ｂおよび第２電極パッド６２Ｂは、第１絶縁層６４１の上面６４１Ｓに配置されている。第１電極パッド６１Ｂおよび第２電極パッド６２Ｂは、第１絶縁層６４１に接している。また、トランスチップ６０Ｂは、第１絶縁層６４１を挟んで第１電極パッド６１Ｂと対向する第１対向電極６８Ａと、第１絶縁層６４１を挟んで第２電極パッド６２Ｂと対向する第２対向電極６８Ｂと、を含む。第１対向電極６８Ａと第２対向電極６８Ｂは、配線６６Ｃにより互いに電気的に接続されている。その配線６６Ｃは、配線６６Ｄにより第３基板６３に接続されている。第１キャパシタ３１は、第１絶縁層６４１を挟む第１電極パッド６１Ｂと第１対向電極６８Ａとにより構成される。第２キャパシタ３２は、第１絶縁層６４１を挟む第２電極パッド６２Ｂと第２対向電極６８Ｂとにより構成される。このように構成されるトランスチップ６０Ｂにおいても、第３基板６３の電位を第１電極パッド６１Ｂと第２電極パッド６２Ｂとにそれぞれ加わる電圧の中間電圧とすることができる。このため、トランスチップ６０Ｂの絶縁耐圧を向上することができる。 In the transformer chip 60B of the signal transmission device 112 shown in FIG. has been done. The first electrode pad 61B and the second electrode pad 62B are in contact with the first insulating layer 641. The transformer chip 60B also includes a first opposing electrode 68A that faces the first electrode pad 61B with the first insulating layer 641 in between, and a second opposing electrode that faces the second electrode pad 62B with the first insulating layer 641 in between. 68B. The first opposing electrode 68A and the second opposing electrode 68B are electrically connected to each other by a wiring 66C. The wiring 66C is connected to the third substrate 63 by a wiring 66D. The first capacitor 31 includes a first electrode pad 61B and a first counter electrode 68A, which sandwich a first insulating layer 641 therebetween. The second capacitor 32 is composed of a second electrode pad 62B and a second opposing electrode 68B, which sandwich the first insulating layer 641 therebetween. Also in the transformer chip 60B configured in this manner, the potential of the third substrate 63 can be set to an intermediate voltage between the voltages applied to the first electrode pad 61B and the second electrode pad 62B, respectively. Therefore, the dielectric strength of the transformer chip 60B can be improved.
　・１次側回路１３と２次側回路１４との間に複数のトランスが設けられてもよい。
　図９に示される信号伝達装置１１４（信号伝達回路１１４Ａ）は、１次側回路１３と２次側回路１４との間に、２つのトランス１５Ａ，１５Ｂを有している。２つのトランス１５Ａ，１５Ｂは、上記実施形態のトランス１５と同一構成であり、それぞれ第１トランス２１および第２トランス２２を含む。これら２つのトランス１５Ａ，１５Ｂは、たとえば、２次側回路１４から１次側回路１３に向けて信号を伝達するために用いられる。なお、２つのトランス１５Ａ，１５Ｂは、１次側回路１３から２次側回路１４に向けて信号を伝達するために用いられてもよい。また、トランス１５Ａは２次側回路１４から１次側回路１３に向けて信号を伝達するために用いられ、トランス１５Ｂは１次側回路１３から２次側回路１４に向けて信号を伝達するために用いられてもよい。２つのトランス１５Ａ，１５Ｂは、上記実施形態のトランスチップ６０を２つ用いてもよいし、１つのトランスチップとして構成されてもよい。なお、１次側回路１３と２次側回路１４との間に、３つ以上のトランスが設けられてもよい。 - A plurality of transformers may be provided between the primary side circuit 13 and the secondary side circuit 14.
The signal transmission device 114 (signal transmission circuit 114A) shown in FIG. 9 has two transformers 15A and 15B between the primary side circuit 13 and the secondary side circuit 14. The two transformers 15A and 15B have the same configuration as the transformer 15 of the above embodiment, and each includes a first transformer 21 and a second transformer 22. These two transformers 15A and 15B are used, for example, to transmit a signal from the secondary circuit 14 to the primary circuit 13. Note that the two transformers 15A and 15B may be used to transmit signals from the primary circuit 13 to the secondary circuit 14. Further, the transformer 15A is used to transmit a signal from the secondary circuit 14 to the primary circuit 13, and the transformer 15B is used to transmit a signal from the primary circuit 13 to the secondary circuit 14. May be used for. The two transformers 15A and 15B may use two transformer chips 60 of the above embodiment, or may be configured as one transformer chip. Note that three or more transformers may be provided between the primary circuit 13 and the secondary circuit 14.
　本開示で使用される「～上に」という用語は、文脈によって明らかにそうでないことが示されない限り、「～上に」と「～の上方に」との双方の意味を含む。したがって、「第１層が第２層上に形成される」という表現は、或る実施形態では第１層が第２層に接触して第２層上に直接配置され得るが、他の実施形態では第１層が第２層に接触することなく第２層の上方に配置され得ることが意図される。すなわち、「～上に」という用語は、第１層と第２層との間に他の層が形成される構造を排除しない。 As used in this disclosure, the term "on" includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "the first layer is formed on the second layer" refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term "on" does not exclude structures in which other layers are formed between the first layer and the second layer.
　本開示で使用されるＺ軸方向は必ずしも鉛直方向である必要はなく、鉛直方向に完全に一致している必要もない。したがって、本開示による種々の構造（たとえば、図１に示される構造）は、本明細書で説明されるＺ軸方向の「上」および「下」が鉛直方向の「上」および「下」であることに限定されない。たとえば、Ｘ軸方向が鉛直方向であってもよく、またはＹ軸方向が鉛直方向であってもよい。 The Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. Accordingly, various structures according to the present disclosure (e.g., the structure shown in FIG. 1) are different from each other in that "upper" and "lower" in the Z-axis direction described herein are "upper" and "lower" in the vertical direction. Not limited to one thing. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.
　（付記）
　本開示から把握できる技術的思想を以下に記載する。なお、限定する意図ではなく理解の補助のために、付記に記載される構成要素には、実施形態中の対応する構成要素の参照符号が付されている。参照符号は、理解の補助のために例として示すものであり、各付記に記載された構成要素は、参照符号で示される構成要素に限定されるべきではない。 (Additional note)
The technical ideas that can be understood from this disclosure are described below. Note that, not for the purpose of limitation but for the purpose of aiding understanding, the reference numerals of the corresponding components in the embodiments are attached to the components described in the supplementary notes. Reference numerals are shown by way of example to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.
　（付記１）
　導電性を有する基板（６３）と、
　前記基板（６３）上に設けられ、前記基板（６３）と平行に配置される第１絶縁層（６４１）を含む絶縁体（６４）と、
　前記第１絶縁層（６４１）を挟んで配置されるとともに前記第１絶縁層（６４１）の厚さ方向に磁気結合可能に配置された第１コイル（２３）および第２コイル（２４）を含む第１トランス（２１）と、前記第１絶縁層（６４１）を挟んで配置されるとともに前記第１絶縁層（６４１）の厚さ方向に磁気結合可能に配置された第３コイル（２５）および第４コイル（２６）を含み且つ前記第１トランス（２１）と電気的に接続された第２トランス（２２）と、を有する絶縁トランス（１５）と、
　前記絶縁トランス（１５）に電気的に接続され、外部との電気的な接続に用いられる第１接続電極（６１Ｂ）および第２接続電極（６２Ｂ）と、
　前記第１接続電極（６１Ｂ）と電気的に接続された第１キャパシタ（３１）と、
　前記第２接続電極（６２Ｂ）と電気的に接続され、前記第１キャパシタ（３１）と電気的に直列に接続された第２キャパシタ（３２）と、
　前記第１キャパシタ（３１）および前記第２キャパシタ（３２）を前記基板（６３）に電気的に接続する接続部（６６Ｃ，６６Ｄ，６７Ａ，６７Ｂ）と、
　を含む、トランスチップ。 (Additional note 1)
a conductive substrate (63);
an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63);
A first coil (23) and a second coil (24) are arranged to sandwich the first insulating layer (641) and are arranged to be magnetically coupled in the thickness direction of the first insulating layer (641). A first transformer (21), a third coil (25) that is arranged to sandwich the first insulating layer (641) and magnetically coupled in the thickness direction of the first insulating layer (641); an isolation transformer (15) having a second transformer (22) including a fourth coil (26) and electrically connected to the first transformer (21);
A first connection electrode (61B) and a second connection electrode (62B) that are electrically connected to the insulation transformer (15) and used for electrical connection with the outside;
a first capacitor (31) electrically connected to the first connection electrode (61B);
a second capacitor (32) electrically connected to the second connection electrode (62B) and electrically connected in series with the first capacitor (31);
connection parts (66C, 66D, 67A, 67B) that electrically connect the first capacitor (31) and the second capacitor (32) to the substrate (63);
Including transformer chip.
　（付記２）
　前記第１キャパシタ（３１）および前記第２キャパシタ（３２）は、同じ容量を有するように形成されている、付記１に記載のトランスチップ。 (Additional note 2)
The transformer chip according to appendix 1, wherein the first capacitor (31) and the second capacitor (32) are formed to have the same capacitance.
　（付記３）
　前記第１キャパシタ（３１）は、前記絶縁体（６４）内に設けられ、前記第１接続電極（６１Ｂ）に電気的に接続された第１電極板（３３）と、前記絶縁体（６４）内に設けられ、前記第１絶縁層（６４１）を介して前記第１電極板（３３）と対向して配置された第２電極板（３４）と、を含み、
　前記第２キャパシタ（３２）は、前記絶縁体（６４）内に設けられ、前記第２接続電極（６２Ｂ）に電気的に接続された第３電極板（３５）と、前記絶縁体（６４）内に設けられ、前記第１絶縁層（６４１）を介して前記第３電極板（３５）と対向して配置された第４電極板（３６）と、を含み、
　前記接続部（６６Ｃ，６６Ｄ，６７Ａ，６７Ｂ）は、前記第２電極板（３４）および前記第４電極板（３６）を前記基板（６３）に接続する、
　付記１または付記２に記載のトランスチップ。 (Additional note 3)
The first capacitor (31) includes a first electrode plate (33) provided within the insulator (64) and electrically connected to the first connection electrode (61B), and the insulator (64). a second electrode plate (34) provided therein and disposed opposite to the first electrode plate (33) with the first insulating layer (641) interposed therebetween;
The second capacitor (32) includes a third electrode plate (35) provided within the insulator (64) and electrically connected to the second connection electrode (62B), and the insulator (64). a fourth electrode plate (36) provided therein and disposed opposite to the third electrode plate (35) with the first insulating layer (641) interposed therebetween;
The connecting portions (66C, 66D, 67A, 67B) connect the second electrode plate (34) and the fourth electrode plate (36) to the substrate (63).
The transformer chip according to appendix 1 or appendix 2.
　（付記４）
　前記第１キャパシタ（３１）は、前記第１接続電極（６１Ｂ）と、前記絶縁体（６４）内における前記第１絶縁層（６４１）を介して前記第１接続電極（６１Ｂ）と対向する位置に設けられた第１対向電極（６８Ａ）とにより構成され、
　前記第２キャパシタ（３２）は、前記第２接続電極（６２Ｂ）と、前記絶縁体（６４）内における前記第１絶縁層（６４１）を介して前記第２接続電極（６２Ｂ）と対向する位置に設けられた第２対向電極（６８Ｂ）とにより構成され、
　前記接続部（６６Ｃ，６６Ｄ）は、前記第１対向電極（６８Ａ）および前記第２対向電極（６８Ｂ）を前記基板（６３）に接続する、
　付記１または付記２に記載のトランスチップ。 (Additional note 4)
The first capacitor (31) is located at a position opposite to the first connection electrode (61B) via the first insulating layer (641) in the insulator (64). a first counter electrode (68A) provided in the
The second capacitor (32) is located at a position opposite to the second connection electrode (62B) through the first insulating layer (641) in the insulator (64). a second opposing electrode (68B) provided in the
The connection portion (66C, 66D) connects the first counter electrode (68A) and the second counter electrode (68B) to the substrate (63).
The transformer chip according to appendix 1 or appendix 2.
　（付記５）
　前記第１コイル（２３）は前記第１接続電極（６１Ｂ）に接続され、
　前記第３コイル（２５）は前記第２接続電極（６２Ｂ）に接続され、
　前記第２コイル（２４）および前記第４コイル（２６）は互いに接続されている、
　付記１から付記４のいずれか一つに記載のトランスチップ。 (Appendix 5)
The first coil (23) is connected to the first connection electrode (61B),
The third coil (25) is connected to the second connection electrode (62B),
the second coil (24) and the fourth coil (26) are connected to each other;
The transformer chip according to any one of Supplementary notes 1 to 4.
　（付記６）
　前記絶縁体（６４）は、前記第１絶縁層（６４１）の上の第２絶縁層（６４２）と、前記第１絶縁層（６４１）の下の第３絶縁層（６４３）とを含み、
　前記第１コイル（２３）および前記第３コイル（２５）は前記第２絶縁層（６４２）内に配置され、
　前記第２コイル（２４）および前記第４コイル（２６）は前記第３絶縁層（６４３）内に配置されている、
　付記１から付記５のいずれか一つに記載のトランスチップ。 (Appendix 6)
The insulator (64) includes a second insulating layer (642) above the first insulating layer (641) and a third insulating layer (643) below the first insulating layer (641),
The first coil (23) and the third coil (25) are arranged within the second insulating layer (642),
the second coil (24) and the fourth coil (26) are arranged within the third insulating layer (643);
The transformer chip according to any one of Supplementary notes 1 to 5.
　（付記７）
　第１回路（１３）を含む第１チップ（４０）と、
　トランスチップ（６０）と、
　前記トランスチップ（６０）を通して前記第１回路（１３）と信号の送信および受信の少なくとも一方を行うように構成された第２回路（１４）を含む第２チップ（５０）と、
　前記第１チップ（４０）が実装された第１ダイパッド（７１）と、
　前記第２チップ（５０）が実装された第２ダイパッド（７２）と、
　前記第１ダイパッド（７１）および前記第２ダイパッド（７２）の双方と絶縁され、前記トランスチップ（６０）が実装された第３ダイパッド（７３）と、を含み、
　前記トランスチップ（６０）は、
　導電性を有する基板（６３）と、
　前記基板（６３）上に設けられ、前記基板（６３）と平行に配置される第１絶縁層（６４１）を含む絶縁体（６４）と、
　前記第１絶縁層（６４１）を挟んで配置されるとともに前記第１絶縁層（６４１）の厚さ方向に磁気結合可能に配置された第１コイル（２３）および第２コイル（２４）を含む第１トランス（２１）と、前記第１絶縁層（６４１）を挟んで配置されるとともに前記第１絶縁層（６４１）の厚さ方向に磁気結合可能に配置された第３コイル（２５）および第４コイル（２６）を含み且つ前記第１トランス（２１）と電気的に接続された第２トランス（２２）と、を有する絶縁トランス（１５）と、
　前記絶縁トランス（１５）に電気的に接続され、外部との電気的な接続に用いられる第１接続電極（６１Ｂ）および第２接続電極（６２Ｂ）と、
　前記第１接続電極（６１Ｂ）と電気的に接続された第１キャパシタ（３１）と、
　前記第２接続電極（６２Ｂ）と電気的に接続され、前記第１キャパシタ（３１）と電気的に直列に接続された第２キャパシタ（３２）と、
　前記第１キャパシタ（３１）および前記第２キャパシタ（３２）を前記基板（６３）に電気的に接続する接続部と、
　を含む、
　信号伝達装置。 (Appendix 7)
a first chip (40) including a first circuit (13);
Transformer chip (60) and
a second chip (50) including a second circuit (14) configured to at least one transmit and receive signals with the first circuit (13) through the transformer chip (60);
a first die pad (71) on which the first chip (40) is mounted;
a second die pad (72) on which the second chip (50) is mounted;
a third die pad (73) insulated from both the first die pad (71) and the second die pad (72), and on which the transformer chip (60) is mounted;
The transformer chip (60) is
a conductive substrate (63);
an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63);
A first coil (23) and a second coil (24) are arranged to sandwich the first insulating layer (641) and are arranged to be magnetically coupled in the thickness direction of the first insulating layer (641). A first transformer (21), a third coil (25) that is arranged to sandwich the first insulating layer (641) and magnetically coupled in the thickness direction of the first insulating layer (641); an isolation transformer (15) having a second transformer (22) including a fourth coil (26) and electrically connected to the first transformer (21);
A first connection electrode (61B) and a second connection electrode (62B) that are electrically connected to the insulation transformer (15) and used for electrical connection with the outside;
a first capacitor (31) electrically connected to the first connection electrode (61B);
a second capacitor (32) electrically connected to the second connection electrode (62B) and electrically connected in series with the first capacitor (31);
a connection part that electrically connects the first capacitor (31) and the second capacitor (32) to the substrate (63);
including,
Signal transmission device.
　（付記８）
　前記トランスチップ（６０）は、導電性接合材（８３）により前記第３ダイパッド（７３）に電気的に接続されている、付記７に記載の信号伝達装置。 (Appendix 8)
The signal transmission device according to appendix 7, wherein the transformer chip (60) is electrically connected to the third die pad (73) by a conductive bonding material (83).
　（付記９）
　前記第１キャパシタ（３１）および前記第２キャパシタ（３２）は、同じ容量を有するように形成されている、付記７または付記８に記載の信号伝達装置。 (Appendix 9)
The signal transmission device according to appendix 7 or 8, wherein the first capacitor (31) and the second capacitor (32) are formed to have the same capacitance.
　（付記１０）
　前記第１キャパシタ（３１）は、前記絶縁体（６４）内に設けられ、前記第１接続電極（６１Ｂ）に電気的に接続された第１電極板（３３）と、前記絶縁体（６４）内に設けられ、前記第１絶縁層（６４１）を介して前記第１電極板（３３）と対向して配置された第２電極板（３４）と、を含み、
　前記第２キャパシタ（３２）は、前記絶縁体（６４）内に設けられ、前記第２接続電極（６２Ｂ）に電気的に接続された第３電極板（３５）と、前記絶縁体（６４）内に設けられ、前記第１絶縁層（６４１）を介して前記第３電極板（３５）と対向して配置された第４電極板（３６）と、を含み、
　前記接続部は、前記第２電極板（３４）および前記第４電極板（３６）を前記基板（６３）に接続する、
　付記７から付記９のいずれか一つに記載の信号伝達装置。 (Appendix 10)
The first capacitor (31) includes a first electrode plate (33) provided within the insulator (64) and electrically connected to the first connection electrode (61B), and the insulator (64). a second electrode plate (34) provided therein and disposed opposite to the first electrode plate (33) with the first insulating layer (641) interposed therebetween;
The second capacitor (32) includes a third electrode plate (35) provided within the insulator (64) and electrically connected to the second connection electrode (62B), and the insulator (64). a fourth electrode plate (36) provided therein and disposed opposite to the third electrode plate (35) with the first insulating layer (641) interposed therebetween;
The connecting portion connects the second electrode plate (34) and the fourth electrode plate (36) to the substrate (63).
The signal transmission device according to any one of Supplementary notes 7 to 9.
　（付記１１）
　前記第１キャパシタ（３１）は、前記第１接続電極（６１Ｂ）と、前記絶縁体（６４）内における前記第１絶縁層（６４１）を介して前記第１接続電極（６１Ｂ）と対向する位置に設けられた第１対向電極（６８Ａ）とにより構成され、
　前記第２キャパシタ（３２）は、前記第２接続電極（６２Ｂ）と、前記絶縁体（６４）内における前記第１絶縁層（６４１）を介して前記第２接続電極（６２Ｂ）と対向する位置に設けられた第２対向電極（６８Ｂ）とにより構成され、
　前記接続部は、前記第１対向電極（６８Ａ）および前記第２対向電極（６８Ｂ）を前記基板（６３）に接続する、
　付記７から付記９のいずれか一つに記載の信号伝達装置。 (Appendix 11)
The first capacitor (31) is located at a position opposite to the first connection electrode (61B) via the first insulating layer (641) in the insulator (64). a first counter electrode (68A) provided in the
The second capacitor (32) is located at a position opposite to the second connection electrode (62B) through the first insulating layer (641) in the insulator (64). a second opposing electrode (68B) provided in the
The connection portion connects the first counter electrode (68A) and the second counter electrode (68B) to the substrate (63).
The signal transmission device according to any one of Supplementary notes 7 to 9.
　（付記１２）
　前記第１コイル（２３）は前記第１接続電極（６１Ｂ）に接続され、
　前記第３コイル（２５）は前記第２接続電極（６２Ｂ）に接続され、
　前記第２コイル（２４）および前記第４コイル（２６）は互いに接続されている、
　付記７から付記１１のいずれか一つに記載の信号伝達装置。 (Appendix 12)
The first coil (23) is connected to the first connection electrode (61B),
The third coil (25) is connected to the second connection electrode (62B),
the second coil (24) and the fourth coil (26) are connected to each other;
The signal transmission device according to any one of Supplementary notes 7 to 11.
　（付記１３）
　前記絶縁体（６４）は、前記第１絶縁層（６４１）の上の第２絶縁層（６４２）と、前記第１絶縁層（６４１）の下の第３絶縁層（６４３）とを含み、
　前記第１コイル（２３）および前記第３コイル（２５）は前記第２絶縁層（６４２）内に配置され、
　前記第２コイル（２４）および前記第４コイル（２６）は前記第３絶縁層（６４３）内に配置されている、
　付記７から付記１２のいずれか一つに記載の信号伝達装置。 (Appendix 13)
The insulator (64) includes a second insulating layer (642) above the first insulating layer (641) and a third insulating layer (643) below the first insulating layer (641),
The first coil (23) and the third coil (25) are arranged within the second insulating layer (642),
the second coil (24) and the fourth coil (26) are arranged within the third insulating layer (643);
The signal transmission device according to any one of attachments 7 to 12.
　（付記１４）
　第１回路（１３）を含む第１チップ（４０）と、
　トランスチップ（６０）と、
　前記トランスチップ（６０）を通して前記第１回路（１３）と信号の送信および受信の少なくとも一方を行うように構成された第２回路（１４）を含む第２チップ（５０）と、
　前記第１チップ（４０）が実装された第１ダイパッド（７１）と、
　前記第２チップ（５０）が実装された第２ダイパッド（７２）と、
　前記第１ダイパッド（７１）および前記第２ダイパッド（７２）の双方と絶縁され、前記トランスチップ（６０）が実装された第３ダイパッド（７３）と、
　を含み、
　前記トランスチップ（６０）は、
　導電性を有する基板（６３）と、
　前記基板（６３）上に設けられ、前記基板（６３）と平行に配置される第１絶縁層（６４１）を含む絶縁体（６４）と、
　前記第１絶縁層（６４１）を挟んで配置されるとともに前記第１絶縁層（６４１）の厚さ方向に磁気結合可能に配置された第１コイル（２３）および第２コイル（２４）を含む第１トランス（２１）と、前記第１絶縁層（６４１）を挟んで配置されるとともに前記第１絶縁層（６４１）の厚さ方向に磁気結合可能に配置された第３コイル（２５）および第４コイル（２６）を含み且つ前記第１トランス（２１）と電気的に接続された第２トランス（２２）と、を有する絶縁トランス（１５）と、
　前記絶縁トランス（１５）に電気的に接続され、外部との電気的な接続に用いられる第１接続電極（６１Ｂ）および第２接続電極（６２Ｂ）と、
　を含む、
　信号伝達装置。 (Appendix 14)
a first chip (40) including a first circuit (13);
Transformer chip (60) and
a second chip (50) including a second circuit (14) configured to at least one transmit and receive signals with the first circuit (13) through the transformer chip (60);
a first die pad (71) on which the first chip (40) is mounted;
a second die pad (72) on which the second chip (50) is mounted;
a third die pad (73) that is insulated from both the first die pad (71) and the second die pad (72) and has the transformer chip (60) mounted thereon;
including;
The transformer chip (60) is
a conductive substrate (63);
an insulator (64) provided on the substrate (63) and including a first insulating layer (641) arranged parallel to the substrate (63);
A first coil (23) and a second coil (24) are arranged to sandwich the first insulating layer (641) and are arranged to be magnetically coupled in the thickness direction of the first insulating layer (641). A first transformer (21), a third coil (25) that is arranged to sandwich the first insulating layer (641) and magnetically coupled in the thickness direction of the first insulating layer (641); an isolation transformer (15) having a second transformer (22) including a fourth coil (26) and electrically connected to the first transformer (21);
A first connection electrode (61B) and a second connection electrode (62B) that are electrically connected to the insulation transformer (15) and used for electrical connection with the outside;
including,
Signal transmission device.
　以上の説明は単に例示である。本開示の技術を説明する目的のために列挙された構成要素および方法（製造プロセス）以外に、より多くの考えられる組み合わせおよび置換が可能であることを当業者は認識し得る。本開示は、特許請求の範囲を含む本開示の範囲内に含まれるすべての代替、変形、および変更を包含することが意図される。 The above description is merely an example. Those skilled in the art will recognize that many more possible combinations and permutations are possible beyond those listed for the purpose of describing the techniques of the present disclosure. This disclosure is intended to cover all alternatives, variations, and modifications falling within the scope of this disclosure, including the claims.
　１０、１１０，１１２，１１４　信号伝達装置
　１０Ａ、１１４Ａ　信号伝達回路
　１１　１次側端子
　１２　２次側端子
　１３　１次側回路
　１４　２次側回路
　１５，１５Ａ，１５Ｂ　トランス
　１６Ａ，１６Ｂ　１次側信号線
　１７Ａ，１７Ｂ　２次側信号線
　１８Ａ，１８Ｂ　接続信号線
　２１　第１トランス
　２２　第２トランス
　２３　第１コイル
　２３Ａ　コイル部
　２３Ｂ　第１端部
　２３Ｃ　第２端部
　２４　第２コイル
　２４Ａ　コイル部
　２５　第３コイル
　２５Ａ　コイル部
　２５Ｂ　第１端部
　２５Ｃ　第２端部
　２６　第４コイル
　２６Ａ　コイル部
　３１　第１キャパシタ
　３２　第２キャパシタ
　３３　第１電極板
　３４　第２電極板
　３５　第３電極板
　３６　第４電極板
　４０　第１チップ
　４０Ｒ　チップ裏面
　４０Ｓ　チップ主面
　４１　第１電極パッド
　４２　第２電極パッド
　４３　第１基板
　４４　配線層
　５０　第２チップ
　５０Ｒ　チップ裏面
　５０Ｓ　チップ主面
　５１　第１電極パッド
　５２　第２電極パッド
　５３　第２基板
　５４　配線層
　６０，６０Ａ，６０Ｂ　トランスチップ
　６０Ｒ　チップ裏面
　６０Ｓ　チップ主面
　６０１　チップ側面
　６０２　チップ側面
　６０３　チップ側面
　６０４　チップ側面
　６１，６１Ａ，６１Ｂ　第１電極パッド
　６２，６２Ａ，６２Ｂ　第２電極パッド
　６３　第３基板
　６３Ｒ　基板裏面
　６３Ｓ　基板表面
　６４　絶縁体
　６４１　第１絶縁層
　６４１Ａ　絶縁膜
　６４１Ｓ　上面
　６４２　第２絶縁層
　６４２Ａ　絶縁膜
　６４３　第３絶縁層
　６４３Ａ　絶縁膜
　６５Ａ～６５Ｄ　配線
　６６Ａ～６６Ｄ　配線
　６７Ａ，６７Ｂ　配線
　６８Ａ　第１対向電極
　６８Ｂ　第２対向電極
　７１　１次側ダイパッド
　７２　２次側ダイパッド
　７３　中間ダイパッド
　８１　第１接合材
　８２　第２接合材
　８３　第３接合材
　９０　封止樹脂
　Ｄ１～Ｄ７　距離
　Ｖ１　第１電圧
　Ｖ２　第２電圧
　Ｗ１～Ｗ４　ワイヤ 10, 110, 112, 114 Signal transmission device 10A, 114A Signal transmission circuit 11 Primary side terminal 12 Secondary side terminal 13 Primary side circuit 14 Secondary side circuit 15, 15A, 15B Transformer 16A, 16B Primary side signal line 17A, 17B Secondary side signal line 18A, 18B Connection signal line 21 First transformer 22 Second transformer 23 First coil 23A Coil part 23B First end part 23C Second end part 24 Second coil 24A Coil part 25 Third coil 25A Coil part 25B First end part 25C Second end part 26 Fourth coil 26A Coil part 31 First capacitor 32 Second capacitor 33 First electrode plate 34 Second electrode plate 35 Third electrode plate 36 Fourth electrode plate 40 1 chip 40R Chip back surface 40S Chip main surface 41 First electrode pad 42 Second electrode pad 43 First substrate 44 Wiring layer 50 Second chip 50R Chip back surface 50S Chip main surface 51 First electrode pad 52 Second electrode pad 53 Second Substrate 54 Wiring layer 60, 60A, 60B Transformer chip 60R Chip back surface 60S Chip main surface 601 Chip side surface 602 Chip side surface 603 Chip side surface 604 Chip side surface 61, 61A, 61B First electrode pad 62, 62A, 62B Second electrode pad 63 3 Substrate 63R Substrate back surface 63S Substrate surface 64 Insulator 641 First insulating layer 641A Insulating film 641S Top surface 642 Second insulating layer 642A Insulating film 643 Third insulating layer 643A Insulating film 65A to 65D Wiring 66A to 66D Wiring 67A, 67B Wiring 68A First opposing electrode 68B Second opposing electrode 71 Primary die pad 72 Secondary die pad 73 Intermediate die pad 81 First bonding material 82 Second bonding material 83 Third bonding material 90 Sealing resin D1 to D7 Distance V1 First voltage V2 2nd voltage W1~W4 wire

Claims (8)

  1. 　導電性を有する基板と、
    　前記基板上に設けられ、前記基板と平行に配置される第１絶縁層を含む絶縁体と、
    　前記第１絶縁層を挟んで配置されるとともに前記第１絶縁層の厚さ方向に磁気結合可能に配置された第１コイルおよび第２コイルを含む第１トランスと、前記第１絶縁層を挟んで配置されるとともに前記第１絶縁層の厚さ方向に磁気結合可能に配置された第３コイルおよび第４コイルを含み且つ前記第１トランスと電気的に接続された第２トランスと、を有する絶縁トランスと、
    　前記絶縁トランスに電気的に接続され、外部との電気的な接続に用いられる第１接続電極および第２接続電極と、
    　前記第１接続電極と電気的に接続された第１キャパシタと、
    　前記第２接続電極と電気的に接続され、前記第１キャパシタと電気的に直列に接続された第２キャパシタと、
    　前記第１キャパシタおよび前記第２キャパシタを前記基板に電気的に接続する接続部と、
    　を含む、トランスチップ。     a conductive substrate;
    an insulator provided on the substrate and including a first insulating layer arranged parallel to the substrate;
    a first transformer including a first coil and a second coil disposed with the first insulating layer in between and magnetically coupled in the thickness direction of the first insulating layer; a second transformer including a third coil and a fourth coil arranged in a thickness direction of the first insulating layer so as to be magnetically coupled, and electrically connected to the first transformer. an isolation transformer,
    a first connection electrode and a second connection electrode that are electrically connected to the isolation transformer and used for electrical connection with the outside;
    a first capacitor electrically connected to the first connection electrode;
    a second capacitor electrically connected to the second connection electrode and electrically connected in series with the first capacitor;
    a connection part that electrically connects the first capacitor and the second capacitor to the substrate;
    Including transformer chip.
  2. 　前記第１キャパシタおよび前記第２キャパシタは、同じ容量を有するように形成されている、請求項１に記載のトランスチップ。 The transformer chip according to claim 1, wherein the first capacitor and the second capacitor are formed to have the same capacitance.
  3. 　前記第１キャパシタは、前記絶縁体内に設けられ、前記第１接続電極に電気的に接続された第１電極板と、前記絶縁体内に設けられ、前記第１絶縁層を介して前記第１電極板と対向して配置された第２電極板と、を含み、
    　前記第２キャパシタは、前記絶縁体内に設けられ、前記第２接続電極に電気的に接続された第３電極板と、前記絶縁体内に設けられ、前記第１絶縁層を介して前記第３電極板と対向して配置された第４電極板と、を含み、
    　前記接続部は、前記第２電極板および前記第４電極板を前記基板に接続する、
    　請求項１または請求項２に記載のトランスチップ。     The first capacitor includes a first electrode plate provided in the insulator and electrically connected to the first connection electrode, and a first electrode plate provided in the insulator and connected to the first electrode through the first insulating layer. a second electrode plate disposed opposite to the plate;
    The second capacitor includes a third electrode plate provided in the insulator and electrically connected to the second connection electrode, and a third electrode plate provided in the insulator and connected to the third electrode through the first insulating layer. a fourth electrode plate disposed opposite to the plate;
    the connecting portion connects the second electrode plate and the fourth electrode plate to the substrate;
    The transformer chip according to claim 1 or claim 2.
  4. 　前記第１キャパシタは、前記第１接続電極と、前記絶縁体内における前記第１絶縁層を介して前記第１接続電極と対向する位置に設けられた第１対向電極とにより構成され、
    　前記第２キャパシタは、前記第２接続電極と、前記絶縁体内における前記第１絶縁層を介して前記第２接続電極と対向する位置に設けられた第２対向電極とにより構成され、
    　前記接続部は、前記第１対向電極および前記第２対向電極を前記基板に接続する、
    　請求項１または請求項２に記載のトランスチップ。     The first capacitor includes the first connection electrode and a first opposing electrode provided in the insulator at a position facing the first connection electrode via the first insulating layer,
    The second capacitor includes the second connection electrode and a second opposing electrode provided in the insulator at a position facing the second connection electrode via the first insulating layer,
    the connecting portion connects the first counter electrode and the second counter electrode to the substrate;
    The transformer chip according to claim 1 or claim 2.
  5. 　前記第１コイルは前記第１接続電極に接続され、
    　前記第３コイルは前記第２接続電極に接続され、
    　前記第２コイルおよび前記第４コイルは互いに接続されている、
    　請求項１から請求項４のいずれか一項に記載のトランスチップ。     the first coil is connected to the first connection electrode,
    the third coil is connected to the second connection electrode,
    the second coil and the fourth coil are connected to each other,
    A transformer chip according to any one of claims 1 to 4.
  6. 　前記絶縁体は、前記第１絶縁層の上の第２絶縁層と、前記第１絶縁層の下の第３絶縁層とを含み、
    　前記第１コイルおよび前記第３コイルは前記第２絶縁層内に配置され、
    　前記第２コイルおよび前記第４コイルは前記第３絶縁層内に配置されている、
    　請求項１から請求項５のいずれか一項に記載のトランスチップ。     The insulator includes a second insulating layer above the first insulating layer and a third insulating layer below the first insulating layer,
    the first coil and the third coil are disposed within the second insulating layer;
    the second coil and the fourth coil are disposed within the third insulating layer;
    A transformer chip according to any one of claims 1 to 5.
  7. 　第１回路を含む第１チップと、
    　トランスチップと、
    　前記トランスチップを通して前記第１回路と信号の送信および受信の少なくとも一方を行うように構成された第２回路を含む第２チップと、
    　前記第１チップが実装された第１ダイパッドと、
    　前記第２チップが実装された第２ダイパッドと、
    　前記第１ダイパッドおよび前記第２ダイパッドの双方と絶縁され、前記トランスチップが実装された第３ダイパッドと、を含み、
    　前記トランスチップは、
    　導電性を有する基板と、
    　前記基板上に設けられ、前記基板と平行に配置される第１絶縁層を含む絶縁体と、
    　前記第１絶縁層を挟んで配置されるとともに前記第１絶縁層の厚さ方向に磁気結合可能に配置された第１コイルおよび第２コイルを含む第１トランスと、前記第１絶縁層を挟んで配置されるとともに前記第１絶縁層の厚さ方向に磁気結合可能に配置された第３コイルおよび第４コイルを含み且つ前記第１トランスと電気的に接続された第２トランスと、を有する絶縁トランスと、
    　前記絶縁トランスに電気的に接続され、外部との電気的な接続に用いられる第１接続電極および第２接続電極と、
    　前記第１接続電極と電気的に接続された第１キャパシタと、
    　前記第２接続電極と電気的に接続され、前記第１キャパシタと電気的に直列に接続された第２キャパシタと、
    　前記第１キャパシタおよび前記第２キャパシタを前記基板に電気的に接続する接続部と、
    　を含む、
    　信号伝達装置。     a first chip including a first circuit;
    transformer chip,
    a second chip including a second circuit configured to at least one transmit and receive signals with the first circuit through the transformer chip;
    a first die pad on which the first chip is mounted;
    a second die pad on which the second chip is mounted;
    a third die pad that is insulated from both the first die pad and the second die pad and has the transformer chip mounted thereon;
    The transformer chip is
    a conductive substrate;
    an insulator provided on the substrate and including a first insulating layer arranged parallel to the substrate;
    a first transformer including a first coil and a second coil disposed with the first insulating layer in between and magnetically coupled in the thickness direction of the first insulating layer; a second transformer including a third coil and a fourth coil arranged in a thickness direction of the first insulating layer so as to be magnetically coupled, and electrically connected to the first transformer. an isolation transformer,
    a first connection electrode and a second connection electrode that are electrically connected to the isolation transformer and used for electrical connection with the outside;
    a first capacitor electrically connected to the first connection electrode;
    a second capacitor electrically connected to the second connection electrode and electrically connected in series with the first capacitor;
    a connection part that electrically connects the first capacitor and the second capacitor to the substrate;
    including,
    Signal transmission device.
  8. 　前記トランスチップは、導電性接合材により前記第３ダイパッドに電気的に接続されている、請求項７に記載の信号伝達装置。 The signal transmission device according to claim 7, wherein the transformer chip is electrically connected to the third die pad by a conductive bonding material.
PCT/JP2023/029140 2022-08-24 2023-08-09 Transformer chip and signal transmission device WO2024043105A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022101068A (en) * 2020-12-24 2022-07-06 ローム株式会社 Gate driver
WO2022163347A1 (en) * 2021-01-29 2022-08-04 ローム株式会社 Transformer chip, and signal-transmitting device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022101068A (en) * 2020-12-24 2022-07-06 ローム株式会社 Gate driver
WO2022163347A1 (en) * 2021-01-29 2022-08-04 ローム株式会社 Transformer chip, and signal-transmitting device

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