WO2024035176A1 - Substrat de boîtier semi-conducteur et boîtier semi-conducteur le comprenant - Google Patents

Substrat de boîtier semi-conducteur et boîtier semi-conducteur le comprenant Download PDF

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WO2024035176A1
WO2024035176A1 PCT/KR2023/011868 KR2023011868W WO2024035176A1 WO 2024035176 A1 WO2024035176 A1 WO 2024035176A1 KR 2023011868 W KR2023011868 W KR 2023011868W WO 2024035176 A1 WO2024035176 A1 WO 2024035176A1
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Prior art keywords
semiconductor package
insulating layer
hole
electrode
package substrate
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PCT/KR2023/011868
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English (en)
Korean (ko)
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배진수
나용석
정헌
권순규
명세호
황정호
Original Assignee
엘지이노텍 주식회사
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Publication of WO2024035176A1 publication Critical patent/WO2024035176A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • the embodiment relates to a semiconductor package substrate and a semiconductor package including the same.
  • a typical semiconductor package has a structure in which multiple chips are arranged.
  • the size of semiconductor packages is increasing due to the recent higher specifications of products to which semiconductor packages are applied and the adoption of a large number of chips such as HBM (High Bandwidth Memory).
  • HBM High Bandwidth Memory
  • various configurations are being studied to ensure reliability, such as including interposers to connect multiple chips.
  • high performance may include conditions such as high-speed transmission of signals, integration of semiconductor packages, and high allowable current for signals that can be transmitted.
  • the pad may be a mounting pad connected to a chip or a bump pad connected to various substrates.
  • the various substrates may include additional packages such as a memory substrate, an interposer connecting a chip and a semiconductor package substrate, and a main board of an electronic device to which the semiconductor package is applied.
  • a multilayer semiconductor package substrate includes a through electrode disposed in a through hole formed in a core substrate such as a copper clad laminate (CCL).
  • CCL copper clad laminate
  • the number of stacks of semiconductor package substrates is increasing as wiring becomes more complex, and as the area increases, the thickness of the core substrate is increasing to improve strength and bending characteristics.
  • the thickness of the conventional core substrate was around 200 ⁇ m, but recently, the thickness has been increasing several times or more.
  • a drill machine is used to form a through hole in the core substrate.
  • Patent Document 1 KR 10-2011-0016266 A
  • Embodiments provide a semiconductor package substrate with a new structure and a semiconductor package including the same.
  • the embodiment provides a semiconductor package substrate capable of forming a through hole in a core substrate of 200 ⁇ m or more using a laser process, and a semiconductor package including the same.
  • the embodiment provides a semiconductor package substrate in which the difference between the maximum and minimum widths of the through hole in the vertical direction is minimized, and a semiconductor package including the same.
  • the embodiment provides a semiconductor package substrate that prevents expansion of the size of the through hole and ensures that the inner wall of the through hole has an inclination close to a right angle, and a semiconductor package including the same.
  • a semiconductor package substrate includes an insulating layer having a top and bottom surfaces; and a through electrode penetrating the upper and lower surfaces of the insulating layer, and a side surface of the through electrode includes concave portions and convex portions alternately provided along a vertical direction.
  • a semiconductor package substrate includes an insulating layer having a top and bottom surfaces; and a through hole penetrating the upper and lower surfaces of the insulating layer, wherein side walls of the through hole include concave portions and convex portions alternately provided along a vertical direction.
  • the semiconductor package substrate further includes a through electrode disposed in the through hole, and a side surface of the through electrode has a convex portion corresponding to a convex portion of a side wall of the through hole and a concave portion corresponding to a concave portion of a side wall of the through hole.
  • the semiconductor package substrate further includes an insulating member penetrating the insulating layer, and the penetrating electrode is provided to surround an outside of the insulating member.
  • a plurality of concave portions and convex portions of the through electrode are provided alternately along the vertical direction.
  • the insulating member includes a first part having a first width in the horizontal direction, and a second part having a second width different from the first width in the horizontal direction.
  • the first width is greater than the second width, the first portion horizontally overlaps the concave portion of the through electrode, and the second portion horizontally overlaps the convex portion of the through electrode.
  • the insulating layer includes a resin and reinforcing fibers disposed in the resin, wherein the reinforcing fibers include first fibers disposed in a first horizontal direction and first fibers disposed in a second horizontal direction perpendicular to the first horizontal direction. Contains 2 fibers.
  • the reinforcing fibers include a plurality of groups spaced apart from each other along the vertical direction and each having the first and second fibers.
  • the concave portion of the penetrating electrode overlaps the reinforcing fiber in a horizontal direction.
  • the thickness of the insulating layer in the vertical direction satisfies the range of 250 ⁇ m to 1200 ⁇ m.
  • the inner wall of the through hole in the insulating layer includes a plurality of first inner walls having protrusions and a second inner wall not having the protrusions.
  • the second inner wall refers to a portion of the inner wall of the through hole having a concave portion.
  • the through electrode includes a first part in contact with the first inner wall and a second part in contact with the second inner wall. At this time, the first and second through patterns have a step.
  • the first portion of the through electrode has a concave portion corresponding to a concave portion of the through hole
  • the second portion of the through electrode has a convex portion corresponding to a convex portion of the through hole.
  • each of the first and second portions of the penetrating electrode satisfies the range of 10 ⁇ m to 25 ⁇ m.
  • the thickness of the first portion of the through electrode in the horizontal direction is the same as the thickness of the second portion in the horizontal direction.
  • the first through electrode includes a first metal layer disposed on the inner wall of the first through hole of the insulating layer, and a second metal layer disposed on the first metal layer.
  • the minimum width of the area having the smallest width in the entire area in the vertical direction of the first through hole is 55% of the maximum width of the area having the largest width in the entire area in the vertical direction of the first through hole. Satisfies 95% coverage.
  • the semiconductor package substrate of the embodiment allows the formation of a through hole with a minimized difference between the maximum and minimum widths using laser processing equipment in the first insulating layer having a thickness of 250 ⁇ m or more. Through this, the embodiment makes it possible to improve the physical and electrical characteristics of the first through electrode provided on the semiconductor package substrate.
  • the first insulating layer is a core layer containing reinforcing fibers.
  • the through hole when a through hole is formed in the first insulating layer using a laser device, the through hole includes areas with different widths along the vertical direction, and the minimum width is less than 50% of the maximum width. Accordingly, in the comparative example, there was a problem of non-uniform placement of the through electrodes due to differences in plating speeds for each region in the plating process of placing the through electrodes in the through holes.
  • the laser intensity under laser processing conditions was increased to minimize the difference between the minimum and maximum widths.
  • a size expansion problem occurs in which the size of the through hole is formed larger than the target size.
  • a through hole is formed using machine drill equipment to minimize the difference between the minimum and maximum width.
  • machine drill equipment only one through hole can be formed at a time. This had the problem of lowering the production yield.
  • a through hole is formed in the first insulating layer using at least two coordinate codes (T-code).
  • T-code coordinate codes
  • a portion of a through hole is formed by irradiating a laser having a first laser energy intensity to a first mask having an opening of a first size using a first coordinate code.
  • a laser of a second laser energy intensity having an energy intensity different from the first laser energy intensity is irradiated to a second mask having an opening of a second size different from the first size using the second coordinate code to form a remaining portion of the through hole.
  • the embodiment can form a through hole with a minimized difference between the maximum and minimum widths in the first insulating layer using a laser device while preventing expansion of the size of the through hole.
  • the embodiment can solve the non-uniformity of the thickness of the first through electrode in the plating process of disposing the first through electrode in the first through hole.
  • the embodiment can improve the physical properties of the semiconductor package substrate.
  • the first through-electrode can be disposed to have a uniform thickness in the first insulating layer through improved plating characteristics.
  • the loss of the signal transmitted through the first through electrode can be minimized, voltage drop can be prevented, and the degree of freedom in wiring design can be increased by benefiting impedance matching. Furthermore, the first through hole according to this embodiment can improve the electrical characteristics of the semiconductor package substrate and the semiconductor package including the same.
  • the embodiment it is possible to form a through hole using a laser device in the first insulating layer that has a vertical thickness of 250 ⁇ m to 1200 ⁇ m and includes reinforcing fibers therein.
  • the embodiment can reduce the time required to form a through hole compared to forming a through hole using machine drill equipment. Accordingly, the embodiment can improve the production yield of semiconductor package substrates.
  • the embodiment can reduce the manufacturing cost of the semiconductor package substrate by eliminating the need to use relatively expensive machine drill equipment.
  • 1A is a cross-sectional view for explaining a semiconductor package substrate according to a first comparative example.
  • FIG. 1B is a cross-sectional view illustrating a semiconductor package substrate according to a second comparative example.
  • Figure 2a is a cross-sectional view showing a semiconductor package according to the first embodiment.
  • Figure 2b is a cross-sectional view showing a semiconductor package according to a second embodiment.
  • Figure 2c is a cross-sectional view showing a semiconductor package according to a third embodiment.
  • Figure 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.
  • Figure 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.
  • Figure 2f is a cross-sectional view showing a semiconductor package according to the sixth embodiment.
  • Figure 2g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.
  • FIG. 3A is a diagram showing a semiconductor package substrate according to the first embodiment.
  • Figure 3b is a diagram showing a semiconductor package substrate according to a second embodiment.
  • Figure 4 is a cross-sectional view for explaining the first insulating layer of the embodiment.
  • FIG. 5 is a cross-sectional view showing a first through hole provided in the first insulating layer of FIG. 4.
  • FIG. 6 is a cross-sectional view showing a first through electrode and an insulating member disposed in the through hole of FIG. 5.
  • Figure 7 is a diagram showing the layer structure of the first through electrode and the first circuit pattern layer in the first embodiment.
  • Figure 8 is a diagram showing the layer structure of the first through electrode and the first circuit pattern layer in the second embodiment.
  • FIG. 9 is an optical microscope photograph of an actual product including a first through hole, a first through electrode, and an insulating member according to an embodiment.
  • 10 to 14 are diagrams showing part of a method for manufacturing a semiconductor package substrate according to an embodiment, in process order.
  • the technical idea of the present invention is not limited to some of the described embodiments, but may be implemented in various different forms, and as long as it is within the scope of the technical idea of the present invention, one or more of the components may be optionally used between the embodiments. It can be used by combining and replacing.
  • top or bottom refers not only to cases where two components are in direct contact with each other, but also to one component. This also includes cases where another component described above is formed or placed between two components.
  • top (above) or bottom (bottom) it may include not only the upward direction but also the downward direction based on one component.
  • FIG. 1A is a cross-sectional view illustrating a semiconductor package substrate according to a first comparative example
  • FIG. 1B is a cross-sectional view illustrating a semiconductor package substrate according to a second comparative example.
  • the semiconductor package substrate Before explaining comparative examples, semiconductor package substrates are required to have higher densities as electronic devices become more functional and semiconductor devices become more integrated. Accordingly, the semiconductor package substrate has a multi-layer structure.
  • FCBGA Flexible Chip Ball Grid Array
  • FCCSP Flip Chip Chip Scale Package
  • the core layer is an insulating layer with rigidity to implement multi-layer build-up, and has a thickness above a certain level.
  • the thickness of the core layer may vary depending on the number of layers in the multi-layer build-up.
  • the semiconductor package substrate may have a thickness of 250 ⁇ m to 1200 ⁇ m in order to increase the complexity of wiring and reduce voltage drop problems and/or signal loss.
  • penetrating electrodes are formed in the core layer for electrical connection with the circuit patterns of each layer.
  • the through electrode may be provided by filling a through hole penetrating the upper and lower surfaces of the core layer with a conductive material.
  • the above-described core layer has a thickness of 250 ⁇ m to 1200 ⁇ m, and accordingly, the process of forming the through hole and/or the through electrode of the comparative example has the following problems.
  • the through hole is formed using either a laser device or a drill machine device.
  • Figure 1a shows a first comparative example of forming a through hole using a laser equipment
  • Figure 1b shows a second comparative example of forming a through hole using a drill machine equipment.
  • an insulating layer 10 to be used as a core layer is prepared.
  • the thickness (t) of the insulating layer 10 may be 250 ⁇ m to 1200 ⁇ m.
  • a through hole is formed in the insulating layer 10 using a laser device.
  • the insulating layer 10 has a thickness (t) of 250 ⁇ m to 1200 ⁇ m, it is difficult to form a through hole by performing laser processing on only one side of the insulating layer 10. Accordingly, in the first comparative example, laser processing is performed on each of the upper and lower surfaces of the insulating layer 10 to form through holes.
  • the first part of the through hole is formed on the upper surface of the insulating layer 10 to correspond to the target size that the through hole should have, and the first part of the through hole is connected to the lower surface of the insulating layer 10. forms the second part.
  • the energy intensity of the laser is set large to solve the problem of non-penetration of the insulating layer 10 described above. Accordingly, as shown in (c) of FIG. 1A, the first part 11 and the second part 12 are formed having a size larger than the target size that the through hole should have.
  • the through hole has a width (w1) larger than the target size. Accordingly, there is a problem that it is difficult to adjust the size of the through hole and the through electrode formed by filling the through hole in the first comparative example to the desired target size.
  • a laser beam is irradiated several times to a specific through hole using one coordinate code (eg, T-code).
  • one coordinate code eg, T-code
  • the laser process conditions may mean mask size, pulse width, energy intensity, collimation, and number of steps.
  • the minimum width in the entire area in the vertical direction of the through hole is less than 50% of the maximum width. Additionally, as the difference between the minimum and maximum widths increases, there is a problem in that the plating characteristics in the plating process for forming the through electrode deteriorate.
  • the second comparative example is a through hole 20 using drill machine equipment such as a CNC (computer numerical control) drill rather than a laser. forms.
  • the inclination of the inner wall of the through hole formed in the insulating layer 10 is substantially close to vertical.
  • this through hole 20 does not include a plating bridge, unlike the hourglass-shaped through hole of FIG. 1A, there is a problem in that it is difficult to uniformly fill the through hole 20 with a conductive material. .
  • drill machine equipment is more expensive than laser equipment. Therefore, when forming a through hole using drill machine equipment, there is a problem that a large cost is required to build infrastructure or the manufacturing cost of the semiconductor package substrate increases.
  • the through hole 20 when forming the through hole 20 using drill machine equipment, there is a problem that the productivity of the semiconductor package substrate is reduced. Specifically, when using drill machine equipment, exemplarily, only one through hole can be formed at a time. Accordingly, the manufacturing process time for a semiconductor package substrate can increase several times compared to using laser equipment, and there is a problem of decreased productivity and yield.
  • a plurality of through holes can be formed at once using the opening included in the mask, and a uniform through electrode can be formed in each of the plurality of through holes. You can. Additionally, compared to using drill machine equipment, the manufacturing process time for semiconductor package substrates can be significantly shortened, and productivity and yield can be greatly improved.
  • a through electrode with improved electrical and physical reliability can be formed inside a through hole formed in a core layer having a thickness of 250 ⁇ m to 1200 ⁇ m.
  • the embodiment provides a semiconductor package substrate including a through electrode having a new structure and a package substrate including the same.
  • Electronic devices include smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, and computers. It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. . However, it is not limited to this, and of course, it can be any other electronic device that processes data.
  • the electronic device includes a main board (not shown).
  • the main board may be physically and/or electrically connected to various components. Additionally, the main board may be connected to the semiconductor package substrate of the embodiment.
  • Various semiconductor devices can be mounted on a semiconductor package substrate.
  • Semiconductor devices may include active devices and/or passive devices.
  • the active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of active devices, such as transistors, are integrated into a single chip.
  • Semiconductor devices may be logic chips, memory chips, etc.
  • the logic chip may be a central processor (CPU), a graphics processor (GPU), or the like.
  • the logic chip is an application processor (AP) chip that includes at least one of a central processor (CPU), graphics processor (GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or an analog-digital chip. It could be a converter, an application-specific IC (ASIC), or a set of chips containing a specific combination of the ones listed so far.
  • ASIC application-specific IC
  • the memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.
  • volatile memory eg, DRAM
  • non-volatile memory eg, ROM
  • flash memory e.g., NAND
  • the product groups of semiconductor package substrates to which the semiconductor package of the embodiment is applied include CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), and POP (Package On Package). ) and SIP (System In Package), but is not limited thereto.
  • the semiconductor package of the embodiment may have various package structures including a semiconductor package substrate that will be described later. Additionally, the semiconductor package substrate in one embodiment may be referred to as a first semiconductor package substrate described below, and the semiconductor package substrate in another embodiment may be referred to as a second semiconductor package substrate described below.
  • FIG. 2A is a cross-sectional view showing a semiconductor package according to a first embodiment
  • FIG. 2B is a cross-sectional view showing a semiconductor package according to a second embodiment
  • FIG. 2C is a cross-sectional view showing a semiconductor package according to a third embodiment
  • FIG. 2D is a cross-sectional view showing a semiconductor package according to the fourth embodiment
  • FIG. 2E is a cross-sectional view showing a semiconductor package according to the fifth embodiment
  • FIG. 2F is a cross-sectional view showing a semiconductor package according to the sixth embodiment
  • FIG. 2G is a cross-sectional view showing a semiconductor package according to the sixth embodiment.
  • This is a cross-sectional view showing a semiconductor package according to Example 7.
  • the semiconductor package of the first embodiment may include a first semiconductor package substrate 100, a second semiconductor package substrate 200, and a semiconductor device 300.
  • the first semiconductor package substrate 100 refers to a package substrate.
  • the first semiconductor package substrate 100 may provide a space where at least one external substrate is coupled.
  • the external substrate may refer to the second semiconductor package substrate 200 coupled to the first semiconductor package substrate 100.
  • the external substrate may refer to a main board included in an electronic device coupled to the lower part of the first semiconductor package substrate 100.
  • the first semiconductor package substrate 100 may provide a space where at least one semiconductor device is mounted in addition to a space where the second semiconductor package substrate 200 is mounted.
  • the first semiconductor package substrate 100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a penetrating portion penetrating the at least one insulating layer.
  • a second semiconductor package substrate 200 is disposed on the first semiconductor package substrate 100.
  • the second semiconductor package substrate 200 may be an interposer. Additionally, the second semiconductor package substrate 200 may provide a space in which at least one semiconductor device is mounted. The second semiconductor package substrate 200 may be connected to at least one semiconductor device 300. For example, the second semiconductor package substrate 200 may provide a space in which the first semiconductor device 310 and/or the second semiconductor device 320 are mounted. The second semiconductor package substrate 200 electrically connects the first semiconductor device 310 and the second semiconductor device 320, and connects the first and second semiconductor devices 310 and 320 to the first semiconductor package substrate ( 100) can be electrically connected. That is, the second semiconductor package substrate 200 can function as a horizontal connection between a plurality of semiconductor devices and a vertical connection function between the semiconductor devices and the package substrate. In addition, in order to improve stress and bending problems that occur as the number of insulating layers increases due to multilayer build-up, the semiconductor package substrate can be divided into a first semiconductor package substrate 100 and a second semiconductor package substrate 200. there is.
  • FIG. 2A two semiconductor devices 310 and 320 are shown disposed on the second semiconductor package substrate 200, but the present invention is not limited thereto.
  • one semiconductor device may be disposed on the second semiconductor package substrate 200, and alternatively, three or more semiconductor devices may be disposed on the second semiconductor package substrate 200.
  • the second semiconductor package substrate 200 may be an active interposer that functions as a semiconductor device.
  • the package of the embodiment may have a plurality of logic chips mounted vertically on the first semiconductor package substrate 100. And among the logic chips, the first logic chip corresponding to the active interposer can function as the corresponding logic chip and perform a signal transmission function between the second logic chip disposed on top of the logic chip and the first semiconductor package substrate 100. there is.
  • the second semiconductor package substrate 200 may be a passive interposer.
  • the second semiconductor package substrate 200 may function as a signal relay between the semiconductor device 300 and the first semiconductor package substrate 100.
  • the number of terminals of the semiconductor device 300 is gradually increasing due to 5G, Internet of Things (IOT), increased image quality, increased communication speed, etc. That is, the number of terminals provided in the semiconductor device 300 increases, and as a result, the width of the terminal or the gap between a plurality of terminals is reduced.
  • the first semiconductor package substrate 100 is connected to the main board of the electronic device.
  • the second semiconductor package substrate 200 is disposed on the first semiconductor package substrate 100 and the semiconductor device 300. Additionally, the second semiconductor package substrate 200 may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device 300 .
  • the semiconductor package of the first embodiment may include a connection part.
  • the semiconductor package includes a first connection portion 410 disposed between the first semiconductor package substrate 100 and the second semiconductor package substrate 200.
  • the first connection portion 410 connects the second semiconductor package substrate 200 to the first semiconductor package substrate 100 and electrically connects them.
  • the semiconductor package may further include a second connection portion 420 disposed between the second semiconductor package substrate 200 and the semiconductor device 300.
  • the second connection portion 420 may couple the semiconductor devices 300 to the second semiconductor package substrate 200 and electrically connect them.
  • the semiconductor package includes a third connection portion 430 disposed on the lower surface of the first semiconductor package substrate 100.
  • the third connection portion 430 may couple the first semiconductor package substrate 100 to the main board and electrically connect them.
  • the first connection part 410, the second connection part 420, and the third connection part 430 may mean at least one bonding method among wire bonding, solder bonding, and direct bonding between metals. That is, because the first connection part 410, the second connection part 420, and the third connection part 430 have the function of electrically connecting a plurality of components, when direct bonding between metals is used, the semiconductor package is made using solder or wire. It can be understood as a part that is electrically connected, rather than as a part.
  • the wire bonding method may mean electrically connecting a plurality of components using conductors such as gold (Au). Additionally, the solder bonding method can electrically connect a plurality of components using a material containing at least one of Sn, Ag, and Cu.
  • the direct bonding method between metals may mean recrystallization by applying heat and pressure between a plurality of components without the absence of solder, wire, conductive adhesive, etc., thereby directly bonding the plurality of components. .
  • the direct bonding method between metals may refer to a bonding method using the second connection portion 420. In this case, the second connection portion 420 may refer to a metal layer formed between a plurality of components through recrystallization.
  • the first connection part 410, the second connection part 420, and the third connection part 430 may be connected to a plurality of components using a TC (Thermal Compression) bonding method.
  • TC bonding may refer to a method of bonding a plurality of components by applying heat and pressure to the first connection part 410, the second connection part 420, and the third connection part 430.
  • the electrode on which the first connection part 410, the second connection part 420, and the third connection part 430 are disposed has a protrusion.
  • the protrusion may protrude outward from the first semiconductor package substrate 100 or the second semiconductor package substrate 200 .
  • the protrusion may be referred to as a bump.
  • the protrusion may also be called a post.
  • the protrusion may also be called a pillar.
  • the protrusion may refer to an electrode of the second semiconductor package substrate 200 on which the second connection portion 420 for coupling to the semiconductor device 300 is disposed. That is, as the pitch of the terminals of the semiconductor device 300 becomes finer, a short circuit may occur in the second connection portions 420 respectively connected to the terminals of the semiconductor device 300.
  • the electrode of the second semiconductor package substrate 200 on which the second connection part 420 is disposed includes a protrusion. The protrusion may prevent diffusion of the second connection portion 420 and the matching between the electrode of the second semiconductor package substrate 200 and the terminal of the semiconductor device 300.
  • the semiconductor package of the second embodiment includes a connecting member 210 that horizontally connects a plurality of semiconductor devices disposed on the second semiconductor package substrate 200 to the second semiconductor package substrate 200. ) differs from the semiconductor package of the first embodiment in that it is arranged.
  • the connection member 210 may be referred to as a bridge board.
  • connecting member 210 may be a silicon bridge. That is, the connection member 210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.
  • the connecting member 210 may be an organic bridge.
  • the connecting member 210 may include an organic material.
  • the connection member 210 may include an organic substrate containing an organic material instead of a silicon substrate and a redistribution layer disposed on the organic substrate.
  • connection member 210 may be embedded in the second semiconductor package substrate 200, but is not limited thereto.
  • the connecting member 210 may be disposed on the second semiconductor package substrate 200 to have a protruding structure.
  • the second semiconductor package substrate 200 may include a cavity, and the connecting member 210 may be disposed within the cavity of the second semiconductor package substrate 200.
  • the semiconductor package of the third embodiment includes a second semiconductor package substrate 200 and a semiconductor device 300. At this time, the semiconductor package of the third embodiment has a structure in which the first semiconductor package substrate 100 is removed compared to the semiconductor package of the second embodiment.
  • the second semiconductor package substrate 200 of the third embodiment can function as an interposer and as a package substrate.
  • the first connection portion 410 disposed on the lower surface of the second semiconductor package substrate 200 may couple the second semiconductor package substrate 200 to the main board of the electronic device.
  • the semiconductor package of the fourth embodiment includes a first semiconductor package substrate 100 and a semiconductor device 300.
  • the semiconductor package of the fourth embodiment has a structure in which the second semiconductor package substrate 200 is removed compared to the semiconductor package of the second embodiment.
  • the first semiconductor package substrate 100 of the fourth embodiment can function as a package substrate and an interposer that connects the semiconductor device 300 and the main board.
  • the first semiconductor package substrate 100 may include a connecting member 110 for connecting a plurality of semiconductor devices.
  • the connection member 110 may be a silicon bridge or an organic bridge that connects a plurality of semiconductor devices.
  • the semiconductor package of the fifth embodiment further includes a third semiconductor element 330 compared to the semiconductor package of the fourth embodiment.
  • a fourth connection portion 440 is disposed on the lower surface of the first semiconductor package substrate 100.
  • a third semiconductor element 330 may be disposed in the fourth connection part 400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively.
  • the third semiconductor device 330 may have a structure disposed on the lower surface of the second semiconductor package substrate 200 in the semiconductor package of FIG. 2C.
  • the semiconductor package of the sixth embodiment includes a first semiconductor package substrate 100.
  • a first semiconductor device 310 may be disposed on the first semiconductor package substrate 100.
  • a first connection portion 410 is disposed between the first semiconductor package substrate 100 and the first semiconductor device 310.
  • the first semiconductor package substrate 100 includes a conductive coupling portion 450.
  • the conductive coupling portion 450 may protrude further from the first semiconductor package substrate 100 toward the second semiconductor device 320 .
  • the conductive coupling portion 450 may be referred to as a bump or, alternatively, may be referred to as a post.
  • the conductive coupling portion 450 may be disposed to have a protruding structure on the electrode disposed on the uppermost side of the first semiconductor package substrate 100 .
  • the second semiconductor device 320 is disposed on the conductive coupling portion 450 of the first semiconductor package substrate 100. At this time, the second semiconductor device 320 may be connected to the first semiconductor package substrate 100 through the conductive coupling portion 450. Additionally, a second connection portion 420 may be disposed on the first semiconductor device 310 and the second semiconductor device 320.
  • the second semiconductor device 320 may be electrically connected to the first semiconductor device 310 through the second connection portion 420.
  • the second semiconductor device 320 is connected to the first semiconductor package substrate 100 through the conductive coupling portion 450 and is also connected to the first semiconductor device 310 through the second connection portion 420.
  • the second semiconductor device 320 can receive a power signal through the conductive coupling portion 450. Additionally, the second semiconductor device 320 may exchange communication signals with the first semiconductor device 310 through the second connection unit 420.
  • the semiconductor package of the sixth embodiment provides a power signal to the second semiconductor device 320 through the conductive coupling portion 450, thereby providing sufficient power to drive the second semiconductor device 320. Accordingly, the embodiment can improve the driving characteristics of the second semiconductor device 320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 320. Furthermore, the embodiment allows the power signal and communication signal of the second semiconductor device 320 to be provided through different paths through the conductive coupling portion 450 and the second connection portion 420. Through this, the embodiment can solve the problem of loss of communication signals caused by power signals. For example, embodiments may minimize mutual interference between power signals and communication signals.
  • the second semiconductor device 320 in the sixth embodiment may have a POP (Package On Package) structure and be disposed on the first semiconductor package substrate 100.
  • the second semiconductor device 320 may be a memory package including a memory chip.
  • the memory package may be coupled to the conductive coupling portion 450.
  • the memory package may not be connected to the first semiconductor device 310.
  • the second connection unit 420 may be omitted.
  • the semiconductor package in the sixth embodiment may include a molding member 1460.
  • the molding member 1460 may be disposed between the first substrate 1100 and the second semiconductor device 1320.
  • the molding member 1460 may mold the first connection part 1410, the second connection part 1420, the first semiconductor device 1310, and the conductive coupling part 1450.
  • the semiconductor package of the seventh embodiment includes a first semiconductor package substrate 100, a first connection part 410, a first connection part 410, a semiconductor device 300, and a third connection part 430. do.
  • the semiconductor package of the seventh embodiment differs from the semiconductor package of the fourth embodiment in that the connecting member 110 is removed and the first semiconductor package substrate 100 includes a plurality of substrate layers.
  • the first semiconductor package substrate 100 includes a plurality of substrate layers.
  • the first semiconductor package substrate 100 may include a first substrate layer 100A corresponding to the package substrate and a second substrate layer 100B corresponding to the redistribution layer of the connection member.
  • the first semiconductor package substrate 100 arranges the second substrate layer 100B corresponding to the redistribution layer on the first substrate layer 100A.
  • the semiconductor package of the seventh embodiment includes a semiconductor package substrate including a first substrate layer 100A and a second substrate layer 100B formed integrally.
  • the material of the insulating layer of the second substrate layer 100B may be different from the material of the insulating layer of the first substrate layer 100A.
  • the material of the insulating layer of the second substrate layer 100B may include a photocurable material.
  • the second substrate layer 100B may be a photo imageable dielectric (PID).
  • PID photo imageable dielectric
  • the electrode can be miniaturized.
  • the seventh embodiment sequentially stacks an insulating layer of a photo-curable material on the first substrate layer 100A and forms a micronized electrode on the insulating layer of a photo-curable material to form a second substrate layer 100B.
  • the second substrate 100B may be a redistribution layer including miniaturized electrodes.
  • the semiconductor package substrate described below may refer to any one of a plurality of semiconductor package substrates included in a previous semiconductor package.
  • the semiconductor package substrate described below may refer to the first semiconductor package substrate 100 and/or the second semiconductor package substrate 200 shown in any one of FIGS. 2A to 2G. there is.
  • FIG. 3A is a diagram showing a semiconductor package substrate according to a first embodiment
  • FIG. 3B is a diagram showing a semiconductor package substrate according to a second embodiment.
  • FIG. 3A a semiconductor package substrate according to an embodiment will be briefly described with reference to FIG. 3A, and some configurations different from FIG. 3A will be described with reference to FIG. 3B.
  • the semiconductor package substrate 500 of the embodiment includes an insulating layer 510.
  • the insulating layer 510 of the embodiment may have a multilayer structure.
  • the insulating layer 510 of the semiconductor package substrate of the embodiment may include a first insulating layer 511, a second insulating layer 512, and a third insulating layer 513.
  • the second insulating layer 512 and the third insulating layer 513 are shown as one layer, but the present invention is not limited to this and may be a configuration in which a plurality of insulating layers are stacked.
  • the first insulating layer 511 may include an insulating material different from the second insulating layer 512 and the third insulating layer 513.
  • the first insulating layer 511 may include an insulating material including reinforcing fibers and may be a core layer.
  • the first insulating layer 511 may include prepreg.
  • the first insulating layer 511 can improve bending characteristics by increasing the physical strength of the semiconductor package substrate.
  • the first insulating layer 511 of the embodiment may have a structure in which a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, is impregnated with an epoxy resin or the like.
  • the prepreg constituting the first insulating layer 511 of the embodiment may include a fiber layer in the form of a fabric sheet woven with carbon fiber thread.
  • the first insulating layer 511 may include a resin and reinforcing fibers disposed within the resin.
  • the resin may be an epoxy resin, but is not limited thereto.
  • the resin is not particularly limited to epoxy resin, and for example, it may contain one or more epoxy groups in the molecule, alternatively, it may contain two or more epoxy groups, and alternatively, it may contain four or more epoxy groups.
  • the resin constituting the first insulating layer 511 may contain a naphthalene group, for example, may be an aromatic amine type, but is not limited thereto.
  • the resins include bisphenol A-type epoxy resin, bisphenol F-type epoxy resin, bisphenol S-type epoxy resin, phenol novolak-type epoxy resin, alkylphenol novolak-type epoxy resin, biphenyl-type epoxy resin, and aralkyl-type epoxy resin. , dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of condensate of phenols and aromatic aldehyde having a phenolic hydroxyl group, biphenylaralkyl type epoxy resin, fluorene type epoxy resin.
  • the reinforcing fiber may be glass fiber, carbon fiber, aramid fiber (e.g., aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material. there is. Reinforcing fibers may be arranged within the resin in a form that intersects each other in a planar direction.
  • glass fiber for example, glass fiber, carbon fiber, aramid fiber (for example, aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material may be used.
  • aramid fiber for example, aramid-based organic material
  • nylon for example, silica-based inorganic material
  • titania-based inorganic material may be used.
  • the first insulating layer 511 may be provided with at least two layers of reinforcing fibers. Through this, the embodiment can further improve the rigidity of the substrate 500.
  • the vertical thickness of the first insulating layer 511 may be greater than the vertical thickness of at least one of the second insulating layer 512 and the third insulating layer 513.
  • the vertical thickness of the first insulating layer 511 is 3 times or more, 4 times or more, or 5 times or more than the vertical thickness of the second insulating layer 512 and the third insulating layer 513. , may be 7 times or more or 10 times or more.
  • the number of insulating layers of a semiconductor package substrate may be 10 or more layers, 12 or more layers, 16 or more layers, or 20 or more layers.
  • the second insulating layer 512 and the third insulating layer 513 are each stacked as a plurality of layers as shown, bending of the semiconductor package substrate may occur due to the stress of each insulating layer.
  • the semiconductor package substrate is bent, it may be difficult to form the through electrode included in the semiconductor package substrate at an accurate position.
  • problems such as the position of the semiconductor device being distorted during the process of mounting the semiconductor device on the semiconductor package substrate may occur.
  • the vertical thickness of the first insulating layer 511 may be 250 ⁇ m or more. Accordingly, in order to increase the physical rigidity of the semiconductor package substrate and improve the bending characteristics of the semiconductor package substrate during the packaging process, the first insulating layer 511 may have a vertical thickness of 250 ⁇ m or more. In addition, when the thickness of the first insulating layer 511 becomes too thick, the process of forming a through hole in the first insulating layer 511 becomes difficult, and electrical characteristics such as signals and/or power applied to the semiconductor device decrease. may deteriorate. Additionally, it may become difficult to slim the semiconductor package, which may lead to difficulties in providing electronic devices with a small volume. Therefore, it is appropriate that the vertical thickness of the first insulating layer 511 is 1200 ⁇ m or less.
  • the second insulating layer 512 and the third insulating layer 513 may include an insulating material different from the first insulating layer 511.
  • the second insulating layer 512 and the third insulating layer 513 may not include reinforcing fibers, but are not limited thereto.
  • the second insulating layer 512 and the third insulating layer 513 are made of ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. It can include either one.
  • the second insulating layer 512 and the third insulating layer 513 may include reinforcing fibers, and the reinforcing fibers may be glass fibers and may include a GCP (Glass Core Primer) material, but are limited thereto. It doesn't work.
  • GCP Glass Core Primer
  • the second insulating layer 512 and the third insulating layer 513 may use a CCL (Copper Clad Laminate) type insulating layer, but are not limited thereto.
  • CCL Copper Clad Laminate
  • the second insulating layer 512 and the third insulating layer 513 may have a vertical thickness ranging from 10 ⁇ m to 50 ⁇ m. If the vertical thickness of the second insulating layer 512 or the third insulating layer 513 is less than 10 ⁇ m, the bending characteristics of the semiconductor package substrate 500 may deteriorate. In addition, if the vertical thickness of the second insulating layer 512 or the third insulating layer 513 is less than 10 ⁇ m, the circuit pattern layer included in the semiconductor package substrate 500 may not be stably protected or the insulating properties may be poor. may deteriorate, thereby reducing electrical reliability.
  • the vertical thickness of the second insulating layer 512 or the third insulating layer 513 exceeds 50 ⁇ m, the overall thickness of the semiconductor package substrate 500 increases, and thus the thickness of the semiconductor package increases. can do. Additionally, if the thickness of the second insulating layer 512 or the third insulating layer 513 exceeds 50 ⁇ m, it may be difficult to miniaturize the circuit pattern layer of the semiconductor package substrate 500.
  • the thickness in the vertical direction may refer to the length from the top to the bottom of the semiconductor package substrate 500 or from the bottom to the top.
  • the upper surface may mean the highest position in each component along the vertical direction
  • the lower surface may mean the lowest position in each component along the vertical direction. And their positions can be referred to as opposites to each other.
  • the second insulating layer 512 and the third insulating layer 513 are each shown as consisting of one layer, but this is not limited to this.
  • the semiconductor package substrate 500 of the embodiment may have an 11-layer structure based on the number of insulating layers.
  • the second insulating layer 512 and the third insulating layer 513 may each be composed of five layers.
  • the semiconductor package substrate 500 of the embodiment may have a 17-layer structure based on the number of insulating layers.
  • each of the second insulating layer 512 and the third insulating layer 513 may be composed of 8 layers.
  • the semiconductor package substrate 500 may include a circuit pattern layer disposed on the insulating layer 510 .
  • the semiconductor package substrate 500 may include a first circuit pattern layer 521 disposed on the top of the first insulating layer 511.
  • the semiconductor package substrate 500 may include a second circuit pattern layer 522 disposed on the lower surface of the first insulating layer 511.
  • the semiconductor package substrate 500 may include a third circuit pattern layer 523 disposed on the second insulating layer 512 .
  • the semiconductor package substrate 500 may include a fourth circuit pattern layer 524 disposed on the lower surface of the third insulating layer 513.
  • the third circuit pattern layer 523 disposed on the uppermost side among the circuit pattern layers may include an electrode pattern on which a semiconductor device is disposed.
  • the semiconductor package substrate may be disposed on the electrode pattern of the third circuit pattern layer 523 and include a protrusion 590 that protrudes toward the semiconductor device.
  • the protrusion 590 may be referred to as a bump.
  • the protrusion 590 may also be referred to as a post.
  • the protrusion 590 may also be referred to as a pillar.
  • TC Thermal Compression bonding
  • the protrusion 590 may function to improve alignment between the electrode pattern and the terminal of the semiconductor device and to prevent diffusion of the conductive adhesive.
  • the volume of the conductive adhesive disposed on each of the plurality of terminals can be reduced, thereby preventing electrical short-circuit problems due to the fine pitch of the terminals.
  • solder may be used as the conductive adhesive, but is not limited thereto.
  • the circuit pattern layers 521, 522, 523, and 524 are selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It may contain at least one metal material.
  • the circuit pattern layers 521, 522, 523, and 524 are made of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (which have excellent bonding properties). It may include a paste or solder paste containing at least one metal material selected from Zn).
  • the circuit pattern layers 521, 522, 523, and 524 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.
  • the circuit pattern layers 521, 522, 523, and 524 may have a thickness ranging from 10 ⁇ m to 25 ⁇ m.
  • the thickness of the circuit pattern layers 521, 522, 523, and 524 may refer to the thickness in the vertical direction.
  • the thickness of the circuit pattern layers 521, 522, 523, and 524 is less than 10 ⁇ m, the resistance of the circuit pattern layers 521, 522, 523, and 524 may increase, and the allowable current of the transmittable signal may decrease. there is. Additionally, if the thickness of the circuit pattern layers 521, 522, 523, and 524 exceeds 25 ⁇ m, it may be difficult to miniaturize the circuit pattern layers 521, 522, 523, and 524. If the thickness of the circuit pattern layers 521, 522, 523, and 524 exceeds 25 ⁇ m, the thickness of the insulating layer 510 must increase correspondingly, and the insulating function and/or protection of the insulating layer as described above. In order to function, the thickness of each insulating layer must be thick. Accordingly, the thickness of the semiconductor package substrate and the semiconductor package may increase, and it may become difficult to alleviate the bending of the semiconductor package substrate.
  • the circuit pattern layers 521, 522, 523, and 524 may include a pad connected to a through electrode of the semiconductor package substrate 500 and at least one electrode pattern connected to an external substrate or semiconductor device. Additionally, the circuit pattern layers 521, 522, 523, and 524 may include traces of signal transmission lines connected to pads or electrode patterns.
  • circuit pattern layers 521, 522, 523, and 524 are manufactured using typical semiconductor package substrate manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP ( This is possible using the Semi Additive Process (Semi Additive Process) method, and detailed explanations are omitted here.
  • the semiconductor package substrate 500 may include a first through electrode 530 that penetrates the first insulating layer 511 .
  • the first insulating layer 511 may include a first through hole penetrating the upper and lower surfaces.
  • the first through electrode 530 may be provided to fill at least a portion of the first through hole of the first insulating layer 511.
  • the semiconductor package substrate 500 has an insulating member 540 that fills the remaining portion of the first through hole of the first insulating layer 511, and when the first through electrode 530 does not entirely fill the first through hole, 1 It may be arranged to improve the flatness of the circuit pattern layer 521, and the first through electrode 530 may be arranged to be located between the insulating member 540 and the first insulating layer 511.
  • the insulating member 540 may be referred to as a hole plugging layer.
  • the insulating member 540 may include an insulating material.
  • the insulating member 540 may be a paste made of insulating ink material.
  • the insulating member 540 may be plugging ink.
  • the embodiment is not limited to this.
  • the insulating member 540 may include a conductive material.
  • the insulating member 540 may include a conductive paste containing conductive metal powder.
  • the semiconductor package substrate 500 may include a second through electrode 550 that penetrates the second insulating layer 512 .
  • the second insulating layer 512 may include a second through hole penetrating the upper and lower surfaces.
  • the second through electrode 550 may be provided to entirely fill the second through hole of the second insulating layer 512.
  • the semiconductor package substrate 500 may include a third through electrode 560 that penetrates the third insulating layer 513.
  • the third insulating layer 513 may include a third through hole penetrating the upper and lower surfaces.
  • the third through electrode 560 may be provided to entirely fill the third through hole of the third insulating layer 513.
  • the first through electrode 530, second through electrode 550, and third through electrode 560 may have different shapes.
  • the first through hole, the second through hole, and the third through hole may have different shapes.
  • the inclination of the first through electrode 530 surrounding the insulating member 540 disposed in the first through hole, the inclination of the second through electrode 550, and the inclination of the third through electrode 560 are each other.
  • the slope of the side of the first through electrode 530, the side of the second through electrode 550, and the side of the third through electrode 560 may be different from each other.
  • the vertical cross-sectional shape of the first through electrode 530, the vertical cross-sectional shape of the side of the second through electrode 550, and the vertical cross-sectional shape of the third through electrode 560 may be different from each other.
  • the inner wall of the first through hole may include a plurality of concave portions and convex portions, and the concave portions and convex portions may be provided in a structure in which the concave portions and convex portions are alternately stacked along the vertical direction.
  • the convex portion refers to an area that protrudes and/or is convex toward the horizontal center of the first through hole
  • the concave portion refers to a concave area in the opposite direction.
  • the second through hole may have a shape whose width decreases from the top to the bottom. Additionally, the second through hole may be arranged not to include a plurality of concave portions and convex portions, unlike the first through hole.
  • the third through hole may have a shape whose width increases from the top to the bottom. Additionally, the third through hole may be arranged not to include a plurality of concave portions and convex portions. Additionally, the third through hole may have a symmetrical shape with the second through hole with respect to the first insulating layer 511, but is not limited thereto.
  • the vertical thickness of the first through electrode 530, the depth of the first through hole, and the vertical thickness of the insulating member 540 may correspond to the thickness of the first insulating layer 511. Accordingly, the vertical thickness of the first through electrode 530, the depth of the first through hole, and the vertical thickness of the insulating member 540 may be 250 ⁇ m to 1200 ⁇ m.
  • a first through hole is formed in the first insulating layer 511 using a laser device, while minimizing the difference between the maximum and minimum widths of the first through hole in the vertical direction.
  • the vertical direction refers to the thickness direction from the top to the bottom of the first insulating layer 511.
  • a through hole is formed in which the difference between the maximum and minimum widths of the first insulating layer 511 is minimized using a laser device rather than a drill machine device.
  • the embodiment uses a plurality of coordinate codes (eg, T-code) to form the first through hole in the first insulating layer 511. That is, when using a laser device, in the comparative example, a through hole was formed in the core layer corresponding to the first insulating layer 511 using only one coordinate code. Accordingly, in the process of forming a through hole, it is difficult to change the laser process conditions during the process. Therefore, when a through hole is formed by a laser device using only one coordinate code, the through hole has an hourglass shape in which the width gradually decreases from the top and/or bottom to the center, and thus the minimum width is equal to the maximum width. had less than 50%.
  • T-code coordinate codes
  • the first through hole is formed in the first insulating layer 511 using at least two coordinate codes.
  • a portion of the first through hole is formed in the first insulating layer 511 using the first coordinate code. Thereafter, in the embodiment, the remaining part of the first through hole connected to the part of the first through hole is formed in the first insulating layer 511 using the second coordinate code. Through this, the embodiment can finally form a first through hole penetrating the first insulating layer 511.
  • the embodiment uses two coordinate codes, unlike the comparative example, it is possible to change the laser process conditions during the forming process of the first through hole.
  • the embodiment it is possible to form a first through hole with a minimized difference between the maximum and minimum widths in the first insulating layer 511 corresponding to the core layer using a laser device.
  • the embodiment includes a first process of forming a portion of the first through hole in the first insulating layer 511 using a first coordinate code, and a first process of forming a portion of the first through hole in the first insulating layer 511 using the second coordinate code.
  • a second process is performed to form the remaining part connected to part of the through hole.
  • a first mask having an opening of the first size is used to form a part of the first through hole.
  • the first size may correspond to the target size that the first through hole should have.
  • the embodiment forms a portion of the first through hole corresponding to the target size on each of the upper and lower surfaces of the first insulating layer 511 using the first mask.
  • the embodiment proceeds with a second process using a second coordinate code after a portion of the first through hole is formed.
  • a second mask having an opening of a second size different from the first size is used to form the remaining part of the first through hole.
  • the second size is smaller than the first size.
  • the energy intensity of the laser is increased in the second process of forming the remaining part of the first through hole using the second mask.
  • the embodiment irradiates the first insulating layer 511 with a laser having a first energy intensity.
  • the embodiment irradiates the first insulating layer 511 with a laser having a second energy intensity greater than the first energy intensity.
  • the size of the opening provided in the second mask is smaller than the target size of the first through hole. That is, in the embodiment, a laser with a relatively low energy intensity is irradiated through the opening of the first mask having a first size, and a laser with a relatively large energy intensity is irradiated through the opening of the second mask with a second size smaller than the first size.
  • the embodiment can minimize the difference between the maximum width and the minimum width in the entire vertical area of the first through hole.
  • the size of the opening of the second mask used when irradiating a laser with a relatively high energy intensity is smaller than the target size, and accordingly, the embodiment can prevent the size of the first through hole from expanding.
  • the semiconductor package substrate 500 of the embodiment includes a protective layer.
  • the protective layer may also be referred to as an insulating layer or a resist layer.
  • the protective layer refers to the insulating layer of the outermost layer of the semiconductor package substrate.
  • the protective layer functions to protect the surface of the outermost layer of the semiconductor package substrate 500 and prevents short circuits between adjacent conductive adhesives. Accordingly, the protective layer can also be functionally referred to as a ‘protective layer.’ For example, when a conductive adhesive is used as solder, the protective layer may be referred to as a solder resist.
  • the protective layer includes a first protective layer 570 disposed on the upper surface of the second insulating layer 512.
  • the first protective layer 570 includes at least one first opening 571 that vertically overlaps a portion of the third circuit pattern layer 523.
  • the first opening 571 may be provided to correspond to an area where a conductive adhesive such as a connection portion is to be placed.
  • the protective layer includes a second protective layer 580 disposed on the lower surface of the third insulating layer 53.
  • the second protective layer 580 includes at least one second opening 581 that vertically overlaps the fourth circuit pattern layer 524.
  • the second opening 581 may be provided to correspond to an area where a conductive adhesive such as a connection portion is to be placed.
  • the first protective layer 570 and the second protective layer 580 may include an organic polymer material.
  • the first protective layer 570 and the second protective layer 580 may be solder protective layers.
  • the first protective layer 570 and the second protective layer 580 may include an epoxy acrylate-based resin.
  • the first protective layer 570 and the second protective layer 580 may include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc.
  • the embodiment is not limited to this.
  • the first protective layer 570 and the second protective layer 580 may include any one of a photo solder protective layer, a coverlay, and a polymer material.
  • the first protective layer 570 and the second protective layer 580 may have a thickness of 1 ⁇ m to 20 ⁇ m. At this time, when the thickness of the first protective layer 570 and the second protective layer 580 exceeds 20 ⁇ m, the overall thickness of the semiconductor package substrate and the overall thickness of the semiconductor package may increase, and as the stress increases, The warpage of the semiconductor package substrate may increase.
  • the circuit pattern layer may not be stably protected. If the thickness of the first protective layer 570 and the second protective layer 580 is less than 1 ⁇ m, the electrical reliability of the semiconductor package substrate and the semiconductor package may deteriorate.
  • the first through hole, the first through electrode, and the insulating member formed in the first insulating layer 511 according to the embodiment will be described in more detail.
  • FIG. 4 is a cross-sectional view for explaining the first insulating layer of the embodiment
  • FIG. 5 is a cross-sectional view showing the first through hole provided in the first insulating layer of FIG. 4
  • FIG. 6 is a cross-sectional view showing the first through hole provided in the first insulating layer of FIG. 5.
  • 1 is a cross-sectional view showing a through electrode and an insulating member
  • FIG. 7 is a view showing the layer structure of the first through electrode and the first circuit pattern layer in the first embodiment
  • FIG. 8 is a view showing the first through electrode and the first circuit pattern layer in the second embodiment. It is a diagram showing the layer structure of the circuit pattern layer
  • FIG. 9 is an optical micrograph of an actual product including a first through hole, a first through electrode, and an insulating member according to an embodiment.
  • the first through electrode 530, the first circuit pattern layer 521, the second circuit pattern layer 522, the first through electrode 530, and the insulating member according to the embodiment. (540) will be explained in detail.
  • the vertical thickness T1 of the first insulating layer 511 in the embodiment may satisfy the range of 250 ⁇ m to 1200 ⁇ m as described above.
  • the first insulating layer 511 may include a resin 511a and reinforcing fibers 511b disposed within the resin 511a.
  • the reinforcing fibers 511b may include a plurality of fibers arranged in different directions within the resin 511a.
  • the reinforcing fibers 511b include first fibers arranged in a first horizontal direction and second fibers arranged in a second horizontal direction perpendicular to the first horizontal direction.
  • the wave-shaped fiber may be the first fiber
  • the point-shaped fiber may be the second fiber.
  • the first fiber of the reinforcing fiber 511b can be called a warp yarn.
  • the second fiber of the reinforcing fiber 511b can be called a fill yarn.
  • the reinforcing fiber 511b may be made of a bundle of filaments that are long glass fibers. Additionally, the first fibers and second fibers of the reinforcing fibers 511b may be arranged in the first and second horizontal directions that intersect each other within the resin 511a, but are not limited thereto.
  • Reinforcement fibers 511b may be divided into multiple groups.
  • the reinforcing fibers 511b may be divided into a plurality of groups spaced apart from each other in the vertical direction within the resin 511a of the first insulating layer 511.
  • the reinforcing fibers 511b may include first to third groups separated from each other along the vertical direction between the upper surface 511U and the lower surface 511L of the first insulating layer 511.
  • Each of the first to third groups of reinforcing fibers is arranged in the horizontal direction within the first insulating layer 511.
  • the first to third groups of reinforcing fibers are spaced apart from each other in the vertical direction within the first insulating layer 511.
  • the drawing shows that the reinforcing fibers 511b are arranged in three groups in the first insulating layer 511, but the present invention is not limited thereto.
  • the number of groups of reinforcing fibers 511b may be determined based on the vertical thickness of the first insulating layer 511.
  • the reinforcing fibers 511b may be divided into three groups and disposed in the first insulating layer 511.
  • the reinforcing fibers 511b are divided into four groups and are attached to the first insulating layer 511. can be placed.
  • the first insulating layer 511 may be divided into a plurality of regions in the vertical direction.
  • the first insulating layer 511 may include a first region 511R1 that does not include the reinforcing fibers 511b and a second region 511R2 that includes the reinforcing fibers 511b in the vertical direction. .
  • the second regions 511R2 of the first insulating layer 511 are spaced apart from each other with the first region 511R1 in between. may include at least three sub-areas.
  • the first region 511R1 of the first insulating layer 511 has 1-1 to 1-4 sub-regions 511R11, 511R12 from a position adjacent to the top surface 511U of the first insulating layer 511. , 511R13, 511R14).
  • the second region 511R2 of the first insulating layer 511 is the 2-1st to 2nd sub-regions 511R11, 511R12, 511R13, and 511R14, respectively. It may include -3 sub-regions 511R21, 511R22, and 511R23.
  • the second region 511R2 is spaced further from the upper and lower surfaces 511U and 511L of the first insulating layer 511 than the first region 511R1. can be located. This is because, when the reinforcing fibers 511b are exposed to the upper surface 511U or the lower surface 511L of the first insulating layer 511, the physical and electrical reliability of the circuit pattern layers are deteriorated.
  • the first through hole TH1 is formed through at least two coordinate codes using a laser device, a concave portion and a concave portion along the vertical direction are formed on the inner wall of the first through hole TH1.
  • the convex portions are arranged alternately.
  • the difference between the minimum and maximum widths of the first through hole TH1 having the concave portion and the convex portion in the embodiment is the difference between the minimum width and the maximum width of the first through hole TH1 formed through one coordinate code using a conventional laser equipment. It is small compared to the difference between the minimum and maximum width.
  • the concave portion may be provided in the 1-1st to 1-4th sub-regions 511R11, 511R12, 511R13, and 511R14, and the convex portion may be provided in the 2-1st to 2-3rd subregions 511R21, 511R22, and 511R23. It can be provided in .
  • the etching rate of the resin layer composed only of the resin 511a in the first insulating layer 511 is greater than the etching rate of the layer provided with the reinforcing fibers 511b, and for this reason, the concave portion and the convex portion may be provided at the above-described positions.
  • it is not limited to this.
  • the inner wall of the first through hole TH1 includes a first inner wall IW1 and a second inner wall IW2.
  • the second inner wall (IW2) of the first through hole (TH1) may be provided as a convex portion that is convex toward the inside of the first through hole (TH1) compared to the first inner wall (IW1).
  • the inner wall of the first insulating layer 511 constituting the first through hole TH1 of the embodiment has a second inner wall IW2 that is convex toward the first through hole TH1 with respect to the first inner wall IW1.
  • the first inner wall IW1 exemplarily has a vertical slope, but is not limited thereto and may be provided as a concave portion that is concave toward the outer surface of the first insulating layer 511 .
  • the second inner wall IW2 of the embodiment may include a plurality of convex portions spaced apart from each other in the vertical direction.
  • the convex portion may be an area where the width increases or decreases.
  • the convex portion may be provided as a curved surface with a certain curvature along the vertical direction, but is not limited to this.
  • the inner walls (IW1, IW2) of the first through hole (TH1) have convex portions and concave portions to enable uniform placement of the first through electrode in the first through hole (TH1), thereby reducing the impedance.
  • Stable matching is possible and voltage drop or current and/or signal loss can be reduced.
  • reliability against thermal stress can be improved. That is, by arranging the horizontal width of the first through electrode to be thicker than the thickness of the conventional vertical first through electrode 530 shown in FIG. 3A, voltage drop or current and/or signal loss can be reduced. , it can be a more advantageous structure for heat dissipation.
  • the first inner wall IW1 may be formed in the first region 511R1 of the first insulating layer 511 in the first through hole TH1, and the second inner wall IW2 may be formed in the first through hole TH1. It may be formed in the second region 511R2 of the first insulating layer 511.
  • the first through hole TH1 is formed in the first insulating layer 511 with a thickness T1 of 250 ⁇ m or more using a laser device.
  • the first insulating layer 511 of the embodiment corresponds to the inner wall of the second region 511R2 of the first insulating layer 511 where the reinforcing fibers 511b are disposed, and is convex toward the first through hole TH1. It may include a second inner wall (IW2). Additionally, the first inner wall (IW1) and the second inner wall (IW2) may each include a plurality of sub-parts.
  • the first inner wall (IW1) has 1-1 to 1-4 sub-parts (IW1-1, IW1-2, IW1- 3, IW1-4) may be included.
  • the second inner wall (IW2) includes the 2-1 to 2-3 sub parts disposed between the 1-1 to 1-4 sub parts (IW1-1, IW1-2, IW1-3, and IW1-4), respectively. May include parts (IW2-1, IW2-2, IW2-3).
  • the number of sub-parts of the second inner wall IW2 may correspond to the number of groups of reinforcing fibers 511b provided in the first insulating layer 511. Accordingly, the number of sub-parts of the second inner wall IW2 may be more than 2, more than 3, more than 4, or more than 5.
  • the first through hole TH1 has a first width W1 in the horizontal direction in an area corresponding to the 1-1 subpart IW1-1 of the first inner wall IW1 and has a first width W1 in the second inner wall IW2. It has a second width (W2) smaller than the first width (W1) in the area corresponding to the 2-1 subpart (IW2-1).
  • the first through hole TH1 has a first width W1 again in an area corresponding to the 1-2 subpart IW1-2 of the first inner wall IW1 and has a first width W1 in the area corresponding to the 1-2 subpart IW1-2 of the first inner wall IW1.
  • the first through hole TH1 has a first width W1 again in an area corresponding to the 1-3 subpart IW1-3 of the first inner wall IW1 and then has a first width W1 in the area corresponding to the 1-3 subpart IW1-3 of the first inner wall IW1. It has a second width (W2) smaller than the first width (W1) in the area corresponding to the 2-3 subpart (IW2-3).
  • the first insulating layer 511 has a first width W1 again in the area corresponding to the 1-4 subpart (IW1-4) of the first inner wall (IW1).
  • the first through hole TH1 is connected to the 1-1 to 1-4 sub-parts (IW1-1, IW1-2, IW1-3, IW1-4) of the first inner wall (IW1). ) may not all have the same first width (W1) in each region corresponding to ), and the 2-1st to 2-3rd subparts (IW2-1, IW2-2, IW2) of the second inner wall (IW2) In -3), they may not all have the same second width (W2).
  • the first insulating layer 511 of the embodiment includes reinforcing fibers 511b vertically spaced in groups of more than 2, more than 3, more than 4, or more than 5.
  • the inner wall of the first insulating layer 511 where the first through hole TH1 is formed includes a plurality of convex portions that are convex toward the center of the first through hole TH1 in the area where the reinforcing fibers 511b are disposed.
  • the plurality of convex portions may be spaced apart from each other in the vertical direction in the first insulating layer 511 . Additionally, each convex portion may extend from the inner wall of the first through hole TH1 along a circumferential direction of the inner wall of the first through hole TH1.
  • the first width W1 of the first through hole TH1 may mean the width in the horizontal direction of the area having the maximum width in the entire area in the vertical direction.
  • the second width W2 of the first through hole TH1 may mean the horizontal width of the area having the minimum width in the entire vertical area.
  • the second width was less than 50% of the first width.
  • the second width W2 of the embodiment may satisfy a range of 55% to 95% of the first width W1.
  • the second width W2 is less than 55% of the first width W1
  • the difference in the width of the through hole increases, and as a result, plating characteristics in the plating process of filling the through hole may deteriorate.
  • the difference in width is large, the difference in plating growth speed during the plating process also increases, and accordingly, a void area of an empty space that is not filled with a metal material may exist inside the through hole.
  • plating characteristics in the plating process may be deteriorated due to the absence of a plating bridge.
  • first through electrode 530 and the insulating member 540 of the embodiment may be disposed in the first through hole TH1.
  • the first through electrode 530 may contact the inner walls (IW1, IW2) of the first insulating layer 511 including the first through hole (TH1).
  • the insulating member 540 may be disposed inside the first through electrode 530 within the first through hole TH1.
  • the first through electrode 530 may be provided to surround the outside of the insulating member 540 within the first through hole TH1.
  • the first through electrode 530 may have a certain thickness and may be disposed on the inner wall of the first insulating layer 511 including the first through hole TH1.
  • the thickness of the first through electrode 530 may refer to the distance of the first through electrode 530 in the horizontal direction. Specifically, the thickness of the first through electrode 530 may mean the width of the first through electrode 530 in the horizontal direction.
  • the first through electrode 530 may be divided into a plurality of parts.
  • the first through electrode 530 may include a concave portion disposed on the first inner wall IW1 corresponding to the first region 511R1 of the first insulating layer 511.
  • the first through electrode 530 may include a convex portion disposed on the second inner wall IW2 corresponding to the second region 511R2 of the first insulating layer 511.
  • the side surface of the first through electrode 530 having the concave portion and the convex portion may have a step in the vertical direction. Specifically, the concave portion of the first through electrode 530 does not overlap the reinforcing fiber 511b in the horizontal direction.
  • the convex portion of the first through electrode 530 overlaps the reinforcing fiber 511b in the horizontal direction.
  • the convex portion of the first through electrode 530 corresponds to the convex portion provided on the second inner wall (IW2) of the first insulating layer 511.
  • the concave portion of the first through electrode 530 corresponds to the concave portion provided in the first inner wall (IW1) of the first insulating layer 511.
  • the first through electrode 530 may have a shape in which concave portions and convex portions are alternately arranged along the vertical direction.
  • the concave portion of the first through electrode 530 corresponds to the concave portion provided in the first inner wall (IW1) of the first through hole (TH1), and the convex portion of the first through electrode 530 corresponds to the concave portion of the first through hole (TH1). It appears to correspond to the convex portion provided on the second inner wall (IW2) of TH1), but is not limited to this.
  • the first through electrode 530 may have a third thickness W3 in the horizontal direction in the area where the concave portion is provided. Additionally, the first through electrode 530 may have a fourth thickness W4 in the horizontal direction in the area where the convex portion is provided. At this time, the third thickness W3 may correspond to the fourth thickness W4. For example, the third thickness W3 and the fourth thickness W4 may be equal to each other. That is, the first through electrode 530 may have the same thickness in the horizontal direction in each of the areas provided with the concave portion and the area provided with the convex portion. Here, having the same thickness may mean that the difference in thickness in the horizontal direction between the area provided with the concave portion and the area provided with the convex portion is 3 ⁇ m or less.
  • the horizontal thicknesses W3 and W4 of the first through electrode 530 may range from 10 ⁇ m to 25 ⁇ m.
  • the resistance of the first through electrode 530 may increase and the allowable current of a signal that can be transmitted may decrease. Additionally, if the horizontal thickness of the first through electrode 530 is less than 10 ⁇ m, electrical characteristics may deteriorate. For example, when the horizontal thickness of the first through electrode 530 is less than 10 ⁇ m, the reinforcing fibers 511b exposed through the first through hole TH1 are stably stabilized by the first through electrode 530. It may not be covered. In addition, when the reinforcing fibers 511b are not covered by the first through electrode 530, a problem in which electrical properties are deteriorated due to the reinforcing fibers 511b may occur.
  • the horizontal thickness of the first through electrode 530 exceeds 25 ⁇ m, a concave portion of the first through electrode 530 is formed due to a difference in plating speed growth in the process of forming the first through electrode 530.
  • the thickness difference between the exposed area and the area provided with the convex portion of the first through electrode 530 may increase.
  • the insulating member 540 may include a region whose width changes from the upper surface to the lower surface.
  • the insulating member 540 may include a plurality of concave portions that are concave inward and a plurality of convex portions that are convex toward the first through electrode 530 .
  • the insulating member 540 may be provided with a plurality of concave portions spaced apart in the vertical direction. Additionally, the convex portion of the insulating member 540 may be provided between each of the plurality of concave portions of the insulating member 540.
  • the insulating member 540 includes a first part 541 having a fifth width W5, and a second part having a sixth width W6 smaller than the fifth width W5 ( 542) may be included. Additionally, the side surface of the first portion 541 of the insulating member 540 may be provided with a convex portion that protrudes toward the first through electrode 530 . Additionally, a side surface of the second portion 542 of the insulating member 540 may be provided with a concave portion that is concave inward.
  • the inner wall of the first through hole TH1 of the first insulating layer 511 includes a convex portion corresponding to the reinforcing fiber 511b.
  • the insulating member 540 may also have a concave portion corresponding to the convex portion of the first through hole TH1.
  • the insulating member 540 may include a convex portion provided in the first through hole TH1 and a concave portion that overlaps in the horizontal direction.
  • the insulating member 540 may have a convex portion that overlaps the concave portion provided in the first through hole TH1 in the horizontal direction.
  • the side surface of the first portion 541 of the insulating member 540 is shown to be vertical, but the present invention is not limited to this.
  • the side surface of the first portion 541 may be provided with a curved convex portion that is convex toward the first through electrode 530.
  • a plurality of first portions 541 of the insulating member 540 may be provided and spaced apart from each other in the vertical direction.
  • the first part 541 of the insulating member 540 includes a 1-1 part 541-1, a 1-2 part 541-2, and a 1-1 part 541-1. It may include part 3 (541-3) and first to fourth parts (541-4).
  • the second part 542 of the insulating member 540 may include a 2-1 part 542-1, a 2-2 part 542-2, and a 2-3 part 542-3. You can.
  • the 2-1 part 542-1, the 2-2 part 542-2, and the 2-3 part 542-3 may be parts that overlap the reinforcing fiber 511b in the horizontal direction.
  • the 1-1 part (541-1), the 1-2 part (541-2), the 1-3 part (541-3), and the 1-4 part (541-4) are reinforced fibers (511b). ) may be a part that does not overlap in the horizontal direction.
  • the 2-1 part (542-1), the 2-2 part (542-2), and the 2-3 part (542-3) are formed by the reinforcing fibers (511b). 1), it may have a smaller width than the 1-2 part 541-2, the 1-3 part 541-3, and the 1-4 part 541-4.
  • the first through electrode 530 may be composed of multiple layers.
  • the first through electrode 530 is used to form the first circuit pattern layer 521 and the second circuit pattern layer 522.
  • the first through electrode 530 may have a layer structure corresponding to the layers constituting the first circuit pattern layer 521 and the second circuit pattern layer 522.
  • the first circuit pattern layer 521 may include a plurality of metal layers.
  • the first circuit pattern layer 521 includes a first metal layer 521-1 disposed on the first insulating layer 511, and a second metal layer 521 disposed on the first metal layer 521-1. -2), and a third metal layer 521-3 disposed on the second metal layer 521-2.
  • the first metal layer 521-1 of the first circuit pattern layer 521 may refer to a copper foil layer attached to the surface of the first insulating layer 511.
  • the second metal layer 521-2 of the first circuit pattern layer 521 may be a plating layer formed on the first metal layer 521-1 through electroless plating.
  • the second metal layer 521-2 of the first circuit pattern layer 521 may be a chemical copper plating layer.
  • the third metal layer 521-3 of the first circuit pattern layer 521 may be a plating layer formed by electrolytic plating using the second metal layer 521-2 as a seed layer.
  • the third metal layer 521-3 of the first circuit pattern layer 521 may be an electrolytic plating layer.
  • the third metal layer 521-3 of the first circuit pattern layer 521 in the first embodiment may be disposed on the upper surface of the insulating member 540.
  • the third metal layer 521-3 of the first circuit pattern layer 521 may be formed by performing electrolytic plating multiple times.
  • the third metal layer 521-3 of the first circuit pattern layer 521 in the second embodiment may not cover the top surface of the insulating member 540.
  • the third metal layer 521-3 of the first circuit pattern layer 521 may be formed by performing one electrolytic plating process. At this time, the third metal layer 521-3 of the first circuit pattern layer 521 may not overlap the top surface of the insulating member 540 in the vertical direction.
  • the first through electrode 530 is disposed on the fourth metal layer 530-1 and the fourth metal layer 530-1 corresponding to the second metal layer 521-2 of the first circuit pattern layer 521. and may include a fifth metal layer 530-2 corresponding to the third metal layer 521-3 of the first circuit pattern layer 521.
  • the fourth metal layer 530-1 of the first through electrode 530 may be provided on the inner wall of the first insulating layer 511 including the first through hole TH1. Additionally, the fifth metal layer 530-2 of the first through electrode 530 may be disposed between the fourth metal layer 530-1 of the first through electrode 530 and the insulating member 540.
  • the thicknesses W4 and W5 in the horizontal direction of the first through electrode 530 are the horizontal directions of the fourth metal layer 530-1 and the fifth metal layer 530-2 of the first through electrode 530. It can mean the sum of the thicknesses.
  • the thickness of the first insulating layer 511 in the vertical direction may be 400 ⁇ m or more, and accordingly, the reinforcing fibers 511b are divided into four groups in the vertical direction. can be placed. Accordingly, the inner wall of the first through hole TH1 of the first insulating layer 511 may be provided with protruding portions corresponding to each of the four groups of reinforcing fibers 511b.
  • the first through electrode 530 disposed on the sidewall of the first through hole TH1 includes one side facing the insulating member 540 and the other side facing the first insulating layer 511. , one surface includes a convex portion protruding toward the insulating member 540 and a concave portion concave toward the first through hole TH1.
  • the first through electrode 530 shown in FIG. 9 shows one cross section, and one side of the first through electrode 530 is arranged to surround the insulating member 540.
  • the concave portions of the first through electrodes 530 may face each other and overlap along the horizontal direction, and the convex portions of the first through electrodes 530 may face each other and overlap along the horizontal direction. Additionally, the convex portions and concave portions may have a structure in which the convex portions and concave portions are alternately arranged along the vertical direction. Through this, the thickness of the first penetrating electrode 530 in the horizontal direction can be placed relatively uniformly, and it can be placed thicker than in the process using drill machine equipment.
  • the other surface of the first penetrating electrode 530 may have a different shape from the one surface. That is, one surface on which the concave portion of the first through electrode 530 is disposed and the other surface overlapping along the horizontal direction may not have a concave surface or may have different curvatures. Referring to FIG. 9, the curvature of one surface of the first through electrode 530 and the curvature of the other surface overlapping the concave surface in the horizontal direction are shown to be different from each other. Through this, the bonding force between the insulating member 540 and the first through electrode 530 can be improved, heat dissipation characteristics can be improved, and mechanical reliability of the semiconductor package substrate can be improved by controlling stress.
  • the convex portion of one surface of the first through electrode 530 may have a different curvature from the convex portion of the other surface that overlaps the convex portion in the horizontal direction. Since the convex portion on the other side may be arranged in a structure that surrounds the glass fiber differently from the convex portion on one side, its curvature may be different from the convex portion on one side. Specifically, when the first through electrode 530 surrounds a glass fiber, the horizontal thickness of the first through electrode 530 must be 10 ⁇ m or more to prevent the problem of deterioration of electrical characteristics. Therefore, the convex portion on the other side surrounds the glass fiber, and in order to prevent electrical properties from being deteriorated, the convex portion on one side and the convex portion on the other side can be arranged to have different curvatures.
  • FIGS. 10 to 14 are diagrams showing part of a method for manufacturing a semiconductor package substrate according to an embodiment, in process order. Hereinafter, a process for forming the first through hole TH1 in the first insulating layer 511 will be described.
  • a first insulating layer 511 is prepared.
  • the first insulating layer 511 may be CCL.
  • copper foil layers may be disposed on both sides of the first insulating layer 511, respectively.
  • the copper foil layer may include a first metal layer 521-1 of the first circuit pattern layer 521 and a first metal layer 522-1 of the second circuit pattern layer 522.
  • the embodiment may proceed with a process of forming the first through hole TH1 in the first insulating layer 511.
  • the first through hole TH1 may be formed through multiple laser processes using multiple coordinate codes.
  • the first insulating layer 511 has a vertical thickness of 250 ⁇ m or more. Accordingly, it may be difficult to form the first through hole TH1 penetrating the first insulating layer 511 only on one side of the first insulating layer 511 . Accordingly, the embodiment may proceed with a process of initially forming a portion of the first through hole TH1 on the upper side of the first insulating layer 511.
  • the embodiment proceeds with a process of forming a portion of the first through hole TH1 on the upper side of the first insulating layer 511 using the first coordinate code (T-code A).
  • the first coordinate code (T-code A) may include location information (TCI) corresponding to the location where the first through hole (TH1) will be formed.
  • a portion of the first through hole TH1 may be formed by irradiating a laser from the upper side of the first insulating layer 511 using the first coordinate code (T-code A).
  • a first mask having an opening of the first size may be used.
  • a laser of the first laser energy intensity is irradiated through the opening of the first mask to form the first portion HP1, which is part of the first through hole TH1, on the upper side of the first insulating layer 511. The process can proceed.
  • a second part (HP2) connected to the first part (BP1) is formed on the upper side of the first insulating layer 511 using a second coordinate code (T-code B).
  • the forming process can proceed.
  • the second coordinate code (T-code B) may include location information (TCI) corresponding to the first coordinate code (T-code A).
  • a second mask having an opening of a second size smaller than the first size is used. Available.
  • a laser of a second energy intensity greater than the first energy intensity is irradiated through the opening of the second mask, and the second portion of the first through hole TH1 is on the upper side of the first insulating layer 511 ( HP2) can be formed.
  • the horizontal widths of the first portion HP1 and the second portion HP2 of the first through hole TH1 may be substantially the same.
  • the first insulating layer 511 includes reinforcing fibers 511b. Accordingly, in the first portion HP1 and the second portion HP2 of the first through hole TH1, protrusions may be provided in areas that overlap the reinforcing fibers 511b in the horizontal direction.
  • the embodiment proceeds with a process of forming the remaining portion of the first through hole TH1 on the lower side of the first insulating layer 511 using the first coordinate code (T-code A).
  • the embodiment applies the first laser process conditions according to the first coordinate code (T-code A), and perpendicular to the first part (HP1) and the second part (HP2) of the first through hole (TH1).
  • a third portion (HP3) of the first through hole (TH1) aligned in the direction may be formed.
  • the embodiment forms the fourth part (HP4) connected to the third part (HP3) of the first through hole (TH1) using the second coordinate code (T-code B).
  • the process can proceed.
  • the fourth part HP4 is connected to the second part HP2, and thus the final first through hole TH1 can be formed.
  • the semiconductor package substrate having the characteristics of the above-described invention when used in IT devices or home appliances such as smartphones, server computers, and TVs, functions such as signal transmission or power supply can be stably performed.
  • a semiconductor package substrate having the characteristics of the present invention when a semiconductor package substrate having the characteristics of the present invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can prevent problems with leakage current or electrical short circuits between terminals. It can solve the problem of electrical opening of the terminal supplying the semiconductor chip. Additionally, if it is responsible for the function of signal transmission, the noise problem can be solved.
  • the semiconductor package substrate having the characteristics of the above-described invention can maintain the stable function of IT devices or home appliances, so that the entire product and the semiconductor package substrate to which the present invention is applied can achieve functional unity or technical interoperability with each other. .
  • the semiconductor package substrate having the characteristics of the above-described invention When the semiconductor package substrate having the characteristics of the above-described invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of the signal transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside, The stability of the transportation device can be further improved by solving the problem of leakage current, electrical short-circuiting between terminals, or electrical opening of the terminal supplying the semiconductor chip. Accordingly, the transportation device and the semiconductor package substrate to which the present invention is applied can achieve functional unity or technical interoperability with each other. Furthermore, when the semiconductor package substrate having the characteristics of the above-described invention is used in a transportation device such as a vehicle, a high-current signal required by the vehicle can be transmitted at high speed, thereby improving the safety of the transportation device. Furthermore, it enables normal operation of the semiconductor package substrate and the semiconductor package including it even in unexpected situations that occur in various driving environments of transportation devices, thereby protecting drivers safely.

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Abstract

Un substrat de boîtier semi-conducteur selon un mode de réalisation comprend : une couche isolante ayant une surface supérieure et une surface inférieure ; et une électrode traversante pénétrant la surface supérieure et la surface inférieure de la couche isolante, une surface latérale de l'électrode traversante comprenant une partie concave et une partie convexe disposées en alternance dans une direction verticale. En outre, un substrat de boîtier semi-conducteur selon un autre mode de réalisation comprend : une couche isolante ayant une surface supérieure et une surface inférieure ; et un trou traversant pénétrant la surface supérieure et la surface inférieure de la couche isolante, une paroi latérale du trou traversant comprenant une partie concave et une partie convexe disposées en alternance dans la direction verticale.
PCT/KR2023/011868 2022-08-10 2023-08-10 Substrat de boîtier semi-conducteur et boîtier semi-conducteur le comprenant WO2024035176A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093247A (ja) * 1996-09-18 1998-04-10 Kyocera Corp 多層配線基板
JP2009054689A (ja) * 2007-08-24 2009-03-12 Kyocera Corp 配線基板、実装基板および実装構造体、並びに配線基板の製造方法
KR20160123525A (ko) * 2015-04-16 2016-10-26 엘지이노텍 주식회사 인쇄회로기판
CN208016126U (zh) * 2015-07-06 2018-10-26 株式会社村田制作所 基板以及具备该基板的电子设备
KR20210143997A (ko) * 2020-05-21 2021-11-30 엘지이노텍 주식회사 인쇄회로기판 및 이의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093247A (ja) * 1996-09-18 1998-04-10 Kyocera Corp 多層配線基板
JP2009054689A (ja) * 2007-08-24 2009-03-12 Kyocera Corp 配線基板、実装基板および実装構造体、並びに配線基板の製造方法
KR20160123525A (ko) * 2015-04-16 2016-10-26 엘지이노텍 주식회사 인쇄회로기판
CN208016126U (zh) * 2015-07-06 2018-10-26 株式会社村田制作所 基板以及具备该基板的电子设备
KR20210143997A (ko) * 2020-05-21 2021-11-30 엘지이노텍 주식회사 인쇄회로기판 및 이의 제조 방법

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