WO2024035176A1 - Semiconductor package substrate and semiconductor package including same - Google Patents

Semiconductor package substrate and semiconductor package including same Download PDF

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Publication number
WO2024035176A1
WO2024035176A1 PCT/KR2023/011868 KR2023011868W WO2024035176A1 WO 2024035176 A1 WO2024035176 A1 WO 2024035176A1 KR 2023011868 W KR2023011868 W KR 2023011868W WO 2024035176 A1 WO2024035176 A1 WO 2024035176A1
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WIPO (PCT)
Prior art keywords
semiconductor package
insulating layer
hole
electrode
package substrate
Prior art date
Application number
PCT/KR2023/011868
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French (fr)
Korean (ko)
Inventor
배진수
나용석
정헌
권순규
명세호
황정호
Original Assignee
엘지이노텍 주식회사
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Publication of WO2024035176A1 publication Critical patent/WO2024035176A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • the embodiment relates to a semiconductor package substrate and a semiconductor package including the same.
  • a typical semiconductor package has a structure in which multiple chips are arranged.
  • the size of semiconductor packages is increasing due to the recent higher specifications of products to which semiconductor packages are applied and the adoption of a large number of chips such as HBM (High Bandwidth Memory).
  • HBM High Bandwidth Memory
  • various configurations are being studied to ensure reliability, such as including interposers to connect multiple chips.
  • high performance may include conditions such as high-speed transmission of signals, integration of semiconductor packages, and high allowable current for signals that can be transmitted.
  • the pad may be a mounting pad connected to a chip or a bump pad connected to various substrates.
  • the various substrates may include additional packages such as a memory substrate, an interposer connecting a chip and a semiconductor package substrate, and a main board of an electronic device to which the semiconductor package is applied.
  • a multilayer semiconductor package substrate includes a through electrode disposed in a through hole formed in a core substrate such as a copper clad laminate (CCL).
  • CCL copper clad laminate
  • the number of stacks of semiconductor package substrates is increasing as wiring becomes more complex, and as the area increases, the thickness of the core substrate is increasing to improve strength and bending characteristics.
  • the thickness of the conventional core substrate was around 200 ⁇ m, but recently, the thickness has been increasing several times or more.
  • a drill machine is used to form a through hole in the core substrate.
  • Patent Document 1 KR 10-2011-0016266 A
  • Embodiments provide a semiconductor package substrate with a new structure and a semiconductor package including the same.
  • the embodiment provides a semiconductor package substrate capable of forming a through hole in a core substrate of 200 ⁇ m or more using a laser process, and a semiconductor package including the same.
  • the embodiment provides a semiconductor package substrate in which the difference between the maximum and minimum widths of the through hole in the vertical direction is minimized, and a semiconductor package including the same.
  • the embodiment provides a semiconductor package substrate that prevents expansion of the size of the through hole and ensures that the inner wall of the through hole has an inclination close to a right angle, and a semiconductor package including the same.
  • a semiconductor package substrate includes an insulating layer having a top and bottom surfaces; and a through electrode penetrating the upper and lower surfaces of the insulating layer, and a side surface of the through electrode includes concave portions and convex portions alternately provided along a vertical direction.
  • a semiconductor package substrate includes an insulating layer having a top and bottom surfaces; and a through hole penetrating the upper and lower surfaces of the insulating layer, wherein side walls of the through hole include concave portions and convex portions alternately provided along a vertical direction.
  • the semiconductor package substrate further includes a through electrode disposed in the through hole, and a side surface of the through electrode has a convex portion corresponding to a convex portion of a side wall of the through hole and a concave portion corresponding to a concave portion of a side wall of the through hole.
  • the semiconductor package substrate further includes an insulating member penetrating the insulating layer, and the penetrating electrode is provided to surround an outside of the insulating member.
  • a plurality of concave portions and convex portions of the through electrode are provided alternately along the vertical direction.
  • the insulating member includes a first part having a first width in the horizontal direction, and a second part having a second width different from the first width in the horizontal direction.
  • the first width is greater than the second width, the first portion horizontally overlaps the concave portion of the through electrode, and the second portion horizontally overlaps the convex portion of the through electrode.
  • the insulating layer includes a resin and reinforcing fibers disposed in the resin, wherein the reinforcing fibers include first fibers disposed in a first horizontal direction and first fibers disposed in a second horizontal direction perpendicular to the first horizontal direction. Contains 2 fibers.
  • the reinforcing fibers include a plurality of groups spaced apart from each other along the vertical direction and each having the first and second fibers.
  • the concave portion of the penetrating electrode overlaps the reinforcing fiber in a horizontal direction.
  • the thickness of the insulating layer in the vertical direction satisfies the range of 250 ⁇ m to 1200 ⁇ m.
  • the inner wall of the through hole in the insulating layer includes a plurality of first inner walls having protrusions and a second inner wall not having the protrusions.
  • the second inner wall refers to a portion of the inner wall of the through hole having a concave portion.
  • the through electrode includes a first part in contact with the first inner wall and a second part in contact with the second inner wall. At this time, the first and second through patterns have a step.
  • the first portion of the through electrode has a concave portion corresponding to a concave portion of the through hole
  • the second portion of the through electrode has a convex portion corresponding to a convex portion of the through hole.
  • each of the first and second portions of the penetrating electrode satisfies the range of 10 ⁇ m to 25 ⁇ m.
  • the thickness of the first portion of the through electrode in the horizontal direction is the same as the thickness of the second portion in the horizontal direction.
  • the first through electrode includes a first metal layer disposed on the inner wall of the first through hole of the insulating layer, and a second metal layer disposed on the first metal layer.
  • the minimum width of the area having the smallest width in the entire area in the vertical direction of the first through hole is 55% of the maximum width of the area having the largest width in the entire area in the vertical direction of the first through hole. Satisfies 95% coverage.
  • the semiconductor package substrate of the embodiment allows the formation of a through hole with a minimized difference between the maximum and minimum widths using laser processing equipment in the first insulating layer having a thickness of 250 ⁇ m or more. Through this, the embodiment makes it possible to improve the physical and electrical characteristics of the first through electrode provided on the semiconductor package substrate.
  • the first insulating layer is a core layer containing reinforcing fibers.
  • the through hole when a through hole is formed in the first insulating layer using a laser device, the through hole includes areas with different widths along the vertical direction, and the minimum width is less than 50% of the maximum width. Accordingly, in the comparative example, there was a problem of non-uniform placement of the through electrodes due to differences in plating speeds for each region in the plating process of placing the through electrodes in the through holes.
  • the laser intensity under laser processing conditions was increased to minimize the difference between the minimum and maximum widths.
  • a size expansion problem occurs in which the size of the through hole is formed larger than the target size.
  • a through hole is formed using machine drill equipment to minimize the difference between the minimum and maximum width.
  • machine drill equipment only one through hole can be formed at a time. This had the problem of lowering the production yield.
  • a through hole is formed in the first insulating layer using at least two coordinate codes (T-code).
  • T-code coordinate codes
  • a portion of a through hole is formed by irradiating a laser having a first laser energy intensity to a first mask having an opening of a first size using a first coordinate code.
  • a laser of a second laser energy intensity having an energy intensity different from the first laser energy intensity is irradiated to a second mask having an opening of a second size different from the first size using the second coordinate code to form a remaining portion of the through hole.
  • the embodiment can form a through hole with a minimized difference between the maximum and minimum widths in the first insulating layer using a laser device while preventing expansion of the size of the through hole.
  • the embodiment can solve the non-uniformity of the thickness of the first through electrode in the plating process of disposing the first through electrode in the first through hole.
  • the embodiment can improve the physical properties of the semiconductor package substrate.
  • the first through-electrode can be disposed to have a uniform thickness in the first insulating layer through improved plating characteristics.
  • the loss of the signal transmitted through the first through electrode can be minimized, voltage drop can be prevented, and the degree of freedom in wiring design can be increased by benefiting impedance matching. Furthermore, the first through hole according to this embodiment can improve the electrical characteristics of the semiconductor package substrate and the semiconductor package including the same.
  • the embodiment it is possible to form a through hole using a laser device in the first insulating layer that has a vertical thickness of 250 ⁇ m to 1200 ⁇ m and includes reinforcing fibers therein.
  • the embodiment can reduce the time required to form a through hole compared to forming a through hole using machine drill equipment. Accordingly, the embodiment can improve the production yield of semiconductor package substrates.
  • the embodiment can reduce the manufacturing cost of the semiconductor package substrate by eliminating the need to use relatively expensive machine drill equipment.
  • 1A is a cross-sectional view for explaining a semiconductor package substrate according to a first comparative example.
  • FIG. 1B is a cross-sectional view illustrating a semiconductor package substrate according to a second comparative example.
  • Figure 2a is a cross-sectional view showing a semiconductor package according to the first embodiment.
  • Figure 2b is a cross-sectional view showing a semiconductor package according to a second embodiment.
  • Figure 2c is a cross-sectional view showing a semiconductor package according to a third embodiment.
  • Figure 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.
  • Figure 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.
  • Figure 2f is a cross-sectional view showing a semiconductor package according to the sixth embodiment.
  • Figure 2g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.
  • FIG. 3A is a diagram showing a semiconductor package substrate according to the first embodiment.
  • Figure 3b is a diagram showing a semiconductor package substrate according to a second embodiment.
  • Figure 4 is a cross-sectional view for explaining the first insulating layer of the embodiment.
  • FIG. 5 is a cross-sectional view showing a first through hole provided in the first insulating layer of FIG. 4.
  • FIG. 6 is a cross-sectional view showing a first through electrode and an insulating member disposed in the through hole of FIG. 5.
  • Figure 7 is a diagram showing the layer structure of the first through electrode and the first circuit pattern layer in the first embodiment.
  • Figure 8 is a diagram showing the layer structure of the first through electrode and the first circuit pattern layer in the second embodiment.
  • FIG. 9 is an optical microscope photograph of an actual product including a first through hole, a first through electrode, and an insulating member according to an embodiment.
  • 10 to 14 are diagrams showing part of a method for manufacturing a semiconductor package substrate according to an embodiment, in process order.
  • the technical idea of the present invention is not limited to some of the described embodiments, but may be implemented in various different forms, and as long as it is within the scope of the technical idea of the present invention, one or more of the components may be optionally used between the embodiments. It can be used by combining and replacing.
  • top or bottom refers not only to cases where two components are in direct contact with each other, but also to one component. This also includes cases where another component described above is formed or placed between two components.
  • top (above) or bottom (bottom) it may include not only the upward direction but also the downward direction based on one component.
  • FIG. 1A is a cross-sectional view illustrating a semiconductor package substrate according to a first comparative example
  • FIG. 1B is a cross-sectional view illustrating a semiconductor package substrate according to a second comparative example.
  • the semiconductor package substrate Before explaining comparative examples, semiconductor package substrates are required to have higher densities as electronic devices become more functional and semiconductor devices become more integrated. Accordingly, the semiconductor package substrate has a multi-layer structure.
  • FCBGA Flexible Chip Ball Grid Array
  • FCCSP Flip Chip Chip Scale Package
  • the core layer is an insulating layer with rigidity to implement multi-layer build-up, and has a thickness above a certain level.
  • the thickness of the core layer may vary depending on the number of layers in the multi-layer build-up.
  • the semiconductor package substrate may have a thickness of 250 ⁇ m to 1200 ⁇ m in order to increase the complexity of wiring and reduce voltage drop problems and/or signal loss.
  • penetrating electrodes are formed in the core layer for electrical connection with the circuit patterns of each layer.
  • the through electrode may be provided by filling a through hole penetrating the upper and lower surfaces of the core layer with a conductive material.
  • the above-described core layer has a thickness of 250 ⁇ m to 1200 ⁇ m, and accordingly, the process of forming the through hole and/or the through electrode of the comparative example has the following problems.
  • the through hole is formed using either a laser device or a drill machine device.
  • Figure 1a shows a first comparative example of forming a through hole using a laser equipment
  • Figure 1b shows a second comparative example of forming a through hole using a drill machine equipment.
  • an insulating layer 10 to be used as a core layer is prepared.
  • the thickness (t) of the insulating layer 10 may be 250 ⁇ m to 1200 ⁇ m.
  • a through hole is formed in the insulating layer 10 using a laser device.
  • the insulating layer 10 has a thickness (t) of 250 ⁇ m to 1200 ⁇ m, it is difficult to form a through hole by performing laser processing on only one side of the insulating layer 10. Accordingly, in the first comparative example, laser processing is performed on each of the upper and lower surfaces of the insulating layer 10 to form through holes.
  • the first part of the through hole is formed on the upper surface of the insulating layer 10 to correspond to the target size that the through hole should have, and the first part of the through hole is connected to the lower surface of the insulating layer 10. forms the second part.
  • the energy intensity of the laser is set large to solve the problem of non-penetration of the insulating layer 10 described above. Accordingly, as shown in (c) of FIG. 1A, the first part 11 and the second part 12 are formed having a size larger than the target size that the through hole should have.
  • the through hole has a width (w1) larger than the target size. Accordingly, there is a problem that it is difficult to adjust the size of the through hole and the through electrode formed by filling the through hole in the first comparative example to the desired target size.
  • a laser beam is irradiated several times to a specific through hole using one coordinate code (eg, T-code).
  • one coordinate code eg, T-code
  • the laser process conditions may mean mask size, pulse width, energy intensity, collimation, and number of steps.
  • the minimum width in the entire area in the vertical direction of the through hole is less than 50% of the maximum width. Additionally, as the difference between the minimum and maximum widths increases, there is a problem in that the plating characteristics in the plating process for forming the through electrode deteriorate.
  • the second comparative example is a through hole 20 using drill machine equipment such as a CNC (computer numerical control) drill rather than a laser. forms.
  • the inclination of the inner wall of the through hole formed in the insulating layer 10 is substantially close to vertical.
  • this through hole 20 does not include a plating bridge, unlike the hourglass-shaped through hole of FIG. 1A, there is a problem in that it is difficult to uniformly fill the through hole 20 with a conductive material. .
  • drill machine equipment is more expensive than laser equipment. Therefore, when forming a through hole using drill machine equipment, there is a problem that a large cost is required to build infrastructure or the manufacturing cost of the semiconductor package substrate increases.
  • the through hole 20 when forming the through hole 20 using drill machine equipment, there is a problem that the productivity of the semiconductor package substrate is reduced. Specifically, when using drill machine equipment, exemplarily, only one through hole can be formed at a time. Accordingly, the manufacturing process time for a semiconductor package substrate can increase several times compared to using laser equipment, and there is a problem of decreased productivity and yield.
  • a plurality of through holes can be formed at once using the opening included in the mask, and a uniform through electrode can be formed in each of the plurality of through holes. You can. Additionally, compared to using drill machine equipment, the manufacturing process time for semiconductor package substrates can be significantly shortened, and productivity and yield can be greatly improved.
  • a through electrode with improved electrical and physical reliability can be formed inside a through hole formed in a core layer having a thickness of 250 ⁇ m to 1200 ⁇ m.
  • the embodiment provides a semiconductor package substrate including a through electrode having a new structure and a package substrate including the same.
  • Electronic devices include smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, and computers. It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. . However, it is not limited to this, and of course, it can be any other electronic device that processes data.
  • the electronic device includes a main board (not shown).
  • the main board may be physically and/or electrically connected to various components. Additionally, the main board may be connected to the semiconductor package substrate of the embodiment.
  • Various semiconductor devices can be mounted on a semiconductor package substrate.
  • Semiconductor devices may include active devices and/or passive devices.
  • the active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of active devices, such as transistors, are integrated into a single chip.
  • Semiconductor devices may be logic chips, memory chips, etc.
  • the logic chip may be a central processor (CPU), a graphics processor (GPU), or the like.
  • the logic chip is an application processor (AP) chip that includes at least one of a central processor (CPU), graphics processor (GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or an analog-digital chip. It could be a converter, an application-specific IC (ASIC), or a set of chips containing a specific combination of the ones listed so far.
  • ASIC application-specific IC
  • the memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.
  • volatile memory eg, DRAM
  • non-volatile memory eg, ROM
  • flash memory e.g., NAND
  • the product groups of semiconductor package substrates to which the semiconductor package of the embodiment is applied include CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), and POP (Package On Package). ) and SIP (System In Package), but is not limited thereto.
  • the semiconductor package of the embodiment may have various package structures including a semiconductor package substrate that will be described later. Additionally, the semiconductor package substrate in one embodiment may be referred to as a first semiconductor package substrate described below, and the semiconductor package substrate in another embodiment may be referred to as a second semiconductor package substrate described below.
  • FIG. 2A is a cross-sectional view showing a semiconductor package according to a first embodiment
  • FIG. 2B is a cross-sectional view showing a semiconductor package according to a second embodiment
  • FIG. 2C is a cross-sectional view showing a semiconductor package according to a third embodiment
  • FIG. 2D is a cross-sectional view showing a semiconductor package according to the fourth embodiment
  • FIG. 2E is a cross-sectional view showing a semiconductor package according to the fifth embodiment
  • FIG. 2F is a cross-sectional view showing a semiconductor package according to the sixth embodiment
  • FIG. 2G is a cross-sectional view showing a semiconductor package according to the sixth embodiment.
  • This is a cross-sectional view showing a semiconductor package according to Example 7.
  • the semiconductor package of the first embodiment may include a first semiconductor package substrate 100, a second semiconductor package substrate 200, and a semiconductor device 300.
  • the first semiconductor package substrate 100 refers to a package substrate.
  • the first semiconductor package substrate 100 may provide a space where at least one external substrate is coupled.
  • the external substrate may refer to the second semiconductor package substrate 200 coupled to the first semiconductor package substrate 100.
  • the external substrate may refer to a main board included in an electronic device coupled to the lower part of the first semiconductor package substrate 100.
  • the first semiconductor package substrate 100 may provide a space where at least one semiconductor device is mounted in addition to a space where the second semiconductor package substrate 200 is mounted.
  • the first semiconductor package substrate 100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a penetrating portion penetrating the at least one insulating layer.
  • a second semiconductor package substrate 200 is disposed on the first semiconductor package substrate 100.
  • the second semiconductor package substrate 200 may be an interposer. Additionally, the second semiconductor package substrate 200 may provide a space in which at least one semiconductor device is mounted. The second semiconductor package substrate 200 may be connected to at least one semiconductor device 300. For example, the second semiconductor package substrate 200 may provide a space in which the first semiconductor device 310 and/or the second semiconductor device 320 are mounted. The second semiconductor package substrate 200 electrically connects the first semiconductor device 310 and the second semiconductor device 320, and connects the first and second semiconductor devices 310 and 320 to the first semiconductor package substrate ( 100) can be electrically connected. That is, the second semiconductor package substrate 200 can function as a horizontal connection between a plurality of semiconductor devices and a vertical connection function between the semiconductor devices and the package substrate. In addition, in order to improve stress and bending problems that occur as the number of insulating layers increases due to multilayer build-up, the semiconductor package substrate can be divided into a first semiconductor package substrate 100 and a second semiconductor package substrate 200. there is.
  • FIG. 2A two semiconductor devices 310 and 320 are shown disposed on the second semiconductor package substrate 200, but the present invention is not limited thereto.
  • one semiconductor device may be disposed on the second semiconductor package substrate 200, and alternatively, three or more semiconductor devices may be disposed on the second semiconductor package substrate 200.
  • the second semiconductor package substrate 200 may be an active interposer that functions as a semiconductor device.
  • the package of the embodiment may have a plurality of logic chips mounted vertically on the first semiconductor package substrate 100. And among the logic chips, the first logic chip corresponding to the active interposer can function as the corresponding logic chip and perform a signal transmission function between the second logic chip disposed on top of the logic chip and the first semiconductor package substrate 100. there is.
  • the second semiconductor package substrate 200 may be a passive interposer.
  • the second semiconductor package substrate 200 may function as a signal relay between the semiconductor device 300 and the first semiconductor package substrate 100.
  • the number of terminals of the semiconductor device 300 is gradually increasing due to 5G, Internet of Things (IOT), increased image quality, increased communication speed, etc. That is, the number of terminals provided in the semiconductor device 300 increases, and as a result, the width of the terminal or the gap between a plurality of terminals is reduced.
  • the first semiconductor package substrate 100 is connected to the main board of the electronic device.
  • the second semiconductor package substrate 200 is disposed on the first semiconductor package substrate 100 and the semiconductor device 300. Additionally, the second semiconductor package substrate 200 may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device 300 .
  • the semiconductor package of the first embodiment may include a connection part.
  • the semiconductor package includes a first connection portion 410 disposed between the first semiconductor package substrate 100 and the second semiconductor package substrate 200.
  • the first connection portion 410 connects the second semiconductor package substrate 200 to the first semiconductor package substrate 100 and electrically connects them.
  • the semiconductor package may further include a second connection portion 420 disposed between the second semiconductor package substrate 200 and the semiconductor device 300.
  • the second connection portion 420 may couple the semiconductor devices 300 to the second semiconductor package substrate 200 and electrically connect them.
  • the semiconductor package includes a third connection portion 430 disposed on the lower surface of the first semiconductor package substrate 100.
  • the third connection portion 430 may couple the first semiconductor package substrate 100 to the main board and electrically connect them.
  • the first connection part 410, the second connection part 420, and the third connection part 430 may mean at least one bonding method among wire bonding, solder bonding, and direct bonding between metals. That is, because the first connection part 410, the second connection part 420, and the third connection part 430 have the function of electrically connecting a plurality of components, when direct bonding between metals is used, the semiconductor package is made using solder or wire. It can be understood as a part that is electrically connected, rather than as a part.
  • the wire bonding method may mean electrically connecting a plurality of components using conductors such as gold (Au). Additionally, the solder bonding method can electrically connect a plurality of components using a material containing at least one of Sn, Ag, and Cu.
  • the direct bonding method between metals may mean recrystallization by applying heat and pressure between a plurality of components without the absence of solder, wire, conductive adhesive, etc., thereby directly bonding the plurality of components. .
  • the direct bonding method between metals may refer to a bonding method using the second connection portion 420. In this case, the second connection portion 420 may refer to a metal layer formed between a plurality of components through recrystallization.
  • the first connection part 410, the second connection part 420, and the third connection part 430 may be connected to a plurality of components using a TC (Thermal Compression) bonding method.
  • TC bonding may refer to a method of bonding a plurality of components by applying heat and pressure to the first connection part 410, the second connection part 420, and the third connection part 430.
  • the electrode on which the first connection part 410, the second connection part 420, and the third connection part 430 are disposed has a protrusion.
  • the protrusion may protrude outward from the first semiconductor package substrate 100 or the second semiconductor package substrate 200 .
  • the protrusion may be referred to as a bump.
  • the protrusion may also be called a post.
  • the protrusion may also be called a pillar.
  • the protrusion may refer to an electrode of the second semiconductor package substrate 200 on which the second connection portion 420 for coupling to the semiconductor device 300 is disposed. That is, as the pitch of the terminals of the semiconductor device 300 becomes finer, a short circuit may occur in the second connection portions 420 respectively connected to the terminals of the semiconductor device 300.
  • the electrode of the second semiconductor package substrate 200 on which the second connection part 420 is disposed includes a protrusion. The protrusion may prevent diffusion of the second connection portion 420 and the matching between the electrode of the second semiconductor package substrate 200 and the terminal of the semiconductor device 300.
  • the semiconductor package of the second embodiment includes a connecting member 210 that horizontally connects a plurality of semiconductor devices disposed on the second semiconductor package substrate 200 to the second semiconductor package substrate 200. ) differs from the semiconductor package of the first embodiment in that it is arranged.
  • the connection member 210 may be referred to as a bridge board.
  • connecting member 210 may be a silicon bridge. That is, the connection member 210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.
  • the connecting member 210 may be an organic bridge.
  • the connecting member 210 may include an organic material.
  • the connection member 210 may include an organic substrate containing an organic material instead of a silicon substrate and a redistribution layer disposed on the organic substrate.
  • connection member 210 may be embedded in the second semiconductor package substrate 200, but is not limited thereto.
  • the connecting member 210 may be disposed on the second semiconductor package substrate 200 to have a protruding structure.
  • the second semiconductor package substrate 200 may include a cavity, and the connecting member 210 may be disposed within the cavity of the second semiconductor package substrate 200.
  • the semiconductor package of the third embodiment includes a second semiconductor package substrate 200 and a semiconductor device 300. At this time, the semiconductor package of the third embodiment has a structure in which the first semiconductor package substrate 100 is removed compared to the semiconductor package of the second embodiment.
  • the second semiconductor package substrate 200 of the third embodiment can function as an interposer and as a package substrate.
  • the first connection portion 410 disposed on the lower surface of the second semiconductor package substrate 200 may couple the second semiconductor package substrate 200 to the main board of the electronic device.
  • the semiconductor package of the fourth embodiment includes a first semiconductor package substrate 100 and a semiconductor device 300.
  • the semiconductor package of the fourth embodiment has a structure in which the second semiconductor package substrate 200 is removed compared to the semiconductor package of the second embodiment.
  • the first semiconductor package substrate 100 of the fourth embodiment can function as a package substrate and an interposer that connects the semiconductor device 300 and the main board.
  • the first semiconductor package substrate 100 may include a connecting member 110 for connecting a plurality of semiconductor devices.
  • the connection member 110 may be a silicon bridge or an organic bridge that connects a plurality of semiconductor devices.
  • the semiconductor package of the fifth embodiment further includes a third semiconductor element 330 compared to the semiconductor package of the fourth embodiment.
  • a fourth connection portion 440 is disposed on the lower surface of the first semiconductor package substrate 100.
  • a third semiconductor element 330 may be disposed in the fourth connection part 400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively.
  • the third semiconductor device 330 may have a structure disposed on the lower surface of the second semiconductor package substrate 200 in the semiconductor package of FIG. 2C.
  • the semiconductor package of the sixth embodiment includes a first semiconductor package substrate 100.
  • a first semiconductor device 310 may be disposed on the first semiconductor package substrate 100.
  • a first connection portion 410 is disposed between the first semiconductor package substrate 100 and the first semiconductor device 310.
  • the first semiconductor package substrate 100 includes a conductive coupling portion 450.
  • the conductive coupling portion 450 may protrude further from the first semiconductor package substrate 100 toward the second semiconductor device 320 .
  • the conductive coupling portion 450 may be referred to as a bump or, alternatively, may be referred to as a post.
  • the conductive coupling portion 450 may be disposed to have a protruding structure on the electrode disposed on the uppermost side of the first semiconductor package substrate 100 .
  • the second semiconductor device 320 is disposed on the conductive coupling portion 450 of the first semiconductor package substrate 100. At this time, the second semiconductor device 320 may be connected to the first semiconductor package substrate 100 through the conductive coupling portion 450. Additionally, a second connection portion 420 may be disposed on the first semiconductor device 310 and the second semiconductor device 320.
  • the second semiconductor device 320 may be electrically connected to the first semiconductor device 310 through the second connection portion 420.
  • the second semiconductor device 320 is connected to the first semiconductor package substrate 100 through the conductive coupling portion 450 and is also connected to the first semiconductor device 310 through the second connection portion 420.
  • the second semiconductor device 320 can receive a power signal through the conductive coupling portion 450. Additionally, the second semiconductor device 320 may exchange communication signals with the first semiconductor device 310 through the second connection unit 420.
  • the semiconductor package of the sixth embodiment provides a power signal to the second semiconductor device 320 through the conductive coupling portion 450, thereby providing sufficient power to drive the second semiconductor device 320. Accordingly, the embodiment can improve the driving characteristics of the second semiconductor device 320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 320. Furthermore, the embodiment allows the power signal and communication signal of the second semiconductor device 320 to be provided through different paths through the conductive coupling portion 450 and the second connection portion 420. Through this, the embodiment can solve the problem of loss of communication signals caused by power signals. For example, embodiments may minimize mutual interference between power signals and communication signals.
  • the second semiconductor device 320 in the sixth embodiment may have a POP (Package On Package) structure and be disposed on the first semiconductor package substrate 100.
  • the second semiconductor device 320 may be a memory package including a memory chip.
  • the memory package may be coupled to the conductive coupling portion 450.
  • the memory package may not be connected to the first semiconductor device 310.
  • the second connection unit 420 may be omitted.
  • the semiconductor package in the sixth embodiment may include a molding member 1460.
  • the molding member 1460 may be disposed between the first substrate 1100 and the second semiconductor device 1320.
  • the molding member 1460 may mold the first connection part 1410, the second connection part 1420, the first semiconductor device 1310, and the conductive coupling part 1450.
  • the semiconductor package of the seventh embodiment includes a first semiconductor package substrate 100, a first connection part 410, a first connection part 410, a semiconductor device 300, and a third connection part 430. do.
  • the semiconductor package of the seventh embodiment differs from the semiconductor package of the fourth embodiment in that the connecting member 110 is removed and the first semiconductor package substrate 100 includes a plurality of substrate layers.
  • the first semiconductor package substrate 100 includes a plurality of substrate layers.
  • the first semiconductor package substrate 100 may include a first substrate layer 100A corresponding to the package substrate and a second substrate layer 100B corresponding to the redistribution layer of the connection member.
  • the first semiconductor package substrate 100 arranges the second substrate layer 100B corresponding to the redistribution layer on the first substrate layer 100A.
  • the semiconductor package of the seventh embodiment includes a semiconductor package substrate including a first substrate layer 100A and a second substrate layer 100B formed integrally.
  • the material of the insulating layer of the second substrate layer 100B may be different from the material of the insulating layer of the first substrate layer 100A.
  • the material of the insulating layer of the second substrate layer 100B may include a photocurable material.
  • the second substrate layer 100B may be a photo imageable dielectric (PID).
  • PID photo imageable dielectric
  • the electrode can be miniaturized.
  • the seventh embodiment sequentially stacks an insulating layer of a photo-curable material on the first substrate layer 100A and forms a micronized electrode on the insulating layer of a photo-curable material to form a second substrate layer 100B.
  • the second substrate 100B may be a redistribution layer including miniaturized electrodes.
  • the semiconductor package substrate described below may refer to any one of a plurality of semiconductor package substrates included in a previous semiconductor package.
  • the semiconductor package substrate described below may refer to the first semiconductor package substrate 100 and/or the second semiconductor package substrate 200 shown in any one of FIGS. 2A to 2G. there is.
  • FIG. 3A is a diagram showing a semiconductor package substrate according to a first embodiment
  • FIG. 3B is a diagram showing a semiconductor package substrate according to a second embodiment.
  • FIG. 3A a semiconductor package substrate according to an embodiment will be briefly described with reference to FIG. 3A, and some configurations different from FIG. 3A will be described with reference to FIG. 3B.
  • the semiconductor package substrate 500 of the embodiment includes an insulating layer 510.
  • the insulating layer 510 of the embodiment may have a multilayer structure.
  • the insulating layer 510 of the semiconductor package substrate of the embodiment may include a first insulating layer 511, a second insulating layer 512, and a third insulating layer 513.
  • the second insulating layer 512 and the third insulating layer 513 are shown as one layer, but the present invention is not limited to this and may be a configuration in which a plurality of insulating layers are stacked.
  • the first insulating layer 511 may include an insulating material different from the second insulating layer 512 and the third insulating layer 513.
  • the first insulating layer 511 may include an insulating material including reinforcing fibers and may be a core layer.
  • the first insulating layer 511 may include prepreg.
  • the first insulating layer 511 can improve bending characteristics by increasing the physical strength of the semiconductor package substrate.
  • the first insulating layer 511 of the embodiment may have a structure in which a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, is impregnated with an epoxy resin or the like.
  • the prepreg constituting the first insulating layer 511 of the embodiment may include a fiber layer in the form of a fabric sheet woven with carbon fiber thread.
  • the first insulating layer 511 may include a resin and reinforcing fibers disposed within the resin.
  • the resin may be an epoxy resin, but is not limited thereto.
  • the resin is not particularly limited to epoxy resin, and for example, it may contain one or more epoxy groups in the molecule, alternatively, it may contain two or more epoxy groups, and alternatively, it may contain four or more epoxy groups.
  • the resin constituting the first insulating layer 511 may contain a naphthalene group, for example, may be an aromatic amine type, but is not limited thereto.
  • the resins include bisphenol A-type epoxy resin, bisphenol F-type epoxy resin, bisphenol S-type epoxy resin, phenol novolak-type epoxy resin, alkylphenol novolak-type epoxy resin, biphenyl-type epoxy resin, and aralkyl-type epoxy resin. , dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of condensate of phenols and aromatic aldehyde having a phenolic hydroxyl group, biphenylaralkyl type epoxy resin, fluorene type epoxy resin.
  • the reinforcing fiber may be glass fiber, carbon fiber, aramid fiber (e.g., aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material. there is. Reinforcing fibers may be arranged within the resin in a form that intersects each other in a planar direction.
  • glass fiber for example, glass fiber, carbon fiber, aramid fiber (for example, aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material may be used.
  • aramid fiber for example, aramid-based organic material
  • nylon for example, silica-based inorganic material
  • titania-based inorganic material may be used.
  • the first insulating layer 511 may be provided with at least two layers of reinforcing fibers. Through this, the embodiment can further improve the rigidity of the substrate 500.
  • the vertical thickness of the first insulating layer 511 may be greater than the vertical thickness of at least one of the second insulating layer 512 and the third insulating layer 513.
  • the vertical thickness of the first insulating layer 511 is 3 times or more, 4 times or more, or 5 times or more than the vertical thickness of the second insulating layer 512 and the third insulating layer 513. , may be 7 times or more or 10 times or more.
  • the number of insulating layers of a semiconductor package substrate may be 10 or more layers, 12 or more layers, 16 or more layers, or 20 or more layers.
  • the second insulating layer 512 and the third insulating layer 513 are each stacked as a plurality of layers as shown, bending of the semiconductor package substrate may occur due to the stress of each insulating layer.
  • the semiconductor package substrate is bent, it may be difficult to form the through electrode included in the semiconductor package substrate at an accurate position.
  • problems such as the position of the semiconductor device being distorted during the process of mounting the semiconductor device on the semiconductor package substrate may occur.
  • the vertical thickness of the first insulating layer 511 may be 250 ⁇ m or more. Accordingly, in order to increase the physical rigidity of the semiconductor package substrate and improve the bending characteristics of the semiconductor package substrate during the packaging process, the first insulating layer 511 may have a vertical thickness of 250 ⁇ m or more. In addition, when the thickness of the first insulating layer 511 becomes too thick, the process of forming a through hole in the first insulating layer 511 becomes difficult, and electrical characteristics such as signals and/or power applied to the semiconductor device decrease. may deteriorate. Additionally, it may become difficult to slim the semiconductor package, which may lead to difficulties in providing electronic devices with a small volume. Therefore, it is appropriate that the vertical thickness of the first insulating layer 511 is 1200 ⁇ m or less.
  • the second insulating layer 512 and the third insulating layer 513 may include an insulating material different from the first insulating layer 511.
  • the second insulating layer 512 and the third insulating layer 513 may not include reinforcing fibers, but are not limited thereto.
  • the second insulating layer 512 and the third insulating layer 513 are made of ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. It can include either one.
  • the second insulating layer 512 and the third insulating layer 513 may include reinforcing fibers, and the reinforcing fibers may be glass fibers and may include a GCP (Glass Core Primer) material, but are limited thereto. It doesn't work.
  • GCP Glass Core Primer
  • the second insulating layer 512 and the third insulating layer 513 may use a CCL (Copper Clad Laminate) type insulating layer, but are not limited thereto.
  • CCL Copper Clad Laminate
  • the second insulating layer 512 and the third insulating layer 513 may have a vertical thickness ranging from 10 ⁇ m to 50 ⁇ m. If the vertical thickness of the second insulating layer 512 or the third insulating layer 513 is less than 10 ⁇ m, the bending characteristics of the semiconductor package substrate 500 may deteriorate. In addition, if the vertical thickness of the second insulating layer 512 or the third insulating layer 513 is less than 10 ⁇ m, the circuit pattern layer included in the semiconductor package substrate 500 may not be stably protected or the insulating properties may be poor. may deteriorate, thereby reducing electrical reliability.
  • the vertical thickness of the second insulating layer 512 or the third insulating layer 513 exceeds 50 ⁇ m, the overall thickness of the semiconductor package substrate 500 increases, and thus the thickness of the semiconductor package increases. can do. Additionally, if the thickness of the second insulating layer 512 or the third insulating layer 513 exceeds 50 ⁇ m, it may be difficult to miniaturize the circuit pattern layer of the semiconductor package substrate 500.
  • the thickness in the vertical direction may refer to the length from the top to the bottom of the semiconductor package substrate 500 or from the bottom to the top.
  • the upper surface may mean the highest position in each component along the vertical direction
  • the lower surface may mean the lowest position in each component along the vertical direction. And their positions can be referred to as opposites to each other.
  • the second insulating layer 512 and the third insulating layer 513 are each shown as consisting of one layer, but this is not limited to this.
  • the semiconductor package substrate 500 of the embodiment may have an 11-layer structure based on the number of insulating layers.
  • the second insulating layer 512 and the third insulating layer 513 may each be composed of five layers.
  • the semiconductor package substrate 500 of the embodiment may have a 17-layer structure based on the number of insulating layers.
  • each of the second insulating layer 512 and the third insulating layer 513 may be composed of 8 layers.
  • the semiconductor package substrate 500 may include a circuit pattern layer disposed on the insulating layer 510 .
  • the semiconductor package substrate 500 may include a first circuit pattern layer 521 disposed on the top of the first insulating layer 511.
  • the semiconductor package substrate 500 may include a second circuit pattern layer 522 disposed on the lower surface of the first insulating layer 511.
  • the semiconductor package substrate 500 may include a third circuit pattern layer 523 disposed on the second insulating layer 512 .
  • the semiconductor package substrate 500 may include a fourth circuit pattern layer 524 disposed on the lower surface of the third insulating layer 513.
  • the third circuit pattern layer 523 disposed on the uppermost side among the circuit pattern layers may include an electrode pattern on which a semiconductor device is disposed.
  • the semiconductor package substrate may be disposed on the electrode pattern of the third circuit pattern layer 523 and include a protrusion 590 that protrudes toward the semiconductor device.
  • the protrusion 590 may be referred to as a bump.
  • the protrusion 590 may also be referred to as a post.
  • the protrusion 590 may also be referred to as a pillar.
  • TC Thermal Compression bonding
  • the protrusion 590 may function to improve alignment between the electrode pattern and the terminal of the semiconductor device and to prevent diffusion of the conductive adhesive.
  • the volume of the conductive adhesive disposed on each of the plurality of terminals can be reduced, thereby preventing electrical short-circuit problems due to the fine pitch of the terminals.
  • solder may be used as the conductive adhesive, but is not limited thereto.
  • the circuit pattern layers 521, 522, 523, and 524 are selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It may contain at least one metal material.
  • the circuit pattern layers 521, 522, 523, and 524 are made of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (which have excellent bonding properties). It may include a paste or solder paste containing at least one metal material selected from Zn).
  • the circuit pattern layers 521, 522, 523, and 524 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.
  • the circuit pattern layers 521, 522, 523, and 524 may have a thickness ranging from 10 ⁇ m to 25 ⁇ m.
  • the thickness of the circuit pattern layers 521, 522, 523, and 524 may refer to the thickness in the vertical direction.
  • the thickness of the circuit pattern layers 521, 522, 523, and 524 is less than 10 ⁇ m, the resistance of the circuit pattern layers 521, 522, 523, and 524 may increase, and the allowable current of the transmittable signal may decrease. there is. Additionally, if the thickness of the circuit pattern layers 521, 522, 523, and 524 exceeds 25 ⁇ m, it may be difficult to miniaturize the circuit pattern layers 521, 522, 523, and 524. If the thickness of the circuit pattern layers 521, 522, 523, and 524 exceeds 25 ⁇ m, the thickness of the insulating layer 510 must increase correspondingly, and the insulating function and/or protection of the insulating layer as described above. In order to function, the thickness of each insulating layer must be thick. Accordingly, the thickness of the semiconductor package substrate and the semiconductor package may increase, and it may become difficult to alleviate the bending of the semiconductor package substrate.
  • the circuit pattern layers 521, 522, 523, and 524 may include a pad connected to a through electrode of the semiconductor package substrate 500 and at least one electrode pattern connected to an external substrate or semiconductor device. Additionally, the circuit pattern layers 521, 522, 523, and 524 may include traces of signal transmission lines connected to pads or electrode patterns.
  • circuit pattern layers 521, 522, 523, and 524 are manufactured using typical semiconductor package substrate manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP ( This is possible using the Semi Additive Process (Semi Additive Process) method, and detailed explanations are omitted here.
  • the semiconductor package substrate 500 may include a first through electrode 530 that penetrates the first insulating layer 511 .
  • the first insulating layer 511 may include a first through hole penetrating the upper and lower surfaces.
  • the first through electrode 530 may be provided to fill at least a portion of the first through hole of the first insulating layer 511.
  • the semiconductor package substrate 500 has an insulating member 540 that fills the remaining portion of the first through hole of the first insulating layer 511, and when the first through electrode 530 does not entirely fill the first through hole, 1 It may be arranged to improve the flatness of the circuit pattern layer 521, and the first through electrode 530 may be arranged to be located between the insulating member 540 and the first insulating layer 511.
  • the insulating member 540 may be referred to as a hole plugging layer.
  • the insulating member 540 may include an insulating material.
  • the insulating member 540 may be a paste made of insulating ink material.
  • the insulating member 540 may be plugging ink.
  • the embodiment is not limited to this.
  • the insulating member 540 may include a conductive material.
  • the insulating member 540 may include a conductive paste containing conductive metal powder.
  • the semiconductor package substrate 500 may include a second through electrode 550 that penetrates the second insulating layer 512 .
  • the second insulating layer 512 may include a second through hole penetrating the upper and lower surfaces.
  • the second through electrode 550 may be provided to entirely fill the second through hole of the second insulating layer 512.
  • the semiconductor package substrate 500 may include a third through electrode 560 that penetrates the third insulating layer 513.
  • the third insulating layer 513 may include a third through hole penetrating the upper and lower surfaces.
  • the third through electrode 560 may be provided to entirely fill the third through hole of the third insulating layer 513.
  • the first through electrode 530, second through electrode 550, and third through electrode 560 may have different shapes.
  • the first through hole, the second through hole, and the third through hole may have different shapes.
  • the inclination of the first through electrode 530 surrounding the insulating member 540 disposed in the first through hole, the inclination of the second through electrode 550, and the inclination of the third through electrode 560 are each other.
  • the slope of the side of the first through electrode 530, the side of the second through electrode 550, and the side of the third through electrode 560 may be different from each other.
  • the vertical cross-sectional shape of the first through electrode 530, the vertical cross-sectional shape of the side of the second through electrode 550, and the vertical cross-sectional shape of the third through electrode 560 may be different from each other.
  • the inner wall of the first through hole may include a plurality of concave portions and convex portions, and the concave portions and convex portions may be provided in a structure in which the concave portions and convex portions are alternately stacked along the vertical direction.
  • the convex portion refers to an area that protrudes and/or is convex toward the horizontal center of the first through hole
  • the concave portion refers to a concave area in the opposite direction.
  • the second through hole may have a shape whose width decreases from the top to the bottom. Additionally, the second through hole may be arranged not to include a plurality of concave portions and convex portions, unlike the first through hole.
  • the third through hole may have a shape whose width increases from the top to the bottom. Additionally, the third through hole may be arranged not to include a plurality of concave portions and convex portions. Additionally, the third through hole may have a symmetrical shape with the second through hole with respect to the first insulating layer 511, but is not limited thereto.
  • the vertical thickness of the first through electrode 530, the depth of the first through hole, and the vertical thickness of the insulating member 540 may correspond to the thickness of the first insulating layer 511. Accordingly, the vertical thickness of the first through electrode 530, the depth of the first through hole, and the vertical thickness of the insulating member 540 may be 250 ⁇ m to 1200 ⁇ m.
  • a first through hole is formed in the first insulating layer 511 using a laser device, while minimizing the difference between the maximum and minimum widths of the first through hole in the vertical direction.
  • the vertical direction refers to the thickness direction from the top to the bottom of the first insulating layer 511.
  • a through hole is formed in which the difference between the maximum and minimum widths of the first insulating layer 511 is minimized using a laser device rather than a drill machine device.
  • the embodiment uses a plurality of coordinate codes (eg, T-code) to form the first through hole in the first insulating layer 511. That is, when using a laser device, in the comparative example, a through hole was formed in the core layer corresponding to the first insulating layer 511 using only one coordinate code. Accordingly, in the process of forming a through hole, it is difficult to change the laser process conditions during the process. Therefore, when a through hole is formed by a laser device using only one coordinate code, the through hole has an hourglass shape in which the width gradually decreases from the top and/or bottom to the center, and thus the minimum width is equal to the maximum width. had less than 50%.
  • T-code coordinate codes
  • the first through hole is formed in the first insulating layer 511 using at least two coordinate codes.
  • a portion of the first through hole is formed in the first insulating layer 511 using the first coordinate code. Thereafter, in the embodiment, the remaining part of the first through hole connected to the part of the first through hole is formed in the first insulating layer 511 using the second coordinate code. Through this, the embodiment can finally form a first through hole penetrating the first insulating layer 511.
  • the embodiment uses two coordinate codes, unlike the comparative example, it is possible to change the laser process conditions during the forming process of the first through hole.
  • the embodiment it is possible to form a first through hole with a minimized difference between the maximum and minimum widths in the first insulating layer 511 corresponding to the core layer using a laser device.
  • the embodiment includes a first process of forming a portion of the first through hole in the first insulating layer 511 using a first coordinate code, and a first process of forming a portion of the first through hole in the first insulating layer 511 using the second coordinate code.
  • a second process is performed to form the remaining part connected to part of the through hole.
  • a first mask having an opening of the first size is used to form a part of the first through hole.
  • the first size may correspond to the target size that the first through hole should have.
  • the embodiment forms a portion of the first through hole corresponding to the target size on each of the upper and lower surfaces of the first insulating layer 511 using the first mask.
  • the embodiment proceeds with a second process using a second coordinate code after a portion of the first through hole is formed.
  • a second mask having an opening of a second size different from the first size is used to form the remaining part of the first through hole.
  • the second size is smaller than the first size.
  • the energy intensity of the laser is increased in the second process of forming the remaining part of the first through hole using the second mask.
  • the embodiment irradiates the first insulating layer 511 with a laser having a first energy intensity.
  • the embodiment irradiates the first insulating layer 511 with a laser having a second energy intensity greater than the first energy intensity.
  • the size of the opening provided in the second mask is smaller than the target size of the first through hole. That is, in the embodiment, a laser with a relatively low energy intensity is irradiated through the opening of the first mask having a first size, and a laser with a relatively large energy intensity is irradiated through the opening of the second mask with a second size smaller than the first size.
  • the embodiment can minimize the difference between the maximum width and the minimum width in the entire vertical area of the first through hole.
  • the size of the opening of the second mask used when irradiating a laser with a relatively high energy intensity is smaller than the target size, and accordingly, the embodiment can prevent the size of the first through hole from expanding.
  • the semiconductor package substrate 500 of the embodiment includes a protective layer.
  • the protective layer may also be referred to as an insulating layer or a resist layer.
  • the protective layer refers to the insulating layer of the outermost layer of the semiconductor package substrate.
  • the protective layer functions to protect the surface of the outermost layer of the semiconductor package substrate 500 and prevents short circuits between adjacent conductive adhesives. Accordingly, the protective layer can also be functionally referred to as a ‘protective layer.’ For example, when a conductive adhesive is used as solder, the protective layer may be referred to as a solder resist.
  • the protective layer includes a first protective layer 570 disposed on the upper surface of the second insulating layer 512.
  • the first protective layer 570 includes at least one first opening 571 that vertically overlaps a portion of the third circuit pattern layer 523.
  • the first opening 571 may be provided to correspond to an area where a conductive adhesive such as a connection portion is to be placed.
  • the protective layer includes a second protective layer 580 disposed on the lower surface of the third insulating layer 53.
  • the second protective layer 580 includes at least one second opening 581 that vertically overlaps the fourth circuit pattern layer 524.
  • the second opening 581 may be provided to correspond to an area where a conductive adhesive such as a connection portion is to be placed.
  • the first protective layer 570 and the second protective layer 580 may include an organic polymer material.
  • the first protective layer 570 and the second protective layer 580 may be solder protective layers.
  • the first protective layer 570 and the second protective layer 580 may include an epoxy acrylate-based resin.
  • the first protective layer 570 and the second protective layer 580 may include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc.
  • the embodiment is not limited to this.
  • the first protective layer 570 and the second protective layer 580 may include any one of a photo solder protective layer, a coverlay, and a polymer material.
  • the first protective layer 570 and the second protective layer 580 may have a thickness of 1 ⁇ m to 20 ⁇ m. At this time, when the thickness of the first protective layer 570 and the second protective layer 580 exceeds 20 ⁇ m, the overall thickness of the semiconductor package substrate and the overall thickness of the semiconductor package may increase, and as the stress increases, The warpage of the semiconductor package substrate may increase.
  • the circuit pattern layer may not be stably protected. If the thickness of the first protective layer 570 and the second protective layer 580 is less than 1 ⁇ m, the electrical reliability of the semiconductor package substrate and the semiconductor package may deteriorate.
  • the first through hole, the first through electrode, and the insulating member formed in the first insulating layer 511 according to the embodiment will be described in more detail.
  • FIG. 4 is a cross-sectional view for explaining the first insulating layer of the embodiment
  • FIG. 5 is a cross-sectional view showing the first through hole provided in the first insulating layer of FIG. 4
  • FIG. 6 is a cross-sectional view showing the first through hole provided in the first insulating layer of FIG. 5.
  • 1 is a cross-sectional view showing a through electrode and an insulating member
  • FIG. 7 is a view showing the layer structure of the first through electrode and the first circuit pattern layer in the first embodiment
  • FIG. 8 is a view showing the first through electrode and the first circuit pattern layer in the second embodiment. It is a diagram showing the layer structure of the circuit pattern layer
  • FIG. 9 is an optical micrograph of an actual product including a first through hole, a first through electrode, and an insulating member according to an embodiment.
  • the first through electrode 530, the first circuit pattern layer 521, the second circuit pattern layer 522, the first through electrode 530, and the insulating member according to the embodiment. (540) will be explained in detail.
  • the vertical thickness T1 of the first insulating layer 511 in the embodiment may satisfy the range of 250 ⁇ m to 1200 ⁇ m as described above.
  • the first insulating layer 511 may include a resin 511a and reinforcing fibers 511b disposed within the resin 511a.
  • the reinforcing fibers 511b may include a plurality of fibers arranged in different directions within the resin 511a.
  • the reinforcing fibers 511b include first fibers arranged in a first horizontal direction and second fibers arranged in a second horizontal direction perpendicular to the first horizontal direction.
  • the wave-shaped fiber may be the first fiber
  • the point-shaped fiber may be the second fiber.
  • the first fiber of the reinforcing fiber 511b can be called a warp yarn.
  • the second fiber of the reinforcing fiber 511b can be called a fill yarn.
  • the reinforcing fiber 511b may be made of a bundle of filaments that are long glass fibers. Additionally, the first fibers and second fibers of the reinforcing fibers 511b may be arranged in the first and second horizontal directions that intersect each other within the resin 511a, but are not limited thereto.
  • Reinforcement fibers 511b may be divided into multiple groups.
  • the reinforcing fibers 511b may be divided into a plurality of groups spaced apart from each other in the vertical direction within the resin 511a of the first insulating layer 511.
  • the reinforcing fibers 511b may include first to third groups separated from each other along the vertical direction between the upper surface 511U and the lower surface 511L of the first insulating layer 511.
  • Each of the first to third groups of reinforcing fibers is arranged in the horizontal direction within the first insulating layer 511.
  • the first to third groups of reinforcing fibers are spaced apart from each other in the vertical direction within the first insulating layer 511.
  • the drawing shows that the reinforcing fibers 511b are arranged in three groups in the first insulating layer 511, but the present invention is not limited thereto.
  • the number of groups of reinforcing fibers 511b may be determined based on the vertical thickness of the first insulating layer 511.
  • the reinforcing fibers 511b may be divided into three groups and disposed in the first insulating layer 511.
  • the reinforcing fibers 511b are divided into four groups and are attached to the first insulating layer 511. can be placed.
  • the first insulating layer 511 may be divided into a plurality of regions in the vertical direction.
  • the first insulating layer 511 may include a first region 511R1 that does not include the reinforcing fibers 511b and a second region 511R2 that includes the reinforcing fibers 511b in the vertical direction. .
  • the second regions 511R2 of the first insulating layer 511 are spaced apart from each other with the first region 511R1 in between. may include at least three sub-areas.
  • the first region 511R1 of the first insulating layer 511 has 1-1 to 1-4 sub-regions 511R11, 511R12 from a position adjacent to the top surface 511U of the first insulating layer 511. , 511R13, 511R14).
  • the second region 511R2 of the first insulating layer 511 is the 2-1st to 2nd sub-regions 511R11, 511R12, 511R13, and 511R14, respectively. It may include -3 sub-regions 511R21, 511R22, and 511R23.
  • the second region 511R2 is spaced further from the upper and lower surfaces 511U and 511L of the first insulating layer 511 than the first region 511R1. can be located. This is because, when the reinforcing fibers 511b are exposed to the upper surface 511U or the lower surface 511L of the first insulating layer 511, the physical and electrical reliability of the circuit pattern layers are deteriorated.
  • the first through hole TH1 is formed through at least two coordinate codes using a laser device, a concave portion and a concave portion along the vertical direction are formed on the inner wall of the first through hole TH1.
  • the convex portions are arranged alternately.
  • the difference between the minimum and maximum widths of the first through hole TH1 having the concave portion and the convex portion in the embodiment is the difference between the minimum width and the maximum width of the first through hole TH1 formed through one coordinate code using a conventional laser equipment. It is small compared to the difference between the minimum and maximum width.
  • the concave portion may be provided in the 1-1st to 1-4th sub-regions 511R11, 511R12, 511R13, and 511R14, and the convex portion may be provided in the 2-1st to 2-3rd subregions 511R21, 511R22, and 511R23. It can be provided in .
  • the etching rate of the resin layer composed only of the resin 511a in the first insulating layer 511 is greater than the etching rate of the layer provided with the reinforcing fibers 511b, and for this reason, the concave portion and the convex portion may be provided at the above-described positions.
  • it is not limited to this.
  • the inner wall of the first through hole TH1 includes a first inner wall IW1 and a second inner wall IW2.
  • the second inner wall (IW2) of the first through hole (TH1) may be provided as a convex portion that is convex toward the inside of the first through hole (TH1) compared to the first inner wall (IW1).
  • the inner wall of the first insulating layer 511 constituting the first through hole TH1 of the embodiment has a second inner wall IW2 that is convex toward the first through hole TH1 with respect to the first inner wall IW1.
  • the first inner wall IW1 exemplarily has a vertical slope, but is not limited thereto and may be provided as a concave portion that is concave toward the outer surface of the first insulating layer 511 .
  • the second inner wall IW2 of the embodiment may include a plurality of convex portions spaced apart from each other in the vertical direction.
  • the convex portion may be an area where the width increases or decreases.
  • the convex portion may be provided as a curved surface with a certain curvature along the vertical direction, but is not limited to this.
  • the inner walls (IW1, IW2) of the first through hole (TH1) have convex portions and concave portions to enable uniform placement of the first through electrode in the first through hole (TH1), thereby reducing the impedance.
  • Stable matching is possible and voltage drop or current and/or signal loss can be reduced.
  • reliability against thermal stress can be improved. That is, by arranging the horizontal width of the first through electrode to be thicker than the thickness of the conventional vertical first through electrode 530 shown in FIG. 3A, voltage drop or current and/or signal loss can be reduced. , it can be a more advantageous structure for heat dissipation.
  • the first inner wall IW1 may be formed in the first region 511R1 of the first insulating layer 511 in the first through hole TH1, and the second inner wall IW2 may be formed in the first through hole TH1. It may be formed in the second region 511R2 of the first insulating layer 511.
  • the first through hole TH1 is formed in the first insulating layer 511 with a thickness T1 of 250 ⁇ m or more using a laser device.
  • the first insulating layer 511 of the embodiment corresponds to the inner wall of the second region 511R2 of the first insulating layer 511 where the reinforcing fibers 511b are disposed, and is convex toward the first through hole TH1. It may include a second inner wall (IW2). Additionally, the first inner wall (IW1) and the second inner wall (IW2) may each include a plurality of sub-parts.
  • the first inner wall (IW1) has 1-1 to 1-4 sub-parts (IW1-1, IW1-2, IW1- 3, IW1-4) may be included.
  • the second inner wall (IW2) includes the 2-1 to 2-3 sub parts disposed between the 1-1 to 1-4 sub parts (IW1-1, IW1-2, IW1-3, and IW1-4), respectively. May include parts (IW2-1, IW2-2, IW2-3).
  • the number of sub-parts of the second inner wall IW2 may correspond to the number of groups of reinforcing fibers 511b provided in the first insulating layer 511. Accordingly, the number of sub-parts of the second inner wall IW2 may be more than 2, more than 3, more than 4, or more than 5.
  • the first through hole TH1 has a first width W1 in the horizontal direction in an area corresponding to the 1-1 subpart IW1-1 of the first inner wall IW1 and has a first width W1 in the second inner wall IW2. It has a second width (W2) smaller than the first width (W1) in the area corresponding to the 2-1 subpart (IW2-1).
  • the first through hole TH1 has a first width W1 again in an area corresponding to the 1-2 subpart IW1-2 of the first inner wall IW1 and has a first width W1 in the area corresponding to the 1-2 subpart IW1-2 of the first inner wall IW1.
  • the first through hole TH1 has a first width W1 again in an area corresponding to the 1-3 subpart IW1-3 of the first inner wall IW1 and then has a first width W1 in the area corresponding to the 1-3 subpart IW1-3 of the first inner wall IW1. It has a second width (W2) smaller than the first width (W1) in the area corresponding to the 2-3 subpart (IW2-3).
  • the first insulating layer 511 has a first width W1 again in the area corresponding to the 1-4 subpart (IW1-4) of the first inner wall (IW1).
  • the first through hole TH1 is connected to the 1-1 to 1-4 sub-parts (IW1-1, IW1-2, IW1-3, IW1-4) of the first inner wall (IW1). ) may not all have the same first width (W1) in each region corresponding to ), and the 2-1st to 2-3rd subparts (IW2-1, IW2-2, IW2) of the second inner wall (IW2) In -3), they may not all have the same second width (W2).
  • the first insulating layer 511 of the embodiment includes reinforcing fibers 511b vertically spaced in groups of more than 2, more than 3, more than 4, or more than 5.
  • the inner wall of the first insulating layer 511 where the first through hole TH1 is formed includes a plurality of convex portions that are convex toward the center of the first through hole TH1 in the area where the reinforcing fibers 511b are disposed.
  • the plurality of convex portions may be spaced apart from each other in the vertical direction in the first insulating layer 511 . Additionally, each convex portion may extend from the inner wall of the first through hole TH1 along a circumferential direction of the inner wall of the first through hole TH1.
  • the first width W1 of the first through hole TH1 may mean the width in the horizontal direction of the area having the maximum width in the entire area in the vertical direction.
  • the second width W2 of the first through hole TH1 may mean the horizontal width of the area having the minimum width in the entire vertical area.
  • the second width was less than 50% of the first width.
  • the second width W2 of the embodiment may satisfy a range of 55% to 95% of the first width W1.
  • the second width W2 is less than 55% of the first width W1
  • the difference in the width of the through hole increases, and as a result, plating characteristics in the plating process of filling the through hole may deteriorate.
  • the difference in width is large, the difference in plating growth speed during the plating process also increases, and accordingly, a void area of an empty space that is not filled with a metal material may exist inside the through hole.
  • plating characteristics in the plating process may be deteriorated due to the absence of a plating bridge.
  • first through electrode 530 and the insulating member 540 of the embodiment may be disposed in the first through hole TH1.
  • the first through electrode 530 may contact the inner walls (IW1, IW2) of the first insulating layer 511 including the first through hole (TH1).
  • the insulating member 540 may be disposed inside the first through electrode 530 within the first through hole TH1.
  • the first through electrode 530 may be provided to surround the outside of the insulating member 540 within the first through hole TH1.
  • the first through electrode 530 may have a certain thickness and may be disposed on the inner wall of the first insulating layer 511 including the first through hole TH1.
  • the thickness of the first through electrode 530 may refer to the distance of the first through electrode 530 in the horizontal direction. Specifically, the thickness of the first through electrode 530 may mean the width of the first through electrode 530 in the horizontal direction.
  • the first through electrode 530 may be divided into a plurality of parts.
  • the first through electrode 530 may include a concave portion disposed on the first inner wall IW1 corresponding to the first region 511R1 of the first insulating layer 511.
  • the first through electrode 530 may include a convex portion disposed on the second inner wall IW2 corresponding to the second region 511R2 of the first insulating layer 511.
  • the side surface of the first through electrode 530 having the concave portion and the convex portion may have a step in the vertical direction. Specifically, the concave portion of the first through electrode 530 does not overlap the reinforcing fiber 511b in the horizontal direction.
  • the convex portion of the first through electrode 530 overlaps the reinforcing fiber 511b in the horizontal direction.
  • the convex portion of the first through electrode 530 corresponds to the convex portion provided on the second inner wall (IW2) of the first insulating layer 511.
  • the concave portion of the first through electrode 530 corresponds to the concave portion provided in the first inner wall (IW1) of the first insulating layer 511.
  • the first through electrode 530 may have a shape in which concave portions and convex portions are alternately arranged along the vertical direction.
  • the concave portion of the first through electrode 530 corresponds to the concave portion provided in the first inner wall (IW1) of the first through hole (TH1), and the convex portion of the first through electrode 530 corresponds to the concave portion of the first through hole (TH1). It appears to correspond to the convex portion provided on the second inner wall (IW2) of TH1), but is not limited to this.
  • the first through electrode 530 may have a third thickness W3 in the horizontal direction in the area where the concave portion is provided. Additionally, the first through electrode 530 may have a fourth thickness W4 in the horizontal direction in the area where the convex portion is provided. At this time, the third thickness W3 may correspond to the fourth thickness W4. For example, the third thickness W3 and the fourth thickness W4 may be equal to each other. That is, the first through electrode 530 may have the same thickness in the horizontal direction in each of the areas provided with the concave portion and the area provided with the convex portion. Here, having the same thickness may mean that the difference in thickness in the horizontal direction between the area provided with the concave portion and the area provided with the convex portion is 3 ⁇ m or less.
  • the horizontal thicknesses W3 and W4 of the first through electrode 530 may range from 10 ⁇ m to 25 ⁇ m.
  • the resistance of the first through electrode 530 may increase and the allowable current of a signal that can be transmitted may decrease. Additionally, if the horizontal thickness of the first through electrode 530 is less than 10 ⁇ m, electrical characteristics may deteriorate. For example, when the horizontal thickness of the first through electrode 530 is less than 10 ⁇ m, the reinforcing fibers 511b exposed through the first through hole TH1 are stably stabilized by the first through electrode 530. It may not be covered. In addition, when the reinforcing fibers 511b are not covered by the first through electrode 530, a problem in which electrical properties are deteriorated due to the reinforcing fibers 511b may occur.
  • the horizontal thickness of the first through electrode 530 exceeds 25 ⁇ m, a concave portion of the first through electrode 530 is formed due to a difference in plating speed growth in the process of forming the first through electrode 530.
  • the thickness difference between the exposed area and the area provided with the convex portion of the first through electrode 530 may increase.
  • the insulating member 540 may include a region whose width changes from the upper surface to the lower surface.
  • the insulating member 540 may include a plurality of concave portions that are concave inward and a plurality of convex portions that are convex toward the first through electrode 530 .
  • the insulating member 540 may be provided with a plurality of concave portions spaced apart in the vertical direction. Additionally, the convex portion of the insulating member 540 may be provided between each of the plurality of concave portions of the insulating member 540.
  • the insulating member 540 includes a first part 541 having a fifth width W5, and a second part having a sixth width W6 smaller than the fifth width W5 ( 542) may be included. Additionally, the side surface of the first portion 541 of the insulating member 540 may be provided with a convex portion that protrudes toward the first through electrode 530 . Additionally, a side surface of the second portion 542 of the insulating member 540 may be provided with a concave portion that is concave inward.
  • the inner wall of the first through hole TH1 of the first insulating layer 511 includes a convex portion corresponding to the reinforcing fiber 511b.
  • the insulating member 540 may also have a concave portion corresponding to the convex portion of the first through hole TH1.
  • the insulating member 540 may include a convex portion provided in the first through hole TH1 and a concave portion that overlaps in the horizontal direction.
  • the insulating member 540 may have a convex portion that overlaps the concave portion provided in the first through hole TH1 in the horizontal direction.
  • the side surface of the first portion 541 of the insulating member 540 is shown to be vertical, but the present invention is not limited to this.
  • the side surface of the first portion 541 may be provided with a curved convex portion that is convex toward the first through electrode 530.
  • a plurality of first portions 541 of the insulating member 540 may be provided and spaced apart from each other in the vertical direction.
  • the first part 541 of the insulating member 540 includes a 1-1 part 541-1, a 1-2 part 541-2, and a 1-1 part 541-1. It may include part 3 (541-3) and first to fourth parts (541-4).
  • the second part 542 of the insulating member 540 may include a 2-1 part 542-1, a 2-2 part 542-2, and a 2-3 part 542-3. You can.
  • the 2-1 part 542-1, the 2-2 part 542-2, and the 2-3 part 542-3 may be parts that overlap the reinforcing fiber 511b in the horizontal direction.
  • the 1-1 part (541-1), the 1-2 part (541-2), the 1-3 part (541-3), and the 1-4 part (541-4) are reinforced fibers (511b). ) may be a part that does not overlap in the horizontal direction.
  • the 2-1 part (542-1), the 2-2 part (542-2), and the 2-3 part (542-3) are formed by the reinforcing fibers (511b). 1), it may have a smaller width than the 1-2 part 541-2, the 1-3 part 541-3, and the 1-4 part 541-4.
  • the first through electrode 530 may be composed of multiple layers.
  • the first through electrode 530 is used to form the first circuit pattern layer 521 and the second circuit pattern layer 522.
  • the first through electrode 530 may have a layer structure corresponding to the layers constituting the first circuit pattern layer 521 and the second circuit pattern layer 522.
  • the first circuit pattern layer 521 may include a plurality of metal layers.
  • the first circuit pattern layer 521 includes a first metal layer 521-1 disposed on the first insulating layer 511, and a second metal layer 521 disposed on the first metal layer 521-1. -2), and a third metal layer 521-3 disposed on the second metal layer 521-2.
  • the first metal layer 521-1 of the first circuit pattern layer 521 may refer to a copper foil layer attached to the surface of the first insulating layer 511.
  • the second metal layer 521-2 of the first circuit pattern layer 521 may be a plating layer formed on the first metal layer 521-1 through electroless plating.
  • the second metal layer 521-2 of the first circuit pattern layer 521 may be a chemical copper plating layer.
  • the third metal layer 521-3 of the first circuit pattern layer 521 may be a plating layer formed by electrolytic plating using the second metal layer 521-2 as a seed layer.
  • the third metal layer 521-3 of the first circuit pattern layer 521 may be an electrolytic plating layer.
  • the third metal layer 521-3 of the first circuit pattern layer 521 in the first embodiment may be disposed on the upper surface of the insulating member 540.
  • the third metal layer 521-3 of the first circuit pattern layer 521 may be formed by performing electrolytic plating multiple times.
  • the third metal layer 521-3 of the first circuit pattern layer 521 in the second embodiment may not cover the top surface of the insulating member 540.
  • the third metal layer 521-3 of the first circuit pattern layer 521 may be formed by performing one electrolytic plating process. At this time, the third metal layer 521-3 of the first circuit pattern layer 521 may not overlap the top surface of the insulating member 540 in the vertical direction.
  • the first through electrode 530 is disposed on the fourth metal layer 530-1 and the fourth metal layer 530-1 corresponding to the second metal layer 521-2 of the first circuit pattern layer 521. and may include a fifth metal layer 530-2 corresponding to the third metal layer 521-3 of the first circuit pattern layer 521.
  • the fourth metal layer 530-1 of the first through electrode 530 may be provided on the inner wall of the first insulating layer 511 including the first through hole TH1. Additionally, the fifth metal layer 530-2 of the first through electrode 530 may be disposed between the fourth metal layer 530-1 of the first through electrode 530 and the insulating member 540.
  • the thicknesses W4 and W5 in the horizontal direction of the first through electrode 530 are the horizontal directions of the fourth metal layer 530-1 and the fifth metal layer 530-2 of the first through electrode 530. It can mean the sum of the thicknesses.
  • the thickness of the first insulating layer 511 in the vertical direction may be 400 ⁇ m or more, and accordingly, the reinforcing fibers 511b are divided into four groups in the vertical direction. can be placed. Accordingly, the inner wall of the first through hole TH1 of the first insulating layer 511 may be provided with protruding portions corresponding to each of the four groups of reinforcing fibers 511b.
  • the first through electrode 530 disposed on the sidewall of the first through hole TH1 includes one side facing the insulating member 540 and the other side facing the first insulating layer 511. , one surface includes a convex portion protruding toward the insulating member 540 and a concave portion concave toward the first through hole TH1.
  • the first through electrode 530 shown in FIG. 9 shows one cross section, and one side of the first through electrode 530 is arranged to surround the insulating member 540.
  • the concave portions of the first through electrodes 530 may face each other and overlap along the horizontal direction, and the convex portions of the first through electrodes 530 may face each other and overlap along the horizontal direction. Additionally, the convex portions and concave portions may have a structure in which the convex portions and concave portions are alternately arranged along the vertical direction. Through this, the thickness of the first penetrating electrode 530 in the horizontal direction can be placed relatively uniformly, and it can be placed thicker than in the process using drill machine equipment.
  • the other surface of the first penetrating electrode 530 may have a different shape from the one surface. That is, one surface on which the concave portion of the first through electrode 530 is disposed and the other surface overlapping along the horizontal direction may not have a concave surface or may have different curvatures. Referring to FIG. 9, the curvature of one surface of the first through electrode 530 and the curvature of the other surface overlapping the concave surface in the horizontal direction are shown to be different from each other. Through this, the bonding force between the insulating member 540 and the first through electrode 530 can be improved, heat dissipation characteristics can be improved, and mechanical reliability of the semiconductor package substrate can be improved by controlling stress.
  • the convex portion of one surface of the first through electrode 530 may have a different curvature from the convex portion of the other surface that overlaps the convex portion in the horizontal direction. Since the convex portion on the other side may be arranged in a structure that surrounds the glass fiber differently from the convex portion on one side, its curvature may be different from the convex portion on one side. Specifically, when the first through electrode 530 surrounds a glass fiber, the horizontal thickness of the first through electrode 530 must be 10 ⁇ m or more to prevent the problem of deterioration of electrical characteristics. Therefore, the convex portion on the other side surrounds the glass fiber, and in order to prevent electrical properties from being deteriorated, the convex portion on one side and the convex portion on the other side can be arranged to have different curvatures.
  • FIGS. 10 to 14 are diagrams showing part of a method for manufacturing a semiconductor package substrate according to an embodiment, in process order. Hereinafter, a process for forming the first through hole TH1 in the first insulating layer 511 will be described.
  • a first insulating layer 511 is prepared.
  • the first insulating layer 511 may be CCL.
  • copper foil layers may be disposed on both sides of the first insulating layer 511, respectively.
  • the copper foil layer may include a first metal layer 521-1 of the first circuit pattern layer 521 and a first metal layer 522-1 of the second circuit pattern layer 522.
  • the embodiment may proceed with a process of forming the first through hole TH1 in the first insulating layer 511.
  • the first through hole TH1 may be formed through multiple laser processes using multiple coordinate codes.
  • the first insulating layer 511 has a vertical thickness of 250 ⁇ m or more. Accordingly, it may be difficult to form the first through hole TH1 penetrating the first insulating layer 511 only on one side of the first insulating layer 511 . Accordingly, the embodiment may proceed with a process of initially forming a portion of the first through hole TH1 on the upper side of the first insulating layer 511.
  • the embodiment proceeds with a process of forming a portion of the first through hole TH1 on the upper side of the first insulating layer 511 using the first coordinate code (T-code A).
  • the first coordinate code (T-code A) may include location information (TCI) corresponding to the location where the first through hole (TH1) will be formed.
  • a portion of the first through hole TH1 may be formed by irradiating a laser from the upper side of the first insulating layer 511 using the first coordinate code (T-code A).
  • a first mask having an opening of the first size may be used.
  • a laser of the first laser energy intensity is irradiated through the opening of the first mask to form the first portion HP1, which is part of the first through hole TH1, on the upper side of the first insulating layer 511. The process can proceed.
  • a second part (HP2) connected to the first part (BP1) is formed on the upper side of the first insulating layer 511 using a second coordinate code (T-code B).
  • the forming process can proceed.
  • the second coordinate code (T-code B) may include location information (TCI) corresponding to the first coordinate code (T-code A).
  • a second mask having an opening of a second size smaller than the first size is used. Available.
  • a laser of a second energy intensity greater than the first energy intensity is irradiated through the opening of the second mask, and the second portion of the first through hole TH1 is on the upper side of the first insulating layer 511 ( HP2) can be formed.
  • the horizontal widths of the first portion HP1 and the second portion HP2 of the first through hole TH1 may be substantially the same.
  • the first insulating layer 511 includes reinforcing fibers 511b. Accordingly, in the first portion HP1 and the second portion HP2 of the first through hole TH1, protrusions may be provided in areas that overlap the reinforcing fibers 511b in the horizontal direction.
  • the embodiment proceeds with a process of forming the remaining portion of the first through hole TH1 on the lower side of the first insulating layer 511 using the first coordinate code (T-code A).
  • the embodiment applies the first laser process conditions according to the first coordinate code (T-code A), and perpendicular to the first part (HP1) and the second part (HP2) of the first through hole (TH1).
  • a third portion (HP3) of the first through hole (TH1) aligned in the direction may be formed.
  • the embodiment forms the fourth part (HP4) connected to the third part (HP3) of the first through hole (TH1) using the second coordinate code (T-code B).
  • the process can proceed.
  • the fourth part HP4 is connected to the second part HP2, and thus the final first through hole TH1 can be formed.
  • the semiconductor package substrate having the characteristics of the above-described invention when used in IT devices or home appliances such as smartphones, server computers, and TVs, functions such as signal transmission or power supply can be stably performed.
  • a semiconductor package substrate having the characteristics of the present invention when a semiconductor package substrate having the characteristics of the present invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can prevent problems with leakage current or electrical short circuits between terminals. It can solve the problem of electrical opening of the terminal supplying the semiconductor chip. Additionally, if it is responsible for the function of signal transmission, the noise problem can be solved.
  • the semiconductor package substrate having the characteristics of the above-described invention can maintain the stable function of IT devices or home appliances, so that the entire product and the semiconductor package substrate to which the present invention is applied can achieve functional unity or technical interoperability with each other. .
  • the semiconductor package substrate having the characteristics of the above-described invention When the semiconductor package substrate having the characteristics of the above-described invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of the signal transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside, The stability of the transportation device can be further improved by solving the problem of leakage current, electrical short-circuiting between terminals, or electrical opening of the terminal supplying the semiconductor chip. Accordingly, the transportation device and the semiconductor package substrate to which the present invention is applied can achieve functional unity or technical interoperability with each other. Furthermore, when the semiconductor package substrate having the characteristics of the above-described invention is used in a transportation device such as a vehicle, a high-current signal required by the vehicle can be transmitted at high speed, thereby improving the safety of the transportation device. Furthermore, it enables normal operation of the semiconductor package substrate and the semiconductor package including it even in unexpected situations that occur in various driving environments of transportation devices, thereby protecting drivers safely.

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Abstract

A semiconductor package substrate according to an embodiment comprises: an insulating layer having a top surface and a bottom surface; and a through electrode penetrating the top surface and the bottom surface of the insulating layer, wherein a side surface of the through electrode includes a concave part and a convex part alternately provided in a vertical direction. In addition, a semiconductor package substrate according to another embodiment comprises: an insulating layer having a top surface and a bottom surface; and a through-hole penetrating the top surface and the bottom surface of the insulating layer, wherein a side wall of the through-hole includes a concave part and a convex part alternately provided in the vertical direction.

Description

반도체 패키지 기판 및 이를 포함하는 반도체 패키지Semiconductor package substrate and semiconductor package including the same
실시 예는 반도체 패키지 기판 및 이를 포함하는 반도체 패키지에 관한 것이다.The embodiment relates to a semiconductor package substrate and a semiconductor package including the same.
전기/전자 제품의 고성능화가 진행됨에 따라, 한정된 크기의 기판에 더 많은 수의 패키지를 부착하기 위한 기술들이 제안 및 연구되고 있다. As the performance of electrical/electronic products progresses, technologies for attaching a greater number of packages to a limited-sized substrate are being proposed and researched.
일반적인 반도체 패키지는 다수의 칩이 배치된 구조를 가진다. 그리고 최근의 반도체 패키지가 적용되는 제품의 고 사양화 및 HBM(High Bandwidth Memory) 등의 다수의 칩 채용 등으로 인해 반도체 패키지의 사이즈가 커지고 있다. 반도체 패키지의 사이즈가 커짐에 따라 신뢰성 등의 확보를 위해 반도체 패키지는 다수의 칩을 연결하기 위해 인터포저를 포함하는 등 다양한 구성이 연구되고 있다. A typical semiconductor package has a structure in which multiple chips are arranged. In addition, the size of semiconductor packages is increasing due to the recent higher specifications of products to which semiconductor packages are applied and the adoption of a large number of chips such as HBM (High Bandwidth Memory). As the size of semiconductor packages increases, various configurations are being studied to ensure reliability, such as including interposers to connect multiple chips.
또한, 사물 인터넷(IoT:Internet of Things)을 제공하는 제품, 자율 주행차 및 고성능 서버 등에 적용되는 반도체 패키지는 고집적화 추세에 따라 높은 성능 및 높은 신뢰성이 요구된다. 여기에서, 높은 성능은 신호의 고속 전송 가능, 반도체 패키지의 집적화 및 전송 가능한 신호의 허용 전류가 높은 조건 등을 포함할 수 있다.In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), self-driving cars, and high-performance servers require high performance and reliability in accordance with the trend toward high integration. Here, high performance may include conditions such as high-speed transmission of signals, integration of semiconductor packages, and high allowable current for signals that can be transmitted.
이때, 반도체 패키지는 소형화 및 집적화를 위하여 패드의 사이즈가 감소하고 있다. 패드는 칩과 연결되는 실장 패드일 수 있고, 다양한 기판과 연결되는 범프 패드일 수 있다. 여기에서, 다양한 기판은 메모리 기판과 같은 추가적인 패키지, 칩과 반도체 패키지 기판 사이를 연결하는 인터포저 및 반도체 패키지가 적용되는 전자 디바이스의 메인 보드 등을 포함할 수 있다.At this time, the pad size of semiconductor packages is decreasing for miniaturization and integration. The pad may be a mounting pad connected to a chip or a bump pad connected to various substrates. Here, the various substrates may include additional packages such as a memory substrate, an interposer connecting a chip and a semiconductor package substrate, and a main board of an electronic device to which the semiconductor package is applied.
이러한 반도체 패키지 기판은 다층 반도체 패키지 기판으로 제공된다. 다층 반도체 패키지 기판은 동박 적층판(CCL) 등 코어 기판에 형성된 관통 홀에 배치되는 관통 전극을 포함한다. 이때, 반도체 패키지 기판은 배선이 복잡해짐에 따라 적층 수가 증가하고 있고, 면적이 증가함에 따라 강도 향상 및 휨 특성 향상을 위해, 코어 기판의 두께가 증가하고 있다. 예시적으로, 종래의 코어 기판의 두께는 200㎛ 내외의 두께였으나, 최근에는 그 두께가 수 배 이상 두꺼워지고 있는 추세에 있다.These semiconductor package substrates are provided as multilayer semiconductor package substrates. A multilayer semiconductor package substrate includes a through electrode disposed in a through hole formed in a core substrate such as a copper clad laminate (CCL). At this time, the number of stacks of semiconductor package substrates is increasing as wiring becomes more complex, and as the area increases, the thickness of the core substrate is increasing to improve strength and bending characteristics. For example, the thickness of the conventional core substrate was around 200㎛, but recently, the thickness has been increasing several times or more.
이때, 코어 기판의 두께가 증가하는 경우, 레이저를 이용하여 코어 기판에 관통 홀을 형성하는 것이 어려울 수 있다. 따라서, 종래에는 드릴 머신을 이용하여 코어 기판에 관통 홀을 형성하고 있다. At this time, when the thickness of the core substrate increases, it may be difficult to form a through hole in the core substrate using a laser. Therefore, conventionally, a drill machine is used to form a through hole in the core substrate.
그러나 드릴 머신을 사용하여 관통 홀을 형성하는 경우, 반도체 패키지 기판의 제조 공정 시간이 증가하고, 이에 따른 생산성이나 수율이 저하되는 문제가 있다. 나아가, 드릴 머신은 레이저 장비 대비 고가이며, 이에 의해 반도체 패키지 기판의 제조 단가가 증가하는 문제가 있다.However, when forming a through hole using a drill machine, there is a problem that the manufacturing process time of the semiconductor package substrate increases, and productivity or yield decreases accordingly. Furthermore, drill machines are more expensive than laser equipment, which increases the manufacturing cost of semiconductor package substrates.
이에 따라, 200㎛ 이상의 코어 기판을 포함하는 반도체 패키지 기판에 효율적으로 관통 홀을 형성할 수 있는 새로운 방안이 요구된다.Accordingly, a new method for efficiently forming through holes in a semiconductor package substrate including a core substrate of 200 μm or more is required.
(특허문헌 1) KR 10-2011-0016266 A (Patent Document 1) KR 10-2011-0016266 A
실시 예는 새로운 구조의 반도체 패키지 기판 및 이를 포함하는 반도체 패키지를 제공한다.Embodiments provide a semiconductor package substrate with a new structure and a semiconductor package including the same.
또한, 실시 예는 레이저 공정을 이용하여 200㎛ 이상의 코어 기판에 관통 홀을 형성할 수 있는 반도체 패키지 기판 및 이를 포함하는 반도체 패키지를 제공한다.Additionally, the embodiment provides a semiconductor package substrate capable of forming a through hole in a core substrate of 200 μm or more using a laser process, and a semiconductor package including the same.
또한, 실시 예는 관통 홀의 수직 방향으로의 최대 폭 및 최소폭의 차이가 최소화된 반도체 패키지 기판 및 이를 포함하는 반도체 패키지를 제공한다.Additionally, the embodiment provides a semiconductor package substrate in which the difference between the maximum and minimum widths of the through hole in the vertical direction is minimized, and a semiconductor package including the same.
또한, 실시 예는 관통 홀의 사이즈 확장을 방지하면서 관통 홀의 내벽의 경사가 직각에 가깝도록 한 반도체 패키지 기판 및 이를 포함하는 반도체 패키지를 제공한다.Additionally, the embodiment provides a semiconductor package substrate that prevents expansion of the size of the through hole and ensures that the inner wall of the through hole has an inclination close to a right angle, and a semiconductor package including the same.
제안되는 실시 예에서 이루고자 하는 기술적 과제들은 이상에서 언급한 기술적 과제들로 제한되지 않으며, 언급되지 않은 또 다른 기술적 과제들은 아래의 기재로부터 제안되는 실시 예가 속하는 기술분야에서 통상의 지식을 가진 자에게 명확하게 이해될 수 있을 것이다.The technical challenges to be achieved in the proposed embodiment are not limited to the technical challenges mentioned above, and other technical challenges not mentioned are clear to those skilled in the art from the description below. It will be understandable.
실시 예에 따른 반도체 패키지 기판은 상면 및 하면을 구비한 절연층; 및 상기 절연층의 상기 상면 및 상기 하면을 관통하는 관통 전극을 포함하고, 상기 관통 전극의 측면은 수직 방향을 따라 교번적으로 구비된 오목부 및 볼록부를 포함한다.A semiconductor package substrate according to an embodiment includes an insulating layer having a top and bottom surfaces; and a through electrode penetrating the upper and lower surfaces of the insulating layer, and a side surface of the through electrode includes concave portions and convex portions alternately provided along a vertical direction.
또한, 다른 실시 예에 따른 반도체 패키지 기판은 상면 및 하면을 구비한 절연층; 및 상기 절연층의 상기 상면 및 하면을 관통하는 관통 홀을 포함하고, 상기 관통 홀의 측벽은 수직 방향을 따라 교번적으로 구비된 오목부 및 볼록부를 포함한다.Additionally, a semiconductor package substrate according to another embodiment includes an insulating layer having a top and bottom surfaces; and a through hole penetrating the upper and lower surfaces of the insulating layer, wherein side walls of the through hole include concave portions and convex portions alternately provided along a vertical direction.
또한, 상기 반도체 패키지 기판은 상기 관통 홀 내에 배치된 관통 전극을 더 포함하고, 상기 관통 전극의 측면은 상기 관통 홀의 측벽의 볼록부에 대응하는 볼록부 및 상기 관통 홀의 측벽의 오목부에 대응하는 오목부를 구비한다.In addition, the semiconductor package substrate further includes a through electrode disposed in the through hole, and a side surface of the through electrode has a convex portion corresponding to a convex portion of a side wall of the through hole and a concave portion corresponding to a concave portion of a side wall of the through hole. have wealth
또한, 상기 반도체 패키지 기판은 상기 절연층을 관통하는 절연 부재를 더 포함하고, 상기 관통 전극은 상기 절연 부재의 외측을 감싸며 구비된다.Additionally, the semiconductor package substrate further includes an insulating member penetrating the insulating layer, and the penetrating electrode is provided to surround an outside of the insulating member.
또한, 상기 관통 전극의 오목부 및 볼록부는 상기 수직 방향을 따라 교번적으로 각각 복수 개 구비된다.Additionally, a plurality of concave portions and convex portions of the through electrode are provided alternately along the vertical direction.
또한, 상기 절연 부재는 수평 방향으로의 제1폭을 가지는 제1부와, 상기 수평 방향으로 상기 제1폭과 다른 제2폭을 가진 제2부를 포함한다.Additionally, the insulating member includes a first part having a first width in the horizontal direction, and a second part having a second width different from the first width in the horizontal direction.
또한, 상기 제1폭은 상기 제2폭보다 크고, 상기 제1부는 상기 관통 전극의 상기 오목부와 수평 방향으로 중첩되고, 상기 제2부는 상기 관통 전극의 상기 볼록부와 수평 방향으로 중첩된다.Additionally, the first width is greater than the second width, the first portion horizontally overlaps the concave portion of the through electrode, and the second portion horizontally overlaps the convex portion of the through electrode.
또한, 상기 절연층은 레진 및 상기 레진 내에 배치된 강화 섬유를 포함하고, 상기 강화 섬유는 제1 수평 방향으로 배치된 제1 섬유 및 상기 제1 수평 방향과 수직한 제2 수평 방향으로 배치된 제2 섬유를 포함한다.In addition, the insulating layer includes a resin and reinforcing fibers disposed in the resin, wherein the reinforcing fibers include first fibers disposed in a first horizontal direction and first fibers disposed in a second horizontal direction perpendicular to the first horizontal direction. Contains 2 fibers.
또한, 상기 강화 섬유는 수직 방향을 따라 서로 이격되고 상기 제1 및 제2 섬유 각각을 구비한 복수 개의 그룹을 포함한다.Additionally, the reinforcing fibers include a plurality of groups spaced apart from each other along the vertical direction and each having the first and second fibers.
또한, 상기 관통 전극의 상기 오목부는 상기 강화 섬유와 수평 방향으로 중첩된다.Additionally, the concave portion of the penetrating electrode overlaps the reinforcing fiber in a horizontal direction.
또한, 상기 절연층의 수직 방향으로의 두께는 250㎛ 내지 1200㎛의 범위를 만족한다.Additionally, the thickness of the insulating layer in the vertical direction satisfies the range of 250㎛ to 1200㎛.
또한, 상기 절연층의 상기 관통 홀의 내벽은, 돌출부를 구비한 복수의 제1 내벽과, 상기 돌출부를 구비하지 않은 제2 내벽을 포함한다.Additionally, the inner wall of the through hole in the insulating layer includes a plurality of first inner walls having protrusions and a second inner wall not having the protrusions.
또한, 상기 제2 내벽은 상기 관통 홀의 내벽의 오목부를 구비한 부분을 의미한다.Additionally, the second inner wall refers to a portion of the inner wall of the through hole having a concave portion.
또한, 상기 관통 전극은 상기 제1 내벽과 접촉하는 제1부와, 상기 제2 내벽과 접촉하는 제2부를 포함한다. 이때, 상기 제1 및 제2 관통 패턴은 단차를 가진다.Additionally, the through electrode includes a first part in contact with the first inner wall and a second part in contact with the second inner wall. At this time, the first and second through patterns have a step.
또한, 상기 관통 전극의 상기 제1부는 상기 관통 홀의 오목부에 대응하는 오목부를 구비하고, 상기 관통 전극의 상기 제2부는 상기 관통 홀의 볼록부에 대응하는 볼록부를 구비한다.Additionally, the first portion of the through electrode has a concave portion corresponding to a concave portion of the through hole, and the second portion of the through electrode has a convex portion corresponding to a convex portion of the through hole.
또한, 상기 관통 전극의 상기 제1 및 제2부 각각의 수평 방향으로의 두께는 10㎛ 내지 25㎛의 범위를 만족한다.Additionally, the horizontal thickness of each of the first and second portions of the penetrating electrode satisfies the range of 10 μm to 25 μm.
또한, 상기 관통 전극의 제1부의 수평 방향으로의 두께는, 상기 제2부의 수평 방향으로의 두께와 동일하다.Additionally, the thickness of the first portion of the through electrode in the horizontal direction is the same as the thickness of the second portion in the horizontal direction.
또한, 상기 제1 관통 전극은, 상기 절연층의 상기 제1 관통 홀의 내벽에 배치된 제1 금속층과, 상기 제1 금속층 상에 배치된 제2 금속층을 포함한다.Additionally, the first through electrode includes a first metal layer disposed on the inner wall of the first through hole of the insulating layer, and a second metal layer disposed on the first metal layer.
또한, 상기 제1 관통 홀의 수직 방향으로의 전체 영역에서 가장 작은 폭을 가지는 영역의 최소 폭은, 상기 제1 관통 홀의 수직 방향으로의 전체 영역에서 가장 큰 폭을 가지는 영역의 최대 폭의 55% 내지 95%의 범위를 만족한다.In addition, the minimum width of the area having the smallest width in the entire area in the vertical direction of the first through hole is 55% of the maximum width of the area having the largest width in the entire area in the vertical direction of the first through hole. Satisfies 95% coverage.
실시 예의 반도체 패키지 기판은 250㎛ 이상의 두께를 가지는 제1 절연층에 레이저 공정 장비를 이용하여 최대 폭과 최소폭의 차이가 최소화된 관통 홀을 형성할 수 있도록 한다. 이를 통해, 실시 예는 반도체 패키지 기판에 구비되는 제1 관통 전극의 물리적 특성 및 전기적 특성을 향상시킬 수 있도록 한다. The semiconductor package substrate of the embodiment allows the formation of a through hole with a minimized difference between the maximum and minimum widths using laser processing equipment in the first insulating layer having a thickness of 250㎛ or more. Through this, the embodiment makes it possible to improve the physical and electrical characteristics of the first through electrode provided on the semiconductor package substrate.
구체적으로, 제1 절연층은 강화 섬유를 포함하는 코어층이다.Specifically, the first insulating layer is a core layer containing reinforcing fibers.
이때, 비교 예는 제1 절연층에 레이저 장비를 이용하여 관통 홀을 형성하는 경우, 관통 홀은 수직 방향을 따라 폭이 서로 다른 영역을 포함하게 되고, 최소폭이 최대폭의 50% 미만이 된다. 이에 따라, 비교 예에서는 관통 홀 내에 관통 전극을 배치하는 도금 공정에서 영역별 도금 속도의 차이에 따라 불균일한 관통 전극이 배치되는 문제가 있었다. At this time, as a comparative example, when a through hole is formed in the first insulating layer using a laser device, the through hole includes areas with different widths along the vertical direction, and the minimum width is less than 50% of the maximum width. Accordingly, in the comparative example, there was a problem of non-uniform placement of the through electrodes due to differences in plating speeds for each region in the plating process of placing the through electrodes in the through holes.
또한, 비교 예는 최소폭과 최대폭의 차이를 최소화하기 위해 레이저 공정 조건에서의 레이저 세기를 증가시켰다. 그러나, 이 경우 관통 홀의 사이즈가 목표 사이즈보다 더 크게 형성되는 사이즈 확장 문제가 발생하게 된다. Additionally, in the comparative example, the laser intensity under laser processing conditions was increased to minimize the difference between the minimum and maximum widths. However, in this case, a size expansion problem occurs in which the size of the through hole is formed larger than the target size.
또한, 또 다른 비교 예에서는 최소폭과 최대폭의 차이를 최소화하기 위해 머신 드릴 장비를 이용하여 관통 홀을 형성하고 있다. 그러나, 머신 드릴 장비를 이용하는 경우, 한 번에 1개의 관통 홀만을 형성할 수 있다. 이에 의해 생산 수율이 저하되는 문제를 가졌다.Additionally, in another comparative example, a through hole is formed using machine drill equipment to minimize the difference between the minimum and maximum width. However, when using machine drill equipment, only one through hole can be formed at a time. This had the problem of lowering the production yield.
이에 반하여, 실시 예는 적어도 2개 이상의 좌표 코드(T-code)를 이용하여 제1 절연층에 관통 홀을 형성한다. 실시 예에 따르면 에너지 세기에 따라 2개의 좌표 코드를 이용하는 것에 의해 관통 홀의 형성 공정 중에 레이저 공정 조건의 변경이 가능하다. 실시 예에 따르면, 제1 좌표 코드를 이용하여 제1 사이즈의 개구를 가진 제1 마스크에 제1 레이저 에너지 세기의 레이저를 조사하여 관통 홀의 일부를 형성한다. 나아가, 제2 좌표 코드를 이용하여 제1 사이즈와 다른 제2 사이즈의 개구를 가지는 제2 마스크에 제1 레이저 에너지 세기와 다른 에너지 세기를 갖는 제2 레이저 에너지 세기의 레이저를 조사하여 관통 홀의 나머지 일부를 형성한다. 이를 통해 실시 예는 관통 홀의 사이즈 확장을 방지하면서, 레이저 장비를 이용하여 제1 절연층에 최대 폭과 최소폭의 차이가 최소화된 관통 홀을 형성할 수 있다. 이를 통해, 실시 예는 제1 관통 홀 내에 제1 관통 전극을 배치하는 도금 공정에 있어서, 제1 관통 전극의 두께의 불균일함을 해결할 수 있다. 또한, 제1 관통 전극이 제1 절연층으로부터 박리되거나, 제1 관통 전극에 크랙이 발생하는 물리적 문제를 해결할 수 있다. 이를 통해 실시 예는 반도체 패키지 기판의 물리적 특성을 향상시킬 수 있다. 상술한 바와 같이, 실시 예에서는 도금 특성 개선을 통해 제1 절연층에 균일한 두께를 갖도록 제1 관통 전극을 배치할 수 있다. 이를 통해, 제1 관통 전극을 통해 전달되는 신호의 손실을 최소화할 수 있고, 전압 강하를 방지할 수 있을 뿐만 아니라, 임피던스 매칭에 유리하여 배선 설계에 자유도를 높일 수 있다. 나아가 본 실시 예에 따른 제1 관통홀은 반도체 패키지 기판 및 이를 포함하는 반도체 패키지의 전기적 특성을 향상시킬 수 있다.In contrast, in the embodiment, a through hole is formed in the first insulating layer using at least two coordinate codes (T-code). According to an embodiment, it is possible to change laser processing conditions during the through-hole forming process by using two coordinate codes according to energy intensity. According to an embodiment, a portion of a through hole is formed by irradiating a laser having a first laser energy intensity to a first mask having an opening of a first size using a first coordinate code. Furthermore, a laser of a second laser energy intensity having an energy intensity different from the first laser energy intensity is irradiated to a second mask having an opening of a second size different from the first size using the second coordinate code to form a remaining portion of the through hole. forms. Through this, the embodiment can form a through hole with a minimized difference between the maximum and minimum widths in the first insulating layer using a laser device while preventing expansion of the size of the through hole. Through this, the embodiment can solve the non-uniformity of the thickness of the first through electrode in the plating process of disposing the first through electrode in the first through hole. In addition, it is possible to solve physical problems in which the first through electrode is separated from the first insulating layer or cracks occur in the first through electrode. Through this, the embodiment can improve the physical properties of the semiconductor package substrate. As described above, in the embodiment, the first through-electrode can be disposed to have a uniform thickness in the first insulating layer through improved plating characteristics. Through this, the loss of the signal transmitted through the first through electrode can be minimized, voltage drop can be prevented, and the degree of freedom in wiring design can be increased by benefiting impedance matching. Furthermore, the first through hole according to this embodiment can improve the electrical characteristics of the semiconductor package substrate and the semiconductor package including the same.
또한, 실시 예는 250㎛ 내지 1200㎛의 수직 방향의 두께를 가지면서 내부에 강화 섬유가 포함된 제1 절연층에 레이저 장비를 이용하여 관통 홀을 형성하는 것이 가능하다. 이를 통해 실시 예는 머신 드릴 장비를 이용하여 관통 홀을 형성하는 것 대비 관통 홀을 형성하는데 소요되는 시간을 줄일 수 있다. 이에 따라, 실시 예는 반도체 패키지 기판의 생산 수율을 향상시킬 수 있다. 나아가, 실시 예는 레이저 장비만을 이용하여 코어층을 포함하는 다층 기판의 모든 절연층에 관통 홀을 형성하는 것이 가능하다. 이에 따라 실시 예는 반도체 패키지 기판의 제조 공정에서의 효율성을 향상시킬 수 있다. 나아가, 실시 예는 상대적으로 가격이 비싼 머신 드릴 장비를 이용하지 않아도 됨으로써, 반도체 패키지 기판의 제조 단가를 줄일 수 있다.In addition, in the embodiment, it is possible to form a through hole using a laser device in the first insulating layer that has a vertical thickness of 250㎛ to 1200㎛ and includes reinforcing fibers therein. Through this, the embodiment can reduce the time required to form a through hole compared to forming a through hole using machine drill equipment. Accordingly, the embodiment can improve the production yield of semiconductor package substrates. Furthermore, in the embodiment, it is possible to form through holes in all insulating layers of the multilayer substrate including the core layer using only a laser device. Accordingly, the embodiment can improve efficiency in the manufacturing process of a semiconductor package substrate. Furthermore, the embodiment can reduce the manufacturing cost of the semiconductor package substrate by eliminating the need to use relatively expensive machine drill equipment.
도 1a는 제1 비교 예에 따른 반도체 패키지 기판을 설명하기 위한 단면도이다.1A is a cross-sectional view for explaining a semiconductor package substrate according to a first comparative example.
도 1b는 제2 비교 예에 따른 반도체 패키지 기판을 설명하기 위한 단면도이다.FIG. 1B is a cross-sectional view illustrating a semiconductor package substrate according to a second comparative example.
도 2a는 제1 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.Figure 2a is a cross-sectional view showing a semiconductor package according to the first embodiment.
도 2b는 제2 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.Figure 2b is a cross-sectional view showing a semiconductor package according to a second embodiment.
도 2c는 제3 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.Figure 2c is a cross-sectional view showing a semiconductor package according to a third embodiment.
도 2d는 제4 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.Figure 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.
도 2e는 제5 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.Figure 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.
도 2f는 제6 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.Figure 2f is a cross-sectional view showing a semiconductor package according to the sixth embodiment.
도 2g는 제7 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.Figure 2g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.
도 3a는 제1 실시 예에 따른 반도체 패키지 기판을 나타낸 도면이다.FIG. 3A is a diagram showing a semiconductor package substrate according to the first embodiment.
도 3b는 제2 실시 예에 따른 반도체 패키지 기판을 나타낸 도면이다.Figure 3b is a diagram showing a semiconductor package substrate according to a second embodiment.
도 4는 실시 예의 제1 절연층을 설명하기 위한 단면도이다.Figure 4 is a cross-sectional view for explaining the first insulating layer of the embodiment.
도 5는 도 4의 제1 절연층에 구비된 제1 관통 홀을 나타낸 단면도이다.FIG. 5 is a cross-sectional view showing a first through hole provided in the first insulating layer of FIG. 4.
도 6은 도 5의 관통 홀에 배치된 제1 관통 전극 및 절연 부재를 나타낸 단면도이다.FIG. 6 is a cross-sectional view showing a first through electrode and an insulating member disposed in the through hole of FIG. 5.
도 7은 제1 실시 예의 제1 관통 전극 및 제1 회로 패턴층의 층 구조를 나타낸 도면이다.Figure 7 is a diagram showing the layer structure of the first through electrode and the first circuit pattern layer in the first embodiment.
도 8은 제2 실시 예의 제1 관통 전극 및 제1 회로 패턴층의 층 구조를 나타낸 도면이다.Figure 8 is a diagram showing the layer structure of the first through electrode and the first circuit pattern layer in the second embodiment.
도 9는 실시 예에 따른 제1 관통 홀, 제1 관통 전극 및 절연 부재를 포함하는 실제 제품의 광학 현미경 사진이다.9 is an optical microscope photograph of an actual product including a first through hole, a first through electrode, and an insulating member according to an embodiment.
도 10 내지 14는 실시 예에 따른 반도체 패키지 기판의 제조 방법의 일부를 공정 순으로 나타낸 도면이다.10 to 14 are diagrams showing part of a method for manufacturing a semiconductor package substrate according to an embodiment, in process order.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세히 설명한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.
다만, 본 발명의 기술 사상은 설명되는 일부 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있고, 본 발명의 기술 사상 범위 내에서라면, 실시 예들간 그 구성 요소들 중 하나 이상을 선택적으로 결합, 치환하여 사용할 수 있다.However, the technical idea of the present invention is not limited to some of the described embodiments, but may be implemented in various different forms, and as long as it is within the scope of the technical idea of the present invention, one or more of the components may be optionally used between the embodiments. It can be used by combining and replacing.
또한, 본 발명의 실시 예에서 사용되는 용어(기술 및 과학적 용어를 포함)는, 명백하게 특별히 정의되어 기술되지 않는 한, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 일반적으로 이해될 수 있는 의미로 해석될 수 있으며, 사전에 정의된 용어와 같이 일반적으로 사용되는 용어들은 관련 기술의 문맥상의 의미를 고려하여 그 의미를 해석할 수 있을 것이다. 또한, 본 발명의 실시예에서 사용된 용어는 실시 예들을 설명하기 위한 것이며 본 발명을 제한하고자 하는 것은 아니다.In addition, terms (including technical and scientific terms) used in the embodiments of the present invention, unless specifically defined and described, are generally understood by those skilled in the art to which the present invention pertains. It can be interpreted as meaning, and the meaning of commonly used terms, such as terms defined in a dictionary, can be interpreted by considering the contextual meaning of the related technology. Additionally, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.
본 명세서에서, 단수형은 문구에서 특별히 언급하지 않는 한 복수형도 포함할 수 있고, "A 및(와) B, C중 적어도 하나(또는 한 개 이상)"로 기재되는 경우 A, B, C로 조합할 수 있는 모든 조합 중 하나 이상을 포함할 수 있다. 또한, 본 발명의 실시 예의 구성 요소를 설명하는 데 있어서, 제1, 제2, A, B, (a), (b) 등의 용어를 사용할 수 있다.In this specification, the singular may also include the plural unless specifically stated in the phrase, and when described as "at least one (or more than one) of A and B and C", it is combined with A, B, and C. It can contain one or more of all possible combinations. Additionally, when describing the components of an embodiment of the present invention, terms such as first, second, A, B, (a), and (b) may be used.
이러한 용어는 그 구성 요소를 다른 구성 요소와 구별하기 위한 것일 뿐, 그 용어에 의해 해당 구성 요소의 본질이나 차례 또는 순서 등으로 한정되지 않는다. 그리고, 어떤 구성 요소가 다른 구성요소에 '연결', '결합' 또는 '접속'된다고 기재된 경우, 그 구성 요소는 그 다른 구성요소에 직접적으로 연결, 결합 또는 접속되는 경우 뿐만 아니라, 그 구성 요소와 그 다른 구성요소 사이에 있는 또 다른 구성 요소로 인해 '연결', '결합' 또는 '접속＇되는 경우도 포함할 수 있다.These terms are only used to distinguish the component from other components, and are not limited to the essence, sequence, or order of the component. And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected, coupled or connected to that other component, but also is connected to that component. It may also include cases where other components are 'connected', 'coupled', or 'connected' by another component between them.
또한, 각 구성 요소의 " 상(위) 또는 하(아래)"에 형성 또는 배치되는 것으로 기재되는 경우, 상(위) 또는 하(아래)는 두개의 구성 요소들이 서로 직접 접촉되는 경우 뿐만 아니라 하나 이상의 또 다른 구성 요소가 두 개의 구성 요소들 사이에 형성 또는 배치되는 경우도 포함한다. 또한, "상(위) 또는 하(아래)"으로 표현되는 경우 하나의 구성 요소를 기준으로 위쪽 방향 뿐만 아니라 아래쪽 방향의 의미도 포함할 수 있다.In addition, when described as being formed or disposed "on top or bottom" of each component, top or bottom refers not only to cases where two components are in direct contact with each other, but also to one component. This also includes cases where another component described above is formed or placed between two components. In addition, when expressed as "top (above) or bottom (bottom)", it may include not only the upward direction but also the downward direction based on one component.
도 1a는 제1 비교 예에 따른 반도체 패키지 기판을 설명하기 위한 단면도이고, 도 1b는 제2 비교 예에 따른 반도체 패키지 기판을 설명하기 위한 단면도이다.FIG. 1A is a cross-sectional view illustrating a semiconductor package substrate according to a first comparative example, and FIG. 1B is a cross-sectional view illustrating a semiconductor package substrate according to a second comparative example.
비교 예의 설명에 앞서, 반도체 패키지 기판은 전자기기의 고기능화 및 반도체 디바이스의 고집적화에 수반하여 고밀도화가 요구되고 있다. 이에 따라, 반도체 패키지 기판은 다층 구조를 가진다.Before explaining comparative examples, semiconductor package substrates are required to have higher densities as electronic devices become more functional and semiconductor devices become more integrated. Accordingly, the semiconductor package substrate has a multi-layer structure.
이러한 다층 구조의 반도체 패키지 기판이 적용되는 제품군에는 FCBGA(Flip Chip Ball Grid Array)이나 FCCSP((Flip Chip Chip Scale Package)가 포함된다. 그리고, FCBGA나 FCCSP에 적용되는 일부 반도체 패키지 기판에는 코어층이 포함된다. Product lines to which this multi-layered semiconductor package substrate is applied include FCBGA (Flip Chip Ball Grid Array) and FCCSP ((Flip Chip Chip Scale Package). Additionally, some semiconductor package substrates applied to FCBGA or FCCSP have a core layer. Included.
코어층은 다층 빌드업 구현을 위해 강성을 갖고 있는 절연층으로, 일정 이상의 두께를 가지고 있다. 다층 빌드업에 따른 적층 수에 따라 코어층의 두께는 다양하게 나타날 수 있다. 예시적으로, 반도체 패키지 기판의 배선이 복잡해지고, 전압 강하 문제 및/또는 신호의 손실 감소를 위해, 250㎛ 내지 1200㎛의 두께를 가질 수 있다. The core layer is an insulating layer with rigidity to implement multi-layer build-up, and has a thickness above a certain level. The thickness of the core layer may vary depending on the number of layers in the multi-layer build-up. As an example, the semiconductor package substrate may have a thickness of 250 ㎛ to 1200 ㎛ in order to increase the complexity of wiring and reduce voltage drop problems and/or signal loss.
또한, 코어층에는 각층의 회로 패턴과의 전기적 도통을 위한 관통 전극이 형성된다. 관통 전극은 코어층의 상면과 하면을 관통하는 관통 홀을 전도성 물질로 충진하여 구비될 수 있다. 그러나 상술한 코어층은 250㎛ 내지 1200㎛의두께를 가지며, 이에 따라 비교 예의 관통 홀을 형성하는 공정 및/또는 관통 전극을 형성하는 공정에서는 다음과 같은 문제점이 있다.Additionally, penetrating electrodes are formed in the core layer for electrical connection with the circuit patterns of each layer. The through electrode may be provided by filling a through hole penetrating the upper and lower surfaces of the core layer with a conductive material. However, the above-described core layer has a thickness of 250㎛ to 1200㎛, and accordingly, the process of forming the through hole and/or the through electrode of the comparative example has the following problems.
관통 홀은 레이저 장비 및 드릴 머신 장비 중 어느 하나를 이용하여 형성된다. 도 1a는 레이저 장비를 이용하여 관통 홀을 형성하는 제1 비교 예를 나타낸 것이고, 도 1b는 드릴 머신 장비를 이용하여 관통 홀을 형성하는 제2 비교 예를 나타낸 것이다.The through hole is formed using either a laser device or a drill machine device. Figure 1a shows a first comparative example of forming a through hole using a laser equipment, and Figure 1b shows a second comparative example of forming a through hole using a drill machine equipment.
도 1a의 (a)에서와 같이, 제1 비교 예에서는 코어층으로 사용될 절연층(10)을 준비한다. 이때, 절연층(10)의 두께(t)는 250㎛ 내지 1200㎛ 일수 있다.As shown in (a) of FIG. 1A, in the first comparative example, an insulating layer 10 to be used as a core layer is prepared. At this time, the thickness (t) of the insulating layer 10 may be 250㎛ to 1200㎛.
그리고, 제1 비교 예에서는 레이저 장비를 이용하여 절연층(10)에 관통 홀을 형성한다.And, in the first comparative example, a through hole is formed in the insulating layer 10 using a laser device.
이때, 절연층(10)은 250㎛ 내지 1200㎛의 두께(t)를 가지기 때문에 절연층(10)의 일측에서만 레이저 가공을 진행하여 관통 홀을 형성하는 것이 어렵다. 이에 따라, 제1 비교 예는 절연층(10)의 상면 및 하면의 각각에서 레이저 가공을 진행하여 관통 홀을 형성한다. At this time, since the insulating layer 10 has a thickness (t) of 250㎛ to 1200㎛, it is difficult to form a through hole by performing laser processing on only one side of the insulating layer 10. Accordingly, in the first comparative example, laser processing is performed on each of the upper and lower surfaces of the insulating layer 10 to form through holes.
구체적으로, 제1 비교 예는 관통 홀이 가져야 하는 목표 사이즈에 대응하도록 절연층(10)의 상면에서 관통 홀의 제1 파트를 형성하고, 절연층(10)의 하면에서 관통 홀의 제1 파트와 연결되는 제2 파트를 형성한다.Specifically, in the first comparative example, the first part of the through hole is formed on the upper surface of the insulating layer 10 to correspond to the target size that the through hole should have, and the first part of the through hole is connected to the lower surface of the insulating layer 10. forms the second part.
그러나, 도 1a의 (b)에서와 같이, 목표 사이즈에 대응되도록 레이저의 에너지 세기를 설정하는 경우, 절연층(10)의 두께에 비해 레이저의 에너지 세기가 작아, 상술한 바와 같이 제1 파트(11)와 제2 파트(12)를 형성하는 경우, 제1 파트(11)와 제2 파트(12)가 서로 연결되지 않는 미관통 문제가 발생할 수 있다.However, as shown in (b) of FIG. 1A, when the energy intensity of the laser is set to correspond to the target size, the energy intensity of the laser is small compared to the thickness of the insulating layer 10, and as described above, the first part ( When forming 11) and the second part 12, a problem of non-penetration may occur in which the first part 11 and the second part 12 are not connected to each other.
이에 따라, 제1 비교 예에서는 상술한 절연층(10) 미관통 문제를 해결하기 위해, 레이저의 에너지 세기를 크게 설정한다. 따라서 도 1a의 (c)에서와 같이, 관통 홀이 가져야 하는 목표 사이즈보다 큰 사이즈를 갖는 제1 파트(11)와 제2 파트(12)가 형성된다. Accordingly, in the first comparative example, the energy intensity of the laser is set large to solve the problem of non-penetration of the insulating layer 10 described above. Accordingly, as shown in (c) of FIG. 1A, the first part 11 and the second part 12 are formed having a size larger than the target size that the through hole should have.
그러나 이와 같은 경우, 관통 홀은 목표 사이즈보다 큰 폭(w1)을 가지게 된다. 이에 따라, 제1 비교 예에서의 관통 홀 및 이를 충진하여 형성되는 관통 전극의 사이즈를 원하는 목표 사이즈로 맞추기 어려운 문제가 있다.However, in this case, the through hole has a width (w1) larger than the target size. Accordingly, there is a problem that it is difficult to adjust the size of the through hole and the through electrode formed by filling the through hole in the first comparative example to the desired target size.
나아가, 제1 비교 예에서는 관통 홀의 사이즈가 커짐에 따라, 관통 홀 내부를 도전성 물질로 충진하는 과정에서, 도금 속도의 차이에 의해 보이드(void, 관통 홀의 일부가 충진되지 않는 현상)나 딤플(dimple)과 같은 문제가 발생할 수 있다.Furthermore, in the first comparative example, as the size of the through hole increases, in the process of filling the inside of the through hole with a conductive material, voids (a phenomenon in which part of the through hole is not filled) or dimples occur due to differences in plating speed. ) problems may occur.
또한, 제1 비교 예는 특정 관통 홀에 대해 1개의 좌표 코드(예를 들어, T-code)를 이용하여 여러 차례 레이저 빔을 조사한다. 이때, 제1 비교 예는 1개의 좌표 코드를 이용하기 때문에 복수의 스텝의 진행 중에 레이저 공정 조건을 변경하는 것이 불가하다. 여기에서 레이저 공정 조건은 마스크 사이즈, 펄스 폭, 에너지 세기, 콜리메이션 및 스텝 수 등을 의미할 수 있다. Additionally, in the first comparative example, a laser beam is irradiated several times to a specific through hole using one coordinate code (eg, T-code). At this time, because the first comparative example uses one coordinate code, it is impossible to change the laser process conditions while a plurality of steps are in progress. Here, the laser process conditions may mean mask size, pulse width, energy intensity, collimation, and number of steps.
이에 따라, 제1 비교 예는 초기 설정된 레이저 공정 조건이 목표 사이즈에 대응하는 경우, 미관통 문제가 발생한다. 나아가, 제1 비교 예는 관통 홀이 절연층(10)을 관통하며 형성되더라도, 관통 홀의 수직 방향으로의 전체 영역에서의 최소 폭이 최대 폭의 50% 미만이다. 그리고 최소 폭과 최대 폭의 차이가 커질수록 관통 전극을 형성하는 도금 공정에서의 도금 특성이 저하되는 문제가 있다.Accordingly, in the first comparative example, when the initially set laser process conditions correspond to the target size, a non-penetration problem occurs. Furthermore, in the first comparative example, even though the through hole is formed penetrating the insulating layer 10, the minimum width in the entire area in the vertical direction of the through hole is less than 50% of the maximum width. Additionally, as the difference between the minimum and maximum widths increases, there is a problem in that the plating characteristics in the plating process for forming the through electrode deteriorate.
또 다른 종래 기술을 참고하면, 도 1b의 (a) 및 (b)에서와 같이, 제2 비교 예는 레이저가 아닌 CNC(computer numerical control) 드릴과 같은 드릴 머신 장비를 이용하여 관통 홀(20)을 형성한다. Referring to another prior art, as shown in (a) and (b) of Figure 1b, the second comparative example is a through hole 20 using drill machine equipment such as a CNC (computer numerical control) drill rather than a laser. forms.
드릴 머신 장비를 이용하는 경우, 절연층(10)에 형성되는 관통 홀의 내벽의 경사는 실질적으로 수직에 가깝다. When using drill machine equipment, the inclination of the inner wall of the through hole formed in the insulating layer 10 is substantially close to vertical.
그러나 이와 같은 관통 홀(20)은 모래시계 형상을 가지는 도 1a의 관통 홀과는 다르게 도금 브리지(bridge)를 포함하지 않기 때문에, 관통 홀(20) 내에 전도성 물질을 균일하게 충진하기 어려운 문제가 있다. However, since this through hole 20 does not include a plating bridge, unlike the hourglass-shaped through hole of FIG. 1A, there is a problem in that it is difficult to uniformly fill the through hole 20 with a conductive material. .
나아가, 드릴 머신 장비는 레이저 장비 대비 고가이다. 따라서, 드릴 머신 장비를 이용하여 관통 홀을 형성하는 경우, 인프라 구축에 큰 비용이 필요하거나 반도체 패키지 기판의 제조 단가가 증가하는 문제가 있다.Furthermore, drill machine equipment is more expensive than laser equipment. Therefore, when forming a through hole using drill machine equipment, there is a problem that a large cost is required to build infrastructure or the manufacturing cost of the semiconductor package substrate increases.
또한, 드릴 머신 장비를 이용하여 관통 홀(20)을 형성하는 경우, 반도체 패키지 기판의 생산성이 저하되는 문제가 있다. 구체적으로, 드릴 머신 장비를 이용하는 경우, 예시적으로 한 번에 1개의 관통 홀 만을 형성할 수 있다. 이에 따라, 레이저 장비를 이용하는 것 대비 반도체 패키지 기판의 제조 공정 시간이 수배 이상 증가할 수 있고, 이에 따른 생산성이나 수율이 저하되는 문제가 있다.Additionally, when forming the through hole 20 using drill machine equipment, there is a problem that the productivity of the semiconductor package substrate is reduced. Specifically, when using drill machine equipment, exemplarily, only one through hole can be formed at a time. Accordingly, the manufacturing process time for a semiconductor package substrate can increase several times compared to using laser equipment, and there is a problem of decreased productivity and yield.
그러나, 본 실시 예에 따른 레이저 장비를 이용하여 관통 홀을 형성하는 경우, 마스크에 포함된 개구를 이용하여 한 번에 복수의 관통 홀을 형성하면서 복수의 관통 홀 각각에 균일한 관통 전극을 형성할 수 있다. 또한, 드릴 머신 장비를 이용하는 것에 비해 반도체 패키지 기판의 제조 공정 시간을 크게 단축할 수 있고, 이에 따른 생산성이나 수율을 크게 개선할 수 있다.However, when forming through holes using the laser equipment according to this embodiment, a plurality of through holes can be formed at once using the opening included in the mask, and a uniform through electrode can be formed in each of the plurality of through holes. You can. Additionally, compared to using drill machine equipment, the manufacturing process time for semiconductor package substrates can be significantly shortened, and productivity and yield can be greatly improved.
실시 예에서는 250㎛ 내지 1200㎛의 두께를 가지는 코어층에 형성된 관통 홀 내부에 전기적 신뢰성 및 물리적 신뢰성이 향상된 관통 전극을 형성할 수 있도록 한다. 예를 들어, 실시 예에서는 새로운 구조를 가지는 관통 전극을 포함한 반도체 패키지 기판 및 이를 포함하는 패키지 기판을 제공하도록 한다. In an embodiment, a through electrode with improved electrical and physical reliability can be formed inside a through hole formed in a core layer having a thickness of 250㎛ to 1200㎛. For example, the embodiment provides a semiconductor package substrate including a through electrode having a new structure and a package substrate including the same.
-전자 -former 디바이스device --
실시 예의 설명에 앞서, 실시 예의 반도체 패키지가 적용되는 전자 디바이스에 대해 간략하게 설명하기로 한다. Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described.
전자 디바이스는 스마트폰(smart phone), 개인용 정보 단말기(personal digital assistant), 디지털 비디오 카메라(digital video camera), 디지털 스틸 카메라(digital still camera), 차량, 고성능 서버, 네트워크 시스템(network system), 컴퓨터(computer), 모니터(monitor), 태블릿(tablet), 랩탑(laptop), 넷북(netbook), 텔레비전(television), 비디오 게임(video game), 스마트 워치(smart watch), 오토모티브(Automotive) 등일 수 있다. 다만, 이에 한정되는 것은 아니며, 이들 외에도 데이터를 처리하는 임의의 다른 전자기기일 수 있음은 물론이다.Electronic devices include smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, and computers. It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. . However, it is not limited to this, and of course, it can be any other electronic device that processes data.
전자 디바이스는 메인 보드(미도시)를 포함한다. 메인 보드는 다양한 부품들과 물리적 및/또는 전기적으로 연결될 수 있다. 또한, 메인 보드는 실시 예의 반도체 패키지 기판과 연결될 수 있다. 반도체 패키지 기판에는 다양한 반도체 소자가 실장될 수 있다.The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. Additionally, the main board may be connected to the semiconductor package substrate of the embodiment. Various semiconductor devices can be mounted on a semiconductor package substrate.
반도체 소자는 능동소자 및/또는 수동소자를 포함할 수 있다. 능동소자는 수백 내지 수백만 개 이상의 트랜지스터 등의 능동 소자가 하나의 칩 안에 집적화된 집적회로(IC) 형태의 반도체칩일 수 있다. 반도체 소자는 로직 칩, 메모리칩 등일 수 있다. 로직 칩은 센트랄 프로세서(CPU), 그래픽 프로세서(GPU) 등일 수 있다. 예를 들어, 로직 칩은 센트랄 프로세서(CPU), 그래픽 프로세서(GPU), 디지털 신호 프로세서, 암호화 프로세서, 마이크로 프로세서, 마이크로 컨트롤러 중 적어도 하나를 포함하는 애플리케이션 프로세서(AP) 칩이거나, 또는 아날로그-디지털 컨버터, ASIC(application-specific IC) 등이거나, 또는 지금까지 나열한 것들의 특정 조합을 포함하는 칩 세트일 수 있다. Semiconductor devices may include active devices and/or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of active devices, such as transistors, are integrated into a single chip. Semiconductor devices may be logic chips, memory chips, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an application processor (AP) chip that includes at least one of a central processor (CPU), graphics processor (GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or an analog-digital chip. It could be a converter, an application-specific IC (ASIC), or a set of chips containing a specific combination of the ones listed so far.
메모리 칩은 HBM 등의 스택 메모리일 수 있다. 또한, 메모리 칩은 휘발성 메모리(예컨대, DRAM), 비-휘발성 메모리(예컨대, ROM), 플래시 메모리 등의 메모리 칩을 포함할 수 있다.The memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.
한편, 실시 예의 반도체 패키지가 적용되는 반도체 패키지 기판의 제품군은 CSP(Chip Scale Package), FC-CSP(Flip Chip-Chip Scale Package), FC-BGA(Flip Chip Ball Grid Array), POP (Package On Package) 및 SIP(System In Package) 중 어느 하나일 수 있으나, 이에 한정되는 것은 아니다.Meanwhile, the product groups of semiconductor package substrates to which the semiconductor package of the embodiment is applied include CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), and POP (Package On Package). ) and SIP (System In Package), but is not limited thereto.
이하에서는 실시 예에 따른 반도체 패키지 기판을 포함하는 반도체 패키지에 대해 설명하기로 한다. 실시 예의 반도체 패키지는 추후 설명될 반도체 패키지 기판을 포함한 다양한 패키지 구조를 가질 수 있다. 그리고 일 실시 예에서의 반도체 패키지 기판은 이하에서 설명되는 제1 반도체 패키지 기판으로 지칭될 수 있고, 다른 실시 예에서의 반도체 패키지 기판은 이하에서 설명되는 제2 반도체 패키지 기판으로 지칭될 수 있다.Hereinafter, a semiconductor package including a semiconductor package substrate according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a semiconductor package substrate that will be described later. Additionally, the semiconductor package substrate in one embodiment may be referred to as a first semiconductor package substrate described below, and the semiconductor package substrate in another embodiment may be referred to as a second semiconductor package substrate described below.
도 2a는 제1 실시 예에 따른 반도체 패키지를 나타낸 단면도이고, 도 2b는 제2 실시 예에 따른 반도체 패키지를 나타낸 단면도이고, 도 2c는 제3 실시 예에 따른 반도체 패키지를 나타낸 단면도이고, 도 2d는 제4 실시 예에 따른 반도체 패키지를 나타낸 단면도이고, 도 2e는 제5 실시 예에 따른 반도체 패키지를 나타낸 단면도이고, 도 2f는 제6 실시 예에 따른 반도체 패키지를 나타낸 단면도이고, 도 2g는 제7 실시 예에 따른 반도체 패키지를 나타낸 단면도이다.FIG. 2A is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 2B is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 2C is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 2D is a cross-sectional view showing a semiconductor package according to the fourth embodiment, FIG. 2E is a cross-sectional view showing a semiconductor package according to the fifth embodiment, FIG. 2F is a cross-sectional view showing a semiconductor package according to the sixth embodiment, and FIG. 2G is a cross-sectional view showing a semiconductor package according to the sixth embodiment. This is a cross-sectional view showing a semiconductor package according to Example 7.
도 2a를 참조하면, 제1 실시 예의 반도체 패키지는 제1 반도체 패키지 기판(100), 제2 반도체 패키지 기판(200) 및 반도체 소자(300)를 포함할 수 있다.Referring to FIG. 2A , the semiconductor package of the first embodiment may include a first semiconductor package substrate 100, a second semiconductor package substrate 200, and a semiconductor device 300.
제1 반도체 패키지 기판(100)은 패키지 기판을 의미한다. The first semiconductor package substrate 100 refers to a package substrate.
예를 들어, 제1 반도체 패키지 기판(100)은 적어도 하나의 외부 기판이 결합되는 공간을 제공할 수 있다. 외부 기판은 제1 반도체 패키지 기판(100) 상에 결합되는 제2 반도체 패키지 기판(200)을 의미할 수 있다. 또한, 외부 기판은 제1 반도체 패키지 기판(100)의 하부에 결합되는 전자 디바이스에 포함된 메인 보드를 의미할 수 있다. For example, the first semiconductor package substrate 100 may provide a space where at least one external substrate is coupled. The external substrate may refer to the second semiconductor package substrate 200 coupled to the first semiconductor package substrate 100. Additionally, the external substrate may refer to a main board included in an electronic device coupled to the lower part of the first semiconductor package substrate 100.
또한, 도면상에 도시하지는 않았지만, 제1 반도체 패키지 기판(100)은 제2 반도체 패키지 기판(200)이 실장되는 공간 외에도, 적어도 하나의 반도체 소자가 실장되는 공간을 제공할 수 있다. In addition, although not shown in the drawing, the first semiconductor package substrate 100 may provide a space where at least one semiconductor device is mounted in addition to a space where the second semiconductor package substrate 200 is mounted.
제1 반도체 패키지 기판(100)은 적어도 하나의 절연층, 적어도 하나의 절연층에 배치된 전극, 및 적어도 하나의 절연층을 관통하는 관통부를 포함한다.The first semiconductor package substrate 100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a penetrating portion penetrating the at least one insulating layer.
제1 반도체 패키지 기판(100) 상에는 제2 반도체 패키지 기판(200)이 배치된다.A second semiconductor package substrate 200 is disposed on the first semiconductor package substrate 100.
예시적으로, 제2 반도체 패키지 기판(200)은 인터포저일 수 있다. 또한, 제2 반도체 패키지 기판(200)은 적어도 하나의 반도체 소자가 실장되는 공간을 제공할 수 있다. 제2 반도체 패키지 기판(200)은 적어도 하나의 반도체 소자(300)와 연결될 수 있다. 예를 들어, 제2 반도체 패키지 기판(200)은 제1 반도체 소자(310) 및/또는 제2 반도체 소자(320)가 실장되는 공간을 제공할 수 있다. 제2 반도체 패키지 기판(200)은 제1 반도체 소자(310)와 제2 반도체 소자(320) 사이를 전기적으로 연결하면서, 제1 및 제2 반도체 소자(310, 320)와 제1 반도체 패키지 기판(100) 사이를 전기적으로 연결할 수 있다. 즉, 제2 반도체 패키지 기판(200)은 복수의 반도체 소자 사이의 수평적 연결 기능 및 반도체 소자와 패키지 기판 사이의 수직적 연결 기능을 할 수 있다. 또한, 다층 빌드업에 의하여 절연층의 적층 수가 많아짐에 따라 발생하는 응력과 휨 문제를 개선하기 위해 반도체 패키지 기판을 제1 반도체 패키지 기판(100)과 제2 반도체 패키지 기판(200)으로 분할할 수 있다.Illustratively, the second semiconductor package substrate 200 may be an interposer. Additionally, the second semiconductor package substrate 200 may provide a space in which at least one semiconductor device is mounted. The second semiconductor package substrate 200 may be connected to at least one semiconductor device 300. For example, the second semiconductor package substrate 200 may provide a space in which the first semiconductor device 310 and/or the second semiconductor device 320 are mounted. The second semiconductor package substrate 200 electrically connects the first semiconductor device 310 and the second semiconductor device 320, and connects the first and second semiconductor devices 310 and 320 to the first semiconductor package substrate ( 100) can be electrically connected. That is, the second semiconductor package substrate 200 can function as a horizontal connection between a plurality of semiconductor devices and a vertical connection function between the semiconductor devices and the package substrate. In addition, in order to improve stress and bending problems that occur as the number of insulating layers increases due to multilayer build-up, the semiconductor package substrate can be divided into a first semiconductor package substrate 100 and a second semiconductor package substrate 200. there is.
도 2a에서는 제2 반도체 패키지 기판(200) 상에 2개의 반도체 소자(310, 320)가 배치되는 것으로 도시하였으나, 이에 한정되는 것은 아니다. 예를 들어, 제2 반도체 패키지 기판(200) 상에는 1개의 반도체 소자가 배치될 수 있고, 이와 다르게 3개 이상의 반도체 소자가 배치될 수 있다.In FIG. 2A, two semiconductor devices 310 and 320 are shown disposed on the second semiconductor package substrate 200, but the present invention is not limited thereto. For example, one semiconductor device may be disposed on the second semiconductor package substrate 200, and alternatively, three or more semiconductor devices may be disposed on the second semiconductor package substrate 200.
일 실시 예에서, 제2 반도체 패키지 기판(200)은 반도체 소자 기능을 하는 능동 인터포저일 수 있다. 제2 반도체 패키지 기판(200)이 능동 회로의 기능을 하는 경우, 실시 예의 패키지는 제1 반도체 패키지 기판(100) 상에 수직 방향으로 적층되도록 복수의 로직 칩이 실장될 수 있다. 그리고 로직 칩 중 능동 인터포저에 대응하는 제1 로직 칩은 해당 로직 칩의 기능을 하면서, 이의 상부에 배치된 제2 로직 칩과 제1 반도체 패키지 기판(100) 사이의 신호 전달 기능을 수행할 수 있다. In one embodiment, the second semiconductor package substrate 200 may be an active interposer that functions as a semiconductor device. When the second semiconductor package substrate 200 functions as an active circuit, the package of the embodiment may have a plurality of logic chips mounted vertically on the first semiconductor package substrate 100. And among the logic chips, the first logic chip corresponding to the active interposer can function as the corresponding logic chip and perform a signal transmission function between the second logic chip disposed on top of the logic chip and the first semiconductor package substrate 100. there is.
다른 실시 예에 따르면, 제2 반도체 패키지 기판(200)은 수동 인터포저일 수 있다. 예를 들어, 제2 반도체 패키지 기판(200)은 반도체 소자(300)와 제1 반도체 패키지 기판(100) 사이에서의 신호 중계 기능을 할 수 있다. 예를 들어, 반도체 소자(300)는 5G, 사물인터넷(IOT, Internet of Things), 화질 증가, 통신 속도 증가 등의 이유로 단자의 개수가 점차 증가하고 있다. 즉 반도체 소자(300)에 구비되는 단자의 개수가 증가하고, 이에 의해 단자의 폭이나 복수의 단자들 사이의 간격이 감소하고 있다. 이때, 제1 반도체 패키지 기판(100)은 전자 디바이스의 메인 보드와 연결된다. 이에 따라, 제1 반도체 패키지 기판(100)에 구비된 전극들이 반도체 소자(300) 및 메인 보드와 각각 연결되기 위한 폭 및 간격을 가지기 위해서는 제1 반도체 패키지 기판(100)의 두께가 증가하거나, 제1 반도체 패키지 기판(100)의 층 구조가 복잡해지는 문제가 있다. 따라서, 제1 실시 예는 제1 반도체 패키지 기판(100)과 반도체 소자(300)에 제2 반도체 패키지 기판(200)을 배치한다. 그리고 제2 반도체 패키지 기판(200)은 반도체 소자(300)의 단자에 대응하는 미세 폭 및 간격을 가지는 전극을 포함할 수 있다.According to another embodiment, the second semiconductor package substrate 200 may be a passive interposer. For example, the second semiconductor package substrate 200 may function as a signal relay between the semiconductor device 300 and the first semiconductor package substrate 100. For example, the number of terminals of the semiconductor device 300 is gradually increasing due to 5G, Internet of Things (IOT), increased image quality, increased communication speed, etc. That is, the number of terminals provided in the semiconductor device 300 increases, and as a result, the width of the terminal or the gap between a plurality of terminals is reduced. At this time, the first semiconductor package substrate 100 is connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first semiconductor package substrate 100 to have a width and spacing for being connected to the semiconductor device 300 and the main board, the thickness of the first semiconductor package substrate 100 must be increased or the thickness of the first semiconductor package substrate 100 must be increased. 1 There is a problem that the layer structure of the semiconductor package substrate 100 becomes complicated. Accordingly, in the first embodiment, the second semiconductor package substrate 200 is disposed on the first semiconductor package substrate 100 and the semiconductor device 300. Additionally, the second semiconductor package substrate 200 may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device 300 .
한편, 제1 실시 예의 반도체 패키지는 접속부를 포함할 수 있다.Meanwhile, the semiconductor package of the first embodiment may include a connection part.
예를 들어, 반도체 패키지는 제1 반도체 패키지 기판(100)과 제2 반도체 패키지 기판(200) 사이에 배치되는 제1 접속부(410)를 포함한다. 제1 접속부(410)는 제1 반도체 패키지 기판(100)에 제2 반도체 패키지 기판(200)을 결합시키면서 이들 사이를 전기적으로 연결한다. For example, the semiconductor package includes a first connection portion 410 disposed between the first semiconductor package substrate 100 and the second semiconductor package substrate 200. The first connection portion 410 connects the second semiconductor package substrate 200 to the first semiconductor package substrate 100 and electrically connects them.
예를 들어, 반도체 패키지는 제2 반도체 패키지 기판(200)과 반도체 소자(300) 사이에 배치되는 제2 접속부(420)를 더 포함할 수 있다. 제2 접속부(420)는 제2 반도체 패키지 기판(200) 상에 반도체 소자(300)를 결합시키면서 이들 사이를 전기적으로 연결할 수 있다. For example, the semiconductor package may further include a second connection portion 420 disposed between the second semiconductor package substrate 200 and the semiconductor device 300. The second connection portion 420 may couple the semiconductor devices 300 to the second semiconductor package substrate 200 and electrically connect them.
반도체 패키지는 제1 반도체 패키지 기판(100)의 하면에 배치된 제3 접속부(430)를 포함한다. 제3 접속부(430)는 제1 반도체 패키지 기판(100)을 메인 보드에 결합시키면서, 이들 사이를 전기적으로 연결할 수 있다.The semiconductor package includes a third connection portion 430 disposed on the lower surface of the first semiconductor package substrate 100. The third connection portion 430 may couple the first semiconductor package substrate 100 to the main board and electrically connect them.
이때, 제1 접속부(410), 제2 접속부(420) 및 제3 접속부(430)는 와이어 본딩, 솔더 본딩, 메탈 간 다이렉트 본딩 중 적어도 하나의 본딩 방식을 의미할 수 있다. 즉, 제1 접속부(410), 제2 접속부(420) 및 제3 접속부(430)는 복수의 구성 요소를 전기적으로 연결하는 기능을 갖기 때문에, 메탈 간 다이렉트 본딩을 이용할 경우 반도체 패키지는 솔더나 와이어가 아닌, 전기적으로 연결되는 부분으로 이해될 수 있다.At this time, the first connection part 410, the second connection part 420, and the third connection part 430 may mean at least one bonding method among wire bonding, solder bonding, and direct bonding between metals. That is, because the first connection part 410, the second connection part 420, and the third connection part 430 have the function of electrically connecting a plurality of components, when direct bonding between metals is used, the semiconductor package is made using solder or wire. It can be understood as a part that is electrically connected, rather than as a part.
와이어 본딩 방식은 금(Au) 등의 도선을 이용하여 복수의 구성 요소 사이를 전기적으로 연결하는 것을 의미할 수 있다. 또한, 솔더 본딩 방식은 Sn, Ag, Cu 중 적어도 하나를 포함하는 물질을 이용하여 복수의 구성요소 사이를 전기적으로 연결할 수 있다. 또한, 메탈 간 다이렉트 본딩 방식은 솔더, 와이어, 전도성 접착제 등의 부재 없이, 복수의 구성 요소 사이에 열과 압력을 인가하여 재결정화하고, 이를 통해 복수의 구성요소 사이를 직접 결합시키는 것을 의미할 수 있다. 그리고, 메탈 간 다이렉트 본딩 방식은 제2 접속부(420)에 의한 본딩 방식을 의미할 수 있다. 이 경우, 제2 접속부(420)는 재결정화에 의해 복수의 구성요소 사이에 형성되는 금속층을 의미할 수 있다.The wire bonding method may mean electrically connecting a plurality of components using conductors such as gold (Au). Additionally, the solder bonding method can electrically connect a plurality of components using a material containing at least one of Sn, Ag, and Cu. In addition, the direct bonding method between metals may mean recrystallization by applying heat and pressure between a plurality of components without the absence of solder, wire, conductive adhesive, etc., thereby directly bonding the plurality of components. . And, the direct bonding method between metals may refer to a bonding method using the second connection portion 420. In this case, the second connection portion 420 may refer to a metal layer formed between a plurality of components through recrystallization.
제1 접속부(410), 제2 접속부(420) 및 제3 접속부(430)는 TC(Thermal Compression) 본딩 방식에 의해 복수의 구성을 서로 결합시킬 수 있다. TC 본딩은 제1 접속부(410), 제2 접속부(420) 및 제3 접속부(430)에 열과 압력을 가하여 복수의 구성 사이를 결합시키는 방식을 의미할 수 있다.The first connection part 410, the second connection part 420, and the third connection part 430 may be connected to a plurality of components using a TC (Thermal Compression) bonding method. TC bonding may refer to a method of bonding a plurality of components by applying heat and pressure to the first connection part 410, the second connection part 420, and the third connection part 430.
이때, 제1 반도체 패키지 기판(100) 및 제2 반도체 패키지 기판(200) 중 적어도 하나에서, 제1 접속부(410), 제2 접속부(420) 및 제3 접속부(430)가 배치되는 전극에는 돌출부가 배치될 수 있다. 돌출부는 제1 반도체 패키지 기판(100) 또는 제2 반도체 패키지 기판(200)에서 외측 방향을 향하여 돌출될 수 있다. At this time, in at least one of the first semiconductor package substrate 100 and the second semiconductor package substrate 200, the electrode on which the first connection part 410, the second connection part 420, and the third connection part 430 are disposed has a protrusion. can be placed. The protrusion may protrude outward from the first semiconductor package substrate 100 or the second semiconductor package substrate 200 .
돌출부는 범프(bump)라고 할 수 있다. 돌출부는 포스트(post)라고도 할 수 있다. 돌출부는 필라(pillar)라고도 할 수 있다. 바람직하게, 돌출부는 제2 반도체 패키지 기판(200)의 전극 중 반도체 소자(300)와의 결합을 위한 제2 접속부(420)가 배치된 전극을 의미할 수 있다. 즉, 반도체 소자(300)의 단자들의 피치가 미세화되면서, 반도체 소자(300)의 단자와 각각 연결되는 제2 접속부(420)의 단락이 발생할 수 있다. 따라서, 실시 예는 제2 접속부(420)의 볼륨을 줄이기 위해 제2 접속부(420)가 배치되는 제2 반도체 패키지 기판(200)의 전극에 돌출부가 포함되도록 한다. 돌출부는 제2 반도체 패키지 기판(200)의 전극과 반도체 소자(300)의 단자 사이의 정합도 및 제2 접속부(420)의 확산을 방지할 수 있다. The protrusion may be referred to as a bump. The protrusion may also be called a post. The protrusion may also be called a pillar. Preferably, the protrusion may refer to an electrode of the second semiconductor package substrate 200 on which the second connection portion 420 for coupling to the semiconductor device 300 is disposed. That is, as the pitch of the terminals of the semiconductor device 300 becomes finer, a short circuit may occur in the second connection portions 420 respectively connected to the terminals of the semiconductor device 300. Accordingly, in the embodiment, in order to reduce the volume of the second connection part 420, the electrode of the second semiconductor package substrate 200 on which the second connection part 420 is disposed includes a protrusion. The protrusion may prevent diffusion of the second connection portion 420 and the matching between the electrode of the second semiconductor package substrate 200 and the terminal of the semiconductor device 300.
한편, 도 2b를 참조하면, 제2 실시 예의 반도체 패키지는 제2 반도체 패키지 기판(200)에 제2 반도체 패키지 기판(200) 상에 배치되는 복수의 반도체 소자들을 수평적으로 연결하는 연결 부재(210)가 배치되는 점에서 제1 실시 예의 반도체 패키지와 차이가 있다. 연결 부재(210)는 브리지 기판이라고 할 수 있다. Meanwhile, referring to FIG. 2B, the semiconductor package of the second embodiment includes a connecting member 210 that horizontally connects a plurality of semiconductor devices disposed on the second semiconductor package substrate 200 to the second semiconductor package substrate 200. ) differs from the semiconductor package of the first embodiment in that it is arranged. The connection member 210 may be referred to as a bridge board.
일 실시 예에서, 연결 부재(210)는 실리콘 브리지일 수 있다. 즉, 연결 부재(210)는 실리콘 기판과 실리콘 기판 상에 배치되는 재배선층을 포함할 수 있다. In one embodiment, connecting member 210 may be a silicon bridge. That is, the connection member 210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.
다른 실시 예에서, 연결 부재(210)는 유기 브리지일 수 있다. 예를 들어, 연결 부재(210)는 유기물을 포함할 수 있다. 예를 들어, 연결 부재(210)는 실리콘 기판 대신에 유기물을 포함하는 유기 기판과 유기 기판 상에 배치되는 재배선층을 포함할 수 있다.In another embodiment, the connecting member 210 may be an organic bridge. For example, the connecting member 210 may include an organic material. For example, the connection member 210 may include an organic substrate containing an organic material instead of a silicon substrate and a redistribution layer disposed on the organic substrate.
연결 부재(210)는 제2 반도체 패키지 기판(200) 내에 매립될 수 있으나, 이에 한정되는 것은 아니다. 예를 들어, 연결 부재(210)는 제2 반도체 패키지 기판(200) 상에 돌출되는 구조를 가지고 배치될 수 있다.The connection member 210 may be embedded in the second semiconductor package substrate 200, but is not limited thereto. For example, the connecting member 210 may be disposed on the second semiconductor package substrate 200 to have a protruding structure.
또한, 제2 반도체 패키지 기판(200)은 캐비티를 포함할 수 있고, 연결 부재(210)는 제2 반도체 패키지 기판(200)의 캐비티 내에 배치될 수 있다. Additionally, the second semiconductor package substrate 200 may include a cavity, and the connecting member 210 may be disposed within the cavity of the second semiconductor package substrate 200.
도 2c를 참조하면, 제3 실시 예의 반도체 패키지는 제2 반도체 패키지 기판(200) 및 반도체 소자(300)를 포함한다. 이때, 제3 실시 예의 반도체 패키지는 제2 실시 예의 반도체 패키지 대비 제1 반도체 패키지 기판(100)이 제거된 구조를 가진다.Referring to FIG. 2C, the semiconductor package of the third embodiment includes a second semiconductor package substrate 200 and a semiconductor device 300. At this time, the semiconductor package of the third embodiment has a structure in which the first semiconductor package substrate 100 is removed compared to the semiconductor package of the second embodiment.
즉, 제3 실시 예의 제2 반도체 패키지 기판(200)은 인터포저 기능을 하면서 패키지 기판의 기능을 할 수 있다. That is, the second semiconductor package substrate 200 of the third embodiment can function as an interposer and as a package substrate.
제2 반도체 패키지 기판(200)의 하면에 배치된 제1 접속부(410)는 전자 디바이스의 메인 보드에 제2 반도체 패키지 기판(200)을 결합시킬 수 있다.The first connection portion 410 disposed on the lower surface of the second semiconductor package substrate 200 may couple the second semiconductor package substrate 200 to the main board of the electronic device.
도 2d를 참조하면, 제4 실시 예의 반도체 패키지는 제1 반도체 패키지 기판(100) 및 반도체 소자(300)를 포함한다. Referring to FIG. 2D, the semiconductor package of the fourth embodiment includes a first semiconductor package substrate 100 and a semiconductor device 300.
이때, 제4 실시 예의 반도체 패키지는 제2 실시 예의 반도체 패키지 대비 제2 반도체 패키지 기판(200)이 제거된 구조를 가진다. At this time, the semiconductor package of the fourth embodiment has a structure in which the second semiconductor package substrate 200 is removed compared to the semiconductor package of the second embodiment.
즉, 제4 실시 예의 제1 반도체 패키지 기판(100)은 패키지 기판 기능을 하면서, 반도체 소자(300)와 메인 보드 사이를 연결하는 인터포저 기능을 할 수 있다. 이를 위해, 제1 반도체 패키지 기판(100)에는 복수의 반도체 소자 사이를 연결하기 위한 연결 부재(110)를 포함할 수 있다. 연결 부재(110)는 복수의 반도체 소자 사이를 연결하는 실리콘 브리지 또는 유기물 브리지일 수 있다.That is, the first semiconductor package substrate 100 of the fourth embodiment can function as a package substrate and an interposer that connects the semiconductor device 300 and the main board. To this end, the first semiconductor package substrate 100 may include a connecting member 110 for connecting a plurality of semiconductor devices. The connection member 110 may be a silicon bridge or an organic bridge that connects a plurality of semiconductor devices.
도 2e를 참조하면, 제5 실시 예의 반도체 패키지는 제4 실시 예의 반도체 패키지 대비, 제3 반도체 소자(330)를 더 포함한다.Referring to FIG. 2E, the semiconductor package of the fifth embodiment further includes a third semiconductor element 330 compared to the semiconductor package of the fourth embodiment.
이를 위해, 제1 반도체 패키지 기판(100)의 하면에는 제4 접속부(440)가 배치된다.For this purpose, a fourth connection portion 440 is disposed on the lower surface of the first semiconductor package substrate 100.
그리고, 제4 접속부(400)에는 제3 반도체 소자(330)가 배치될 수 있다. 즉, 제5 실시 예의 반도체 패키지는 상측 및 하측에 각각 반도체 소자가 실장되는 구조를 가질 수 있다. Also, a third semiconductor element 330 may be disposed in the fourth connection part 400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively.
이때, 제3 반도체 소자(330)는 도 2c의 반도체 패키지에서, 제2 반도체 패키지 기판(200)의 하면에 배치된 구조를 가질 수도 있을 것이다. At this time, the third semiconductor device 330 may have a structure disposed on the lower surface of the second semiconductor package substrate 200 in the semiconductor package of FIG. 2C.
도 2f를 참조하면, 제6 실시 예의 반도체 패키지는 제1 반도체 패키지 기판(100)을 포함한다.Referring to FIG. 2F, the semiconductor package of the sixth embodiment includes a first semiconductor package substrate 100.
제1 반도체 패키지 기판(100) 상에는 제1 반도체 소자(310)가 배치될 수 있다. 이를 위해, 제1 반도체 패키지 기판(100)과 제1 반도체 소자(310) 사이에는 제1 접속부(410)가 배치된다.A first semiconductor device 310 may be disposed on the first semiconductor package substrate 100. To this end, a first connection portion 410 is disposed between the first semiconductor package substrate 100 and the first semiconductor device 310.
또한, 제1 반도체 패키지 기판(100)은 도전성 결합부(450)를 포함한다. 도전성 결합부(450)는 제1 반도체 패키지 기판(100)에서 제2 반도체 소자(320)를 향하여 더 돌출될 수 있다. 도전성 결합부(450)는 범프라고 할 수 있고, 이와 다르게 포스트라고도 할 수 있다. 도전성 결합부(450)는 제1 반도체 패키지 기판(100)의 최상측에 배치된 전극 상에 돌출된 구조를 가지고 배치될 수 있다. Additionally, the first semiconductor package substrate 100 includes a conductive coupling portion 450. The conductive coupling portion 450 may protrude further from the first semiconductor package substrate 100 toward the second semiconductor device 320 . The conductive coupling portion 450 may be referred to as a bump or, alternatively, may be referred to as a post. The conductive coupling portion 450 may be disposed to have a protruding structure on the electrode disposed on the uppermost side of the first semiconductor package substrate 100 .
제1 반도체 패키지 기판(100)의 도전성 결합부(450) 상에는 제2 반도체 소자(320)가 배치된다. 이때, 제2 반도체 소자(320)는 도전성 결합부(450)를 통해 제1 반도체 패키지 기판(100)과 연결될 수 있다. 또한, 제1 반도체 소자(310)와 제2 반도체 소자(320) 상에는 제2 접속부(420)가 배치될 수 있다.The second semiconductor device 320 is disposed on the conductive coupling portion 450 of the first semiconductor package substrate 100. At this time, the second semiconductor device 320 may be connected to the first semiconductor package substrate 100 through the conductive coupling portion 450. Additionally, a second connection portion 420 may be disposed on the first semiconductor device 310 and the second semiconductor device 320.
이에 따라, 제2 반도체 소자(320)는 제2 접속부(420)를 통해 제1 반도체 소자(310)와 전기적으로 연결될 수 있다. Accordingly, the second semiconductor device 320 may be electrically connected to the first semiconductor device 310 through the second connection portion 420.
즉, 제2 반도체 소자(320)는 도전성 결합부(450)을 통해 제1 반도체 패키지 기판(100)과 연결되면서, 제2 접속부(420)를 통해 제1 반도체 소자(310)와도 연결된다. That is, the second semiconductor device 320 is connected to the first semiconductor package substrate 100 through the conductive coupling portion 450 and is also connected to the first semiconductor device 310 through the second connection portion 420.
이때, 제2 반도체 소자(320)는 도전성 결합부(450)을 통해 전원신호를 제공받을 수 있다. 또한, 제2 반도체 소자(320)는 제2 접속부(420)를 통해 제1 반도체 소자(310)와 통신 신호를 주고받을 수 있다.At this time, the second semiconductor device 320 can receive a power signal through the conductive coupling portion 450. Additionally, the second semiconductor device 320 may exchange communication signals with the first semiconductor device 310 through the second connection unit 420.
제6 실시 예의 반도체 패키지는 도전성 결합부(450)를 통해 제2 반도체 소자(320)에 전원신호를 제공함으로써, 제2 반도체 소자(320)의 구동을 위한 충분한 전원의 제공이 가능하다. 이에 따라, 실시 예는 제2 반도체 소자(320)의 구동 특성을 향상시킬 수 있다. 즉, 실시 예는 제2 반도체 소자(320)에 제공되는 전원이 부족 문제를 해결할 수 있다. 나아가, 실시 예는 제2 반도체 소자(320)의 전원 신호 및 통신 신호가 도전성 결합부(450)와 제2 접속부(420)를 통해 서로 다른 경로를 통해 제공되도록 한다. 이를 통해, 실시 예는 전원 신호에 의해 통신 신호의 손실이 발생하는 문제를 해결할 수 있다. 예를 들어, 실시 예는 전원 신호의 통신 신호 사이의 상호 간섭을 최소화할 수 있다. 한편, 제6 실시 예에서의 제2 반도체 소자(320)는 POP(Package On Package) 구조를 가지고 제1 반도체 패키지 기판(100) 상에 배치될 수 있다. 예를 들어, 제2 반도체 소자(320)는 메모리 칩을 포함하는 메모리 패키지일 수 있다. 그리고 메모리 패키지는 도전성 결합부(450) 상에 결합될 수 있다. 이때, 메모리 패키지는 제1 반도체 소자(310)와는 연결되지 않을 수 있다. 예를 들어, POP 구조의 경우, 제2 접속부(420)는 생략될 수 있다.The semiconductor package of the sixth embodiment provides a power signal to the second semiconductor device 320 through the conductive coupling portion 450, thereby providing sufficient power to drive the second semiconductor device 320. Accordingly, the embodiment can improve the driving characteristics of the second semiconductor device 320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 320. Furthermore, the embodiment allows the power signal and communication signal of the second semiconductor device 320 to be provided through different paths through the conductive coupling portion 450 and the second connection portion 420. Through this, the embodiment can solve the problem of loss of communication signals caused by power signals. For example, embodiments may minimize mutual interference between power signals and communication signals. Meanwhile, the second semiconductor device 320 in the sixth embodiment may have a POP (Package On Package) structure and be disposed on the first semiconductor package substrate 100. For example, the second semiconductor device 320 may be a memory package including a memory chip. And the memory package may be coupled to the conductive coupling portion 450. At this time, the memory package may not be connected to the first semiconductor device 310. For example, in the case of a POP structure, the second connection unit 420 may be omitted.
한편, 제6 실시 예에서의 반도체 패키지는 몰딩 부재(1460)를 포함할 수 있다. 몰딩 부재(1460)는 제1 기판(1100)과 제2 반도체 소자(1320) 사이에 배치될 수 있다. 예를 들어, 몰딩 부재(1460)는 제1 접속부(1410), 제2 접속부(1420), 제1 반도체 소자(1310) 및 도전성 결합부(1450)를 몰딩할 수 있다.Meanwhile, the semiconductor package in the sixth embodiment may include a molding member 1460. The molding member 1460 may be disposed between the first substrate 1100 and the second semiconductor device 1320. For example, the molding member 1460 may mold the first connection part 1410, the second connection part 1420, the first semiconductor device 1310, and the conductive coupling part 1450.
도 2g를 참조하면, 제7 실시 예의 반도체 패키지는 제1 반도체 패키지 기판(100), 제1 접속부(410), 제1 접속부(410), 반도체 소자(300) 및 제3 접속부(430)를 포함한다. Referring to FIG. 2G, the semiconductor package of the seventh embodiment includes a first semiconductor package substrate 100, a first connection part 410, a first connection part 410, a semiconductor device 300, and a third connection part 430. do.
이때, 제7 실시 예의 반도체 패키지는 제4 실시 예의 반도체 패키지 대비 연결 부재(110)가 제거되면서, 제1 반도체 패키지 기판(100)이 복수의 기판층을 포함하는 것에서 차이가 있다.At this time, the semiconductor package of the seventh embodiment differs from the semiconductor package of the fourth embodiment in that the connecting member 110 is removed and the first semiconductor package substrate 100 includes a plurality of substrate layers.
제1 반도체 패키지 기판(100)은 복수의 기판층을 포함한다. 예를 들어, 제1 반도체 패키지 기판(100)은 패키지 기판에 대응하는 제1 기판층(100A)과 연결 부재의 재배선층에 대응하는 제2 기판층(100B)을 포함할 수 있다.The first semiconductor package substrate 100 includes a plurality of substrate layers. For example, the first semiconductor package substrate 100 may include a first substrate layer 100A corresponding to the package substrate and a second substrate layer 100B corresponding to the redistribution layer of the connection member.
즉, 제1 반도체 패키지 기판(100)은 제1 기판층(100A) 상에 재배선층에 대응하는 제2 기판층(100B)을 배치한다. That is, the first semiconductor package substrate 100 arranges the second substrate layer 100B corresponding to the redistribution layer on the first substrate layer 100A.
다시 말해서, 제7 실시 예의 반도체 패키지는 일체로 형성된 제1 기판층(100A) 및 제2 기판층(100B)을 포함한 반도체 패키지 기판을 포함한다. 제2 기판층(100B)의 절연층의 물질은 제1 기판층(100A)의 절연층의 물질과 다를 수 있다. 예를 들어, 제2 기판층(100B)의 절연층의 물질은 광경화성 물질을 포함할 수 있다. 예를 들어, 제2 기판층(100B)은 PID(Photo Imageable Dielectric)일 수 있다. 그리고, 제2 기판층(100B)은 광경화성 물질을 포함함에 따라 전극의 미세화가 가능하다. 따라서, 제7 실시 예는 제1 기판층(100A) 상에 광 경화성 물질의 절연층을 순차적으로 적층하고, 광 경화성 물질의 절연층 상에 미세화된 전극을 형성하는 것에 의해 제2 기판층(100B)을 형성할 수 있다. 이를 통해 제2 기판(100B)은 미세화된 전극을 포함하는 재배선층일 수 있다.In other words, the semiconductor package of the seventh embodiment includes a semiconductor package substrate including a first substrate layer 100A and a second substrate layer 100B formed integrally. The material of the insulating layer of the second substrate layer 100B may be different from the material of the insulating layer of the first substrate layer 100A. For example, the material of the insulating layer of the second substrate layer 100B may include a photocurable material. For example, the second substrate layer 100B may be a photo imageable dielectric (PID). In addition, since the second substrate layer 100B contains a photocurable material, the electrode can be miniaturized. Accordingly, the seventh embodiment sequentially stacks an insulating layer of a photo-curable material on the first substrate layer 100A and forms a micronized electrode on the insulating layer of a photo-curable material to form a second substrate layer 100B. ) can be formed. Through this, the second substrate 100B may be a redistribution layer including miniaturized electrodes.
이하에서는 실시 예의 반도체 패키지 기판에 대해 설명한다.Hereinafter, a semiconductor package substrate of an example will be described.
실시 예의 반도체 패키지 기판의 설명에 앞서, 이하에서 설명되는 반도체 패키지 기판은 이전의 반도체 패키지에 포함된 복수의 반도체 패키지 기판 중 어느 하나의 반도체 패키지 기판을 의미할 수 있다.Before describing the semiconductor package substrate of the embodiment, the semiconductor package substrate described below may refer to any one of a plurality of semiconductor package substrates included in a previous semiconductor package.
예를 들어, 일 실시 예에서의 이하에서 설명되는 반도체 패키지 기판은 도 2a 내지 2g 중 어느 하나에 도시된 제1 반도체 패키지 기판(100) 및/또는 제2 반도체 패키지 기판(200)을 의미할 수 있다. For example, in one embodiment, the semiconductor package substrate described below may refer to the first semiconductor package substrate 100 and/or the second semiconductor package substrate 200 shown in any one of FIGS. 2A to 2G. there is.
도 3a는 제1 실시 예에 따른 반도체 패키지 기판을 나타낸 도면이고, 도 3b는 제2 실시 예에 따른 반도체 패키지 기판을 나타낸 도면이다.FIG. 3A is a diagram showing a semiconductor package substrate according to a first embodiment, and FIG. 3B is a diagram showing a semiconductor package substrate according to a second embodiment.
이하에서는 도 3a를 참조하여, 실시 예에 따른 반도체 패키지 기판에 대해 간략하게 설명하고, 도 3a와 상이한 일부 구성에 대해서는 도 3b를 참조하여 설명한다.Hereinafter, a semiconductor package substrate according to an embodiment will be briefly described with reference to FIG. 3A, and some configurations different from FIG. 3A will be described with reference to FIG. 3B.
실시 예의 반도체 패키지 기판(500)은 절연층(510)을 포함한다. 이때, 실시 예의 절연층(510)은 다층 구조를 가질 수 있다. 예를 들어, 실시 예의 반도체 패키지 기판의 절연층(510)은 제1 절연층(511), 제2 절연층(512) 및 제3 절연층(513)을 포함할 수 있다. 도 3에서는 제2 절연층(512), 및 제3 절연층(513)이 하나의 층으로 도시되어 있으나, 이에 한정하지 않고 복수의 절연층이 적층된 구성일 수 있다.The semiconductor package substrate 500 of the embodiment includes an insulating layer 510. At this time, the insulating layer 510 of the embodiment may have a multilayer structure. For example, the insulating layer 510 of the semiconductor package substrate of the embodiment may include a first insulating layer 511, a second insulating layer 512, and a third insulating layer 513. In FIG. 3 , the second insulating layer 512 and the third insulating layer 513 are shown as one layer, but the present invention is not limited to this and may be a configuration in which a plurality of insulating layers are stacked.
제1 절연층(511)은 제2 절연층(512) 및 제3 절연층(513)과는 다른 절연물질을 포함할 수 있다.The first insulating layer 511 may include an insulating material different from the second insulating layer 512 and the third insulating layer 513.
예를 들어, 제1 절연층(511)은 강화 섬유를 포함하는 절연물질을 포함할 수 있고, 코어층일 수 있다. For example, the first insulating layer 511 may include an insulating material including reinforcing fibers and may be a core layer.
예를 들어, 제1 절연층(511)은 프리프레그를 포함할 수 있다. 제1 절연층(511)은 반도체 패키지 기판의 물리적 강도를 증가시켜 휨 특성을 향상시킬 수 있다.For example, the first insulating layer 511 may include prepreg. The first insulating layer 511 can improve bending characteristics by increasing the physical strength of the semiconductor package substrate.
실시 예의 제1 절연층(511)은 유리 섬유 실(glass yarn)로 직조된 글라스 패브릭(glass fabric)과 같은 직물 시트(fabric sheet) 형태의 섬유층에 에폭시 수지 등을 함침된 구조를 가질 수 있다. The first insulating layer 511 of the embodiment may have a structure in which a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, is impregnated with an epoxy resin or the like.
또한, 실시 예의 제1 절연층(511)을 구성하는 프리프레그는 탄소 섬유 실로 직조된 직물 시트 형태의 섬유층을 포함할 수 있을 것이다. Additionally, the prepreg constituting the first insulating layer 511 of the embodiment may include a fiber layer in the form of a fabric sheet woven with carbon fiber thread.
구체적으로, 제1 절연층(511)은 수지 및 수지 내에 배치되는 강화 섬유를 포함할 수 있다. 수지는 에폭시 수지일 수 있으나, 이에 한정되는 것은 아니다. 수지는 에폭시 수지에 특별히 제한되지 않으며, 예를 들어 분자 내에 에폭시기가 1개 이상 포함될 수 있고, 이와 다르게 에폭시계가 2개 이상 포함될 수 있으며, 이와 다르게 에폭시계가 4개 이상 포함될 수 있을 것이다. 또한, 제1 절연층(511)을 구성하는 수지는 나프탈렌(naphthalene)기가 포함될 수 있으며, 예를 들어, 방향족 아민형일 수 있으나, 이에 한정되는 것은 아니다. 예를 들어, 수지는 비스페놀 A형 에폭시 수지, 비스페놀 F형 에폭시 수지, 비스페놀 S형 에폭시 수지, 페놀 노볼락형 에폭시 수지, 알킬페놀 노볼락형 에폭시 수지, 비페닐형 에폭시 수지, 아르알킬형 에폭시 수지, 디사이클로펜타디엔형 에폭시 수지, 나프탈렌형 에폭시 수지, 나프톨형 에폭시 수지, 페놀류와 페놀성 히드록실기를 갖는 방향족 알데히드와의 축합물의 에폭시 수지, 비페닐아르알킬형 에폭시 수지, 플루오렌형 에폭시 수지, 크산텐형 에폭시 수지, 트리글리시딜이소시아누레이트, 고무 변성형 에폭시 수지 및 인(phosphorous)계 에폭시 수지 등을 들 수 있으며, 나프탈렌계 에폭시 수지, 비스페놀 A형 에폭시 수지, 페놀 노볼락 에폭시 수지, 크레졸 노볼락 에폭시 수지, 고무 변성형 에폭시 수지, 및 인(phosphorous)계 에폭시 수지를 포함할 수 있다. 또한, 강화 섬유는 유리 섬유, 탄소 섬유, 아라미드 섬유(예를 들어, 아라미드 계열의 유기 재료), 나일론(nylon), 실리카(silica) 계열의 무기 재료 또는 티타니아(titania) 계열의 무기 재료가 사용될 수 있다. 강화 섬유는 수지 내에서, 평면 방향으로 서로 교차하는 형태로 배열될 수 있다.Specifically, the first insulating layer 511 may include a resin and reinforcing fibers disposed within the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to epoxy resin, and for example, it may contain one or more epoxy groups in the molecule, alternatively, it may contain two or more epoxy groups, and alternatively, it may contain four or more epoxy groups. Additionally, the resin constituting the first insulating layer 511 may contain a naphthalene group, for example, may be an aromatic amine type, but is not limited thereto. For example, the resins include bisphenol A-type epoxy resin, bisphenol F-type epoxy resin, bisphenol S-type epoxy resin, phenol novolak-type epoxy resin, alkylphenol novolak-type epoxy resin, biphenyl-type epoxy resin, and aralkyl-type epoxy resin. , dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of condensate of phenols and aromatic aldehyde having a phenolic hydroxyl group, biphenylaralkyl type epoxy resin, fluorene type epoxy resin. , xanthene-type epoxy resin, triglycidyl isocyanurate, rubber-modified epoxy resin, and phosphorous-based epoxy resin, etc., naphthalene-type epoxy resin, bisphenol A-type epoxy resin, phenol novolak epoxy resin, It may include cresol novolac epoxy resin, rubber-modified epoxy resin, and phosphorous-based epoxy resin. In addition, the reinforcing fiber may be glass fiber, carbon fiber, aramid fiber (e.g., aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material. there is. Reinforcing fibers may be arranged within the resin in a form that intersects each other in a planar direction.
한편, 유리 섬유, 탄소 섬유, 아라미드 섬유(예를 들어, 아라미드 계열의 유기 재료), 나일론(nylon), 실리카(silica) 계열의 무기 재료 또는 티타니아(titania) 계열의 무기 재료가 사용될 수 있다.Meanwhile, glass fiber, carbon fiber, aramid fiber (for example, aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material may be used.
이때, 제1 절연층(511)에는 강화 섬유가 적어도 2층 이상 구비될 수 있다. 이를 통해, 실시 예는 기판(500)의 강성을 더욱 향상시킬 수 있다.At this time, the first insulating layer 511 may be provided with at least two layers of reinforcing fibers. Through this, the embodiment can further improve the rigidity of the substrate 500.
제1 절연층(511)의 수직 방향의 두께는 제2 절연층(512) 및 제3 절연층(513) 중 적어도 하나의 수직 방향의 두께보다 클 수 있다. 예를 들어, 제1 절연층(511)의 수직 방향의 두께는 제2 절연층(512)의 및 제3 절연층(513)의 수직 방향의 두께의 3배 이상, 4배 이상, 5배 이상, 7배 이상 또는 10배 이상일 수 있다. The vertical thickness of the first insulating layer 511 may be greater than the vertical thickness of at least one of the second insulating layer 512 and the third insulating layer 513. For example, the vertical thickness of the first insulating layer 511 is 3 times or more, 4 times or more, or 5 times or more than the vertical thickness of the second insulating layer 512 and the third insulating layer 513. , may be 7 times or more or 10 times or more.
최근 반도체 패키지의 고성능화가 진행되면서, 반도체 패키지 기판의 절연층의 층수도 증가하고 있다. 예를 들어, 반도체 패키지 기판의 절연층의 층수는 10층 이상, 12층 이상, 16층 이상, 또는 20층 이상을 가질 수 있다. 구체적으로, 제2 절연층(512) 및 제3 절연층(513)이 도시된 바와 다르게 각각 복수의 층으로 적층되는 경우, 각 절연층의 응력에 의해 반도체 패키지 기판에 휨이 발생할 수 있다. 반도체 패키지 기판이 휘어지는 경우, 반도체 패키지 기판에 포함되는 관통 전극을 정확한 위치에 형성하기 어려울 수 있다. 또한, 반도체 패키지 기판이 휘어지는 경우, 반도체 패키지 기판 상에 반도체 소자를 실장하는 공정에서의 반도체 소자의 위치가 틀어지는 등의 문제가 발생할 수 있다. 따라서, 반도체 패키지 기판의 휨을 방지하기 위해 제1 절연층(511)의 수직 방향의 두께는 250㎛ 이상이 될 수 있다. 이에 따라 반도체 패키지 기판의 물리적 강성을 증가시키면서, 패키지 공정에서 반도체 패키지 기판의 휨 특성을 향상시키기 위해 제1 절연층(511)은 250㎛ 이상의 수직 방향의 두께를 가질 수 있다. 또한, 제1 절연층(511)의 두께가 너무 두꺼워질 경우, 제1 절연층(511)에 관통 홀을 형성하는 공정이 어려워지고, 반도체 소자로 인가되는 신호 및/또는 전원 등의 전기적 특성이 저하될 수 있다. 또한, 반도체 패키지의 슬림화가 어려워질 수 있어, 전자 디바이스의 볼륨을 작게 구비하는 데에 어려움이 있을 수 있다. 따라서, 제1 절연층(511)의 수직 방향의 두께는 1200㎛ 이하로 구비하는 것이 적절하다.Recently, as the performance of semiconductor packages progresses, the number of insulating layers of the semiconductor package substrate is also increasing. For example, the number of insulating layers of a semiconductor package substrate may be 10 or more layers, 12 or more layers, 16 or more layers, or 20 or more layers. Specifically, when the second insulating layer 512 and the third insulating layer 513 are each stacked as a plurality of layers as shown, bending of the semiconductor package substrate may occur due to the stress of each insulating layer. When the semiconductor package substrate is bent, it may be difficult to form the through electrode included in the semiconductor package substrate at an accurate position. Additionally, when the semiconductor package substrate is bent, problems such as the position of the semiconductor device being distorted during the process of mounting the semiconductor device on the semiconductor package substrate may occur. Therefore, in order to prevent bending of the semiconductor package substrate, the vertical thickness of the first insulating layer 511 may be 250 μm or more. Accordingly, in order to increase the physical rigidity of the semiconductor package substrate and improve the bending characteristics of the semiconductor package substrate during the packaging process, the first insulating layer 511 may have a vertical thickness of 250 μm or more. In addition, when the thickness of the first insulating layer 511 becomes too thick, the process of forming a through hole in the first insulating layer 511 becomes difficult, and electrical characteristics such as signals and/or power applied to the semiconductor device decrease. may deteriorate. Additionally, it may become difficult to slim the semiconductor package, which may lead to difficulties in providing electronic devices with a small volume. Therefore, it is appropriate that the vertical thickness of the first insulating layer 511 is 1200 μm or less.
제2 절연층(512) 및 제3 절연층(513)은 제1 절연층(511)과는 다른 절연물질을 포함할 수 있다. 예를 들어, 제2 절연층(512) 및 제3 절연층(513)은 강화 섬유를 포함하지 않을 수 있으나, 이에 한정되는 것은 아니다. The second insulating layer 512 and the third insulating layer 513 may include an insulating material different from the first insulating layer 511. For example, the second insulating layer 512 and the third insulating layer 513 may not include reinforcing fibers, but are not limited thereto.
예를 들어, 제2 절연층(512) 및 제3 절연층(513)은 ABF(Ajinomoto Build-up Film), FR-4, BT(Bismaleimide Triazine), PID(Photo Imageable Dielectric resin), BT 등 중 어느 하나를 포함할 수 있다. For example, the second insulating layer 512 and the third insulating layer 513 are made of ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. It can include either one.
또한, 제2 절연층(512) 및 제3 절연층(513)에는 강화 섬유를 포함할 수 있고, 강화 섬유는 유리 섬유일 수 있고, GCP(Glass Core Primer) 물질을 포함할 수 있으나, 이에 한정되는 것은 아니다.In addition, the second insulating layer 512 and the third insulating layer 513 may include reinforcing fibers, and the reinforcing fibers may be glass fibers and may include a GCP (Glass Core Primer) material, but are limited thereto. It doesn't work.
나아가, 제2 절연층(512) 및 제3 절연층(513)은 CCL(Copper Clad Laminate) 타입의 절연층을 사용할 수 있으나, 이에 한정되는 것은 아니다.Furthermore, the second insulating layer 512 and the third insulating layer 513 may use a CCL (Copper Clad Laminate) type insulating layer, but are not limited thereto.
제2 절연층(512) 및 제3 절연층(513)은 10㎛ 내지 50㎛의 범위의 수직 방향의 두께를 가질 수 있다. 제2 절연층(512) 또는 제3 절연층(513)의 수직 방향의 두께가 10㎛ 미만이면, 반도체 패키지 기판(500)의 휨 특성이 저하될 수 있다. 또한, 제2 절연층(512) 또는 제3 절연층(513)의 수직 방향의 두께가 10㎛ 미만이면, 반도체 패키지 기판(500)에 포함된 회로 패턴층이 안정적으로 보호되지 못하거나 절연 특성이 저하될 수 있고, 이에 의해 전기적 신뢰성이 저하될 수 있다. 또한, 제2 절연층(512) 또는 제3 절연층(513)의 수직 방향의 두께가 50㎛를 초과하면, 반도체 패키지 기판(500)의 전체적인 두께가 증가하고, 이에 따라 반도체 패키지의 두께가 증가할 수 있다. 또한, 제2 절연층(512) 또는 제3 절연층(513)의 두께가 50㎛를 초과하면, 반도체 패키지 기판(500)의 회로 패턴층의 미세화가 어려울 수 있다.The second insulating layer 512 and the third insulating layer 513 may have a vertical thickness ranging from 10 μm to 50 μm. If the vertical thickness of the second insulating layer 512 or the third insulating layer 513 is less than 10 μm, the bending characteristics of the semiconductor package substrate 500 may deteriorate. In addition, if the vertical thickness of the second insulating layer 512 or the third insulating layer 513 is less than 10㎛, the circuit pattern layer included in the semiconductor package substrate 500 may not be stably protected or the insulating properties may be poor. may deteriorate, thereby reducing electrical reliability. In addition, when the vertical thickness of the second insulating layer 512 or the third insulating layer 513 exceeds 50㎛, the overall thickness of the semiconductor package substrate 500 increases, and thus the thickness of the semiconductor package increases. can do. Additionally, if the thickness of the second insulating layer 512 or the third insulating layer 513 exceeds 50 μm, it may be difficult to miniaturize the circuit pattern layer of the semiconductor package substrate 500.
수직 방향의 두께는 반도체 패키지 기판(500)의 상면에서 하면을 향하는 방향 또는 하면에서 상면을 향하는 방향의 길이를 의미할 수 있다. 여기에서, 상면은 각 구성요소에서 수직 방향을 따라 가장 높은 위치를 의미할 수 있고, 하면은 각 구성요소에서 수직 방향을 따라 가장 낮은 위치를 의미할 수 있다. 그리고 이의 위치는 서로 반대로 지칭될 수 있다.The thickness in the vertical direction may refer to the length from the top to the bottom of the semiconductor package substrate 500 or from the bottom to the top. Here, the upper surface may mean the highest position in each component along the vertical direction, and the lower surface may mean the lowest position in each component along the vertical direction. And their positions can be referred to as opposites to each other.
한편, 도면상에는 제2 절연층(512) 및 제3 절연층(513)이 각각 1층으로 구성되는 것으로 도시하였으나, 이에 한정되는 것은 아니다. 예를 들어 실시 예의 반도체 패키지 기판(500)은 절연층의 층수를 기준으로 11층의 구조를 가질 수 있다. 이 경우, 제2 절연층(512) 및 제3 절연층(513)은 각각 5층으로 구성될 수 있다. 예를 들어, 실시 예의 반도체 패키지 기판(500)은 절연층의 층수를 기준으로 17층의 구조를 가질 수 있다. 이 경우, 제2 절연층(512) 및 제3 절연층(513) 각각은 8층으로 구성될 수 있다.Meanwhile, in the drawing, the second insulating layer 512 and the third insulating layer 513 are each shown as consisting of one layer, but this is not limited to this. For example, the semiconductor package substrate 500 of the embodiment may have an 11-layer structure based on the number of insulating layers. In this case, the second insulating layer 512 and the third insulating layer 513 may each be composed of five layers. For example, the semiconductor package substrate 500 of the embodiment may have a 17-layer structure based on the number of insulating layers. In this case, each of the second insulating layer 512 and the third insulating layer 513 may be composed of 8 layers.
반도체 패키지 기판(500)은 절연층(510) 상에 배치된 회로 패턴층을 포함할 수 있다. The semiconductor package substrate 500 may include a circuit pattern layer disposed on the insulating layer 510 .
반도체 패키지 기판(500)은 제1 절연층(511)의 상면에 배치된 제1 회로 패턴층(521)을 포함할 수 있다. 반도체 패키지 기판(500)은 제1 절연층(511)의 하면에 배치된 제2 회로 패턴층(522)을 포함할 수 있다. 반도체 패키지 기판(500)은 제2 절연층(512)의 상면에 배치된 제3 회로 패턴층(523)을 포함할 수 있다. 반도체 패키지 기판(500)은 제3 절연층(513)의 하면에 배치된 제4 회로 패턴층(524)을 포함할 수 있다. The semiconductor package substrate 500 may include a first circuit pattern layer 521 disposed on the top of the first insulating layer 511. The semiconductor package substrate 500 may include a second circuit pattern layer 522 disposed on the lower surface of the first insulating layer 511. The semiconductor package substrate 500 may include a third circuit pattern layer 523 disposed on the second insulating layer 512 . The semiconductor package substrate 500 may include a fourth circuit pattern layer 524 disposed on the lower surface of the third insulating layer 513.
회로 패턴층들 중 최상측에 배치된 제3 회로 패턴층(523)은 반도체 소자가 배치되는 전극 패턴을 포함할 수 있다. 이때, 도 3b에 도시된 바와 같이, 반도체 패키지 기판은 제3 회로 패턴층(523)의 전극 패턴 상에 배치되고 반도체 소자를 향하여 돌출된 돌출부(590)를 포함할 수 있다. 돌출부(590)는 범프(bump)라고 할 수 있다. 돌출부(590)는 포스트(post)라고도 할 수 있다. 돌출부(590)는 필라(pillar)라고도 할 수 있다. 즉, 반도체 소자의 단자의 피치가 미세화되면서, 전극 패턴과 반도체 소자의 단자 사이에 배치되는 도전성 접착제에 열과 압력을 인가하여 결합시키는 TC(Thermal Compression) 본딩을 이용할 수 있다. TC(Thermal Compression) 본딩을 이용하는 경우, 돌출부(590)는 전극 패턴과 반도체 소자의 단자 사이의 정합도 및 도전성 접착제의 확산을 방지하기 위한 기능을 할 수도 있다. 또한, 복수의 단자에 각각 배치되는 도전성 접착제의 볼륨을 줄일 수 있어, 미세한 단자의 피치로 인한 전기적 단락 문제를 방지할 수 있다. 여기서, 도전성 접착제는 예시적으로 솔더가 이용될 수 있으나, 이에 한정되지 않는다.The third circuit pattern layer 523 disposed on the uppermost side among the circuit pattern layers may include an electrode pattern on which a semiconductor device is disposed. At this time, as shown in FIG. 3B, the semiconductor package substrate may be disposed on the electrode pattern of the third circuit pattern layer 523 and include a protrusion 590 that protrudes toward the semiconductor device. The protrusion 590 may be referred to as a bump. The protrusion 590 may also be referred to as a post. The protrusion 590 may also be referred to as a pillar. That is, as the pitch of the terminals of semiconductor devices becomes finer, TC (Thermal Compression) bonding, which bonds the electrode pattern to the terminals of the semiconductor devices by applying heat and pressure to the conductive adhesive disposed between them, can be used. When using TC (Thermal Compression) bonding, the protrusion 590 may function to improve alignment between the electrode pattern and the terminal of the semiconductor device and to prevent diffusion of the conductive adhesive. Additionally, the volume of the conductive adhesive disposed on each of the plurality of terminals can be reduced, thereby preventing electrical short-circuit problems due to the fine pitch of the terminals. Here, solder may be used as the conductive adhesive, but is not limited thereto.
회로 패턴층들(521, 522, 523, 524)은 금(Au), 은(Ag), 백금(Pt), 티타늄(Ti), 주석(Sn), 구리(Cu) 및 아연(Zn) 중에서 선택되는 적어도 하나의 금속물질을 포함할 수 있다. 회로 패턴층들(521, 522, 523, 524)은 본딩력이 우수한 금(Au), 은(Ag), 백금(Pt), 티타늄(Ti), 주석(Sn), 구리(Cu), 아연(Zn) 중에서 선택되는 적어도 하나의 금속 물질을 포함하는 페이스트 또는 솔더 페이스트를 포함할 수 있다. 바람직하게, 회로 패턴층들(521, 522, 523, 524)은 전기전도성이 높으면서 가격이 비교적 저렴한 구리(Cu)로 형성될 수 있다. The circuit pattern layers 521, 522, 523, and 524 are selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It may contain at least one metal material. The circuit pattern layers 521, 522, 523, and 524 are made of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (which have excellent bonding properties). It may include a paste or solder paste containing at least one metal material selected from Zn). Preferably, the circuit pattern layers 521, 522, 523, and 524 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.
회로 패턴층들(521, 522, 523, 524)은 10㎛ 내지 25㎛의 범위의 두께를 가질 수 있다. 회로 패턴층들(521, 522, 523, 524)의 두께는 수직 방향의 두께를 의미할 수 있다.The circuit pattern layers 521, 522, 523, and 524 may have a thickness ranging from 10 μm to 25 μm. The thickness of the circuit pattern layers 521, 522, 523, and 524 may refer to the thickness in the vertical direction.
회로 패턴층들(521, 522, 523, 524)의 두께가 10㎛ 미만이면, 회로 패턴층들(521, 522, 523, 524)의 저항이 증가하고, 전송 가능한 신호의 허용 전류가 감소할 수 있다. 또한, 회로 패턴층들(521, 522, 523, 524)의 두께가 25㎛을 초과하면, 회로 패턴층들(521, 522, 523, 524)의 미세화가 어려울 수 있다. 회로 패턴층들(521, 522, 523, 524)의 두께가 25㎛을 초과하면, 이에 대응하게 절연층(510)의 두께가 증가해야하고, 상술한 바와 같이 절연층의 절연 기능 및/또는 보호 기능을 위해서는 각 절연층의 두께가 두꺼워져야 한다. 따라서, 반도체 패키지 기판 및 반도체 패키지의 두께가 증가할 수 있고, 반도체 패키지 기판의 휨을 완화하기 어려워질 수 있다.If the thickness of the circuit pattern layers 521, 522, 523, and 524 is less than 10 μm, the resistance of the circuit pattern layers 521, 522, 523, and 524 may increase, and the allowable current of the transmittable signal may decrease. there is. Additionally, if the thickness of the circuit pattern layers 521, 522, 523, and 524 exceeds 25㎛, it may be difficult to miniaturize the circuit pattern layers 521, 522, 523, and 524. If the thickness of the circuit pattern layers 521, 522, 523, and 524 exceeds 25㎛, the thickness of the insulating layer 510 must increase correspondingly, and the insulating function and/or protection of the insulating layer as described above. In order to function, the thickness of each insulating layer must be thick. Accordingly, the thickness of the semiconductor package substrate and the semiconductor package may increase, and it may become difficult to alleviate the bending of the semiconductor package substrate.
회로 패턴층들(521, 522, 523, 524)은 반도체 패키지 기판(500)의 관통 전극과 연결되는 패드, 외부 기판이나 반도체 소자와 연결되는 적어도 하나의 전극 패턴을 포함할 수 있다. 또한, 회로 패턴층들(521, 522, 523, 524)은 패드나 전극 패턴과 연결되는 신호 전송 라인의 트레이스를 포함할 수 있다. The circuit pattern layers 521, 522, 523, and 524 may include a pad connected to a through electrode of the semiconductor package substrate 500 and at least one electrode pattern connected to an external substrate or semiconductor device. Additionally, the circuit pattern layers 521, 522, 523, and 524 may include traces of signal transmission lines connected to pads or electrode patterns.
회로 패턴층들(521, 522, 523, 524)은 통상적인 반도체 패키지 기판의 제조 공정인 어디티브 공법(Additive process), 서브트렉티브 공법(Subtractive Process), MSAP(Modified Semi Additive Process) 및 SAP(Semi Additive Process) 공법 등으로 가능하며 여기에서는 상세한 설명은 생략한다.The circuit pattern layers 521, 522, 523, and 524 are manufactured using typical semiconductor package substrate manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP ( This is possible using the Semi Additive Process (Semi Additive Process) method, and detailed explanations are omitted here.
반도체 패키지 기판(500)은 제1 절연층(511)을 관통하는 제1 관통 전극(530)을 포함할 수 있다. 예를 들어, 제1 절연층(511)은 상면 및 하면을 관통하는 제1 관통 홀을 포함할 수 있다. 그리고 제1 관통 전극(530)은 제1 절연층(511)의 제1 관통 홀의 적어도 일부를 채우며 구비될 수 있다. 또한, 반도체 패키지 기판(500)은 제1 절연층(511)의 제1 관통 홀의 나머지 일부를 채우는 절연 부재(540)는 제1 관통 전극(530)이 제1 관통 홀을 전체적으로 채우지 못하는 경우, 제1 회로 패턴층(521)의 평탄도를 개선하기 위해 배치될 수 있고, 제1 관통 전극(530)은 절연부재(540)와 제1 절연층(511) 사이에 위치하도록 배치될 수 있다. 절연 부재(540)는 홀 플러깅층이라고 할 수 있다. 절연 부재(540)는 절연물질을 포함할 수 있다. 예를 들어, 절연 부재(540)는 절연성 잉크 재질의 페이스트일 수 있다. 예를 들어, 절연 부재(540)는 플러깅 잉크일 수 있다. 다만, 실시 예는 이에 한정되지 않는다. 예를 들어, 절연 부재(540)는 도전성 물질을 포함할 수 있다. 예를 들어, 절연 부재(540)는 전도성 금속 분말이 함유된 도전성 페이스트를 포함할 수도 있을 것이다.The semiconductor package substrate 500 may include a first through electrode 530 that penetrates the first insulating layer 511 . For example, the first insulating layer 511 may include a first through hole penetrating the upper and lower surfaces. And the first through electrode 530 may be provided to fill at least a portion of the first through hole of the first insulating layer 511. In addition, the semiconductor package substrate 500 has an insulating member 540 that fills the remaining portion of the first through hole of the first insulating layer 511, and when the first through electrode 530 does not entirely fill the first through hole, 1 It may be arranged to improve the flatness of the circuit pattern layer 521, and the first through electrode 530 may be arranged to be located between the insulating member 540 and the first insulating layer 511. The insulating member 540 may be referred to as a hole plugging layer. The insulating member 540 may include an insulating material. For example, the insulating member 540 may be a paste made of insulating ink material. For example, the insulating member 540 may be plugging ink. However, the embodiment is not limited to this. For example, the insulating member 540 may include a conductive material. For example, the insulating member 540 may include a conductive paste containing conductive metal powder.
반도체 패키지 기판(500)은 제2 절연층(512)을 관통하는 제2 관통 전극(550)을 포함할 수 있다. 예를 들어, 제2 절연층(512)은 상면 및 하면을 관통하는 제2 관통 홀을 포함할 수 있다. 그리고 제2 관통 전극(550)은 제2 절연층(512)의 제2 관통 홀을 전체적으로 채우며 구비될 수 있다. The semiconductor package substrate 500 may include a second through electrode 550 that penetrates the second insulating layer 512 . For example, the second insulating layer 512 may include a second through hole penetrating the upper and lower surfaces. And the second through electrode 550 may be provided to entirely fill the second through hole of the second insulating layer 512.
반도체 패키지 기판(500)은 제3 절연층(513)을 관통하는 제3 관통 전극(560)을 포함할 수 있다. 예를 들어, 제3 절연층(513)은 상면 및 하면을 관통하는 제3 관통 홀을 포함할 수 있다. 그리고 제3 관통 전극(560)은 제3 절연층(513)의 제3 관통 홀을 전체적으로 채우며 구비될 수 있다. The semiconductor package substrate 500 may include a third through electrode 560 that penetrates the third insulating layer 513. For example, the third insulating layer 513 may include a third through hole penetrating the upper and lower surfaces. And the third through electrode 560 may be provided to entirely fill the third through hole of the third insulating layer 513.
제1 관통 전극(530), 제2 관통 전극(550) 및 제3 관통 전극(560)은 서로 다른 형상을 가질 수 있다. The first through electrode 530, second through electrode 550, and third through electrode 560 may have different shapes.
제1 관통 홀, 제2 관통 홀 및 제3 관통 홀은 서로 다른 형상을 가질 수 있다. 이에 의해, 제1 관통 홀 내에 배치된 절연 부재(540)를 둘러싸는 제1 관통 전극(530)의 경사, 제2 관통 전극(550)의 경사, 및 제3 관통 전극(560)의 경사는 서로 다를 수 있다. 예시적으로, 제1 관통 전극(530)의 측면의 기울기, 제2 관통 전극(550)의 측면의 기울기, 및 제3 관통 전극(560)의 측면의 기울기는 서로 다를 수 있다. 예시적으로, 제1 관통 전극(530)의 수직 단면 형상, 제2 관통 전극(550)의 측면의 수직 단면 형상, 및 제3 관통 전극(560)의 수직 단면 형상은 서로 다를 수 있다.The first through hole, the second through hole, and the third through hole may have different shapes. As a result, the inclination of the first through electrode 530 surrounding the insulating member 540 disposed in the first through hole, the inclination of the second through electrode 550, and the inclination of the third through electrode 560 are each other. can be different. For example, the slope of the side of the first through electrode 530, the side of the second through electrode 550, and the side of the third through electrode 560 may be different from each other. For example, the vertical cross-sectional shape of the first through electrode 530, the vertical cross-sectional shape of the side of the second through electrode 550, and the vertical cross-sectional shape of the third through electrode 560 may be different from each other.
잠시, 도 5를 참조하면, , 제1 관통 홀의 내벽은 복수의 오목부와 볼록부를 포함할 수 있고, 오목부와 볼록부는 수직 방향을 따라 교번 적층된 구조로 구비될 수 있다. 여기서, 볼록부는 제1 관통홀의 수평 방향의 중심을 향하여 돌출 및/또는 볼록한 영역을 의미하고, 오목부는 이에 반대되는 방향으로 오목한 것을 의미한다. Referring to FIG. 5 for a moment, the inner wall of the first through hole may include a plurality of concave portions and convex portions, and the concave portions and convex portions may be provided in a structure in which the concave portions and convex portions are alternately stacked along the vertical direction. Here, the convex portion refers to an area that protrudes and/or is convex toward the horizontal center of the first through hole, and the concave portion refers to a concave area in the opposite direction.
이와 다르게, 제2 관통 홀은 상측에서 하측을 향하여 폭이 감소하는 형상을 가질 수 있다. 또한, 제2 관통 홀은 제1 관통홀과 다르게 복수의 오목부 및 볼록부를 포함하지 않도록 배치될 수 있다.Alternatively, the second through hole may have a shape whose width decreases from the top to the bottom. Additionally, the second through hole may be arranged not to include a plurality of concave portions and convex portions, unlike the first through hole.
또한, 제3 관통 홀은 상측에서 하측을 향하여 폭이 증가하는 형상을 가질 수 있다. 또한, 제3 관통 홀은 복수의 오목부 및 볼록부를 포함하지 않도록 배치될 수 있다. 또한, 제3 관통 홀은 제1 절연층(511)을 기준으로 제2 관통 홀과 대칭 형상을 가질 수 있으나, 이에 한정되는 것은 아니다.Additionally, the third through hole may have a shape whose width increases from the top to the bottom. Additionally, the third through hole may be arranged not to include a plurality of concave portions and convex portions. Additionally, the third through hole may have a symmetrical shape with the second through hole with respect to the first insulating layer 511, but is not limited thereto.
이때, 제1 관통 전극(530)의 수직 방향의 두께, 제1 관통 홀의 깊이, 나아가 절연 부재(540)의 수직 방향의 두께는 제1 절연층(511)의 두께에 대응할 수 있다. 이에 따라, 제1 관통 전극(530)의 수직 방향의 두께, 제1 관통 홀의 깊이, 및 절연 부재(540)의 수직 방향의 두께는 250 ㎛ 내지 1200 ㎛ 일 수 있다.At this time, the vertical thickness of the first through electrode 530, the depth of the first through hole, and the vertical thickness of the insulating member 540 may correspond to the thickness of the first insulating layer 511. Accordingly, the vertical thickness of the first through electrode 530, the depth of the first through hole, and the vertical thickness of the insulating member 540 may be 250 ㎛ to 1200 ㎛.
실시 예는 제1 절연층(511)에 레이저 장비를 이용하여 제1 관통 홀을 형성하면서, 제1 관통 홀의 수직 방향으로의 최대폭과 최소폭의 차이를 최소화할 수 있도록 한다. 여기에서, 수직 방향은 제1 절연층(511)의 상면에서 하면을 향하는 두께 방향을 의미한다.In the embodiment, a first through hole is formed in the first insulating layer 511 using a laser device, while minimizing the difference between the maximum and minimum widths of the first through hole in the vertical direction. Here, the vertical direction refers to the thickness direction from the top to the bottom of the first insulating layer 511.
종래 기술에 따르면, 제1 관통 전극(530)의 최대폭과 최소폭의 차이를 최소화하기 위해서는, 비교 예와 같이 드릴 머신 장비를 이용해야 한다. 그러나 설명한 바와 같이, 드릴 머신 장비를 이용하여 관통 홀을 형성하는 경우, 관통 홀의 내벽의 경사가 수직에 가까워 제1 관통 전극의 최대폭과 최소폭의 차이를 최소화할 수는 있으나, 생산성 저하, 수율 저하, 및 공정 단가 상승과 같은 문제가 있다.According to the prior art, in order to minimize the difference between the maximum and minimum widths of the first through electrode 530, drill machine equipment must be used as in the comparative example. However, as explained, when forming a through hole using drill machine equipment, the slope of the inner wall of the through hole is close to vertical, so the difference between the maximum and minimum width of the first through electrode can be minimized, but productivity and yield are reduced. , and there are problems such as an increase in process costs.
따라서, 실시 예는 드릴 머신 장비가 아닌 레이저 장비를 이용하여 제1 절연층(511)의 최대폭과 최소폭의 차이가 최소화된 관통 홀을 형성한다.Accordingly, in the embodiment, a through hole is formed in which the difference between the maximum and minimum widths of the first insulating layer 511 is minimized using a laser device rather than a drill machine device.
이를 위해, 실시 예는 제1 절연층(511)에 제1 관통 홀을 형성하기 위해 복수의 좌표 코드(예를 들어, T-code)를 이용한다. 즉, 레이저 장비를 이용하는 경우, 비교 예는 1개의 좌표 코드만을 이용하여 제1 절연층(511)에 대응하는 코어층에 관통 홀을 형성하였다. 이에 따라, 관통 홀을 형성하는 공정에 있어서, 공정 중 레이저 공정 조건을 변경하는 것이 어렵다. 따라서, 1개의 좌표 코드만을 사용한 레이저 장비에 의해 관통 홀을 형성하는 경우, 관통 홀은 상부 및/또는 하부에서 센터로 갈수록 폭이 점진적으로 감소하는 모래시계 형상을 가지며, 이에 따라 최소폭은 최대폭의 50% 미만을 가졌다.To this end, the embodiment uses a plurality of coordinate codes (eg, T-code) to form the first through hole in the first insulating layer 511. That is, when using a laser device, in the comparative example, a through hole was formed in the core layer corresponding to the first insulating layer 511 using only one coordinate code. Accordingly, in the process of forming a through hole, it is difficult to change the laser process conditions during the process. Therefore, when a through hole is formed by a laser device using only one coordinate code, the through hole has an hourglass shape in which the width gradually decreases from the top and/or bottom to the center, and thus the minimum width is equal to the maximum width. had less than 50%.
이와 다르게, 실시 예는 적어도 2개의 좌표 코드를 이용하여 제1 절연층(511)에 제1 관통 홀을 형성한다. Differently, in the embodiment, the first through hole is formed in the first insulating layer 511 using at least two coordinate codes.
실시 예에서는 제1 좌표 코드를 이용하여 제1 절연층(511)에 제1 관통 홀의 일부를 형성한다. 이후, 실시 예는 제2 좌표 코드를 이용하여 제1 절연층(511)에 제1 관통홀의 일부와 연결되는 제1 관통 홀의 나머지 일부를 형성한다. 이를 통해, 실시 예는 최종적으로 제1 절연층(511)을 관통하는 제1 관통 홀을 형성할 수 있다.In an embodiment, a portion of the first through hole is formed in the first insulating layer 511 using the first coordinate code. Thereafter, in the embodiment, the remaining part of the first through hole connected to the part of the first through hole is formed in the first insulating layer 511 using the second coordinate code. Through this, the embodiment can finally form a first through hole penetrating the first insulating layer 511.
이때, 실시 예는 2개의 좌표 코드를 이용하기 때문에, 비교 예와 다르게, 제1 관통 홀의 형성 공정 중에 레이저 공정 조건의 변경이 가능하다. At this time, because the embodiment uses two coordinate codes, unlike the comparative example, it is possible to change the laser process conditions during the forming process of the first through hole.
이에 따라, 실시 예는 코어층에 대응하는 제1 절연층(511)에 레이저 장비를 이용하여 최대폭과 최소폭의 차이를 최소화된 제1 관통 홀을 형성하는 것이 가능하다. Accordingly, in the embodiment, it is possible to form a first through hole with a minimized difference between the maximum and minimum widths in the first insulating layer 511 corresponding to the core layer using a laser device.
즉, 실시 예는 제1 좌표 코드를 이용하여 제1 절연층(511)에 제1 관통 홀의 일부를 형성하는 제1 공정과, 제2 좌표 코드를 이용하여 제1 절연층(511)에 제1 관통 홀의 일부와 연결되는 나머지 일부를 형성하는 제2 공정을 진행한다. 이때, 제1 좌표 코드를 이용한 제1 공정에서 제1 관통 홀의 일부를 형성하기 위해 제1 사이즈의 개구를 가진 제1 마스크를 이용한다. 제1 사이즈는 제1 관통 홀이 가져야 할 목표 사이즈에 대응할 수 있다. 이를 통해, 실시 예는 제1 마스크를 이용하여 제1 절연층(511)의 상면 및 하면 각각에 목표 사이즈에 대응하는 제1 관통 홀의 일부를 형성한다.That is, the embodiment includes a first process of forming a portion of the first through hole in the first insulating layer 511 using a first coordinate code, and a first process of forming a portion of the first through hole in the first insulating layer 511 using the second coordinate code. A second process is performed to form the remaining part connected to part of the through hole. At this time, in the first process using the first coordinate code, a first mask having an opening of the first size is used to form a part of the first through hole. The first size may correspond to the target size that the first through hole should have. Through this, the embodiment forms a portion of the first through hole corresponding to the target size on each of the upper and lower surfaces of the first insulating layer 511 using the first mask.
이후, 실시 예는 제1 관통 홀의 일부가 형성된 이후에 제2 좌표 코드를 이용한 제2 공정을 진행한다. 이때, 제2 좌표 코드를 이용한 제2 공정에서 제1 관통 홀의 나머지 일부를 형성하기 위해 제1 사이즈와 다른 제2 사이즈의 개구를 가진 제2 마스크를 이용한다. 이때, 제2 사이즈는 제1 사이즈보다 작다. 실시 예는 제2 마스크를 이용하여 제1 관통 홀의 나머지 일부를 형성하는 제2 공정에서, 레이저의 에너지 세기를 증가시킨다. 구체적으로, 제1 마스크를 이용하여 제1 관통 홀의 일부를 형성하는 제1 공정에서, 실시 예는 제1 에너지 세기를 가지는 레이저를 제1 절연층(511)에 조사한다. 또한, 제2 마스크를 이용하여 제1 관통 홀의 나머지 일부를 형성하는 제2 공정에서, 실시 예는 제1 에너지 세기보다 큰 제2 에너지 세기를 가진 레이저를 제1 절연층(511)에 조사한다. 이때, 제2 마스크에 구비된 개구의 사이즈는 제1 관통 홀의 목표 사이즈보다 작다. 즉, 실시 예에서는 상대적으로 에너지 세기가 작은 레이저를 제1 사이즈를 가진 제1 마스크의 개구로 조사하고, 상대적으로 에너지 세기가 큰 레이저를 제1 사이즈보다 작은 제2 사이즈를 가진 제2 마스크의 개구로 조사한다. 따라서, 실시 예는 제1 관통 홀의 수직 방향으로의 전체 영역에서의 최대폭과 최소폭의 차이를 최소화할 수 있다. 또한, 상대적으로 큰 에너지 세기를 가진 레이저를 조사할 때 사용되는 제2 마스크의 개구의 사이즈는 목표 사이즈보다 작으며, 이에 따라, 실시 예는 제1 관통 홀의 사이즈가 확장되는 것을 방지할 수 있다. Thereafter, the embodiment proceeds with a second process using a second coordinate code after a portion of the first through hole is formed. At this time, in the second process using the second coordinate code, a second mask having an opening of a second size different from the first size is used to form the remaining part of the first through hole. At this time, the second size is smaller than the first size. In the embodiment, the energy intensity of the laser is increased in the second process of forming the remaining part of the first through hole using the second mask. Specifically, in the first process of forming a portion of the first through hole using the first mask, the embodiment irradiates the first insulating layer 511 with a laser having a first energy intensity. Additionally, in the second process of forming the remaining portion of the first through hole using the second mask, the embodiment irradiates the first insulating layer 511 with a laser having a second energy intensity greater than the first energy intensity. At this time, the size of the opening provided in the second mask is smaller than the target size of the first through hole. That is, in the embodiment, a laser with a relatively low energy intensity is irradiated through the opening of the first mask having a first size, and a laser with a relatively large energy intensity is irradiated through the opening of the second mask with a second size smaller than the first size. Investigate with Accordingly, the embodiment can minimize the difference between the maximum width and the minimum width in the entire vertical area of the first through hole. Additionally, the size of the opening of the second mask used when irradiating a laser with a relatively high energy intensity is smaller than the target size, and accordingly, the embodiment can prevent the size of the first through hole from expanding.
결론적으로, 실시 예는 상기와 같은 방법을 통해 레이저 장비를 이용하면서 내벽의 경사가 실질적으로 수직에 가까우며 목표 사이즈에 대응하는 사이즈를 가진 제1 관통 홀을 형성하는 것이 가능하다.In conclusion, in the embodiment, it is possible to form a first through hole whose inner wall has an inclination substantially close to vertical and whose size corresponds to the target size while using a laser device through the method described above.
이에 대해서는 하기에서 더욱 상세히 설명한다.This is explained in more detail below.
다시, 도 3a를 참조하면, 실시 예의 반도체 패키지 기판(500)은 보호층을 포함한다. 보호층은 절연층 또는 레지스트층이라고도 할 수 있다. 보호층은 반도체 패키지 기판의 최외층의 절연층을 의미한다. 보호층은 반도체 패키지 기판(500)의 최외층의 표면을 보호하는 기능과, 서로 인접한 도전성 접착제 간 단락을 방지하는 기능을 한다. 이에 따라 보호층은 기능적으로 '보호층'이라고도 할 수 있다. 예시적으로, 전도성 접착제를 솔더로 이용하는 경우, 보호층은 솔더 레지스트라고 할 수 있다.Referring again to FIG. 3A, the semiconductor package substrate 500 of the embodiment includes a protective layer. The protective layer may also be referred to as an insulating layer or a resist layer. The protective layer refers to the insulating layer of the outermost layer of the semiconductor package substrate. The protective layer functions to protect the surface of the outermost layer of the semiconductor package substrate 500 and prevents short circuits between adjacent conductive adhesives. Accordingly, the protective layer can also be functionally referred to as a ‘protective layer.’ For example, when a conductive adhesive is used as solder, the protective layer may be referred to as a solder resist.
구체적으로, 보호층은 제2 절연층(512)의 상면에 배치되는 제1 보호층(570)을 포함한다. 제1 보호층(570)은 제3 회로 패턴층(523)의 일부와 수직으로 중첩되는 적어도 하나의 제1 개구(571)를 포함한다. 제1 개구(571)는 접속부와 같은 전도성 접착제가 배치될 영역에 대응하게 구비될 수 있다. Specifically, the protective layer includes a first protective layer 570 disposed on the upper surface of the second insulating layer 512. The first protective layer 570 includes at least one first opening 571 that vertically overlaps a portion of the third circuit pattern layer 523. The first opening 571 may be provided to correspond to an area where a conductive adhesive such as a connection portion is to be placed.
또한, 보호층은 제3 절연층(53)의 하면에 배치되는 제2 보호층(580)을 포함한다. 제2 보호층(580)은 제4 회로 패턴층(524)과 수직으로 중첩되는 적어도 하나의 제2 개구(581)를 포함한다. 제2 개구(581)는 접속부와 같은 전도성 접착제가 배치될 영역에 대응하게 구비될 수 있다.Additionally, the protective layer includes a second protective layer 580 disposed on the lower surface of the third insulating layer 53. The second protective layer 580 includes at least one second opening 581 that vertically overlaps the fourth circuit pattern layer 524. The second opening 581 may be provided to correspond to an area where a conductive adhesive such as a connection portion is to be placed.
제1 보호층(570) 및 제2 보호층(580)은 유기 고분자 물질을 포함할 수 있다. 예를 들어, 제1 보호층(570) 및 제2 보호층(580)은 솔더 보호층일 수 있다. 일 예로, 제1 보호층(570) 및 제2 보호층(580)은 에폭시 아크릴레이트 계열의 수지를 포함할 수 있다. 자세하게, 제1 보호층(570) 및 제2 보호층(580)은 수지, 경화제, 광 개시제, 안료, 용매, 필러, 첨가제, 아크릴 계열의 모노머 등을 포함할 수 있다. 다만, 실시 예는 이에 한정되지 않는다. 예를 들어, 제1 보호층(570) 및 제2 보호층(580)은 포토 솔더 보호층, 커버레이 및 고분자 물질 중 어느 하나를 포함할 수도 있을 것이다.The first protective layer 570 and the second protective layer 580 may include an organic polymer material. For example, the first protective layer 570 and the second protective layer 580 may be solder protective layers. For example, the first protective layer 570 and the second protective layer 580 may include an epoxy acrylate-based resin. In detail, the first protective layer 570 and the second protective layer 580 may include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. However, the embodiment is not limited to this. For example, the first protective layer 570 and the second protective layer 580 may include any one of a photo solder protective layer, a coverlay, and a polymer material.
제1 보호층(570) 및 제2 보호층(580)은 1㎛ 내지 20㎛의 두께를 가질 수 있다. 이때, 제1 보호층(570) 및 제2 보호층(580)의 두께가 20㎛를 초과하는 경우, 반도체 패키지 기판의 전체적인 두께 및 반도체 패키지의 전체적인 두께가 증가할 수 있고, 응력이 커짐에 따라 반도체 패키지 기판의 휨이 커질 수 있다.The first protective layer 570 and the second protective layer 580 may have a thickness of 1 μm to 20 μm. At this time, when the thickness of the first protective layer 570 and the second protective layer 580 exceeds 20㎛, the overall thickness of the semiconductor package substrate and the overall thickness of the semiconductor package may increase, and as the stress increases, The warpage of the semiconductor package substrate may increase.
또한, 제1 보호층(570) 및 제2 보호층(580)의 두께가 1㎛ 미만이면, 회로 패턴층이 안정적으로 보호되지 못할 수 있다. 제1 보호층(570) 및 제2 보호층(580)의 두께가 1㎛ 미만이면, 반도체 패키지 기판의 전기적 신뢰성 및 반도체 패키지의 전기적 신뢰성이 저하될 수 있다.Additionally, if the thickness of the first protective layer 570 and the second protective layer 580 is less than 1 μm, the circuit pattern layer may not be stably protected. If the thickness of the first protective layer 570 and the second protective layer 580 is less than 1 μm, the electrical reliability of the semiconductor package substrate and the semiconductor package may deteriorate.
이하에서는 실시 예에 따른 제1 절연층(511)에 형성되는 제1 관통 홀, 제1 관통 전극 및 절연 부재에 대해 보다 구체적으로 설명한다.Hereinafter, the first through hole, the first through electrode, and the insulating member formed in the first insulating layer 511 according to the embodiment will be described in more detail.
도 4는 실시 예의 제1 절연층을 설명하기 위한 단면도이고, 도 5는 도 4의 제1 절연층에 구비된 제1 관통 홀을 나타낸 단면도이고, 도 6은 도 5의 관통 홀에 배치된 제1 관통 전극 및 절연 부재를 나타낸 단면도이고, 도 7은 제1 실시 예의 제1 관통 전극 및 제1 회로 패턴층의 층 구조를 나타낸 도면이고, 도 8은 제2 실시 예의 제1 관통 전극 및 제1 회로 패턴층의 층 구조를 나타낸 도면이며, 도 9는 실시 예에 따른 제1 관통 홀, 제1 관통 전극 및 절연 부재를 포함하는 실제 제품의 광학 현미경 사진이다.FIG. 4 is a cross-sectional view for explaining the first insulating layer of the embodiment, FIG. 5 is a cross-sectional view showing the first through hole provided in the first insulating layer of FIG. 4, and FIG. 6 is a cross-sectional view showing the first through hole provided in the first insulating layer of FIG. 5. 1 is a cross-sectional view showing a through electrode and an insulating member, FIG. 7 is a view showing the layer structure of the first through electrode and the first circuit pattern layer in the first embodiment, and FIG. 8 is a view showing the first through electrode and the first circuit pattern layer in the second embodiment. It is a diagram showing the layer structure of the circuit pattern layer, and FIG. 9 is an optical micrograph of an actual product including a first through hole, a first through electrode, and an insulating member according to an embodiment.
이하에서는 도 4 내지 9를 참조하여, 실시 예에 따른 제1 관통 전극(530), 제1 회로 패턴층(521), 제2 회로 패턴층(522), 제1 관통 전극(530) 및 절연 부재(540)에 대해 구체적으로 설명한다.Hereinafter, with reference to FIGS. 4 to 9, the first through electrode 530, the first circuit pattern layer 521, the second circuit pattern layer 522, the first through electrode 530, and the insulating member according to the embodiment. (540) will be explained in detail.
실시 예의 제1 절연층(511)의 수직 방향의 두께(T1)는 상술한 바와 같이 250㎛ 1200㎛의 범위를 만족할 수 있다.The vertical thickness T1 of the first insulating layer 511 in the embodiment may satisfy the range of 250 ㎛ to 1200 ㎛ as described above.
이때, 도 4를 참조하면, 제1 절연층(511)은 레진(511a) 및 레진(511a) 내에 배치된 강화 섬유(511b)를 포함할 수 있다. At this time, referring to FIG. 4 , the first insulating layer 511 may include a resin 511a and reinforcing fibers 511b disposed within the resin 511a.
강화 섬유(511b)는 레진(511a) 내에 서로 다른 방향으로 배열된 복수의 섬유를 포함할 수 있다. 예를 들어, 강화 섬유(511b)는 제1 수평 방향으로 배열된 제1 섬유 및 제1 수평 방향과 수직한 제2 수평 방향으로 배열된 제2 섬유를 포함한다. 예를 들어, 도 4에서의 강화 섬유(511b) 중 물결 형상의 섬유가 제1 섬유일 수 있고, 점 형상의 섬유가 제2 섬유일 수 있다.The reinforcing fibers 511b may include a plurality of fibers arranged in different directions within the resin 511a. For example, the reinforcing fibers 511b include first fibers arranged in a first horizontal direction and second fibers arranged in a second horizontal direction perpendicular to the first horizontal direction. For example, among the reinforcing fibers 511b in FIG. 4, the wave-shaped fiber may be the first fiber, and the point-shaped fiber may be the second fiber.
강화 섬유(511b)의 제1 섬유는 날실(warp yarn)이라고 할 수 있다. 강화 섬유(511b)의 제2 섬유는 씨실(fill yarn)이라고 할 수 있다.The first fiber of the reinforcing fiber 511b can be called a warp yarn. The second fiber of the reinforcing fiber 511b can be called a fill yarn.
즉, 강화 섬유(511b)는 유리 장 섬유(long glass fiber)인 필라멘트의 다발로 이루어질 수 있다. 그리고, 강화 섬유(511b)의 제1 섬유 및 제2 섬유는 레진(511a) 내에 상호 교차되는 제1 및 제2 수평 방향으로 배열될 수 있으나, 이에 한정되지는 않는다.That is, the reinforcing fiber 511b may be made of a bundle of filaments that are long glass fibers. Additionally, the first fibers and second fibers of the reinforcing fibers 511b may be arranged in the first and second horizontal directions that intersect each other within the resin 511a, but are not limited thereto.
강화 섬유(511b)는 복수의 그룹으로 구분될 수 있다. 예를 들어, 강화 섬유(511b)는 제1 절연층(511)의 레진(511a) 내에 수직 방향으로 상호 이격되는 복수의 그룹으로 구분될 수 있다. Reinforcement fibers 511b may be divided into multiple groups. For example, the reinforcing fibers 511b may be divided into a plurality of groups spaced apart from each other in the vertical direction within the resin 511a of the first insulating layer 511.
예를 들어, 강화 섬유(511b)는 제1 절연층(511)의 상면(511U) 및 하면(511L) 사이에서 수직 방향을 따라 서로 구분되는 제1 그룹 내지 제3 그룹을 포함할 수 있다. 제1 내지 제3 그룹의 강화섬유 각각은 제1 절연층(511) 내에서 수평 방향으로 배열된다. 그리고, 제1 내지 제3 그룹의 강화섬유는 제1 절연층(511) 내에서 수직 방향으로 상호 이격된다. For example, the reinforcing fibers 511b may include first to third groups separated from each other along the vertical direction between the upper surface 511U and the lower surface 511L of the first insulating layer 511. Each of the first to third groups of reinforcing fibers is arranged in the horizontal direction within the first insulating layer 511. And, the first to third groups of reinforcing fibers are spaced apart from each other in the vertical direction within the first insulating layer 511.
이때, 도면에는 강화 섬유(511b)가 3개의 그룹으로 제1 절연층(511)에 배치되는 것으로 도시하였으나, 이에 한정되지는 않는다. 예를 들어, 강화 섬유(511b)의 그룹 수는 제1 절연층(511)의 수직 방향의 두께를 기준으로 결정될 수 있다. 예를 들어, 제1 절연층(511)의 수직 방향의 두께가 250㎛일 경우, 강화 섬유(511b)는 3개의 그룹으로 구분되어 제1 절연층(511) 내에 배치될 수 있다. 예를 들어, 도 9에 도시된 바와 같이, 제1 절연층(511)의 수직 방향의 두께가 300㎛일 경우, 강화 섬유(511b)는 4개의 그룹으로 구분되어 제1 절연층(511)에 배치될 수 있다.At this time, the drawing shows that the reinforcing fibers 511b are arranged in three groups in the first insulating layer 511, but the present invention is not limited thereto. For example, the number of groups of reinforcing fibers 511b may be determined based on the vertical thickness of the first insulating layer 511. For example, when the vertical thickness of the first insulating layer 511 is 250㎛, the reinforcing fibers 511b may be divided into three groups and disposed in the first insulating layer 511. For example, as shown in FIG. 9, when the vertical thickness of the first insulating layer 511 is 300㎛, the reinforcing fibers 511b are divided into four groups and are attached to the first insulating layer 511. can be placed.
이에 따라, 제1 절연층(511)은 수직 방향으로 복수의 영역으로 구분될 수 있다. 예를 들어, 제1 절연층(511)은 수직 방향으로 강화 섬유(511b)를 포함하지 않는 제1 영역(511R1) 및 강화 섬유(511b)를 포함하는 제2 영역(511R2)을 포함할 수 있다. Accordingly, the first insulating layer 511 may be divided into a plurality of regions in the vertical direction. For example, the first insulating layer 511 may include a first region 511R1 that does not include the reinforcing fibers 511b and a second region 511R2 that includes the reinforcing fibers 511b in the vertical direction. .
제1 절연층(511)의 제2 영역(511R2)은 제1 절연층(511)의 제1 영역(511R1) 사이에 두고 수직 방향으로 상호 이격되며 복수 개 구비될 수 있다.There may be a plurality of second regions 511R2 of the first insulating layer 511 spaced apart from each other in the vertical direction between the first regions 511R1 of the first insulating layer 511.
도 4 내지 6을 참조하였을 때, 강화 섬유(511b)가 3개의 그룹으로 구분된 경우, 제1 절연층(511)의 제2 영역(511R2)은 제1 영역(511R1)을 사이에 두고 상호 이격된 적어도 3개의 서브 영역을 포함할 수 있다.4 to 6, when the reinforcing fibers 511b are divided into three groups, the second regions 511R2 of the first insulating layer 511 are spaced apart from each other with the first region 511R1 in between. may include at least three sub-areas.
예를 들어, 제1 절연층(511)의 제1 영역(511R1)은 제1 절연층(511)의 상면(511U)에 인접한 위치에서부터 제1-1 내지 제1-4 서브 영역(511R11, 511R12, 511R13, 511R14)을 포함할 수 있다. 또한, 제1 절연층(511)의 제2 영역(511R2)은 제1-1 내지 제1-4 서브 영역(511R11, 511R12, 511R13, 511R14) 각각의 사이에 배치된 제2-1 내지 제2-3 서브 영역(511R21, 511R22, 511R23)을 포함할 수 있다.제2 영역(511R2)은 제1 영역(511R1)보다 제1 절연층(511)의 상면(511U) 및 하면(511L)으로부터 이격되어 위치할 수 있다. 이는, 제1 절연층(511)의 상면(511U) 또는 하면(511L)에 강화 섬유(511b)가 노출되는 경우, 회로 패턴층들의 물리적 신뢰성 및 전기적 신뢰성이 저하되는 문제가 발생하기 때문이다.For example, the first region 511R1 of the first insulating layer 511 has 1-1 to 1-4 sub-regions 511R11, 511R12 from a position adjacent to the top surface 511U of the first insulating layer 511. , 511R13, 511R14). In addition, the second region 511R2 of the first insulating layer 511 is the 2-1st to 2nd sub-regions 511R11, 511R12, 511R13, and 511R14, respectively. It may include -3 sub-regions 511R21, 511R22, and 511R23. The second region 511R2 is spaced further from the upper and lower surfaces 511U and 511L of the first insulating layer 511 than the first region 511R1. can be located. This is because, when the reinforcing fibers 511b are exposed to the upper surface 511U or the lower surface 511L of the first insulating layer 511, the physical and electrical reliability of the circuit pattern layers are deteriorated.
도 5 및 6에 따른 실시 예에서는 레이저 장비를 이용하여 적어도 2개의 좌표 코드를 통해 제1 관통 홀(TH1)을 형성하기 때문에, 제1 관통 홀(TH1)의 내벽에 수직 방향을 따라 오목부와 볼록부가 교번 배치된다. 또한, 실시 예의 오목부와 볼록부를 구비한 제1 관통 홀(TH1)의 최소 폭과 최대 폭의 차이는 종래의 레이저 장비를 이용하여 1개의 좌표 코드를 통해 형성한 제1 관통 홀(TH1)의 최소 폭과 최대 폭의 차이에 비해 작다.In the embodiment according to FIGS. 5 and 6, since the first through hole TH1 is formed through at least two coordinate codes using a laser device, a concave portion and a concave portion along the vertical direction are formed on the inner wall of the first through hole TH1. The convex portions are arranged alternately. In addition, the difference between the minimum and maximum widths of the first through hole TH1 having the concave portion and the convex portion in the embodiment is the difference between the minimum width and the maximum width of the first through hole TH1 formed through one coordinate code using a conventional laser equipment. It is small compared to the difference between the minimum and maximum width.
또한, 오목부는 제1-1 내지 제1-4 서브 영역(511R11, 511R12, 511R13, 511R14)에 구비될 수 있고, 볼록부는 제2-1 내지 제2-3 서브 영역(511R21, 511R22, 511R23)에 구비될 수 있다. 이는, 제1 절연층(511)에서 레진(511a)으로만 구성된 레진층의 식각률이 강화 섬유(511b)가 구비된 층의 식각률보다 크고, 이 때문에 오목부 및 볼록부는 상술한 위치에 구비될 수 있으나, 이에 한정하지 않는다.Additionally, the concave portion may be provided in the 1-1st to 1-4th sub-regions 511R11, 511R12, 511R13, and 511R14, and the convex portion may be provided in the 2-1st to 2-3rd subregions 511R21, 511R22, and 511R23. It can be provided in . This means that the etching rate of the resin layer composed only of the resin 511a in the first insulating layer 511 is greater than the etching rate of the layer provided with the reinforcing fibers 511b, and for this reason, the concave portion and the convex portion may be provided at the above-described positions. However, it is not limited to this.
. .
도 5에 따른 실시 예는 제1 관통 홀(TH1)의 내벽은 제1 내벽(IW1) 및 제2 내벽(IW2)을 포함한다. 제1 관통 홀(TH1)의 제2 내벽(IW2)은 제1 내벽(IW1) 대비 제1 관통 홀(TH1)의 내측을 향하여 볼록한 볼록부로 구비될 수 있다.In the embodiment according to FIG. 5 , the inner wall of the first through hole TH1 includes a first inner wall IW1 and a second inner wall IW2. The second inner wall (IW2) of the first through hole (TH1) may be provided as a convex portion that is convex toward the inside of the first through hole (TH1) compared to the first inner wall (IW1).
즉, 실시 예의 제1 관통 홀(TH1)을 구성하는 제1 절연층(511)의 내벽은 제1 내벽(IW1)을 기준으로 제1 관통 홀(TH1)을 향하여 볼록한 제2 내벽(IW2)을 포함한다. 또한, 도 5를 참조하면, 제1 내벽(IW1)은 예시적으로 수직한 경사를 갖지만, 이에 한정되지 않고, 제1 절연층(511)의 외측면을 향하여 오목한 오목부로 구비될 수 있다.That is, the inner wall of the first insulating layer 511 constituting the first through hole TH1 of the embodiment has a second inner wall IW2 that is convex toward the first through hole TH1 with respect to the first inner wall IW1. Includes. Additionally, referring to FIG. 5 , the first inner wall IW1 exemplarily has a vertical slope, but is not limited thereto and may be provided as a concave portion that is concave toward the outer surface of the first insulating layer 511 .
이때, 실시 예의 제2 내벽(IW2)은 수직 방향으로 서로 이격된 복수의 볼록부를 포함할 수 있다. 또한, 볼록부는 폭의 증감이 변화하는 영역일 수 있다. 일 예로, 볼록부는 수직 방향을 따라 일정 곡률을 가진 곡면으로 구비될 수 있으나, 이에 한정되는 것은 아니다.At this time, the second inner wall IW2 of the embodiment may include a plurality of convex portions spaced apart from each other in the vertical direction. Additionally, the convex portion may be an area where the width increases or decreases. For example, the convex portion may be provided as a curved surface with a certain curvature along the vertical direction, but is not limited to this.
이를 통해 실시 예는, 제1 관통 홀(TH1)의 내벽(IW1, IW2)이 볼록부 및 오목부를 구비하여 제1 관통 홀(TH1)에 제1 관통전극을 균일하게 배치할 수 있도록 함으로써 임피던스를 안정적으로 매칭할 수 있고, 전압 강하나 전류 및/또는 신호의 손실을 줄일 수 있다. 뿐만 아니라 열응력에 대한 신뢰성을 개선할 수 있다. 즉, 제1 관통전극의 수평 방향의 폭을 도 3a에 도시된 종래의 수직한 제1 관통전극(530)의 두께에 비해 더 두껍게 배치하여, 전압 강하나 전류 및/또는 신호의 손실을 줄일 수 있고, 방열에 더 유리한 구조가 될 수 있다.Through this, in the embodiment, the inner walls (IW1, IW2) of the first through hole (TH1) have convex portions and concave portions to enable uniform placement of the first through electrode in the first through hole (TH1), thereby reducing the impedance. Stable matching is possible and voltage drop or current and/or signal loss can be reduced. In addition, reliability against thermal stress can be improved. That is, by arranging the horizontal width of the first through electrode to be thicker than the thickness of the conventional vertical first through electrode 530 shown in FIG. 3A, voltage drop or current and/or signal loss can be reduced. , it can be a more advantageous structure for heat dissipation.
제1 내벽(IW1)은 제1 관통 홀(TH1) 중에서 제1 절연층(511)의 제1 영역(511R1)에 형성될 수 있고, 제2 내벽(IW2)은 제1 관통 홀(TH1) 중에서 제1 절연층(511)의 제2 영역(511R2)에 형성될 수 있다.The first inner wall IW1 may be formed in the first region 511R1 of the first insulating layer 511 in the first through hole TH1, and the second inner wall IW2 may be formed in the first through hole TH1. It may be formed in the second region 511R2 of the first insulating layer 511.
즉, 실시 예는 레이저 장비를 이용하여 250㎛ 이상의 두께(T1)를 가진 제1 절연층(511)에 제1 관통 홀(TH1)을 형성한다. 이때 레이저 장비를 이용하는 경우, 제1 절연층(511)에 구비된 강화 섬유(511b)를 용이하게 제거하기 어려울 수 있다. 따라서, 실시 예의 제1 절연층(511)은 강화 섬유(511b)가 배치된 제1 절연층(511)의 제2 영역(511R2)의 내벽에 대응하며, 제1 관통 홀(TH1)을 향하여 볼록한 제2 내벽(IW2)을 포함할 수 있다. 그리고, 제1 내벽(IW1) 및 제2 내벽(IW2)은 각각 복수의 서브 파트를 포함할 수 있다.That is, in the embodiment, the first through hole TH1 is formed in the first insulating layer 511 with a thickness T1 of 250 μm or more using a laser device. At this time, when using laser equipment, it may be difficult to easily remove the reinforcing fibers 511b provided in the first insulating layer 511. Accordingly, the first insulating layer 511 of the embodiment corresponds to the inner wall of the second region 511R2 of the first insulating layer 511 where the reinforcing fibers 511b are disposed, and is convex toward the first through hole TH1. It may include a second inner wall (IW2). Additionally, the first inner wall (IW1) and the second inner wall (IW2) may each include a plurality of sub-parts.
예를 들어, 제1 내벽(IW1)은 제1 절연층(511)의 상면(511U)에 인접한 것을 기준으로 제1-1 내지 제1-4 서브 파트(IW1-1, IW1-2, IW1-3, IW1-4)를 포함할 수 있다. 제2 내벽(IW2)은 제1-1 내지 제1-4 서브 파트(IW1-1, IW1-2, IW1-3, IW1-4) 사이에 각각 배치된 제2-1 내지 제2-3 서브 파트(IW2-1, IW2-2, IW2-3)을 포함할 수 있다. For example, the first inner wall (IW1) has 1-1 to 1-4 sub-parts (IW1-1, IW1-2, IW1- 3, IW1-4) may be included. The second inner wall (IW2) includes the 2-1 to 2-3 sub parts disposed between the 1-1 to 1-4 sub parts (IW1-1, IW1-2, IW1-3, and IW1-4), respectively. May include parts (IW2-1, IW2-2, IW2-3).
제2 내벽(IW2)의 서브 파트의 개수는 제1 절연층(511)에 구비된 강화 섬유(511b)의 그룹 수에 대응할 수 있다. 이에 따라, 제2 내벽(IW2)의 서브 파트의 개수는 2개 초과, 3개 이상, 4개 이상, 또는 5개 이상일 수 있다.The number of sub-parts of the second inner wall IW2 may correspond to the number of groups of reinforcing fibers 511b provided in the first insulating layer 511. Accordingly, the number of sub-parts of the second inner wall IW2 may be more than 2, more than 3, more than 4, or more than 5.
제1 관통 홀(TH1)은 제1 내벽(IW1)의 제1-1 서브 파트(IW1-1)에 대응하는 영역에서 수평 방향으로 제1 폭(W1)을 가지다가 제2 내벽(IW2)의 제2-1 서브 파트(IW2-1)에 대응하는 영역에서 제1 폭(W1)보다 작은 제2 폭(W2)을 가진다. 또한, 제1 관통 홀(TH1)은 제1 내벽(IW1)의 제1-2 서브 파트(IW1-2)에 대응하는 영역에서 다시 제1 폭(W1)을 가지다가 제2 내벽(IW2)의 제2-2 서브 파트(IW2-2)에 대응하는 영역에서 제1 폭(W1)보다 작은 제2 폭(W2)을 가진다. 또한, 제1 관통 홀(TH1)은 제1 내벽(IW1)의 제1-3 서브 파트(IW1-3)에 대응하는 영역에서 다시 제1 폭(W1)을 가지다가 제2 내벽(IW2)의 제2-3 서브 파트(IW2-3)에 대응하는 영역에서 제1 폭(W1)보다 작은 제2 폭(W2)을 가진다. 그리고, 제1 절연층(511)은 제1 내벽(IW1)의 제1-4 서브 파트(IW1-4)에 대응하는 영역에서 다시 제1 폭(W1)을 가지게 된다. 다만, 도 9를 참조하면, 제1 관통 홀(TH1)은 제1 내벽(IW1)의 제1-1 내지 제1-4 서브 파트(IW1-1, IW1-2, IW1-3, IW1-4)에 대응하는 각각의 영역에서 모두 같은 제1 폭(W1)을 갖지 않을 수 있고, 제2 내벽(IW2)의 제2-1 내지 제2-3 서브 파트(IW2-1, IW2-2, IW2-3)에서 모두 같은 제2 폭(W2)을 갖지 않을 수 있다. The first through hole TH1 has a first width W1 in the horizontal direction in an area corresponding to the 1-1 subpart IW1-1 of the first inner wall IW1 and has a first width W1 in the second inner wall IW2. It has a second width (W2) smaller than the first width (W1) in the area corresponding to the 2-1 subpart (IW2-1). In addition, the first through hole TH1 has a first width W1 again in an area corresponding to the 1-2 subpart IW1-2 of the first inner wall IW1 and has a first width W1 in the area corresponding to the 1-2 subpart IW1-2 of the first inner wall IW1. It has a second width (W2) smaller than the first width (W1) in the area corresponding to the 2-2 subpart (IW2-2). In addition, the first through hole TH1 has a first width W1 again in an area corresponding to the 1-3 subpart IW1-3 of the first inner wall IW1 and then has a first width W1 in the area corresponding to the 1-3 subpart IW1-3 of the first inner wall IW1. It has a second width (W2) smaller than the first width (W1) in the area corresponding to the 2-3 subpart (IW2-3). And, the first insulating layer 511 has a first width W1 again in the area corresponding to the 1-4 subpart (IW1-4) of the first inner wall (IW1). However, referring to FIG. 9, the first through hole TH1 is connected to the 1-1 to 1-4 sub-parts (IW1-1, IW1-2, IW1-3, IW1-4) of the first inner wall (IW1). ) may not all have the same first width (W1) in each region corresponding to ), and the 2-1st to 2-3rd subparts (IW2-1, IW2-2, IW2) of the second inner wall (IW2) In -3), they may not all have the same second width (W2).
실시 예의 제1 절연층(511)은 2개 초과, 3개 이상, 4개 이상 또는 5개 이상의 그룹으로 수직으로 이격된 강화 섬유(511b)를 포함한다. 그리고 제1 관통 홀(TH1)이 형성된 제1 절연층(511)의 내벽은 강화 섬유(511b)가 배치된 영역에서 제1 관통 홀(TH1)의 중심을 향하여 볼록한 복수의 볼록부를 포함한다. 복수의 볼록부는 제1 절연층(511)에서 수직 방향으로 서로 이격될 수 있다. 그리고, 각각의 볼록부는 제1 관통 홀(TH1)의 내벽에서 제1 관통 홀(TH1)의 내벽의 둘레 방향을 따라 연장될 수 있다. 이때, 제1 관통 홀(TH1)의 제1 폭(W1)은 수직 방향으로의 전체 영역에서 최대 폭을 가지는 영역의 수평 방향의 폭을 의미할 수 있다. 제1 관통 홀(TH1)의 제2 폭(W2)은 수직 방향으로의 전체 영역에서 최소 폭을 가지는 영역의 수평 방향의 폭을 의미할 수 있다.The first insulating layer 511 of the embodiment includes reinforcing fibers 511b vertically spaced in groups of more than 2, more than 3, more than 4, or more than 5. And the inner wall of the first insulating layer 511 where the first through hole TH1 is formed includes a plurality of convex portions that are convex toward the center of the first through hole TH1 in the area where the reinforcing fibers 511b are disposed. The plurality of convex portions may be spaced apart from each other in the vertical direction in the first insulating layer 511 . Additionally, each convex portion may extend from the inner wall of the first through hole TH1 along a circumferential direction of the inner wall of the first through hole TH1. At this time, the first width W1 of the first through hole TH1 may mean the width in the horizontal direction of the area having the maximum width in the entire area in the vertical direction. The second width W2 of the first through hole TH1 may mean the horizontal width of the area having the minimum width in the entire vertical area.
비교 예의 레이저 장비를 이용하여 250㎛ 이상의 절연층에 형성된 관통 홀의 경우, 제2 폭이 제1 폭의 50% 미만이었다.In the case of a through hole formed in an insulating layer of 250㎛ or more using the laser equipment of the comparative example, the second width was less than 50% of the first width.
이와 다르게, 실시 예의 제2 폭(W2)은 제1 폭(W1)의 55% 내지 95%의 범위를 만족할 수 있다. Differently, the second width W2 of the embodiment may satisfy a range of 55% to 95% of the first width W1.
제2 폭(W2)이 제1 폭(W1)의 55% 미만이면, 관통 홀의 폭 차이가 심해지고, 이에 의해 관통 홀을 채우는 도금 공정에서의 도금 특성이 저하될 수 있다. 예를 들어, 폭의 차이가 심하면, 도금 공정에서 도금 성장 속도의 차이도 커지고, 이에 따라 관통 홀의 내부에 금속 물질로 채워지지 않은 빈 공간의 보이드 영역이 존재할 수 있다. 또한, 제2 폭(W2)이 제1 폭(W1)의 95%를 초과하는 경우에도, 도금 브리지가 존재하지 않음에 따라 도금 공정에서의 도금 특성이 저하될 수 있다. If the second width W2 is less than 55% of the first width W1, the difference in the width of the through hole increases, and as a result, plating characteristics in the plating process of filling the through hole may deteriorate. For example, if the difference in width is large, the difference in plating growth speed during the plating process also increases, and accordingly, a void area of an empty space that is not filled with a metal material may exist inside the through hole. Additionally, even when the second width W2 exceeds 95% of the first width W1, plating characteristics in the plating process may be deteriorated due to the absence of a plating bridge.
한편, 실시 예의 제1 관통 전극(530) 및 절연 부재(540)는 제1 관통 홀(TH1) 내에 배치될 수 있다.Meanwhile, the first through electrode 530 and the insulating member 540 of the embodiment may be disposed in the first through hole TH1.
제1 관통 전극(530)은 제1 관통 홀(TH1)을 포함하는 제1 절연층(511)의 내벽(IW1, IW2)과 접촉할 수 있다. 절연 부재(540)는 제1 관통 홀(TH1) 내에서 제1 관통 전극(530)의 내측에 배치될 수 있다. 예시적으로, 제1 관통 전극(530)은 제1 관통 홀(TH1) 내에서 절연 부재(540)의 외측을 감싸며 구비될 수 있다.The first through electrode 530 may contact the inner walls (IW1, IW2) of the first insulating layer 511 including the first through hole (TH1). The insulating member 540 may be disposed inside the first through electrode 530 within the first through hole TH1. Illustratively, the first through electrode 530 may be provided to surround the outside of the insulating member 540 within the first through hole TH1.
제1 관통 전극(530)은 일정 두께를 가지고 제1 관통 홀(TH1)을 포함하는 제1 절연층(511)의 내벽에 배치될 수 있다. 제1 관통 전극(530)의 두께는 제1 관통 전극(530)의 수평 방향의 거리를 의미할 수 있다. 구체적으로, 제1 관통 전극(530)의 두께는 제1 관통 전극(530)의 수평 방향으로의 폭을 의미할 수 있다.The first through electrode 530 may have a certain thickness and may be disposed on the inner wall of the first insulating layer 511 including the first through hole TH1. The thickness of the first through electrode 530 may refer to the distance of the first through electrode 530 in the horizontal direction. Specifically, the thickness of the first through electrode 530 may mean the width of the first through electrode 530 in the horizontal direction.
이때, 제1 관통 전극(530)은 복수의 부분으로 구분될 수 있다. 예를 들어, 제1 관통 전극(530)은 제1 절연층(511)의 제1 영역(511R1)에 대응하는 제1 내벽(IW1) 상에 배치된 오목부를 포함할 수 있다. 또한, 제1 관통 전극(530)은 제1 절연층(511)의 제2 영역(511R2)에 대응하는 제2 내벽(IW2) 상에 배치된 볼록부를 포함할 수 있다. 그리고, 오목부 및 볼록부를 구비한 제1 관통 전극(530)의 측면은 수직 방향으로 단차를 가질 수 있다. 구체적으로, 제1 관통 전극(530)의 오목부는 강화 섬유(511b)와 수평 방향으로 중첩되지 않는다. 그리고, 제1 관통 전극(530)의 볼록부는 수평 방향으로 강화 섬유(511b)와 중첩된다. 바람직하게, 제1 관통 전극(530)의 볼록부는 제1 절연층(511)의 제2 내벽(IW2)에 구비된 볼록부에 대응된다. 또한, 제1 관통 전극(530)의 오목부는 제1 절연층(511)의 제1 내벽(IW1)에 구비된 오목부에 대응된다. 또한, 도 9를 참조하면, 제1 관통 전극(530)은 오목부와 볼록부가 수직 방향을 따라 교번 배치된 형상을 가질 수 있다. 이때, 제1 관통 전극(530)의 오목부가 제1 관통 홀(TH1)의 제1 내벽(IW1)에 구비된 오목부에 대응되고, 제1 관통 전극(530)의 볼록부가 제1 관통 홀(TH1)의 제2 내벽(IW2)에 구비된 볼록부에 대응되는 것으로 보이고 있으나, 이에 한정하지 않는다.At this time, the first through electrode 530 may be divided into a plurality of parts. For example, the first through electrode 530 may include a concave portion disposed on the first inner wall IW1 corresponding to the first region 511R1 of the first insulating layer 511. Additionally, the first through electrode 530 may include a convex portion disposed on the second inner wall IW2 corresponding to the second region 511R2 of the first insulating layer 511. Also, the side surface of the first through electrode 530 having the concave portion and the convex portion may have a step in the vertical direction. Specifically, the concave portion of the first through electrode 530 does not overlap the reinforcing fiber 511b in the horizontal direction. And, the convex portion of the first through electrode 530 overlaps the reinforcing fiber 511b in the horizontal direction. Preferably, the convex portion of the first through electrode 530 corresponds to the convex portion provided on the second inner wall (IW2) of the first insulating layer 511. Additionally, the concave portion of the first through electrode 530 corresponds to the concave portion provided in the first inner wall (IW1) of the first insulating layer 511. Additionally, referring to FIG. 9 , the first through electrode 530 may have a shape in which concave portions and convex portions are alternately arranged along the vertical direction. At this time, the concave portion of the first through electrode 530 corresponds to the concave portion provided in the first inner wall (IW1) of the first through hole (TH1), and the convex portion of the first through electrode 530 corresponds to the concave portion of the first through hole (TH1). It appears to correspond to the convex portion provided on the second inner wall (IW2) of TH1), but is not limited to this.
제1 관통 전극(530)은 오목부가 구비된 영역에서 수평 방향으로 제3 두께(W3)를 가질 수 있다. 그리고 제1 관통 전극(530)는 볼록부가 구비된 영역에서 수평 방향으로 제4 두께(W4)를 가질 수 있다. 이때, 제3 두께(W3)는 제4 두께(W4)에 대응할 수 있다. 예를 들어, 제3 두께(W3)와 제4 두께(W4)는 서로 동일할 수 있다. 즉, 제1 관통 전극(530)는 오목부가 구비된 영역 및 볼록부가 구비된 영역 각각에서 서로 동일한 수평 방향으로의 두께를 가질 수 있다. 여기서, 서로 동일한 두께를 가진다는 것은 오목부가 구비된 영역 및 볼록부가 구비된 영역에서의 수평 방향으로의 두께의 차이가 3㎛ 이하인 것을 의미할 수 있다. The first through electrode 530 may have a third thickness W3 in the horizontal direction in the area where the concave portion is provided. Additionally, the first through electrode 530 may have a fourth thickness W4 in the horizontal direction in the area where the convex portion is provided. At this time, the third thickness W3 may correspond to the fourth thickness W4. For example, the third thickness W3 and the fourth thickness W4 may be equal to each other. That is, the first through electrode 530 may have the same thickness in the horizontal direction in each of the areas provided with the concave portion and the area provided with the convex portion. Here, having the same thickness may mean that the difference in thickness in the horizontal direction between the area provided with the concave portion and the area provided with the convex portion is 3 μm or less.
제1 관통 전극(530)의 수평 방향의 두께(W3, W4)는 10㎛ 내지 25㎛의 범위를 가질 수 있다. The horizontal thicknesses W3 and W4 of the first through electrode 530 may range from 10 μm to 25 μm.
제1 관통 전극(530)의 수평 방향의 두께가 10㎛ 미만이면, 제1 관통 전극(530)의 저항이 증가하고, 전송 가능한 신호의 허용 전류가 감소할 수 있다. 또한, 제1 관통 전극(530)의 수평 방향의 두께가 10㎛ 미만이면 전기적 특성이 저하될 수 있다. 예를 들어, 제1 관통 전극(530)의 수평 방향의 두께가 10㎛ 미만이면, 제1 관통 홀(TH1)을 통해 노출된 강화 섬유(511b)가 제1 관통 전극(530)에 의해 안정적으로 덮이지 않을 수 있다. 그리고, 제1 관통 전극(530)에 의해 강화 섬유(511b)가 덮이지 않는 경우, 강화 섬유(511b)에 의해 전기적 특성이 저하되는 문제가 발생할 수 있다. 제1 관통 전극(530)의 수평 방향의 두께가 25㎛을 초과하면, 제1 관통 전극(530)을 형성하는 공정에서의 도금 속도 성장 차이로 인해, 제1 관통 전극(530)의 오목부가 구비된 영역 및 제1 관통 전극(530)의 볼록부가 구비된 영역 사이의 두께 편차가 커질 수 있다.If the horizontal thickness of the first through electrode 530 is less than 10 μm, the resistance of the first through electrode 530 may increase and the allowable current of a signal that can be transmitted may decrease. Additionally, if the horizontal thickness of the first through electrode 530 is less than 10 μm, electrical characteristics may deteriorate. For example, when the horizontal thickness of the first through electrode 530 is less than 10㎛, the reinforcing fibers 511b exposed through the first through hole TH1 are stably stabilized by the first through electrode 530. It may not be covered. In addition, when the reinforcing fibers 511b are not covered by the first through electrode 530, a problem in which electrical properties are deteriorated due to the reinforcing fibers 511b may occur. When the horizontal thickness of the first through electrode 530 exceeds 25㎛, a concave portion of the first through electrode 530 is formed due to a difference in plating speed growth in the process of forming the first through electrode 530. The thickness difference between the exposed area and the area provided with the convex portion of the first through electrode 530 may increase.
절연 부재(540)는 상면에서 하면을 향하여 폭이 변화하는 영역을 포함할 수 있다. 예를 들어, 절연 부재(540)는 내측 방향으로 오목한 복수의 오목부 및 제1 관통 전극(530)을 향하여 볼록한 복수의 볼록부를 구비할 수 있다. 절연 부재(540)의 오목부는 수직 방향으로 이격되어 복수 개 구비될 수 있다. 또한, 절연 부재(540)의 볼록부는 절연 부재(540)의 복수의 오목부 각각의 사이에 구비될 수 있다. The insulating member 540 may include a region whose width changes from the upper surface to the lower surface. For example, the insulating member 540 may include a plurality of concave portions that are concave inward and a plurality of convex portions that are convex toward the first through electrode 530 . The insulating member 540 may be provided with a plurality of concave portions spaced apart in the vertical direction. Additionally, the convex portion of the insulating member 540 may be provided between each of the plurality of concave portions of the insulating member 540.
도 6의 실시 예에 따르면, 절연 부재(540)는 제5 폭(W5)을 가지는 제1 부분(541)과, 제5 폭(W5)보다 작은 제6 폭(W6)을 가지는 제2 부분(542)을 포함할 수 있다. 그리고, 절연 부재(540)의 제1 부분(541)의 측면에는 제1 관통 전극(530)을 향하여 볼록한 볼록부가 구비될 수 있다. 또한, 절연 부재(540)의 제2 부분(542)의 측면에는 내측으로 오목한 오목부가 구비될 수 있다.According to the embodiment of FIG. 6, the insulating member 540 includes a first part 541 having a fifth width W5, and a second part having a sixth width W6 smaller than the fifth width W5 ( 542) may be included. Additionally, the side surface of the first portion 541 of the insulating member 540 may be provided with a convex portion that protrudes toward the first through electrode 530 . Additionally, a side surface of the second portion 542 of the insulating member 540 may be provided with a concave portion that is concave inward.
즉, 제1 절연층(511)의 제1 관통 홀(TH1)의 내벽은 강화 섬유(511b)에 대응하게 볼록한 볼록부를 포함한다. 이에 따라, 절연 부재(540)도 제1 관통 홀(TH1)의 볼록부에 대응하는 오목부를 구비할 수 있다. 예시적으로, 절연 부재(540)는 제1 관통 홀(TH1)에 구비된 볼록부와 수평 방향으로 중첩된 오목부를 구비할 수 있다. 또한, 절연 부재(540)는 제1 관통 홀(TH1)에 구비된 오목부와 수평 방향으로 중첩된 볼록부를 구비할 수 있다. 이때, 도 6에서는 절연 부재(540)의 제1 부분(541)의 측면이 수직한 것으로 도시되었으나, 이에 한정하지 않는다. 일 예로, 제1 부분(541)의 측면은 제1 관통 전극(530)을 향하여 볼록한 곡면의 볼록부로 구비될 수 있다.That is, the inner wall of the first through hole TH1 of the first insulating layer 511 includes a convex portion corresponding to the reinforcing fiber 511b. Accordingly, the insulating member 540 may also have a concave portion corresponding to the convex portion of the first through hole TH1. As an example, the insulating member 540 may include a convex portion provided in the first through hole TH1 and a concave portion that overlaps in the horizontal direction. Additionally, the insulating member 540 may have a convex portion that overlaps the concave portion provided in the first through hole TH1 in the horizontal direction. At this time, in FIG. 6, the side surface of the first portion 541 of the insulating member 540 is shown to be vertical, but the present invention is not limited to this. As an example, the side surface of the first portion 541 may be provided with a curved convex portion that is convex toward the first through electrode 530.
절연 부재(540)의 제1 부분(541)은 수직 방향으로 상호 이격되어 복수 개 구비될 수 있다.A plurality of first portions 541 of the insulating member 540 may be provided and spaced apart from each other in the vertical direction.
예를 들어, 도 6에 도시된 바와 같이, 절연 부재(540)의 제1 부분(541)은 제1-1 부분(541-1), 제1-2 부분(541-2), 제1-3 부분(541-3) 및 제1-4 부분(541-4)을 포함할 수 있다.For example, as shown in FIG. 6, the first part 541 of the insulating member 540 includes a 1-1 part 541-1, a 1-2 part 541-2, and a 1-1 part 541-1. It may include part 3 (541-3) and first to fourth parts (541-4).
그리고, 절연 부재(540)의 제2 부분(542)은 제2-1 부분(542-1), 제2-2 부분(542-2) 및 제2-3 부분(542-3)을 포함할 수 있다. 제2-1 부분(542-1), 제2-2 부분(542-2) 및 제2-3 부분(542-3)은 강화 섬유(511b)와 수평 방향으로 중첩되는 부분일 수 있다.And, the second part 542 of the insulating member 540 may include a 2-1 part 542-1, a 2-2 part 542-2, and a 2-3 part 542-3. You can. The 2-1 part 542-1, the 2-2 part 542-2, and the 2-3 part 542-3 may be parts that overlap the reinforcing fiber 511b in the horizontal direction.
그리고, 제1-1 부분(541-1), 제1-2 부분(541-2), 제1-3 부분(541-3) 및 제1-4 부분(541-4)은 강화 섬유(511b)와 수평 방향으로 중첩되지 않는 부분일 수 있다.And, the 1-1 part (541-1), the 1-2 part (541-2), the 1-3 part (541-3), and the 1-4 part (541-4) are reinforced fibers (511b). ) may be a part that does not overlap in the horizontal direction.
그리고, 제2-1 부분(542-1), 제2-2 부분(542-2) 및 제2-3 부분(542-3)은 강화 섬유(511b)에 의해 제1-1 부분(541-1), 제1-2 부분(541-2), 제1-3 부분(541-3) 및 제1-4 부분(541-4)보다 작은 폭을 가질 수 있다.And, the 2-1 part (542-1), the 2-2 part (542-2), and the 2-3 part (542-3) are formed by the reinforcing fibers (511b). 1), it may have a smaller width than the 1-2 part 541-2, the 1-3 part 541-3, and the 1-4 part 541-4.
한편, 제1 관통 전극(530)은 복수의 층으로 구성될 수 있다. 예를 들어, 제1 관통 전극(530)은 제1 회로 패턴층(521) 및 제2 회로 패턴층(522)의 형성 시에, 제1 회로 패턴층(521) 및 제2 회로 패턴층(522)과 함께 형성될 수 있다. 이에 따라 제1 관통 전극(530)은 제1 회로 패턴층(521) 및 제2 회로 패턴층(522)를 구성하는 층에 대응하는 층 구조를 가질 수 있다. Meanwhile, the first through electrode 530 may be composed of multiple layers. For example, when forming the first circuit pattern layer 521 and the second circuit pattern layer 522, the first through electrode 530 is used to form the first circuit pattern layer 521 and the second circuit pattern layer 522. ) can be formed together. Accordingly, the first through electrode 530 may have a layer structure corresponding to the layers constituting the first circuit pattern layer 521 and the second circuit pattern layer 522.
제1 회로 패턴층(521)은 복수의 금속층을 포함할 수 있다.The first circuit pattern layer 521 may include a plurality of metal layers.
예를 들어, 제1 회로 패턴층(521)은 제1 절연층(511) 상에 배치된 제1 금속층(521-1), 제1 금속층(521-1) 상에 배치된 제2 금속층(521-2), 및 제2 금속층(521-2) 상에 배치된 제3 금속층(521-3)을 포함할 수 있다.For example, the first circuit pattern layer 521 includes a first metal layer 521-1 disposed on the first insulating layer 511, and a second metal layer 521 disposed on the first metal layer 521-1. -2), and a third metal layer 521-3 disposed on the second metal layer 521-2.
제1 회로 패턴층(521)의 제1 금속층(521-1)은 제1 절연층(511)의 표면에 부착되어 있던 동박층을 의미할 수 있다.The first metal layer 521-1 of the first circuit pattern layer 521 may refer to a copper foil layer attached to the surface of the first insulating layer 511.
제1 회로 패턴층(521)의 제2 금속층(521-2)은 제1 금속층(521-1) 상에 무전해 도금을 통해 형성한 도금층일 수 있다. 예를 들어, 제1 회로 패턴층(521)의 제2 금속층(521-2)은 화학동도금층일 수 있다.The second metal layer 521-2 of the first circuit pattern layer 521 may be a plating layer formed on the first metal layer 521-1 through electroless plating. For example, the second metal layer 521-2 of the first circuit pattern layer 521 may be a chemical copper plating layer.
제1 회로 패턴층(521)의 제3 금속층(521-3)은 제2 금속층(521-2)을 시드층으로 전해 도금을 진행하여 형성한 도금층일 수 있다. 예를 들어, 제1 회로 패턴층(521)의 제3 금속층(521-3)은 전해 도금층일 수 있다. The third metal layer 521-3 of the first circuit pattern layer 521 may be a plating layer formed by electrolytic plating using the second metal layer 521-2 as a seed layer. For example, the third metal layer 521-3 of the first circuit pattern layer 521 may be an electrolytic plating layer.
이때, 도 7에 도시된 바와 같이, 제1 실시 예에서의 제1 회로 패턴층(521)의 제3 금속층(521-3)은 절연 부재(540)의 상면에 배치될 수 있다. 이 경우, 제1 회로 패턴층(521)의 제3 금속층(521-3)은 복수 회의 전해 도금을 진행하는 것에 의해 형성될 수 있다. At this time, as shown in FIG. 7, the third metal layer 521-3 of the first circuit pattern layer 521 in the first embodiment may be disposed on the upper surface of the insulating member 540. In this case, the third metal layer 521-3 of the first circuit pattern layer 521 may be formed by performing electrolytic plating multiple times.
또한, 도 8에 도시된 바와 같이, 제2 실시 예에서의 제1 회로 패턴층(521)의 제3 금속층(521-3)은 절연 부재(540)의 상면을 덮지 않을 수 있다. 이 경우, 제1 회로 패턴층(521)의 제3 금속층(521-3)은 1회의 전해 도금을 진행하는 것에 의해 형성될 수 있다. 이때의 제1 회로 패턴층(521)의 제3 금속층(521-3)은 절연 부재(540)의 상면과 수직 방향으로 중첩되지 않을 수 있다.Additionally, as shown in FIG. 8, the third metal layer 521-3 of the first circuit pattern layer 521 in the second embodiment may not cover the top surface of the insulating member 540. In this case, the third metal layer 521-3 of the first circuit pattern layer 521 may be formed by performing one electrolytic plating process. At this time, the third metal layer 521-3 of the first circuit pattern layer 521 may not overlap the top surface of the insulating member 540 in the vertical direction.
한편, 제1 관통 전극(530)은 제1 회로 패턴층(521)의 제2 금속층(521-2)에 대응하는 제4 금속층(530-1) 및 제4 금속층(530-1) 상에 배치되고 제1 회로 패턴층(521)의 제3 금속층(521-3)에 대응하는 제5 금속층(530-2)을 포함할 수 있다. Meanwhile, the first through electrode 530 is disposed on the fourth metal layer 530-1 and the fourth metal layer 530-1 corresponding to the second metal layer 521-2 of the first circuit pattern layer 521. and may include a fifth metal layer 530-2 corresponding to the third metal layer 521-3 of the first circuit pattern layer 521.
그리고, 제1 관통 전극(530)의 제4 금속층(530-1)은 제1 관통 홀(TH1)을 포함하는 제1 절연층(511)의 내벽에 구비될 수 있다. 그리고, 제1 관통 전극(530)의 제5 금속층(530-2)은 제1 관통 전극(530)의 제4 금속층(530-1)과 절연 부재(540) 사이에 배치될 수 있다.Additionally, the fourth metal layer 530-1 of the first through electrode 530 may be provided on the inner wall of the first insulating layer 511 including the first through hole TH1. Additionally, the fifth metal layer 530-2 of the first through electrode 530 may be disposed between the fourth metal layer 530-1 of the first through electrode 530 and the insulating member 540.
한편, 제1 관통 전극(530)의 수평 방향으로의 두께(W4, W5)는 제1 관통 전극(530)의 제4 금속층(530-1)과 제5 금속층(530-2)의 수평 방향으로의 두께의 합을 의미할 수 있다.Meanwhile, the thicknesses W4 and W5 in the horizontal direction of the first through electrode 530 are the horizontal directions of the fourth metal layer 530-1 and the fifth metal layer 530-2 of the first through electrode 530. It can mean the sum of the thicknesses.
한편, 도 9를 참조하면, 실시 예에 따르면, 제1 절연층(511)의 수직 방향으로의 두께는 400㎛ 이상일 수 있고, 이에 따라 강화 섬유(511b)는 수직 방향으로 4개의 그룹으로 구분되어 배치될 수 있다. 따라서, 제1 절연층(511)의 제1 관통 홀(TH1)의 내벽에는 4개의 그룹의 강화 섬유(511b)에 각각 대응하는 돌출 부분이 구비할 수 있다.Meanwhile, referring to FIG. 9, according to the embodiment, the thickness of the first insulating layer 511 in the vertical direction may be 400㎛ or more, and accordingly, the reinforcing fibers 511b are divided into four groups in the vertical direction. can be placed. Accordingly, the inner wall of the first through hole TH1 of the first insulating layer 511 may be provided with protruding portions corresponding to each of the four groups of reinforcing fibers 511b.
도 9를 참조하면, 제1 관통 홀(TH1)의 측벽에 배치된 제1 관통 전극(530)은 절연부재(540)와 마주보는 일면과 제1 절연층(511)을 마주보는 타면을 포함하고, 일면은 절연부재(540)을 향하여 돌출된 볼록부와, 제1 관통 홀(TH1)을 향하여 오목한 오목부를 포함한다. 도 9에 도시된 제1 관통 전극(530)은 일 단면을 도시하는 것이고, 제1 관통 전극(530)의 일면은 절연부재(540)를 감싸며 배치된 구조이다. Referring to FIG. 9, the first through electrode 530 disposed on the sidewall of the first through hole TH1 includes one side facing the insulating member 540 and the other side facing the first insulating layer 511. , one surface includes a convex portion protruding toward the insulating member 540 and a concave portion concave toward the first through hole TH1. The first through electrode 530 shown in FIG. 9 shows one cross section, and one side of the first through electrode 530 is arranged to surround the insulating member 540.
제1 관통 전극(530)의 오목부는 서로 마주보며 수평 방향을 따라 중첩될 수 있고, 제1 관통 전극(530)의 볼록부는 서로 마주보며 수평 방향을 따라 중첩될 수 있다. 또한, 볼록부와 오목부는 수직 방향을 따라 교번 배치된 구조일 수 있다. 이를 통해 제1 관통 전극(530)의 수평 방향에 대한 두께를 비교적 균일하게 배치할 수 있고, 드릴 머신 장비를 이용한 공정에 비해 두껍게 배치할 수 있다. The concave portions of the first through electrodes 530 may face each other and overlap along the horizontal direction, and the convex portions of the first through electrodes 530 may face each other and overlap along the horizontal direction. Additionally, the convex portions and concave portions may have a structure in which the convex portions and concave portions are alternately arranged along the vertical direction. Through this, the thickness of the first penetrating electrode 530 in the horizontal direction can be placed relatively uniformly, and it can be placed thicker than in the process using drill machine equipment.
제1 관통 전극(530)의 타면은 일면과 다른 형상을 가질 수 있다. 즉, 제1 관통 전극(530)의 오목부가 배치된 일면과 수평 방향을 따라 중첩되는 타면은 오목한 면을 갖지 않거나, 곡률이 서로 다를 수 있다. 도 9를 참조하면, 제1 관통 전극(530)의 일면의 곡률과, 오목한 일면과 수평 방향으로 중첩된 타면의 곡률이 서로 다르게 개시되어 있다. 이를 통해, 절연 부재(540)와 제1 관통 전극(530) 간의 결합력을 개선할 수 있고, 방열 특성을 개선할 수 있을 뿐만 아니라, 응력을 제어함으로써 반도체 패키지 기판의 기계적 신뢰성을 개선할 수 있다. 이와 마찬가지로, 제1 관통 전극(530)의 일면의 볼록부는 이와 수평 방향으로 중첩된 타면의 볼록부와 서로 다른 곡률을 가질 수 있다. 타면의 볼록부는 일면의 볼록부와 다르게 유리 섬유를 감싸는 구조로 배치될 수 있기 때문에, 그 곡률이 일면의 볼록부와 다를 수 있다. 구체적으로, 제1 관통 전극(530)이 유리 섬유를 감싸는 경우, 제1 관통 전극(530)의 수평 방향의 두께가 10㎛ 이상이 되어야 전기적 특성이 저하되는 문제를 방지할 수 있다. 따라서, 타면의 볼록부가 유리 섬유를 감싸며, 전기적 특성이 저하되지 않도록 하기 위해 일면의 볼록부와 타면의 볼록부가 서로 다른 곡률을 갖도록 배치할 수 있다.The other surface of the first penetrating electrode 530 may have a different shape from the one surface. That is, one surface on which the concave portion of the first through electrode 530 is disposed and the other surface overlapping along the horizontal direction may not have a concave surface or may have different curvatures. Referring to FIG. 9, the curvature of one surface of the first through electrode 530 and the curvature of the other surface overlapping the concave surface in the horizontal direction are shown to be different from each other. Through this, the bonding force between the insulating member 540 and the first through electrode 530 can be improved, heat dissipation characteristics can be improved, and mechanical reliability of the semiconductor package substrate can be improved by controlling stress. Likewise, the convex portion of one surface of the first through electrode 530 may have a different curvature from the convex portion of the other surface that overlaps the convex portion in the horizontal direction. Since the convex portion on the other side may be arranged in a structure that surrounds the glass fiber differently from the convex portion on one side, its curvature may be different from the convex portion on one side. Specifically, when the first through electrode 530 surrounds a glass fiber, the horizontal thickness of the first through electrode 530 must be 10 μm or more to prevent the problem of deterioration of electrical characteristics. Therefore, the convex portion on the other side surrounds the glass fiber, and in order to prevent electrical properties from being deteriorated, the convex portion on one side and the convex portion on the other side can be arranged to have different curvatures.
도 10 내지 14는 실시 예에 따른 반도체 패키지 기판의 제조 방법의 일부를 공정 순으로 나타낸 도면이다. 이하에서는 제1 절연층(511)에 제1 관통 홀(TH1)을 형성하는 공정에 대해 설명한다.10 to 14 are diagrams showing part of a method for manufacturing a semiconductor package substrate according to an embodiment, in process order. Hereinafter, a process for forming the first through hole TH1 in the first insulating layer 511 will be described.
도 10을 참조하면, 실시 예는 제1 절연층(511)을 준비한다. 제1 절연층(511)은 CCL일 수 있다. 따라서, 제1 절연층(511)의 양면에는 각각 동박층에 배치될 수 있다. 동박층은 제1 회로 패턴층(521)의 제1 금속층(521-1)과, 제2 회로 패턴층(522)의 제1 금속층(522-1)을 포함할 수 있다.Referring to FIG. 10, in the embodiment, a first insulating layer 511 is prepared. The first insulating layer 511 may be CCL. Accordingly, copper foil layers may be disposed on both sides of the first insulating layer 511, respectively. The copper foil layer may include a first metal layer 521-1 of the first circuit pattern layer 521 and a first metal layer 522-1 of the second circuit pattern layer 522.
이후, 실시 예는 제1 절연층(511)에 제1 관통 홀(TH1)을 형성하는 공정을 진행할 수 있다.Thereafter, the embodiment may proceed with a process of forming the first through hole TH1 in the first insulating layer 511.
제1 관통 홀(TH1)은 복수의 좌표 코드를 이용한 복수의 레이저 공정에 의해 형성될 수 있다.The first through hole TH1 may be formed through multiple laser processes using multiple coordinate codes.
이때, 제1 절연층(511)은 250㎛ 이상의 수직 방향의 두께를 가진다. 따라서, 제1 절연층(511)의 일측에서만 제1 절연층(511)을 관통하는 제1 관통 홀(TH1)을 형성하는 것이 어려울 수 있다. 따라서, 실시 예는 제1 절연층(511)의 상측에서 1차적으로 제1 관통 홀(TH1)의 일부를 형성하는 공정을 진행할 수 있다.At this time, the first insulating layer 511 has a vertical thickness of 250 μm or more. Accordingly, it may be difficult to form the first through hole TH1 penetrating the first insulating layer 511 only on one side of the first insulating layer 511 . Accordingly, the embodiment may proceed with a process of initially forming a portion of the first through hole TH1 on the upper side of the first insulating layer 511.
이를 위해, 도 11을 참조하면, 실시 예는 제1 좌표 코드(T-code A)를 이용하여 제1 절연층(511)의 상측에서 제1 관통 홀(TH1)의 일부를 형성하는 공정을 진행할 수 있다. 제1 좌표 코드(T-code A)에는 제1 관통 홀(TH1)이 형성될 위치에 대응하는 위치 정보(TCI)가 포함될 수 있다. 그리고, 실시 예는 제1 좌표 코드(T-code A)를 이용하여 제1 절연층(511)의 상측에서 레이저를 조사하여 제1 관통 홀(TH1)의 일부를 형성할 수 있다. 이때, 제1 좌표 코드(T-code A)를 이용하여 제1 관통 홀(TH1)의 일부를 형성하는 공정에서는 제1 사이즈의 개구를 가진 제1 마스크를 이용할 수 있다. 또한, 실시 예는 제1 마스크의 개구를 통해 제1 레이저 에너지 세기의 레이저를 조사하여, 제1 절연층(511)의 상측에 제1 관통 홀(TH1)의 일부인 제1 부분(HP1)을 형성하는 공정을 진행할 수 있다.To this end, referring to FIG. 11, the embodiment proceeds with a process of forming a portion of the first through hole TH1 on the upper side of the first insulating layer 511 using the first coordinate code (T-code A). You can. The first coordinate code (T-code A) may include location information (TCI) corresponding to the location where the first through hole (TH1) will be formed. And, in the embodiment, a portion of the first through hole TH1 may be formed by irradiating a laser from the upper side of the first insulating layer 511 using the first coordinate code (T-code A). At this time, in the process of forming part of the first through hole TH1 using the first coordinate code (T-code A), a first mask having an opening of the first size may be used. In addition, in the embodiment, a laser of the first laser energy intensity is irradiated through the opening of the first mask to form the first portion HP1, which is part of the first through hole TH1, on the upper side of the first insulating layer 511. The process can proceed.
이후, 도 12를 참조하면, 실시 예는 제2 좌표 코드(T-code B)를 이용하여 제1 절연층(511)의 상측에 제1 부분(BP1)과 연결되는 제2 부분(HP2)을 형성하는 공정을 진행할 수 있다. 이때, 제2 좌표 코드(T-code B)에는 제1 좌표 코드(T-code A)에 대응하는 위치 정보(TCI)가 포함될 수 있다.Next, referring to FIG. 12, in the embodiment, a second part (HP2) connected to the first part (BP1) is formed on the upper side of the first insulating layer 511 using a second coordinate code (T-code B). The forming process can proceed. At this time, the second coordinate code (T-code B) may include location information (TCI) corresponding to the first coordinate code (T-code A).
그리고, 실시 예는 제2 좌표 코드(T-code B)를 이용하는 경우, 제1 좌표 코드(T-code A)를 이용할 때 사용한 레이저 공정 조건과는 다른 조건을 적용하여 제1 관통 홀(TH1)의 제1 부분(BP1)과 연결되는 제1 관통 홀(TH1)의 제2 부분(HP2)을 형성한다. In addition, in the embodiment, when using the second coordinate code (T-code B), conditions different from the laser processing conditions used when using the first coordinate code (T-code A) are applied to form the first through hole (TH1). It forms a second part (HP2) of the first through hole (TH1) connected to the first part (BP1) of .
이때, 제2 좌표 코드(T-code B)를 이용하여 제1 관통 홀(TH1)의 제1 부분(BP1)을 형성하는 공정에서는 제1 사이즈보다 작은 제2 사이즈의 개구를 가진 제2 마스크를 이용할 수 있다. 또한, 실시 예는 제2 마스크의 개구를 통해 제1 에너지 세기보다 큰 제2 에너지 세기의 레이저를 조사하여, 제1 절연층(511)의 상측에 제1 관통 홀(TH1)의 제2 부분(HP2)을 형성할 수 있다.At this time, in the process of forming the first portion (BP1) of the first through hole (TH1) using the second coordinate code (T-code B), a second mask having an opening of a second size smaller than the first size is used. Available. In addition, in the embodiment, a laser of a second energy intensity greater than the first energy intensity is irradiated through the opening of the second mask, and the second portion of the first through hole TH1 is on the upper side of the first insulating layer 511 ( HP2) can be formed.
따라서, 실시 예는 제1 관통 홀(TH1)의 제1 부분(HP1)과 제2 부분(HP2) 각각의 수평 방향으로의 폭이 실질적으로 동일할 수 있다. 다만, 제1 절연층(511)에는 강화 섬유(511b)가 포함된다. 따라서, 제1 관통 홀(TH1)의 제1 부분(HP1)과 제2 부분(HP2)에서, 강화 섬유(511b)와 수평 방향으로 중첩된 영역에 돌출부가 구비될 수 있다.Accordingly, in the embodiment, the horizontal widths of the first portion HP1 and the second portion HP2 of the first through hole TH1 may be substantially the same. However, the first insulating layer 511 includes reinforcing fibers 511b. Accordingly, in the first portion HP1 and the second portion HP2 of the first through hole TH1, protrusions may be provided in areas that overlap the reinforcing fibers 511b in the horizontal direction.
또한, 도 13을 참조하면, 실시 예는 제1 좌표 코드(T-code A)를 이용하여 제1 절연층(511)의 하측에서 제1 관통 홀(TH1)의 나머지 일부를 형성하는 공정을 진행할 수 있다. 구체적으로, 실시 예는 제1 좌표 코드(T-code A)에 따른 제1 레이저 공정 조건을 적용하여, 제1 관통 홀(TH1)의 제1 부분(HP1) 및 제2 부분(HP2)과 수직 방향으로 정렬된 제1 관통 홀(TH1)의 제3 부분(HP3)을 형성할 수 있다.Additionally, referring to FIG. 13, the embodiment proceeds with a process of forming the remaining portion of the first through hole TH1 on the lower side of the first insulating layer 511 using the first coordinate code (T-code A). You can. Specifically, the embodiment applies the first laser process conditions according to the first coordinate code (T-code A), and perpendicular to the first part (HP1) and the second part (HP2) of the first through hole (TH1). A third portion (HP3) of the first through hole (TH1) aligned in the direction may be formed.
다음으로, 도 14를 참조하면, 실시 예는 제2 좌표 코드(T-code B)를 이용하여 제1 관통 홀(TH1)의 제3 부분(HP3)과 연결되는 제4 부분(HP4)을 형성하는 공정을 진행할 수 있다. 제4 부분(HP4)은 제2 부분(HP2)과 연결되며, 이에 따라 최종적인 제1 관통 홀(TH1)이 형성될 수 있다.Next, referring to FIG. 14, the embodiment forms the fourth part (HP4) connected to the third part (HP3) of the first through hole (TH1) using the second coordinate code (T-code B). The process can proceed. The fourth part HP4 is connected to the second part HP2, and thus the final first through hole TH1 can be formed.
한편, 상술한 발명의 특징을 갖는 반도체 패키지 기판이 스마트폰, 서버용 컴퓨터, TV 등의 IT 장치나 가전제품에 이용되는 경우, 신호 전송 또는 전력 공급 등의 기능을 안정적으로 할 수 있다. 예를 들어, 본 발명의 특징을 갖는 반도체 패키지 기판이 반도체 패키지 기능을 수행하는 경우, 반도체 칩을 외부의 습기나 오염 물질로부터 안전하게 보호하는 기능을 할 수 있고, 누설전류 혹은 단자 간의 전기적인 단락 문제나 혹은 반도체 칩에 공급하는 단자의 전기적인 개방의 문제를 해결할 수 있다. 또한, 신호 전송의 기능을 담당하는 경우 노이즈 문제를 해결할 수 있다. 이를 통해, 상술한 발명의 특징을 갖는 반도체 패키지 기판은 IT 장치나 가전제품의 안정적인 기능을 유지할 수 있도록 함으로써, 전체 제품과 본 발명이 적용된 반도체 패키지 기판은 서로 기능적 일체성 또는 기술적 연동성을 이룰 수 있다.Meanwhile, when the semiconductor package substrate having the characteristics of the above-described invention is used in IT devices or home appliances such as smartphones, server computers, and TVs, functions such as signal transmission or power supply can be stably performed. For example, when a semiconductor package substrate having the characteristics of the present invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can prevent problems with leakage current or electrical short circuits between terminals. It can solve the problem of electrical opening of the terminal supplying the semiconductor chip. Additionally, if it is responsible for the function of signal transmission, the noise problem can be solved. Through this, the semiconductor package substrate having the characteristics of the above-described invention can maintain the stable function of IT devices or home appliances, so that the entire product and the semiconductor package substrate to which the present invention is applied can achieve functional unity or technical interoperability with each other. .
상술한 발명의 특징을 갖는 반도체 패키지 기판이 차량 등의 운송 장치에 이용되는 경우, 운송 장치로 전송되는 신호의 왜곡 문제를 해결할 수 있고, 또는 운송 장치를 제어하는 반도체 칩을 외부로부터 안전하게 보호하고, 누설전류 혹은 단자 간의 전기적인 단락 문제나 혹은 반도체 칩에 공급하는 단자의 전기적인 개방의 문제를 해결하여 운송 장치의 안정성을 더 개선할 수 있다. 따라서, 운송 장치와 본 발명이 적용된 반도체 패키지 기판은 서로 기능적 일체성 또는 기술적 연동성을 이룰 수 있다. 나아가, 상술한 발명의 특징을 갖는 반도체 패키지 기판이 차량 등의 운송 장치에 이용되는 경우, 차량에서 요구되는 대전류의 신호를 고속으로 전송할 수 있고, 이에 따라 운송장치의 안전성을 향상시킬 수 있다. 나아가, 운송 장치의 다양한 주행 환경에서 발생하는 돌발 상황에서도 반도체 패키지 기판 및 이를 포함하는 반도체 패키지의 정상적 동작이 가능하도록 하고, 이를 통해 운전자를 안전하게 보호할 수 있다.When the semiconductor package substrate having the characteristics of the above-described invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of the signal transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside, The stability of the transportation device can be further improved by solving the problem of leakage current, electrical short-circuiting between terminals, or electrical opening of the terminal supplying the semiconductor chip. Accordingly, the transportation device and the semiconductor package substrate to which the present invention is applied can achieve functional unity or technical interoperability with each other. Furthermore, when the semiconductor package substrate having the characteristics of the above-described invention is used in a transportation device such as a vehicle, a high-current signal required by the vehicle can be transmitted at high speed, thereby improving the safety of the transportation device. Furthermore, it enables normal operation of the semiconductor package substrate and the semiconductor package including it even in unexpected situations that occur in various driving environments of transportation devices, thereby protecting drivers safely.
이상에서 실시 예들에 설명된 특징, 구조, 효과 등은 적어도 하나의 실시 예에 포함되며, 반드시 하나의 실시 예에만 한정되는 것은 아니다. 나아가, 각 실시 예에서 예시된 특징, 구조, 효과 등은 실시 예들이 속하는 분야의 통상의 지식을 가지는 자에 의해 다른 실시 예들에 대해서도 조합 또는 변형되어 실시 가능하다. 따라서 이러한 조합과 변형에 관계된 내용은 실시 예의 범위에 포함되는 것으로 해석되어야 할 것이다.The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.
이상에서 실시 예를 중심으로 설명하였으나 이는 단지 예시일 뿐 실시 예를 한정하는 것이 아니며, 실시 예가 속하는 분야의 통상의 지식을 가진 자라면 본 실시예의 본질적인 특성을 벗어나지 않는 범위에서 이상에 예시되지 않은 여러 가지의 변형과 응용이 가능함을 알 수 있을 것이다. 예를 들어, 실시 예에 구체적으로 나타난 각 구성 요소는 변형하여 실시할 수 있는 것이다. 그리고 이러한 변형과 응용에 관계된 차이점들은 첨부된 청구 범위에서 설정하는 실시 예의 범위에 포함되는 것으로 해석되어야 할 것이다.Although the above description focuses on the embodiment, this is only an example and does not limit the embodiment, and those skilled in the art will understand that there are various options not exemplified above without departing from the essential characteristics of the present embodiment. You will see that variations and applications of branches are possible. For example, each component specifically shown in the examples can be modified and implemented. And these variations and differences related to application should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

Claims (10)

  1. 상면 및 하면을 구비한 절연층; 및an insulating layer having an upper and lower surface; and
    상기 절연층의 상기 상면 및 상기 하면을 관통하는 관통 전극을 포함하고,It includes a penetrating electrode penetrating the upper and lower surfaces of the insulating layer,
    상기 관통 전극의 측면은 수직 방향을 따라 교번적으로 구비된 오목부 및 볼록부를 포함하는, 회로 기판.A circuit board wherein a side surface of the through electrode includes concave portions and convex portions provided alternately along a vertical direction.
  2. 상면 및 하면을 구비한 절연층; 및an insulating layer having an upper and lower surface; and
    상기 절연층의 상기 상면 및 하면을 관통하는 관통 홀을 포함하고,It includes a through hole penetrating the upper and lower surfaces of the insulating layer,
    상기 관통 홀의 측벽은 수직 방향을 따라 교번적으로 구비된 오목부 및 볼록부를 포함하는, 회로 기판.A circuit board wherein the sidewall of the through hole includes concave portions and convex portions provided alternately along a vertical direction.
  3. 제2항에 있어서,According to paragraph 2,
    상기 관통 홀 내에 배치된 관통 전극을 더 포함하고,Further comprising a through electrode disposed in the through hole,
    상기 관통 전극의 측면은 상기 관통 홀의 측벽의 오목부에 대응하는 오목부 및 상기 관통 홀의 측벽의 볼록부에 대응하는 볼록부를 구비한, 회로 기판.A circuit board, wherein a side surface of the through electrode has a concave portion corresponding to a concave portion of a side wall of the through hole and a convex portion corresponding to a convex portion of a side wall of the through hole.
  4. 제1항 또는 제3항에 있어서,According to claim 1 or 3,
    상기 절연층을 관통하는 절연 부재를 더 포함하고,Further comprising an insulating member penetrating the insulating layer,
    상기 관통 전극은 상기 절연 부재의 외측을 감싸며 구비된, 회로 기판.The through electrode is provided to surround the outside of the insulating member.
  5. 제1항 또는 제3항에 있어서,According to claim 1 or 3,
    상기 관통 전극의 오목부 및 볼록부는 상기 수직 방향을 따라 교번적으로 각각 복수 개 구비된 회로 기판.A circuit board wherein a plurality of concave portions and convex portions of the through electrode are provided alternately along the vertical direction.
  6. 제4항에 있어서,According to clause 4,
    상기 절연 부재는 수평 방향으로의 제1폭을 가지는 제1부와, 상기 수평 방향으로 상기 제1폭과 다른 제2폭을 가진 제2부를 포함하는, 회로 기판.The circuit board, wherein the insulating member includes a first portion having a first width in the horizontal direction, and a second portion having a second width different from the first width in the horizontal direction.
  7. 제5항에 있어서,According to clause 5,
    상기 제1폭은 상기 제2폭보다 크고,The first width is larger than the second width,
    상기 제1부는 상기 관통 전극의 상기 오목부와 수평 방향으로 중첩되고,The first portion overlaps the concave portion of the penetrating electrode in a horizontal direction,
    상기 제2부는 상기 관통 전극의 상기 볼록부와 수평 방향으로 중첩된, 회로 기판.A circuit board wherein the second portion overlaps the convex portion of the through electrode in a horizontal direction.
  8. 제1항 또는 제3항에 있어서,According to claim 1 or 3,
    상기 절연층은 레진 및 상기 레진 내에 배치된 강화 섬유를 포함하고,The insulating layer includes a resin and reinforcing fibers disposed within the resin,
    상기 강화 섬유는 제1 수평 방향으로 배치된 제1 섬유 및 상기 제1 수평 방향과 수직한 제2 수평 방향으로 배치된 제2 섬유를 포함하는, 회로 기판.The reinforcing fiber includes a first fiber disposed in a first horizontal direction and a second fiber disposed in a second horizontal direction perpendicular to the first horizontal direction.
  9. 제8항에 있어서,According to clause 8,
    상기 강화 섬유는 수직 방향을 따라 서로 이격되고 상기 제1 및 제2 섬유 각각을 구비한 복수 개의 그룹을 포함하는, 회로 기판.The circuit board, wherein the reinforcing fibers are spaced apart from each other along a vertical direction and include a plurality of groups each having the first and second fibers.
  10. 제8항에 있어서,According to clause 8,
    상기 관통 전극의 상기 오목부는 상기 강화 섬유와 수평 방향으로 중첩된, 회로 기판.A circuit board, wherein the concave portion of the penetrating electrode overlaps the reinforcing fiber in a horizontal direction.
PCT/KR2023/011868 2022-08-10 2023-08-10 Semiconductor package substrate and semiconductor package including same WO2024035176A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093247A (en) * 1996-09-18 1998-04-10 Kyocera Corp Multilayer wiring board
JP2009054689A (en) * 2007-08-24 2009-03-12 Kyocera Corp Wiring board, mounting board and mounting structure, and manufacturing method of wiring board
KR20160123525A (en) * 2015-04-16 2016-10-26 엘지이노텍 주식회사 Printed circuit board
CN208016126U (en) * 2015-07-06 2018-10-26 株式会社村田制作所 Substrate and the electronic equipment for having the substrate
KR20210143997A (en) * 2020-05-21 2021-11-30 엘지이노텍 주식회사 Printed circuit board and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093247A (en) * 1996-09-18 1998-04-10 Kyocera Corp Multilayer wiring board
JP2009054689A (en) * 2007-08-24 2009-03-12 Kyocera Corp Wiring board, mounting board and mounting structure, and manufacturing method of wiring board
KR20160123525A (en) * 2015-04-16 2016-10-26 엘지이노텍 주식회사 Printed circuit board
CN208016126U (en) * 2015-07-06 2018-10-26 株式会社村田制作所 Substrate and the electronic equipment for having the substrate
KR20210143997A (en) * 2020-05-21 2021-11-30 엘지이노텍 주식회사 Printed circuit board and method for manufacturing the same

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